system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13addTwoNumbersiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13addTwoNumbersiiPi
.globl _Z13addTwoNumbersiiPi
.p2align 8
.type _Z13addTwoNumbersiiPi,@function
_Z13addTwoNumbersiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13addTwoNumbersiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13addTwoNumbersiiPi, .Lfunc_end0-_Z13addTwoNumbersiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13addTwoNumbersiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z13addTwoNumbersiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00012ec2_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13addTwoNumbersiiPiiiPi
.type _Z35__device_stub__Z13addTwoNumbersiiPiiiPi, @function
_Z35__device_stub__Z13addTwoNumbersiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13addTwoNumbersiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z13addTwoNumbersiiPiiiPi, .-_Z35__device_stub__Z13addTwoNumbersiiPiiiPi
.globl _Z13addTwoNumbersiiPi
.type _Z13addTwoNumbersiiPi, @function
_Z13addTwoNumbersiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13addTwoNumbersiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13addTwoNumbersiiPi, .-_Z13addTwoNumbersiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " 2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $1, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z35__device_stub__Z13addTwoNumbersiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13addTwoNumbersiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13addTwoNumbersiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z28__device_stub__addTwoNumbersiiPi # -- Begin function _Z28__device_stub__addTwoNumbersiiPi
.p2align 4, 0x90
.type _Z28__device_stub__addTwoNumbersiiPi,@function
_Z28__device_stub__addTwoNumbersiiPi: # @_Z28__device_stub__addTwoNumbersiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13addTwoNumbersiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__addTwoNumbersiiPi, .Lfunc_end0-_Z28__device_stub__addTwoNumbersiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13addTwoNumbersiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
movl $1, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13addTwoNumbersiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13addTwoNumbersiiPi,@object # @_Z13addTwoNumbersiiPi
.section .rodata,"a",@progbits
.globl _Z13addTwoNumbersiiPi
.p2align 3, 0x0
_Z13addTwoNumbersiiPi:
.quad _Z28__device_stub__addTwoNumbersiiPi
.size _Z13addTwoNumbersiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " 2 + 7 = %d\n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13addTwoNumbersiiPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__addTwoNumbersiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13addTwoNumbersiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void polynomial_expansion (float* poly,int degree,int n,float* array)
{
int idx=blockIdx.x*blockDim.x+threadIdx.x;
if(idx<n)
{
float val=0.0;
float exp=1.0;
for(int x=0;x<=degree;++x)
{
val+=exp*poly[x];
exp*=array[idx];
}
array[idx]=val;
}
} | code for sm_80
Function : _Z20polynomial_expansionPfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f03270 */
/*0070*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe400078e0208 */
/*00a0*/ @!P0 BRA 0xa30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, c[0x0][0x168] ; /* 0x00005a0000097a02 */
/* 0x000fe20000000f00 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*00d0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*00f0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0100*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0120*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fca00078ec0ff */
/*0130*/ @!P0 BRA 0x8d0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R10, -R9, c[0x0][0x168], RZ ; /* 0x00005a00090a7a10 */
/* 0x001fe20007ffe1ff */
/*0150*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0160*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*0170*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe40003f04270 */
/*0190*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fd20000000f00 */
/*01b0*/ @!P0 BRA 0x790 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x570 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R26, [R4.64+0x4] ; /* 0x00000404041a7981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000128000c1e1900 */
/*0250*/ LDG.E R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R21, [R4.64+0x14] ; /* 0x0000140404157981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R20, [R4.64+0x18] ; /* 0x0000180404147981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R19, [R4.64+0x1c] ; /* 0x00001c0404137981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R15, [R4.64+0x2c] ; /* 0x00002c04040f7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000128000c1e1900 */
/*02e0*/ LDG.E R13, [R4.64+0x34] ; /* 0x00003404040d7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000122000c1e1900 */
/*0300*/ FMUL R27, R0, R6 ; /* 0x00000006001b7220 */
/* 0x020fc40000400000 */
/*0310*/ FFMA R25, R25, R6, R7 ; /* 0x0000000619197223 */
/* 0x004fe40000000007 */
/*0320*/ LDG.E R7, [R4.64+0x3c] ; /* 0x00003c0404077981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0340*/ FFMA R25, R26, R27.reuse, R25 ; /* 0x0000001b1a197223 */
/* 0x088fe20000000019 */
/*0350*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*0370*/ ISETP.GT.AND P1, PT, R10, 0xb, PT ; /* 0x0000000b0a00780c */
/* 0x000fc60003f24270 */
/*0380*/ FFMA R24, R27, R24, R25 ; /* 0x000000181b187223 */
/* 0x010fe40000000019 */
/*0390*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*03a0*/ IADD3 R4, P2, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fc60007f5e0ff */
/*03b0*/ FFMA R23, R27, R23, R24 ; /* 0x000000171b177223 */
/* 0x000fe20000000018 */
/*03c0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*03d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*03e0*/ FFMA R22, R27, R22, R23 ; /* 0x000000161b167223 */
/* 0x000fe40000000017 */
/*03f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0400*/ FFMA R21, R21, R27.reuse, R22 ; /* 0x0000001b15157223 */
/* 0x080fe40000000016 */
/*0410*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0420*/ FFMA R20, R27, R20, R21 ; /* 0x000000141b147223 */
/* 0x000fe40000000015 */
/*0430*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0440*/ FFMA R19, R27, R19, R20 ; /* 0x000000131b137223 */
/* 0x000fe40000000014 */
/*0450*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0460*/ FFMA R18, R27, R18, R19 ; /* 0x000000121b127223 */
/* 0x000fe40000000013 */
/*0470*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0480*/ FFMA R17, R17, R27.reuse, R18 ; /* 0x0000001b11117223 */
/* 0x080fe40000000012 */
/*0490*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04a0*/ FFMA R16, R27, R16, R17 ; /* 0x000000101b107223 */
/* 0x000fe40000000011 */
/*04b0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04c0*/ FFMA R15, R27, R15, R16 ; /* 0x0000000f1b0f7223 */
/* 0x000fe40000000010 */
/*04d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04e0*/ FFMA R14, R27, R14, R15 ; /* 0x0000000e1b0e7223 */
/* 0x000fe4000000000f */
/*04f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0500*/ FFMA R13, R13, R27.reuse, R14 ; /* 0x0000001b0d0d7223 */
/* 0x080fe4000000000e */
/*0510*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0520*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x000fe4000000000d */
/*0530*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0540*/ FMUL R6, R0, R27 ; /* 0x0000001b00067220 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R7, R27, R7, R12 ; /* 0x000000071b077223 */
/* 0x004fe2000000000c */
/*0560*/ @P1 BRA 0x210 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*0570*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fc80007ffe0ff */
/*0580*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x770 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05a0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000128000c1e1900 */
/*05d0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000128000c1e1900 */
/*05f0*/ LDG.E R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000128000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000122000c1e1900 */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0630*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0640*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fc80007f3e0ff */
/*0660*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0670*/ FFMA R14, R6, R14, R7 ; /* 0x0000000e060e7223 */
/* 0x004fe40000000007 */
/*0680*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0690*/ FFMA R14, R15, R7.reuse, R14 ; /* 0x000000070f0e7223 */
/* 0x088fe4000000000e */
/*06a0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06b0*/ FFMA R14, R7, R16, R14 ; /* 0x00000010070e7223 */
/* 0x010fe4000000000e */
/*06c0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06d0*/ FFMA R14, R7, R17, R14 ; /* 0x00000011070e7223 */
/* 0x000fe4000000000e */
/*06e0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06f0*/ FFMA R14, R7, R18, R14 ; /* 0x00000012070e7223 */
/* 0x000fe4000000000e */
/*0700*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0710*/ FFMA R19, R19, R7.reuse, R14 ; /* 0x0000000713137223 */
/* 0x080fe4000000000e */
/*0720*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0730*/ FFMA R12, R7, R12, R19 ; /* 0x0000000c070c7223 */
/* 0x000fe40000000013 */
/*0740*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R7, R15, R13, R12 ; /* 0x0000000d0f077223 */
/* 0x000fe4000000000c */
/*0760*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe40000400000 */
/*0770*/ ISETP.NE.OR P0, PT, R10, -0x1, P0 ; /* 0xffffffff0a00780c */
/* 0x000fda0000705670 */
/*0780*/ @!P0 BRA 0x8d0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000122000c1e1900 */
/*07d0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*07e0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe20003f05270 */
/*0800*/ FFMA R12, R12, R6.reuse, R7 ; /* 0x000000060c0c7223 */
/* 0x084fe40000000007 */
/*0810*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0820*/ FFMA R12, R13, R7.reuse, R12 ; /* 0x000000070d0c7223 */
/* 0x088fe2000000000c */
/*0830*/ IADD3 R13, P1, R4, 0x10, RZ ; /* 0x00000010040d7810 */
/* 0x000fe20007f3e0ff */
/*0840*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc60000400000 */
/*0850*/ IADD3.X R14, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe20000ffe4ff */
/*0860*/ FFMA R12, R15, R7, R12 ; /* 0x000000070f0c7223 */
/* 0x010fe2000000000c */
/*0870*/ MOV R4, R13 ; /* 0x0000000d00047202 */
/* 0x001fe20000000f00 */
/*0880*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fe20000400000 */
/*0890*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fc60000000f00 */
/*08a0*/ FFMA R7, R17, R15.reuse, R12 ; /* 0x0000000f11077223 */
/* 0x080fe4000000000c */
/*08b0*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe20000400000 */
/*08c0*/ @P0 BRA 0x790 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fda0003f05270 */
/*08e0*/ @!P0 BRA 0xa40 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.WIDE R4, R11, R8, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fca00078e0208 */
/*0900*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007f3e0ff */
/*0930*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3.X R12, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0c7210 */
/* 0x000fe20000ffe4ff */
/*0950*/ FFMA R7, R8, R6, R7 ; /* 0x0000000608077223 */
/* 0x004fd40000000007 */
/*0960*/ @!P0 BRA 0xa40 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FMUL R11, R0, R6 ; /* 0x00000006000b7220 */
/* 0x020fe40000400000 */
/*0980*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0990*/ MOV R5, R12 ; /* 0x0000000c00057202 */
/* 0x000fca0000000f00 */
/*09a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ FFMA R7, R4, R11.reuse, R7 ; /* 0x0000000b04077223 */
/* 0x084fe40000000007 */
/*0a00*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x000fd00000400000 */
/*0a10*/ @P0 BRA 0x980 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BRA 0xa40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a30*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fca0000000f00 */
/*0a40*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void polynomial_expansion (float* poly,int degree,int n,float* array)
{
int idx=blockIdx.x*blockDim.x+threadIdx.x;
if(idx<n)
{
float val=0.0;
float exp=1.0;
for(int x=0;x<=degree;++x)
{
val+=exp*poly[x];
exp*=array[idx];
}
array[idx]=val;
}
} | .file "tmpxft_00065c5d_00000000-6_polynomial_expansion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.type _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, @function
_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, .-_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.globl _Z20polynomial_expansionPfiiS_
.type _Z20polynomial_expansionPfiiS_, @function
_Z20polynomial_expansionPfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20polynomial_expansionPfiiS_, .-_Z20polynomial_expansionPfiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20polynomial_expansionPfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void polynomial_expansion (float* poly,int degree,int n,float* array)
{
int idx=blockIdx.x*blockDim.x+threadIdx.x;
if(idx<n)
{
float val=0.0;
float exp=1.0;
for(int x=0;x<=degree;++x)
{
val+=exp*poly[x];
exp*=array[idx];
}
array[idx]=val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void polynomial_expansion (float* poly,int degree,int n,float* array)
{
int idx=blockIdx.x*blockDim.x+threadIdx.x;
if(idx<n)
{
float val=0.0;
float exp=1.0;
for(int x=0;x<=degree;++x)
{
val+=exp*poly[x];
exp*=array[idx];
}
array[idx]=val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void polynomial_expansion (float* poly,int degree,int n,float* array)
{
int idx=blockIdx.x*blockDim.x+threadIdx.x;
if(idx<n)
{
float val=0.0;
float exp=1.0;
for(int x=0;x<=degree;++x)
{
val+=exp*poly[x];
exp*=array[idx];
}
array[idx]=val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20polynomial_expansionPfiiS_
.globl _Z20polynomial_expansionPfiiS_
.p2align 8
.type _Z20polynomial_expansionPfiiS_,@function
_Z20polynomial_expansionPfiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_add_i32 s4, s4, 1
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 1.0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20polynomial_expansionPfiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20polynomial_expansionPfiiS_, .Lfunc_end0-_Z20polynomial_expansionPfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20polynomial_expansionPfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20polynomial_expansionPfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void polynomial_expansion (float* poly,int degree,int n,float* array)
{
int idx=blockIdx.x*blockDim.x+threadIdx.x;
if(idx<n)
{
float val=0.0;
float exp=1.0;
for(int x=0;x<=degree;++x)
{
val+=exp*poly[x];
exp*=array[idx];
}
array[idx]=val;
}
} | .text
.file "polynomial_expansion.hip"
.globl _Z35__device_stub__polynomial_expansionPfiiS_ # -- Begin function _Z35__device_stub__polynomial_expansionPfiiS_
.p2align 4, 0x90
.type _Z35__device_stub__polynomial_expansionPfiiS_,@function
_Z35__device_stub__polynomial_expansionPfiiS_: # @_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20polynomial_expansionPfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__polynomial_expansionPfiiS_, .Lfunc_end0-_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20polynomial_expansionPfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20polynomial_expansionPfiiS_,@object # @_Z20polynomial_expansionPfiiS_
.section .rodata,"a",@progbits
.globl _Z20polynomial_expansionPfiiS_
.p2align 3, 0x0
_Z20polynomial_expansionPfiiS_:
.quad _Z35__device_stub__polynomial_expansionPfiiS_
.size _Z20polynomial_expansionPfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20polynomial_expansionPfiiS_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__polynomial_expansionPfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20polynomial_expansionPfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20polynomial_expansionPfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f03270 */
/*0070*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe400078e0208 */
/*00a0*/ @!P0 BRA 0xa30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, c[0x0][0x168] ; /* 0x00005a0000097a02 */
/* 0x000fe20000000f00 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*00d0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*00f0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0100*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0120*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fca00078ec0ff */
/*0130*/ @!P0 BRA 0x8d0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R10, -R9, c[0x0][0x168], RZ ; /* 0x00005a00090a7a10 */
/* 0x001fe20007ffe1ff */
/*0150*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0160*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*0170*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe40003f04270 */
/*0190*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fd20000000f00 */
/*01b0*/ @!P0 BRA 0x790 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x570 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R26, [R4.64+0x4] ; /* 0x00000404041a7981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000128000c1e1900 */
/*0250*/ LDG.E R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R21, [R4.64+0x14] ; /* 0x0000140404157981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R20, [R4.64+0x18] ; /* 0x0000180404147981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R19, [R4.64+0x1c] ; /* 0x00001c0404137981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R15, [R4.64+0x2c] ; /* 0x00002c04040f7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000128000c1e1900 */
/*02e0*/ LDG.E R13, [R4.64+0x34] ; /* 0x00003404040d7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000122000c1e1900 */
/*0300*/ FMUL R27, R0, R6 ; /* 0x00000006001b7220 */
/* 0x020fc40000400000 */
/*0310*/ FFMA R25, R25, R6, R7 ; /* 0x0000000619197223 */
/* 0x004fe40000000007 */
/*0320*/ LDG.E R7, [R4.64+0x3c] ; /* 0x00003c0404077981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0340*/ FFMA R25, R26, R27.reuse, R25 ; /* 0x0000001b1a197223 */
/* 0x088fe20000000019 */
/*0350*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*0370*/ ISETP.GT.AND P1, PT, R10, 0xb, PT ; /* 0x0000000b0a00780c */
/* 0x000fc60003f24270 */
/*0380*/ FFMA R24, R27, R24, R25 ; /* 0x000000181b187223 */
/* 0x010fe40000000019 */
/*0390*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*03a0*/ IADD3 R4, P2, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fc60007f5e0ff */
/*03b0*/ FFMA R23, R27, R23, R24 ; /* 0x000000171b177223 */
/* 0x000fe20000000018 */
/*03c0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*03d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*03e0*/ FFMA R22, R27, R22, R23 ; /* 0x000000161b167223 */
/* 0x000fe40000000017 */
/*03f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0400*/ FFMA R21, R21, R27.reuse, R22 ; /* 0x0000001b15157223 */
/* 0x080fe40000000016 */
/*0410*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0420*/ FFMA R20, R27, R20, R21 ; /* 0x000000141b147223 */
/* 0x000fe40000000015 */
/*0430*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0440*/ FFMA R19, R27, R19, R20 ; /* 0x000000131b137223 */
/* 0x000fe40000000014 */
/*0450*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0460*/ FFMA R18, R27, R18, R19 ; /* 0x000000121b127223 */
/* 0x000fe40000000013 */
/*0470*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0480*/ FFMA R17, R17, R27.reuse, R18 ; /* 0x0000001b11117223 */
/* 0x080fe40000000012 */
/*0490*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04a0*/ FFMA R16, R27, R16, R17 ; /* 0x000000101b107223 */
/* 0x000fe40000000011 */
/*04b0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04c0*/ FFMA R15, R27, R15, R16 ; /* 0x0000000f1b0f7223 */
/* 0x000fe40000000010 */
/*04d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04e0*/ FFMA R14, R27, R14, R15 ; /* 0x0000000e1b0e7223 */
/* 0x000fe4000000000f */
/*04f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0500*/ FFMA R13, R13, R27.reuse, R14 ; /* 0x0000001b0d0d7223 */
/* 0x080fe4000000000e */
/*0510*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0520*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x000fe4000000000d */
/*0530*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0540*/ FMUL R6, R0, R27 ; /* 0x0000001b00067220 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R7, R27, R7, R12 ; /* 0x000000071b077223 */
/* 0x004fe2000000000c */
/*0560*/ @P1 BRA 0x210 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*0570*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fc80007ffe0ff */
/*0580*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x770 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05a0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000128000c1e1900 */
/*05d0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000128000c1e1900 */
/*05f0*/ LDG.E R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000128000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000122000c1e1900 */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0630*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0640*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fc80007f3e0ff */
/*0660*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0670*/ FFMA R14, R6, R14, R7 ; /* 0x0000000e060e7223 */
/* 0x004fe40000000007 */
/*0680*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0690*/ FFMA R14, R15, R7.reuse, R14 ; /* 0x000000070f0e7223 */
/* 0x088fe4000000000e */
/*06a0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06b0*/ FFMA R14, R7, R16, R14 ; /* 0x00000010070e7223 */
/* 0x010fe4000000000e */
/*06c0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06d0*/ FFMA R14, R7, R17, R14 ; /* 0x00000011070e7223 */
/* 0x000fe4000000000e */
/*06e0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06f0*/ FFMA R14, R7, R18, R14 ; /* 0x00000012070e7223 */
/* 0x000fe4000000000e */
/*0700*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0710*/ FFMA R19, R19, R7.reuse, R14 ; /* 0x0000000713137223 */
/* 0x080fe4000000000e */
/*0720*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0730*/ FFMA R12, R7, R12, R19 ; /* 0x0000000c070c7223 */
/* 0x000fe40000000013 */
/*0740*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R7, R15, R13, R12 ; /* 0x0000000d0f077223 */
/* 0x000fe4000000000c */
/*0760*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe40000400000 */
/*0770*/ ISETP.NE.OR P0, PT, R10, -0x1, P0 ; /* 0xffffffff0a00780c */
/* 0x000fda0000705670 */
/*0780*/ @!P0 BRA 0x8d0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000122000c1e1900 */
/*07d0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*07e0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe20003f05270 */
/*0800*/ FFMA R12, R12, R6.reuse, R7 ; /* 0x000000060c0c7223 */
/* 0x084fe40000000007 */
/*0810*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0820*/ FFMA R12, R13, R7.reuse, R12 ; /* 0x000000070d0c7223 */
/* 0x088fe2000000000c */
/*0830*/ IADD3 R13, P1, R4, 0x10, RZ ; /* 0x00000010040d7810 */
/* 0x000fe20007f3e0ff */
/*0840*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc60000400000 */
/*0850*/ IADD3.X R14, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe20000ffe4ff */
/*0860*/ FFMA R12, R15, R7, R12 ; /* 0x000000070f0c7223 */
/* 0x010fe2000000000c */
/*0870*/ MOV R4, R13 ; /* 0x0000000d00047202 */
/* 0x001fe20000000f00 */
/*0880*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fe20000400000 */
/*0890*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fc60000000f00 */
/*08a0*/ FFMA R7, R17, R15.reuse, R12 ; /* 0x0000000f11077223 */
/* 0x080fe4000000000c */
/*08b0*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe20000400000 */
/*08c0*/ @P0 BRA 0x790 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fda0003f05270 */
/*08e0*/ @!P0 BRA 0xa40 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.WIDE R4, R11, R8, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fca00078e0208 */
/*0900*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007f3e0ff */
/*0930*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3.X R12, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0c7210 */
/* 0x000fe20000ffe4ff */
/*0950*/ FFMA R7, R8, R6, R7 ; /* 0x0000000608077223 */
/* 0x004fd40000000007 */
/*0960*/ @!P0 BRA 0xa40 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FMUL R11, R0, R6 ; /* 0x00000006000b7220 */
/* 0x020fe40000400000 */
/*0980*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0990*/ MOV R5, R12 ; /* 0x0000000c00057202 */
/* 0x000fca0000000f00 */
/*09a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ FFMA R7, R4, R11.reuse, R7 ; /* 0x0000000b04077223 */
/* 0x084fe40000000007 */
/*0a00*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x000fd00000400000 */
/*0a10*/ @P0 BRA 0x980 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BRA 0xa40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a30*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fca0000000f00 */
/*0a40*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20polynomial_expansionPfiiS_
.globl _Z20polynomial_expansionPfiiS_
.p2align 8
.type _Z20polynomial_expansionPfiiS_,@function
_Z20polynomial_expansionPfiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_add_i32 s4, s4, 1
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 1.0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20polynomial_expansionPfiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20polynomial_expansionPfiiS_, .Lfunc_end0-_Z20polynomial_expansionPfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20polynomial_expansionPfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20polynomial_expansionPfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00065c5d_00000000-6_polynomial_expansion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.type _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, @function
_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, .-_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.globl _Z20polynomial_expansionPfiiS_
.type _Z20polynomial_expansionPfiiS_, @function
_Z20polynomial_expansionPfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20polynomial_expansionPfiiS_, .-_Z20polynomial_expansionPfiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20polynomial_expansionPfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "polynomial_expansion.hip"
.globl _Z35__device_stub__polynomial_expansionPfiiS_ # -- Begin function _Z35__device_stub__polynomial_expansionPfiiS_
.p2align 4, 0x90
.type _Z35__device_stub__polynomial_expansionPfiiS_,@function
_Z35__device_stub__polynomial_expansionPfiiS_: # @_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20polynomial_expansionPfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__polynomial_expansionPfiiS_, .Lfunc_end0-_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20polynomial_expansionPfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20polynomial_expansionPfiiS_,@object # @_Z20polynomial_expansionPfiiS_
.section .rodata,"a",@progbits
.globl _Z20polynomial_expansionPfiiS_
.p2align 3, 0x0
_Z20polynomial_expansionPfiiS_:
.quad _Z35__device_stub__polynomial_expansionPfiiS_
.size _Z20polynomial_expansionPfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20polynomial_expansionPfiiS_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__polynomial_expansionPfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20polynomial_expansionPfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
struct node{
int dst;
struct node* next;
};
struct list{
struct node *head;
};
struct graph{
int n;
struct list* set;
};
extern __managed__ struct node* newnode;
extern __managed__ struct graph* newgraph;
/*struct node* new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
return newnode;
}*/
void new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
}
/*struct graph* new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
return newgraph;
}*/
void new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
}
/*void addEdge(struct graph* gph, int src, int dst){
struct node* newnode = new_node(dst);
newnode->next = gph->set[src].head;
gph->set[src].head = newnode;
newnode = new_node(src);
newnode->next = gph->set[dst].head;
gph->set[dst].head = newnode;
}*/
void addEdge( int src, int dst){
new_node(dst);
newnode->next = newgraph->set[src].head;
newgraph->set[src].head = newnode;
new_node(src);
newnode->next = newgraph->set[dst].head;
newgraph->set[dst].head = newnode;
}
__global__ void count(int* auth_num) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x * blockDim.x + threadIdx.x; // HERE
// This if statement is added in case we have more threads executing
// Than number of elements in the vectors. How can this help?
int co_auth = 0;
struct node* vert_node = newgraph->set[tid].head;
//printf("\n Adjacency list of vertex %d\n head ", v);
/*while (vert_node)
{
//printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
co_auth++;
}*/
auth_num[tid] = vert_node->dst;
}
//Utility functions to read the file
long get_vert(char *str){
char vert[20];
int space_count = 0;
int num_vert=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 2){
vert[j] = str[i];
j++;
}
else if(space_count>2)
break;
i++;
}
vert[j] = '\0';
//printf("%s\n", vert);
num_vert = atoi(vert);
//printf("%d\n", num_vert);
return num_vert;
}
int get_src(char *str){
char s[20];
int space_count = 0;
int src=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 0){
s[j] = str[i];
j++;
}
else
break;
i++;
}
s[j] = '\0';
//printf("%s\n", s);
src = atoi(s);
//printf("%d\n", src);
return src;
}
int get_dst(char *str){
char d[20];
int space_count = 0;
int dst=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 1){
d[j] = str[i];
j++;
}
else if(space_count>1)
break;
i++;
}
d[j] = '\0';
//printf("%s\n", d);
dst = atoi(d);
//printf("%d\n", dst);
return dst;
}
int compare (const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int main() {
FILE *fp;
char str[200];
const char* file = "dblp-co-authors.txt";
fp = fopen(file, "r");
if (fp == NULL){
printf("Could not open file %s",file);
return 1;
}
int vert;
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
//printf("%s", str);
vert = get_vert(str);
long src, dst;
new_graph(vert);
//struct graph* gph = new_graph(vert);
while (fgets(str, 200, fp) != NULL){
//printf("%s", str);
src = get_src(str);
dst = get_dst(str);
addEdge(src,dst);
}
printf("Graph Created....\n");
/*for(int v=0;v<10;v++){
struct node* vert_node = newgraph->set[v].head;
checkauth=0;
printf("\n Adjacency list of vertex %d\n head ", v);
while (vert_node)
{
printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
}
}*/
// Set GPU Variables based on input arguments
int graph_size = newgraph->n;
int block_size = 512;
int grid_size = ((graph_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
float time;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Input Arrays and variables
int *auth_num = new int [graph_size];
// Pointers in GPU memory
int *auth_num_gpu;
struct graph *gph_gpu;
int actual_size = 1049866 * sizeof(struct graph);
int num_size = graph_size * sizeof(int);
// allocate the memory on the GPU
//cudaMalloc(&gph_gpu, actual_size);
//cudaMalloc(&auth_num_gpu, num_size);
// copy the arrays 'a' and 'b' to the GPU
//cudaMemcpy(gph_gpu,gph,actual_size,cudaMemcpyHostToDevice);
//
// GPU Calculation
////////////////////////
printf("Counting....\n");
cudaEventRecord(start,0);
// call the kernel
//count<<<grid_size,block_size>>>(auth_num_gpu);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
//printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
//cudaMemcpy(auth_num,auth_num_gpu,num_size,cudaMemcpyDeviceToHost);
/*for(int i=0;i<graph_size;i++)
printf("Authors: %d\n",auth_num[i]);*/
// free CPU data
free (newgraph);
free (auth_num);
// free the memory allocated on the GPU
// HERE
//cudaFree(auth_num_gpu);
return 0;
} | code for sm_80
Function : _Z5countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x4][0x8] ; /* 0x0100020000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x4][0xc] ; /* 0x0100030000037a02 */
/* 0x000fcc0000000f00 */
/*0040*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0070*/ LDG.E.64 R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x004ea2000c1e1b00 */
/*0080*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD.WIDE R4, R7, 0x8, R4 ; /* 0x0000000807047825 */
/* 0x004fcc00078e0204 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc600000001ff */
/*00c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x004eae000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0206 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
struct node{
int dst;
struct node* next;
};
struct list{
struct node *head;
};
struct graph{
int n;
struct list* set;
};
extern __managed__ struct node* newnode;
extern __managed__ struct graph* newgraph;
/*struct node* new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
return newnode;
}*/
void new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
}
/*struct graph* new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
return newgraph;
}*/
void new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
}
/*void addEdge(struct graph* gph, int src, int dst){
struct node* newnode = new_node(dst);
newnode->next = gph->set[src].head;
gph->set[src].head = newnode;
newnode = new_node(src);
newnode->next = gph->set[dst].head;
gph->set[dst].head = newnode;
}*/
void addEdge( int src, int dst){
new_node(dst);
newnode->next = newgraph->set[src].head;
newgraph->set[src].head = newnode;
new_node(src);
newnode->next = newgraph->set[dst].head;
newgraph->set[dst].head = newnode;
}
__global__ void count(int* auth_num) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x * blockDim.x + threadIdx.x; // HERE
// This if statement is added in case we have more threads executing
// Than number of elements in the vectors. How can this help?
int co_auth = 0;
struct node* vert_node = newgraph->set[tid].head;
//printf("\n Adjacency list of vertex %d\n head ", v);
/*while (vert_node)
{
//printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
co_auth++;
}*/
auth_num[tid] = vert_node->dst;
}
//Utility functions to read the file
long get_vert(char *str){
char vert[20];
int space_count = 0;
int num_vert=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 2){
vert[j] = str[i];
j++;
}
else if(space_count>2)
break;
i++;
}
vert[j] = '\0';
//printf("%s\n", vert);
num_vert = atoi(vert);
//printf("%d\n", num_vert);
return num_vert;
}
int get_src(char *str){
char s[20];
int space_count = 0;
int src=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 0){
s[j] = str[i];
j++;
}
else
break;
i++;
}
s[j] = '\0';
//printf("%s\n", s);
src = atoi(s);
//printf("%d\n", src);
return src;
}
int get_dst(char *str){
char d[20];
int space_count = 0;
int dst=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 1){
d[j] = str[i];
j++;
}
else if(space_count>1)
break;
i++;
}
d[j] = '\0';
//printf("%s\n", d);
dst = atoi(d);
//printf("%d\n", dst);
return dst;
}
int compare (const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int main() {
FILE *fp;
char str[200];
const char* file = "dblp-co-authors.txt";
fp = fopen(file, "r");
if (fp == NULL){
printf("Could not open file %s",file);
return 1;
}
int vert;
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
//printf("%s", str);
vert = get_vert(str);
long src, dst;
new_graph(vert);
//struct graph* gph = new_graph(vert);
while (fgets(str, 200, fp) != NULL){
//printf("%s", str);
src = get_src(str);
dst = get_dst(str);
addEdge(src,dst);
}
printf("Graph Created....\n");
/*for(int v=0;v<10;v++){
struct node* vert_node = newgraph->set[v].head;
checkauth=0;
printf("\n Adjacency list of vertex %d\n head ", v);
while (vert_node)
{
printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
}
}*/
// Set GPU Variables based on input arguments
int graph_size = newgraph->n;
int block_size = 512;
int grid_size = ((graph_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
float time;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Input Arrays and variables
int *auth_num = new int [graph_size];
// Pointers in GPU memory
int *auth_num_gpu;
struct graph *gph_gpu;
int actual_size = 1049866 * sizeof(struct graph);
int num_size = graph_size * sizeof(int);
// allocate the memory on the GPU
//cudaMalloc(&gph_gpu, actual_size);
//cudaMalloc(&auth_num_gpu, num_size);
// copy the arrays 'a' and 'b' to the GPU
//cudaMemcpy(gph_gpu,gph,actual_size,cudaMemcpyHostToDevice);
//
// GPU Calculation
////////////////////////
printf("Counting....\n");
cudaEventRecord(start,0);
// call the kernel
//count<<<grid_size,block_size>>>(auth_num_gpu);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
//printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
//cudaMemcpy(auth_num,auth_num_gpu,num_size,cudaMemcpyDeviceToHost);
/*for(int i=0;i<graph_size;i++)
printf("Authors: %d\n",auth_num[i]);*/
// free CPU data
free (newgraph);
free (auth_num);
// free the memory allocated on the GPU
// HERE
//cudaFree(auth_num_gpu);
return 0;
} | .file "tmpxft_000c0d79_00000000-6_p2a_authors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE1:
.size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8new_nodei
.type _Z8new_nodei, @function
_Z8new_nodei:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L16
.L11:
movl $1, %edx
movl $16, %esi
movq _ZL7newnode(%rip), %rdi
call cudaMallocManaged@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L17
.L12:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rdi
movl $-1, %ecx
movl $5, %edx
movl $16, %esi
call cudaMemAdvise@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L18
.L13:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L19
.L14:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rax
movq $0, 8(%rax)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L11
.L17:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L12
.L18:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L13
.L19:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L14
.cfi_endproc
.LFE2057:
.size _Z8new_nodei, .-_Z8new_nodei
.globl _Z9new_graphi
.type _Z9new_graphi, @function
_Z9new_graphi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L30
.L21:
movl $1, %edx
movl $16, %esi
movq _ZL8newgraph(%rip), %rdi
call cudaMallocManaged@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L31
.L22:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rdi
movl $-1, %ecx
movl $5, %edx
movl $16, %esi
call cudaMemAdvise@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L32
.L23:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movslq %ebx, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L33
.L24:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq %r12, 8(%rax)
testl %ebx, %ebx
jle .L20
movl $0, %ebx
jmp .L27
.L30:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L21
.L31:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L22
.L32:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L23
.L33:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L24
.L26:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq $0, (%rax,%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
je .L20
.L27:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L26
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L26
.L20:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9new_graphi, .-_Z9new_graphi
.globl _Z7addEdgeii
.type _Z7addEdgeii, @function
_Z7addEdgeii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movl %esi, %edi
call _Z8new_nodei
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L45
movslq %ebp, %rax
leaq 0(,%rax,8), %r13
movq _ZL8newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq (%rdx,%rax,8), %r12
.L36:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rdx
movq %r12, 8(%rdx)
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L46
movq (%rax), %r12
.L38:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq %r12, (%rax,%r13)
movl %ebp, %edi
call _Z8new_nodei
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L47
movslq %ebx, %rbx
leaq 0(,%rbx,8), %rbp
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq (%rax,%rbx,8), %rbx
.L40:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rdx
movq %rbx, 8(%rdx)
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L48
movq (%rax), %rbx
.L42:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq %rbx, (%rax,%rbp)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movslq %ebp, %rdx
leaq 0(,%rdx,8), %r13
movq _ZL8newgraph(%rip), %rcx
movq (%rcx), %rcx
movq 8(%rcx), %rcx
movq (%rcx,%rdx,8), %r12
testb %al, %al
jne .L36
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L36
.L46:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movq _ZL7newnode(%rip), %rdx
movq (%rdx), %r12
testb %al, %al
jne .L38
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L38
.L47:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movslq %ebx, %rbx
leaq 0(,%rbx,8), %rbp
movq _ZL8newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq (%rdx,%rbx,8), %rbx
testb %al, %al
jne .L40
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L40
.L48:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movq _ZL7newnode(%rip), %rdx
movq (%rdx), %rbx
testb %al, %al
jne .L42
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L42
.cfi_endproc
.LFE2059:
.size _Z7addEdgeii, .-_Z7addEdgeii
.globl _Z8get_vertPc
.type _Z8get_vertPc, @function
_Z8get_vertPc:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl (%rdi), %eax
cmpb $10, %al
je .L57
addq $1, %rdi
movl $0, %ecx
movl $0, %edx
jmp .L54
.L62:
addl $1, %edx
cmpl $2, %edx
je .L55
jle .L53
.L50:
movslq %ecx, %rcx
movb $0, (%rsp,%rcx)
movq %rsp, %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movslq %ecx, %rdx
movb %al, (%rsp,%rdx)
addl $1, %ecx
movl $2, %edx
.L53:
addq $1, %rdi
movzbl -1(%rdi), %eax
cmpb $10, %al
je .L50
.L54:
cmpb $32, %al
je .L62
cmpl $2, %edx
jne .L53
jmp .L55
.L57:
movl $0, %ecx
jmp .L50
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8get_vertPc, .-_Z8get_vertPc
.globl _Z7get_srcPc
.type _Z7get_srcPc, @function
_Z7get_srcPc:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl (%rdi), %eax
cmpb $10, %al
je .L68
movl $1, %edx
leaq -1(%rsp), %rsi
jmp .L66
.L68:
movl $0, %edx
jmp .L64
.L65:
movb %al, (%rsi,%rdx)
leaq 1(%rdx), %rcx
movzbl -1(%rdi,%rcx), %eax
cmpb $10, %al
je .L64
movq %rcx, %rdx
.L66:
cmpb $32, %al
jne .L65
subl $1, %edx
.L64:
movslq %edx, %rdx
movb $0, (%rsp,%rdx)
movq %rsp, %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L72
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7get_srcPc, .-_Z7get_srcPc
.globl _Z7get_dstPc
.type _Z7get_dstPc, @function
_Z7get_dstPc:
.LFB2062:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl (%rdi), %eax
cmpb $10, %al
je .L81
addq $1, %rdi
movl $0, %ecx
movl $0, %edx
jmp .L78
.L86:
addl $1, %edx
cmpl $1, %edx
je .L79
jle .L77
.L74:
movslq %ecx, %rcx
movb $0, (%rsp,%rcx)
movq %rsp, %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L85
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movslq %ecx, %rdx
movb %al, (%rsp,%rdx)
addl $1, %ecx
movl $1, %edx
.L77:
addq $1, %rdi
movzbl -1(%rdi), %eax
cmpb $10, %al
je .L74
.L78:
cmpb $32, %al
je .L86
cmpl $1, %edx
jne .L77
jmp .L79
.L81:
movl $0, %ecx
jmp .L74
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z7get_dstPc, .-_Z7get_dstPc
.globl _Z7comparePKvS0_
.type _Z7comparePKvS0_, @function
_Z7comparePKvS0_:
.LFB2063:
.cfi_startproc
endbr64
movl (%rsi), %eax
subl (%rdi), %eax
ret
.cfi_endproc
.LFE2063:
.size _Z7comparePKvS0_, .-_Z7comparePKvS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "dblp-co-authors.txt"
.LC2:
.string "Could not open file %s"
.LC3:
.string "Graph Created....\n"
.LC4:
.string "Counting....\n"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $240, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L101
movq %rax, %r12
leaq 32(%rsp), %rbx
movq %rax, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rdi
call _Z8get_vertPc
movl %eax, %edi
call _Z9new_graphi
movq %rbx, %rbp
jmp .L91
.L101:
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L88
.L92:
movq %rbp, %rdi
call _Z7get_srcPc
movl %eax, %ebx
movq %rbp, %rdi
call _Z7get_dstPc
movl %eax, %esi
movl %ebx, %edi
call _Z7addEdgeii
.L91:
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbp, %rdi
call __fgets_chk@PLT
testq %rax, %rax
jne .L92
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L102
.L93:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movl (%rax), %ebx
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebx, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L94
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L103
.L95:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L88:
movq 232(%rsp), %rdx
subq %fs:40, %rdx
jne .L104
addq $240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
call _ZL20__nv_init_managed_rtv
jmp .L93
.L94:
movq 232(%rsp), %rax
subq %fs:40, %rax
je .L97
call __stack_chk_fail@PLT
.L97:
call __cxa_throw_bad_array_new_length@PLT
.L103:
call _ZL20__nv_init_managed_rtv
jmp .L95
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size main, .-main
.globl _Z24__device_stub__Z5countPiPi
.type _Z24__device_stub__Z5countPiPi, @function
_Z24__device_stub__Z5countPiPi:
.LFB2089:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L109
.L105:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L110
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L105
.L110:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z24__device_stub__Z5countPiPi, .-_Z24__device_stub__Z5countPiPi
.globl _Z5countPi
.type _Z5countPi, @function
_Z5countPi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z5countPi, .-_Z5countPi
.section .rodata.str1.1
.LC5:
.string "_Z5countPi"
.LC6:
.string "newnode"
.LC7:
.string "newgraph"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5countPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7newnode(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8newgraph(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL8newgraph, @object
.size _ZL8newgraph, 8
_ZL8newgraph:
.zero 8
.align 8
.type _ZL7newnode, @object
.size _ZL7newnode, 8
_ZL7newnode:
.zero 8
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
struct node{
int dst;
struct node* next;
};
struct list{
struct node *head;
};
struct graph{
int n;
struct list* set;
};
extern __managed__ struct node* newnode;
extern __managed__ struct graph* newgraph;
/*struct node* new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
return newnode;
}*/
void new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
}
/*struct graph* new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
return newgraph;
}*/
void new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
}
/*void addEdge(struct graph* gph, int src, int dst){
struct node* newnode = new_node(dst);
newnode->next = gph->set[src].head;
gph->set[src].head = newnode;
newnode = new_node(src);
newnode->next = gph->set[dst].head;
gph->set[dst].head = newnode;
}*/
void addEdge( int src, int dst){
new_node(dst);
newnode->next = newgraph->set[src].head;
newgraph->set[src].head = newnode;
new_node(src);
newnode->next = newgraph->set[dst].head;
newgraph->set[dst].head = newnode;
}
__global__ void count(int* auth_num) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x * blockDim.x + threadIdx.x; // HERE
// This if statement is added in case we have more threads executing
// Than number of elements in the vectors. How can this help?
int co_auth = 0;
struct node* vert_node = newgraph->set[tid].head;
//printf("\n Adjacency list of vertex %d\n head ", v);
/*while (vert_node)
{
//printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
co_auth++;
}*/
auth_num[tid] = vert_node->dst;
}
//Utility functions to read the file
long get_vert(char *str){
char vert[20];
int space_count = 0;
int num_vert=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 2){
vert[j] = str[i];
j++;
}
else if(space_count>2)
break;
i++;
}
vert[j] = '\0';
//printf("%s\n", vert);
num_vert = atoi(vert);
//printf("%d\n", num_vert);
return num_vert;
}
int get_src(char *str){
char s[20];
int space_count = 0;
int src=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 0){
s[j] = str[i];
j++;
}
else
break;
i++;
}
s[j] = '\0';
//printf("%s\n", s);
src = atoi(s);
//printf("%d\n", src);
return src;
}
int get_dst(char *str){
char d[20];
int space_count = 0;
int dst=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 1){
d[j] = str[i];
j++;
}
else if(space_count>1)
break;
i++;
}
d[j] = '\0';
//printf("%s\n", d);
dst = atoi(d);
//printf("%d\n", dst);
return dst;
}
int compare (const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int main() {
FILE *fp;
char str[200];
const char* file = "dblp-co-authors.txt";
fp = fopen(file, "r");
if (fp == NULL){
printf("Could not open file %s",file);
return 1;
}
int vert;
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
//printf("%s", str);
vert = get_vert(str);
long src, dst;
new_graph(vert);
//struct graph* gph = new_graph(vert);
while (fgets(str, 200, fp) != NULL){
//printf("%s", str);
src = get_src(str);
dst = get_dst(str);
addEdge(src,dst);
}
printf("Graph Created....\n");
/*for(int v=0;v<10;v++){
struct node* vert_node = newgraph->set[v].head;
checkauth=0;
printf("\n Adjacency list of vertex %d\n head ", v);
while (vert_node)
{
printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
}
}*/
// Set GPU Variables based on input arguments
int graph_size = newgraph->n;
int block_size = 512;
int grid_size = ((graph_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
float time;
cudaEventCreate (&start);
cudaEventCreate (&stop);
// Input Arrays and variables
int *auth_num = new int [graph_size];
// Pointers in GPU memory
int *auth_num_gpu;
struct graph *gph_gpu;
int actual_size = 1049866 * sizeof(struct graph);
int num_size = graph_size * sizeof(int);
// allocate the memory on the GPU
//cudaMalloc(&gph_gpu, actual_size);
//cudaMalloc(&auth_num_gpu, num_size);
// copy the arrays 'a' and 'b' to the GPU
//cudaMemcpy(gph_gpu,gph,actual_size,cudaMemcpyHostToDevice);
//
// GPU Calculation
////////////////////////
printf("Counting....\n");
cudaEventRecord(start,0);
// call the kernel
//count<<<grid_size,block_size>>>(auth_num_gpu);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
//printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
//cudaMemcpy(auth_num,auth_num_gpu,num_size,cudaMemcpyDeviceToHost);
/*for(int i=0;i<graph_size;i++)
printf("Authors: %d\n",auth_num[i]);*/
// free CPU data
free (newgraph);
free (auth_num);
// free the memory allocated on the GPU
// HERE
//cudaFree(auth_num_gpu);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
struct node{
int dst;
struct node* next;
};
struct list{
struct node *head;
};
struct graph{
int n;
struct list* set;
};
extern __managed__ struct node* newnode;
extern __managed__ struct graph* newgraph;
/*struct node* new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
return newnode;
}*/
void new_node(int dst){
hipMallocManaged(&newnode, sizeof(struct node), (unsigned int)hipMemAttachGlobal);
hipMemAdvise(newnode, sizeof(struct node), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
}
/*struct graph* new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
return newgraph;
}*/
void new_graph(int n){
hipMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)hipMemAttachGlobal);
hipMemAdvise(newgraph, sizeof(struct graph), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
}
/*void addEdge(struct graph* gph, int src, int dst){
struct node* newnode = new_node(dst);
newnode->next = gph->set[src].head;
gph->set[src].head = newnode;
newnode = new_node(src);
newnode->next = gph->set[dst].head;
gph->set[dst].head = newnode;
}*/
void addEdge( int src, int dst){
new_node(dst);
newnode->next = newgraph->set[src].head;
newgraph->set[src].head = newnode;
new_node(src);
newnode->next = newgraph->set[dst].head;
newgraph->set[dst].head = newnode;
}
__global__ void count(int* auth_num) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x * blockDim.x + threadIdx.x; // HERE
// This if statement is added in case we have more threads executing
// Than number of elements in the vectors. How can this help?
int co_auth = 0;
struct node* vert_node = newgraph->set[tid].head;
//printf("\n Adjacency list of vertex %d\n head ", v);
/*while (vert_node)
{
//printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
co_auth++;
}*/
auth_num[tid] = vert_node->dst;
}
//Utility functions to read the file
long get_vert(char *str){
char vert[20];
int space_count = 0;
int num_vert=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 2){
vert[j] = str[i];
j++;
}
else if(space_count>2)
break;
i++;
}
vert[j] = '\0';
//printf("%s\n", vert);
num_vert = atoi(vert);
//printf("%d\n", num_vert);
return num_vert;
}
int get_src(char *str){
char s[20];
int space_count = 0;
int src=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 0){
s[j] = str[i];
j++;
}
else
break;
i++;
}
s[j] = '\0';
//printf("%s\n", s);
src = atoi(s);
//printf("%d\n", src);
return src;
}
int get_dst(char *str){
char d[20];
int space_count = 0;
int dst=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 1){
d[j] = str[i];
j++;
}
else if(space_count>1)
break;
i++;
}
d[j] = '\0';
//printf("%s\n", d);
dst = atoi(d);
//printf("%d\n", dst);
return dst;
}
int compare (const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int main() {
FILE *fp;
char str[200];
const char* file = "dblp-co-authors.txt";
fp = fopen(file, "r");
if (fp == NULL){
printf("Could not open file %s",file);
return 1;
}
int vert;
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
//printf("%s", str);
vert = get_vert(str);
long src, dst;
new_graph(vert);
//struct graph* gph = new_graph(vert);
while (fgets(str, 200, fp) != NULL){
//printf("%s", str);
src = get_src(str);
dst = get_dst(str);
addEdge(src,dst);
}
printf("Graph Created....\n");
/*for(int v=0;v<10;v++){
struct node* vert_node = newgraph->set[v].head;
checkauth=0;
printf("\n Adjacency list of vertex %d\n head ", v);
while (vert_node)
{
printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
}
}*/
// Set GPU Variables based on input arguments
int graph_size = newgraph->n;
int block_size = 512;
int grid_size = ((graph_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
float time;
hipEventCreate (&start);
hipEventCreate (&stop);
// Input Arrays and variables
int *auth_num = new int [graph_size];
// Pointers in GPU memory
int *auth_num_gpu;
struct graph *gph_gpu;
int actual_size = 1049866 * sizeof(struct graph);
int num_size = graph_size * sizeof(int);
// allocate the memory on the GPU
//cudaMalloc(&gph_gpu, actual_size);
//cudaMalloc(&auth_num_gpu, num_size);
// copy the arrays 'a' and 'b' to the GPU
//cudaMemcpy(gph_gpu,gph,actual_size,cudaMemcpyHostToDevice);
//
// GPU Calculation
////////////////////////
printf("Counting....\n");
hipEventRecord(start,0);
// call the kernel
//count<<<grid_size,block_size>>>(auth_num_gpu);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
//printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
//cudaMemcpy(auth_num,auth_num_gpu,num_size,cudaMemcpyDeviceToHost);
/*for(int i=0;i<graph_size;i++)
printf("Authors: %d\n",auth_num[i]);*/
// free CPU data
free (newgraph);
free (auth_num);
// free the memory allocated on the GPU
// HERE
//cudaFree(auth_num_gpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
struct node{
int dst;
struct node* next;
};
struct list{
struct node *head;
};
struct graph{
int n;
struct list* set;
};
extern __managed__ struct node* newnode;
extern __managed__ struct graph* newgraph;
/*struct node* new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
return newnode;
}*/
void new_node(int dst){
hipMallocManaged(&newnode, sizeof(struct node), (unsigned int)hipMemAttachGlobal);
hipMemAdvise(newnode, sizeof(struct node), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
}
/*struct graph* new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
return newgraph;
}*/
void new_graph(int n){
hipMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)hipMemAttachGlobal);
hipMemAdvise(newgraph, sizeof(struct graph), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
}
/*void addEdge(struct graph* gph, int src, int dst){
struct node* newnode = new_node(dst);
newnode->next = gph->set[src].head;
gph->set[src].head = newnode;
newnode = new_node(src);
newnode->next = gph->set[dst].head;
gph->set[dst].head = newnode;
}*/
void addEdge( int src, int dst){
new_node(dst);
newnode->next = newgraph->set[src].head;
newgraph->set[src].head = newnode;
new_node(src);
newnode->next = newgraph->set[dst].head;
newgraph->set[dst].head = newnode;
}
__global__ void count(int* auth_num) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x * blockDim.x + threadIdx.x; // HERE
// This if statement is added in case we have more threads executing
// Than number of elements in the vectors. How can this help?
int co_auth = 0;
struct node* vert_node = newgraph->set[tid].head;
//printf("\n Adjacency list of vertex %d\n head ", v);
/*while (vert_node)
{
//printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
co_auth++;
}*/
auth_num[tid] = vert_node->dst;
}
//Utility functions to read the file
long get_vert(char *str){
char vert[20];
int space_count = 0;
int num_vert=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 2){
vert[j] = str[i];
j++;
}
else if(space_count>2)
break;
i++;
}
vert[j] = '\0';
//printf("%s\n", vert);
num_vert = atoi(vert);
//printf("%d\n", num_vert);
return num_vert;
}
int get_src(char *str){
char s[20];
int space_count = 0;
int src=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 0){
s[j] = str[i];
j++;
}
else
break;
i++;
}
s[j] = '\0';
//printf("%s\n", s);
src = atoi(s);
//printf("%d\n", src);
return src;
}
int get_dst(char *str){
char d[20];
int space_count = 0;
int dst=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 1){
d[j] = str[i];
j++;
}
else if(space_count>1)
break;
i++;
}
d[j] = '\0';
//printf("%s\n", d);
dst = atoi(d);
//printf("%d\n", dst);
return dst;
}
int compare (const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int main() {
FILE *fp;
char str[200];
const char* file = "dblp-co-authors.txt";
fp = fopen(file, "r");
if (fp == NULL){
printf("Could not open file %s",file);
return 1;
}
int vert;
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
//printf("%s", str);
vert = get_vert(str);
long src, dst;
new_graph(vert);
//struct graph* gph = new_graph(vert);
while (fgets(str, 200, fp) != NULL){
//printf("%s", str);
src = get_src(str);
dst = get_dst(str);
addEdge(src,dst);
}
printf("Graph Created....\n");
/*for(int v=0;v<10;v++){
struct node* vert_node = newgraph->set[v].head;
checkauth=0;
printf("\n Adjacency list of vertex %d\n head ", v);
while (vert_node)
{
printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
}
}*/
// Set GPU Variables based on input arguments
int graph_size = newgraph->n;
int block_size = 512;
int grid_size = ((graph_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
float time;
hipEventCreate (&start);
hipEventCreate (&stop);
// Input Arrays and variables
int *auth_num = new int [graph_size];
// Pointers in GPU memory
int *auth_num_gpu;
struct graph *gph_gpu;
int actual_size = 1049866 * sizeof(struct graph);
int num_size = graph_size * sizeof(int);
// allocate the memory on the GPU
//cudaMalloc(&gph_gpu, actual_size);
//cudaMalloc(&auth_num_gpu, num_size);
// copy the arrays 'a' and 'b' to the GPU
//cudaMemcpy(gph_gpu,gph,actual_size,cudaMemcpyHostToDevice);
//
// GPU Calculation
////////////////////////
printf("Counting....\n");
hipEventRecord(start,0);
// call the kernel
//count<<<grid_size,block_size>>>(auth_num_gpu);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
//printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
//cudaMemcpy(auth_num,auth_num_gpu,num_size,cudaMemcpyDeviceToHost);
/*for(int i=0;i<graph_size;i++)
printf("Authors: %d\n",auth_num[i]);*/
// free CPU data
free (newgraph);
free (auth_num);
// free the memory allocated on the GPU
// HERE
//cudaFree(auth_num_gpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5countPi
.globl _Z5countPi
.p2align 8
.type _Z5countPi,@function
_Z5countPi:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, newgraph@rel32@lo+4
s_addc_u32 s3, s3, newgraph@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
flat_load_b64 v[1:2], v[1:2] offset:8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v1, v5
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v6, vcc_lo
flat_load_b64 v[0:1], v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_load_b32 v2, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5countPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5countPi, .Lfunc_end0-_Z5countPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected newgraph
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5countPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
struct node{
int dst;
struct node* next;
};
struct list{
struct node *head;
};
struct graph{
int n;
struct list* set;
};
extern __managed__ struct node* newnode;
extern __managed__ struct graph* newgraph;
/*struct node* new_node(int dst){
cudaMallocManaged(&newnode, sizeof(struct node), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newnode, sizeof(struct node), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
return newnode;
}*/
void new_node(int dst){
hipMallocManaged(&newnode, sizeof(struct node), (unsigned int)hipMemAttachGlobal);
hipMemAdvise(newnode, sizeof(struct node), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
newnode -> dst = dst;
newnode -> next = NULL;
}
/*struct graph* new_graph(int n){
cudaMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)cudaMemAttachGlobal);
cudaMemAdvise(newgraph, sizeof(struct graph), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
return newgraph;
}*/
void new_graph(int n){
hipMallocManaged(&newgraph, sizeof(struct graph), (unsigned int)hipMemAttachGlobal);
hipMemAdvise(newgraph, sizeof(struct graph), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
newgraph -> n = n;
newgraph -> set = (struct list*)malloc(n * sizeof(struct list)) ;
int i;
for(i=0;i<n;i++)
newgraph->set[i].head = NULL;
}
/*void addEdge(struct graph* gph, int src, int dst){
struct node* newnode = new_node(dst);
newnode->next = gph->set[src].head;
gph->set[src].head = newnode;
newnode = new_node(src);
newnode->next = gph->set[dst].head;
gph->set[dst].head = newnode;
}*/
void addEdge( int src, int dst){
new_node(dst);
newnode->next = newgraph->set[src].head;
newgraph->set[src].head = newnode;
new_node(src);
newnode->next = newgraph->set[dst].head;
newgraph->set[dst].head = newnode;
}
__global__ void count(int* auth_num) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x * blockDim.x + threadIdx.x; // HERE
// This if statement is added in case we have more threads executing
// Than number of elements in the vectors. How can this help?
int co_auth = 0;
struct node* vert_node = newgraph->set[tid].head;
//printf("\n Adjacency list of vertex %d\n head ", v);
/*while (vert_node)
{
//printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
co_auth++;
}*/
auth_num[tid] = vert_node->dst;
}
//Utility functions to read the file
long get_vert(char *str){
char vert[20];
int space_count = 0;
int num_vert=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 2){
vert[j] = str[i];
j++;
}
else if(space_count>2)
break;
i++;
}
vert[j] = '\0';
//printf("%s\n", vert);
num_vert = atoi(vert);
//printf("%d\n", num_vert);
return num_vert;
}
int get_src(char *str){
char s[20];
int space_count = 0;
int src=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 0){
s[j] = str[i];
j++;
}
else
break;
i++;
}
s[j] = '\0';
//printf("%s\n", s);
src = atoi(s);
//printf("%d\n", src);
return src;
}
int get_dst(char *str){
char d[20];
int space_count = 0;
int dst=0;
int i=0, j=0;
while(str[i] != '\n'){
if(str[i] == ' ')
space_count++;
if(space_count == 1){
d[j] = str[i];
j++;
}
else if(space_count>1)
break;
i++;
}
d[j] = '\0';
//printf("%s\n", d);
dst = atoi(d);
//printf("%d\n", dst);
return dst;
}
int compare (const void * a, const void * b)
{
return ( *(int*)b - *(int*)a );
}
int main() {
FILE *fp;
char str[200];
const char* file = "dblp-co-authors.txt";
fp = fopen(file, "r");
if (fp == NULL){
printf("Could not open file %s",file);
return 1;
}
int vert;
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
fgets(str, 200, fp);
//printf("%s", str);
vert = get_vert(str);
long src, dst;
new_graph(vert);
//struct graph* gph = new_graph(vert);
while (fgets(str, 200, fp) != NULL){
//printf("%s", str);
src = get_src(str);
dst = get_dst(str);
addEdge(src,dst);
}
printf("Graph Created....\n");
/*for(int v=0;v<10;v++){
struct node* vert_node = newgraph->set[v].head;
checkauth=0;
printf("\n Adjacency list of vertex %d\n head ", v);
while (vert_node)
{
printf("-> %d", vert_node->dst);
vert_node = vert_node->next;
}
}*/
// Set GPU Variables based on input arguments
int graph_size = newgraph->n;
int block_size = 512;
int grid_size = ((graph_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
float time;
hipEventCreate (&start);
hipEventCreate (&stop);
// Input Arrays and variables
int *auth_num = new int [graph_size];
// Pointers in GPU memory
int *auth_num_gpu;
struct graph *gph_gpu;
int actual_size = 1049866 * sizeof(struct graph);
int num_size = graph_size * sizeof(int);
// allocate the memory on the GPU
//cudaMalloc(&gph_gpu, actual_size);
//cudaMalloc(&auth_num_gpu, num_size);
// copy the arrays 'a' and 'b' to the GPU
//cudaMemcpy(gph_gpu,gph,actual_size,cudaMemcpyHostToDevice);
//
// GPU Calculation
////////////////////////
printf("Counting....\n");
hipEventRecord(start,0);
// call the kernel
//count<<<grid_size,block_size>>>(auth_num_gpu);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
//printf("\tParallel Job Time: %.2f ms\n", time);
// copy the array 'c' back from the GPU to the CPU
// HERE (there's one more at the end, don't miss it!)
//cudaMemcpy(auth_num,auth_num_gpu,num_size,cudaMemcpyDeviceToHost);
/*for(int i=0;i<graph_size;i++)
printf("Authors: %d\n",auth_num[i]);*/
// free CPU data
free (newgraph);
free (auth_num);
// free the memory allocated on the GPU
// HERE
//cudaFree(auth_num_gpu);
return 0;
} | .text
.file "p2a_authors.hip"
.globl _Z8new_nodei # -- Begin function _Z8new_nodei
.p2align 4, 0x90
.type _Z8new_nodei,@function
_Z8new_nodei: # @_Z8new_nodei
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
movq newnode(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newnode(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newnode(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movq newnode(%rip), %rax
movq (%rax), %rax
movq $0, 8(%rax)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8new_nodei, .Lfunc_end0-_Z8new_nodei
.cfi_endproc
# -- End function
.globl _Z9new_graphi # -- Begin function _Z9new_graphi
.p2align 4, 0x90
.type _Z9new_graphi,@function
_Z9new_graphi: # @_Z9new_graphi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movq newgraph(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newgraph(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newgraph(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movslq %ebx, %r14
leaq (,%r14,8), %rdi
callq malloc
movq newgraph(%rip), %rcx
movq (%rcx), %rcx
movq %rax, 8(%rcx)
testl %r14d, %r14d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq $0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9new_graphi, .Lfunc_end1-_Z9new_graphi
.cfi_endproc
# -- End function
.globl _Z7addEdgeii # -- Begin function _Z7addEdgeii
.p2align 4, 0x90
.type _Z7addEdgeii,@function
_Z7addEdgeii: # @_Z7addEdgeii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movq newnode(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newnode(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newnode(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movq newnode(%rip), %rax
movq (%rax), %rcx
movq $0, 8(%rcx)
movq newgraph(%rip), %rcx
movq (%rcx), %rdx
movq 8(%rdx), %rdx
movslq %ebp, %r14
movq (%rdx,%r14,8), %rdx
movq (%rax), %rsi
movq %rdx, 8(%rsi)
movq (%rax), %rax
movq (%rcx), %rcx
movq 8(%rcx), %rcx
movq %rax, (%rcx,%r14,8)
movq newnode(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newnode(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newnode(%rip), %rax
movq (%rax), %rax
movl %r14d, (%rax)
movq newnode(%rip), %rax
movq (%rax), %rcx
movq $0, 8(%rcx)
movq newgraph(%rip), %rcx
movq (%rcx), %rdx
movq 8(%rdx), %rdx
movslq %ebx, %rsi
movq (%rdx,%rsi,8), %rdx
movq (%rax), %rdi
movq %rdx, 8(%rdi)
movq (%rax), %rax
movq (%rcx), %rcx
movq 8(%rcx), %rcx
movq %rax, (%rcx,%rsi,8)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7addEdgeii, .Lfunc_end2-_Z7addEdgeii
.cfi_endproc
# -- End function
.globl _Z20__device_stub__countPi # -- Begin function _Z20__device_stub__countPi
.p2align 4, 0x90
.type _Z20__device_stub__countPi,@function
_Z20__device_stub__countPi: # @_Z20__device_stub__countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z20__device_stub__countPi, .Lfunc_end3-_Z20__device_stub__countPi
.cfi_endproc
# -- End function
.globl _Z8get_vertPc # -- Begin function _Z8get_vertPc
.p2align 4, 0x90
.type _Z8get_vertPc,@function
_Z8get_vertPc: # @_Z8get_vertPc
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_6: # in Loop: Header=BB4_1 Depth=1
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %rdi
.LBB4_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi), %edx
cmpl $32, %edx
je .LBB4_4
# %bb.2: # in Loop: Header=BB4_1 Depth=1
cmpl $10, %edx
je .LBB4_3
# %bb.5: # in Loop: Header=BB4_1 Depth=1
cmpl $2, %eax
je .LBB4_6
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_1 Depth=1
incl %eax
cmpl $2, %eax
je .LBB4_6
.LBB4_7: # in Loop: Header=BB4_1 Depth=1
jg .LBB4_3
# %bb.8: # in Loop: Header=BB4_1 Depth=1
incq %rdi
jmp .LBB4_1
.LBB4_3:
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cltq
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8get_vertPc, .Lfunc_end4-_Z8get_vertPc
.cfi_endproc
# -- End function
.globl _Z7get_srcPc # -- Begin function _Z7get_srcPc
.p2align 4, 0x90
.type _Z7get_srcPc,@function
_Z7get_srcPc: # @_Z7get_srcPc
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rax), %ecx
cmpl $10, %ecx
je .LBB5_4
# %bb.2: # in Loop: Header=BB5_1 Depth=1
cmpl $32, %ecx
je .LBB5_4
# %bb.3: # in Loop: Header=BB5_1 Depth=1
movb %cl, (%rsp,%rax)
incq %rax
jmp .LBB5_1
.LBB5_4:
movl %eax, %eax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z7get_srcPc, .Lfunc_end5-_Z7get_srcPc
.cfi_endproc
# -- End function
.globl _Z7get_dstPc # -- Begin function _Z7get_dstPc
.p2align 4, 0x90
.type _Z7get_dstPc,@function
_Z7get_dstPc: # @_Z7get_dstPc
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_1 Depth=1
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %rdi
.LBB6_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi), %edx
cmpl $32, %edx
je .LBB6_4
# %bb.2: # in Loop: Header=BB6_1 Depth=1
cmpl $10, %edx
je .LBB6_3
# %bb.5: # in Loop: Header=BB6_1 Depth=1
cmpl $1, %eax
je .LBB6_6
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_4: # in Loop: Header=BB6_1 Depth=1
incl %eax
cmpl $1, %eax
je .LBB6_6
.LBB6_7: # in Loop: Header=BB6_1 Depth=1
jg .LBB6_3
# %bb.8: # in Loop: Header=BB6_1 Depth=1
incq %rdi
jmp .LBB6_1
.LBB6_3:
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7get_dstPc, .Lfunc_end6-_Z7get_dstPc
.cfi_endproc
# -- End function
.globl _Z7comparePKvS0_ # -- Begin function _Z7comparePKvS0_
.p2align 4, 0x90
.type _Z7comparePKvS0_,@function
_Z7comparePKvS0_: # @_Z7comparePKvS0_
.cfi_startproc
# %bb.0:
movl (%rsi), %eax
subl (%rdi), %eax
retq
.Lfunc_end7:
.size _Z7comparePKvS0_, .Lfunc_end7-_Z7comparePKvS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB8_1
# %bb.2:
movq %rax, %rbx
leaq 48(%rsp), %r14
movq %r14, %rdi
movl $200, %esi
movq %rax, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB8_3
.p2align 4, 0x90
.LBB8_16: # in Loop: Header=BB8_3 Depth=1
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %r14
.LBB8_3: # =>This Inner Loop Header: Depth=1
movzbl (%r14), %edx
cmpl $32, %edx
je .LBB8_14
# %bb.4: # in Loop: Header=BB8_3 Depth=1
cmpl $10, %edx
je .LBB8_5
# %bb.15: # in Loop: Header=BB8_3 Depth=1
cmpl $2, %eax
je .LBB8_16
jmp .LBB8_17
.p2align 4, 0x90
.LBB8_14: # in Loop: Header=BB8_3 Depth=1
incl %eax
cmpl $2, %eax
je .LBB8_16
.LBB8_17: # in Loop: Header=BB8_3 Depth=1
jg .LBB8_5
# %bb.18: # in Loop: Header=BB8_3 Depth=1
incq %r14
jmp .LBB8_3
.LBB8_5: # %_Z8get_vertPc.exit
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq newgraph(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newgraph(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newgraph(%rip), %rax
movq (%rax), %rax
movl %r14d, (%rax)
movslq %r14d, %r15
leaq (,%r15,8), %rdi
callq malloc
movq newgraph(%rip), %rcx
movq (%rcx), %rcx
movq %rax, 8(%rcx)
testl %r15d, %r15d
jle .LBB8_8
# %bb.6: # %.lr.ph.preheader.i
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq $0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB8_7
.LBB8_8: # %_Z9new_graphi.exit
leaq 48(%rsp), %r14
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB8_23
# %bb.9: # %.lr.ph.preheader
movq %rsp, %r15
jmp .LBB8_10
.p2align 4, 0x90
.LBB8_22: # %_Z7get_dstPc.exit
# in Loop: Header=BB8_10 Depth=1
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %r12d, %edi
movl %eax, %esi
callq _Z7addEdgeii
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB8_23
.LBB8_10: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB8_11 Depth 2
# Child Loop BB8_20 Depth 2
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_11: # Parent Loop BB8_10 Depth=1
# => This Inner Loop Header: Depth=2
movzbl 48(%rsp,%rax), %ecx
cmpl $10, %ecx
je .LBB8_19
# %bb.12: # in Loop: Header=BB8_11 Depth=2
cmpl $32, %ecx
je .LBB8_19
# %bb.13: # in Loop: Header=BB8_11 Depth=2
movb %cl, (%rsp,%rax)
incq %rax
jmp .LBB8_11
.p2align 4, 0x90
.LBB8_19: # %_Z7get_srcPc.exit
# in Loop: Header=BB8_10 Depth=1
movl %eax, %eax
movb $0, (%rsp,%rax)
xorl %r13d, %r13d
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq %r14, %rax
xorl %ecx, %ecx
jmp .LBB8_20
.p2align 4, 0x90
.LBB8_27: # in Loop: Header=BB8_20 Depth=2
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %rax
.LBB8_20: # Parent Loop BB8_10 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%rax), %edx
cmpl $32, %edx
je .LBB8_25
# %bb.21: # in Loop: Header=BB8_20 Depth=2
cmpl $10, %edx
je .LBB8_22
# %bb.26: # in Loop: Header=BB8_20 Depth=2
cmpl $1, %r13d
je .LBB8_27
jmp .LBB8_28
.p2align 4, 0x90
.LBB8_25: # in Loop: Header=BB8_20 Depth=2
incl %r13d
cmpl $1, %r13d
je .LBB8_27
.LBB8_28: # in Loop: Header=BB8_20 Depth=2
jg .LBB8_22
# %bb.29: # in Loop: Header=BB8_20 Depth=2
incq %rax
jmp .LBB8_20
.LBB8_23: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movq newgraph(%rip), %rax
movq (%rax), %rax
movslq (%rax), %r14
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movq %rsp, %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq (,%r14,4), %rax
testq %r14, %r14
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r14
movl $.Lstr.1, %edi
callq puts@PLT
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq (%rsp), %rsi
movq 32(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movq newgraph(%rip), %rax
movq (%rax), %rdi
callq free
movq %r14, %rdi
callq free
jmp .LBB8_24
.LBB8_1:
movl $.L.str.2, %edi
movl $.L.str, %esi
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB8_24:
movl %ebx, %eax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5countPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5countPi,@object # @_Z5countPi
.section .rodata,"a",@progbits
.globl _Z5countPi
.p2align 3, 0x0
_Z5countPi:
.quad _Z20__device_stub__countPi
.size _Z5countPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "dblp-co-authors.txt"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Could not open file %s"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5countPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Graph Created...."
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Counting...."
.size .Lstr.1, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__countPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5countPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x4][0x8] ; /* 0x0100020000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x4][0xc] ; /* 0x0100030000037a02 */
/* 0x000fcc0000000f00 */
/*0040*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0070*/ LDG.E.64 R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x004ea2000c1e1b00 */
/*0080*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD.WIDE R4, R7, 0x8, R4 ; /* 0x0000000807047825 */
/* 0x004fcc00078e0204 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc600000001ff */
/*00c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x004eae000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0206 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5countPi
.globl _Z5countPi
.p2align 8
.type _Z5countPi,@function
_Z5countPi:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, newgraph@rel32@lo+4
s_addc_u32 s3, s3, newgraph@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
flat_load_b64 v[1:2], v[1:2] offset:8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v1, v5
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v6, vcc_lo
flat_load_b64 v[0:1], v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_load_b32 v2, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5countPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5countPi, .Lfunc_end0-_Z5countPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected newgraph
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5countPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0d79_00000000-6_p2a_authors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE1:
.size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8new_nodei
.type _Z8new_nodei, @function
_Z8new_nodei:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L16
.L11:
movl $1, %edx
movl $16, %esi
movq _ZL7newnode(%rip), %rdi
call cudaMallocManaged@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L17
.L12:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rdi
movl $-1, %ecx
movl $5, %edx
movl $16, %esi
call cudaMemAdvise@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L18
.L13:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L19
.L14:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rax
movq $0, 8(%rax)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L11
.L17:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L12
.L18:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L13
.L19:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L14
.cfi_endproc
.LFE2057:
.size _Z8new_nodei, .-_Z8new_nodei
.globl _Z9new_graphi
.type _Z9new_graphi, @function
_Z9new_graphi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L30
.L21:
movl $1, %edx
movl $16, %esi
movq _ZL8newgraph(%rip), %rdi
call cudaMallocManaged@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L31
.L22:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rdi
movl $-1, %ecx
movl $5, %edx
movl $16, %esi
call cudaMemAdvise@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L32
.L23:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movslq %ebx, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L33
.L24:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq %r12, 8(%rax)
testl %ebx, %ebx
jle .L20
movl $0, %ebx
jmp .L27
.L30:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L21
.L31:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L22
.L32:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L23
.L33:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L24
.L26:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq $0, (%rax,%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
je .L20
.L27:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L26
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L26
.L20:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9new_graphi, .-_Z9new_graphi
.globl _Z7addEdgeii
.type _Z7addEdgeii, @function
_Z7addEdgeii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movl %esi, %edi
call _Z8new_nodei
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L45
movslq %ebp, %rax
leaq 0(,%rax,8), %r13
movq _ZL8newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq (%rdx,%rax,8), %r12
.L36:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rdx
movq %r12, 8(%rdx)
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L46
movq (%rax), %r12
.L38:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq %r12, (%rax,%r13)
movl %ebp, %edi
call _Z8new_nodei
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L47
movslq %ebx, %rbx
leaq 0(,%rbx,8), %rbp
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq (%rax,%rbx,8), %rbx
.L40:
movq _ZL7newnode(%rip), %rax
movq (%rax), %rdx
movq %rbx, 8(%rdx)
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L48
movq (%rax), %rbx
.L42:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movq 8(%rax), %rax
movq %rbx, (%rax,%rbp)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movslq %ebp, %rdx
leaq 0(,%rdx,8), %r13
movq _ZL8newgraph(%rip), %rcx
movq (%rcx), %rcx
movq 8(%rcx), %rcx
movq (%rcx,%rdx,8), %r12
testb %al, %al
jne .L36
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L36
.L46:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movq _ZL7newnode(%rip), %rdx
movq (%rdx), %r12
testb %al, %al
jne .L38
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L38
.L47:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movslq %ebx, %rbx
leaq 0(,%rbx,8), %rbp
movq _ZL8newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq (%rdx,%rbx,8), %rbx
testb %al, %al
jne .L40
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L40
.L48:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movq _ZL7newnode(%rip), %rdx
movq (%rdx), %rbx
testb %al, %al
jne .L42
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L42
.cfi_endproc
.LFE2059:
.size _Z7addEdgeii, .-_Z7addEdgeii
.globl _Z8get_vertPc
.type _Z8get_vertPc, @function
_Z8get_vertPc:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl (%rdi), %eax
cmpb $10, %al
je .L57
addq $1, %rdi
movl $0, %ecx
movl $0, %edx
jmp .L54
.L62:
addl $1, %edx
cmpl $2, %edx
je .L55
jle .L53
.L50:
movslq %ecx, %rcx
movb $0, (%rsp,%rcx)
movq %rsp, %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movslq %ecx, %rdx
movb %al, (%rsp,%rdx)
addl $1, %ecx
movl $2, %edx
.L53:
addq $1, %rdi
movzbl -1(%rdi), %eax
cmpb $10, %al
je .L50
.L54:
cmpb $32, %al
je .L62
cmpl $2, %edx
jne .L53
jmp .L55
.L57:
movl $0, %ecx
jmp .L50
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8get_vertPc, .-_Z8get_vertPc
.globl _Z7get_srcPc
.type _Z7get_srcPc, @function
_Z7get_srcPc:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl (%rdi), %eax
cmpb $10, %al
je .L68
movl $1, %edx
leaq -1(%rsp), %rsi
jmp .L66
.L68:
movl $0, %edx
jmp .L64
.L65:
movb %al, (%rsi,%rdx)
leaq 1(%rdx), %rcx
movzbl -1(%rdi,%rcx), %eax
cmpb $10, %al
je .L64
movq %rcx, %rdx
.L66:
cmpb $32, %al
jne .L65
subl $1, %edx
.L64:
movslq %edx, %rdx
movb $0, (%rsp,%rdx)
movq %rsp, %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L72
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7get_srcPc, .-_Z7get_srcPc
.globl _Z7get_dstPc
.type _Z7get_dstPc, @function
_Z7get_dstPc:
.LFB2062:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl (%rdi), %eax
cmpb $10, %al
je .L81
addq $1, %rdi
movl $0, %ecx
movl $0, %edx
jmp .L78
.L86:
addl $1, %edx
cmpl $1, %edx
je .L79
jle .L77
.L74:
movslq %ecx, %rcx
movb $0, (%rsp,%rcx)
movq %rsp, %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L85
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movslq %ecx, %rdx
movb %al, (%rsp,%rdx)
addl $1, %ecx
movl $1, %edx
.L77:
addq $1, %rdi
movzbl -1(%rdi), %eax
cmpb $10, %al
je .L74
.L78:
cmpb $32, %al
je .L86
cmpl $1, %edx
jne .L77
jmp .L79
.L81:
movl $0, %ecx
jmp .L74
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z7get_dstPc, .-_Z7get_dstPc
.globl _Z7comparePKvS0_
.type _Z7comparePKvS0_, @function
_Z7comparePKvS0_:
.LFB2063:
.cfi_startproc
endbr64
movl (%rsi), %eax
subl (%rdi), %eax
ret
.cfi_endproc
.LFE2063:
.size _Z7comparePKvS0_, .-_Z7comparePKvS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "dblp-co-authors.txt"
.LC2:
.string "Could not open file %s"
.LC3:
.string "Graph Created....\n"
.LC4:
.string "Counting....\n"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $240, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L101
movq %rax, %r12
leaq 32(%rsp), %rbx
movq %rax, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rdi
call _Z8get_vertPc
movl %eax, %edi
call _Z9new_graphi
movq %rbx, %rbp
jmp .L91
.L101:
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L88
.L92:
movq %rbp, %rdi
call _Z7get_srcPc
movl %eax, %ebx
movq %rbp, %rdi
call _Z7get_dstPc
movl %eax, %esi
movl %ebx, %edi
call _Z7addEdgeii
.L91:
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbp, %rdi
call __fgets_chk@PLT
testq %rax, %rax
jne .L92
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L102
.L93:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rax
movl (%rax), %ebx
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebx, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L94
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L103
.L95:
movq _ZL8newgraph(%rip), %rax
movq (%rax), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L88:
movq 232(%rsp), %rdx
subq %fs:40, %rdx
jne .L104
addq $240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
call _ZL20__nv_init_managed_rtv
jmp .L93
.L94:
movq 232(%rsp), %rax
subq %fs:40, %rax
je .L97
call __stack_chk_fail@PLT
.L97:
call __cxa_throw_bad_array_new_length@PLT
.L103:
call _ZL20__nv_init_managed_rtv
jmp .L95
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size main, .-main
.globl _Z24__device_stub__Z5countPiPi
.type _Z24__device_stub__Z5countPiPi, @function
_Z24__device_stub__Z5countPiPi:
.LFB2089:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L109
.L105:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L110
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L105
.L110:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z24__device_stub__Z5countPiPi, .-_Z24__device_stub__Z5countPiPi
.globl _Z5countPi
.type _Z5countPi, @function
_Z5countPi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z5countPi, .-_Z5countPi
.section .rodata.str1.1
.LC5:
.string "_Z5countPi"
.LC6:
.string "newnode"
.LC7:
.string "newgraph"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5countPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7newnode(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8newgraph(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL8newgraph, @object
.size _ZL8newgraph, 8
_ZL8newgraph:
.zero 8
.align 8
.type _ZL7newnode, @object
.size _ZL7newnode, 8
_ZL7newnode:
.zero 8
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p2a_authors.hip"
.globl _Z8new_nodei # -- Begin function _Z8new_nodei
.p2align 4, 0x90
.type _Z8new_nodei,@function
_Z8new_nodei: # @_Z8new_nodei
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
movq newnode(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newnode(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newnode(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movq newnode(%rip), %rax
movq (%rax), %rax
movq $0, 8(%rax)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8new_nodei, .Lfunc_end0-_Z8new_nodei
.cfi_endproc
# -- End function
.globl _Z9new_graphi # -- Begin function _Z9new_graphi
.p2align 4, 0x90
.type _Z9new_graphi,@function
_Z9new_graphi: # @_Z9new_graphi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movq newgraph(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newgraph(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newgraph(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movslq %ebx, %r14
leaq (,%r14,8), %rdi
callq malloc
movq newgraph(%rip), %rcx
movq (%rcx), %rcx
movq %rax, 8(%rcx)
testl %r14d, %r14d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq $0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9new_graphi, .Lfunc_end1-_Z9new_graphi
.cfi_endproc
# -- End function
.globl _Z7addEdgeii # -- Begin function _Z7addEdgeii
.p2align 4, 0x90
.type _Z7addEdgeii,@function
_Z7addEdgeii: # @_Z7addEdgeii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movq newnode(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newnode(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newnode(%rip), %rax
movq (%rax), %rax
movl %ebx, (%rax)
movq newnode(%rip), %rax
movq (%rax), %rcx
movq $0, 8(%rcx)
movq newgraph(%rip), %rcx
movq (%rcx), %rdx
movq 8(%rdx), %rdx
movslq %ebp, %r14
movq (%rdx,%r14,8), %rdx
movq (%rax), %rsi
movq %rdx, 8(%rsi)
movq (%rax), %rax
movq (%rcx), %rcx
movq 8(%rcx), %rcx
movq %rax, (%rcx,%r14,8)
movq newnode(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newnode(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newnode(%rip), %rax
movq (%rax), %rax
movl %r14d, (%rax)
movq newnode(%rip), %rax
movq (%rax), %rcx
movq $0, 8(%rcx)
movq newgraph(%rip), %rcx
movq (%rcx), %rdx
movq 8(%rdx), %rdx
movslq %ebx, %rsi
movq (%rdx,%rsi,8), %rdx
movq (%rax), %rdi
movq %rdx, 8(%rdi)
movq (%rax), %rax
movq (%rcx), %rcx
movq 8(%rcx), %rcx
movq %rax, (%rcx,%rsi,8)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7addEdgeii, .Lfunc_end2-_Z7addEdgeii
.cfi_endproc
# -- End function
.globl _Z20__device_stub__countPi # -- Begin function _Z20__device_stub__countPi
.p2align 4, 0x90
.type _Z20__device_stub__countPi,@function
_Z20__device_stub__countPi: # @_Z20__device_stub__countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z20__device_stub__countPi, .Lfunc_end3-_Z20__device_stub__countPi
.cfi_endproc
# -- End function
.globl _Z8get_vertPc # -- Begin function _Z8get_vertPc
.p2align 4, 0x90
.type _Z8get_vertPc,@function
_Z8get_vertPc: # @_Z8get_vertPc
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_6: # in Loop: Header=BB4_1 Depth=1
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %rdi
.LBB4_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi), %edx
cmpl $32, %edx
je .LBB4_4
# %bb.2: # in Loop: Header=BB4_1 Depth=1
cmpl $10, %edx
je .LBB4_3
# %bb.5: # in Loop: Header=BB4_1 Depth=1
cmpl $2, %eax
je .LBB4_6
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_1 Depth=1
incl %eax
cmpl $2, %eax
je .LBB4_6
.LBB4_7: # in Loop: Header=BB4_1 Depth=1
jg .LBB4_3
# %bb.8: # in Loop: Header=BB4_1 Depth=1
incq %rdi
jmp .LBB4_1
.LBB4_3:
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cltq
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8get_vertPc, .Lfunc_end4-_Z8get_vertPc
.cfi_endproc
# -- End function
.globl _Z7get_srcPc # -- Begin function _Z7get_srcPc
.p2align 4, 0x90
.type _Z7get_srcPc,@function
_Z7get_srcPc: # @_Z7get_srcPc
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rax), %ecx
cmpl $10, %ecx
je .LBB5_4
# %bb.2: # in Loop: Header=BB5_1 Depth=1
cmpl $32, %ecx
je .LBB5_4
# %bb.3: # in Loop: Header=BB5_1 Depth=1
movb %cl, (%rsp,%rax)
incq %rax
jmp .LBB5_1
.LBB5_4:
movl %eax, %eax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z7get_srcPc, .Lfunc_end5-_Z7get_srcPc
.cfi_endproc
# -- End function
.globl _Z7get_dstPc # -- Begin function _Z7get_dstPc
.p2align 4, 0x90
.type _Z7get_dstPc,@function
_Z7get_dstPc: # @_Z7get_dstPc
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_1 Depth=1
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %rdi
.LBB6_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi), %edx
cmpl $32, %edx
je .LBB6_4
# %bb.2: # in Loop: Header=BB6_1 Depth=1
cmpl $10, %edx
je .LBB6_3
# %bb.5: # in Loop: Header=BB6_1 Depth=1
cmpl $1, %eax
je .LBB6_6
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_4: # in Loop: Header=BB6_1 Depth=1
incl %eax
cmpl $1, %eax
je .LBB6_6
.LBB6_7: # in Loop: Header=BB6_1 Depth=1
jg .LBB6_3
# %bb.8: # in Loop: Header=BB6_1 Depth=1
incq %rdi
jmp .LBB6_1
.LBB6_3:
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7get_dstPc, .Lfunc_end6-_Z7get_dstPc
.cfi_endproc
# -- End function
.globl _Z7comparePKvS0_ # -- Begin function _Z7comparePKvS0_
.p2align 4, 0x90
.type _Z7comparePKvS0_,@function
_Z7comparePKvS0_: # @_Z7comparePKvS0_
.cfi_startproc
# %bb.0:
movl (%rsi), %eax
subl (%rdi), %eax
retq
.Lfunc_end7:
.size _Z7comparePKvS0_, .Lfunc_end7-_Z7comparePKvS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB8_1
# %bb.2:
movq %rax, %rbx
leaq 48(%rsp), %r14
movq %r14, %rdi
movl $200, %esi
movq %rax, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB8_3
.p2align 4, 0x90
.LBB8_16: # in Loop: Header=BB8_3 Depth=1
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %r14
.LBB8_3: # =>This Inner Loop Header: Depth=1
movzbl (%r14), %edx
cmpl $32, %edx
je .LBB8_14
# %bb.4: # in Loop: Header=BB8_3 Depth=1
cmpl $10, %edx
je .LBB8_5
# %bb.15: # in Loop: Header=BB8_3 Depth=1
cmpl $2, %eax
je .LBB8_16
jmp .LBB8_17
.p2align 4, 0x90
.LBB8_14: # in Loop: Header=BB8_3 Depth=1
incl %eax
cmpl $2, %eax
je .LBB8_16
.LBB8_17: # in Loop: Header=BB8_3 Depth=1
jg .LBB8_5
# %bb.18: # in Loop: Header=BB8_3 Depth=1
incq %r14
jmp .LBB8_3
.LBB8_5: # %_Z8get_vertPc.exit
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %rsp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq newgraph(%rip), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq newgraph(%rip), %rax
movq (%rax), %rdi
movl $16, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
movq newgraph(%rip), %rax
movq (%rax), %rax
movl %r14d, (%rax)
movslq %r14d, %r15
leaq (,%r15,8), %rdi
callq malloc
movq newgraph(%rip), %rcx
movq (%rcx), %rcx
movq %rax, 8(%rcx)
testl %r15d, %r15d
jle .LBB8_8
# %bb.6: # %.lr.ph.preheader.i
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq newgraph(%rip), %rdx
movq (%rdx), %rdx
movq 8(%rdx), %rdx
movq $0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB8_7
.LBB8_8: # %_Z9new_graphi.exit
leaq 48(%rsp), %r14
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB8_23
# %bb.9: # %.lr.ph.preheader
movq %rsp, %r15
jmp .LBB8_10
.p2align 4, 0x90
.LBB8_22: # %_Z7get_dstPc.exit
# in Loop: Header=BB8_10 Depth=1
movslq %ecx, %rax
movb $0, (%rsp,%rax)
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %r12d, %edi
movl %eax, %esi
callq _Z7addEdgeii
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB8_23
.LBB8_10: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB8_11 Depth 2
# Child Loop BB8_20 Depth 2
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_11: # Parent Loop BB8_10 Depth=1
# => This Inner Loop Header: Depth=2
movzbl 48(%rsp,%rax), %ecx
cmpl $10, %ecx
je .LBB8_19
# %bb.12: # in Loop: Header=BB8_11 Depth=2
cmpl $32, %ecx
je .LBB8_19
# %bb.13: # in Loop: Header=BB8_11 Depth=2
movb %cl, (%rsp,%rax)
incq %rax
jmp .LBB8_11
.p2align 4, 0x90
.LBB8_19: # %_Z7get_srcPc.exit
# in Loop: Header=BB8_10 Depth=1
movl %eax, %eax
movb $0, (%rsp,%rax)
xorl %r13d, %r13d
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq %r14, %rax
xorl %ecx, %ecx
jmp .LBB8_20
.p2align 4, 0x90
.LBB8_27: # in Loop: Header=BB8_20 Depth=2
movslq %ecx, %rsi
movb %dl, (%rsp,%rsi)
incl %ecx
incq %rax
.LBB8_20: # Parent Loop BB8_10 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%rax), %edx
cmpl $32, %edx
je .LBB8_25
# %bb.21: # in Loop: Header=BB8_20 Depth=2
cmpl $10, %edx
je .LBB8_22
# %bb.26: # in Loop: Header=BB8_20 Depth=2
cmpl $1, %r13d
je .LBB8_27
jmp .LBB8_28
.p2align 4, 0x90
.LBB8_25: # in Loop: Header=BB8_20 Depth=2
incl %r13d
cmpl $1, %r13d
je .LBB8_27
.LBB8_28: # in Loop: Header=BB8_20 Depth=2
jg .LBB8_22
# %bb.29: # in Loop: Header=BB8_20 Depth=2
incq %rax
jmp .LBB8_20
.LBB8_23: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movq newgraph(%rip), %rax
movq (%rax), %rax
movslq (%rax), %r14
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movq %rsp, %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq (,%r14,4), %rax
testq %r14, %r14
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r14
movl $.Lstr.1, %edi
callq puts@PLT
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq (%rsp), %rsi
movq 32(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movq newgraph(%rip), %rax
movq (%rax), %rdi
callq free
movq %r14, %rdi
callq free
jmp .LBB8_24
.LBB8_1:
movl $.L.str.2, %edi
movl $.L.str, %esi
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB8_24:
movl %ebx, %eax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5countPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5countPi,@object # @_Z5countPi
.section .rodata,"a",@progbits
.globl _Z5countPi
.p2align 3, 0x0
_Z5countPi:
.quad _Z20__device_stub__countPi
.size _Z5countPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "dblp-co-authors.txt"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Could not open file %s"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5countPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Graph Created...."
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Counting...."
.size .Lstr.1, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__countPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5countPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Shared memory bandwidth benchmark
// contributed by Sebastian Keller
//
// Relevant nvprof metrics:
// nvprof -m shared_load_throughput,shared_store_throughput
#include <iostream>
#include <malloc.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define NTHREADS 256
#define NITER 4096
// length of the thread block swap chain (must be even)
#define SHARED_SEGMENTS 4
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
template <class T>
__device__ void swap(T* a, T* b)
{
T tmp;
tmp = *a;
*a = *b;
// +1 isn't needed to prevent code elimination by the
// compiler, but is added in case it gets smarter in
// a future version
*b = tmp + T{1};
}
template <class T>
__global__ void test_shmem(T* glob_mem)
{
__shared__ T smem[NTHREADS*SHARED_SEGMENTS];
int tid = threadIdx.x;
smem[tid] = T{0};
for (int i = 0; i < NITER; ++i)
{
// even shared segments
for (int j = 0; j < SHARED_SEGMENTS-1; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
// uneven shared segments
for (int j = 1; j < SHARED_SEGMENTS-2; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
}
glob_mem[blockIdx.x * blockDim.x + tid] = smem[tid];
}
template <class T>
double test_bw(long size)
{
T* buffer = (T*)malloc(size);
T* dev_buffer;
HANDLE_ERROR( cudaMalloc((void**)&dev_buffer, size) );
int nblocks = size / (NTHREADS * sizeof(T));
cudaEvent_t start, stop;
HANDLE_ERROR( cudaEventCreate(&start) );
HANDLE_ERROR( cudaEventCreate(&stop) );
HANDLE_ERROR( cudaEventRecord(start,0) );
test_shmem<<<nblocks, NTHREADS>>>(dev_buffer);
HANDLE_ERROR( cudaEventRecord(stop,0) );
HANDLE_ERROR( cudaEventSynchronize(stop) );
float gpu_time;
HANDLE_ERROR( cudaEventElapsedTime( &gpu_time, start, stop ) );
// convert to seconds
gpu_time /= 1000;
// 2 writes + 2 reads per swap
double nbytes = NITER * size * (SHARED_SEGMENTS-1) * 4;
cudaEventDestroy(start);
cudaEventDestroy(stop);
free(buffer);
cudaFree(dev_buffer);
return nbytes / gpu_time;
}
int main()
{
long size = 1024 * 1024 * 64; // 64 MB global buffer
// warmup
test_bw<int>(size);
std::cout << "Bandwidth(int) " << test_bw<int>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
std::cout << "Bandwidth(double) " << test_bw<double>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
} | code for sm_80
Function : _Z10test_shmemIdEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0050*/ STS.64 [R0.X8], RZ ; /* 0x000000ff00007388 */
/* 0x0011e20000008a00 */
/*0060*/ SHF.L.U32 R2, R0, 0x3, RZ ; /* 0x0000000300027819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD R2, R7, 0x8, R2 ; /* 0x0000000807027824 */
/* 0x000fca00078e0202 */
/*0080*/ LEA R3, R7, R2, 0x3 ; /* 0x0000000207037211 */
/* 0x000fc800078e18ff */
/*0090*/ LEA R4, R7, R3, 0x3 ; /* 0x0000000307047211 */
/* 0x001fe400078e18ff */
/*00a0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*00b0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fc60007ffe0ff */
/*00c0*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x002e620000000a00 */
/*00d0*/ ISETP.NE.AND P0, PT, R5, 0x1000, PT ; /* 0x000010000500780c */
/* 0x000fe20003f05270 */
/*00e0*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e240000000000 */
/*00f0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fea0000008a00 */
/*0100*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*0110*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*0120*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*0130*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*0140*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*0150*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0160*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0170*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0180*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0190*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*01a0*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*01b0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*01c0*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*01d0*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*01e0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*01f0*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*0200*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*0210*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*0220*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*0230*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*0240*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0250*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0260*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0270*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0280*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*0290*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*02a0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*02b0*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*02c0*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*02d0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*02e0*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*02f0*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*0300*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*0310*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*0320*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*0330*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0340*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0350*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0360*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0370*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*0380*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*0390*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*03a0*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*03b0*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*03c0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*03d0*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*03e0*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*03f0*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*0400*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*0410*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*0420*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0430*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0440*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0450*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0460*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*0470*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*0480*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0490*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*04a0*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*04b0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*04c0*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*04d0*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*04e0*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*04f0*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*0500*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*0510*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0520*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0530*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0540*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0550*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*0560*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*0570*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0580*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*0590*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*05a0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*05b0*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*05c0*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*05d0*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*05e0*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*05f0*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*0600*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0610*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0620*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0630*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0640*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*0650*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*0660*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0670*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*0680*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*0690*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*06a0*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*06b0*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*06c0*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*06d0*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*06e0*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*06f0*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*0700*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0710*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0720*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0730*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x002fe80000000a00 */
/*0740*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x001fe80000000a00 */
/*0750*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0760*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x000e620000000a00 */
/*0770*/ DADD R6, R6, 1 ; /* 0x3ff0000006067429 */
/* 0x001e060000000000 */
/*0780*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x002fe80000008a00 */
/*0790*/ STS.64 [R2], R6 ; /* 0x0000000602007388 */
/* 0x001fe80000000a00 */
/*07a0*/ LDS.64 R10, [R3] ; /* 0x00000000030a7984 */
/* 0x000e280000000a00 */
/*07b0*/ LDS.64 R12, [R4] ; /* 0x00000000040c7984 */
/* 0x000e620000000a00 */
/*07c0*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x001e060000000000 */
/*07d0*/ STS.64 [R3], R12 ; /* 0x0000000c03007388 */
/* 0x002fe80000000a00 */
/*07e0*/ STS.64 [R4], R10 ; /* 0x0000000a04007388 */
/* 0x001fe80000000a00 */
/*07f0*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e280000000a00 */
/*0800*/ LDS.64 R16, [R3] ; /* 0x0000000003107984 */
/* 0x000e620000000a00 */
/*0810*/ DADD R14, R14, 1 ; /* 0x3ff000000e0e7429 */
/* 0x001e060000000000 */
/*0820*/ STS.64 [R2], R16 ; /* 0x0000001002007388 */
/* 0x0023e80000000a00 */
/*0830*/ STS.64 [R3], R14 ; /* 0x0000000e03007388 */
/* 0x0013e20000000a00 */
/*0840*/ @P0 BRA 0xa0 ; /* 0xfffff85000000947 */
/* 0x000fea000383ffff */
/*0850*/ LDS.64 R2, [R0.X8] ; /* 0x0000000000027984 */
/* 0x002e220000008a00 */
/*0860*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fc60000000f00 */
/*0870*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e640000002500 */
/*0880*/ IMAD R4, R5, c[0x0][0x0], R0 ; /* 0x0000000005047a24 */
/* 0x002fc800078e0200 */
/*0890*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0007 */
/*08a0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10test_shmemIiEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0050*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0011e20000004800 */
/*0060*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD R2, R7, 0x4, R2 ; /* 0x0000000407027824 */
/* 0x000fc800078e0202 */
/*0080*/ IMAD R3, R7, 0x4, R2 ; /* 0x0000000407037824 */
/* 0x000fc800078e0202 */
/*0090*/ IMAD R4, R7, 0x4, R3 ; /* 0x0000000407047824 */
/* 0x001fe400078e0203 */
/*00a0*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x001e220000004800 */
/*00b0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fc60007ffe0ff */
/*00c0*/ LDS R7, [R2] ; /* 0x0000000002077984 */
/* 0x000e620000000800 */
/*00d0*/ ISETP.NE.AND P0, PT, R5, 0x1000, PT ; /* 0x000010000500780c */
/* 0x000fe40003f05270 */
/*00e0*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x001fe20007ffe0ff */
/*00f0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x002fe80000004800 */
/*0100*/ STS [R2], R9 ; /* 0x0000000902007388 */
/* 0x000fe80000000800 */
/*0110*/ LDS R6, [R3] ; /* 0x0000000003067984 */
/* 0x000e280000000800 */
/*0120*/ LDS R8, [R4] ; /* 0x0000000004087984 */
/* 0x000e620000000800 */
/*0130*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x001fc60007ffe0ff */
/*0140*/ STS [R3], R8 ; /* 0x0000000803007388 */
/* 0x002fe80000000800 */
/*0150*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0160*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0170*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0180*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0190*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*01a0*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*01b0*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*01c0*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*01d0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*01e0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*01f0*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*0200*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*0210*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*0220*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*0230*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*0240*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0250*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0260*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0270*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0280*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*0290*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*02a0*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*02b0*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*02c0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*02d0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*02e0*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*02f0*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*0300*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*0310*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*0320*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*0330*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0340*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0350*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0360*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0370*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*0380*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*0390*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*03a0*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*03b0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*03c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*03d0*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*03e0*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*03f0*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*0400*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*0410*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*0420*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0430*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0440*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0450*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0460*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*0470*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*0480*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0490*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*04a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*04b0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*04c0*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*04d0*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*04e0*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*04f0*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*0500*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*0510*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0520*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0530*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0540*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0550*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*0560*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*0570*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0580*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*0590*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*05a0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*05b0*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*05c0*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*05d0*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*05e0*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*05f0*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*0600*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0610*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0620*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0630*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0640*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*0650*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*0660*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0670*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*0680*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*0690*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*06a0*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*06b0*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*06c0*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*06d0*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*06e0*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*06f0*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*0700*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0710*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0720*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0730*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x002fe80000000800 */
/*0740*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000000800 */
/*0750*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0760*/ LDS R9, [R2] ; /* 0x0000000002097984 */
/* 0x000e620000000800 */
/*0770*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc60007ffe0ff */
/*0780*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x002fe80000004800 */
/*0790*/ STS [R2], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000000800 */
/*07a0*/ LDS R8, [R3] ; /* 0x0000000003087984 */
/* 0x000e280000000800 */
/*07b0*/ LDS R10, [R4] ; /* 0x00000000040a7984 */
/* 0x000e620000000800 */
/*07c0*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x001fc60007ffe0ff */
/*07d0*/ STS [R3], R10 ; /* 0x0000000a03007388 */
/* 0x002fe80000000800 */
/*07e0*/ STS [R4], R11 ; /* 0x0000000b04007388 */
/* 0x000fe80000000800 */
/*07f0*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x000e280000000800 */
/*0800*/ LDS R13, [R3] ; /* 0x00000000030d7984 */
/* 0x000e620000000800 */
/*0810*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fc60007ffe0ff */
/*0820*/ STS [R2], R13 ; /* 0x0000000d02007388 */
/* 0x0021e80000000800 */
/*0830*/ STS [R3], R6 ; /* 0x0000000603007388 */
/* 0x0001e20000000800 */
/*0840*/ @P0 BRA 0xa0 ; /* 0xfffff85000000947 */
/* 0x000fea000383ffff */
/*0850*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e620000004800 */
/*0860*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0870*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x001e240000002500 */
/*0880*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fc800078e0200 */
/*0890*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0007 */
/*08a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Shared memory bandwidth benchmark
// contributed by Sebastian Keller
//
// Relevant nvprof metrics:
// nvprof -m shared_load_throughput,shared_store_throughput
#include <iostream>
#include <malloc.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define NTHREADS 256
#define NITER 4096
// length of the thread block swap chain (must be even)
#define SHARED_SEGMENTS 4
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
template <class T>
__device__ void swap(T* a, T* b)
{
T tmp;
tmp = *a;
*a = *b;
// +1 isn't needed to prevent code elimination by the
// compiler, but is added in case it gets smarter in
// a future version
*b = tmp + T{1};
}
template <class T>
__global__ void test_shmem(T* glob_mem)
{
__shared__ T smem[NTHREADS*SHARED_SEGMENTS];
int tid = threadIdx.x;
smem[tid] = T{0};
for (int i = 0; i < NITER; ++i)
{
// even shared segments
for (int j = 0; j < SHARED_SEGMENTS-1; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
// uneven shared segments
for (int j = 1; j < SHARED_SEGMENTS-2; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
}
glob_mem[blockIdx.x * blockDim.x + tid] = smem[tid];
}
template <class T>
double test_bw(long size)
{
T* buffer = (T*)malloc(size);
T* dev_buffer;
HANDLE_ERROR( cudaMalloc((void**)&dev_buffer, size) );
int nblocks = size / (NTHREADS * sizeof(T));
cudaEvent_t start, stop;
HANDLE_ERROR( cudaEventCreate(&start) );
HANDLE_ERROR( cudaEventCreate(&stop) );
HANDLE_ERROR( cudaEventRecord(start,0) );
test_shmem<<<nblocks, NTHREADS>>>(dev_buffer);
HANDLE_ERROR( cudaEventRecord(stop,0) );
HANDLE_ERROR( cudaEventSynchronize(stop) );
float gpu_time;
HANDLE_ERROR( cudaEventElapsedTime( &gpu_time, start, stop ) );
// convert to seconds
gpu_time /= 1000;
// 2 writes + 2 reads per swap
double nbytes = NITER * size * (SHARED_SEGMENTS-1) * 4;
cudaEventDestroy(start);
cudaEventDestroy(stop);
free(buffer);
cudaFree(dev_buffer);
return nbytes / gpu_time;
}
int main()
{
long size = 1024 * 1024 * 64; // 64 MB global buffer
// warmup
test_bw<int>(size);
std::cout << "Bandwidth(int) " << test_bw<int>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
std::cout << "Bandwidth(double) " << test_bw<double>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
} | .file "tmpxft_0012a135_00000000-6_shmem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL35__device_stub__Z10test_shmemIiEvPT_Pi, @function
_ZL35__device_stub__Z10test_shmemIiEvPT_Pi:
.LFB3699:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10test_shmemIiEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _ZL35__device_stub__Z10test_shmemIiEvPT_Pi, .-_ZL35__device_stub__Z10test_shmemIiEvPT_Pi
.section .text._Z10test_shmemIiEvPT_,"axG",@progbits,_Z10test_shmemIiEvPT_,comdat
.weak _Z10test_shmemIiEvPT_
.type _Z10test_shmemIiEvPT_, @function
_Z10test_shmemIiEvPT_:
.LFB4010:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL35__device_stub__Z10test_shmemIiEvPT_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4010:
.size _Z10test_shmemIiEvPT_, .-_Z10test_shmemIiEvPT_
.text
.type _ZL35__device_stub__Z10test_shmemIdEvPT_Pd, @function
_ZL35__device_stub__Z10test_shmemIdEvPT_Pd:
.LFB3701:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10test_shmemIdEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _ZL35__device_stub__Z10test_shmemIdEvPT_Pd, .-_ZL35__device_stub__Z10test_shmemIdEvPT_Pd
.section .text._Z10test_shmemIdEvPT_,"axG",@progbits,_Z10test_shmemIdEvPT_,comdat
.weak _Z10test_shmemIdEvPT_
.type _Z10test_shmemIdEvPT_, @function
_Z10test_shmemIdEvPT_:
.LFB4012:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL35__device_stub__Z10test_shmemIdEvPT_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4012:
.size _Z10test_shmemIdEvPT_, .-_Z10test_shmemIdEvPT_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L22
ret
.L22:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "_Z10test_shmemIdEvPT_"
.LC2:
.string "_Z10test_shmemIiEvPT_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10test_shmemIdEvPT_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10test_shmemIiEvPT_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z7test_bwIiEdl.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/boegel/reframe/master/cscs-checks/microbenchmarks/shmem/src/shmem.cu"
.section .text._Z7test_bwIiEdl,"axG",@progbits,_Z7test_bwIiEdl,comdat
.weak _Z7test_bwIiEdl
.type _Z7test_bwIiEdl, @function
_Z7test_bwIiEdl:
.LFB4004:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $70, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $74, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $75, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $76, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq %rbx, %rax
shrq $10, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $80, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $81, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $83, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movss 44(%rsp), %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, 44(%rsp)
leaq (%rbx,%rbx,2), %rax
salq $14, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
pxor %xmm1, %xmm1
cvtss2sd 44(%rsp), %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsp), %rdi
call _ZL35__device_stub__Z10test_shmemIiEvPT_Pi
jmp .L28
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4004:
.size _Z7test_bwIiEdl, .-_Z7test_bwIiEdl
.section .text._Z7test_bwIdEdl,"axG",@progbits,_Z7test_bwIdEdl,comdat
.weak _Z7test_bwIdEdl
.type _Z7test_bwIdEdl, @function
_Z7test_bwIdEdl:
.LFB4009:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $70, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $74, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $75, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $76, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq %rbx, %rax
shrq $11, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $80, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $81, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $83, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movss 44(%rsp), %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, 44(%rsp)
leaq (%rbx,%rbx,2), %rax
salq $14, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
pxor %xmm1, %xmm1
cvtss2sd 44(%rsp), %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq 8(%rsp), %rdi
call _ZL35__device_stub__Z10test_shmemIdEvPT_Pd
jmp .L34
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4009:
.size _Z7test_bwIdEdl, .-_Z7test_bwIdEdl
.section .rodata.str1.1
.LC5:
.string "Bandwidth(int) "
.LC7:
.string " GB/s"
.LC8:
.string "Bandwidth(double) "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $67108864, %edi
call _Z7test_bwIiEdl
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $67108864, %edi
call _Z7test_bwIiEdl
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl $67108864, %edi
call _Z7test_bwIdEdl
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1062207488
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Shared memory bandwidth benchmark
// contributed by Sebastian Keller
//
// Relevant nvprof metrics:
// nvprof -m shared_load_throughput,shared_store_throughput
#include <iostream>
#include <malloc.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define NTHREADS 256
#define NITER 4096
// length of the thread block swap chain (must be even)
#define SHARED_SEGMENTS 4
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
template <class T>
__device__ void swap(T* a, T* b)
{
T tmp;
tmp = *a;
*a = *b;
// +1 isn't needed to prevent code elimination by the
// compiler, but is added in case it gets smarter in
// a future version
*b = tmp + T{1};
}
template <class T>
__global__ void test_shmem(T* glob_mem)
{
__shared__ T smem[NTHREADS*SHARED_SEGMENTS];
int tid = threadIdx.x;
smem[tid] = T{0};
for (int i = 0; i < NITER; ++i)
{
// even shared segments
for (int j = 0; j < SHARED_SEGMENTS-1; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
// uneven shared segments
for (int j = 1; j < SHARED_SEGMENTS-2; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
}
glob_mem[blockIdx.x * blockDim.x + tid] = smem[tid];
}
template <class T>
double test_bw(long size)
{
T* buffer = (T*)malloc(size);
T* dev_buffer;
HANDLE_ERROR( cudaMalloc((void**)&dev_buffer, size) );
int nblocks = size / (NTHREADS * sizeof(T));
cudaEvent_t start, stop;
HANDLE_ERROR( cudaEventCreate(&start) );
HANDLE_ERROR( cudaEventCreate(&stop) );
HANDLE_ERROR( cudaEventRecord(start,0) );
test_shmem<<<nblocks, NTHREADS>>>(dev_buffer);
HANDLE_ERROR( cudaEventRecord(stop,0) );
HANDLE_ERROR( cudaEventSynchronize(stop) );
float gpu_time;
HANDLE_ERROR( cudaEventElapsedTime( &gpu_time, start, stop ) );
// convert to seconds
gpu_time /= 1000;
// 2 writes + 2 reads per swap
double nbytes = NITER * size * (SHARED_SEGMENTS-1) * 4;
cudaEventDestroy(start);
cudaEventDestroy(stop);
free(buffer);
cudaFree(dev_buffer);
return nbytes / gpu_time;
}
int main()
{
long size = 1024 * 1024 * 64; // 64 MB global buffer
// warmup
test_bw<int>(size);
std::cout << "Bandwidth(int) " << test_bw<int>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
std::cout << "Bandwidth(double) " << test_bw<double>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
} | // Shared memory bandwidth benchmark
// contributed by Sebastian Keller
//
// Relevant nvprof metrics:
// nvprof -m shared_load_throughput,shared_store_throughput
#include <iostream>
#include <malloc.h>
#include <hip/hip_runtime.h>
#define NTHREADS 256
#define NITER 4096
// length of the thread block swap chain (must be even)
#define SHARED_SEGMENTS 4
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
template <class T>
__device__ void swap(T* a, T* b)
{
T tmp;
tmp = *a;
*a = *b;
// +1 isn't needed to prevent code elimination by the
// compiler, but is added in case it gets smarter in
// a future version
*b = tmp + T{1};
}
template <class T>
__global__ void test_shmem(T* glob_mem)
{
__shared__ T smem[NTHREADS*SHARED_SEGMENTS];
int tid = threadIdx.x;
smem[tid] = T{0};
for (int i = 0; i < NITER; ++i)
{
// even shared segments
for (int j = 0; j < SHARED_SEGMENTS-1; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
// uneven shared segments
for (int j = 1; j < SHARED_SEGMENTS-2; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
}
glob_mem[blockIdx.x * blockDim.x + tid] = smem[tid];
}
template <class T>
double test_bw(long size)
{
T* buffer = (T*)malloc(size);
T* dev_buffer;
HANDLE_ERROR( hipMalloc((void**)&dev_buffer, size) );
int nblocks = size / (NTHREADS * sizeof(T));
hipEvent_t start, stop;
HANDLE_ERROR( hipEventCreate(&start) );
HANDLE_ERROR( hipEventCreate(&stop) );
HANDLE_ERROR( hipEventRecord(start,0) );
test_shmem<<<nblocks, NTHREADS>>>(dev_buffer);
HANDLE_ERROR( hipEventRecord(stop,0) );
HANDLE_ERROR( hipEventSynchronize(stop) );
float gpu_time;
HANDLE_ERROR( hipEventElapsedTime( &gpu_time, start, stop ) );
// convert to seconds
gpu_time /= 1000;
// 2 writes + 2 reads per swap
double nbytes = NITER * size * (SHARED_SEGMENTS-1) * 4;
hipEventDestroy(start);
hipEventDestroy(stop);
free(buffer);
hipFree(dev_buffer);
return nbytes / gpu_time;
}
int main()
{
long size = 1024 * 1024 * 64; // 64 MB global buffer
// warmup
test_bw<int>(size);
std::cout << "Bandwidth(int) " << test_bw<int>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
std::cout << "Bandwidth(double) " << test_bw<double>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Shared memory bandwidth benchmark
// contributed by Sebastian Keller
//
// Relevant nvprof metrics:
// nvprof -m shared_load_throughput,shared_store_throughput
#include <iostream>
#include <malloc.h>
#include <hip/hip_runtime.h>
#define NTHREADS 256
#define NITER 4096
// length of the thread block swap chain (must be even)
#define SHARED_SEGMENTS 4
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
template <class T>
__device__ void swap(T* a, T* b)
{
T tmp;
tmp = *a;
*a = *b;
// +1 isn't needed to prevent code elimination by the
// compiler, but is added in case it gets smarter in
// a future version
*b = tmp + T{1};
}
template <class T>
__global__ void test_shmem(T* glob_mem)
{
__shared__ T smem[NTHREADS*SHARED_SEGMENTS];
int tid = threadIdx.x;
smem[tid] = T{0};
for (int i = 0; i < NITER; ++i)
{
// even shared segments
for (int j = 0; j < SHARED_SEGMENTS-1; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
// uneven shared segments
for (int j = 1; j < SHARED_SEGMENTS-2; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
}
glob_mem[blockIdx.x * blockDim.x + tid] = smem[tid];
}
template <class T>
double test_bw(long size)
{
T* buffer = (T*)malloc(size);
T* dev_buffer;
HANDLE_ERROR( hipMalloc((void**)&dev_buffer, size) );
int nblocks = size / (NTHREADS * sizeof(T));
hipEvent_t start, stop;
HANDLE_ERROR( hipEventCreate(&start) );
HANDLE_ERROR( hipEventCreate(&stop) );
HANDLE_ERROR( hipEventRecord(start,0) );
test_shmem<<<nblocks, NTHREADS>>>(dev_buffer);
HANDLE_ERROR( hipEventRecord(stop,0) );
HANDLE_ERROR( hipEventSynchronize(stop) );
float gpu_time;
HANDLE_ERROR( hipEventElapsedTime( &gpu_time, start, stop ) );
// convert to seconds
gpu_time /= 1000;
// 2 writes + 2 reads per swap
double nbytes = NITER * size * (SHARED_SEGMENTS-1) * 4;
hipEventDestroy(start);
hipEventDestroy(stop);
free(buffer);
hipFree(dev_buffer);
return nbytes / gpu_time;
}
int main()
{
long size = 1024 * 1024 * 64; // 64 MB global buffer
// warmup
test_bw<int>(size);
std::cout << "Bandwidth(int) " << test_bw<int>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
std::cout << "Bandwidth(double) " << test_bw<double>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10test_shmemIiEvPT_,"axG",@progbits,_Z10test_shmemIiEvPT_,comdat
.protected _Z10test_shmemIiEvPT_
.globl _Z10test_shmemIiEvPT_
.p2align 8
.type _Z10test_shmemIiEvPT_,@function
_Z10test_shmemIiEvPT_:
s_load_b32 s2, s[0:1], 0x14
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_mov_b32 s4, 0
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s2, s3, 2
s_lshl_b32 s3, s3, 3
v_add_nc_u32_e32 v2, s2, v1
v_add_nc_u32_e32 v3, s3, v1
.p2align 6
.LBB0_1:
v_mov_b32_e32 v4, v1
s_mov_b32 s5, 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, s2, v4
s_add_i32 s5, s5, -2
ds_load_b32 v6, v4
ds_load_b32 v7, v5
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v6, 1, v6
s_waitcnt lgkmcnt(0)
ds_store_b32 v4, v7
v_add_nc_u32_e32 v4, s3, v4
ds_store_b32 v5, v6
s_cbranch_scc1 .LBB0_2
ds_load_b32 v4, v2
ds_load_b32 v5, v3
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s4, 0x1000
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v4, 1, v4
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v5
ds_store_b32 v3, v4
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10test_shmemIiEvPT_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10test_shmemIiEvPT_,"axG",@progbits,_Z10test_shmemIiEvPT_,comdat
.Lfunc_end0:
.size _Z10test_shmemIiEvPT_, .Lfunc_end0-_Z10test_shmemIiEvPT_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z10test_shmemIdEvPT_,"axG",@progbits,_Z10test_shmemIdEvPT_,comdat
.protected _Z10test_shmemIdEvPT_
.globl _Z10test_shmemIdEvPT_
.p2align 8
.type _Z10test_shmemIdEvPT_,@function
_Z10test_shmemIdEvPT_:
s_load_b32 s2, s[0:1], 0x14
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v1, 3, v0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s2, s3, 3
s_lshl_b32 s3, s3, 4
v_dual_mov_b32 v5, v4 :: v_dual_add_nc_u32 v2, s2, v1
v_add_nc_u32_e32 v3, s3, v1
ds_store_b64 v1, v[4:5]
.p2align 6
.LBB1_1:
v_mov_b32_e32 v4, v1
s_mov_b32 s5, 2
.LBB1_2:
ds_load_b64 v[5:6], v4
v_add_nc_u32_e32 v9, s2, v4
s_add_i32 s5, s5, -2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
ds_load_b64 v[7:8], v9
s_waitcnt lgkmcnt(1)
v_add_f64 v[5:6], v[5:6], 1.0
s_waitcnt lgkmcnt(0)
ds_store_b64 v4, v[7:8]
v_add_nc_u32_e32 v4, s3, v4
ds_store_b64 v9, v[5:6]
s_cbranch_scc1 .LBB1_2
ds_load_b64 v[4:5], v2
ds_load_b64 v[6:7], v3
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s4, 0x1000
s_waitcnt lgkmcnt(1)
v_add_f64 v[4:5], v[4:5], 1.0
s_waitcnt lgkmcnt(0)
ds_store_b64 v2, v[6:7]
ds_store_b64 v3, v[4:5]
s_cbranch_scc0 .LBB1_1
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
ds_load_b64 v[0:1], v1
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10test_shmemIdEvPT_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10test_shmemIdEvPT_,"axG",@progbits,_Z10test_shmemIdEvPT_,comdat
.Lfunc_end1:
.size _Z10test_shmemIdEvPT_, .Lfunc_end1-_Z10test_shmemIdEvPT_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10test_shmemIiEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10test_shmemIiEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10test_shmemIdEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10test_shmemIdEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Shared memory bandwidth benchmark
// contributed by Sebastian Keller
//
// Relevant nvprof metrics:
// nvprof -m shared_load_throughput,shared_store_throughput
#include <iostream>
#include <malloc.h>
#include <hip/hip_runtime.h>
#define NTHREADS 256
#define NITER 4096
// length of the thread block swap chain (must be even)
#define SHARED_SEGMENTS 4
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
template <class T>
__device__ void swap(T* a, T* b)
{
T tmp;
tmp = *a;
*a = *b;
// +1 isn't needed to prevent code elimination by the
// compiler, but is added in case it gets smarter in
// a future version
*b = tmp + T{1};
}
template <class T>
__global__ void test_shmem(T* glob_mem)
{
__shared__ T smem[NTHREADS*SHARED_SEGMENTS];
int tid = threadIdx.x;
smem[tid] = T{0};
for (int i = 0; i < NITER; ++i)
{
// even shared segments
for (int j = 0; j < SHARED_SEGMENTS-1; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
// uneven shared segments
for (int j = 1; j < SHARED_SEGMENTS-2; j+=2)
swap(smem + tid + j*blockDim.x, smem + tid + (j+1)*blockDim.x);
}
glob_mem[blockIdx.x * blockDim.x + tid] = smem[tid];
}
template <class T>
double test_bw(long size)
{
T* buffer = (T*)malloc(size);
T* dev_buffer;
HANDLE_ERROR( hipMalloc((void**)&dev_buffer, size) );
int nblocks = size / (NTHREADS * sizeof(T));
hipEvent_t start, stop;
HANDLE_ERROR( hipEventCreate(&start) );
HANDLE_ERROR( hipEventCreate(&stop) );
HANDLE_ERROR( hipEventRecord(start,0) );
test_shmem<<<nblocks, NTHREADS>>>(dev_buffer);
HANDLE_ERROR( hipEventRecord(stop,0) );
HANDLE_ERROR( hipEventSynchronize(stop) );
float gpu_time;
HANDLE_ERROR( hipEventElapsedTime( &gpu_time, start, stop ) );
// convert to seconds
gpu_time /= 1000;
// 2 writes + 2 reads per swap
double nbytes = NITER * size * (SHARED_SEGMENTS-1) * 4;
hipEventDestroy(start);
hipEventDestroy(stop);
free(buffer);
hipFree(dev_buffer);
return nbytes / gpu_time;
}
int main()
{
long size = 1024 * 1024 * 64; // 64 MB global buffer
// warmup
test_bw<int>(size);
std::cout << "Bandwidth(int) " << test_bw<int>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
std::cout << "Bandwidth(double) " << test_bw<double>(size) / 1024 / 1024 / 1024 << " GB/s" << std::endl;
} | .text
.file "shmem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $67108864, %edi # imm = 0x4000000
callq _Z7test_bwIiEdl
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $67108864, %edi # imm = 0x4000000
callq _Z7test_bwIiEdl
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB0_4
.LBB0_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $67108864, %edi # imm = 0x4000000
callq _Z7test_bwIdEdl
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i4
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit7
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7test_bwIiEdl
.LCPI1_0:
.long 0x447a0000 # float 1000
.section .text._Z7test_bwIiEdl,"axG",@progbits,_Z7test_bwIiEdl,comdat
.weak _Z7test_bwIiEdl
.p2align 4, 0x90
.type _Z7test_bwIiEdl,@function
_Z7test_bwIiEdl: # @_Z7test_bwIiEdl
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit9
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit11
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_ZL11HandleError10hipError_tPKci.exit13
movq %rbx, %rax
shrq $10, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10test_shmemIiEvPT_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit15
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit17
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_ZL11HandleError10hipError_tPKci.exit19
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 16(%rsp)
shlq $14, %rbx
leaq (%rbx,%rbx,2), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipFree
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 128
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $70, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $74, %ecx
jmp .LBB1_2
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $75, %ecx
jmp .LBB1_2
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $76, %ecx
jmp .LBB1_2
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $80, %ecx
jmp .LBB1_2
.LBB1_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $81, %ecx
jmp .LBB1_2
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $83, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z7test_bwIiEdl, .Lfunc_end1-_Z7test_bwIiEdl
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7test_bwIdEdl
.LCPI2_0:
.long 0x447a0000 # float 1000
.section .text._Z7test_bwIdEdl,"axG",@progbits,_Z7test_bwIdEdl,comdat
.weak _Z7test_bwIdEdl
.p2align 4, 0x90
.type _Z7test_bwIdEdl,@function
_Z7test_bwIdEdl: # @_Z7test_bwIdEdl
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit9
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit11
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_ZL11HandleError10hipError_tPKci.exit13
movq %rbx, %rax
shrq $11, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10test_shmemIdEvPT_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit15
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit17
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_ZL11HandleError10hipError_tPKci.exit19
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
movss %xmm0, 16(%rsp)
shlq $14, %rbx
leaq (%rbx,%rbx,2), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipFree
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 128
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $70, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $74, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $75, %ecx
jmp .LBB2_2
.LBB2_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $76, %ecx
jmp .LBB2_2
.LBB2_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $80, %ecx
jmp .LBB2_2
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $81, %ecx
jmp .LBB2_2
.LBB2_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $83, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z7test_bwIdEdl, .Lfunc_end2-_Z7test_bwIdEdl
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__test_shmemIiEvPT_,"axG",@progbits,_Z25__device_stub__test_shmemIiEvPT_,comdat
.weak _Z25__device_stub__test_shmemIiEvPT_ # -- Begin function _Z25__device_stub__test_shmemIiEvPT_
.p2align 4, 0x90
.type _Z25__device_stub__test_shmemIiEvPT_,@function
_Z25__device_stub__test_shmemIiEvPT_: # @_Z25__device_stub__test_shmemIiEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10test_shmemIiEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__test_shmemIiEvPT_, .Lfunc_end3-_Z25__device_stub__test_shmemIiEvPT_
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__test_shmemIdEvPT_,"axG",@progbits,_Z25__device_stub__test_shmemIdEvPT_,comdat
.weak _Z25__device_stub__test_shmemIdEvPT_ # -- Begin function _Z25__device_stub__test_shmemIdEvPT_
.p2align 4, 0x90
.type _Z25__device_stub__test_shmemIdEvPT_,@function
_Z25__device_stub__test_shmemIdEvPT_: # @_Z25__device_stub__test_shmemIdEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10test_shmemIdEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z25__device_stub__test_shmemIdEvPT_, .Lfunc_end4-_Z25__device_stub__test_shmemIdEvPT_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10test_shmemIiEvPT_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10test_shmemIdEvPT_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bandwidth(int) "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " GB/s"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Bandwidth(double) "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/boegel/reframe/master/cscs-checks/microbenchmarks/shmem/src/shmem.hip"
.size .L.str.3, 127
.type _Z10test_shmemIiEvPT_,@object # @_Z10test_shmemIiEvPT_
.section .rodata._Z10test_shmemIiEvPT_,"aG",@progbits,_Z10test_shmemIiEvPT_,comdat
.weak _Z10test_shmemIiEvPT_
.p2align 3, 0x0
_Z10test_shmemIiEvPT_:
.quad _Z25__device_stub__test_shmemIiEvPT_
.size _Z10test_shmemIiEvPT_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type _Z10test_shmemIdEvPT_,@object # @_Z10test_shmemIdEvPT_
.section .rodata._Z10test_shmemIdEvPT_,"aG",@progbits,_Z10test_shmemIdEvPT_,comdat
.weak _Z10test_shmemIdEvPT_
.p2align 3, 0x0
_Z10test_shmemIdEvPT_:
.quad _Z25__device_stub__test_shmemIdEvPT_
.size _Z10test_shmemIdEvPT_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10test_shmemIiEvPT_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10test_shmemIdEvPT_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__test_shmemIiEvPT_
.addrsig_sym _Z25__device_stub__test_shmemIdEvPT_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10test_shmemIiEvPT_
.addrsig_sym _Z10test_shmemIdEvPT_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012a135_00000000-6_shmem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL35__device_stub__Z10test_shmemIiEvPT_Pi, @function
_ZL35__device_stub__Z10test_shmemIiEvPT_Pi:
.LFB3699:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10test_shmemIiEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _ZL35__device_stub__Z10test_shmemIiEvPT_Pi, .-_ZL35__device_stub__Z10test_shmemIiEvPT_Pi
.section .text._Z10test_shmemIiEvPT_,"axG",@progbits,_Z10test_shmemIiEvPT_,comdat
.weak _Z10test_shmemIiEvPT_
.type _Z10test_shmemIiEvPT_, @function
_Z10test_shmemIiEvPT_:
.LFB4010:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL35__device_stub__Z10test_shmemIiEvPT_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4010:
.size _Z10test_shmemIiEvPT_, .-_Z10test_shmemIiEvPT_
.text
.type _ZL35__device_stub__Z10test_shmemIdEvPT_Pd, @function
_ZL35__device_stub__Z10test_shmemIdEvPT_Pd:
.LFB3701:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10test_shmemIdEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _ZL35__device_stub__Z10test_shmemIdEvPT_Pd, .-_ZL35__device_stub__Z10test_shmemIdEvPT_Pd
.section .text._Z10test_shmemIdEvPT_,"axG",@progbits,_Z10test_shmemIdEvPT_,comdat
.weak _Z10test_shmemIdEvPT_
.type _Z10test_shmemIdEvPT_, @function
_Z10test_shmemIdEvPT_:
.LFB4012:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL35__device_stub__Z10test_shmemIdEvPT_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4012:
.size _Z10test_shmemIdEvPT_, .-_Z10test_shmemIdEvPT_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L22
ret
.L22:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "_Z10test_shmemIdEvPT_"
.LC2:
.string "_Z10test_shmemIiEvPT_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10test_shmemIdEvPT_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10test_shmemIiEvPT_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z7test_bwIiEdl.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/boegel/reframe/master/cscs-checks/microbenchmarks/shmem/src/shmem.cu"
.section .text._Z7test_bwIiEdl,"axG",@progbits,_Z7test_bwIiEdl,comdat
.weak _Z7test_bwIiEdl
.type _Z7test_bwIiEdl, @function
_Z7test_bwIiEdl:
.LFB4004:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $70, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $74, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $75, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $76, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq %rbx, %rax
shrq $10, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $80, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $81, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $83, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movss 44(%rsp), %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, 44(%rsp)
leaq (%rbx,%rbx,2), %rax
salq $14, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
pxor %xmm1, %xmm1
cvtss2sd 44(%rsp), %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsp), %rdi
call _ZL35__device_stub__Z10test_shmemIiEvPT_Pi
jmp .L28
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4004:
.size _Z7test_bwIiEdl, .-_Z7test_bwIiEdl
.section .text._Z7test_bwIdEdl,"axG",@progbits,_Z7test_bwIdEdl,comdat
.weak _Z7test_bwIdEdl
.type _Z7test_bwIdEdl, @function
_Z7test_bwIdEdl:
.LFB4009:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $70, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $74, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $75, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $76, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq %rbx, %rax
shrq $11, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $80, %edx
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $81, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $83, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movss 44(%rsp), %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, 44(%rsp)
leaq (%rbx,%rbx,2), %rax
salq $14, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
pxor %xmm1, %xmm1
cvtss2sd 44(%rsp), %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq 8(%rsp), %rdi
call _ZL35__device_stub__Z10test_shmemIdEvPT_Pd
jmp .L34
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4009:
.size _Z7test_bwIdEdl, .-_Z7test_bwIdEdl
.section .rodata.str1.1
.LC5:
.string "Bandwidth(int) "
.LC7:
.string " GB/s"
.LC8:
.string "Bandwidth(double) "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $67108864, %edi
call _Z7test_bwIiEdl
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $67108864, %edi
call _Z7test_bwIiEdl
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl $67108864, %edi
call _Z7test_bwIdEdl
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
mulsd .LC6(%rip), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1062207488
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shmem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $67108864, %edi # imm = 0x4000000
callq _Z7test_bwIiEdl
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $67108864, %edi # imm = 0x4000000
callq _Z7test_bwIiEdl
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB0_4
.LBB0_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $67108864, %edi # imm = 0x4000000
callq _Z7test_bwIdEdl
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i4
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit7
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7test_bwIiEdl
.LCPI1_0:
.long 0x447a0000 # float 1000
.section .text._Z7test_bwIiEdl,"axG",@progbits,_Z7test_bwIiEdl,comdat
.weak _Z7test_bwIiEdl
.p2align 4, 0x90
.type _Z7test_bwIiEdl,@function
_Z7test_bwIiEdl: # @_Z7test_bwIiEdl
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit9
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit11
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_ZL11HandleError10hipError_tPKci.exit13
movq %rbx, %rax
shrq $10, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10test_shmemIiEvPT_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit15
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit17
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_ZL11HandleError10hipError_tPKci.exit19
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 16(%rsp)
shlq $14, %rbx
leaq (%rbx,%rbx,2), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipFree
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 128
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $70, %ecx
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $74, %ecx
jmp .LBB1_2
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $75, %ecx
jmp .LBB1_2
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $76, %ecx
jmp .LBB1_2
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $80, %ecx
jmp .LBB1_2
.LBB1_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $81, %ecx
jmp .LBB1_2
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $83, %ecx
.LBB1_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z7test_bwIiEdl, .Lfunc_end1-_Z7test_bwIiEdl
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7test_bwIdEdl
.LCPI2_0:
.long 0x447a0000 # float 1000
.section .text._Z7test_bwIdEdl,"axG",@progbits,_Z7test_bwIdEdl,comdat
.weak _Z7test_bwIdEdl
.p2align 4, 0x90
.type _Z7test_bwIdEdl,@function
_Z7test_bwIdEdl: # @_Z7test_bwIdEdl
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit9
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit11
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_ZL11HandleError10hipError_tPKci.exit13
movq %rbx, %rax
shrq $11, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10test_shmemIdEvPT_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit15
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit17
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_ZL11HandleError10hipError_tPKci.exit19
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
movss %xmm0, 16(%rsp)
shlq $14, %rbx
leaq (%rbx,%rbx,2), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipFree
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 128
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $70, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $74, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $75, %ecx
jmp .LBB2_2
.LBB2_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $76, %ecx
jmp .LBB2_2
.LBB2_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $80, %ecx
jmp .LBB2_2
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $81, %ecx
jmp .LBB2_2
.LBB2_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $83, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z7test_bwIdEdl, .Lfunc_end2-_Z7test_bwIdEdl
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__test_shmemIiEvPT_,"axG",@progbits,_Z25__device_stub__test_shmemIiEvPT_,comdat
.weak _Z25__device_stub__test_shmemIiEvPT_ # -- Begin function _Z25__device_stub__test_shmemIiEvPT_
.p2align 4, 0x90
.type _Z25__device_stub__test_shmemIiEvPT_,@function
_Z25__device_stub__test_shmemIiEvPT_: # @_Z25__device_stub__test_shmemIiEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10test_shmemIiEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__test_shmemIiEvPT_, .Lfunc_end3-_Z25__device_stub__test_shmemIiEvPT_
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__test_shmemIdEvPT_,"axG",@progbits,_Z25__device_stub__test_shmemIdEvPT_,comdat
.weak _Z25__device_stub__test_shmemIdEvPT_ # -- Begin function _Z25__device_stub__test_shmemIdEvPT_
.p2align 4, 0x90
.type _Z25__device_stub__test_shmemIdEvPT_,@function
_Z25__device_stub__test_shmemIdEvPT_: # @_Z25__device_stub__test_shmemIdEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10test_shmemIdEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z25__device_stub__test_shmemIdEvPT_, .Lfunc_end4-_Z25__device_stub__test_shmemIdEvPT_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10test_shmemIiEvPT_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10test_shmemIdEvPT_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bandwidth(int) "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " GB/s"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Bandwidth(double) "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/boegel/reframe/master/cscs-checks/microbenchmarks/shmem/src/shmem.hip"
.size .L.str.3, 127
.type _Z10test_shmemIiEvPT_,@object # @_Z10test_shmemIiEvPT_
.section .rodata._Z10test_shmemIiEvPT_,"aG",@progbits,_Z10test_shmemIiEvPT_,comdat
.weak _Z10test_shmemIiEvPT_
.p2align 3, 0x0
_Z10test_shmemIiEvPT_:
.quad _Z25__device_stub__test_shmemIiEvPT_
.size _Z10test_shmemIiEvPT_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type _Z10test_shmemIdEvPT_,@object # @_Z10test_shmemIdEvPT_
.section .rodata._Z10test_shmemIdEvPT_,"aG",@progbits,_Z10test_shmemIdEvPT_,comdat
.weak _Z10test_shmemIdEvPT_
.p2align 3, 0x0
_Z10test_shmemIdEvPT_:
.quad _Z25__device_stub__test_shmemIdEvPT_
.size _Z10test_shmemIdEvPT_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10test_shmemIiEvPT_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10test_shmemIdEvPT_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__test_shmemIiEvPT_
.addrsig_sym _Z25__device_stub__test_shmemIdEvPT_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10test_shmemIiEvPT_
.addrsig_sym _Z10test_shmemIdEvPT_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by binhpht on 27.3.2021.
//
#include <stdio.h>
#include "iostream"
#include "square.cuh"
__global__ void square (float * d_out, float * d_in) {
// int idx = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
}
void call_square (int thread_num, float * d_out, float * d_in) {
::square<<<8,8>>>(d_out, d_in);
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by binhpht on 27.3.2021.
//
#include <stdio.h>
#include "iostream"
#include "square.cuh"
__global__ void square (float * d_out, float * d_in) {
// int idx = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
}
void call_square (int thread_num, float * d_out, float * d_in) {
::square<<<8,8>>>(d_out, d_in);
} | .file "tmpxft_0000414e_00000000-6_square.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6squarePfS_, .-_Z6squarePfS_
.globl _Z11call_squareiPfS_
.type _Z11call_squareiPfS_, @function
_Z11call_squareiPfS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq %rdx, %rbp
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L11
.cfi_endproc
.LFE3669:
.size _Z11call_squareiPfS_, .-_Z11call_squareiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by binhpht on 27.3.2021.
//
#include <stdio.h>
#include "iostream"
#include "square.cuh"
__global__ void square (float * d_out, float * d_in) {
// int idx = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
}
void call_square (int thread_num, float * d_out, float * d_in) {
::square<<<8,8>>>(d_out, d_in);
} | //
// Created by binhpht on 27.3.2021.
//
#ifndef CUDA_CS344_SQUARE_CUH
#define CUDA_CS344_SQUARE_CUH
__global__ void square (float * d_out, float * d_in);
void call_square (int thread_num, float * d_out, float * d_in) ;
#endif//CUDA_CS344_SQUARE_CUH |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by binhpht on 27.3.2021.
//
#ifndef CUDA_CS344_SQUARE_CUH
#define CUDA_CS344_SQUARE_CUH
__global__ void square (float * d_out, float * d_in);
void call_square (int thread_num, float * d_out, float * d_in) ;
#endif//CUDA_CS344_SQUARE_CUH | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by binhpht on 27.3.2021.
//
#ifndef CUDA_CS344_SQUARE_CUH
#define CUDA_CS344_SQUARE_CUH
__global__ void square (float * d_out, float * d_in);
void call_square (int thread_num, float * d_out, float * d_in) ;
#endif//CUDA_CS344_SQUARE_CUH | .text
.file "square.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000414e_00000000-6_square.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6squarePfS_, .-_Z6squarePfS_
.globl _Z11call_squareiPfS_
.type _Z11call_squareiPfS_, @function
_Z11call_squareiPfS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq %rdx, %rbp
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L11
.cfi_endproc
.LFE3669:
.size _Z11call_squareiPfS_, .-_Z11call_squareiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define DEBUG
#ifdef DEBUG
#include <stdio.h>
#endif
#include <time.h> // for rand()
#define BLOCKDIM 8
#define WIDTH 10
#define HEIGHT 10
#define RADIUS BLOCKDIM-2
__global__ void shared1D(int * in, int * out, int radius, int n) {
extern __shared__ int smem[];
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int xIndex = tx + bx*dx;
int index = xIndex;
#define SMEM(txOffset) smem[tx + txOffset]
if (xIndex < n)
SMEM(radius) = in[index];
else
SMEM(radius) = in[n - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0) = in[index - radius];
} else {
SMEM(0) = in[0];
}
if (xIndex + dx < n) {
SMEM(dx + radius) = in[index + dx];
} else {
SMEM(dx + radius) = in[n - 1];
}
}
__syncthreads();
if (xIndex >= n)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1);
#undef SMEM
}
__global__ void horizShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (yIndex >= height)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width)
SMEM(radius, 0) = in[index];
else
SMEM(radius, 0) = in[(yIndex+1)*width - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius];
} else {
SMEM(0, 0) = in[yIndex*width];
}
if (xIndex + dx < width) {
SMEM(dx + radius, 0) = in[index + dx];
} else {
SMEM(dx + radius, 0) = in[(yIndex + 1)*width - 1];
}
}
__syncthreads();
if (xIndex >= width)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1, 0);
#undef SMEM
}
__global__ void vertShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (xIndex >= width)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*dx]
if (yIndex < height)
SMEM(0, radius) = in[index];
else
SMEM(0, radius) = in[(height-1)*width + xIndex];
if (ty < radius) {
if (yIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius*width];
} else {
SMEM(0, 0) = in[xIndex];
}
if (yIndex + dy < height) {
SMEM(0, dy + radius) = in[index + dy*width];
} else {
SMEM(0, dy + radius) = in[(height - 1)*width + xIndex];
}
}
__syncthreads();
if (yIndex >= height)
return ;
ty += radius;
out[index] = SMEM(0, RADIUS-1);
#undef SMEM
}
__global__ void shared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width && yIndex < height) {
SMEM(radius, radius) = in[index];
} else if (xIndex < width) {
SMEM(radius, radius) = in[(height - 1)*width + xIndex];
} else if (yIndex < height) {
SMEM(radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(radius, radius) = in[height*width - 1];
}
if (tx < radius) {
if (xIndex - radius >= 0) {
if (yIndex < height) {
SMEM(0, radius) = in[index - radius];
} else {
SMEM(0, radius) = in[(height - 1)*width + xIndex - radius];
}
} else {
if (yIndex < height) {
SMEM(0, radius) = in[yIndex*width];
} else {
SMEM(0, radius) = in[(height - 1)*width];
}
}
if (xIndex + dx < width) {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[index + dx];
} else {
SMEM(dx+radius, radius) = in[(height - 1)*width + xIndex + dx];
}
} else {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(dx+radius, radius) = in[height*width - 1];
}
}
}
if (ty < radius) {
if (yIndex - radius >= 0) {
if (xIndex < width) {
SMEM(radius, 0) = in[index - width*radius];
} else {
SMEM(radius, 0) = in[(yIndex - radius)*width];
}
} else {
if (xIndex < width) {
SMEM(radius, 0) = in[xIndex];
} else {
SMEM(radius, 0) = in[0];
}
}
if (yIndex + dy < width) {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[index + dy*width];
} else {
SMEM(radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
}
} else {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[(height - 1)*width + xIndex];
} else {
SMEM(radius, dy + radius) = in[height*width - 1];
}
}
}
if (tx < radius && ty < radius) {
// top left corner
if (xIndex - radius >= 0) {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[index - radius*(width + 1)];
else
SMEM(0, 0) = in[xIndex - radius];
} else {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[(yIndex - radius)*width];
else
SMEM(0, 0) = in[0];
}
// bottom left corner
if (xIndex - radius >= 0) {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[index - radius + dx*width];
else
SMEM(0, dy + radius) = in[xIndex - radius + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[(yIndex + dy)*width];
else
SMEM(0, dy + radius) = in[(height - 1)*width];
}
// top right corner
if (xIndex + dx < width) {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[index + dx - radius*width];
else
SMEM(dx + radius, 0) = in[xIndex + dx];
} else {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[(yIndex - radius + 1)*width - 1];
else
SMEM(dx + radius, 0) = in[width - 1];
}
// bottom right corner
if (xIndex + dx < width) {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[index + dy*(width + 1)];
else
SMEM(dx + radius, dy + radius) = in[xIndex + dx + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
else
SMEM(dx + radius, dy + radius) = in[height*width - 1];
}
SMEM(0, 0) = 11;
SMEM(dx + radius, 0) = 33;
SMEM(0, dy + radius) = 88;
SMEM(dx + radius, dy + radius) = 99;
}
if (xIndex >= width || yIndex >= height)
return ;
tx += radius;
ty += radius;
out[index] = SMEM(4, 4);
#undef SMEM
}
__host__ void init(int * list, int width, int height) {
int ii, jj;
for (ii = 0; ii < height; ii++) {
for (jj = 0; jj < width; jj++) {
list[ii*width + jj] = ii;
}
}
}
int main( ) {
int * in, * d_in;
int * out, * d_out;
int width, height, radius;
int sharedMemSize;
#ifdef DEBUG
int ii, jj;
#endif
width = WIDTH;
height = HEIGHT;
radius = RADIUS;
in = (int *) malloc(width*height*sizeof(int));
out = (int *) malloc(width*height*sizeof(int));
init(in, width, height);
cudaMalloc((void **) &d_in, width*height*sizeof(int));
cudaMalloc((void **) &d_out, width*height*sizeof(int));
cudaMemcpy(d_in, in, width*height*sizeof(int), cudaMemcpyHostToDevice);
dim3 blockDim(BLOCKDIM,BLOCKDIM);
dim3 gridDim((width + BLOCKDIM - 1)/BLOCKDIM, (height + BLOCKDIM -1)/BLOCKDIM);
sharedMemSize = BLOCKDIM*(BLOCKDIM+2*RADIUS)*sizeof(int)*sizeof(int);
shared2D<<<gridDim, blockDim, sharedMemSize>>>(d_in, d_out, radius, width, height);
cudaMemcpy(out, d_out, width*height*sizeof(int), cudaMemcpyDeviceToHost);
#ifdef NDEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
if (out[jj*width + ii] != in[jj*width + (ii + RADIUS)%WIDTH]) {
printf("foo");
}
}
}
#endif
#ifdef DEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
printf("%d ", out[jj*width + ii]);
}
printf("\n");
}
#endif
free(in);
free(out);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | .file "tmpxft_000ca88a_00000000-6_sharedMemory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPiii
.type _Z4initPiii, @function
_Z4initPiii:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movl $0, %r9d
movl $0, %ecx
movslq %esi, %r10
jmp .L5
.L7:
movslq %r9d, %r8
leaq (%rdi,%r8,4), %rax
addq %r10, %r8
leaq (%rdi,%r8,4), %r8
.L6:
movl %ecx, (%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L6
.L8:
addl $1, %ecx
addl %esi, %r9d
cmpl %ecx, %edx
je .L3
.L5:
testl %esi, %esi
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z4initPiii, .-_Z4initPiii
.globl _Z31__device_stub__Z8shared1DPiS_iiPiS_ii
.type _Z31__device_stub__Z8shared1DPiS_iiPiS_ii, @function
_Z31__device_stub__Z8shared1DPiS_iiPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8shared1DPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8shared1DPiS_iiPiS_ii, .-_Z31__device_stub__Z8shared1DPiS_iiPiS_ii
.globl _Z8shared1DPiS_ii
.type _Z8shared1DPiS_ii, @function
_Z8shared1DPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8shared1DPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8shared1DPiS_ii, .-_Z8shared1DPiS_ii
.globl _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
.type _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii, @function
_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13horizShared2DPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii, .-_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
.globl _Z13horizShared2DPiS_iii
.type _Z13horizShared2DPiS_iii, @function
_Z13horizShared2DPiS_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13horizShared2DPiS_iii, .-_Z13horizShared2DPiS_iii
.globl _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
.type _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii, @function
_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vertShared2DPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii, .-_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
.globl _Z12vertShared2DPiS_iii
.type _Z12vertShared2DPiS_iii, @function
_Z12vertShared2DPiS_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12vertShared2DPiS_iii, .-_Z12vertShared2DPiS_iii
.globl _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
.type _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii, @function
_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8shared2DPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii, .-_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
.globl _Z8shared2DPiS_iii
.type _Z8shared2DPiS_iii, @function
_Z8shared2DPiS_iii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z8shared2DPiS_iii, .-_Z8shared2DPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "foo"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $400, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $10, %edx
movl $10, %esi
movq %r13, %rdi
call _Z4initPiii
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl $2, 60(%rsp)
movl $2, 64(%rsp)
movl $0, %r9d
movl $2816, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L43:
movl $2, %ecx
movl $400, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 400(%r15), %rax
movq %rax, 16(%rsp)
movl $0, 12(%rsp)
leaq .LC0(%rip), %r14
jmp .L44
.L55:
movl $10, %r8d
movl $10, %ecx
movl $6, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
jmp .L43
.L45:
addq $4, %rbp
addl $1, %ebx
cmpl $16, %ebx
je .L56
.L46:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
addl %edx, %edx
movl %ebx, %eax
subl %edx, %eax
addl %r12d, %eax
cltq
movl 0(%r13,%rax,4), %eax
cmpl %eax, 0(%rbp)
je .L45
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L56:
addq $40, %r15
addl $10, 12(%rsp)
movq 16(%rsp), %rax
cmpq %rax, %r15
je .L57
.L44:
movl 12(%rsp), %r12d
movq %r15, %rbp
movl $6, %ebx
jmp .L46
.L57:
movq 24(%rsp), %rax
leaq 40(%rax), %rbp
leaq 440(%rax), %r15
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r14
.L47:
leaq -40(%rbp), %rbx
.L48:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rbp
cmpq %r15, %rbp
jne .L47
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8shared2DPiS_iii"
.LC4:
.string "_Z12vertShared2DPiS_iii"
.LC5:
.string "_Z13horizShared2DPiS_iii"
.LC6:
.string "_Z8shared1DPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8shared2DPiS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vertShared2DPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13horizShared2DPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8shared1DPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define DEBUG
#ifdef DEBUG
#include <stdio.h>
#endif
#include <time.h> // for rand()
#define BLOCKDIM 8
#define WIDTH 10
#define HEIGHT 10
#define RADIUS BLOCKDIM-2
__global__ void shared1D(int * in, int * out, int radius, int n) {
extern __shared__ int smem[];
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int xIndex = tx + bx*dx;
int index = xIndex;
#define SMEM(txOffset) smem[tx + txOffset]
if (xIndex < n)
SMEM(radius) = in[index];
else
SMEM(radius) = in[n - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0) = in[index - radius];
} else {
SMEM(0) = in[0];
}
if (xIndex + dx < n) {
SMEM(dx + radius) = in[index + dx];
} else {
SMEM(dx + radius) = in[n - 1];
}
}
__syncthreads();
if (xIndex >= n)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1);
#undef SMEM
}
__global__ void horizShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (yIndex >= height)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width)
SMEM(radius, 0) = in[index];
else
SMEM(radius, 0) = in[(yIndex+1)*width - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius];
} else {
SMEM(0, 0) = in[yIndex*width];
}
if (xIndex + dx < width) {
SMEM(dx + radius, 0) = in[index + dx];
} else {
SMEM(dx + radius, 0) = in[(yIndex + 1)*width - 1];
}
}
__syncthreads();
if (xIndex >= width)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1, 0);
#undef SMEM
}
__global__ void vertShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (xIndex >= width)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*dx]
if (yIndex < height)
SMEM(0, radius) = in[index];
else
SMEM(0, radius) = in[(height-1)*width + xIndex];
if (ty < radius) {
if (yIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius*width];
} else {
SMEM(0, 0) = in[xIndex];
}
if (yIndex + dy < height) {
SMEM(0, dy + radius) = in[index + dy*width];
} else {
SMEM(0, dy + radius) = in[(height - 1)*width + xIndex];
}
}
__syncthreads();
if (yIndex >= height)
return ;
ty += radius;
out[index] = SMEM(0, RADIUS-1);
#undef SMEM
}
__global__ void shared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width && yIndex < height) {
SMEM(radius, radius) = in[index];
} else if (xIndex < width) {
SMEM(radius, radius) = in[(height - 1)*width + xIndex];
} else if (yIndex < height) {
SMEM(radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(radius, radius) = in[height*width - 1];
}
if (tx < radius) {
if (xIndex - radius >= 0) {
if (yIndex < height) {
SMEM(0, radius) = in[index - radius];
} else {
SMEM(0, radius) = in[(height - 1)*width + xIndex - radius];
}
} else {
if (yIndex < height) {
SMEM(0, radius) = in[yIndex*width];
} else {
SMEM(0, radius) = in[(height - 1)*width];
}
}
if (xIndex + dx < width) {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[index + dx];
} else {
SMEM(dx+radius, radius) = in[(height - 1)*width + xIndex + dx];
}
} else {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(dx+radius, radius) = in[height*width - 1];
}
}
}
if (ty < radius) {
if (yIndex - radius >= 0) {
if (xIndex < width) {
SMEM(radius, 0) = in[index - width*radius];
} else {
SMEM(radius, 0) = in[(yIndex - radius)*width];
}
} else {
if (xIndex < width) {
SMEM(radius, 0) = in[xIndex];
} else {
SMEM(radius, 0) = in[0];
}
}
if (yIndex + dy < width) {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[index + dy*width];
} else {
SMEM(radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
}
} else {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[(height - 1)*width + xIndex];
} else {
SMEM(radius, dy + radius) = in[height*width - 1];
}
}
}
if (tx < radius && ty < radius) {
// top left corner
if (xIndex - radius >= 0) {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[index - radius*(width + 1)];
else
SMEM(0, 0) = in[xIndex - radius];
} else {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[(yIndex - radius)*width];
else
SMEM(0, 0) = in[0];
}
// bottom left corner
if (xIndex - radius >= 0) {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[index - radius + dx*width];
else
SMEM(0, dy + radius) = in[xIndex - radius + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[(yIndex + dy)*width];
else
SMEM(0, dy + radius) = in[(height - 1)*width];
}
// top right corner
if (xIndex + dx < width) {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[index + dx - radius*width];
else
SMEM(dx + radius, 0) = in[xIndex + dx];
} else {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[(yIndex - radius + 1)*width - 1];
else
SMEM(dx + radius, 0) = in[width - 1];
}
// bottom right corner
if (xIndex + dx < width) {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[index + dy*(width + 1)];
else
SMEM(dx + radius, dy + radius) = in[xIndex + dx + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
else
SMEM(dx + radius, dy + radius) = in[height*width - 1];
}
SMEM(0, 0) = 11;
SMEM(dx + radius, 0) = 33;
SMEM(0, dy + radius) = 88;
SMEM(dx + radius, dy + radius) = 99;
}
if (xIndex >= width || yIndex >= height)
return ;
tx += radius;
ty += radius;
out[index] = SMEM(4, 4);
#undef SMEM
}
__host__ void init(int * list, int width, int height) {
int ii, jj;
for (ii = 0; ii < height; ii++) {
for (jj = 0; jj < width; jj++) {
list[ii*width + jj] = ii;
}
}
}
int main( ) {
int * in, * d_in;
int * out, * d_out;
int width, height, radius;
int sharedMemSize;
#ifdef DEBUG
int ii, jj;
#endif
width = WIDTH;
height = HEIGHT;
radius = RADIUS;
in = (int *) malloc(width*height*sizeof(int));
out = (int *) malloc(width*height*sizeof(int));
init(in, width, height);
cudaMalloc((void **) &d_in, width*height*sizeof(int));
cudaMalloc((void **) &d_out, width*height*sizeof(int));
cudaMemcpy(d_in, in, width*height*sizeof(int), cudaMemcpyHostToDevice);
dim3 blockDim(BLOCKDIM,BLOCKDIM);
dim3 gridDim((width + BLOCKDIM - 1)/BLOCKDIM, (height + BLOCKDIM -1)/BLOCKDIM);
sharedMemSize = BLOCKDIM*(BLOCKDIM+2*RADIUS)*sizeof(int)*sizeof(int);
shared2D<<<gridDim, blockDim, sharedMemSize>>>(d_in, d_out, radius, width, height);
cudaMemcpy(out, d_out, width*height*sizeof(int), cudaMemcpyDeviceToHost);
#ifdef NDEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
if (out[jj*width + ii] != in[jj*width + (ii + RADIUS)%WIDTH]) {
printf("foo");
}
}
}
#endif
#ifdef DEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
printf("%d ", out[jj*width + ii]);
}
printf("\n");
}
#endif
free(in);
free(out);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | #define DEBUG
#ifdef DEBUG
#include <hip/hip_runtime.h>
#include <stdio.h>
#endif
#include <time.h> // for rand()
#define BLOCKDIM 8
#define WIDTH 10
#define HEIGHT 10
#define RADIUS BLOCKDIM-2
__global__ void shared1D(int * in, int * out, int radius, int n) {
extern __shared__ int smem[];
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int xIndex = tx + bx*dx;
int index = xIndex;
#define SMEM(txOffset) smem[tx + txOffset]
if (xIndex < n)
SMEM(radius) = in[index];
else
SMEM(radius) = in[n - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0) = in[index - radius];
} else {
SMEM(0) = in[0];
}
if (xIndex + dx < n) {
SMEM(dx + radius) = in[index + dx];
} else {
SMEM(dx + radius) = in[n - 1];
}
}
__syncthreads();
if (xIndex >= n)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1);
#undef SMEM
}
__global__ void horizShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (yIndex >= height)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width)
SMEM(radius, 0) = in[index];
else
SMEM(radius, 0) = in[(yIndex+1)*width - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius];
} else {
SMEM(0, 0) = in[yIndex*width];
}
if (xIndex + dx < width) {
SMEM(dx + radius, 0) = in[index + dx];
} else {
SMEM(dx + radius, 0) = in[(yIndex + 1)*width - 1];
}
}
__syncthreads();
if (xIndex >= width)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1, 0);
#undef SMEM
}
__global__ void vertShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (xIndex >= width)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*dx]
if (yIndex < height)
SMEM(0, radius) = in[index];
else
SMEM(0, radius) = in[(height-1)*width + xIndex];
if (ty < radius) {
if (yIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius*width];
} else {
SMEM(0, 0) = in[xIndex];
}
if (yIndex + dy < height) {
SMEM(0, dy + radius) = in[index + dy*width];
} else {
SMEM(0, dy + radius) = in[(height - 1)*width + xIndex];
}
}
__syncthreads();
if (yIndex >= height)
return ;
ty += radius;
out[index] = SMEM(0, RADIUS-1);
#undef SMEM
}
__global__ void shared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width && yIndex < height) {
SMEM(radius, radius) = in[index];
} else if (xIndex < width) {
SMEM(radius, radius) = in[(height - 1)*width + xIndex];
} else if (yIndex < height) {
SMEM(radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(radius, radius) = in[height*width - 1];
}
if (tx < radius) {
if (xIndex - radius >= 0) {
if (yIndex < height) {
SMEM(0, radius) = in[index - radius];
} else {
SMEM(0, radius) = in[(height - 1)*width + xIndex - radius];
}
} else {
if (yIndex < height) {
SMEM(0, radius) = in[yIndex*width];
} else {
SMEM(0, radius) = in[(height - 1)*width];
}
}
if (xIndex + dx < width) {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[index + dx];
} else {
SMEM(dx+radius, radius) = in[(height - 1)*width + xIndex + dx];
}
} else {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(dx+radius, radius) = in[height*width - 1];
}
}
}
if (ty < radius) {
if (yIndex - radius >= 0) {
if (xIndex < width) {
SMEM(radius, 0) = in[index - width*radius];
} else {
SMEM(radius, 0) = in[(yIndex - radius)*width];
}
} else {
if (xIndex < width) {
SMEM(radius, 0) = in[xIndex];
} else {
SMEM(radius, 0) = in[0];
}
}
if (yIndex + dy < width) {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[index + dy*width];
} else {
SMEM(radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
}
} else {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[(height - 1)*width + xIndex];
} else {
SMEM(radius, dy + radius) = in[height*width - 1];
}
}
}
if (tx < radius && ty < radius) {
// top left corner
if (xIndex - radius >= 0) {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[index - radius*(width + 1)];
else
SMEM(0, 0) = in[xIndex - radius];
} else {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[(yIndex - radius)*width];
else
SMEM(0, 0) = in[0];
}
// bottom left corner
if (xIndex - radius >= 0) {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[index - radius + dx*width];
else
SMEM(0, dy + radius) = in[xIndex - radius + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[(yIndex + dy)*width];
else
SMEM(0, dy + radius) = in[(height - 1)*width];
}
// top right corner
if (xIndex + dx < width) {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[index + dx - radius*width];
else
SMEM(dx + radius, 0) = in[xIndex + dx];
} else {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[(yIndex - radius + 1)*width - 1];
else
SMEM(dx + radius, 0) = in[width - 1];
}
// bottom right corner
if (xIndex + dx < width) {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[index + dy*(width + 1)];
else
SMEM(dx + radius, dy + radius) = in[xIndex + dx + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
else
SMEM(dx + radius, dy + radius) = in[height*width - 1];
}
SMEM(0, 0) = 11;
SMEM(dx + radius, 0) = 33;
SMEM(0, dy + radius) = 88;
SMEM(dx + radius, dy + radius) = 99;
}
if (xIndex >= width || yIndex >= height)
return ;
tx += radius;
ty += radius;
out[index] = SMEM(4, 4);
#undef SMEM
}
__host__ void init(int * list, int width, int height) {
int ii, jj;
for (ii = 0; ii < height; ii++) {
for (jj = 0; jj < width; jj++) {
list[ii*width + jj] = ii;
}
}
}
int main( ) {
int * in, * d_in;
int * out, * d_out;
int width, height, radius;
int sharedMemSize;
#ifdef DEBUG
int ii, jj;
#endif
width = WIDTH;
height = HEIGHT;
radius = RADIUS;
in = (int *) malloc(width*height*sizeof(int));
out = (int *) malloc(width*height*sizeof(int));
init(in, width, height);
hipMalloc((void **) &d_in, width*height*sizeof(int));
hipMalloc((void **) &d_out, width*height*sizeof(int));
hipMemcpy(d_in, in, width*height*sizeof(int), hipMemcpyHostToDevice);
dim3 blockDim(BLOCKDIM,BLOCKDIM);
dim3 gridDim((width + BLOCKDIM - 1)/BLOCKDIM, (height + BLOCKDIM -1)/BLOCKDIM);
sharedMemSize = BLOCKDIM*(BLOCKDIM+2*RADIUS)*sizeof(int)*sizeof(int);
shared2D<<<gridDim, blockDim, sharedMemSize>>>(d_in, d_out, radius, width, height);
hipMemcpy(out, d_out, width*height*sizeof(int), hipMemcpyDeviceToHost);
#ifdef NDEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
if (out[jj*width + ii] != in[jj*width + (ii + RADIUS)%WIDTH]) {
printf("foo");
}
}
}
#endif
#ifdef DEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
printf("%d ", out[jj*width + ii]);
}
printf("\n");
}
#endif
free(in);
free(out);
hipFree(d_in);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define DEBUG
#ifdef DEBUG
#include <hip/hip_runtime.h>
#include <stdio.h>
#endif
#include <time.h> // for rand()
#define BLOCKDIM 8
#define WIDTH 10
#define HEIGHT 10
#define RADIUS BLOCKDIM-2
__global__ void shared1D(int * in, int * out, int radius, int n) {
extern __shared__ int smem[];
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int xIndex = tx + bx*dx;
int index = xIndex;
#define SMEM(txOffset) smem[tx + txOffset]
if (xIndex < n)
SMEM(radius) = in[index];
else
SMEM(radius) = in[n - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0) = in[index - radius];
} else {
SMEM(0) = in[0];
}
if (xIndex + dx < n) {
SMEM(dx + radius) = in[index + dx];
} else {
SMEM(dx + radius) = in[n - 1];
}
}
__syncthreads();
if (xIndex >= n)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1);
#undef SMEM
}
__global__ void horizShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (yIndex >= height)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width)
SMEM(radius, 0) = in[index];
else
SMEM(radius, 0) = in[(yIndex+1)*width - 1];
if (tx < radius) {
if (xIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius];
} else {
SMEM(0, 0) = in[yIndex*width];
}
if (xIndex + dx < width) {
SMEM(dx + radius, 0) = in[index + dx];
} else {
SMEM(dx + radius, 0) = in[(yIndex + 1)*width - 1];
}
}
__syncthreads();
if (xIndex >= width)
return ;
tx += radius;
out[index] = SMEM(RADIUS-1, 0);
#undef SMEM
}
__global__ void vertShared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
if (xIndex >= width)
return ;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*dx]
if (yIndex < height)
SMEM(0, radius) = in[index];
else
SMEM(0, radius) = in[(height-1)*width + xIndex];
if (ty < radius) {
if (yIndex - radius >= 0) {
SMEM(0, 0) = in[index - radius*width];
} else {
SMEM(0, 0) = in[xIndex];
}
if (yIndex + dy < height) {
SMEM(0, dy + radius) = in[index + dy*width];
} else {
SMEM(0, dy + radius) = in[(height - 1)*width + xIndex];
}
}
__syncthreads();
if (yIndex >= height)
return ;
ty += radius;
out[index] = SMEM(0, RADIUS-1);
#undef SMEM
}
__global__ void shared2D(int * in, int * out, int radius, int width, int height) {
extern __shared__ int smem[];
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int dx = blockDim.x, dy = blockDim.y;
int xIndex = tx + bx*dx;
int yIndex = ty + by*dy;
int index = xIndex + yIndex*width;
#define SMEM(txOffset, tyOffset) smem[tx + txOffset + (ty+(tyOffset))*(dx+2*radius)]
if (xIndex < width && yIndex < height) {
SMEM(radius, radius) = in[index];
} else if (xIndex < width) {
SMEM(radius, radius) = in[(height - 1)*width + xIndex];
} else if (yIndex < height) {
SMEM(radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(radius, radius) = in[height*width - 1];
}
if (tx < radius) {
if (xIndex - radius >= 0) {
if (yIndex < height) {
SMEM(0, radius) = in[index - radius];
} else {
SMEM(0, radius) = in[(height - 1)*width + xIndex - radius];
}
} else {
if (yIndex < height) {
SMEM(0, radius) = in[yIndex*width];
} else {
SMEM(0, radius) = in[(height - 1)*width];
}
}
if (xIndex + dx < width) {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[index + dx];
} else {
SMEM(dx+radius, radius) = in[(height - 1)*width + xIndex + dx];
}
} else {
if (yIndex < height) {
SMEM(dx+radius, radius) = in[(yIndex + 1)*width - 1];
} else {
SMEM(dx+radius, radius) = in[height*width - 1];
}
}
}
if (ty < radius) {
if (yIndex - radius >= 0) {
if (xIndex < width) {
SMEM(radius, 0) = in[index - width*radius];
} else {
SMEM(radius, 0) = in[(yIndex - radius)*width];
}
} else {
if (xIndex < width) {
SMEM(radius, 0) = in[xIndex];
} else {
SMEM(radius, 0) = in[0];
}
}
if (yIndex + dy < width) {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[index + dy*width];
} else {
SMEM(radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
}
} else {
if (xIndex < width) {
SMEM(radius, dy + radius) = in[(height - 1)*width + xIndex];
} else {
SMEM(radius, dy + radius) = in[height*width - 1];
}
}
}
if (tx < radius && ty < radius) {
// top left corner
if (xIndex - radius >= 0) {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[index - radius*(width + 1)];
else
SMEM(0, 0) = in[xIndex - radius];
} else {
if (yIndex - radius >= 0)
SMEM(0, 0) = in[(yIndex - radius)*width];
else
SMEM(0, 0) = in[0];
}
// bottom left corner
if (xIndex - radius >= 0) {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[index - radius + dx*width];
else
SMEM(0, dy + radius) = in[xIndex - radius + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(0, dy + radius) = in[(yIndex + dy)*width];
else
SMEM(0, dy + radius) = in[(height - 1)*width];
}
// top right corner
if (xIndex + dx < width) {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[index + dx - radius*width];
else
SMEM(dx + radius, 0) = in[xIndex + dx];
} else {
if (yIndex - radius >= 0)
SMEM(dx + radius, 0) = in[(yIndex - radius + 1)*width - 1];
else
SMEM(dx + radius, 0) = in[width - 1];
}
// bottom right corner
if (xIndex + dx < width) {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[index + dy*(width + 1)];
else
SMEM(dx + radius, dy + radius) = in[xIndex + dx + (height - 1)*width];
} else {
if (yIndex + dy < height)
SMEM(dx + radius, dy + radius) = in[(yIndex + dy + 1)*width - 1];
else
SMEM(dx + radius, dy + radius) = in[height*width - 1];
}
SMEM(0, 0) = 11;
SMEM(dx + radius, 0) = 33;
SMEM(0, dy + radius) = 88;
SMEM(dx + radius, dy + radius) = 99;
}
if (xIndex >= width || yIndex >= height)
return ;
tx += radius;
ty += radius;
out[index] = SMEM(4, 4);
#undef SMEM
}
__host__ void init(int * list, int width, int height) {
int ii, jj;
for (ii = 0; ii < height; ii++) {
for (jj = 0; jj < width; jj++) {
list[ii*width + jj] = ii;
}
}
}
int main( ) {
int * in, * d_in;
int * out, * d_out;
int width, height, radius;
int sharedMemSize;
#ifdef DEBUG
int ii, jj;
#endif
width = WIDTH;
height = HEIGHT;
radius = RADIUS;
in = (int *) malloc(width*height*sizeof(int));
out = (int *) malloc(width*height*sizeof(int));
init(in, width, height);
hipMalloc((void **) &d_in, width*height*sizeof(int));
hipMalloc((void **) &d_out, width*height*sizeof(int));
hipMemcpy(d_in, in, width*height*sizeof(int), hipMemcpyHostToDevice);
dim3 blockDim(BLOCKDIM,BLOCKDIM);
dim3 gridDim((width + BLOCKDIM - 1)/BLOCKDIM, (height + BLOCKDIM -1)/BLOCKDIM);
sharedMemSize = BLOCKDIM*(BLOCKDIM+2*RADIUS)*sizeof(int)*sizeof(int);
shared2D<<<gridDim, blockDim, sharedMemSize>>>(d_in, d_out, radius, width, height);
hipMemcpy(out, d_out, width*height*sizeof(int), hipMemcpyDeviceToHost);
#ifdef NDEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
if (out[jj*width + ii] != in[jj*width + (ii + RADIUS)%WIDTH]) {
printf("foo");
}
}
}
#endif
#ifdef DEBUG
for (jj = 0; jj < height; jj++) {
for (ii = 0; ii < width; ii++) {
printf("%d ", out[jj*width + ii]);
}
printf("\n");
}
#endif
free(in);
free(out);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.file "sharedMemory.hip"
.globl _Z23__device_stub__shared1DPiS_ii # -- Begin function _Z23__device_stub__shared1DPiS_ii
.p2align 4, 0x90
.type _Z23__device_stub__shared1DPiS_ii,@function
_Z23__device_stub__shared1DPiS_ii: # @_Z23__device_stub__shared1DPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8shared1DPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__shared1DPiS_ii, .Lfunc_end0-_Z23__device_stub__shared1DPiS_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__horizShared2DPiS_iii # -- Begin function _Z28__device_stub__horizShared2DPiS_iii
.p2align 4, 0x90
.type _Z28__device_stub__horizShared2DPiS_iii,@function
_Z28__device_stub__horizShared2DPiS_iii: # @_Z28__device_stub__horizShared2DPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13horizShared2DPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__horizShared2DPiS_iii, .Lfunc_end1-_Z28__device_stub__horizShared2DPiS_iii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vertShared2DPiS_iii # -- Begin function _Z27__device_stub__vertShared2DPiS_iii
.p2align 4, 0x90
.type _Z27__device_stub__vertShared2DPiS_iii,@function
_Z27__device_stub__vertShared2DPiS_iii: # @_Z27__device_stub__vertShared2DPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vertShared2DPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__vertShared2DPiS_iii, .Lfunc_end2-_Z27__device_stub__vertShared2DPiS_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__shared2DPiS_iii # -- Begin function _Z23__device_stub__shared2DPiS_iii
.p2align 4, 0x90
.type _Z23__device_stub__shared2DPiS_iii,@function
_Z23__device_stub__shared2DPiS_iii: # @_Z23__device_stub__shared2DPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8shared2DPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__shared2DPiS_iii, .Lfunc_end3-_Z23__device_stub__shared2DPiS_iii
.cfi_endproc
# -- End function
.globl _Z4initPiii # -- Begin function _Z4initPiii
.p2align 4, 0x90
.type _Z4initPiii,@function
_Z4initPiii: # @_Z4initPiii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
movl %esi, %ecx
xorl %edx, %edx
xorl %r8d, %r8d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r8
addl %esi, %edx
cmpq %rax, %r8
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %esi, %esi
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %edx, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge14
retq
.Lfunc_end4:
.size _Z4initPiii, .Lfunc_end4-_Z4initPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%rcx,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB5_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incq %rax
addq $40, %rcx
cmpq $10, %rax
jne .LBB5_1
# %bb.4: # %_Z4initPiii.exit
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $2816, %r8d # imm = 0xB00
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $6, 28(%rsp)
movl $10, 24(%rsp)
movl $10, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8shared2DPiS_iii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq (%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %r12
addq $24, %r12
movabsq $-3689348814741910323, %r13 # imm = 0xCCCCCCCCCCCCCCCD
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rbp
xorl %ebx, %ebx
jmp .LBB5_7
.p2align 4, 0x90
.LBB5_11: # in Loop: Header=BB5_7 Depth=1
incq %rbx
addq $40, %rbp
addq $40, %r12
cmpq $10, %rbx
je .LBB5_12
.LBB5_7: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
movl $6, %r15d
xorl %r14d, %r14d
jmp .LBB5_8
.p2align 4, 0x90
.LBB5_10: # in Loop: Header=BB5_8 Depth=2
incq %r14
incq %r15
cmpq $10, %r14
je .LBB5_11
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rax
mulq %r13
andq $-8, %rdx
leaq (%rdx,%rdx,4), %rax
movq %r12, %rcx
subq %rax, %rcx
movl (%rbp,%r14,4), %eax
cmpl (%rcx,%r14,4), %eax
je .LBB5_10
# %bb.9: # in Loop: Header=BB5_8 Depth=2
movl $.L.str, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_10
.LBB5_12: # %.preheader.preheader
movq 32(%rsp), %r13 # 8-byte Reload
movq %r13, %rbx
xorl %r15d, %r15d
movq 40(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB5_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB5_14
# %bb.15: # in Loop: Header=BB5_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %rbx
cmpq $10, %r15
jne .LBB5_13
# %bb.16:
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8shared1DPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13horizShared2DPiS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vertShared2DPiS_iii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8shared2DPiS_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8shared1DPiS_ii,@object # @_Z8shared1DPiS_ii
.section .rodata,"a",@progbits
.globl _Z8shared1DPiS_ii
.p2align 3, 0x0
_Z8shared1DPiS_ii:
.quad _Z23__device_stub__shared1DPiS_ii
.size _Z8shared1DPiS_ii, 8
.type _Z13horizShared2DPiS_iii,@object # @_Z13horizShared2DPiS_iii
.globl _Z13horizShared2DPiS_iii
.p2align 3, 0x0
_Z13horizShared2DPiS_iii:
.quad _Z28__device_stub__horizShared2DPiS_iii
.size _Z13horizShared2DPiS_iii, 8
.type _Z12vertShared2DPiS_iii,@object # @_Z12vertShared2DPiS_iii
.globl _Z12vertShared2DPiS_iii
.p2align 3, 0x0
_Z12vertShared2DPiS_iii:
.quad _Z27__device_stub__vertShared2DPiS_iii
.size _Z12vertShared2DPiS_iii, 8
.type _Z8shared2DPiS_iii,@object # @_Z8shared2DPiS_iii
.globl _Z8shared2DPiS_iii
.p2align 3, 0x0
_Z8shared2DPiS_iii:
.quad _Z23__device_stub__shared2DPiS_iii
.size _Z8shared2DPiS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "foo"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8shared1DPiS_ii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13horizShared2DPiS_iii"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12vertShared2DPiS_iii"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8shared2DPiS_iii"
.size .L__unnamed_4, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__shared1DPiS_ii
.addrsig_sym _Z28__device_stub__horizShared2DPiS_iii
.addrsig_sym _Z27__device_stub__vertShared2DPiS_iii
.addrsig_sym _Z23__device_stub__shared2DPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8shared1DPiS_ii
.addrsig_sym _Z13horizShared2DPiS_iii
.addrsig_sym _Z12vertShared2DPiS_iii
.addrsig_sym _Z8shared2DPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ca88a_00000000-6_sharedMemory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPiii
.type _Z4initPiii, @function
_Z4initPiii:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movl $0, %r9d
movl $0, %ecx
movslq %esi, %r10
jmp .L5
.L7:
movslq %r9d, %r8
leaq (%rdi,%r8,4), %rax
addq %r10, %r8
leaq (%rdi,%r8,4), %r8
.L6:
movl %ecx, (%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L6
.L8:
addl $1, %ecx
addl %esi, %r9d
cmpl %ecx, %edx
je .L3
.L5:
testl %esi, %esi
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z4initPiii, .-_Z4initPiii
.globl _Z31__device_stub__Z8shared1DPiS_iiPiS_ii
.type _Z31__device_stub__Z8shared1DPiS_iiPiS_ii, @function
_Z31__device_stub__Z8shared1DPiS_iiPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8shared1DPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8shared1DPiS_iiPiS_ii, .-_Z31__device_stub__Z8shared1DPiS_iiPiS_ii
.globl _Z8shared1DPiS_ii
.type _Z8shared1DPiS_ii, @function
_Z8shared1DPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8shared1DPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8shared1DPiS_ii, .-_Z8shared1DPiS_ii
.globl _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
.type _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii, @function
_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13horizShared2DPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii, .-_Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
.globl _Z13horizShared2DPiS_iii
.type _Z13horizShared2DPiS_iii, @function
_Z13horizShared2DPiS_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13horizShared2DPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13horizShared2DPiS_iii, .-_Z13horizShared2DPiS_iii
.globl _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
.type _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii, @function
_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vertShared2DPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii, .-_Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
.globl _Z12vertShared2DPiS_iii
.type _Z12vertShared2DPiS_iii, @function
_Z12vertShared2DPiS_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vertShared2DPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12vertShared2DPiS_iii, .-_Z12vertShared2DPiS_iii
.globl _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
.type _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii, @function
_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8shared2DPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii, .-_Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
.globl _Z8shared2DPiS_iii
.type _Z8shared2DPiS_iii, @function
_Z8shared2DPiS_iii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z8shared2DPiS_iii, .-_Z8shared2DPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "foo"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $400, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $10, %edx
movl $10, %esi
movq %r13, %rdi
call _Z4initPiii
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl $2, 60(%rsp)
movl $2, 64(%rsp)
movl $0, %r9d
movl $2816, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L43:
movl $2, %ecx
movl $400, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 400(%r15), %rax
movq %rax, 16(%rsp)
movl $0, 12(%rsp)
leaq .LC0(%rip), %r14
jmp .L44
.L55:
movl $10, %r8d
movl $10, %ecx
movl $6, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z8shared2DPiS_iiiPiS_iii
jmp .L43
.L45:
addq $4, %rbp
addl $1, %ebx
cmpl $16, %ebx
je .L56
.L46:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
addl %edx, %edx
movl %ebx, %eax
subl %edx, %eax
addl %r12d, %eax
cltq
movl 0(%r13,%rax,4), %eax
cmpl %eax, 0(%rbp)
je .L45
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L56:
addq $40, %r15
addl $10, 12(%rsp)
movq 16(%rsp), %rax
cmpq %rax, %r15
je .L57
.L44:
movl 12(%rsp), %r12d
movq %r15, %rbp
movl $6, %ebx
jmp .L46
.L57:
movq 24(%rsp), %rax
leaq 40(%rax), %rbp
leaq 440(%rax), %r15
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r14
.L47:
leaq -40(%rbp), %rbx
.L48:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rbp
cmpq %r15, %rbp
jne .L47
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8shared2DPiS_iii"
.LC4:
.string "_Z12vertShared2DPiS_iii"
.LC5:
.string "_Z13horizShared2DPiS_iii"
.LC6:
.string "_Z8shared1DPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8shared2DPiS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vertShared2DPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13horizShared2DPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8shared1DPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sharedMemory.hip"
.globl _Z23__device_stub__shared1DPiS_ii # -- Begin function _Z23__device_stub__shared1DPiS_ii
.p2align 4, 0x90
.type _Z23__device_stub__shared1DPiS_ii,@function
_Z23__device_stub__shared1DPiS_ii: # @_Z23__device_stub__shared1DPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8shared1DPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__shared1DPiS_ii, .Lfunc_end0-_Z23__device_stub__shared1DPiS_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__horizShared2DPiS_iii # -- Begin function _Z28__device_stub__horizShared2DPiS_iii
.p2align 4, 0x90
.type _Z28__device_stub__horizShared2DPiS_iii,@function
_Z28__device_stub__horizShared2DPiS_iii: # @_Z28__device_stub__horizShared2DPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13horizShared2DPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__horizShared2DPiS_iii, .Lfunc_end1-_Z28__device_stub__horizShared2DPiS_iii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vertShared2DPiS_iii # -- Begin function _Z27__device_stub__vertShared2DPiS_iii
.p2align 4, 0x90
.type _Z27__device_stub__vertShared2DPiS_iii,@function
_Z27__device_stub__vertShared2DPiS_iii: # @_Z27__device_stub__vertShared2DPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vertShared2DPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__vertShared2DPiS_iii, .Lfunc_end2-_Z27__device_stub__vertShared2DPiS_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__shared2DPiS_iii # -- Begin function _Z23__device_stub__shared2DPiS_iii
.p2align 4, 0x90
.type _Z23__device_stub__shared2DPiS_iii,@function
_Z23__device_stub__shared2DPiS_iii: # @_Z23__device_stub__shared2DPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8shared2DPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__shared2DPiS_iii, .Lfunc_end3-_Z23__device_stub__shared2DPiS_iii
.cfi_endproc
# -- End function
.globl _Z4initPiii # -- Begin function _Z4initPiii
.p2align 4, 0x90
.type _Z4initPiii,@function
_Z4initPiii: # @_Z4initPiii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
movl %esi, %ecx
xorl %edx, %edx
xorl %r8d, %r8d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r8
addl %esi, %edx
cmpq %rax, %r8
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %esi, %esi
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %edx, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge14
retq
.Lfunc_end4:
.size _Z4initPiii, .Lfunc_end4-_Z4initPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%rcx,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB5_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incq %rax
addq $40, %rcx
cmpq $10, %rax
jne .LBB5_1
# %bb.4: # %_Z4initPiii.exit
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $2816, %r8d # imm = 0xB00
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $6, 28(%rsp)
movl $10, 24(%rsp)
movl $10, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8shared2DPiS_iii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq (%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %r12
addq $24, %r12
movabsq $-3689348814741910323, %r13 # imm = 0xCCCCCCCCCCCCCCCD
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rbp
xorl %ebx, %ebx
jmp .LBB5_7
.p2align 4, 0x90
.LBB5_11: # in Loop: Header=BB5_7 Depth=1
incq %rbx
addq $40, %rbp
addq $40, %r12
cmpq $10, %rbx
je .LBB5_12
.LBB5_7: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
movl $6, %r15d
xorl %r14d, %r14d
jmp .LBB5_8
.p2align 4, 0x90
.LBB5_10: # in Loop: Header=BB5_8 Depth=2
incq %r14
incq %r15
cmpq $10, %r14
je .LBB5_11
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rax
mulq %r13
andq $-8, %rdx
leaq (%rdx,%rdx,4), %rax
movq %r12, %rcx
subq %rax, %rcx
movl (%rbp,%r14,4), %eax
cmpl (%rcx,%r14,4), %eax
je .LBB5_10
# %bb.9: # in Loop: Header=BB5_8 Depth=2
movl $.L.str, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_10
.LBB5_12: # %.preheader.preheader
movq 32(%rsp), %r13 # 8-byte Reload
movq %r13, %rbx
xorl %r15d, %r15d
movq 40(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB5_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB5_14
# %bb.15: # in Loop: Header=BB5_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %rbx
cmpq $10, %r15
jne .LBB5_13
# %bb.16:
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8shared1DPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13horizShared2DPiS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vertShared2DPiS_iii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8shared2DPiS_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8shared1DPiS_ii,@object # @_Z8shared1DPiS_ii
.section .rodata,"a",@progbits
.globl _Z8shared1DPiS_ii
.p2align 3, 0x0
_Z8shared1DPiS_ii:
.quad _Z23__device_stub__shared1DPiS_ii
.size _Z8shared1DPiS_ii, 8
.type _Z13horizShared2DPiS_iii,@object # @_Z13horizShared2DPiS_iii
.globl _Z13horizShared2DPiS_iii
.p2align 3, 0x0
_Z13horizShared2DPiS_iii:
.quad _Z28__device_stub__horizShared2DPiS_iii
.size _Z13horizShared2DPiS_iii, 8
.type _Z12vertShared2DPiS_iii,@object # @_Z12vertShared2DPiS_iii
.globl _Z12vertShared2DPiS_iii
.p2align 3, 0x0
_Z12vertShared2DPiS_iii:
.quad _Z27__device_stub__vertShared2DPiS_iii
.size _Z12vertShared2DPiS_iii, 8
.type _Z8shared2DPiS_iii,@object # @_Z8shared2DPiS_iii
.globl _Z8shared2DPiS_iii
.p2align 3, 0x0
_Z8shared2DPiS_iii:
.quad _Z23__device_stub__shared2DPiS_iii
.size _Z8shared2DPiS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "foo"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8shared1DPiS_ii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13horizShared2DPiS_iii"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12vertShared2DPiS_iii"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8shared2DPiS_iii"
.size .L__unnamed_4, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__shared1DPiS_ii
.addrsig_sym _Z28__device_stub__horizShared2DPiS_iii
.addrsig_sym _Z27__device_stub__vertShared2DPiS_iii
.addrsig_sym _Z23__device_stub__shared2DPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8shared1DPiS_ii
.addrsig_sym _Z13horizShared2DPiS_iii
.addrsig_sym _Z12vertShared2DPiS_iii
.addrsig_sym _Z8shared2DPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define NUM 1024
cudaError_t addWithCuda(double *c, const double *a, const double *b, long size);
__device__ double test(int i);
__global__ void addKernel(double *c, const double *a, const double *b)
{
int i = threadIdx.x;
for (int j = 0; j < NUM; j++) {
c[j] = test(i);
}
}
__device__ double test(int i) {
double tmp = (i - 9.9) * 3.1415926 * 3.1415926;
double ret = sin(tmp);
return ret;
}
int main()
{
const double a[NUM] = { 1, 2, 3, 4, 5 };
const double b[NUM] = { 10, 20, 30, 40, 50 };
double c[NUM] = { 0 };
// Add vectors in parallel.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaError_t cudaStatus = addWithCuda(c, a, b, NUM);
cudaEventRecord(stop, 0);
//confirm that all things have been done before "stop event"
cudaEventSynchronize(stop);
float elapseTime;
cudaEventElapsedTime(&elapseTime, start, stop);
printf("Time for I/O : %.5f ms\n", elapseTime);
printf("%.6f\n", c[2]);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(double *c, const double *a, const double *b, long size)
{
double *dev_a = 0;
double *dev_b = 0;
double *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | code for sm_80
Function : _Z9addKernelPdPKdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ IADD3 R28, R1, c[0x0][0x20], RZ ; /* 0x00000800011c7a10 */
/* 0x000fe20007ffe0ff */
/*0060*/ I2F.F64 R2, R4 ; /* 0x0000000400027312 */
/* 0x001e240000201c00 */
/*0070*/ DADD R2, R2, c[0x2][0x0] ; /* 0x0080000002027629 */
/* 0x001e0c0000000000 */
/*0080*/ DMUL R2, R2, c[0x2][0x8] ; /* 0x0080020002027a28 */
/* 0x001e0c0000000000 */
/*0090*/ DMUL R16, R2, c[0x2][0x8] ; /* 0x0080020002107a28 */
/* 0x0010640000000000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x001fc800078e00ff */
/*00b0*/ DMUL R14, R16, c[0x2][0x10] ; /* 0x00800400100e7a28 */
/* 0x002e080000000000 */
/*00c0*/ LOP3.LUT R2, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff11027812 */
/* 0x000fe400078ec0ff */
/*00d0*/ F2I.F64 R0, R14 ; /* 0x0000000e00007311 */
/* 0x001e240000301100 */
/*00e0*/ ISETP.NE.AND P2, PT, R2, 0x7ff00000, PT ; /* 0x7ff000000200780c */
/* 0x000fe20003f45270 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fc600078e00ff */
/*0100*/ ISETP.EQ.AND P2, PT, R16, RZ, !P2 ; /* 0x000000ff1000720c */
/* 0x000fe40005742270 */
/*0110*/ I2F.F64 R12, R0 ; /* 0x00000000000c7312 */
/* 0x0010700000201c00 */
/*0120*/ IADD3 R3, R3, 0x2, RZ ; /* 0x0000000203037810 */
/* 0x000fe20007ffe0ff */
/*0130*/ BSSY B0, 0x2a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0002 */
/*0150*/ ISETP.NE.AND P3, PT, R3, 0x400, PT ; /* 0x000004000300780c */
/* 0x000fe20003f65270 */
/*0160*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*0170*/ @P2 BRA 0x270 ; /* 0x000000f000002947 */
/* 0x002fea0003800000 */
/*0180*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0005e20000100800 */
/*0190*/ DSETP.GE.AND P0, PT, |R16|, 2.14748364800000000000e+09, PT ; /* 0x41e000001000742a */
/* 0x000fe20003f06200 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0000 */
/*01b0*/ DFMA R4, -R12, c[0x2][0x18], R16 ; /* 0x008006000c047a2b */
/* 0x002e4c0000000110 */
/*01c0*/ DFMA R4, -R12, c[0x2][0x20], R4 ; /* 0x008008000c047a2b */
/* 0x002e4c0000000104 */
/*01d0*/ DFMA R4, -R12, c[0x2][0x28], R4 ; /* 0x00800a000c047a2b */
/* 0x0024620000000104 */
/*01e0*/ @!P0 BRA 0x290 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B1, 0x250 ; /* 0x0000005000017945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0010 */
/*0210*/ MOV R2, 0x240 ; /* 0x0000024000027802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x002fe400078e0011 */
/*0230*/ CALL.REL.NOINC 0x780 ; /* 0x0000054000007944 */
/* 0x005fea0003c00000 */
/*0240*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0250*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x0001620000100800 */
/*0260*/ BRA 0x290 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0270*/ DMUL R4, RZ, R16 ; /* 0x00000010ff047228 */
/* 0x0004e20000000000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fca00078e00ff */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.SHL.U32 R6, R2, 0x8, RZ ; /* 0x0000000802067824 */
/* 0x020fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc600078e00ff */
/*02c0*/ LOP3.LUT R6, R6, 0x8, RZ, 0xc0, !PT ; /* 0x0000000806067812 */
/* 0x000fca00078ec0ff */
/*02d0*/ IMAD.WIDE R6, R6, R7, c[0x4][0x0] ; /* 0x0100000006067625 */
/* 0x000fca00078e0207 */
/*02e0*/ LDG.E.64.CONSTANT R20, [R6.64+0x8] ; /* 0x0000080606147981 */
/* 0x000f28000c1e9b00 */
/*02f0*/ LDG.E.64.CONSTANT R22, [R6.64+0x10] ; /* 0x0000100606167981 */
/* 0x004ea2000c1e9b00 */
/*0300*/ R2P PR, R2, 0x3 ; /* 0x0000000302007804 */
/* 0x000fe20000000000 */
/*0310*/ IMAD.MOV.U32 R24, RZ, RZ, 0x79785eba ; /* 0x79785ebaff187424 */
/* 0x000fe200078e00ff */
/*0320*/ DMUL R8, R4, R4 ; /* 0x0000000404087228 */
/* 0x00af220000000000 */
/*0330*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3de5db65 ; /* 0x3de5db65ff027424 */
/* 0x000fe200078e00ff */
/*0340*/ LDG.E.64.CONSTANT R18, [R6.64+0x18] ; /* 0x0000180606127981 */
/* 0x000ee4000c1e9b00 */
/*0350*/ FSEL R24, -R24, 4.2945490664224492434e-19, !P0 ; /* 0x20fd816418187808 */
/* 0x000fc40004000100 */
/*0360*/ FSEL R25, R2, -0.082518599927425384521, !P0 ; /* 0xbda8ff8302197808 */
/* 0x000fe20004000000 */
/*0370*/ LDG.E.64.CONSTANT R26, [R6.64+0x30] ; /* 0x00003006061a7981 */
/* 0x000eea000c1e9b00 */
/*0380*/ DFMA R24, R8.reuse, R24, R20 ; /* 0x000000180818722b */
/* 0x0502a40000000014 */
/*0390*/ LDG.E.64.CONSTANT R20, [R6.64+0x20] ; /* 0x0000200606147981 */
/* 0x002f28000c1e9b00 */
/*03a0*/ DFMA R24, R8, R24, R22 ; /* 0x000000180818722b */
/* 0x0042c40000000016 */
/*03b0*/ LDG.E.64.CONSTANT R22, [R6.64+0x28] ; /* 0x0000280606167981 */
/* 0x002ea8000c1e9b00 */
/*03c0*/ DFMA R18, R8.reuse, R24, R18 ; /* 0x000000180812722b */
/* 0x048f220000000012 */
/*03d0*/ BSSY B0, 0x5a0 ; /* 0x000001c000007945 */
/* 0x000fea0003800000 */
/*03e0*/ DFMA R18, R8, R18, R20 ; /* 0x000000120812722b */
/* 0x010e8c0000000014 */
/*03f0*/ DFMA R18, R8, R18, R22 ; /* 0x000000120812722b */
/* 0x004e4c0000000016 */
/*0400*/ DFMA R18, R8, R18, R26 ; /* 0x000000120812722b */
/* 0x002e4c000000001a */
/*0410*/ DFMA R4, R18, R4, R4 ; /* 0x000000041204722b */
/* 0x002fc80000000004 */
/*0420*/ @P0 DFMA R4, R8, R18, 1 ; /* 0x3ff000000804042b */
/* 0x000e4c0000000012 */
/*0430*/ @P1 DFMA R4, R4, -1, RZ ; /* 0xbff000000404182b */
/* 0x002e4e00000000ff */
/*0440*/ STG.E.64 [R10.64], R4 ; /* 0x000000040a007986 */
/* 0x0023e2000c101b06 */
/*0450*/ @P2 BRA 0x570 ; /* 0x0000011000002947 */
/* 0x000fea0003800000 */
/*0460*/ F2I.F64 R0, R14 ; /* 0x0000000e00007311 */
/* 0x001e220000301100 */
/*0470*/ DSETP.GE.AND P0, PT, |R16|, 2.14748364800000000000e+09, PT ; /* 0x41e000001000742a */
/* 0x000fce0003f06200 */
/*0480*/ I2F.F64 R12, R0 ; /* 0x00000000000c7312 */
/* 0x001e220000201c00 */
/*0490*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0005e20000100800 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*04b0*/ DFMA R4, -R12, c[0x2][0x18], R16 ; /* 0x008006000c047a2b */
/* 0x003e0c0000000110 */
/*04c0*/ DFMA R4, -R12, c[0x2][0x20], R4 ; /* 0x008008000c047a2b */
/* 0x001e0c0000000104 */
/*04d0*/ DFMA R4, -R12, c[0x2][0x28], R4 ; /* 0x00800a000c047a2b */
/* 0x0014220000000104 */
/*04e0*/ @!P0 BRA 0x590 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*04f0*/ BSSY B1, 0x550 ; /* 0x0000005000017945 */
/* 0x000fe20003800000 */
/*0500*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0010 */
/*0510*/ MOV R2, 0x540 ; /* 0x0000054000027802 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0011 */
/*0530*/ CALL.REL.NOINC 0x780 ; /* 0x0000024000007944 */
/* 0x004fea0003c00000 */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x0001620000100800 */
/*0560*/ BRA 0x590 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0570*/ DMUL R4, RZ, R16 ; /* 0x00000010ff047228 */
/* 0x0022a20000000000 */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fca00078e00ff */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.SHL.U32 R6, R2, 0x8, RZ ; /* 0x0000000802067824 */
/* 0x020fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc600078e00ff */
/*05c0*/ LOP3.LUT R6, R6, 0x8, RZ, 0xc0, !PT ; /* 0x0000000806067812 */
/* 0x000fca00078ec0ff */
/*05d0*/ IMAD.WIDE R6, R6, R7, c[0x4][0x0] ; /* 0x0100000006067625 */
/* 0x000fca00078e0207 */
/*05e0*/ LDG.E.64.CONSTANT R20, [R6.64+0x8] ; /* 0x0000080606147981 */
/* 0x000ee8000c1e9b00 */
/*05f0*/ LDG.E.64.CONSTANT R22, [R6.64+0x10] ; /* 0x0000100606167981 */
/* 0x000f22000c1e9b00 */
/*0600*/ R2P PR, R2, 0x3 ; /* 0x0000000302007804 */
/* 0x000fe20000000000 */
/*0610*/ IMAD.MOV.U32 R24, RZ, RZ, 0x79785eba ; /* 0x79785ebaff187424 */
/* 0x000fe200078e00ff */
/*0620*/ DMUL R8, R4, R4 ; /* 0x0000000404087228 */
/* 0x005ee20000000000 */
/*0630*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3de5db65 ; /* 0x3de5db65ff027424 */
/* 0x000fe200078e00ff */
/*0640*/ LDG.E.64.CONSTANT R18, [R6.64+0x18] ; /* 0x0000180606127981 */
/* 0x000ea4000c1e9b00 */
/*0650*/ FSEL R24, -R24, 4.2945490664224492434e-19, !P0 ; /* 0x20fd816418187808 */
/* 0x000fc40004000100 */
/*0660*/ FSEL R25, R2, -0.082518599927425384521, !P0 ; /* 0xbda8ff8302197808 */
/* 0x000fe20004000000 */
/*0670*/ LDG.E.64.CONSTANT R26, [R6.64+0x30] ; /* 0x00003006061a7981 */
/* 0x000eaa000c1e9b00 */
/*0680*/ DFMA R24, R8.reuse, R24, R20 ; /* 0x000000180818722b */
/* 0x0481240000000014 */
/*0690*/ LDG.E.64.CONSTANT R20, [R6.64+0x20] ; /* 0x0000200606147981 */
/* 0x001ee8000c1e9b00 */
/*06a0*/ DFMA R24, R8, R24, R22 ; /* 0x000000180818722b */
/* 0x0100840000000016 */
/*06b0*/ LDG.E.64.CONSTANT R22, [R6.64+0x28] ; /* 0x0000280606167981 */
/* 0x001f28000c1e9b00 */
/*06c0*/ DFMA R18, R8, R24, R18 ; /* 0x000000180812722b */
/* 0x004ecc0000000012 */
/*06d0*/ DFMA R18, R8, R18, R20 ; /* 0x000000120812722b */
/* 0x008f0c0000000014 */
/*06e0*/ DFMA R18, R8, R18, R22 ; /* 0x000000120812722b */
/* 0x010e0c0000000016 */
/*06f0*/ DFMA R18, R8, R18, R26 ; /* 0x000000120812722b */
/* 0x001e0c000000001a */
/*0700*/ DFMA R4, R18, R4, R4 ; /* 0x000000041204722b */
/* 0x001fc80000000004 */
/*0710*/ @P0 DFMA R4, R8, R18, 1 ; /* 0x3ff000000804042b */
/* 0x000e0c0000000012 */
/*0720*/ @P1 DFMA R4, R4, -1, RZ ; /* 0xbff000000404182b */
/* 0x001e0e00000000ff */
/*0730*/ STG.E.64 [R10.64+0x8], R4 ; /* 0x000008040a007986 */
/* 0x0011e2000c101b06 */
/*0740*/ IADD3 R2, P0, R10, 0x10, RZ ; /* 0x000000100a027810 */
/* 0x000fca0007f1e0ff */
/*0750*/ IMAD.X R9, RZ, RZ, R11, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e060b */
/*0760*/ @P3 BRA 0x120 ; /* 0xfffff9b000003947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ SHF.R.U32.HI R4, RZ, 0x14, R5 ; /* 0x00000014ff047819 */
/* 0x000fc80000011605 */
/*0790*/ LOP3.LUT R4, R4, 0x7ff, RZ, 0xc0, !PT ; /* 0x000007ff04047812 */
/* 0x000fc800078ec0ff */
/*07a0*/ ISETP.NE.AND P0, PT, R4, 0x7ff, PT ; /* 0x000007ff0400780c */
/* 0x000fda0003f05270 */
/*07b0*/ @!P0 BRA 0x1090 ; /* 0x000008d000008947 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R6, R4, -0x400, RZ ; /* 0xfffffc0004067810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ BSSY B2, 0xab0 ; /* 0x000002d000027945 */
/* 0x000fe20003800000 */
/*07e0*/ IADD3 R8, R1, 0x8, RZ ; /* 0x0000000801087810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0800*/ SHF.R.U32.HI R7, RZ, 0x6, R6 ; /* 0x00000006ff077819 */
/* 0x000fe40000011606 */
/*0810*/ LOP3.LUT P4, R6, R6, 0x3f, RZ, 0xc0, !PT ; /* 0x0000003f06067812 */
/* 0x000fe4000788c0ff */
/*0820*/ IADD3 R9, -R7.reuse, 0x10, RZ ; /* 0x0000001007097810 */
/* 0x040fe40007ffe1ff */
/*0830*/ IADD3 R4, -R7, 0x13, RZ ; /* 0x0000001307047810 */
/* 0x000fc40007ffe1ff */
/*0840*/ ISETP.GT.AND P0, PT, R9, 0xe, PT ; /* 0x0000000e0900780c */
/* 0x000fe40003f04270 */
/*0850*/ IADD3 R7, -R7, 0xf, RZ ; /* 0x0000000f07077810 */
/* 0x000fe40007ffe1ff */
/*0860*/ SEL R4, R4, 0x12, !P0 ; /* 0x0000001204047807 */
/* 0x000fc80004000000 */
/*0870*/ ISETP.GT.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fe20003f04270 */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0007 */
/*0890*/ @P0 BRA 0xaa0 ; /* 0x0000020000000947 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x8 ; /* 0x00000008ff167424 */
/* 0x000fe200078e00ff */
/*08b0*/ SHF.L.U64.HI R27, R18.reuse, 0xb, R5 ; /* 0x0000000b121b7819 */
/* 0x040fe20000010205 */
/*08c0*/ IMAD.SHL.U32 R25, R18, 0x800, RZ ; /* 0x0000080012197824 */
/* 0x000fe200078e00ff */
/*08d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*08e0*/ IMAD.WIDE R22, R7, R22, c[0x4][0x8] ; /* 0x0100020007167625 */
/* 0x000fe200078e0216 */
/*08f0*/ LOP3.LUT R27, R27, 0x80000000, RZ, 0xfc, !PT ; /* 0x800000001b1b7812 */
/* 0x000fc600078efcff */
/*0900*/ IMAD.MOV.U32 R24, RZ, RZ, R8 ; /* 0x000000ffff187224 */
/* 0x000fe400078e0008 */
/*0910*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0920*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0930*/ LDG.E.64.CONSTANT R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea2000c1e9b00 */
/*0940*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*0950*/ IMAD.WIDE.U32 R20, P5, R18, R25, R20 ; /* 0x0000001912147225 */
/* 0x004fc800078a0014 */
/*0960*/ IMAD R29, R18.reuse, R27.reuse, RZ ; /* 0x0000001b121d7224 */
/* 0x0c0fe400078e02ff */
/*0970*/ IMAD.HI.U32 R18, R18, R27, RZ ; /* 0x0000001b12127227 */
/* 0x000fc600078e00ff */
/*0980*/ IADD3 R21, P0, R29, R21, RZ ; /* 0x000000151d157210 */
/* 0x000fe20007f1e0ff */
/*0990*/ IMAD R26, R19, R25.reuse, RZ ; /* 0x00000019131a7224 */
/* 0x080fe400078e02ff */
/*09a0*/ IMAD.X R18, RZ, RZ, R18, P5 ; /* 0x000000ffff127224 */
/* 0x000fe200028e0612 */
/*09b0*/ ISETP.GE.AND P5, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fe20003fa6270 */
/*09c0*/ IMAD.HI.U32 R29, R19, R25, RZ ; /* 0x00000019131d7227 */
/* 0x000fe200078e00ff */
/*09d0*/ IADD3 R21, P1, R26, R21, RZ ; /* 0x000000151a157210 */
/* 0x000fc80007f3e0ff */
/*09e0*/ IADD3.X R26, P0, R29, R18, RZ, P0, !PT ; /* 0x000000121d1a7210 */
/* 0x000fe2000071e4ff */
/*09f0*/ IMAD.HI.U32 R18, R19.reuse, R27.reuse, RZ ; /* 0x0000001b13127227 */
/* 0x0c0fe200078e00ff */
/*0a00*/ STL.64 [R24], R20 ; /* 0x0000001418007387 */
/* 0x0001e60000100a00 */
/*0a10*/ IMAD R19, R19, R27, RZ ; /* 0x0000001b13137224 */
/* 0x000fe400078e02ff */
/*0a20*/ IMAD.X R18, RZ, RZ, R18, P0 ; /* 0x000000ffff127224 */
/* 0x000fe200000e0612 */
/*0a30*/ IADD3 R22, P0, R22, 0x8, RZ ; /* 0x0000000816167810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3.X R26, P1, R19, R26, RZ, P1, !PT ; /* 0x0000001a131a7210 */
/* 0x000fc60000f3e4ff */
/*0a50*/ IMAD.X R23, RZ, RZ, R23, P0 ; /* 0x000000ffff177224 */
/* 0x000fe200000e0617 */
/*0a60*/ IADD3 R24, R24, 0x8, RZ ; /* 0x0000000818187810 */
/* 0x001fe20007ffe0ff */
/*0a70*/ IMAD.X R21, RZ, RZ, R18, P1 ; /* 0x000000ffff157224 */
/* 0x000fe400008e0612 */
/*0a80*/ IMAD.MOV.U32 R20, RZ, RZ, R26 ; /* 0x000000ffff147224 */
/* 0x000fe200078e001a */
/*0a90*/ @!P5 BRA 0x920 ; /* 0xfffffe800000d947 */
/* 0x000fea000383ffff */
/*0aa0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD.IADD R7, R9, 0x1, -R7 ; /* 0x0000000109077824 */
/* 0x000fc800078e0a07 */
/*0ac0*/ IMAD R27, R7, 0x8, R8 ; /* 0x00000008071b7824 */
/* 0x000fca00078e0208 */
/*0ad0*/ STL.64 [R27], R20 ; /* 0x000000141b007387 */
/* 0x0001e80000100a00 */
/*0ae0*/ @P4 LDL.64 R22, [R1+0x10] ; /* 0x0000100001164983 */
/* 0x000ea80000100a00 */
/*0af0*/ LDL.64 R18, [R1+0x18] ; /* 0x0000180001127983 */
/* 0x000ee80000100a00 */
/*0b00*/ LDL.64 R8, [R1+0x20] ; /* 0x0000200001087983 */
/* 0x000e220000100a00 */
/*0b10*/ @P4 IADD3 R7, -R6, 0x40, RZ ; /* 0x0000004006074810 */
/* 0x000fe20007ffe1ff */
/*0b20*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0b30*/ @P4 SHF.R.U64 R4, R22, R7.reuse, R23.reuse ; /* 0x0000000716044219 */
/* 0x184fe40000001217 */
/*0b40*/ @P4 SHF.R.U32.HI R22, RZ, R7.reuse, R23 ; /* 0x00000007ff164219 */
/* 0x080fe40000011617 */
/*0b50*/ @P4 SHF.L.U32 R25, R18.reuse, R6.reuse, RZ ; /* 0x0000000612194219 */
/* 0x0c8fe400000006ff */
/*0b60*/ @P4 SHF.R.U64 R24, R18.reuse, R7, R19.reuse ; /* 0x0000000712184219 */
/* 0x140fe40000001213 */
/*0b70*/ @P4 SHF.L.U64.HI R23, R18, R6.reuse, R19 ; /* 0x0000000612174219 */
/* 0x080fe40000010213 */
/*0b80*/ @P4 SHF.L.U32 R21, R8, R6, RZ ; /* 0x0000000608154219 */
/* 0x001fc400000006ff */
/*0b90*/ @P4 SHF.R.U32.HI R7, RZ, R7, R19 ; /* 0x00000007ff074219 */
/* 0x000fe40000011613 */
/*0ba0*/ @P4 SHF.L.U64.HI R20, R8, R6, R9 ; /* 0x0000000608144219 */
/* 0x000fe40000010209 */
/*0bb0*/ @P4 LOP3.LUT R18, R4, R25, RZ, 0xfc, !PT ; /* 0x0000001904124212 */
/* 0x000fe400078efcff */
/*0bc0*/ @P4 LOP3.LUT R19, R22, R23, RZ, 0xfc, !PT ; /* 0x0000001716134212 */
/* 0x000fe400078efcff */
/*0bd0*/ @P4 LOP3.LUT R8, R21, R24, RZ, 0xfc, !PT ; /* 0x0000001815084212 */
/* 0x000fe400078efcff */
/*0be0*/ SHF.L.U64.HI R6, R18.reuse, 0x2, R19.reuse ; /* 0x0000000212067819 */
/* 0x140fe20000010213 */
/*0bf0*/ IMAD.SHL.U32 R18, R18, 0x4, RZ ; /* 0x0000000412127824 */
/* 0x000fe200078e00ff */
/*0c00*/ SHF.R.U32.HI R4, RZ, 0x1e, R19 ; /* 0x0000001eff047819 */
/* 0x000fe20000011613 */
/*0c10*/ IMAD.SHL.U32 R23, R8, 0x4, RZ ; /* 0x0000000408177824 */
/* 0x000fe200078e00ff */
/*0c20*/ @P4 LOP3.LUT R9, R20, R7, RZ, 0xfc, !PT ; /* 0x0000000714094212 */
/* 0x000fc400078efcff */
/*0c30*/ IADD3 RZ, P0, RZ, -R18, RZ ; /* 0x80000012ffff7210 */
/* 0x000fe40007f1e0ff */
/*0c40*/ LOP3.LUT R7, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff077212 */
/* 0x000fe400078e33ff */
/*0c50*/ LOP3.LUT R23, R4, R23, RZ, 0xfc, !PT ; /* 0x0000001704177212 */
/* 0x000fe400078efcff */
/*0c60*/ SHF.L.U64.HI R20, R8, 0x2, R9 ; /* 0x0000000208147819 */
/* 0x000fe40000010209 */
/*0c70*/ IADD3.X R7, P0, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe4000071e4ff */
/*0c80*/ LOP3.LUT R8, RZ, R23, RZ, 0x33, !PT ; /* 0x00000017ff087212 */
/* 0x000fc400078e33ff */
/*0c90*/ LOP3.LUT R19, RZ, R20, RZ, 0x33, !PT ; /* 0x00000014ff137212 */
/* 0x000fe400078e33ff */
/*0ca0*/ IADD3.X R8, P0, RZ, R8, RZ, P0, !PT ; /* 0x00000008ff087210 */
/* 0x000fe4000071e4ff */
/*0cb0*/ SHF.R.U32.HI R4, RZ, 0x1d, R9 ; /* 0x0000001dff047819 */
/* 0x000fc60000011609 */
/*0cc0*/ IMAD.X R19, RZ, RZ, R19, P0 ; /* 0x000000ffff137224 */
/* 0x000fe200000e0613 */
/*0cd0*/ LOP3.LUT P1, RZ, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104ff7812 */
/* 0x000fc8000782c0ff */
/*0ce0*/ SEL R21, R20, R19, !P1 ; /* 0x0000001314157207 */
/* 0x000fe40004800000 */
/*0cf0*/ SEL R23, R23, R8, !P1 ; /* 0x0000000817177207 */
/* 0x000fe40004800000 */
/*0d00*/ ISETP.NE.U32.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc80003f05070 */
/*0d10*/ SEL R19, R23, R21, !P0 ; /* 0x0000001517137207 */
/* 0x000fcc0004000000 */
/*0d20*/ FLO.U32 R19, R19 ; /* 0x0000001300137300 */
/* 0x000e2400000e0000 */
/*0d30*/ IADD3 R20, -R19.reuse, 0x1f, RZ ; /* 0x0000001f13147810 */
/* 0x041fe40007ffe1ff */
/*0d40*/ IADD3 R8, -R19, 0x3f, RZ ; /* 0x0000003f13087810 */
/* 0x000fc60007ffe1ff */
/*0d50*/ @P0 IMAD.MOV R8, RZ, RZ, R20 ; /* 0x000000ffff080224 */
/* 0x000fca00078e0214 */
/*0d60*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0d70*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20003f05300 */
/*0d80*/ @P1 IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff121224 */
/* 0x000fe200078e0a12 */
/*0d90*/ SEL R6, R6, R7, !P1 ; /* 0x0000000706067207 */
/* 0x000fe40004800000 */
/*0da0*/ IADD3 R7, -R8, 0x40, RZ ; /* 0x0000004008077810 */
/* 0x000fe40007ffe1ff */
/*0db0*/ SHF.L.U32 R25, R23.reuse, R8.reuse, RZ ; /* 0x0000000817197219 */
/* 0x0c0fe400000006ff */
/*0dc0*/ SHF.R.U64 R18, R18, R7, R6 ; /* 0x0000000712127219 */
/* 0x000fe40000001206 */
/*0dd0*/ SHF.L.U64.HI R27, R23, R8, R21 ; /* 0x00000008171b7219 */
/* 0x000fc60000010215 */
/*0de0*/ @P0 LOP3.LUT R23, R18, R25, RZ, 0xfc, !PT ; /* 0x0000001912170212 */
/* 0x000fe400078efcff */
/*0df0*/ SHF.R.U32.HI R6, RZ, R7, R6 ; /* 0x00000007ff067219 */
/* 0x000fc60000011606 */
/*0e00*/ IMAD.WIDE.U32 R18, R23, 0x2168c235, RZ ; /* 0x2168c23517127825 */
/* 0x000fe200078e00ff */
/*0e10*/ @P0 LOP3.LUT R21, R6, R27, RZ, 0xfc, !PT ; /* 0x0000001b06150212 */
/* 0x000fc600078efcff */
/*0e20*/ IMAD.MOV.U32 R6, RZ, RZ, R19 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0013 */
/*0e30*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0e40*/ IMAD.WIDE.U32 R6, R23, -0x36f0255e, R6 ; /* 0xc90fdaa217067825 */
/* 0x000fc800078e0006 */
/*0e50*/ IMAD.HI.U32 R19, R21, -0x36f0255e, RZ ; /* 0xc90fdaa215137827 */
/* 0x000fc800078e00ff */
/*0e60*/ IMAD.WIDE.U32 R6, P4, R21, 0x2168c235, R6 ; /* 0x2168c23515067825 */
/* 0x000fe20007880006 */
/*0e70*/ IADD3 RZ, P0, R18, R18, RZ ; /* 0x0000001212ff7210 */
/* 0x000fc60007f1e0ff */
/*0e80*/ IMAD R21, R21, -0x36f0255e, RZ ; /* 0xc90fdaa215157824 */
/* 0x000fe400078e02ff */
/*0e90*/ IMAD.X R18, RZ, RZ, R19, P4 ; /* 0x000000ffff127224 */
/* 0x000fc600020e0613 */
/*0ea0*/ IADD3 R7, P4, R21, R7, RZ ; /* 0x0000000715077210 */
/* 0x000fe40007f9e0ff */
/*0eb0*/ IADD3.X RZ, P0, R6, R6, RZ, P0, !PT ; /* 0x0000000606ff7210 */
/* 0x000fe4000071e4ff */
/*0ec0*/ ISETP.GT.U32.AND P5, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe20003fa4070 */
/*0ed0*/ IMAD.X R18, RZ, RZ, R18, P4 ; /* 0x000000ffff127224 */
/* 0x000fe200020e0612 */
/*0ee0*/ IADD3.X R6, P4, R7, R7, RZ, P0, !PT ; /* 0x0000000707067210 */
/* 0x000fc8000079e4ff */
/*0ef0*/ ISETP.GT.AND.EX P0, PT, R18.reuse, RZ, PT, P5 ; /* 0x000000ff1200720c */
/* 0x040fe20003f04350 */
/*0f00*/ IMAD.X R19, R18, 0x1, R18, P4 ; /* 0x0000000112137824 */
/* 0x000fe200020e0612 */
/*0f10*/ LOP3.LUT P4, RZ, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005ff7812 */
/* 0x000fe4000788c0ff */
/*0f20*/ SEL R6, R6, R7, P0 ; /* 0x0000000706067207 */
/* 0x000fe40000000000 */
/*0f30*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x000fe400078ec0ff */
/*0f40*/ SEL R7, R19, R18, P0 ; /* 0x0000001213077207 */
/* 0x000fe40000000000 */
/*0f50*/ IADD3 R18, P5, R6, 0x1, RZ ; /* 0x0000000106127810 */
/* 0x000fc40007fbe0ff */
/*0f60*/ LEA.HI R4, R9, R4, RZ, 0x2 ; /* 0x0000000409047211 */
/* 0x000fc600078f10ff */
/*0f70*/ IMAD.X R7, RZ, RZ, R7, P5 ; /* 0x000000ffff077224 */
/* 0x000fe400028e0607 */
/*0f80*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a04 */
/*0f90*/ IADD3 R19, R28, -c[0x0][0x20], RZ ; /* 0x800008001c137a10 */
/* 0x000fe40007ffe0ff */
/*0fa0*/ SHF.R.U64 R18, R18, 0xa, R7 ; /* 0x0000000a12127819 */
/* 0x000fe20000001207 */
/*0fb0*/ @P4 IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff044224 */
/* 0x000fe200078e0006 */
/*0fc0*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fe40004000000 */
/*0fd0*/ IADD3 R18, P4, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007f9e0ff */
/*0fe0*/ STL [R19], R4 ; /* 0x0000000413007387 */
/* 0x0001e40000100800 */
/*0ff0*/ LEA.HI.X R7, R7, RZ, RZ, 0x16, P4 ; /* 0x000000ff07077211 */
/* 0x000fe200020fb4ff */
/*1000*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fc600078e0208 */
/*1010*/ SHF.R.U64 R18, R18, 0x1, R7.reuse ; /* 0x0000000112127819 */
/* 0x100fe20000001207 */
/*1020*/ IMAD.SHL.U32 R9, R9, 0x100000, RZ ; /* 0x0010000009097824 */
/* 0x000fe200078e00ff */
/*1030*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fe400078ec0ff */
/*1040*/ SHF.R.U32.HI R6, RZ, 0x1, R7 ; /* 0x00000001ff067819 */
/* 0x000fe40000011607 */
/*1050*/ IADD3 R18, P0, P4, R18, -UR4, RZ ; /* 0x8000000412127c10 */
/* 0x000fe4000fc1e0ff */
/*1060*/ @P1 LOP3.LUT R5, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005051812 */
/* 0x000fe400078e3cff */
/*1070*/ IADD3.X R6, R6, 0x3fe00000, ~R9, P0, P4 ; /* 0x3fe0000006067810 */
/* 0x000fc800007e8c09 */
/*1080*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe400078efcff */
/*1090*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*10a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fe400078e00ff */
/*10b0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0012 */
/*10c0*/ RET.REL.NODEC R6 0x0 ; /* 0xffffef3006007950 */
/* 0x000fea0003c3ffff */
/*10d0*/ BRA 0x10d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define NUM 1024
cudaError_t addWithCuda(double *c, const double *a, const double *b, long size);
__device__ double test(int i);
__global__ void addKernel(double *c, const double *a, const double *b)
{
int i = threadIdx.x;
for (int j = 0; j < NUM; j++) {
c[j] = test(i);
}
}
__device__ double test(int i) {
double tmp = (i - 9.9) * 3.1415926 * 3.1415926;
double ret = sin(tmp);
return ret;
}
int main()
{
const double a[NUM] = { 1, 2, 3, 4, 5 };
const double b[NUM] = { 10, 20, 30, 40, 50 };
double c[NUM] = { 0 };
// Add vectors in parallel.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaError_t cudaStatus = addWithCuda(c, a, b, NUM);
cudaEventRecord(stop, 0);
//confirm that all things have been done before "stop event"
cudaEventSynchronize(stop);
float elapseTime;
cudaEventElapsedTime(&elapseTime, start, stop);
printf("Time for I/O : %.5f ms\n", elapseTime);
printf("%.6f\n", c[2]);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(double *c, const double *a, const double *b, long size)
{
double *dev_a = 0;
double *dev_b = 0;
double *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | .file "tmpxft_00038fbe_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4testi
.type _Z4testi, @function
_Z4testi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4testi, .-_Z4testi
.globl _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
.type _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_, @function
_Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPdPKdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_, .-_Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
.globl _Z9addKernelPdPKdS1_
.type _Z9addKernelPdPKdS1_, @function
_Z9addKernelPdPKdS1_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9addKernelPdPKdS1_, .-_Z9addKernelPdPKdS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z11addWithCudaPdPKdS1_l
.type _Z11addWithCudaPdPKdS1_l, @function
_Z11addWithCudaPdPKdS1_l:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L26
leaq 0(,%rbp,8), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L21:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L15
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L26:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L15:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L28:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L29:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L31:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L32:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
jmp .L21
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L34:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11addWithCudaPdPKdS1_l, .-_Z11addWithCudaPdPKdS1_l
.section .rodata.str1.1
.LC15:
.string "Time for I/O : %.5f ms\n"
.LC16:
.string "%.6f\n"
.LC17:
.string "addWithCuda failed!"
.LC18:
.string "cudaDeviceReset failed!"
.LC19:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -24576(%rsp), %r11
.cfi_def_cfa 11, 24592
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $48, %rsp
.cfi_def_cfa_offset 24640
movq %fs:40, %rax
movq %rax, 24616(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1024, %ecx
rep stosq
movq .LC5(%rip), %rbx
movq %rbx, 32(%rsp)
movq .LC6(%rip), %rbx
movq %rbx, 40(%rsp)
movq .LC7(%rip), %rbx
movq %rbx, 48(%rsp)
movq .LC8(%rip), %rdx
movq %rdx, 56(%rsp)
movq .LC9(%rip), %rcx
movq %rcx, 64(%rsp)
leaq 8224(%rsp), %rdi
movl $1024, %ecx
rep stosq
movq .LC10(%rip), %rbx
movq %rbx, 8224(%rsp)
movq .LC11(%rip), %rdx
movq %rdx, 8232(%rsp)
movq .LC12(%rip), %rcx
movq %rcx, 8240(%rsp)
movq .LC13(%rip), %rbx
movq %rbx, 8248(%rsp)
movq .LC14(%rip), %rdx
movq %rdx, 8256(%rsp)
leaq 16416(%rsp), %rdi
movl $1024, %ecx
rep stosq
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8224(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq 16416(%rsp), %rdi
movl $1024, %ecx
call _Z11addWithCudaPdPKdS1_l
movl %eax, %ebx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16432(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jne .L42
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L43
leaq .LC19(%rip), %rdi
call system@PLT
movl $0, %eax
.L36:
movq 24616(%rsp), %rdx
subq %fs:40, %rdx
jne .L44
addq $24624, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L36
.L43:
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z9addKernelPdPKdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPdPKdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long 0
.long 1073741824
.align 8
.LC7:
.long 0
.long 1074266112
.align 8
.LC8:
.long 0
.long 1074790400
.align 8
.LC9:
.long 0
.long 1075052544
.align 8
.LC10:
.long 0
.long 1076101120
.align 8
.LC11:
.long 0
.long 1077149696
.align 8
.LC12:
.long 0
.long 1077805056
.align 8
.LC13:
.long 0
.long 1078198272
.align 8
.LC14:
.long 0
.long 1078525952
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define NUM 1024
cudaError_t addWithCuda(double *c, const double *a, const double *b, long size);
__device__ double test(int i);
__global__ void addKernel(double *c, const double *a, const double *b)
{
int i = threadIdx.x;
for (int j = 0; j < NUM; j++) {
c[j] = test(i);
}
}
__device__ double test(int i) {
double tmp = (i - 9.9) * 3.1415926 * 3.1415926;
double ret = sin(tmp);
return ret;
}
int main()
{
const double a[NUM] = { 1, 2, 3, 4, 5 };
const double b[NUM] = { 10, 20, 30, 40, 50 };
double c[NUM] = { 0 };
// Add vectors in parallel.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaError_t cudaStatus = addWithCuda(c, a, b, NUM);
cudaEventRecord(stop, 0);
//confirm that all things have been done before "stop event"
cudaEventSynchronize(stop);
float elapseTime;
cudaEventElapsedTime(&elapseTime, start, stop);
printf("Time for I/O : %.5f ms\n", elapseTime);
printf("%.6f\n", c[2]);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(double *c, const double *a, const double *b, long size)
{
double *dev_a = 0;
double *dev_b = 0;
double *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(double));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define NUM 1024
hipError_t addWithCuda(double *c, const double *a, const double *b, long size);
__device__ double test(int i);
__global__ void addKernel(double *c, const double *a, const double *b)
{
int i = threadIdx.x;
for (int j = 0; j < NUM; j++) {
c[j] = test(i);
}
}
__device__ double test(int i) {
double tmp = (i - 9.9) * 3.1415926 * 3.1415926;
double ret = sin(tmp);
return ret;
}
int main()
{
const double a[NUM] = { 1, 2, 3, 4, 5 };
const double b[NUM] = { 10, 20, 30, 40, 50 };
double c[NUM] = { 0 };
// Add vectors in parallel.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipError_t cudaStatus = addWithCuda(c, a, b, NUM);
hipEventRecord(stop, 0);
//confirm that all things have been done before "stop event"
hipEventSynchronize(stop);
float elapseTime;
hipEventElapsedTime(&elapseTime, start, stop);
printf("Time for I/O : %.5f ms\n", elapseTime);
printf("%.6f\n", c[2]);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(double *c, const double *a, const double *b, long size)
{
double *dev_a = 0;
double *dev_b = 0;
double *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define NUM 1024
hipError_t addWithCuda(double *c, const double *a, const double *b, long size);
__device__ double test(int i);
__global__ void addKernel(double *c, const double *a, const double *b)
{
int i = threadIdx.x;
for (int j = 0; j < NUM; j++) {
c[j] = test(i);
}
}
__device__ double test(int i) {
double tmp = (i - 9.9) * 3.1415926 * 3.1415926;
double ret = sin(tmp);
return ret;
}
int main()
{
const double a[NUM] = { 1, 2, 3, 4, 5 };
const double b[NUM] = { 10, 20, 30, 40, 50 };
double c[NUM] = { 0 };
// Add vectors in parallel.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipError_t cudaStatus = addWithCuda(c, a, b, NUM);
hipEventRecord(stop, 0);
//confirm that all things have been done before "stop event"
hipEventSynchronize(stop);
float elapseTime;
hipEventElapsedTime(&elapseTime, start, stop);
printf("Time for I/O : %.5f ms\n", elapseTime);
printf("%.6f\n", c[2]);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(double *c, const double *a, const double *b, long size)
{
double *dev_a = 0;
double *dev_b = 0;
double *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPdPKdS1_
.globl _Z9addKernelPdPKdS1_
.p2align 8
.type _Z9addKernelPdPKdS1_,@function
_Z9addKernelPdPKdS1_:
v_cvt_f64_i32_e32 v[0:1], v0
s_mov_b32 s3, 0xc023cccc
s_mov_b32 s2, 0xcccccccd
v_mov_b32_e32 v24, 0
s_mov_b32 s5, 0x3fe45f30
s_mov_b32 s4, 0x6dc9c883
s_mov_b32 s7, 0xbc91a626
s_mov_b32 s6, 0x33145c00
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], s[2:3]
s_mov_b32 s3, 0x400921fb
s_mov_b32 s2, 0x4d12d84a
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[0:1], v[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[2:3]
s_mov_b32 s3, 0x3ff921fb
v_ldexp_f64 v[2:3], |v[0:1]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[0:1]|
v_trig_preop_f64 v[4:5], |v[0:1]|, 0
v_and_b32_e32 v6, 0x7fffffff, v1
v_trig_preop_f64 v[16:17], |v[0:1]|, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v6, v3 :: v_dual_cndmask_b32 v2, v0, v2
v_trig_preop_f64 v[6:7], |v[0:1]|, 1
v_mul_f64 v[8:9], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[22:23], v[16:17], v[2:3]
v_mul_f64 v[10:11], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[4:5], v[2:3], -v[8:9]
v_fma_f64 v[6:7], v[6:7], v[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[2:3], v[16:17], v[2:3], -v[22:23]
v_add_f64 v[12:13], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[10:11]
v_add_f64 v[20:21], v[8:9], v[12:13]
v_add_f64 v[18:19], v[12:13], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ldexp_f64 v[14:15], v[20:21], -2
v_add_f64 v[8:9], v[20:21], -v[8:9]
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[18:19], v[22:23], v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
v_add_f64 v[8:9], v[12:13], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[10:11]
v_fract_f64_e32 v[10:11], v[14:15]
v_add_f64 v[12:13], v[18:19], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
v_ldexp_f64 v[10:11], v[10:11], 2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[20:21], v[14:15], v[10:11]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21]
v_add_f64 v[20:21], v[18:19], -v[22:23]
v_add_f64 v[8:9], v[12:13], -v[8:9]
v_cndmask_b32_e64 v25, 0, 0x40100000, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[29:30], v[18:19], -v[20:21]
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[10:11], v[10:11], v[24:25]
v_add_f64 v[25:26], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[22:23], -v[29:30]
v_add_f64 v[27:28], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_3)
v_add_f64 v[31:32], v[12:13], -v[25:26]
v_add_f64 v[4:5], v[4:5], -v[25:26]
v_mul_f64 v[12:13], |v[0:1]|, s[4:5]
s_mov_b32 s5, 0x3c91a626
s_mov_b32 s4, 0x33145c07
v_add_f64 v[6:7], v[6:7], v[20:21]
v_cvt_i32_f64_e32 v27, v[27:28]
v_add_f64 v[18:19], v[18:19], -v[31:32]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[25:26], v27
v_add_f64 v[4:5], v[4:5], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[25:26]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[14:15], v[10:11]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[6:7], -v[10:11]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[6:7]
v_add_f64 v[2:3], v[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[14:15], -v[4:5]
v_cndmask_b32_e64 v25, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v26, s2, 0, v27, vcc_lo
s_mov_b32 s2, 0x54442d18
v_cmp_gt_f64_e64 vcc_lo, 0x41d00000, |v[0:1]|
v_add_f64 v[6:7], v[6:7], -v[24:25]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[6:7], v[2:3]
v_mul_f64 v[8:9], v[4:5], s[2:3]
v_add_f64 v[6:7], v[4:5], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[4:5], s[2:3], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[6:7]
v_rndne_f64_e32 v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], s[4:5], v[10:11]
s_mov_b32 s4, 0xf9a43bb8
v_fma_f64 v[2:3], v[2:3], s[2:3], v[4:5]
s_mov_b32 s3, 0xbff921fb
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[6:7], s[6:7]
v_fma_f64 v[10:11], v[6:7], s[2:3], |v[0:1]|
s_mov_b32 s3, 0xb97b839a
s_mov_b32 s2, 0x252049c0
v_add_f64 v[12:13], v[10:11], v[4:5]
v_fma_f64 v[14:15], v[6:7], s[6:7], v[10:11]
s_mov_b32 s7, s5
s_mov_b32 s5, 0x3de5e0b2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[4:5]
v_fma_f64 v[4:5], v[6:7], s[6:7], v[4:5]
s_mov_b32 s7, 0x3ec71de3
s_mov_b32 s6, 0x796cde01
v_add_f64 v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[10:11], -v[4:5]
v_add_f64 v[10:11], v[8:9], v[2:3]
v_fma_f64 v[4:5], v[6:7], s[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[10:11], -v[8:9]
v_cvt_i32_f64_e32 v6, v[6:7]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
v_add_f64 v[12:13], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_cndmask_b32_e32 v6, v26, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v7, 1, v6
v_dual_cndmask_b32 v9, v11, v13 :: v_dual_cndmask_b32 v8, v10, v12
v_add_f64 v[14:15], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[10:11], v[8:9], v[8:9]
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[10:11], s[4:5], s[2:3]
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s2, 0x9037ab78
s_mov_b32 s5, 0xbda907db
s_mov_b32 s4, 0x46cc5e42
v_mul_f64 v[16:17], v[10:11], 0.5
v_fma_f64 v[14:15], v[10:11], s[4:5], s[2:3]
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s2, 0xa17f65f6
s_mov_b32 s5, 0xbf2a01a0
s_mov_b32 s4, 0x19e83e5c
v_mul_f64 v[20:21], v[8:9], -v[10:11]
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_fma_f64 v[12:13], v[10:11], v[12:13], s[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mul_f64 v[4:5], v[2:3], 0.5
v_add_f64 v[18:19], -v[16:17], 1.0
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_mov_b32 s3, 0x3efa01a0
s_mov_b32 s2, 0x19f4ec90
v_fma_f64 v[12:13], v[10:11], v[12:13], s[4:5]
s_mov_b32 s5, 0x3f811111
s_mov_b32 s4, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], -v[18:19], 1.0
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[4:5]
v_add_f64 v[16:17], v[22:23], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[4:5], v[20:21], v[12:13], v[4:5]
v_mul_f64 v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[16:17], v[8:9], -v[2:3], v[16:17]
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[10:11], v[4:5], -v[2:3]
v_fma_f64 v[4:5], v[12:13], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[2:3], v[20:21], s[2:3], v[2:3]
v_cmp_class_f64_e64 s2, v[0:1], 0x1f8
v_lshlrev_b32_e32 v0, 30, v6
v_add_f64 v[4:5], v[18:19], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v1
v_and_b32_e32 v0, 0x80000000, v0
v_add_f64 v[2:3], v[8:9], -v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
v_xor_b32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, 0, v2, s2
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s2
s_mov_b64 s[2:3], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x2000
global_store_b64 v2, v[0:1], s[4:5]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPdPKdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPdPKdS1_, .Lfunc_end0-_Z9addKernelPdPKdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPdPKdS1_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9addKernelPdPKdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define NUM 1024
hipError_t addWithCuda(double *c, const double *a, const double *b, long size);
__device__ double test(int i);
__global__ void addKernel(double *c, const double *a, const double *b)
{
int i = threadIdx.x;
for (int j = 0; j < NUM; j++) {
c[j] = test(i);
}
}
__device__ double test(int i) {
double tmp = (i - 9.9) * 3.1415926 * 3.1415926;
double ret = sin(tmp);
return ret;
}
int main()
{
const double a[NUM] = { 1, 2, 3, 4, 5 };
const double b[NUM] = { 10, 20, 30, 40, 50 };
double c[NUM] = { 0 };
// Add vectors in parallel.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipError_t cudaStatus = addWithCuda(c, a, b, NUM);
hipEventRecord(stop, 0);
//confirm that all things have been done before "stop event"
hipEventSynchronize(stop);
float elapseTime;
hipEventElapsedTime(&elapseTime, start, stop);
printf("Time for I/O : %.5f ms\n", elapseTime);
printf("%.6f\n", c[2]);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(double *c, const double *a, const double *b, long size)
{
double *dev_a = 0;
double *dev_b = 0;
double *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(double));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKernelPdPKdS1_ # -- Begin function _Z24__device_stub__addKernelPdPKdS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPdPKdS1_,@function
_Z24__device_stub__addKernelPdPKdS1_: # @_Z24__device_stub__addKernelPdPKdS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPdPKdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPdPKdS1_, .Lfunc_end0-_Z24__device_stub__addKernelPdPKdS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $24608, %rsp # imm = 0x6020
.cfi_def_cfa_offset 24640
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8224(%rsp), %rbx
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 8224(%rsp)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 8232(%rsp)
movabsq $4613937818241073152, %rax # imm = 0x4008000000000000
movq %rax, 8240(%rsp)
movabsq $4616189618054758400, %rax # imm = 0x4010000000000000
movq %rax, 8248(%rsp)
movabsq $4617315517961601024, %rax # imm = 0x4014000000000000
movq %rax, 8256(%rsp)
leaq 32(%rsp), %r14
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4621819117588971520, %rax # imm = 0x4024000000000000
movq %rax, 32(%rsp)
movabsq $4626322717216342016, %rax # imm = 0x4034000000000000
movq %rax, 40(%rsp)
movabsq $4629137466983448576, %rax # imm = 0x403E000000000000
movq %rax, 48(%rsp)
movabsq $4630826316843712512, %rax # imm = 0x4044000000000000
movq %rax, 56(%rsp)
movabsq $4632233691727265792, %rax # imm = 0x4049000000000000
movq %rax, 64(%rsp)
leaq 16416(%rsp), %r15
movl $8192, %edx # imm = 0x2000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1024, %ecx # imm = 0x400
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq _Z11addWithCudaPdPKdS1_l
movl %eax, %ebx
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movsd 16432(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
testl %ebx, %ebx
jne .LBB1_1
# %bb.3:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl $.L.str.4, %edi
callq system
xorl %eax, %eax
.LBB1_6:
addq $24608, %rsp # imm = 0x6020
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 24640
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $19, %esi
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $22, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_6
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPdPKdS1_l # -- Begin function _Z11addWithCudaPdPKdS1_l
.p2align 4, 0x90
.type _Z11addWithCudaPdPKdS1_l,@function
_Z11addWithCudaPdPKdS1_l: # @_Z11addWithCudaPdPKdS1_l
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_18
# %bb.1:
leaq (,%r15,8), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_13
# %bb.6:
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPdPKdS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_16
.LBB2_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB2_14
.LBB2_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
.LBB2_14:
movl $17, %esi
.LBB2_15:
movl $1, %edx
.LBB2_16:
callq fwrite@PLT
.LBB2_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $63, %esi
jmp .LBB2_15
.LBB2_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_17
.LBB2_20:
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_17
.Lfunc_end2:
.size _Z11addWithCudaPdPKdS1_l, .Lfunc_end2-_Z11addWithCudaPdPKdS1_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPdPKdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPdPKdS1_,@object # @_Z9addKernelPdPKdS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPdPKdS1_
.p2align 3, 0x0
_Z9addKernelPdPKdS1_:
.quad _Z24__device_stub__addKernelPdPKdS1_
.size _Z9addKernelPdPKdS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time for I/O : %.5f ms\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.6f\n"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "addWithCuda failed!"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipDeviceReset failed!"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pause"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.5, 64
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc failed!"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy failed!"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "addKernel launch failed: %s\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.9, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPdPKdS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPdPKdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPdPKdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00038fbe_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4testi
.type _Z4testi, @function
_Z4testi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4testi, .-_Z4testi
.globl _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
.type _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_, @function
_Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPdPKdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_, .-_Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
.globl _Z9addKernelPdPKdS1_
.type _Z9addKernelPdPKdS1_, @function
_Z9addKernelPdPKdS1_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9addKernelPdPKdS1_, .-_Z9addKernelPdPKdS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z11addWithCudaPdPKdS1_l
.type _Z11addWithCudaPdPKdS1_l, @function
_Z11addWithCudaPdPKdS1_l:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L26
leaq 0(,%rbp,8), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L21:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L15
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L26:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L15:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L28:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L29:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L31:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L32:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPdPKdS1_PdPKdS1_
jmp .L21
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L34:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11addWithCudaPdPKdS1_l, .-_Z11addWithCudaPdPKdS1_l
.section .rodata.str1.1
.LC15:
.string "Time for I/O : %.5f ms\n"
.LC16:
.string "%.6f\n"
.LC17:
.string "addWithCuda failed!"
.LC18:
.string "cudaDeviceReset failed!"
.LC19:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -24576(%rsp), %r11
.cfi_def_cfa 11, 24592
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $48, %rsp
.cfi_def_cfa_offset 24640
movq %fs:40, %rax
movq %rax, 24616(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1024, %ecx
rep stosq
movq .LC5(%rip), %rbx
movq %rbx, 32(%rsp)
movq .LC6(%rip), %rbx
movq %rbx, 40(%rsp)
movq .LC7(%rip), %rbx
movq %rbx, 48(%rsp)
movq .LC8(%rip), %rdx
movq %rdx, 56(%rsp)
movq .LC9(%rip), %rcx
movq %rcx, 64(%rsp)
leaq 8224(%rsp), %rdi
movl $1024, %ecx
rep stosq
movq .LC10(%rip), %rbx
movq %rbx, 8224(%rsp)
movq .LC11(%rip), %rdx
movq %rdx, 8232(%rsp)
movq .LC12(%rip), %rcx
movq %rcx, 8240(%rsp)
movq .LC13(%rip), %rbx
movq %rbx, 8248(%rsp)
movq .LC14(%rip), %rdx
movq %rdx, 8256(%rsp)
leaq 16416(%rsp), %rdi
movl $1024, %ecx
rep stosq
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8224(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq 16416(%rsp), %rdi
movl $1024, %ecx
call _Z11addWithCudaPdPKdS1_l
movl %eax, %ebx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16432(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jne .L42
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L43
leaq .LC19(%rip), %rdi
call system@PLT
movl $0, %eax
.L36:
movq 24616(%rsp), %rdx
subq %fs:40, %rdx
jne .L44
addq $24624, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L36
.L43:
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z9addKernelPdPKdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPdPKdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long 0
.long 1073741824
.align 8
.LC7:
.long 0
.long 1074266112
.align 8
.LC8:
.long 0
.long 1074790400
.align 8
.LC9:
.long 0
.long 1075052544
.align 8
.LC10:
.long 0
.long 1076101120
.align 8
.LC11:
.long 0
.long 1077149696
.align 8
.LC12:
.long 0
.long 1077805056
.align 8
.LC13:
.long 0
.long 1078198272
.align 8
.LC14:
.long 0
.long 1078525952
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKernelPdPKdS1_ # -- Begin function _Z24__device_stub__addKernelPdPKdS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPdPKdS1_,@function
_Z24__device_stub__addKernelPdPKdS1_: # @_Z24__device_stub__addKernelPdPKdS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPdPKdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPdPKdS1_, .Lfunc_end0-_Z24__device_stub__addKernelPdPKdS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $24608, %rsp # imm = 0x6020
.cfi_def_cfa_offset 24640
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8224(%rsp), %rbx
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 8224(%rsp)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 8232(%rsp)
movabsq $4613937818241073152, %rax # imm = 0x4008000000000000
movq %rax, 8240(%rsp)
movabsq $4616189618054758400, %rax # imm = 0x4010000000000000
movq %rax, 8248(%rsp)
movabsq $4617315517961601024, %rax # imm = 0x4014000000000000
movq %rax, 8256(%rsp)
leaq 32(%rsp), %r14
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4621819117588971520, %rax # imm = 0x4024000000000000
movq %rax, 32(%rsp)
movabsq $4626322717216342016, %rax # imm = 0x4034000000000000
movq %rax, 40(%rsp)
movabsq $4629137466983448576, %rax # imm = 0x403E000000000000
movq %rax, 48(%rsp)
movabsq $4630826316843712512, %rax # imm = 0x4044000000000000
movq %rax, 56(%rsp)
movabsq $4632233691727265792, %rax # imm = 0x4049000000000000
movq %rax, 64(%rsp)
leaq 16416(%rsp), %r15
movl $8192, %edx # imm = 0x2000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1024, %ecx # imm = 0x400
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq _Z11addWithCudaPdPKdS1_l
movl %eax, %ebx
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movsd 16432(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
testl %ebx, %ebx
jne .LBB1_1
# %bb.3:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl $.L.str.4, %edi
callq system
xorl %eax, %eax
.LBB1_6:
addq $24608, %rsp # imm = 0x6020
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 24640
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $19, %esi
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $22, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_6
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPdPKdS1_l # -- Begin function _Z11addWithCudaPdPKdS1_l
.p2align 4, 0x90
.type _Z11addWithCudaPdPKdS1_l,@function
_Z11addWithCudaPdPKdS1_l: # @_Z11addWithCudaPdPKdS1_l
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_18
# %bb.1:
leaq (,%r15,8), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_13
# %bb.6:
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPdPKdS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_16
.LBB2_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB2_14
.LBB2_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
.LBB2_14:
movl $17, %esi
.LBB2_15:
movl $1, %edx
.LBB2_16:
callq fwrite@PLT
.LBB2_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $63, %esi
jmp .LBB2_15
.LBB2_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_17
.LBB2_20:
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_17
.Lfunc_end2:
.size _Z11addWithCudaPdPKdS1_l, .Lfunc_end2-_Z11addWithCudaPdPKdS1_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPdPKdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPdPKdS1_,@object # @_Z9addKernelPdPKdS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPdPKdS1_
.p2align 3, 0x0
_Z9addKernelPdPKdS1_:
.quad _Z24__device_stub__addKernelPdPKdS1_
.size _Z9addKernelPdPKdS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time for I/O : %.5f ms\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.6f\n"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "addWithCuda failed!"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipDeviceReset failed!"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pause"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.5, 64
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc failed!"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy failed!"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "addKernel launch failed: %s\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.9, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPdPKdS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPdPKdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPdPKdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************************************
*
* (C) Copyright 2010 The Board of Trustees of the
* University of Illinois
* All Rights Reserved
*
***************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <cuda.h>
#include "util.h"
__global__ void histo_prescan_kernel (unsigned int* input, int size, unsigned int* minmax)
{
__shared__ float Avg[PRESCAN_THREADS];
__shared__ float StdDev[PRESCAN_THREADS];
int stride = size/gridDim.x;
int addr = blockIdx.x*stride+threadIdx.x;
int end = blockIdx.x*stride + stride/8; // Only sample 1/8th of the input data
// Compute the average per thread
float avg = 0.0;
unsigned int count = 0;
while (addr < end){
avg += input[addr];
count++;
addr += blockDim.x;
}
avg /= count;
Avg[threadIdx.x] = avg;
// Compute the standard deviation per thread
int addr2 = blockIdx.x*stride+threadIdx.x;
float stddev = 0;
while (addr2 < end){
stddev += (input[addr2]-avg)*(input[addr2]-avg);
addr2 += blockDim.x;
}
stddev /= count;
StdDev[threadIdx.x] = sqrtf(stddev);
#define SUM(stride__)\
if(threadIdx.x < stride__){\
Avg[threadIdx.x] += Avg[threadIdx.x+stride__];\
StdDev[threadIdx.x] += StdDev[threadIdx.x+stride__];\
}
// Add all the averages and standard deviations from all the threads
// and take their arithmetic average (as a simplified approximation of the
// real average and standard deviation.
#if (PRESCAN_THREADS >= 32)
for (int stride = PRESCAN_THREADS/2; stride >= 32; stride = stride >> 1){
__syncthreads();
SUM(stride);
}
#endif
#if (PRESCAN_THREADS >= 16)
SUM(16);
#endif
#if (PRESCAN_THREADS >= 8)
SUM(8);
#endif
#if (PRESCAN_THREADS >= 4)
SUM(4);
#endif
#if (PRESCAN_THREADS >= 2)
SUM(2);
#endif
if (threadIdx.x == 0){
float avg = Avg[0]+Avg[1];
avg /= PRESCAN_THREADS;
float stddev = StdDev[0]+StdDev[1];
stddev /= PRESCAN_THREADS;
// Take the maximum and minimum range from all the blocks. This will
// be the final answer. The standard deviation is taken out to 10 sigma
// away from the average. The value 10 was obtained empirically.
atomicMin(minmax,((unsigned int)(avg-10*stddev))/(KB*1024));
atomicMax(minmax+1,((unsigned int)(avg+10*stddev))/(KB*1024));
}
} | .file "tmpxft_00146a0e_00000000-6_histo_prescan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_
.type _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_, @function
_Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_:
.LFB2081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20histo_prescan_kernelPjiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_, .-_Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_
.globl _Z20histo_prescan_kernelPjiS_
.type _Z20histo_prescan_kernelPjiS_, @function
_Z20histo_prescan_kernelPjiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z20histo_prescan_kernelPjiS_, .-_Z20histo_prescan_kernelPjiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20histo_prescan_kernelPjiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20histo_prescan_kernelPjiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************************************
*
* (C) Copyright 2010 The Board of Trustees of the
* University of Illinois
* All Rights Reserved
*
***************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <cuda.h>
#include "util.h"
__global__ void histo_prescan_kernel (unsigned int* input, int size, unsigned int* minmax)
{
__shared__ float Avg[PRESCAN_THREADS];
__shared__ float StdDev[PRESCAN_THREADS];
int stride = size/gridDim.x;
int addr = blockIdx.x*stride+threadIdx.x;
int end = blockIdx.x*stride + stride/8; // Only sample 1/8th of the input data
// Compute the average per thread
float avg = 0.0;
unsigned int count = 0;
while (addr < end){
avg += input[addr];
count++;
addr += blockDim.x;
}
avg /= count;
Avg[threadIdx.x] = avg;
// Compute the standard deviation per thread
int addr2 = blockIdx.x*stride+threadIdx.x;
float stddev = 0;
while (addr2 < end){
stddev += (input[addr2]-avg)*(input[addr2]-avg);
addr2 += blockDim.x;
}
stddev /= count;
StdDev[threadIdx.x] = sqrtf(stddev);
#define SUM(stride__)\
if(threadIdx.x < stride__){\
Avg[threadIdx.x] += Avg[threadIdx.x+stride__];\
StdDev[threadIdx.x] += StdDev[threadIdx.x+stride__];\
}
// Add all the averages and standard deviations from all the threads
// and take their arithmetic average (as a simplified approximation of the
// real average and standard deviation.
#if (PRESCAN_THREADS >= 32)
for (int stride = PRESCAN_THREADS/2; stride >= 32; stride = stride >> 1){
__syncthreads();
SUM(stride);
}
#endif
#if (PRESCAN_THREADS >= 16)
SUM(16);
#endif
#if (PRESCAN_THREADS >= 8)
SUM(8);
#endif
#if (PRESCAN_THREADS >= 4)
SUM(4);
#endif
#if (PRESCAN_THREADS >= 2)
SUM(2);
#endif
if (threadIdx.x == 0){
float avg = Avg[0]+Avg[1];
avg /= PRESCAN_THREADS;
float stddev = StdDev[0]+StdDev[1];
stddev /= PRESCAN_THREADS;
// Take the maximum and minimum range from all the blocks. This will
// be the final answer. The standard deviation is taken out to 10 sigma
// away from the average. The value 10 was obtained empirically.
atomicMin(minmax,((unsigned int)(avg-10*stddev))/(KB*1024));
atomicMax(minmax+1,((unsigned int)(avg+10*stddev))/(KB*1024));
}
} | /***************************************************************************
*
* (C) Copyright 2010 The Board of Trustees of the
* University of Illinois
* All Rights Reserved
*
***************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#include "util.h"
__global__ void histo_prescan_kernel (unsigned int* input, int size, unsigned int* minmax)
{
__shared__ float Avg[PRESCAN_THREADS];
__shared__ float StdDev[PRESCAN_THREADS];
int stride = size/gridDim.x;
int addr = blockIdx.x*stride+threadIdx.x;
int end = blockIdx.x*stride + stride/8; // Only sample 1/8th of the input data
// Compute the average per thread
float avg = 0.0;
unsigned int count = 0;
while (addr < end){
avg += input[addr];
count++;
addr += blockDim.x;
}
avg /= count;
Avg[threadIdx.x] = avg;
// Compute the standard deviation per thread
int addr2 = blockIdx.x*stride+threadIdx.x;
float stddev = 0;
while (addr2 < end){
stddev += (input[addr2]-avg)*(input[addr2]-avg);
addr2 += blockDim.x;
}
stddev /= count;
StdDev[threadIdx.x] = sqrtf(stddev);
#define SUM(stride__)\
if(threadIdx.x < stride__){\
Avg[threadIdx.x] += Avg[threadIdx.x+stride__];\
StdDev[threadIdx.x] += StdDev[threadIdx.x+stride__];\
}
// Add all the averages and standard deviations from all the threads
// and take their arithmetic average (as a simplified approximation of the
// real average and standard deviation.
#if (PRESCAN_THREADS >= 32)
for (int stride = PRESCAN_THREADS/2; stride >= 32; stride = stride >> 1){
__syncthreads();
SUM(stride);
}
#endif
#if (PRESCAN_THREADS >= 16)
SUM(16);
#endif
#if (PRESCAN_THREADS >= 8)
SUM(8);
#endif
#if (PRESCAN_THREADS >= 4)
SUM(4);
#endif
#if (PRESCAN_THREADS >= 2)
SUM(2);
#endif
if (threadIdx.x == 0){
float avg = Avg[0]+Avg[1];
avg /= PRESCAN_THREADS;
float stddev = StdDev[0]+StdDev[1];
stddev /= PRESCAN_THREADS;
// Take the maximum and minimum range from all the blocks. This will
// be the final answer. The standard deviation is taken out to 10 sigma
// away from the average. The value 10 was obtained empirically.
atomicMin(minmax,((unsigned int)(avg-10*stddev))/(KB*1024));
atomicMax(minmax+1,((unsigned int)(avg+10*stddev))/(KB*1024));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***************************************************************************
*
* (C) Copyright 2010 The Board of Trustees of the
* University of Illinois
* All Rights Reserved
*
***************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#include "util.h"
__global__ void histo_prescan_kernel (unsigned int* input, int size, unsigned int* minmax)
{
__shared__ float Avg[PRESCAN_THREADS];
__shared__ float StdDev[PRESCAN_THREADS];
int stride = size/gridDim.x;
int addr = blockIdx.x*stride+threadIdx.x;
int end = blockIdx.x*stride + stride/8; // Only sample 1/8th of the input data
// Compute the average per thread
float avg = 0.0;
unsigned int count = 0;
while (addr < end){
avg += input[addr];
count++;
addr += blockDim.x;
}
avg /= count;
Avg[threadIdx.x] = avg;
// Compute the standard deviation per thread
int addr2 = blockIdx.x*stride+threadIdx.x;
float stddev = 0;
while (addr2 < end){
stddev += (input[addr2]-avg)*(input[addr2]-avg);
addr2 += blockDim.x;
}
stddev /= count;
StdDev[threadIdx.x] = sqrtf(stddev);
#define SUM(stride__)\
if(threadIdx.x < stride__){\
Avg[threadIdx.x] += Avg[threadIdx.x+stride__];\
StdDev[threadIdx.x] += StdDev[threadIdx.x+stride__];\
}
// Add all the averages and standard deviations from all the threads
// and take their arithmetic average (as a simplified approximation of the
// real average and standard deviation.
#if (PRESCAN_THREADS >= 32)
for (int stride = PRESCAN_THREADS/2; stride >= 32; stride = stride >> 1){
__syncthreads();
SUM(stride);
}
#endif
#if (PRESCAN_THREADS >= 16)
SUM(16);
#endif
#if (PRESCAN_THREADS >= 8)
SUM(8);
#endif
#if (PRESCAN_THREADS >= 4)
SUM(4);
#endif
#if (PRESCAN_THREADS >= 2)
SUM(2);
#endif
if (threadIdx.x == 0){
float avg = Avg[0]+Avg[1];
avg /= PRESCAN_THREADS;
float stddev = StdDev[0]+StdDev[1];
stddev /= PRESCAN_THREADS;
// Take the maximum and minimum range from all the blocks. This will
// be the final answer. The standard deviation is taken out to 10 sigma
// away from the average. The value 10 was obtained empirically.
atomicMin(minmax,((unsigned int)(avg-10*stddev))/(KB*1024));
atomicMax(minmax+1,((unsigned int)(avg+10*stddev))/(KB*1024));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20histo_prescan_kernelPjiS_
.globl _Z20histo_prescan_kernelPjiS_
.p2align 8
.type _Z20histo_prescan_kernelPjiS_,@function
_Z20histo_prescan_kernelPjiS_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_mul_i32 s7, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s3, s7
s_add_i32 s3, s3, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s2, s3
s_mul_i32 s3, s7, s6
s_add_i32 s9, s7, 1
s_sub_i32 s8, s2, s3
s_load_b64 s[2:3], s[0:1], 0x0
s_sub_i32 s10, s8, s6
s_cmp_ge_u32 s8, s6
s_cselect_b32 s7, s9, s7
s_cselect_b32 s8, s10, s8
s_add_i32 s9, s7, 1
s_cmp_ge_u32 s8, s6
s_cselect_b32 s6, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_mul_i32 s8, s6, s15
s_lshr_b32 s7, s7, 29
v_add_nc_u32_e32 v1, s8, v0
s_add_i32 s6, s6, s7
s_mov_b32 s7, exec_lo
s_ashr_i32 s6, s6, 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s8, s6
s_mov_b32 s8, 0
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_4
s_load_b32 s9, s[4:5], 0xc
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, v1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s9, 0xffff
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s10, s10, 1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v5, v3 :: v_dual_add_nc_u32 v2, s9, v2
v_cmp_le_i32_e32 vcc_lo, s6, v2
v_mov_b32_e32 v3, s10
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
v_cvt_f32_u32_e32 v4, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v4, v4, v5
v_div_scale_f32 v7, vcc_lo, v5, v4, v5
s_mov_b32 s7, exec_lo
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v6, v3
v_mul_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v2, v6, v7
v_fmac_f32_e32 v6, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v6, v7
v_div_fmas_f32 v2, v2, v3, v6
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v6, v2, v4, v5
v_mov_b32_e32 v5, 0
ds_store_b32 v3, v6
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_8
s_load_b32 s4, s[4:5], 0xc
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mov_b32 s4, 0
.LBB0_6:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v2, v2
v_dual_sub_f32 v2, v2, v6 :: v_dual_add_nc_u32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s6, v1
v_fmac_f32_e32 v5, v2, v2
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s7
v_div_scale_f32 v1, null, v4, v4, v5
v_div_scale_f32 v7, vcc_lo, v5, v4, v5
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v1, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v6, v2
v_mul_f32_e32 v6, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v1, v6, v7
v_fmac_f32_e32 v6, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v6, v7
v_div_fmas_f32 v1, v1, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v1, v4, v5
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v1
v_fma_f32 v7, -v5, v2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v2, v2, v5, s2
s_movk_i32 s2, 0x100
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_lshlrev_b32_e32 v4, 2, v0
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v2, v2, v1 :: v_dual_add_nc_u32 v1, 0x800, v4
ds_store_b32 v4, v2 offset:2048
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 64
s_mov_b32 s2, s3
s_cbranch_scc1 .LBB0_12
.LBB0_10:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_9
v_add_lshl_u32 v2, s2, v0, 2
ds_load_2addr_stride64_b32 v[4:5], v2 offset1:8
ds_load_b32 v2, v3
ds_load_b32 v6, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v6
ds_store_b32 v3, v2
ds_store_b32 v1, v4
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s3, 64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s3, v2
ds_load_2addr_stride64_b32 v[4:5], v2 offset1:8
ds_load_b32 v2, v3
ds_load_b32 v6, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v6
ds_store_b32 v3, v2
ds_store_b32 v1, v4
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB0_16
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s3, 32
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s3, v2
ds_load_2addr_stride64_b32 v[4:5], v2 offset1:8
ds_load_b32 v2, v3
ds_load_b32 v6, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v6
ds_store_b32 v3, v2
ds_store_b32 v1, v4
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB0_18
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s3, v2
ds_load_2addr_stride64_b32 v[4:5], v2 offset1:8
ds_load_b32 v2, v3
ds_load_b32 v6, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v6
ds_store_b32 v3, v2
ds_store_b32 v1, v4
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_20
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s3, 8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s3, v2
ds_load_2addr_stride64_b32 v[4:5], v2 offset1:8
ds_load_b32 v2, v3
ds_load_b32 v6, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v6
ds_store_b32 v3, v2
ds_store_b32 v1, v4
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_25
v_mov_b32_e32 v0, 0
s_movk_i32 s2, 0x800
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, s2, v0
s_mov_b32 s2, exec_lo
ds_load_2addr_b32 v[1:2], v1 offset1:1
ds_load_2addr_b32 v[3:4], v0 offset1:1
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v1, v1, v2 :: v_dual_add_f32 v2, v3, v4
v_mbcnt_lo_u32_b32 v4, exec_lo, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, 0x3b000000, v1
v_mul_f32_e32 v1, 0x3b000000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v2, 0x41200000, v3
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v1, v2
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v3, 0xaaaaaaab
v_lshrrev_b32_e32 v3, 14, v3
global_atomic_min_u32 v0, v3, s[0:1]
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_25
v_dual_add_f32 v0, v1, v2 :: v_dual_mov_b32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_hi_u32 v0, v0, 0xaaaaaaab
s_delay_alu instid0(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 14, v0
global_atomic_max_u32 v1, v0, s[0:1] offset:4
.LBB0_25:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20histo_prescan_kernelPjiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20histo_prescan_kernelPjiS_, .Lfunc_end0-_Z20histo_prescan_kernelPjiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20histo_prescan_kernelPjiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20histo_prescan_kernelPjiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***************************************************************************
*
* (C) Copyright 2010 The Board of Trustees of the
* University of Illinois
* All Rights Reserved
*
***************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#include "util.h"
__global__ void histo_prescan_kernel (unsigned int* input, int size, unsigned int* minmax)
{
__shared__ float Avg[PRESCAN_THREADS];
__shared__ float StdDev[PRESCAN_THREADS];
int stride = size/gridDim.x;
int addr = blockIdx.x*stride+threadIdx.x;
int end = blockIdx.x*stride + stride/8; // Only sample 1/8th of the input data
// Compute the average per thread
float avg = 0.0;
unsigned int count = 0;
while (addr < end){
avg += input[addr];
count++;
addr += blockDim.x;
}
avg /= count;
Avg[threadIdx.x] = avg;
// Compute the standard deviation per thread
int addr2 = blockIdx.x*stride+threadIdx.x;
float stddev = 0;
while (addr2 < end){
stddev += (input[addr2]-avg)*(input[addr2]-avg);
addr2 += blockDim.x;
}
stddev /= count;
StdDev[threadIdx.x] = sqrtf(stddev);
#define SUM(stride__)\
if(threadIdx.x < stride__){\
Avg[threadIdx.x] += Avg[threadIdx.x+stride__];\
StdDev[threadIdx.x] += StdDev[threadIdx.x+stride__];\
}
// Add all the averages and standard deviations from all the threads
// and take their arithmetic average (as a simplified approximation of the
// real average and standard deviation.
#if (PRESCAN_THREADS >= 32)
for (int stride = PRESCAN_THREADS/2; stride >= 32; stride = stride >> 1){
__syncthreads();
SUM(stride);
}
#endif
#if (PRESCAN_THREADS >= 16)
SUM(16);
#endif
#if (PRESCAN_THREADS >= 8)
SUM(8);
#endif
#if (PRESCAN_THREADS >= 4)
SUM(4);
#endif
#if (PRESCAN_THREADS >= 2)
SUM(2);
#endif
if (threadIdx.x == 0){
float avg = Avg[0]+Avg[1];
avg /= PRESCAN_THREADS;
float stddev = StdDev[0]+StdDev[1];
stddev /= PRESCAN_THREADS;
// Take the maximum and minimum range from all the blocks. This will
// be the final answer. The standard deviation is taken out to 10 sigma
// away from the average. The value 10 was obtained empirically.
atomicMin(minmax,((unsigned int)(avg-10*stddev))/(KB*1024));
atomicMax(minmax+1,((unsigned int)(avg+10*stddev))/(KB*1024));
}
} | .text
.file "histo_prescan.hip"
.globl _Z35__device_stub__histo_prescan_kernelPjiS_ # -- Begin function _Z35__device_stub__histo_prescan_kernelPjiS_
.p2align 4, 0x90
.type _Z35__device_stub__histo_prescan_kernelPjiS_,@function
_Z35__device_stub__histo_prescan_kernelPjiS_: # @_Z35__device_stub__histo_prescan_kernelPjiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20histo_prescan_kernelPjiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__histo_prescan_kernelPjiS_, .Lfunc_end0-_Z35__device_stub__histo_prescan_kernelPjiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20histo_prescan_kernelPjiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20histo_prescan_kernelPjiS_,@object # @_Z20histo_prescan_kernelPjiS_
.section .rodata,"a",@progbits
.globl _Z20histo_prescan_kernelPjiS_
.p2align 3, 0x0
_Z20histo_prescan_kernelPjiS_:
.quad _Z35__device_stub__histo_prescan_kernelPjiS_
.size _Z20histo_prescan_kernelPjiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20histo_prescan_kernelPjiS_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__histo_prescan_kernelPjiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20histo_prescan_kernelPjiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00146a0e_00000000-6_histo_prescan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_
.type _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_, @function
_Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_:
.LFB2081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20histo_prescan_kernelPjiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_, .-_Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_
.globl _Z20histo_prescan_kernelPjiS_
.type _Z20histo_prescan_kernelPjiS_, @function
_Z20histo_prescan_kernelPjiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20histo_prescan_kernelPjiS_PjiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z20histo_prescan_kernelPjiS_, .-_Z20histo_prescan_kernelPjiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20histo_prescan_kernelPjiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20histo_prescan_kernelPjiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histo_prescan.hip"
.globl _Z35__device_stub__histo_prescan_kernelPjiS_ # -- Begin function _Z35__device_stub__histo_prescan_kernelPjiS_
.p2align 4, 0x90
.type _Z35__device_stub__histo_prescan_kernelPjiS_,@function
_Z35__device_stub__histo_prescan_kernelPjiS_: # @_Z35__device_stub__histo_prescan_kernelPjiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20histo_prescan_kernelPjiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__histo_prescan_kernelPjiS_, .Lfunc_end0-_Z35__device_stub__histo_prescan_kernelPjiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20histo_prescan_kernelPjiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20histo_prescan_kernelPjiS_,@object # @_Z20histo_prescan_kernelPjiS_
.section .rodata,"a",@progbits
.globl _Z20histo_prescan_kernelPjiS_
.p2align 3, 0x0
_Z20histo_prescan_kernelPjiS_:
.quad _Z35__device_stub__histo_prescan_kernelPjiS_
.size _Z20histo_prescan_kernelPjiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20histo_prescan_kernelPjiS_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__histo_prescan_kernelPjiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20histo_prescan_kernelPjiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main(int argc, char ** argv){
cudaError_t error;
printf("%s running...\n", argv[0]);
int devCount;
cudaGetDeviceCount(&devCount);
printf("number of devices: %d\n", devCount);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("maxThreadsPerBlock = %d\n", devProp.maxThreadsPerBlock);
printf("max block dimension (%d, %d, %d)\n", devProp.maxThreadsDim[0],
devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("max grid dimension (%d, %d, %d)\n", devProp.maxGridSize[0],
devProp.maxGridSize[1], devProp.maxGridSize[2]);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main(int argc, char ** argv){
cudaError_t error;
printf("%s running...\n", argv[0]);
int devCount;
cudaGetDeviceCount(&devCount);
printf("number of devices: %d\n", devCount);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("maxThreadsPerBlock = %d\n", devProp.maxThreadsPerBlock);
printf("max block dimension (%d, %d, %d)\n", devProp.maxThreadsDim[0],
devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("max grid dimension (%d, %d, %d)\n", devProp.maxGridSize[0],
devProp.maxGridSize[1], devProp.maxGridSize[2]);
return 0;
} | .file "tmpxft_0010fc9a_00000000-6_devprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s running...\n"
.LC1:
.string "number of devices: %d\n"
.LC2:
.string "maxThreadsPerBlock = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "max block dimension (%d, %d, %d)\n"
.align 8
.LC4:
.string "max grid dimension (%d, %d, %d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1064, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 336(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
int main(int argc, char ** argv){
cudaError_t error;
printf("%s running...\n", argv[0]);
int devCount;
cudaGetDeviceCount(&devCount);
printf("number of devices: %d\n", devCount);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("maxThreadsPerBlock = %d\n", devProp.maxThreadsPerBlock);
printf("max block dimension (%d, %d, %d)\n", devProp.maxThreadsDim[0],
devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("max grid dimension (%d, %d, %d)\n", devProp.maxGridSize[0],
devProp.maxGridSize[1], devProp.maxGridSize[2]);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(int argc, char ** argv){
hipError_t error;
printf("%s running...\n", argv[0]);
int devCount;
hipGetDeviceCount(&devCount);
printf("number of devices: %d\n", devCount);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("maxThreadsPerBlock = %d\n", devProp.maxThreadsPerBlock);
printf("max block dimension (%d, %d, %d)\n", devProp.maxThreadsDim[0],
devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("max grid dimension (%d, %d, %d)\n", devProp.maxGridSize[0],
devProp.maxGridSize[1], devProp.maxGridSize[2]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(int argc, char ** argv){
hipError_t error;
printf("%s running...\n", argv[0]);
int devCount;
hipGetDeviceCount(&devCount);
printf("number of devices: %d\n", devCount);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("maxThreadsPerBlock = %d\n", devProp.maxThreadsPerBlock);
printf("max block dimension (%d, %d, %d)\n", devProp.maxThreadsDim[0],
devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("max grid dimension (%d, %d, %d)\n", devProp.maxGridSize[0],
devProp.maxGridSize[1], devProp.maxGridSize[2]);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(int argc, char ** argv){
hipError_t error;
printf("%s running...\n", argv[0]);
int devCount;
hipGetDeviceCount(&devCount);
printf("number of devices: %d\n", devCount);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("maxThreadsPerBlock = %d\n", devProp.maxThreadsPerBlock);
printf("max block dimension (%d, %d, %d)\n", devProp.maxThreadsDim[0],
devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("max grid dimension (%d, %d, %d)\n", devProp.maxGridSize[0],
devProp.maxGridSize[1], devProp.maxGridSize[2]);
return 0;
} | .text
.file "devprop.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 328(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s running...\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number of devices: %d\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "maxThreadsPerBlock = %d\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "max block dimension (%d, %d, %d)\n"
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "max grid dimension (%d, %d, %d)\n"
.size .L.str.4, 33
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010fc9a_00000000-6_devprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s running...\n"
.LC1:
.string "number of devices: %d\n"
.LC2:
.string "maxThreadsPerBlock = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "max block dimension (%d, %d, %d)\n"
.align 8
.LC4:
.string "max grid dimension (%d, %d, %d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1064, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 336(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "devprop.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 328(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s running...\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number of devices: %d\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "maxThreadsPerBlock = %d\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "max block dimension (%d, %d, %d)\n"
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "max grid dimension (%d, %d, %d)\n"
.size .L.str.4, 33
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <curand.h>
#include <curand_kernel.h>
typedef struct mp
{
float x, y; // translation vertex
float a, b, c, d; // scaling/rotation matrix
float p; // mapping probability
} mapping;
__global__ void kernel(float4* d_pointData, int numPoints, mapping *d_mappings, int numMappings)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// If needed for performance, move curand_init to seperate kernel and store
// states in device memory
curandState state;
curand_init((unsigned long long) clock(), index, 0, &state);
// Set up transformation mapping once per block in shared memory
extern __shared__ mapping maps[];
if(threadIdx.x == 0)
{
for(int i = 0; i < numMappings; i++)
maps[i] = d_mappings[i];
}
__syncthreads();
// Initially start at a mapping vertex to guarantee we stay inside the
// iterated function system
int currentTarget = index % numMappings;
float2 currentPosition, newPosition;
currentPosition.x = maps[currentTarget].x;
currentPosition.y = maps[currentTarget].y;
for(int i = index; i < numPoints; i += stride)
{
// set the current vertex to the currentPosition
d_pointData[i].x = currentPosition.x;
d_pointData[i].y = currentPosition.y;
// set the iteration percentage and current target mapping
d_pointData[i].z = i / (float) numPoints;
d_pointData[i].w = currentTarget;
// find random target with given mapping probabilities
// If needed for performance, find method to remove thread divergence
// Note: changing 4 to numMappings in for loop reduced performance 50%
float currentProb = curand_uniform(&state);
float totalProb = 0.0f;
for(int j = 0; j < numMappings; j++)
{
totalProb += maps[j].p;
if(currentProb < totalProb)
{
currentTarget = j;
break;
}
}
// calculate the transformation
// (x_n+1) = (a b)(x_n) + (e)
// (y_n+1) (c d)(y_n) (f)
newPosition.x = maps[currentTarget].a * currentPosition.x +
maps[currentTarget].b * currentPosition.y +
maps[currentTarget].x;
newPosition.y = maps[currentTarget].c * currentPosition.x +
maps[currentTarget].d * currentPosition.y +
maps[currentTarget].y;
currentPosition = newPosition;
}
}
int main() {
const int numBlocks = 1;
const int blockSize = 1024;
const int numMappings = 0;
const int numPoints = 1000000;
mapping *d_map;
float4 *d_glmap;
cudaMalloc(&d_map, sizeof(mapping) * numMappings);
cudaMalloc(&d_glmap, sizeof(float4) * numPoints);
kernel<<<numBlocks, blockSize, numMappings * sizeof(mapping)>>>
((float4*)d_glmap, numPoints, d_map, numMappings);
cudaFree(d_map);
cudaFree(d_glmap);
} | .file "tmpxft_000c8dd5_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2244:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2244:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
.type _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi, @function
_Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi:
.LFB2266:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP6float4iP2mpi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2266:
.size _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi, .-_Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
.globl _Z6kernelP6float4iP2mpi
.type _Z6kernelP6float4iP2mpi, @function
_Z6kernelP6float4iP2mpi:
.LFB2267:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2267:
.size _Z6kernelP6float4iP2mpi, .-_Z6kernelP6float4iP2mpi
.globl main
.type main, @function
main:
.LFB2241:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16000000, %esi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0, %ecx
movq (%rsp), %rdx
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2241:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP6float4iP2mpi"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2269:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP6float4iP2mpi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2269:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand.h>
#include <curand_kernel.h>
typedef struct mp
{
float x, y; // translation vertex
float a, b, c, d; // scaling/rotation matrix
float p; // mapping probability
} mapping;
__global__ void kernel(float4* d_pointData, int numPoints, mapping *d_mappings, int numMappings)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// If needed for performance, move curand_init to seperate kernel and store
// states in device memory
curandState state;
curand_init((unsigned long long) clock(), index, 0, &state);
// Set up transformation mapping once per block in shared memory
extern __shared__ mapping maps[];
if(threadIdx.x == 0)
{
for(int i = 0; i < numMappings; i++)
maps[i] = d_mappings[i];
}
__syncthreads();
// Initially start at a mapping vertex to guarantee we stay inside the
// iterated function system
int currentTarget = index % numMappings;
float2 currentPosition, newPosition;
currentPosition.x = maps[currentTarget].x;
currentPosition.y = maps[currentTarget].y;
for(int i = index; i < numPoints; i += stride)
{
// set the current vertex to the currentPosition
d_pointData[i].x = currentPosition.x;
d_pointData[i].y = currentPosition.y;
// set the iteration percentage and current target mapping
d_pointData[i].z = i / (float) numPoints;
d_pointData[i].w = currentTarget;
// find random target with given mapping probabilities
// If needed for performance, find method to remove thread divergence
// Note: changing 4 to numMappings in for loop reduced performance 50%
float currentProb = curand_uniform(&state);
float totalProb = 0.0f;
for(int j = 0; j < numMappings; j++)
{
totalProb += maps[j].p;
if(currentProb < totalProb)
{
currentTarget = j;
break;
}
}
// calculate the transformation
// (x_n+1) = (a b)(x_n) + (e)
// (y_n+1) (c d)(y_n) (f)
newPosition.x = maps[currentTarget].a * currentPosition.x +
maps[currentTarget].b * currentPosition.y +
maps[currentTarget].x;
newPosition.y = maps[currentTarget].c * currentPosition.x +
maps[currentTarget].d * currentPosition.y +
maps[currentTarget].y;
currentPosition = newPosition;
}
}
int main() {
const int numBlocks = 1;
const int blockSize = 1024;
const int numMappings = 0;
const int numPoints = 1000000;
mapping *d_map;
float4 *d_glmap;
cudaMalloc(&d_map, sizeof(mapping) * numMappings);
cudaMalloc(&d_glmap, sizeof(float4) * numPoints);
kernel<<<numBlocks, blockSize, numMappings * sizeof(mapping)>>>
((float4*)d_glmap, numPoints, d_map, numMappings);
cudaFree(d_map);
cudaFree(d_glmap);
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
typedef struct mp
{
float x, y; // translation vertex
float a, b, c, d; // scaling/rotation matrix
float p; // mapping probability
} mapping;
__global__ void kernel(float4* d_pointData, int numPoints, mapping *d_mappings, int numMappings)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// If needed for performance, move curand_init to seperate kernel and store
// states in device memory
hiprandState state;
hiprand_init((unsigned long long) clock(), index, 0, &state);
// Set up transformation mapping once per block in shared memory
extern __shared__ mapping maps[];
if(threadIdx.x == 0)
{
for(int i = 0; i < numMappings; i++)
maps[i] = d_mappings[i];
}
__syncthreads();
// Initially start at a mapping vertex to guarantee we stay inside the
// iterated function system
int currentTarget = index % numMappings;
float2 currentPosition, newPosition;
currentPosition.x = maps[currentTarget].x;
currentPosition.y = maps[currentTarget].y;
for(int i = index; i < numPoints; i += stride)
{
// set the current vertex to the currentPosition
d_pointData[i].x = currentPosition.x;
d_pointData[i].y = currentPosition.y;
// set the iteration percentage and current target mapping
d_pointData[i].z = i / (float) numPoints;
d_pointData[i].w = currentTarget;
// find random target with given mapping probabilities
// If needed for performance, find method to remove thread divergence
// Note: changing 4 to numMappings in for loop reduced performance 50%
float currentProb = hiprand_uniform(&state);
float totalProb = 0.0f;
for(int j = 0; j < numMappings; j++)
{
totalProb += maps[j].p;
if(currentProb < totalProb)
{
currentTarget = j;
break;
}
}
// calculate the transformation
// (x_n+1) = (a b)(x_n) + (e)
// (y_n+1) (c d)(y_n) (f)
newPosition.x = maps[currentTarget].a * currentPosition.x +
maps[currentTarget].b * currentPosition.y +
maps[currentTarget].x;
newPosition.y = maps[currentTarget].c * currentPosition.x +
maps[currentTarget].d * currentPosition.y +
maps[currentTarget].y;
currentPosition = newPosition;
}
}
int main() {
const int numBlocks = 1;
const int blockSize = 1024;
const int numMappings = 0;
const int numPoints = 1000000;
mapping *d_map;
float4 *d_glmap;
hipMalloc(&d_map, sizeof(mapping) * numMappings);
hipMalloc(&d_glmap, sizeof(float4) * numPoints);
kernel<<<numBlocks, blockSize, numMappings * sizeof(mapping)>>>
((float4*)d_glmap, numPoints, d_map, numMappings);
hipFree(d_map);
hipFree(d_glmap);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
typedef struct mp
{
float x, y; // translation vertex
float a, b, c, d; // scaling/rotation matrix
float p; // mapping probability
} mapping;
__global__ void kernel(float4* d_pointData, int numPoints, mapping *d_mappings, int numMappings)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// If needed for performance, move curand_init to seperate kernel and store
// states in device memory
hiprandState state;
hiprand_init((unsigned long long) clock(), index, 0, &state);
// Set up transformation mapping once per block in shared memory
extern __shared__ mapping maps[];
if(threadIdx.x == 0)
{
for(int i = 0; i < numMappings; i++)
maps[i] = d_mappings[i];
}
__syncthreads();
// Initially start at a mapping vertex to guarantee we stay inside the
// iterated function system
int currentTarget = index % numMappings;
float2 currentPosition, newPosition;
currentPosition.x = maps[currentTarget].x;
currentPosition.y = maps[currentTarget].y;
for(int i = index; i < numPoints; i += stride)
{
// set the current vertex to the currentPosition
d_pointData[i].x = currentPosition.x;
d_pointData[i].y = currentPosition.y;
// set the iteration percentage and current target mapping
d_pointData[i].z = i / (float) numPoints;
d_pointData[i].w = currentTarget;
// find random target with given mapping probabilities
// If needed for performance, find method to remove thread divergence
// Note: changing 4 to numMappings in for loop reduced performance 50%
float currentProb = hiprand_uniform(&state);
float totalProb = 0.0f;
for(int j = 0; j < numMappings; j++)
{
totalProb += maps[j].p;
if(currentProb < totalProb)
{
currentTarget = j;
break;
}
}
// calculate the transformation
// (x_n+1) = (a b)(x_n) + (e)
// (y_n+1) (c d)(y_n) (f)
newPosition.x = maps[currentTarget].a * currentPosition.x +
maps[currentTarget].b * currentPosition.y +
maps[currentTarget].x;
newPosition.y = maps[currentTarget].c * currentPosition.x +
maps[currentTarget].d * currentPosition.y +
maps[currentTarget].y;
currentPosition = newPosition;
}
}
int main() {
const int numBlocks = 1;
const int blockSize = 1024;
const int numMappings = 0;
const int numPoints = 1000000;
mapping *d_map;
float4 *d_glmap;
hipMalloc(&d_map, sizeof(mapping) * numMappings);
hipMalloc(&d_glmap, sizeof(float4) * numPoints);
kernel<<<numBlocks, blockSize, numMappings * sizeof(mapping)>>>
((float4*)d_glmap, numPoints, d_map, numMappings);
hipFree(d_map);
hipFree(d_glmap);
} | .text
.file "main.hip"
.globl _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi # -- Begin function _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.p2align 4, 0x90
.type _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi,@function
_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi: # @_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi, .Lfunc_end0-_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16000000, %esi # imm = 0xF42400
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movl $1000000, 12(%rsp) # imm = 0xF4240
movq %rcx, 80(%rsp)
movl $0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi,@object # @_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi
.section .rodata,"a",@progbits
.globl _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi
.p2align 3, 0x0
_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi:
.quad _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.size _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c8dd5_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2244:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2244:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
.type _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi, @function
_Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi:
.LFB2266:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP6float4iP2mpi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2266:
.size _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi, .-_Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
.globl _Z6kernelP6float4iP2mpi
.type _Z6kernelP6float4iP2mpi, @function
_Z6kernelP6float4iP2mpi:
.LFB2267:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2267:
.size _Z6kernelP6float4iP2mpi, .-_Z6kernelP6float4iP2mpi
.globl main
.type main, @function
main:
.LFB2241:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16000000, %esi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0, %ecx
movq (%rsp), %rdx
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z6kernelP6float4iP2mpiP6float4iP2mpi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2241:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP6float4iP2mpi"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2269:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP6float4iP2mpi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2269:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi # -- Begin function _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.p2align 4, 0x90
.type _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi,@function
_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi: # @_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi, .Lfunc_end0-_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16000000, %esi # imm = 0xF42400
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movl $1000000, 12(%rsp) # imm = 0xF4240
movq %rcx, 80(%rsp)
movl $0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi,@object # @_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi
.section .rodata,"a",@progbits
.globl _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi
.p2align 3, 0x0
_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi:
.quad _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.size _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEiP2mpi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP15HIP_vector_typeIfLj4EEiP2mpi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Tanner Hoelzel
*/
#include <cassert>
#include <unistd.h>
#include <fcntl.h>
#include <cstdio>
#include <string>
void
swap(int &i) {
// Some of the & are superfluous.
i =
(0xff&(i >> 24)) |
(0xff00&(i >> 8)) |
(0xff0000&(i << 8)) |
(0xff000000&(i << 24));
}
int
read_int(int fd) {
int rv;
int i;
rv = read(fd, &i, 4); assert(rv == 4);
swap(i);
return i;
}
void
read_mnist_images(const std::string &fn, float *images, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x803);
int n_images = read_int(fd);
assert(n_images == n);
int n_rows = read_int(fd);
assert(n_rows == 28);
int n_cols = read_int(fd);
assert(n_cols == 28);
for (int i = 0; i < n; i++) {
unsigned char tmp[28*28];
rv = read(fd, tmp, 28*28); assert(rv == 28*28);
for (int r = 0; r < 28*28; r++) {
// Make go from -1 to 1.
images[i*28*28+r] = float(tmp[r])/127.5 - 1;
}
}
rv = close(fd); assert(rv == 0);
}
void
read_mnist_labels(const std::string &fn, unsigned char *labels, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x801);
int n_labels = read_int(fd);
assert(n_labels == n);
rv = read(fd, labels, n); assert(rv == n);
rv = close(fd); assert(rv == 0);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Tanner Hoelzel
*/
#include <cassert>
#include <unistd.h>
#include <fcntl.h>
#include <cstdio>
#include <string>
void
swap(int &i) {
// Some of the & are superfluous.
i =
(0xff&(i >> 24)) |
(0xff00&(i >> 8)) |
(0xff0000&(i << 8)) |
(0xff000000&(i << 24));
}
int
read_int(int fd) {
int rv;
int i;
rv = read(fd, &i, 4); assert(rv == 4);
swap(i);
return i;
}
void
read_mnist_images(const std::string &fn, float *images, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x803);
int n_images = read_int(fd);
assert(n_images == n);
int n_rows = read_int(fd);
assert(n_rows == 28);
int n_cols = read_int(fd);
assert(n_cols == 28);
for (int i = 0; i < n; i++) {
unsigned char tmp[28*28];
rv = read(fd, tmp, 28*28); assert(rv == 28*28);
for (int r = 0; r < 28*28; r++) {
// Make go from -1 to 1.
images[i*28*28+r] = float(tmp[r])/127.5 - 1;
}
}
rv = close(fd); assert(rv == 0);
}
void
read_mnist_labels(const std::string &fn, unsigned char *labels, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x801);
int n_labels = read_int(fd);
assert(n_labels == n);
rv = read(fd, labels, n); assert(rv == n);
rv = close(fd); assert(rv == 0);
} | .file "tmpxft_0016af2c_00000000-6_io.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3079:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapRi
.type _Z4swapRi, @function
_Z4swapRi:
.LFB3073:
.cfi_startproc
endbr64
movl (%rdi), %edx
movl %edx, %eax
sarl $8, %eax
andl $65280, %eax
movl %edx, %ecx
sall $8, %ecx
andl $16711680, %ecx
orl %ecx, %eax
movl %edx, %ecx
sall $24, %ecx
orl %ecx, %eax
shrl $24, %edx
orl %edx, %eax
movl %eax, (%rdi)
ret
.cfi_endproc
.LFE3073:
.size _Z4swapRi, .-_Z4swapRi
.globl _Z8read_inti
.type _Z8read_inti, @function
_Z8read_inti:
.LFB3074:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rbx
movl $4, %ecx
movl $4, %edx
movq %rbx, %rsi
call __read_chk@PLT
movq %rbx, %rdi
call _Z4swapRi
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L7
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3074:
.size _Z8read_inti, .-_Z8read_inti
.globl _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.type _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj, @function
_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj:
.LFB3075:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $808, %rsp
.cfi_def_cfa_offset 848
movq %rsi, %r13
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 792(%rsp)
xorl %eax, %eax
movq (%rdi), %rdi
movl $0, %esi
call __open_2@PLT
movl %eax, %r12d
movl %eax, %edi
call _Z8read_inti
movl %r12d, %edi
call _Z8read_inti
movl %r12d, %edi
call _Z8read_inti
movl %r12d, %edi
call _Z8read_inti
testl %ebp, %ebp
je .L9
movq %r13, %rbx
movl %ebp, %eax
imulq $3136, %rax, %rax
addq %rax, %r13
movq %rsp, %rbp
.L11:
movl $784, %ecx
movl $784, %edx
movq %rbp, %rsi
movl %r12d, %edi
call __read_chk@PLT
movl $0, %eax
.L10:
movzbl (%rax,%rbp), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC0(%rip), %xmm0
subsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $784, %rax
jne .L10
addq $3136, %rbx
cmpq %r13, %rbx
jne .L11
.L9:
movl %r12d, %edi
call close@PLT
movq 792(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $808, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3075:
.size _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj, .-_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.globl _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.type _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj, @function
_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj:
.LFB3076:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
movl %edx, %ebp
movq (%rdi), %rdi
movl $0, %esi
call __open_2@PLT
movl %eax, %ebx
movl %eax, %edi
call _Z8read_inti
movl %ebx, %edi
call _Z8read_inti
movl %ebp, %edx
movq $-1, %rcx
movq %r12, %rsi
movl %ebx, %edi
call __read_chk@PLT
movl %ebx, %edi
call close@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3076:
.size _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj, .-_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1080025088
.align 8
.LC1:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Tanner Hoelzel
*/
#include <cassert>
#include <unistd.h>
#include <fcntl.h>
#include <cstdio>
#include <string>
void
swap(int &i) {
// Some of the & are superfluous.
i =
(0xff&(i >> 24)) |
(0xff00&(i >> 8)) |
(0xff0000&(i << 8)) |
(0xff000000&(i << 24));
}
int
read_int(int fd) {
int rv;
int i;
rv = read(fd, &i, 4); assert(rv == 4);
swap(i);
return i;
}
void
read_mnist_images(const std::string &fn, float *images, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x803);
int n_images = read_int(fd);
assert(n_images == n);
int n_rows = read_int(fd);
assert(n_rows == 28);
int n_cols = read_int(fd);
assert(n_cols == 28);
for (int i = 0; i < n; i++) {
unsigned char tmp[28*28];
rv = read(fd, tmp, 28*28); assert(rv == 28*28);
for (int r = 0; r < 28*28; r++) {
// Make go from -1 to 1.
images[i*28*28+r] = float(tmp[r])/127.5 - 1;
}
}
rv = close(fd); assert(rv == 0);
}
void
read_mnist_labels(const std::string &fn, unsigned char *labels, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x801);
int n_labels = read_int(fd);
assert(n_labels == n);
rv = read(fd, labels, n); assert(rv == n);
rv = close(fd); assert(rv == 0);
} | /*
* Tanner Hoelzel
*/
#include <hip/hip_runtime.h>
#include <cassert>
#include <unistd.h>
#include <fcntl.h>
#include <cstdio>
#include <string>
void
swap(int &i) {
// Some of the & are superfluous.
i =
(0xff&(i >> 24)) |
(0xff00&(i >> 8)) |
(0xff0000&(i << 8)) |
(0xff000000&(i << 24));
}
int
read_int(int fd) {
int rv;
int i;
rv = read(fd, &i, 4); assert(rv == 4);
swap(i);
return i;
}
void
read_mnist_images(const std::string &fn, float *images, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x803);
int n_images = read_int(fd);
assert(n_images == n);
int n_rows = read_int(fd);
assert(n_rows == 28);
int n_cols = read_int(fd);
assert(n_cols == 28);
for (int i = 0; i < n; i++) {
unsigned char tmp[28*28];
rv = read(fd, tmp, 28*28); assert(rv == 28*28);
for (int r = 0; r < 28*28; r++) {
// Make go from -1 to 1.
images[i*28*28+r] = float(tmp[r])/127.5 - 1;
}
}
rv = close(fd); assert(rv == 0);
}
void
read_mnist_labels(const std::string &fn, unsigned char *labels, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x801);
int n_labels = read_int(fd);
assert(n_labels == n);
rv = read(fd, labels, n); assert(rv == n);
rv = close(fd); assert(rv == 0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Tanner Hoelzel
*/
#include <hip/hip_runtime.h>
#include <cassert>
#include <unistd.h>
#include <fcntl.h>
#include <cstdio>
#include <string>
void
swap(int &i) {
// Some of the & are superfluous.
i =
(0xff&(i >> 24)) |
(0xff00&(i >> 8)) |
(0xff0000&(i << 8)) |
(0xff000000&(i << 24));
}
int
read_int(int fd) {
int rv;
int i;
rv = read(fd, &i, 4); assert(rv == 4);
swap(i);
return i;
}
void
read_mnist_images(const std::string &fn, float *images, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x803);
int n_images = read_int(fd);
assert(n_images == n);
int n_rows = read_int(fd);
assert(n_rows == 28);
int n_cols = read_int(fd);
assert(n_cols == 28);
for (int i = 0; i < n; i++) {
unsigned char tmp[28*28];
rv = read(fd, tmp, 28*28); assert(rv == 28*28);
for (int r = 0; r < 28*28; r++) {
// Make go from -1 to 1.
images[i*28*28+r] = float(tmp[r])/127.5 - 1;
}
}
rv = close(fd); assert(rv == 0);
}
void
read_mnist_labels(const std::string &fn, unsigned char *labels, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x801);
int n_labels = read_int(fd);
assert(n_labels == n);
rv = read(fd, labels, n); assert(rv == n);
rv = close(fd); assert(rv == 0);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Tanner Hoelzel
*/
#include <hip/hip_runtime.h>
#include <cassert>
#include <unistd.h>
#include <fcntl.h>
#include <cstdio>
#include <string>
void
swap(int &i) {
// Some of the & are superfluous.
i =
(0xff&(i >> 24)) |
(0xff00&(i >> 8)) |
(0xff0000&(i << 8)) |
(0xff000000&(i << 24));
}
int
read_int(int fd) {
int rv;
int i;
rv = read(fd, &i, 4); assert(rv == 4);
swap(i);
return i;
}
void
read_mnist_images(const std::string &fn, float *images, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x803);
int n_images = read_int(fd);
assert(n_images == n);
int n_rows = read_int(fd);
assert(n_rows == 28);
int n_cols = read_int(fd);
assert(n_cols == 28);
for (int i = 0; i < n; i++) {
unsigned char tmp[28*28];
rv = read(fd, tmp, 28*28); assert(rv == 28*28);
for (int r = 0; r < 28*28; r++) {
// Make go from -1 to 1.
images[i*28*28+r] = float(tmp[r])/127.5 - 1;
}
}
rv = close(fd); assert(rv == 0);
}
void
read_mnist_labels(const std::string &fn, unsigned char *labels, unsigned int n) {
int rv;
int fd;
fd = open(fn.c_str(), O_RDONLY);
assert(fd >= 0);
int magic = read_int(fd);
assert(magic == 0x801);
int n_labels = read_int(fd);
assert(n_labels == n);
rv = read(fd, labels, n); assert(rv == n);
rv = close(fd); assert(rv == 0);
} | .text
.file "io.hip"
.globl _Z4swapRi # -- Begin function _Z4swapRi
.p2align 4, 0x90
.type _Z4swapRi,@function
_Z4swapRi: # @_Z4swapRi
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
bswapl %eax
movl %eax, (%rdi)
retq
.Lfunc_end0:
.size _Z4swapRi, .Lfunc_end0-_Z4swapRi
.cfi_endproc
# -- End function
.globl _Z8read_inti # -- Begin function _Z8read_inti
.p2align 4, 0x90
.type _Z8read_inti,@function
_Z8read_inti: # @_Z8read_inti
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rsi
movl $4, %edx
callq read
movl 4(%rsp), %eax
bswapl %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8read_inti, .Lfunc_end1-_Z8read_inti
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.LCPI2_0:
.quad 0x405fe00000000000 # double 127.5
.LCPI2_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.p2align 4, 0x90
.type _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj,@function
_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj: # @_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $792, %rsp # imm = 0x318
.cfi_def_cfa_offset 848
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movq %rsi, %rbx
movq (%rdi), %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
movl %eax, %ebp
movq %rsp, %rsi
movl $4, %edx
movl %eax, %edi
callq read
movq %rsp, %rsi
movl $4, %edx
movl %ebp, %edi
callq read
movq %rsp, %rsi
movl $4, %edx
movl %ebp, %edi
callq read
movq %rsp, %rsi
movl $4, %edx
movl %ebp, %edi
callq read
testl %r14d, %r14d
je .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl %r14d, %r15d
xorl %r12d, %r12d
movq %rsp, %r14
movabsq $3367254360064, %r13 # imm = 0x31000000000
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl $784, %edx # imm = 0x310
movl %ebp, %edi
movq %r14, %rsi
callq read
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %r12, %rax
imulq %r13, %rax
sarq $30, %rax
addq %rbx, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%rsp,%rcx), %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
divsd %xmm1, %xmm0
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $784, %rcx # imm = 0x310
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=1
incq %r12
cmpq %r15, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge
movl %ebp, %edi
addq $792, %rsp # imm = 0x318
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp close # TAILCALL
.Lfunc_end2:
.size _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj, .Lfunc_end2-_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.cfi_endproc
# -- End function
.globl _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj # -- Begin function _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.p2align 4, 0x90
.type _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj,@function
_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj: # @_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq (%rdi), %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
movl %eax, %r14d
leaq 8(%rsp), %rsi
movl $4, %edx
movl %eax, %edi
callq read
leaq 12(%rsp), %rsi
movl $4, %edx
movl %r14d, %edi
callq read
movl %ebp, %edx
movl %r14d, %edi
movq %rbx, %rsi
callq read
movl %r14d, %edi
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp close # TAILCALL
.Lfunc_end3:
.size _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj, .Lfunc_end3-_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016af2c_00000000-6_io.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3079:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapRi
.type _Z4swapRi, @function
_Z4swapRi:
.LFB3073:
.cfi_startproc
endbr64
movl (%rdi), %edx
movl %edx, %eax
sarl $8, %eax
andl $65280, %eax
movl %edx, %ecx
sall $8, %ecx
andl $16711680, %ecx
orl %ecx, %eax
movl %edx, %ecx
sall $24, %ecx
orl %ecx, %eax
shrl $24, %edx
orl %edx, %eax
movl %eax, (%rdi)
ret
.cfi_endproc
.LFE3073:
.size _Z4swapRi, .-_Z4swapRi
.globl _Z8read_inti
.type _Z8read_inti, @function
_Z8read_inti:
.LFB3074:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rbx
movl $4, %ecx
movl $4, %edx
movq %rbx, %rsi
call __read_chk@PLT
movq %rbx, %rdi
call _Z4swapRi
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L7
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3074:
.size _Z8read_inti, .-_Z8read_inti
.globl _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.type _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj, @function
_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj:
.LFB3075:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $808, %rsp
.cfi_def_cfa_offset 848
movq %rsi, %r13
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 792(%rsp)
xorl %eax, %eax
movq (%rdi), %rdi
movl $0, %esi
call __open_2@PLT
movl %eax, %r12d
movl %eax, %edi
call _Z8read_inti
movl %r12d, %edi
call _Z8read_inti
movl %r12d, %edi
call _Z8read_inti
movl %r12d, %edi
call _Z8read_inti
testl %ebp, %ebp
je .L9
movq %r13, %rbx
movl %ebp, %eax
imulq $3136, %rax, %rax
addq %rax, %r13
movq %rsp, %rbp
.L11:
movl $784, %ecx
movl $784, %edx
movq %rbp, %rsi
movl %r12d, %edi
call __read_chk@PLT
movl $0, %eax
.L10:
movzbl (%rax,%rbp), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC0(%rip), %xmm0
subsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $784, %rax
jne .L10
addq $3136, %rbx
cmpq %r13, %rbx
jne .L11
.L9:
movl %r12d, %edi
call close@PLT
movq 792(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $808, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3075:
.size _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj, .-_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.globl _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.type _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj, @function
_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj:
.LFB3076:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
movl %edx, %ebp
movq (%rdi), %rdi
movl $0, %esi
call __open_2@PLT
movl %eax, %ebx
movl %eax, %edi
call _Z8read_inti
movl %ebx, %edi
call _Z8read_inti
movl %ebp, %edx
movq $-1, %rcx
movq %r12, %rsi
movl %ebx, %edi
call __read_chk@PLT
movl %ebx, %edi
call close@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3076:
.size _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj, .-_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1080025088
.align 8
.LC1:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "io.hip"
.globl _Z4swapRi # -- Begin function _Z4swapRi
.p2align 4, 0x90
.type _Z4swapRi,@function
_Z4swapRi: # @_Z4swapRi
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
bswapl %eax
movl %eax, (%rdi)
retq
.Lfunc_end0:
.size _Z4swapRi, .Lfunc_end0-_Z4swapRi
.cfi_endproc
# -- End function
.globl _Z8read_inti # -- Begin function _Z8read_inti
.p2align 4, 0x90
.type _Z8read_inti,@function
_Z8read_inti: # @_Z8read_inti
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rsi
movl $4, %edx
callq read
movl 4(%rsp), %eax
bswapl %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8read_inti, .Lfunc_end1-_Z8read_inti
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.LCPI2_0:
.quad 0x405fe00000000000 # double 127.5
.LCPI2_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.p2align 4, 0x90
.type _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj,@function
_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj: # @_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $792, %rsp # imm = 0x318
.cfi_def_cfa_offset 848
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movq %rsi, %rbx
movq (%rdi), %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
movl %eax, %ebp
movq %rsp, %rsi
movl $4, %edx
movl %eax, %edi
callq read
movq %rsp, %rsi
movl $4, %edx
movl %ebp, %edi
callq read
movq %rsp, %rsi
movl $4, %edx
movl %ebp, %edi
callq read
movq %rsp, %rsi
movl $4, %edx
movl %ebp, %edi
callq read
testl %r14d, %r14d
je .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl %r14d, %r15d
xorl %r12d, %r12d
movq %rsp, %r14
movabsq $3367254360064, %r13 # imm = 0x31000000000
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl $784, %edx # imm = 0x310
movl %ebp, %edi
movq %r14, %rsi
callq read
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %r12, %rax
imulq %r13, %rax
sarq $30, %rax
addq %rbx, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%rsp,%rcx), %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
divsd %xmm1, %xmm0
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $784, %rcx # imm = 0x310
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=1
incq %r12
cmpq %r15, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge
movl %ebp, %edi
addq $792, %rsp # imm = 0x318
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp close # TAILCALL
.Lfunc_end2:
.size _Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj, .Lfunc_end2-_Z17read_mnist_imagesRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPfj
.cfi_endproc
# -- End function
.globl _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj # -- Begin function _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.p2align 4, 0x90
.type _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj,@function
_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj: # @_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq (%rdi), %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
movl %eax, %r14d
leaq 8(%rsp), %rsi
movl $4, %edx
movl %eax, %edi
callq read
leaq 12(%rsp), %rsi
movl $4, %edx
movl %r14d, %edi
callq read
movl %ebp, %edx
movl %r14d, %edi
movq %rbx, %rsi
callq read
movl %r14d, %edi
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp close # TAILCALL
.Lfunc_end3:
.size _Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj, .Lfunc_end3-_Z17read_mnist_labelsRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPhj
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00061515_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiiiPPdS_S_S_S_S_iiiiiii
.type _Z60__device_stub__Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiiiPPdS_S_S_S_S_iiiiiii, @function
_Z60__device_stub__Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiiiPPdS_S_S_S_S_iiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiiiPPdS_S_S_S_S_iiiiiii, .-_Z60__device_stub__Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiiiPPdS_S_S_S_S_iiiiiii
.globl _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.type _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii, @function
_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z60__device_stub__Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiiiPPdS_S_S_S_S_iiiiiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii, .-_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.globl _Z45__device_stub__Z10initializePdS_S_S_S_iiiiiiiPdS_S_S_S_iiiiiii
.type _Z45__device_stub__Z10initializePdS_S_S_S_iiiiiiiPdS_S_S_S_iiiiiii, @function
_Z45__device_stub__Z10initializePdS_S_S_S_iiiiiiiPdS_S_S_S_iiiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10initializePdS_S_S_S_iiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z10initializePdS_S_S_S_iiiiiiiPdS_S_S_S_iiiiiii, .-_Z45__device_stub__Z10initializePdS_S_S_S_iiiiiiiPdS_S_S_S_iiiiiii
.globl _Z10initializePdS_S_S_S_iiiiiii
.type _Z10initializePdS_S_S_S_iiiiiii, @function
_Z10initializePdS_S_S_S_iiiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z10initializePdS_S_S_S_iiiiiiiPdS_S_S_S_iiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10initializePdS_S_S_S_iiiiiii, .-_Z10initializePdS_S_S_S_iiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10initializePdS_S_S_S_iiiiiii"
.align 8
.LC1:
.string "_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePdS_S_S_S_iiiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii # -- Begin function _Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.p2align 4, 0x90
.type _Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii,@function
_Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii: # @_Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii, .Lfunc_end0-_Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePdS_S_S_S_iiiiiii # -- Begin function _Z25__device_stub__initializePdS_S_S_S_iiiiiii
.p2align 4, 0x90
.type _Z25__device_stub__initializePdS_S_S_S_iiiiiii,@function
_Z25__device_stub__initializePdS_S_S_S_iiiiiii: # @_Z25__device_stub__initializePdS_S_S_S_iiiiiii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10initializePdS_S_S_S_iiiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePdS_S_S_S_iiiiiii, .Lfunc_end1-_Z25__device_stub__initializePdS_S_S_S_iiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePdS_S_S_S_iiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii,@object # @_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.section .rodata,"a",@progbits
.globl _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.p2align 3, 0x0
_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii:
.quad _Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.size _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii, 8
.type _Z10initializePdS_S_S_S_iiiiiii,@object # @_Z10initializePdS_S_S_S_iiiiiii
.globl _Z10initializePdS_S_S_S_iiiiiii
.p2align 3, 0x0
_Z10initializePdS_S_S_S_iiiiiii:
.quad _Z25__device_stub__initializePdS_S_S_S_iiiiiii
.size _Z10initializePdS_S_S_S_iiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii"
.size .L__unnamed_1, 47
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initializePdS_S_S_S_iiiiiii"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.addrsig_sym _Z25__device_stub__initializePdS_S_S_S_iiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22tricubic_interpolationPPdS_S_S_S_S_iiiiiii
.addrsig_sym _Z10initializePdS_S_S_S_iiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void square(float * d_out, float * d_in) {
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void square(float * d_out, float * d_in) {
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
} | .file "tmpxft_000a2431_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void square(float * d_out, float * d_in) {
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square(float * d_out, float * d_in) {
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square(float * d_out, float * d_in) {
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square(float * d_out, float * d_in) {
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f;
} | .text
.file "square.hip"
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a2431_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void returnStatistic ( const int dim, const int nwl, const float *xx, float *s ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
s[t] = powf ( xx[t], 2. );
}
} | code for sm_80
Function : _Z15returnStatisticiiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ HFMA2.MMA R12, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff0c7435 */
/* 0x000fe200000001ff */
/*0100*/ BSSY B0, 0x5a0 ; /* 0x0000049000007945 */
/* 0x000fe20003800000 */
/*0110*/ FMUL R5, |R2|.reuse, 16777216 ; /* 0x4b80000002057820 */
/* 0x044fe20000400200 */
/*0120*/ FSETP.GEU.AND P0, PT, |R2|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000200780b */
/* 0x040fe40003f0e200 */
/*0130*/ FSETP.NEU.AND P2, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fe40003f4d000 */
/*0140*/ FSEL R5, R5, |R2|, !P0 ; /* 0x4000000205057208 */
/* 0x000fe40004000000 */
/*0150*/ FSEL R3, RZ, -24, P0 ; /* 0xc1c00000ff037808 */
/* 0x000fc40000000000 */
/*0160*/ IADD3 R4, R5, -0x3f3504f3, RZ ; /* 0xc0cafb0d05047810 */
/* 0x000fc80007ffe0ff */
/*0170*/ LOP3.LUT R4, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004047812 */
/* 0x000fc800078ec0ff */
/*0180*/ IADD3 R5, R5, -R4, RZ ; /* 0x8000000405057210 */
/* 0x000fe40007ffe0ff */
/*0190*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e260000201400 */
/*01a0*/ FADD R6, R5.reuse, 1 ; /* 0x3f80000005067421 */
/* 0x040fe40000000000 */
/*01b0*/ FADD R5, R5, -1 ; /* 0xbf80000005057421 */
/* 0x000fc80000000000 */
/*01c0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x000e620000001000 */
/*01d0*/ FADD R7, R5, R5 ; /* 0x0000000505077221 */
/* 0x000fe40000000000 */
/*01e0*/ FFMA R3, R4, 1.1920928955078125e-07, R3 ; /* 0x3400000004037823 */
/* 0x001fe40000000003 */
/*01f0*/ FMUL R8, R6, R7 ; /* 0x0000000706087220 */
/* 0x002fc80000400000 */
/*0200*/ FADD R9, R5, -R8 ; /* 0x8000000805097221 */
/* 0x000fe40000000000 */
/*0210*/ FMUL R7, R8.reuse, R8 ; /* 0x0000000808077220 */
/* 0x040fe40000400000 */
/*0220*/ FFMA R10, R8, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b080a7823 */
/* 0x000fe40000000003 */
/*0230*/ FADD R9, R9, R9 ; /* 0x0000000909097221 */
/* 0x000fe40000000000 */
/*0240*/ FFMA R4, R7, R12, 0.0032181653659790754318 ; /* 0x3b52e7db07047423 */
/* 0x000fe4000000000c */
/*0250*/ FADD R3, R3, -R10 ; /* 0x8000000a03037221 */
/* 0x000fc40000000000 */
/*0260*/ FFMA R9, R5, -R8, R9 ; /* 0x8000000805097223 */
/* 0x000fe40000000009 */
/*0270*/ FFMA R4, R7.reuse, R4, 0.018033718690276145935 ; /* 0x3c93bb7307047423 */
/* 0x040fe40000000004 */
/*0280*/ FFMA R12, R8, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b080c7823 */
/* 0x000fe40000000003 */
/*0290*/ FMUL R9, R6, R9 ; /* 0x0000000906097220 */
/* 0x000fe40000400000 */
/*02a0*/ FFMA R4, R7, R4, 0.12022458761930465698 ; /* 0x3df6384f07047423 */
/* 0x000fe40000000004 */
/*02b0*/ FFMA R3, R9, 1.4426950216293334961, R12 ; /* 0x3fb8aa3b09037823 */
/* 0x000fc4000000000c */
/*02c0*/ FMUL R7, R7, R4 ; /* 0x0000000407077220 */
/* 0x000fe40000400000 */
/*02d0*/ FFMA R4, R8, 1.9251366722983220825e-08, R3 ; /* 0x32a55e3408047823 */
/* 0x000fe40000000003 */
/*02e0*/ FMUL R3, R7, 3 ; /* 0x4040000007037820 */
/* 0x000fc80000400000 */
/*02f0*/ FFMA R3, R9, R3, R4 ; /* 0x0000000309037223 */
/* 0x000fc80000000004 */
/*0300*/ FFMA R3, R8, R7, R3 ; /* 0x0000000708037223 */
/* 0x000fe20000000003 */
/*0310*/ MOV R8, 0x391fcb8e ; /* 0x391fcb8e00087802 */
/* 0x000fc60000000f00 */
/*0320*/ FADD R5, R10, R3 ; /* 0x000000030a057221 */
/* 0x000fc80000000000 */
/*0330*/ FMUL R4, R5.reuse, 2 ; /* 0x4000000005047820 */
/* 0x040fe40000400000 */
/*0340*/ FADD R10, -R10, R5 ; /* 0x000000050a0a7221 */
/* 0x000fe40000000100 */
/*0350*/ FRND R7, R4 ; /* 0x0000000400077307 */
/* 0x000e220000201000 */
/*0360*/ FFMA R5, R5, 2, -R4 ; /* 0x4000000005057823 */
/* 0x000fe20000000804 */
/*0370*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*0380*/ FADD R10, R3, -R10 ; /* 0x8000000a030a7221 */
/* 0x000fc80000000000 */
/*0390*/ FFMA R5, R10, 2, R5 ; /* 0x400000000a057823 */
/* 0x000fe20000000005 */
/*03a0*/ F2I.NTZ R3, R4 ; /* 0x0000000400037305 */
/* 0x000e620000203100 */
/*03b0*/ FADD R6, R4, -R7 ; /* 0x8000000704067221 */
/* 0x001fe20000000000 */
/*03c0*/ FSETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc60003f04000 */
/*03d0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x000fc80000000000 */
/*03e0*/ FFMA R6, R5.reuse, R8, 0.0013391353422775864601 ; /* 0x3aaf85ed05067423 */
/* 0x040fe20000000008 */
/*03f0*/ SEL R8, RZ, 0x83000000, P0 ; /* 0x83000000ff087807 */
/* 0x000fe40000000000 */
/*0400*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0410*/ FFMA R6, R5, R6, 0.0096188392490148544312 ; /* 0x3c1d985605067423 */
/* 0x000fe20000000006 */
/*0420*/ IADD3 R7, R8, 0x7f000000, RZ ; /* 0x7f00000008077810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LEA R3, R3, -R8, 0x17 ; /* 0x8000000803037211 */
/* 0x002fe200078eb8ff */
/*0440*/ FFMA R6, R5, R6, 0.055503588169813156128 ; /* 0x3d6357bb05067423 */
/* 0x000fc80000000006 */
/*0450*/ FFMA R6, R5, R6, 0.24022644758224487305 ; /* 0x3e75fdec05067423 */
/* 0x000fc80000000006 */
/*0460*/ FFMA R6, R5, R6, 0.69314718246459960938 ; /* 0x3f31721805067423 */
/* 0x000fc80000000006 */
/*0470*/ FFMA R6, R5, R6, 1 ; /* 0x3f80000005067423 */
/* 0x000fe20000000006 */
/*0480*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fc600000001ff */
/*0490*/ FMUL R6, R6, R7 ; /* 0x0000000706067220 */
/* 0x000fe20000400000 */
/*04a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fc60000011400 */
/*04b0*/ FMUL R3, R6, R3 ; /* 0x0000000306037220 */
/* 0x000fe20000400000 */
/*04c0*/ @P0 FSEL R3, RZ, +INF , !P1 ; /* 0x7f800000ff030808 */
/* 0x000fe20004800000 */
/*04d0*/ @!P2 BRA 0x590 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*04e0*/ FSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f0c200 */
/*04f0*/ @P0 BRA 0x580 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f0d200 */
/*0510*/ FSETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720b */
/* 0x000fda0004702400 */
/*0520*/ @P0 BRA 0x550 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0530*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe20000000f00 */
/*0540*/ BRA 0x590 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0550*/ FADD R2, R2, R2 ; /* 0x0000000202027221 */
/* 0x000fca0000000000 */
/*0560*/ LOP3.LUT R5, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02057812 */
/* 0x000fe200078ec0ff */
/*0570*/ BRA 0x590 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0580*/ FADD R5, R2, 2 ; /* 0x4000000002057421 */
/* 0x000fe40000000000 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*05b0*/ LEA.HI.X R3, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1407 */
/*05c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void returnStatistic ( const int dim, const int nwl, const float *xx, float *s ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
s[t] = powf ( xx[t], 2. );
}
} | .file "tmpxft_0014b55c_00000000-6_returnStatistic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf
.type _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf, @function
_Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15returnStatisticiiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf, .-_Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf
.globl _Z15returnStatisticiiPKfPf
.type _Z15returnStatisticiiPKfPf, @function
_Z15returnStatisticiiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15returnStatisticiiPKfPf, .-_Z15returnStatisticiiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15returnStatisticiiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15returnStatisticiiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void returnStatistic ( const int dim, const int nwl, const float *xx, float *s ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
s[t] = powf ( xx[t], 2. );
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void returnStatistic ( const int dim, const int nwl, const float *xx, float *s ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
s[t] = powf ( xx[t], 2. );
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void returnStatistic ( const int dim, const int nwl, const float *xx, float *s ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
s[t] = powf ( xx[t], 2. );
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15returnStatisticiiPKfPf
.globl _Z15returnStatisticiiPKfPf
.p2align 8
.type _Z15returnStatisticiiPKfPf,@function
_Z15returnStatisticiiPKfPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0x3e76c4e1
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_frexp_mant_f32_e64 v3, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, -1.0, v3
v_add_f32_e32 v4, 1.0, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, v6, v5 :: v_dual_add_f32 v8, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v4, v7
v_sub_f32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v7, v4, -v9
v_fmac_f32_e32 v4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v4
v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v9, v4
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v6, v3
v_add_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v3
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v3
v_mul_f32_e32 v6, v4, v4
v_sub_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v5, v4, v4, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v3, v3
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v5
v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
v_mul_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v8, -v9
v_dual_fmac_f32 v6, v5, v8 :: v_dual_mul_f32 v11, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v9, v6
v_fma_f32 v12, v7, v4, -v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v9, v8, v9 :: v_dual_fmac_f32 v12, v7, v3
v_add_f32_e32 v10, 0x3f2aaaaa, v8
v_ldexp_f32 v3, v3, 1
v_sub_f32_e32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
v_add_f32_e32 v6, 0x31739010, v6
v_add_f32_e32 v9, 0xbf2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v9
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v10, v6
v_dual_add_f32 v7, v11, v12 :: v_dual_sub_f32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v10, v7, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v7, v5, -v9
v_sub_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v7, v6
v_frexp_exp_i32_f32_e32 v6, v2
v_fmac_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
v_add_f32_e32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v5, v5
v_sub_f32_e32 v9, v6, v9
v_add_f32_e32 v7, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v9
v_dual_mul_f32 v10, 0x3f317218, v5 :: v_dual_add_f32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, v5, 0x3f317218, -v10
v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_sub_f32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v6, v4
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v3
v_sub_f32_e32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v5, v10
v_add_f32_e32 v8, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v8, v4
v_sub_f32_e32 v7, v6, v7
v_sub_f32_e32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v6, v6, v9
v_sub_f32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v5, v3 :: v_dual_add_f32 v4, v6, v4
v_sub_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v7, v4
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v5, v7
v_add_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v4, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v4, v9 :: v_dual_mul_f32 v7, v5, v4
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v4, v5, v4, -v7
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_fmac_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v4
v_cndmask_b32_e32 v6, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
v_sub_f32_e32 v9, v6, v8
v_trunc_f32_e32 v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, 0x3fb8aa3b, v9 :: v_dual_sub_f32 v3, v3, v7
v_fma_f32 v11, v9, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v4, v3
v_dual_fmamk_f32 v11, v9, 0x32a5705f, v11 :: v_dual_sub_f32 v10, v10, v12
v_cvt_i32_f32_e32 v7, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v10, v11
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v10, v7
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
v_trunc_f32_e32 v10, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v3, v8, v3 :: v_dual_cndmask_b32 v4, 0x7f800000, v4
v_cmp_eq_f32_e32 vcc_lo, v6, v5
v_cmp_neq_f32_e64 s0, v10, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v3, v4, v3, v4
v_cmp_eq_f32_e64 s1, 0x7f800000, v4
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, 1.0, v2, s0
v_cndmask_b32_e64 v3, v3, v4, s1
v_cmp_eq_f32_e64 s1, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfi_b32 v3, 0x7fffffff, v3, v5
v_cndmask_b32_e64 v4, 0x7f800000, 0, s1
v_cndmask_b32_e64 v5, 0, v2, s0
v_cmp_class_f32_e64 s0, v2, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v6, 0x7fc00000, v3, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v2
v_bfi_b32 v4, 0x7fffffff, v4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_or_b32 vcc_lo, s1, s0
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v2, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15returnStatisticiiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15returnStatisticiiPKfPf, .Lfunc_end0-_Z15returnStatisticiiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15returnStatisticiiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15returnStatisticiiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void returnStatistic ( const int dim, const int nwl, const float *xx, float *s ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
s[t] = powf ( xx[t], 2. );
}
} | .text
.file "returnStatistic.hip"
.globl _Z30__device_stub__returnStatisticiiPKfPf # -- Begin function _Z30__device_stub__returnStatisticiiPKfPf
.p2align 4, 0x90
.type _Z30__device_stub__returnStatisticiiPKfPf,@function
_Z30__device_stub__returnStatisticiiPKfPf: # @_Z30__device_stub__returnStatisticiiPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15returnStatisticiiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__returnStatisticiiPKfPf, .Lfunc_end0-_Z30__device_stub__returnStatisticiiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15returnStatisticiiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15returnStatisticiiPKfPf,@object # @_Z15returnStatisticiiPKfPf
.section .rodata,"a",@progbits
.globl _Z15returnStatisticiiPKfPf
.p2align 3, 0x0
_Z15returnStatisticiiPKfPf:
.quad _Z30__device_stub__returnStatisticiiPKfPf
.size _Z15returnStatisticiiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15returnStatisticiiPKfPf"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__returnStatisticiiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15returnStatisticiiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15returnStatisticiiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ HFMA2.MMA R12, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff0c7435 */
/* 0x000fe200000001ff */
/*0100*/ BSSY B0, 0x5a0 ; /* 0x0000049000007945 */
/* 0x000fe20003800000 */
/*0110*/ FMUL R5, |R2|.reuse, 16777216 ; /* 0x4b80000002057820 */
/* 0x044fe20000400200 */
/*0120*/ FSETP.GEU.AND P0, PT, |R2|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000200780b */
/* 0x040fe40003f0e200 */
/*0130*/ FSETP.NEU.AND P2, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fe40003f4d000 */
/*0140*/ FSEL R5, R5, |R2|, !P0 ; /* 0x4000000205057208 */
/* 0x000fe40004000000 */
/*0150*/ FSEL R3, RZ, -24, P0 ; /* 0xc1c00000ff037808 */
/* 0x000fc40000000000 */
/*0160*/ IADD3 R4, R5, -0x3f3504f3, RZ ; /* 0xc0cafb0d05047810 */
/* 0x000fc80007ffe0ff */
/*0170*/ LOP3.LUT R4, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004047812 */
/* 0x000fc800078ec0ff */
/*0180*/ IADD3 R5, R5, -R4, RZ ; /* 0x8000000405057210 */
/* 0x000fe40007ffe0ff */
/*0190*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e260000201400 */
/*01a0*/ FADD R6, R5.reuse, 1 ; /* 0x3f80000005067421 */
/* 0x040fe40000000000 */
/*01b0*/ FADD R5, R5, -1 ; /* 0xbf80000005057421 */
/* 0x000fc80000000000 */
/*01c0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x000e620000001000 */
/*01d0*/ FADD R7, R5, R5 ; /* 0x0000000505077221 */
/* 0x000fe40000000000 */
/*01e0*/ FFMA R3, R4, 1.1920928955078125e-07, R3 ; /* 0x3400000004037823 */
/* 0x001fe40000000003 */
/*01f0*/ FMUL R8, R6, R7 ; /* 0x0000000706087220 */
/* 0x002fc80000400000 */
/*0200*/ FADD R9, R5, -R8 ; /* 0x8000000805097221 */
/* 0x000fe40000000000 */
/*0210*/ FMUL R7, R8.reuse, R8 ; /* 0x0000000808077220 */
/* 0x040fe40000400000 */
/*0220*/ FFMA R10, R8, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b080a7823 */
/* 0x000fe40000000003 */
/*0230*/ FADD R9, R9, R9 ; /* 0x0000000909097221 */
/* 0x000fe40000000000 */
/*0240*/ FFMA R4, R7, R12, 0.0032181653659790754318 ; /* 0x3b52e7db07047423 */
/* 0x000fe4000000000c */
/*0250*/ FADD R3, R3, -R10 ; /* 0x8000000a03037221 */
/* 0x000fc40000000000 */
/*0260*/ FFMA R9, R5, -R8, R9 ; /* 0x8000000805097223 */
/* 0x000fe40000000009 */
/*0270*/ FFMA R4, R7.reuse, R4, 0.018033718690276145935 ; /* 0x3c93bb7307047423 */
/* 0x040fe40000000004 */
/*0280*/ FFMA R12, R8, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b080c7823 */
/* 0x000fe40000000003 */
/*0290*/ FMUL R9, R6, R9 ; /* 0x0000000906097220 */
/* 0x000fe40000400000 */
/*02a0*/ FFMA R4, R7, R4, 0.12022458761930465698 ; /* 0x3df6384f07047423 */
/* 0x000fe40000000004 */
/*02b0*/ FFMA R3, R9, 1.4426950216293334961, R12 ; /* 0x3fb8aa3b09037823 */
/* 0x000fc4000000000c */
/*02c0*/ FMUL R7, R7, R4 ; /* 0x0000000407077220 */
/* 0x000fe40000400000 */
/*02d0*/ FFMA R4, R8, 1.9251366722983220825e-08, R3 ; /* 0x32a55e3408047823 */
/* 0x000fe40000000003 */
/*02e0*/ FMUL R3, R7, 3 ; /* 0x4040000007037820 */
/* 0x000fc80000400000 */
/*02f0*/ FFMA R3, R9, R3, R4 ; /* 0x0000000309037223 */
/* 0x000fc80000000004 */
/*0300*/ FFMA R3, R8, R7, R3 ; /* 0x0000000708037223 */
/* 0x000fe20000000003 */
/*0310*/ MOV R8, 0x391fcb8e ; /* 0x391fcb8e00087802 */
/* 0x000fc60000000f00 */
/*0320*/ FADD R5, R10, R3 ; /* 0x000000030a057221 */
/* 0x000fc80000000000 */
/*0330*/ FMUL R4, R5.reuse, 2 ; /* 0x4000000005047820 */
/* 0x040fe40000400000 */
/*0340*/ FADD R10, -R10, R5 ; /* 0x000000050a0a7221 */
/* 0x000fe40000000100 */
/*0350*/ FRND R7, R4 ; /* 0x0000000400077307 */
/* 0x000e220000201000 */
/*0360*/ FFMA R5, R5, 2, -R4 ; /* 0x4000000005057823 */
/* 0x000fe20000000804 */
/*0370*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*0380*/ FADD R10, R3, -R10 ; /* 0x8000000a030a7221 */
/* 0x000fc80000000000 */
/*0390*/ FFMA R5, R10, 2, R5 ; /* 0x400000000a057823 */
/* 0x000fe20000000005 */
/*03a0*/ F2I.NTZ R3, R4 ; /* 0x0000000400037305 */
/* 0x000e620000203100 */
/*03b0*/ FADD R6, R4, -R7 ; /* 0x8000000704067221 */
/* 0x001fe20000000000 */
/*03c0*/ FSETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc60003f04000 */
/*03d0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x000fc80000000000 */
/*03e0*/ FFMA R6, R5.reuse, R8, 0.0013391353422775864601 ; /* 0x3aaf85ed05067423 */
/* 0x040fe20000000008 */
/*03f0*/ SEL R8, RZ, 0x83000000, P0 ; /* 0x83000000ff087807 */
/* 0x000fe40000000000 */
/*0400*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0410*/ FFMA R6, R5, R6, 0.0096188392490148544312 ; /* 0x3c1d985605067423 */
/* 0x000fe20000000006 */
/*0420*/ IADD3 R7, R8, 0x7f000000, RZ ; /* 0x7f00000008077810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LEA R3, R3, -R8, 0x17 ; /* 0x8000000803037211 */
/* 0x002fe200078eb8ff */
/*0440*/ FFMA R6, R5, R6, 0.055503588169813156128 ; /* 0x3d6357bb05067423 */
/* 0x000fc80000000006 */
/*0450*/ FFMA R6, R5, R6, 0.24022644758224487305 ; /* 0x3e75fdec05067423 */
/* 0x000fc80000000006 */
/*0460*/ FFMA R6, R5, R6, 0.69314718246459960938 ; /* 0x3f31721805067423 */
/* 0x000fc80000000006 */
/*0470*/ FFMA R6, R5, R6, 1 ; /* 0x3f80000005067423 */
/* 0x000fe20000000006 */
/*0480*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fc600000001ff */
/*0490*/ FMUL R6, R6, R7 ; /* 0x0000000706067220 */
/* 0x000fe20000400000 */
/*04a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fc60000011400 */
/*04b0*/ FMUL R3, R6, R3 ; /* 0x0000000306037220 */
/* 0x000fe20000400000 */
/*04c0*/ @P0 FSEL R3, RZ, +INF , !P1 ; /* 0x7f800000ff030808 */
/* 0x000fe20004800000 */
/*04d0*/ @!P2 BRA 0x590 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*04e0*/ FSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f0c200 */
/*04f0*/ @P0 BRA 0x580 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f0d200 */
/*0510*/ FSETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720b */
/* 0x000fda0004702400 */
/*0520*/ @P0 BRA 0x550 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0530*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe20000000f00 */
/*0540*/ BRA 0x590 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0550*/ FADD R2, R2, R2 ; /* 0x0000000202027221 */
/* 0x000fca0000000000 */
/*0560*/ LOP3.LUT R5, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02057812 */
/* 0x000fe200078ec0ff */
/*0570*/ BRA 0x590 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0580*/ FADD R5, R2, 2 ; /* 0x4000000002057421 */
/* 0x000fe40000000000 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*05b0*/ LEA.HI.X R3, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1407 */
/*05c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15returnStatisticiiPKfPf
.globl _Z15returnStatisticiiPKfPf
.p2align 8
.type _Z15returnStatisticiiPKfPf,@function
_Z15returnStatisticiiPKfPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0x3e76c4e1
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_frexp_mant_f32_e64 v3, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, -1.0, v3
v_add_f32_e32 v4, 1.0, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, v6, v5 :: v_dual_add_f32 v8, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v4, v7
v_sub_f32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v7, v4, -v9
v_fmac_f32_e32 v4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v4
v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v9, v4
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v6, v3
v_add_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v3
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v3
v_mul_f32_e32 v6, v4, v4
v_sub_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v5, v4, v4, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v3, v3
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v5
v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
v_mul_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v8, -v9
v_dual_fmac_f32 v6, v5, v8 :: v_dual_mul_f32 v11, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v9, v6
v_fma_f32 v12, v7, v4, -v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v9, v8, v9 :: v_dual_fmac_f32 v12, v7, v3
v_add_f32_e32 v10, 0x3f2aaaaa, v8
v_ldexp_f32 v3, v3, 1
v_sub_f32_e32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
v_add_f32_e32 v6, 0x31739010, v6
v_add_f32_e32 v9, 0xbf2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v9
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v10, v6
v_dual_add_f32 v7, v11, v12 :: v_dual_sub_f32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v10, v7, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v7, v5, -v9
v_sub_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v7, v6
v_frexp_exp_i32_f32_e32 v6, v2
v_fmac_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
v_add_f32_e32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v5, v5
v_sub_f32_e32 v9, v6, v9
v_add_f32_e32 v7, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v9
v_dual_mul_f32 v10, 0x3f317218, v5 :: v_dual_add_f32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, v5, 0x3f317218, -v10
v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_sub_f32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v6, v4
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v3
v_sub_f32_e32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v5, v10
v_add_f32_e32 v8, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v8, v4
v_sub_f32_e32 v7, v6, v7
v_sub_f32_e32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v6, v6, v9
v_sub_f32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v5, v3 :: v_dual_add_f32 v4, v6, v4
v_sub_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v7, v4
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v5, v7
v_add_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v4, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v4, v9 :: v_dual_mul_f32 v7, v5, v4
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v4, v5, v4, -v7
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_fmac_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v4
v_cndmask_b32_e32 v6, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
v_sub_f32_e32 v9, v6, v8
v_trunc_f32_e32 v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, 0x3fb8aa3b, v9 :: v_dual_sub_f32 v3, v3, v7
v_fma_f32 v11, v9, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v4, v3
v_dual_fmamk_f32 v11, v9, 0x32a5705f, v11 :: v_dual_sub_f32 v10, v10, v12
v_cvt_i32_f32_e32 v7, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v10, v11
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v10, v7
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
v_trunc_f32_e32 v10, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v3, v8, v3 :: v_dual_cndmask_b32 v4, 0x7f800000, v4
v_cmp_eq_f32_e32 vcc_lo, v6, v5
v_cmp_neq_f32_e64 s0, v10, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v3, v4, v3, v4
v_cmp_eq_f32_e64 s1, 0x7f800000, v4
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, 1.0, v2, s0
v_cndmask_b32_e64 v3, v3, v4, s1
v_cmp_eq_f32_e64 s1, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfi_b32 v3, 0x7fffffff, v3, v5
v_cndmask_b32_e64 v4, 0x7f800000, 0, s1
v_cndmask_b32_e64 v5, 0, v2, s0
v_cmp_class_f32_e64 s0, v2, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v6, 0x7fc00000, v3, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v2
v_bfi_b32 v4, 0x7fffffff, v4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_or_b32 vcc_lo, s1, s0
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v2, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15returnStatisticiiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15returnStatisticiiPKfPf, .Lfunc_end0-_Z15returnStatisticiiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15returnStatisticiiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15returnStatisticiiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b55c_00000000-6_returnStatistic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf
.type _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf, @function
_Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15returnStatisticiiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf, .-_Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf
.globl _Z15returnStatisticiiPKfPf
.type _Z15returnStatisticiiPKfPf, @function
_Z15returnStatisticiiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15returnStatisticiiPKfPfiiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15returnStatisticiiPKfPf, .-_Z15returnStatisticiiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15returnStatisticiiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15returnStatisticiiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "returnStatistic.hip"
.globl _Z30__device_stub__returnStatisticiiPKfPf # -- Begin function _Z30__device_stub__returnStatisticiiPKfPf
.p2align 4, 0x90
.type _Z30__device_stub__returnStatisticiiPKfPf,@function
_Z30__device_stub__returnStatisticiiPKfPf: # @_Z30__device_stub__returnStatisticiiPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15returnStatisticiiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__returnStatisticiiPKfPf, .Lfunc_end0-_Z30__device_stub__returnStatisticiiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15returnStatisticiiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15returnStatisticiiPKfPf,@object # @_Z15returnStatisticiiPKfPf
.section .rodata,"a",@progbits
.globl _Z15returnStatisticiiPKfPf
.p2align 3, 0x0
_Z15returnStatisticiiPKfPf:
.quad _Z30__device_stub__returnStatisticiiPKfPf
.size _Z15returnStatisticiiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15returnStatisticiiPKfPf"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__returnStatisticiiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15returnStatisticiiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void addKernel(int a, int b, int *c)
{
*c = (a+b)*(a+b);
}
__global__ void setVectorKernel(int *v, int g)
{
v[threadIdx.x + (blockDim.x * blockIdx.x)] = g;
}
__global__ void addVectorKernel(int* a, int* b, int* out, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N)
out[i] = a[i] + b[i];
}
__global__ void dwtKernel(float* input, float* output)
{
const int VECTOR_SIZE = 32;
const int VECTOR_HALF_SIZE = 16;
__shared__ float res[VECTOR_SIZE];
__shared__ float res2[VECTOR_SIZE];
// scaled and coefficients for Daubechies 4 wavelet
const int WaveletLength = 4;
float Coefficients[WaveletLength];
Coefficients[0] = 0.4829629131;
Coefficients[1] = 0.8365163037;
Coefficients[2] = 0.2241438680;
Coefficients[3] = -0.1294095226;
float Scales[WaveletLength];
Scales[0] = Coefficients[3];
Scales[1] = -Coefficients[2];
Scales[2] = Coefficients[1];
Scales[3] = -Coefficients[0];
int dx= threadIdx.x;
int k = 0;
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE){k -= VECTOR_SIZE;}
// set to zero for smoothing purposes, otherwise use commented formula
res[dx] += 0; // input[k] * Scales[i];
res[dx + VECTOR_HALF_SIZE] += input[k]*Coefficients[i];
}
// wait for DWT
__syncthreads();
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE) {k-=VECTOR_SIZE;}
res2[k] += (res[dx] *Scales[i] + res[dx + VECTOR_HALF_SIZE] * Coefficients[i]);
}
// wait for inverse transform
__syncthreads();
output[dx] = res2[dx];
output[dx + VECTOR_HALF_SIZE] = res2[dx+VECTOR_HALF_SIZE];
}
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i-1]);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i-1]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
int main()
{
// Number of CUDA devices
int devCount;
cudaGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
printf("\nPress any key to exit...");
char c;
scanf("%c", &c);
return 0;
} | code for sm_80
Function : _Z9dwtKernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.GT.AND P0, PT, R3.reuse, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x041fe20003f04270 */
/*0050*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000e220000004800 */
/*0060*/ SHF.L.U32 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027819 */
/* 0x040fe400000006ff */
/*0070*/ ISETP.GT.AND P1, PT, R3, 0xe, PT ; /* 0x0000000e0300780c */
/* 0x000fe40003f24270 */
/*0080*/ IADD3 R11, R2.reuse, -0x20, RZ ; /* 0xffffffe0020b7810 */
/* 0x040fe40007ffe0ff */
/*0090*/ IADD3 R5, R2, -0x1f, RZ ; /* 0xffffffe102057810 */
/* 0x000fc40007ffe0ff */
/*00a0*/ SEL R11, R11, R2, P0 ; /* 0x000000020b0b7207 */
/* 0x000fe40000000000 */
/*00b0*/ IADD3 R9, R2.reuse, -0x1e, RZ ; /* 0xffffffe202097810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ @!P0 IADD3 R5, R2.reuse, 0x1, RZ ; /* 0x0000000102058810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.WIDE R12, R11, R0, c[0x0][0x160] ; /* 0x000058000b0c7625 */
/* 0x000fe200078e0200 */
/*00e0*/ IADD3 R7, R2.reuse, -0x1d, RZ ; /* 0xffffffe302077810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ @!P1 IADD3 R9, R2, 0x2, RZ ; /* 0x0000000202099810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.WIDE R14, R0, R5, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fe200078e0205 */
/*0110*/ @!P1 IADD3 R7, R2, 0x3, RZ ; /* 0x0000000302079810 */
/* 0x000fe20007ffe0ff */
/*0120*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IMAD.WIDE R16, R0, R9, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fc400078e0209 */
/*0140*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee4000c1e1900 */
/*0150*/ IMAD.WIDE R18, R0, R7, c[0x0][0x160] ; /* 0x0000580000127625 */
/* 0x000fe400078e0207 */
/*0160*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDS R2, [R3.X4+0x40] ; /* 0x0000400003027984 */
/* 0x000ea20000004800 */
/*0190*/ FADD R4, RZ, R4 ; /* 0x00000004ff047221 */
/* 0x001fca0000000000 */
/*01a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe20000004800 */
/*01b0*/ FFMA R2, R13, 0.4829629063606262207, R2 ; /* 0x3ef746ea0d027823 */
/* 0x004fc80000000002 */
/*01c0*/ FFMA R2, R15, 0.83651632070541381836, R2 ; /* 0x3f5625ef0f027823 */
/* 0x008fc80000000002 */
/*01d0*/ FFMA R2, R17, 0.22414386272430419922, R2 ; /* 0x3e6585f811027823 */
/* 0x010fc80000000002 */
/*01e0*/ FFMA R2, R19, -0.12940952181816101074, R2 ; /* 0xbe0483ee13027823 */
/* 0x020fca0000000002 */
/*01f0*/ STS [R3.X4+0x40], R2 ; /* 0x0000400203007388 */
/* 0x000fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS R8, [R3.X4+0x40] ; /* 0x0000400003087984 */
/* 0x000e280000004800 */
/*0220*/ LDS R6, [R3.X4] ; /* 0x0000000003067984 */
/* 0x000e680000004800 */
/*0230*/ LDS R10, [R11.X4+0x80] ; /* 0x000080000b0a7984 */
/* 0x000ea20000004800 */
/*0240*/ FMUL R13, R8, 0.4829629063606262207 ; /* 0x3ef746ea080d7820 */
/* 0x001fc80000400000 */
/*0250*/ FFMA R13, R6, -0.12940952181816101074, R13 ; /* 0xbe0483ee060d7823 */
/* 0x002fc8000000000d */
/*0260*/ FADD R10, R13, R10 ; /* 0x0000000a0d0a7221 */
/* 0x004fe40000000000 */
/*0270*/ FMUL R13, R8, 0.83651632070541381836 ; /* 0x3f5625ef080d7820 */
/* 0x000fc60000400000 */
/*0280*/ STS [R11.X4+0x80], R10 ; /* 0x0000800a0b007388 */
/* 0x0001e20000004800 */
/*0290*/ FFMA R13, R6, -0.22414386272430419922, R13 ; /* 0xbe6585f8060d7823 */
/* 0x000fc6000000000d */
/*02a0*/ LDS R12, [R5.X4+0x80] ; /* 0x00008000050c7984 */
/* 0x000e620000004800 */
/*02b0*/ FMUL R11, R8, -0.12940952181816101074 ; /* 0xbe0483ee080b7820 */
/* 0x001fc80000400000 */
/*02c0*/ FFMA R11, R6, -0.4829629063606262207, R11 ; /* 0xbef746ea060b7823 */
/* 0x000fe4000000000b */
/*02d0*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x002fe40000000000 */
/*02e0*/ FMUL R13, R8, 0.22414386272430419922 ; /* 0x3e6585f8080d7820 */
/* 0x000fc60000400000 */
/*02f0*/ STS [R5.X4+0x80], R12 ; /* 0x0000800c05007388 */
/* 0x000fe20000004800 */
/*0300*/ FFMA R13, R6, 0.83651632070541381836, R13 ; /* 0x3f5625ef060d7823 */
/* 0x000fc6000000000d */
/*0310*/ LDS R2, [R9.X4+0x80] ; /* 0x0000800009027984 */
/* 0x000e240000004800 */
/*0320*/ FADD R2, R13, R2 ; /* 0x000000020d027221 */
/* 0x001fca0000000000 */
/*0330*/ STS [R9.X4+0x80], R2 ; /* 0x0000800209007388 */
/* 0x000fe80000004800 */
/*0340*/ LDS R4, [R7.X4+0x80] ; /* 0x0000800007047984 */
/* 0x000e240000004800 */
/*0350*/ FADD R6, R11, R4 ; /* 0x000000040b067221 */
/* 0x001fe40000000000 */
/*0360*/ IMAD.WIDE R4, R3, R0, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc600078e0200 */
/*0370*/ STS [R7.X4+0x80], R6 ; /* 0x0000800607007388 */
/* 0x000fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDS R11, [R3.X4+0x80] ; /* 0x00008000030b7984 */
/* 0x000e280000004800 */
/*03a0*/ LDS R13, [R3.X4+0xc0] ; /* 0x0000c000030d7984 */
/* 0x000e680000004800 */
/*03b0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x001fe8000c101904 */
/*03c0*/ STG.E [R4.64+0x40], R13 ; /* 0x0000400d04007986 */
/* 0x002fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15addVectorKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15setVectorKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKerneliiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x000fca00078e02ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void addKernel(int a, int b, int *c)
{
*c = (a+b)*(a+b);
}
__global__ void setVectorKernel(int *v, int g)
{
v[threadIdx.x + (blockDim.x * blockIdx.x)] = g;
}
__global__ void addVectorKernel(int* a, int* b, int* out, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N)
out[i] = a[i] + b[i];
}
__global__ void dwtKernel(float* input, float* output)
{
const int VECTOR_SIZE = 32;
const int VECTOR_HALF_SIZE = 16;
__shared__ float res[VECTOR_SIZE];
__shared__ float res2[VECTOR_SIZE];
// scaled and coefficients for Daubechies 4 wavelet
const int WaveletLength = 4;
float Coefficients[WaveletLength];
Coefficients[0] = 0.4829629131;
Coefficients[1] = 0.8365163037;
Coefficients[2] = 0.2241438680;
Coefficients[3] = -0.1294095226;
float Scales[WaveletLength];
Scales[0] = Coefficients[3];
Scales[1] = -Coefficients[2];
Scales[2] = Coefficients[1];
Scales[3] = -Coefficients[0];
int dx= threadIdx.x;
int k = 0;
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE){k -= VECTOR_SIZE;}
// set to zero for smoothing purposes, otherwise use commented formula
res[dx] += 0; // input[k] * Scales[i];
res[dx + VECTOR_HALF_SIZE] += input[k]*Coefficients[i];
}
// wait for DWT
__syncthreads();
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE) {k-=VECTOR_SIZE;}
res2[k] += (res[dx] *Scales[i] + res[dx + VECTOR_HALF_SIZE] * Coefficients[i]);
}
// wait for inverse transform
__syncthreads();
output[dx] = res2[dx];
output[dx + VECTOR_HALF_SIZE] = res2[dx+VECTOR_HALF_SIZE];
}
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i-1]);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i-1]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
int main()
{
// Number of CUDA devices
int devCount;
cudaGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
printf("\nPress any key to exit...");
char c;
scanf("%c", &c);
return 0;
} | .file "tmpxft_0016c15a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Major revision number: %d\n"
.align 8
.LC3:
.string "Minor revision number: %d\n"
.align 8
.LC4:
.string "Name: %s\n"
.align 8
.LC5:
.string "Total global memory: %u\n"
.align 8
.LC6:
.string "Total shared memory per block: %u\n"
.align 8
.LC7:
.string "Total registers per block: %d\n"
.align 8
.LC8:
.string "Warp size: %d\n"
.align 8
.LC9:
.string "Maximum memory pitch: %u\n"
.align 8
.LC10:
.string "Maximum threads per block: %d\n"
.align 8
.LC11:
.string "Maximum dimension %d of block: %d\n"
.align 8
.LC12:
.string "Maximum dimension %d of grid: %d\n"
.align 8
.LC13:
.string "Clock rate: %d\n"
.align 8
.LC14:
.string "Total constant memory: %u\n"
.align 8
.LC15:
.string "Texture alignment: %u\n"
.align 8
.LC16:
.string "Concurrent copy and execution: %s\n"
.align 8
.LC17:
.string "Number of multiprocessors: %d\n"
.align 8
.LC18:
.string "Kernel execution timeout: %s\n"
.text
.globl _Z12printDevProp14cudaDeviceProp
.type _Z12printDevProp14cudaDeviceProp, @function
_Z12printDevProp14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC11(%rip), %rbp
.L4:
movl 352(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L4
movl $1, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 364(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L5
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 424(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12printDevProp14cudaDeviceProp, .-_Z12printDevProp14cudaDeviceProp
.section .rodata.str1.1
.LC19:
.string "CUDA Device Query...\n"
.LC20:
.string "There are %d CUDA devices.\n"
.LC21:
.string "\nCUDA Device #%d\n"
.LC22:
.string "\nPress any key to exit..."
.LC23:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L14
movl $0, %ebx
leaq .LC21(%rip), %r12
.L15:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z12printDevProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L15
.L14:
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 11(%rsp), %rsi
leaq .LC23(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.globl _Z30__device_stub__Z9addKerneliiPiiiPi
.type _Z30__device_stub__Z9addKerneliiPiiiPi, @function
_Z30__device_stub__Z9addKerneliiPiiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKerneliiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9addKerneliiPiiiPi, .-_Z30__device_stub__Z9addKerneliiPiiiPi
.globl _Z9addKerneliiPi
.type _Z9addKerneliiPi, @function
_Z9addKerneliiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9addKerneliiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKerneliiPi, .-_Z9addKerneliiPi
.globl _Z36__device_stub__Z15setVectorKernelPiiPii
.type _Z36__device_stub__Z15setVectorKernelPiiPii, @function
_Z36__device_stub__Z15setVectorKernelPiiPii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15setVectorKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z15setVectorKernelPiiPii, .-_Z36__device_stub__Z15setVectorKernelPiiPii
.globl _Z15setVectorKernelPii
.type _Z15setVectorKernelPii, @function
_Z15setVectorKernelPii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15setVectorKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15setVectorKernelPii, .-_Z15setVectorKernelPii
.globl _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15addVectorKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i
.globl _Z15addVectorKernelPiS_S_i
.type _Z15addVectorKernelPiS_S_i, @function
_Z15addVectorKernelPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15addVectorKernelPiS_S_i, .-_Z15addVectorKernelPiS_S_i
.globl _Z30__device_stub__Z9dwtKernelPfS_PfS_
.type _Z30__device_stub__Z9dwtKernelPfS_PfS_, @function
_Z30__device_stub__Z9dwtKernelPfS_PfS_:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9dwtKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z30__device_stub__Z9dwtKernelPfS_PfS_, .-_Z30__device_stub__Z9dwtKernelPfS_PfS_
.globl _Z9dwtKernelPfS_
.type _Z9dwtKernelPfS_, @function
_Z9dwtKernelPfS_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9dwtKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z9dwtKernelPfS_, .-_Z9dwtKernelPfS_
.section .rodata.str1.1
.LC24:
.string "_Z9dwtKernelPfS_"
.LC25:
.string "_Z15addVectorKernelPiS_S_i"
.LC26:
.string "_Z15setVectorKernelPii"
.LC27:
.string "_Z9addKerneliiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z9dwtKernelPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z15addVectorKernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z15setVectorKernelPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKerneliiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void addKernel(int a, int b, int *c)
{
*c = (a+b)*(a+b);
}
__global__ void setVectorKernel(int *v, int g)
{
v[threadIdx.x + (blockDim.x * blockIdx.x)] = g;
}
__global__ void addVectorKernel(int* a, int* b, int* out, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N)
out[i] = a[i] + b[i];
}
__global__ void dwtKernel(float* input, float* output)
{
const int VECTOR_SIZE = 32;
const int VECTOR_HALF_SIZE = 16;
__shared__ float res[VECTOR_SIZE];
__shared__ float res2[VECTOR_SIZE];
// scaled and coefficients for Daubechies 4 wavelet
const int WaveletLength = 4;
float Coefficients[WaveletLength];
Coefficients[0] = 0.4829629131;
Coefficients[1] = 0.8365163037;
Coefficients[2] = 0.2241438680;
Coefficients[3] = -0.1294095226;
float Scales[WaveletLength];
Scales[0] = Coefficients[3];
Scales[1] = -Coefficients[2];
Scales[2] = Coefficients[1];
Scales[3] = -Coefficients[0];
int dx= threadIdx.x;
int k = 0;
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE){k -= VECTOR_SIZE;}
// set to zero for smoothing purposes, otherwise use commented formula
res[dx] += 0; // input[k] * Scales[i];
res[dx + VECTOR_HALF_SIZE] += input[k]*Coefficients[i];
}
// wait for DWT
__syncthreads();
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE) {k-=VECTOR_SIZE;}
res2[k] += (res[dx] *Scales[i] + res[dx + VECTOR_HALF_SIZE] * Coefficients[i]);
}
// wait for inverse transform
__syncthreads();
output[dx] = res2[dx];
output[dx + VECTOR_HALF_SIZE] = res2[dx+VECTOR_HALF_SIZE];
}
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i-1]);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i-1]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
int main()
{
// Number of CUDA devices
int devCount;
cudaGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
printf("\nPress any key to exit...");
char c;
scanf("%c", &c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void addKernel(int a, int b, int *c)
{
*c = (a+b)*(a+b);
}
__global__ void setVectorKernel(int *v, int g)
{
v[threadIdx.x + (blockDim.x * blockIdx.x)] = g;
}
__global__ void addVectorKernel(int* a, int* b, int* out, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N)
out[i] = a[i] + b[i];
}
__global__ void dwtKernel(float* input, float* output)
{
const int VECTOR_SIZE = 32;
const int VECTOR_HALF_SIZE = 16;
__shared__ float res[VECTOR_SIZE];
__shared__ float res2[VECTOR_SIZE];
// scaled and coefficients for Daubechies 4 wavelet
const int WaveletLength = 4;
float Coefficients[WaveletLength];
Coefficients[0] = 0.4829629131;
Coefficients[1] = 0.8365163037;
Coefficients[2] = 0.2241438680;
Coefficients[3] = -0.1294095226;
float Scales[WaveletLength];
Scales[0] = Coefficients[3];
Scales[1] = -Coefficients[2];
Scales[2] = Coefficients[1];
Scales[3] = -Coefficients[0];
int dx= threadIdx.x;
int k = 0;
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE){k -= VECTOR_SIZE;}
// set to zero for smoothing purposes, otherwise use commented formula
res[dx] += 0; // input[k] * Scales[i];
res[dx + VECTOR_HALF_SIZE] += input[k]*Coefficients[i];
}
// wait for DWT
__syncthreads();
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE) {k-=VECTOR_SIZE;}
res2[k] += (res[dx] *Scales[i] + res[dx + VECTOR_HALF_SIZE] * Coefficients[i]);
}
// wait for inverse transform
__syncthreads();
output[dx] = res2[dx];
output[dx + VECTOR_HALF_SIZE] = res2[dx+VECTOR_HALF_SIZE];
}
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i-1]);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i-1]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
int main()
{
// Number of CUDA devices
int devCount;
hipGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
printf("\nPress any key to exit...");
char c;
scanf("%c", &c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void addKernel(int a, int b, int *c)
{
*c = (a+b)*(a+b);
}
__global__ void setVectorKernel(int *v, int g)
{
v[threadIdx.x + (blockDim.x * blockIdx.x)] = g;
}
__global__ void addVectorKernel(int* a, int* b, int* out, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N)
out[i] = a[i] + b[i];
}
__global__ void dwtKernel(float* input, float* output)
{
const int VECTOR_SIZE = 32;
const int VECTOR_HALF_SIZE = 16;
__shared__ float res[VECTOR_SIZE];
__shared__ float res2[VECTOR_SIZE];
// scaled and coefficients for Daubechies 4 wavelet
const int WaveletLength = 4;
float Coefficients[WaveletLength];
Coefficients[0] = 0.4829629131;
Coefficients[1] = 0.8365163037;
Coefficients[2] = 0.2241438680;
Coefficients[3] = -0.1294095226;
float Scales[WaveletLength];
Scales[0] = Coefficients[3];
Scales[1] = -Coefficients[2];
Scales[2] = Coefficients[1];
Scales[3] = -Coefficients[0];
int dx= threadIdx.x;
int k = 0;
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE){k -= VECTOR_SIZE;}
// set to zero for smoothing purposes, otherwise use commented formula
res[dx] += 0; // input[k] * Scales[i];
res[dx + VECTOR_HALF_SIZE] += input[k]*Coefficients[i];
}
// wait for DWT
__syncthreads();
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE) {k-=VECTOR_SIZE;}
res2[k] += (res[dx] *Scales[i] + res[dx + VECTOR_HALF_SIZE] * Coefficients[i]);
}
// wait for inverse transform
__syncthreads();
output[dx] = res2[dx];
output[dx + VECTOR_HALF_SIZE] = res2[dx+VECTOR_HALF_SIZE];
}
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i-1]);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i-1]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
int main()
{
// Number of CUDA devices
int devCount;
hipGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
printf("\nPress any key to exit...");
char c;
scanf("%c", &c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKerneliiPi
.globl _Z9addKerneliiPi
.p2align 8
.type _Z9addKerneliiPi,@function
_Z9addKerneliiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKerneliiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKerneliiPi, .Lfunc_end0-_Z9addKerneliiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15setVectorKernelPii
.globl _Z15setVectorKernelPii
.p2align 8
.type _Z15setVectorKernelPii,@function
_Z15setVectorKernelPii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15setVectorKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15setVectorKernelPii, .Lfunc_end1-_Z15setVectorKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15addVectorKernelPiS_S_i
.globl _Z15addVectorKernelPiS_S_i
.p2align 8
.type _Z15addVectorKernelPiS_S_i,@function
_Z15addVectorKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15addVectorKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15addVectorKernelPiS_S_i, .Lfunc_end2-_Z15addVectorKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9dwtKernelPfS_
.globl _Z9dwtKernelPfS_
.p2align 8
.type _Z9dwtKernelPfS_,@function
_Z9dwtKernelPfS_:
v_dual_mov_b32 v6, 0x3f5625ef :: v_dual_lshlrev_b32 v3, 2, v0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 1, v0
s_mov_b64 s[4:5], 0
ds_load_2addr_b32 v[1:2], v3 offset1:16
v_add_nc_u32_e32 v4, 64, v3
.p2align 6
.LBB3_1:
v_add_nc_u32_e32 v7, s4, v5
s_cmp_eq_u32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, 32, v7
v_cmp_lt_u32_e32 vcc_lo, 31, v7
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s4, 2
global_load_b32 v7, v[7:8], off
v_cndmask_b32_e32 v8, 0x3ef746ea, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s4, 3
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v8, 0x3e6585f8, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 4
v_cndmask_b32_e32 v8, 0xbe0483ee, v8, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v8, v7
s_cbranch_scc0 .LBB3_1
v_add_f32_e32 v1, 0, v1
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[2:3], 0
ds_store_b32 v3, v1
ds_store_b32 v4, v2
v_mov_b32_e32 v4, 0xbe6585f8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[1:2], v5 offset1:16
v_lshlrev_b32_e32 v3, 1, v0
v_mov_b32_e32 v5, 0x3f5625ef
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB3_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s2, v3
s_cmp_eq_u32 s2, 1
v_subrev_nc_u32_e32 v7, 32, v6
v_cmp_lt_u32_e32 vcc_lo, 31, v6
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v7, 0xbe0483ee, v4, vcc_lo
v_cndmask_b32_e32 v8, 0x3ef746ea, v5, vcc_lo
v_lshlrev_b32_e32 v6, 2, v6
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s2, 3
v_cndmask_b32_e64 v7, v7, 0x3f5625ef, s4
v_cndmask_b32_e64 v8, v8, 0x3e6585f8, s4
ds_load_b32 v9, v6 offset:128
s_cselect_b32 s4, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e64 v7, v7, 0xbef746ea, s4
v_cndmask_b32_e64 v8, v8, 0xbe0483ee, s4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v2
v_fmac_f32_e32 v8, v7, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v7, v9, v8
ds_store_b32 v6, v7 offset:128
s_cbranch_scc0 .LBB3_3
s_set_inst_prefetch_distance 0x2
v_lshlrev_b32_e32 v2, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v2 offset0:32 offset1:48
v_add_nc_u32_e32 v3, 64, v2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v0, s[0:1]
global_store_b32 v3, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9dwtKernelPfS_
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9dwtKernelPfS_, .Lfunc_end3-_Z9dwtKernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKerneliiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9addKerneliiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15setVectorKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15setVectorKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15addVectorKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15addVectorKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9dwtKernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9dwtKernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void addKernel(int a, int b, int *c)
{
*c = (a+b)*(a+b);
}
__global__ void setVectorKernel(int *v, int g)
{
v[threadIdx.x + (blockDim.x * blockIdx.x)] = g;
}
__global__ void addVectorKernel(int* a, int* b, int* out, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N)
out[i] = a[i] + b[i];
}
__global__ void dwtKernel(float* input, float* output)
{
const int VECTOR_SIZE = 32;
const int VECTOR_HALF_SIZE = 16;
__shared__ float res[VECTOR_SIZE];
__shared__ float res2[VECTOR_SIZE];
// scaled and coefficients for Daubechies 4 wavelet
const int WaveletLength = 4;
float Coefficients[WaveletLength];
Coefficients[0] = 0.4829629131;
Coefficients[1] = 0.8365163037;
Coefficients[2] = 0.2241438680;
Coefficients[3] = -0.1294095226;
float Scales[WaveletLength];
Scales[0] = Coefficients[3];
Scales[1] = -Coefficients[2];
Scales[2] = Coefficients[1];
Scales[3] = -Coefficients[0];
int dx= threadIdx.x;
int k = 0;
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE){k -= VECTOR_SIZE;}
// set to zero for smoothing purposes, otherwise use commented formula
res[dx] += 0; // input[k] * Scales[i];
res[dx + VECTOR_HALF_SIZE] += input[k]*Coefficients[i];
}
// wait for DWT
__syncthreads();
for (int i = 0; i < WaveletLength; i++)
{
k = (dx*2)+i;
if(k>=VECTOR_SIZE) {k-=VECTOR_SIZE;}
res2[k] += (res[dx] *Scales[i] + res[dx + VECTOR_HALF_SIZE] * Coefficients[i]);
}
// wait for inverse transform
__syncthreads();
output[dx] = res2[dx];
output[dx + VECTOR_HALF_SIZE] = res2[dx+VECTOR_HALF_SIZE];
}
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i-1]);
for (int i = 1; i <= 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i-1]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
int main()
{
// Number of CUDA devices
int devCount;
hipGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
printf("\nPress any key to exit...");
char c;
scanf("%c", &c);
return 0;
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKerneliiPi # -- Begin function _Z24__device_stub__addKerneliiPi
.p2align 4, 0x90
.type _Z24__device_stub__addKerneliiPi,@function
_Z24__device_stub__addKerneliiPi: # @_Z24__device_stub__addKerneliiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKerneliiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKerneliiPi, .Lfunc_end0-_Z24__device_stub__addKerneliiPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__setVectorKernelPii # -- Begin function _Z30__device_stub__setVectorKernelPii
.p2align 4, 0x90
.type _Z30__device_stub__setVectorKernelPii,@function
_Z30__device_stub__setVectorKernelPii: # @_Z30__device_stub__setVectorKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15setVectorKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z30__device_stub__setVectorKernelPii, .Lfunc_end1-_Z30__device_stub__setVectorKernelPii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__addVectorKernelPiS_S_i # -- Begin function _Z30__device_stub__addVectorKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__addVectorKernelPiS_S_i,@function
_Z30__device_stub__addVectorKernelPiS_S_i: # @_Z30__device_stub__addVectorKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15addVectorKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__addVectorKernelPiS_S_i, .Lfunc_end2-_Z30__device_stub__addVectorKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__dwtKernelPfS_ # -- Begin function _Z24__device_stub__dwtKernelPfS_
.p2align 4, 0x90
.type _Z24__device_stub__dwtKernelPfS_,@function
_Z24__device_stub__dwtKernelPfS_: # @_Z24__device_stub__dwtKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9dwtKernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z24__device_stub__dwtKernelPfS_, .Lfunc_end3-_Z24__device_stub__dwtKernelPfS_
.cfi_endproc
# -- End function
.globl _Z12printDevProp20hipDeviceProp_tR0600 # -- Begin function _Z12printDevProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z12printDevProp20hipDeviceProp_tR0600,@function
_Z12printDevProp20hipDeviceProp_tR0600: # @_Z12printDevProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rbx
movl 392(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
incq %r14
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpq $3, %r14
jne .LBB4_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
incq %r14
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpq $3, %r14
jne .LBB4_3
# %bb.4:
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 384(%rbx)
movl $.L.str.16, %r15d
movl $.L.str.15, %r14d
movl $.L.str.15, %esi
cmoveq %r15, %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rbx)
cmoveq %r15, %r14
movl $.L.str.18, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12printDevProp20hipDeviceProp_tR0600, .Lfunc_end4-_Z12printDevProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr, %edi
callq puts@PLT
movl 1476(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 1476(%rsp)
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
leaq 1480(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.21, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep
callq _Z12printDevProp20hipDeviceProp_tR0600
incl %ebp
cmpl 1476(%rsp), %ebp
jl .LBB5_2
.LBB5_3: # %._crit_edge
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
leaq 1480(%rsp), %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq __isoc23_scanf
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKerneliiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15setVectorKernelPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15addVectorKernelPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9dwtKernelPfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKerneliiPi,@object # @_Z9addKerneliiPi
.section .rodata,"a",@progbits
.globl _Z9addKerneliiPi
.p2align 3, 0x0
_Z9addKerneliiPi:
.quad _Z24__device_stub__addKerneliiPi
.size _Z9addKerneliiPi, 8
.type _Z15setVectorKernelPii,@object # @_Z15setVectorKernelPii
.globl _Z15setVectorKernelPii
.p2align 3, 0x0
_Z15setVectorKernelPii:
.quad _Z30__device_stub__setVectorKernelPii
.size _Z15setVectorKernelPii, 8
.type _Z15addVectorKernelPiS_S_i,@object # @_Z15addVectorKernelPiS_S_i
.globl _Z15addVectorKernelPiS_S_i
.p2align 3, 0x0
_Z15addVectorKernelPiS_S_i:
.quad _Z30__device_stub__addVectorKernelPiS_S_i
.size _Z15addVectorKernelPiS_S_i, 8
.type _Z9dwtKernelPfS_,@object # @_Z9dwtKernelPfS_
.globl _Z9dwtKernelPfS_
.p2align 3, 0x0
_Z9dwtKernelPfS_:
.quad _Z24__device_stub__dwtKernelPfS_
.size _Z9dwtKernelPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Major revision number: %d\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minor revision number: %d\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total global memory: %u\n"
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total shared memory per block: %u\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total registers per block: %d\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Warp size: %d\n"
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum memory pitch: %u\n"
.size .L.str.7, 35
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum threads per block: %d\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Maximum dimension %d of block: %d\n"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum dimension %d of grid: %d\n"
.size .L.str.10, 36
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Clock rate: %d\n"
.size .L.str.11, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total constant memory: %u\n"
.size .L.str.12, 35
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Texture alignment: %u\n"
.size .L.str.13, 35
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Concurrent copy and execution: %s\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Yes"
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "No"
.size .L.str.16, 3
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.17, 35
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel execution timeout: %s\n"
.size .L.str.18, 35
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "There are %d CUDA devices.\n"
.size .L.str.20, 28
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "\nCUDA Device #%d\n"
.size .L.str.21, 18
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "\nPress any key to exit..."
.size .L.str.22, 26
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "%c"
.size .L.str.23, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKerneliiPi"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15setVectorKernelPii"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15addVectorKernelPiS_S_i"
.size .L__unnamed_3, 27
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9dwtKernelPfS_"
.size .L__unnamed_4, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA Device Query..."
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKerneliiPi
.addrsig_sym _Z30__device_stub__setVectorKernelPii
.addrsig_sym _Z30__device_stub__addVectorKernelPiS_S_i
.addrsig_sym _Z24__device_stub__dwtKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKerneliiPi
.addrsig_sym _Z15setVectorKernelPii
.addrsig_sym _Z15addVectorKernelPiS_S_i
.addrsig_sym _Z9dwtKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9dwtKernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.GT.AND P0, PT, R3.reuse, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x041fe20003f04270 */
/*0050*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000e220000004800 */
/*0060*/ SHF.L.U32 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027819 */
/* 0x040fe400000006ff */
/*0070*/ ISETP.GT.AND P1, PT, R3, 0xe, PT ; /* 0x0000000e0300780c */
/* 0x000fe40003f24270 */
/*0080*/ IADD3 R11, R2.reuse, -0x20, RZ ; /* 0xffffffe0020b7810 */
/* 0x040fe40007ffe0ff */
/*0090*/ IADD3 R5, R2, -0x1f, RZ ; /* 0xffffffe102057810 */
/* 0x000fc40007ffe0ff */
/*00a0*/ SEL R11, R11, R2, P0 ; /* 0x000000020b0b7207 */
/* 0x000fe40000000000 */
/*00b0*/ IADD3 R9, R2.reuse, -0x1e, RZ ; /* 0xffffffe202097810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ @!P0 IADD3 R5, R2.reuse, 0x1, RZ ; /* 0x0000000102058810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.WIDE R12, R11, R0, c[0x0][0x160] ; /* 0x000058000b0c7625 */
/* 0x000fe200078e0200 */
/*00e0*/ IADD3 R7, R2.reuse, -0x1d, RZ ; /* 0xffffffe302077810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ @!P1 IADD3 R9, R2, 0x2, RZ ; /* 0x0000000202099810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.WIDE R14, R0, R5, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fe200078e0205 */
/*0110*/ @!P1 IADD3 R7, R2, 0x3, RZ ; /* 0x0000000302079810 */
/* 0x000fe20007ffe0ff */
/*0120*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IMAD.WIDE R16, R0, R9, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fc400078e0209 */
/*0140*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee4000c1e1900 */
/*0150*/ IMAD.WIDE R18, R0, R7, c[0x0][0x160] ; /* 0x0000580000127625 */
/* 0x000fe400078e0207 */
/*0160*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDS R2, [R3.X4+0x40] ; /* 0x0000400003027984 */
/* 0x000ea20000004800 */
/*0190*/ FADD R4, RZ, R4 ; /* 0x00000004ff047221 */
/* 0x001fca0000000000 */
/*01a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe20000004800 */
/*01b0*/ FFMA R2, R13, 0.4829629063606262207, R2 ; /* 0x3ef746ea0d027823 */
/* 0x004fc80000000002 */
/*01c0*/ FFMA R2, R15, 0.83651632070541381836, R2 ; /* 0x3f5625ef0f027823 */
/* 0x008fc80000000002 */
/*01d0*/ FFMA R2, R17, 0.22414386272430419922, R2 ; /* 0x3e6585f811027823 */
/* 0x010fc80000000002 */
/*01e0*/ FFMA R2, R19, -0.12940952181816101074, R2 ; /* 0xbe0483ee13027823 */
/* 0x020fca0000000002 */
/*01f0*/ STS [R3.X4+0x40], R2 ; /* 0x0000400203007388 */
/* 0x000fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS R8, [R3.X4+0x40] ; /* 0x0000400003087984 */
/* 0x000e280000004800 */
/*0220*/ LDS R6, [R3.X4] ; /* 0x0000000003067984 */
/* 0x000e680000004800 */
/*0230*/ LDS R10, [R11.X4+0x80] ; /* 0x000080000b0a7984 */
/* 0x000ea20000004800 */
/*0240*/ FMUL R13, R8, 0.4829629063606262207 ; /* 0x3ef746ea080d7820 */
/* 0x001fc80000400000 */
/*0250*/ FFMA R13, R6, -0.12940952181816101074, R13 ; /* 0xbe0483ee060d7823 */
/* 0x002fc8000000000d */
/*0260*/ FADD R10, R13, R10 ; /* 0x0000000a0d0a7221 */
/* 0x004fe40000000000 */
/*0270*/ FMUL R13, R8, 0.83651632070541381836 ; /* 0x3f5625ef080d7820 */
/* 0x000fc60000400000 */
/*0280*/ STS [R11.X4+0x80], R10 ; /* 0x0000800a0b007388 */
/* 0x0001e20000004800 */
/*0290*/ FFMA R13, R6, -0.22414386272430419922, R13 ; /* 0xbe6585f8060d7823 */
/* 0x000fc6000000000d */
/*02a0*/ LDS R12, [R5.X4+0x80] ; /* 0x00008000050c7984 */
/* 0x000e620000004800 */
/*02b0*/ FMUL R11, R8, -0.12940952181816101074 ; /* 0xbe0483ee080b7820 */
/* 0x001fc80000400000 */
/*02c0*/ FFMA R11, R6, -0.4829629063606262207, R11 ; /* 0xbef746ea060b7823 */
/* 0x000fe4000000000b */
/*02d0*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x002fe40000000000 */
/*02e0*/ FMUL R13, R8, 0.22414386272430419922 ; /* 0x3e6585f8080d7820 */
/* 0x000fc60000400000 */
/*02f0*/ STS [R5.X4+0x80], R12 ; /* 0x0000800c05007388 */
/* 0x000fe20000004800 */
/*0300*/ FFMA R13, R6, 0.83651632070541381836, R13 ; /* 0x3f5625ef060d7823 */
/* 0x000fc6000000000d */
/*0310*/ LDS R2, [R9.X4+0x80] ; /* 0x0000800009027984 */
/* 0x000e240000004800 */
/*0320*/ FADD R2, R13, R2 ; /* 0x000000020d027221 */
/* 0x001fca0000000000 */
/*0330*/ STS [R9.X4+0x80], R2 ; /* 0x0000800209007388 */
/* 0x000fe80000004800 */
/*0340*/ LDS R4, [R7.X4+0x80] ; /* 0x0000800007047984 */
/* 0x000e240000004800 */
/*0350*/ FADD R6, R11, R4 ; /* 0x000000040b067221 */
/* 0x001fe40000000000 */
/*0360*/ IMAD.WIDE R4, R3, R0, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc600078e0200 */
/*0370*/ STS [R7.X4+0x80], R6 ; /* 0x0000800607007388 */
/* 0x000fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDS R11, [R3.X4+0x80] ; /* 0x00008000030b7984 */
/* 0x000e280000004800 */
/*03a0*/ LDS R13, [R3.X4+0xc0] ; /* 0x0000c000030d7984 */
/* 0x000e680000004800 */
/*03b0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x001fe8000c101904 */
/*03c0*/ STG.E [R4.64+0x40], R13 ; /* 0x0000400d04007986 */
/* 0x002fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15addVectorKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15setVectorKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKerneliiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x000fca00078e02ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKerneliiPi
.globl _Z9addKerneliiPi
.p2align 8
.type _Z9addKerneliiPi,@function
_Z9addKerneliiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKerneliiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKerneliiPi, .Lfunc_end0-_Z9addKerneliiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15setVectorKernelPii
.globl _Z15setVectorKernelPii
.p2align 8
.type _Z15setVectorKernelPii,@function
_Z15setVectorKernelPii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15setVectorKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15setVectorKernelPii, .Lfunc_end1-_Z15setVectorKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15addVectorKernelPiS_S_i
.globl _Z15addVectorKernelPiS_S_i
.p2align 8
.type _Z15addVectorKernelPiS_S_i,@function
_Z15addVectorKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15addVectorKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15addVectorKernelPiS_S_i, .Lfunc_end2-_Z15addVectorKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9dwtKernelPfS_
.globl _Z9dwtKernelPfS_
.p2align 8
.type _Z9dwtKernelPfS_,@function
_Z9dwtKernelPfS_:
v_dual_mov_b32 v6, 0x3f5625ef :: v_dual_lshlrev_b32 v3, 2, v0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 1, v0
s_mov_b64 s[4:5], 0
ds_load_2addr_b32 v[1:2], v3 offset1:16
v_add_nc_u32_e32 v4, 64, v3
.p2align 6
.LBB3_1:
v_add_nc_u32_e32 v7, s4, v5
s_cmp_eq_u32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, 32, v7
v_cmp_lt_u32_e32 vcc_lo, 31, v7
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s4, 2
global_load_b32 v7, v[7:8], off
v_cndmask_b32_e32 v8, 0x3ef746ea, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s4, 3
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v8, 0x3e6585f8, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 4
v_cndmask_b32_e32 v8, 0xbe0483ee, v8, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v8, v7
s_cbranch_scc0 .LBB3_1
v_add_f32_e32 v1, 0, v1
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[2:3], 0
ds_store_b32 v3, v1
ds_store_b32 v4, v2
v_mov_b32_e32 v4, 0xbe6585f8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[1:2], v5 offset1:16
v_lshlrev_b32_e32 v3, 1, v0
v_mov_b32_e32 v5, 0x3f5625ef
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB3_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s2, v3
s_cmp_eq_u32 s2, 1
v_subrev_nc_u32_e32 v7, 32, v6
v_cmp_lt_u32_e32 vcc_lo, 31, v6
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v7, 0xbe0483ee, v4, vcc_lo
v_cndmask_b32_e32 v8, 0x3ef746ea, v5, vcc_lo
v_lshlrev_b32_e32 v6, 2, v6
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s2, 3
v_cndmask_b32_e64 v7, v7, 0x3f5625ef, s4
v_cndmask_b32_e64 v8, v8, 0x3e6585f8, s4
ds_load_b32 v9, v6 offset:128
s_cselect_b32 s4, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e64 v7, v7, 0xbef746ea, s4
v_cndmask_b32_e64 v8, v8, 0xbe0483ee, s4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v2
v_fmac_f32_e32 v8, v7, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v7, v9, v8
ds_store_b32 v6, v7 offset:128
s_cbranch_scc0 .LBB3_3
s_set_inst_prefetch_distance 0x2
v_lshlrev_b32_e32 v2, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v2 offset0:32 offset1:48
v_add_nc_u32_e32 v3, 64, v2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v0, s[0:1]
global_store_b32 v3, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9dwtKernelPfS_
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9dwtKernelPfS_, .Lfunc_end3-_Z9dwtKernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKerneliiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9addKerneliiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15setVectorKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15setVectorKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15addVectorKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15addVectorKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9dwtKernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9dwtKernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c15a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Major revision number: %d\n"
.align 8
.LC3:
.string "Minor revision number: %d\n"
.align 8
.LC4:
.string "Name: %s\n"
.align 8
.LC5:
.string "Total global memory: %u\n"
.align 8
.LC6:
.string "Total shared memory per block: %u\n"
.align 8
.LC7:
.string "Total registers per block: %d\n"
.align 8
.LC8:
.string "Warp size: %d\n"
.align 8
.LC9:
.string "Maximum memory pitch: %u\n"
.align 8
.LC10:
.string "Maximum threads per block: %d\n"
.align 8
.LC11:
.string "Maximum dimension %d of block: %d\n"
.align 8
.LC12:
.string "Maximum dimension %d of grid: %d\n"
.align 8
.LC13:
.string "Clock rate: %d\n"
.align 8
.LC14:
.string "Total constant memory: %u\n"
.align 8
.LC15:
.string "Texture alignment: %u\n"
.align 8
.LC16:
.string "Concurrent copy and execution: %s\n"
.align 8
.LC17:
.string "Number of multiprocessors: %d\n"
.align 8
.LC18:
.string "Kernel execution timeout: %s\n"
.text
.globl _Z12printDevProp14cudaDeviceProp
.type _Z12printDevProp14cudaDeviceProp, @function
_Z12printDevProp14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC11(%rip), %rbp
.L4:
movl 352(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L4
movl $1, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 364(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L5
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 424(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12printDevProp14cudaDeviceProp, .-_Z12printDevProp14cudaDeviceProp
.section .rodata.str1.1
.LC19:
.string "CUDA Device Query...\n"
.LC20:
.string "There are %d CUDA devices.\n"
.LC21:
.string "\nCUDA Device #%d\n"
.LC22:
.string "\nPress any key to exit..."
.LC23:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L14
movl $0, %ebx
leaq .LC21(%rip), %r12
.L15:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z12printDevProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L15
.L14:
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 11(%rsp), %rsi
leaq .LC23(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.globl _Z30__device_stub__Z9addKerneliiPiiiPi
.type _Z30__device_stub__Z9addKerneliiPiiiPi, @function
_Z30__device_stub__Z9addKerneliiPiiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKerneliiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9addKerneliiPiiiPi, .-_Z30__device_stub__Z9addKerneliiPiiiPi
.globl _Z9addKerneliiPi
.type _Z9addKerneliiPi, @function
_Z9addKerneliiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9addKerneliiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKerneliiPi, .-_Z9addKerneliiPi
.globl _Z36__device_stub__Z15setVectorKernelPiiPii
.type _Z36__device_stub__Z15setVectorKernelPiiPii, @function
_Z36__device_stub__Z15setVectorKernelPiiPii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15setVectorKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z15setVectorKernelPiiPii, .-_Z36__device_stub__Z15setVectorKernelPiiPii
.globl _Z15setVectorKernelPii
.type _Z15setVectorKernelPii, @function
_Z15setVectorKernelPii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15setVectorKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15setVectorKernelPii, .-_Z15setVectorKernelPii
.globl _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15addVectorKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i
.globl _Z15addVectorKernelPiS_S_i
.type _Z15addVectorKernelPiS_S_i, @function
_Z15addVectorKernelPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15addVectorKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15addVectorKernelPiS_S_i, .-_Z15addVectorKernelPiS_S_i
.globl _Z30__device_stub__Z9dwtKernelPfS_PfS_
.type _Z30__device_stub__Z9dwtKernelPfS_PfS_, @function
_Z30__device_stub__Z9dwtKernelPfS_PfS_:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9dwtKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z30__device_stub__Z9dwtKernelPfS_PfS_, .-_Z30__device_stub__Z9dwtKernelPfS_PfS_
.globl _Z9dwtKernelPfS_
.type _Z9dwtKernelPfS_, @function
_Z9dwtKernelPfS_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9dwtKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z9dwtKernelPfS_, .-_Z9dwtKernelPfS_
.section .rodata.str1.1
.LC24:
.string "_Z9dwtKernelPfS_"
.LC25:
.string "_Z15addVectorKernelPiS_S_i"
.LC26:
.string "_Z15setVectorKernelPii"
.LC27:
.string "_Z9addKerneliiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z9dwtKernelPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z15addVectorKernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z15setVectorKernelPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKerneliiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKerneliiPi # -- Begin function _Z24__device_stub__addKerneliiPi
.p2align 4, 0x90
.type _Z24__device_stub__addKerneliiPi,@function
_Z24__device_stub__addKerneliiPi: # @_Z24__device_stub__addKerneliiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKerneliiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKerneliiPi, .Lfunc_end0-_Z24__device_stub__addKerneliiPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__setVectorKernelPii # -- Begin function _Z30__device_stub__setVectorKernelPii
.p2align 4, 0x90
.type _Z30__device_stub__setVectorKernelPii,@function
_Z30__device_stub__setVectorKernelPii: # @_Z30__device_stub__setVectorKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15setVectorKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z30__device_stub__setVectorKernelPii, .Lfunc_end1-_Z30__device_stub__setVectorKernelPii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__addVectorKernelPiS_S_i # -- Begin function _Z30__device_stub__addVectorKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__addVectorKernelPiS_S_i,@function
_Z30__device_stub__addVectorKernelPiS_S_i: # @_Z30__device_stub__addVectorKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15addVectorKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__addVectorKernelPiS_S_i, .Lfunc_end2-_Z30__device_stub__addVectorKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__dwtKernelPfS_ # -- Begin function _Z24__device_stub__dwtKernelPfS_
.p2align 4, 0x90
.type _Z24__device_stub__dwtKernelPfS_,@function
_Z24__device_stub__dwtKernelPfS_: # @_Z24__device_stub__dwtKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9dwtKernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z24__device_stub__dwtKernelPfS_, .Lfunc_end3-_Z24__device_stub__dwtKernelPfS_
.cfi_endproc
# -- End function
.globl _Z12printDevProp20hipDeviceProp_tR0600 # -- Begin function _Z12printDevProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z12printDevProp20hipDeviceProp_tR0600,@function
_Z12printDevProp20hipDeviceProp_tR0600: # @_Z12printDevProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rbx
movl 392(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
incq %r14
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpq $3, %r14
jne .LBB4_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
incq %r14
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpq $3, %r14
jne .LBB4_3
# %bb.4:
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 384(%rbx)
movl $.L.str.16, %r15d
movl $.L.str.15, %r14d
movl $.L.str.15, %esi
cmoveq %r15, %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rbx)
cmoveq %r15, %r14
movl $.L.str.18, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12printDevProp20hipDeviceProp_tR0600, .Lfunc_end4-_Z12printDevProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr, %edi
callq puts@PLT
movl 1476(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 1476(%rsp)
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
leaq 1480(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.21, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep
callq _Z12printDevProp20hipDeviceProp_tR0600
incl %ebp
cmpl 1476(%rsp), %ebp
jl .LBB5_2
.LBB5_3: # %._crit_edge
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
leaq 1480(%rsp), %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq __isoc23_scanf
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKerneliiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15setVectorKernelPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15addVectorKernelPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9dwtKernelPfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKerneliiPi,@object # @_Z9addKerneliiPi
.section .rodata,"a",@progbits
.globl _Z9addKerneliiPi
.p2align 3, 0x0
_Z9addKerneliiPi:
.quad _Z24__device_stub__addKerneliiPi
.size _Z9addKerneliiPi, 8
.type _Z15setVectorKernelPii,@object # @_Z15setVectorKernelPii
.globl _Z15setVectorKernelPii
.p2align 3, 0x0
_Z15setVectorKernelPii:
.quad _Z30__device_stub__setVectorKernelPii
.size _Z15setVectorKernelPii, 8
.type _Z15addVectorKernelPiS_S_i,@object # @_Z15addVectorKernelPiS_S_i
.globl _Z15addVectorKernelPiS_S_i
.p2align 3, 0x0
_Z15addVectorKernelPiS_S_i:
.quad _Z30__device_stub__addVectorKernelPiS_S_i
.size _Z15addVectorKernelPiS_S_i, 8
.type _Z9dwtKernelPfS_,@object # @_Z9dwtKernelPfS_
.globl _Z9dwtKernelPfS_
.p2align 3, 0x0
_Z9dwtKernelPfS_:
.quad _Z24__device_stub__dwtKernelPfS_
.size _Z9dwtKernelPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Major revision number: %d\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minor revision number: %d\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total global memory: %u\n"
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total shared memory per block: %u\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total registers per block: %d\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Warp size: %d\n"
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum memory pitch: %u\n"
.size .L.str.7, 35
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum threads per block: %d\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Maximum dimension %d of block: %d\n"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum dimension %d of grid: %d\n"
.size .L.str.10, 36
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Clock rate: %d\n"
.size .L.str.11, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total constant memory: %u\n"
.size .L.str.12, 35
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Texture alignment: %u\n"
.size .L.str.13, 35
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Concurrent copy and execution: %s\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Yes"
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "No"
.size .L.str.16, 3
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.17, 35
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel execution timeout: %s\n"
.size .L.str.18, 35
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "There are %d CUDA devices.\n"
.size .L.str.20, 28
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "\nCUDA Device #%d\n"
.size .L.str.21, 18
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "\nPress any key to exit..."
.size .L.str.22, 26
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "%c"
.size .L.str.23, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKerneliiPi"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15setVectorKernelPii"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15addVectorKernelPiS_S_i"
.size .L__unnamed_3, 27
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9dwtKernelPfS_"
.size .L__unnamed_4, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA Device Query..."
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKerneliiPi
.addrsig_sym _Z30__device_stub__setVectorKernelPii
.addrsig_sym _Z30__device_stub__addVectorKernelPiS_S_i
.addrsig_sym _Z24__device_stub__dwtKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKerneliiPi
.addrsig_sym _Z15setVectorKernelPii
.addrsig_sym _Z15addVectorKernelPiS_S_i
.addrsig_sym _Z9dwtKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kExpand(float *images, float* targets, int num_images, int num_input_channels, int image_size_y, int image_size_x, int num_modules_y, int num_modules_x, int kernel_size_y, int kernel_size_x, int padding_y, int padding_x, int stride_y, int stride_x, int num_modules_batch, int module_id_offset) {
int color = blockIdx.y;
int src_module_id = module_id_offset + blockIdx.x;
int dst_module_id = blockIdx.x;
int module_id_x = src_module_id % num_modules_x;
int module_id_y = src_module_id / num_modules_x;
int startX = module_id_x * stride_x + padding_x;
int startY = module_id_y * stride_y + padding_y;
int Y, X;
long target_id, source_id;
images += num_images * image_size_x * image_size_y * color;
targets += num_images * (dst_module_id + num_modules_batch * (kernel_size_y * kernel_size_x * color));
for (int y = 0; y < kernel_size_y; y++) {
Y = startY + y;
for (int x = 0; x < kernel_size_x; x++) {
X = startX + x;
target_id = num_images * num_modules_batch * (x + kernel_size_x * y);
source_id = num_images * (X + image_size_x * Y);
if (X < 0 || X >= image_size_x || Y < 0 || Y >= image_size_y) {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = 0;
}
} else {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = images[source_id + im];
}
}
__syncthreads();
}
}
} | code for sm_80
Function : _Z7kExpandPfS_iiiiiiiiiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IABS R5, c[0x0][0x184] ; /* 0x0000610000057a13 */
/* 0x000fe20000000000 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e700000209400 */
/*0080*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0090*/ IADD3 R4, R7, c[0x0][0x1a4], RZ ; /* 0x0000690007047a10 */
/* 0x001fc40007ffe0ff */
/*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fe40007ffe0ff */
/*00b0*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fc60000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD R9, R6, R5, RZ ; /* 0x0000000506097224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R0, R5.reuse, R6, R0 ; /* 0x0000000605007224 */
/* 0x040fe400078e0200 */
/*0140*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e260000002600 */
/*0150*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0160*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f45270 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*01a0*/ LOP3.LUT R0, R4, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610004007a12 */
/* 0x000fe200078e3cff */
/*01b0*/ IMAD R2, R6, c[0x0][0x188], RZ ; /* 0x0000620006027a24 */
/* 0x001fc600078e02ff */
/*01c0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f26270 */
/*01d0*/ IMAD R2, R2, c[0x0][0x18c], RZ ; /* 0x0000630002027a24 */
/* 0x000fe200078e02ff */
/*01e0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e260000002100 */
/*01f0*/ IMAD R2, R2, c[0x0][0x1a0], R7 ; /* 0x0000680002027a24 */
/* 0x000fe400078e0207 */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff077624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a24 */
/* 0x000fc400078e02ff */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*0240*/ IMAD R3, R6, c[0x0][0x170], RZ ; /* 0x00005c0006037a24 */
/* 0x000fe200078e02ff */
/*0250*/ SHF.R.S32.HI R8, RZ, 0x1f, R2 ; /* 0x0000001fff087819 */
/* 0x000fe20000011402 */
/*0260*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0270*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff05aa12 */
/* 0x000fe200078e33ff */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff067624 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a05 */
/*02a0*/ IMAD R4, R9, c[0x0][0x184], R4 ; /* 0x0000610009047a24 */
/* 0x000fe400078e0204 */
/*02b0*/ IMAD R9, R3, c[0x0][0x178], RZ ; /* 0x00005e0003097a24 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD R3, R5, R6, c[0x0][0x190] ; /* 0x0000640005037624 */
/* 0x000fe400078e0206 */
/*02d0*/ IMAD R4, R4, R7, c[0x0][0x194] ; /* 0x0000650004047624 */
/* 0x000fe400078e0207 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD R9, R9, c[0x0][0x17c], RZ ; /* 0x00005f0009097a24 */
/* 0x001fc400078e02ff */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fca00078e00ff */
/*0310*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0320*/ @!P0 BRA 0x6f0 ; /* 0x000003c000008947 */
/* 0x001fea0003800000 */
/*0330*/ IMAD.IADD R7, R3, 0x1, R6 ; /* 0x0000000103077824 */
/* 0x000fe400078e0206 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.IADD R12, R4, 0x1, R5 ; /* 0x00000001040c7824 */
/* 0x001fe200078e0205 */
/*0360*/ ULDC UR4, c[0x0][0x1a0] ; /* 0x0000680000047ab9 */
/* 0x000fe20000000800 */
/*0370*/ BSSY B0, 0x6d0 ; /* 0x0000035000007945 */
/* 0x000fe20003800000 */
/*0380*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*0390*/ LOP3.LUT R10, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c0a7212 */
/* 0x000fe200078efcff */
/*03a0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*03b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f06270 */
/*03c0*/ IMAD R10, R6, c[0x0][0x18c], R5 ; /* 0x00006300060a7a24 */
/* 0x000fe200078e0205 */
/*03d0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x17c], !P0 ; /* 0x00005f000c007a0c */
/* 0x000fe20004706670 */
/*03f0*/ IMAD R11, R10, UR4, RZ ; /* 0x000000040a0b7c24 */
/* 0x000fe2000f8e02ff */
/*0400*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x18c], PT ; /* 0x0000630005007a0c */
/* 0x000fe40003f26270 */
/*0410*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fe40000706670 */
/*0420*/ SHF.R.S32.HI R13, RZ, 0x1f, R11 ; /* 0x0000001fff0d7819 */
/* 0x000fd6000001140b */
/*0430*/ @P0 BRA 0x5f0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0450*/ BSSY B1, 0x5e0 ; /* 0x0000018000017945 */
/* 0x000fd80003800000 */
/*0460*/ @P0 BRA 0x5d0 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD R10, R7, c[0x0][0x17c], R12 ; /* 0x00005f00070a7a24 */
/* 0x000fe200078e020c */
/*0480*/ IADD3 R19, P2, R2, R11, RZ ; /* 0x0000000b02137210 */
/* 0x000fe20007f5e0ff */
/*0490*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0000 */
/*04a0*/ IMAD R10, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0a7a24 */
/* 0x000fe400078e02ff */
/*04b0*/ IMAD.X R21, R8, 0x1, R13, P2 ; /* 0x0000000108157824 */
/* 0x000fc600010e060d */
/*04c0*/ IADD3 R15, P0, R9, R10, RZ ; /* 0x0000000a090f7210 */
/* 0x000fe40007f1e0ff */
/*04d0*/ SHF.R.S32.HI R10, RZ, 0x1f, R10 ; /* 0x0000001fff0a7819 */
/* 0x000fc8000001140a */
/*04e0*/ LEA.HI.X.SX32 R17, R9, R10, 0x1, P0 ; /* 0x0000000a09117211 */
/* 0x000fe400000f0eff */
/*04f0*/ SHF.R.S32.HI R12, RZ, 0x1f, R14 ; /* 0x0000001fff0c7819 */
/* 0x001fe4000001140e */
/*0500*/ IADD3 R11, P0, R14, R15, RZ ; /* 0x0000000f0e0b7210 */
/* 0x000fca0007f1e0ff */
/*0510*/ IMAD.X R16, R12, 0x1, R17, P0 ; /* 0x000000010c107824 */
/* 0x000fe200000e0611 */
/*0520*/ LEA R10, P0, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b0a7a11 */
/* 0x000fc800078010ff */
/*0530*/ LEA.HI.X R11, R11, c[0x0][0x164], R16, 0x2, P0 ; /* 0x000059000b0b7a11 */
/* 0x000fcc00000f1410 */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R13, P0, R14.reuse, R19, RZ ; /* 0x000000130e0d7210 */
/* 0x040fe40007f1e0ff */
/*0560*/ IADD3 R14, R14, c[0x0][0x0], RZ ; /* 0x000000000e0e7a10 */
/* 0x000fc60007ffe0ff */
/*0570*/ IMAD.X R16, R12, 0x1, R21, P0 ; /* 0x000000010c107824 */
/* 0x000fe200000e0615 */
/*0580*/ LEA R12, P0, R13, c[0x0][0x168], 0x2 ; /* 0x00005a000d0c7a11 */
/* 0x000fc800078010ff */
/*0590*/ LEA.HI.X R13, R13, c[0x0][0x16c], R16, 0x2, P0 ; /* 0x00005b000d0d7a11 */
/* 0x000fe400000f1410 */
/*05a0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x170], PT ; /* 0x00005c000e007a0c */
/* 0x000fc60003f06270 */
/*05b0*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0041f4000c101906 */
/*05c0*/ @!P0 BRA 0x4f0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x6c0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x6c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R15, P0, R2, R11, RZ ; /* 0x0000000b020f7210 */
/* 0x000fe20007f1e0ff */
/*0620*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0000 */
/*0630*/ IMAD.X R13, R8, 0x1, R13, P0 ; /* 0x00000001080d7824 */
/* 0x000fe400000e060d */
/*0640*/ IADD3 R11, P0, R12, R15, RZ ; /* 0x0000000f0c0b7210 */
/* 0x000fc80007f1e0ff */
/*0650*/ LEA.HI.X.SX32 R14, R12.reuse, R13, 0x1, P0 ; /* 0x0000000d0c0e7211 */
/* 0x040fe400000f0eff */
/*0660*/ LEA R10, P0, R11.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a000b0a7a11 */
/* 0x040fe400078010ff */
/*0670*/ IADD3 R12, R12, c[0x0][0x0], RZ ; /* 0x000000000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0680*/ LEA.HI.X R11, R11, c[0x0][0x16c], R14, 0x2, P0 ; /* 0x00005b000b0b7a11 */
/* 0x000fe400000f140e */
/*0690*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fc60003f06270 */
/*06a0*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0001f4000c101906 */
/*06b0*/ @!P0 BRA 0x640 ; /* 0xffffff8000008947 */
/* 0x001fea000383ffff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06e0*/ @!P1 BRA 0x350 ; /* 0xfffffc6000009947 */
/* 0x000fea000383ffff */
/*06f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0700*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x188], PT ; /* 0x0000620006007a0c */
/* 0x000fda0003f06270 */
/*0710*/ @!P0 BRA 0x300 ; /* 0xfffffbe000008947 */
/* 0x000fea000383ffff */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kExpand(float *images, float* targets, int num_images, int num_input_channels, int image_size_y, int image_size_x, int num_modules_y, int num_modules_x, int kernel_size_y, int kernel_size_x, int padding_y, int padding_x, int stride_y, int stride_x, int num_modules_batch, int module_id_offset) {
int color = blockIdx.y;
int src_module_id = module_id_offset + blockIdx.x;
int dst_module_id = blockIdx.x;
int module_id_x = src_module_id % num_modules_x;
int module_id_y = src_module_id / num_modules_x;
int startX = module_id_x * stride_x + padding_x;
int startY = module_id_y * stride_y + padding_y;
int Y, X;
long target_id, source_id;
images += num_images * image_size_x * image_size_y * color;
targets += num_images * (dst_module_id + num_modules_batch * (kernel_size_y * kernel_size_x * color));
for (int y = 0; y < kernel_size_y; y++) {
Y = startY + y;
for (int x = 0; x < kernel_size_x; x++) {
X = startX + x;
target_id = num_images * num_modules_batch * (x + kernel_size_x * y);
source_id = num_images * (X + image_size_x * Y);
if (X < 0 || X >= image_size_x || Y < 0 || Y >= image_size_y) {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = 0;
}
} else {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = images[source_id + im];
}
}
__syncthreads();
}
}
} | .file "tmpxft_000375ac_00000000-6_kExpand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii
.type _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii, @function
_Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 264
pushq 40(%rsp)
.cfi_def_cfa_offset 272
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kExpandPfS_iiiiiiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii, .-_Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii
.globl _Z7kExpandPfS_iiiiiiiiiiiiii
.type _Z7kExpandPfS_iiiiiiiiiiiiii, @function
_Z7kExpandPfS_iiiiiiiiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kExpandPfS_iiiiiiiiiiiiii, .-_Z7kExpandPfS_iiiiiiiiiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kExpandPfS_iiiiiiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kExpandPfS_iiiiiiiiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kExpand(float *images, float* targets, int num_images, int num_input_channels, int image_size_y, int image_size_x, int num_modules_y, int num_modules_x, int kernel_size_y, int kernel_size_x, int padding_y, int padding_x, int stride_y, int stride_x, int num_modules_batch, int module_id_offset) {
int color = blockIdx.y;
int src_module_id = module_id_offset + blockIdx.x;
int dst_module_id = blockIdx.x;
int module_id_x = src_module_id % num_modules_x;
int module_id_y = src_module_id / num_modules_x;
int startX = module_id_x * stride_x + padding_x;
int startY = module_id_y * stride_y + padding_y;
int Y, X;
long target_id, source_id;
images += num_images * image_size_x * image_size_y * color;
targets += num_images * (dst_module_id + num_modules_batch * (kernel_size_y * kernel_size_x * color));
for (int y = 0; y < kernel_size_y; y++) {
Y = startY + y;
for (int x = 0; x < kernel_size_x; x++) {
X = startX + x;
target_id = num_images * num_modules_batch * (x + kernel_size_x * y);
source_id = num_images * (X + image_size_x * Y);
if (X < 0 || X >= image_size_x || Y < 0 || Y >= image_size_y) {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = 0;
}
} else {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = images[source_id + im];
}
}
__syncthreads();
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExpand(float *images, float* targets, int num_images, int num_input_channels, int image_size_y, int image_size_x, int num_modules_y, int num_modules_x, int kernel_size_y, int kernel_size_x, int padding_y, int padding_x, int stride_y, int stride_x, int num_modules_batch, int module_id_offset) {
int color = blockIdx.y;
int src_module_id = module_id_offset + blockIdx.x;
int dst_module_id = blockIdx.x;
int module_id_x = src_module_id % num_modules_x;
int module_id_y = src_module_id / num_modules_x;
int startX = module_id_x * stride_x + padding_x;
int startY = module_id_y * stride_y + padding_y;
int Y, X;
long target_id, source_id;
images += num_images * image_size_x * image_size_y * color;
targets += num_images * (dst_module_id + num_modules_batch * (kernel_size_y * kernel_size_x * color));
for (int y = 0; y < kernel_size_y; y++) {
Y = startY + y;
for (int x = 0; x < kernel_size_x; x++) {
X = startX + x;
target_id = num_images * num_modules_batch * (x + kernel_size_x * y);
source_id = num_images * (X + image_size_x * Y);
if (X < 0 || X >= image_size_x || Y < 0 || Y >= image_size_y) {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = 0;
}
} else {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = images[source_id + im];
}
}
__syncthreads();
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExpand(float *images, float* targets, int num_images, int num_input_channels, int image_size_y, int image_size_x, int num_modules_y, int num_modules_x, int kernel_size_y, int kernel_size_x, int padding_y, int padding_x, int stride_y, int stride_x, int num_modules_batch, int module_id_offset) {
int color = blockIdx.y;
int src_module_id = module_id_offset + blockIdx.x;
int dst_module_id = blockIdx.x;
int module_id_x = src_module_id % num_modules_x;
int module_id_y = src_module_id / num_modules_x;
int startX = module_id_x * stride_x + padding_x;
int startY = module_id_y * stride_y + padding_y;
int Y, X;
long target_id, source_id;
images += num_images * image_size_x * image_size_y * color;
targets += num_images * (dst_module_id + num_modules_batch * (kernel_size_y * kernel_size_x * color));
for (int y = 0; y < kernel_size_y; y++) {
Y = startY + y;
for (int x = 0; x < kernel_size_x; x++) {
X = startX + x;
target_id = num_images * num_modules_batch * (x + kernel_size_x * y);
source_id = num_images * (X + image_size_x * Y);
if (X < 0 || X >= image_size_x || Y < 0 || Y >= image_size_y) {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = 0;
}
} else {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = images[source_id + im];
}
}
__syncthreads();
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kExpandPfS_iiiiiiiiiiiiii
.globl _Z7kExpandPfS_iiiiiiiiiiiiii
.p2align 8
.type _Z7kExpandPfS_iiiiiiiiiiiiii,@function
_Z7kExpandPfS_iiiiiiiiiiiiii:
s_load_b64 s[2:3], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s18, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s2, s18
s_xor_b32 s17, s4, s18
s_cmp_lt_i32 s3, 1
v_cvt_f32_u32_e32 v1, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s19, v1
s_cbranch_scc1 .LBB0_17
s_clause 0x4
s_load_b32 s22, s[0:1], 0x44
s_load_b32 s16, s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x2c
s_load_b64 s[12:13], s[0:1], 0x18
s_sub_i32 s23, 0, s17
s_load_b64 s[20:21], s[0:1], 0x3c
s_mul_i32 s23, s23, s19
v_mov_b32_e32 v3, 0
s_mul_hi_u32 s23, s19, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s19, s19, s23
s_waitcnt lgkmcnt(0)
s_add_i32 s22, s14, s22
s_ashr_i32 s24, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s25, s22, s24
s_xor_b32 s23, s25, s24
s_xor_b32 s24, s24, s18
s_mul_hi_u32 s19, s23, s19
s_mul_i32 s25, s15, s3
s_mul_i32 s26, s19, s17
s_mul_i32 s15, s15, s16
s_sub_i32 s18, s23, s26
s_add_i32 s23, s19, 1
s_sub_i32 s26, s18, s17
s_cmp_ge_u32 s18, s17
s_mul_i32 s15, s15, s12
s_cselect_b32 s19, s23, s19
s_cselect_b32 s18, s26, s18
s_add_i32 s23, s19, 1
s_cmp_ge_u32 s18, s17
s_mul_i32 s18, s15, s13
s_cselect_b32 s17, s23, s19
s_ashr_i32 s19, s18, 31
s_xor_b32 s17, s17, s24
s_mul_i32 s25, s25, s4
s_sub_i32 s15, s17, s24
s_lshl_b64 s[18:19], s[18:19], 2
s_mul_i32 s2, s15, s2
s_mul_i32 s7, s15, s7
s_sub_i32 s2, s22, s2
s_mul_i32 s23, s25, s21
s_mul_i32 s15, s2, s20
s_add_i32 s5, s7, s5
s_add_i32 s15, s15, s6
s_add_u32 s17, s8, s18
s_addc_u32 s18, s9, s19
s_add_i32 s2, s23, s14
s_mov_b32 s14, 0
s_mul_i32 s6, s2, s16
v_cmp_gt_i32_e64 s2, s16, v0
s_ashr_i32 s7, s6, 31
s_mul_i32 s20, s21, s16
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s10, s6
s_addc_u32 s11, s11, s7
s_cmp_gt_i32 s4, 0
s_cselect_b32 s19, -1, 0
s_add_u32 s6, s0, 0x48
s_addc_u32 s7, s1, 0
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s3
s_cbranch_scc1 .LBB0_17
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s19
s_cbranch_vccnz .LBB0_2
s_add_i32 s0, s5, s14
s_mul_i32 s1, s14, s4
s_cmp_gt_i32 s0, -1
s_mul_i32 s21, s0, s13
s_cselect_b32 s22, -1, 0
s_cmp_lt_i32 s0, s12
s_mov_b32 s23, 0
s_cselect_b32 s24, -1, 0
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s25
.LBB0_6:
s_add_i32 s23, s23, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s23, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_7:
s_add_i32 s0, s23, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s20, s0
s_add_i32 s0, s15, s23
s_ashr_i32 s9, s8, 31
s_cmp_lt_i32 s0, 0
s_cselect_b32 s25, -1, 0
s_and_b32 vcc_lo, exec_lo, s25
s_cbranch_vccnz .LBB0_13
s_cmp_lt_i32 s0, s13
s_cselect_b32 s25, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s25, s25, s22
s_and_b32 s25, s25, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s25
s_mov_b32 s25, -1
s_cbranch_vccz .LBB0_13
s_and_saveexec_b32 s25, s2
s_cbranch_execz .LBB0_12
s_load_b32 s30, s[6:7], 0xc
s_add_i32 s0, s0, s21
v_mov_b32_e32 v1, v0
s_mul_i32 s26, s0, s16
s_mov_b32 s31, 0
s_ashr_i32 s27, s26, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[26:27], 2
s_add_u32 s26, s17, s26
s_addc_u32 s27, s18, s27
s_lshl_b64 s[28:29], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s28, s10, s28
s_addc_u32 s29, s11, s29
s_waitcnt lgkmcnt(0)
s_and_b32 s30, s30, 0xffff
.p2align 6
.LBB0_11:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s30, v1
v_add_co_u32 v6, vcc_lo, s26, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s27, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s16, v1
v_add_co_u32 v4, s0, s28, v4
global_load_b32 v2, v[6:7], off
v_add_co_ci_u32_e64 v5, s0, s29, v5, s0
s_or_b32 s31, vcc_lo, s31
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s31
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s25
s_mov_b32 s25, 0
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s25
s_cbranch_vccz .LBB0_6
s_and_saveexec_b32 s25, s2
s_cbranch_execz .LBB0_5
s_load_b32 s0, s[6:7], 0xc
s_lshl_b64 s[8:9], s[8:9], 2
v_mov_b32_e32 v1, v0
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s26, s0, 0xffff
.LBB0_16:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s26, v1
v_cmp_le_i32_e32 vcc_lo, s16, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
s_or_b32 s27, vcc_lo, s27
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB0_16
s_branch .LBB0_5
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kExpandPfS_iiiiiiiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kExpandPfS_iiiiiiiiiiiiii, .Lfunc_end0-_Z7kExpandPfS_iiiiiiiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kExpandPfS_iiiiiiiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z7kExpandPfS_iiiiiiiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExpand(float *images, float* targets, int num_images, int num_input_channels, int image_size_y, int image_size_x, int num_modules_y, int num_modules_x, int kernel_size_y, int kernel_size_x, int padding_y, int padding_x, int stride_y, int stride_x, int num_modules_batch, int module_id_offset) {
int color = blockIdx.y;
int src_module_id = module_id_offset + blockIdx.x;
int dst_module_id = blockIdx.x;
int module_id_x = src_module_id % num_modules_x;
int module_id_y = src_module_id / num_modules_x;
int startX = module_id_x * stride_x + padding_x;
int startY = module_id_y * stride_y + padding_y;
int Y, X;
long target_id, source_id;
images += num_images * image_size_x * image_size_y * color;
targets += num_images * (dst_module_id + num_modules_batch * (kernel_size_y * kernel_size_x * color));
for (int y = 0; y < kernel_size_y; y++) {
Y = startY + y;
for (int x = 0; x < kernel_size_x; x++) {
X = startX + x;
target_id = num_images * num_modules_batch * (x + kernel_size_x * y);
source_id = num_images * (X + image_size_x * Y);
if (X < 0 || X >= image_size_x || Y < 0 || Y >= image_size_y) {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = 0;
}
} else {
for (int im = threadIdx.x; im < num_images; im += blockDim.x) {
targets[target_id + im] = images[source_id + im];
}
}
__syncthreads();
}
}
} | .text
.file "kExpand.hip"
.globl _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii # -- Begin function _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.p2align 4, 0x90
.type _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii,@function
_Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii: # @_Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kExpandPfS_iiiiiiiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii, .Lfunc_end0-_Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kExpandPfS_iiiiiiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kExpandPfS_iiiiiiiiiiiiii,@object # @_Z7kExpandPfS_iiiiiiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z7kExpandPfS_iiiiiiiiiiiiii
.p2align 3, 0x0
_Z7kExpandPfS_iiiiiiiiiiiiii:
.quad _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.size _Z7kExpandPfS_iiiiiiiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kExpandPfS_iiiiiiiiiiiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kExpandPfS_iiiiiiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kExpandPfS_iiiiiiiiiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IABS R5, c[0x0][0x184] ; /* 0x0000610000057a13 */
/* 0x000fe20000000000 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e700000209400 */
/*0080*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0090*/ IADD3 R4, R7, c[0x0][0x1a4], RZ ; /* 0x0000690007047a10 */
/* 0x001fc40007ffe0ff */
/*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fe40007ffe0ff */
/*00b0*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fc60000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD R9, R6, R5, RZ ; /* 0x0000000506097224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R0, R5.reuse, R6, R0 ; /* 0x0000000605007224 */
/* 0x040fe400078e0200 */
/*0140*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e260000002600 */
/*0150*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0160*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f45270 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*01a0*/ LOP3.LUT R0, R4, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610004007a12 */
/* 0x000fe200078e3cff */
/*01b0*/ IMAD R2, R6, c[0x0][0x188], RZ ; /* 0x0000620006027a24 */
/* 0x001fc600078e02ff */
/*01c0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f26270 */
/*01d0*/ IMAD R2, R2, c[0x0][0x18c], RZ ; /* 0x0000630002027a24 */
/* 0x000fe200078e02ff */
/*01e0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e260000002100 */
/*01f0*/ IMAD R2, R2, c[0x0][0x1a0], R7 ; /* 0x0000680002027a24 */
/* 0x000fe400078e0207 */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff077624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a24 */
/* 0x000fc400078e02ff */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*0240*/ IMAD R3, R6, c[0x0][0x170], RZ ; /* 0x00005c0006037a24 */
/* 0x000fe200078e02ff */
/*0250*/ SHF.R.S32.HI R8, RZ, 0x1f, R2 ; /* 0x0000001fff087819 */
/* 0x000fe20000011402 */
/*0260*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0270*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff05aa12 */
/* 0x000fe200078e33ff */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff067624 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a05 */
/*02a0*/ IMAD R4, R9, c[0x0][0x184], R4 ; /* 0x0000610009047a24 */
/* 0x000fe400078e0204 */
/*02b0*/ IMAD R9, R3, c[0x0][0x178], RZ ; /* 0x00005e0003097a24 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD R3, R5, R6, c[0x0][0x190] ; /* 0x0000640005037624 */
/* 0x000fe400078e0206 */
/*02d0*/ IMAD R4, R4, R7, c[0x0][0x194] ; /* 0x0000650004047624 */
/* 0x000fe400078e0207 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD R9, R9, c[0x0][0x17c], RZ ; /* 0x00005f0009097a24 */
/* 0x001fc400078e02ff */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fca00078e00ff */
/*0310*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0320*/ @!P0 BRA 0x6f0 ; /* 0x000003c000008947 */
/* 0x001fea0003800000 */
/*0330*/ IMAD.IADD R7, R3, 0x1, R6 ; /* 0x0000000103077824 */
/* 0x000fe400078e0206 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.IADD R12, R4, 0x1, R5 ; /* 0x00000001040c7824 */
/* 0x001fe200078e0205 */
/*0360*/ ULDC UR4, c[0x0][0x1a0] ; /* 0x0000680000047ab9 */
/* 0x000fe20000000800 */
/*0370*/ BSSY B0, 0x6d0 ; /* 0x0000035000007945 */
/* 0x000fe20003800000 */
/*0380*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*0390*/ LOP3.LUT R10, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c0a7212 */
/* 0x000fe200078efcff */
/*03a0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*03b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f06270 */
/*03c0*/ IMAD R10, R6, c[0x0][0x18c], R5 ; /* 0x00006300060a7a24 */
/* 0x000fe200078e0205 */
/*03d0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x17c], !P0 ; /* 0x00005f000c007a0c */
/* 0x000fe20004706670 */
/*03f0*/ IMAD R11, R10, UR4, RZ ; /* 0x000000040a0b7c24 */
/* 0x000fe2000f8e02ff */
/*0400*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x18c], PT ; /* 0x0000630005007a0c */
/* 0x000fe40003f26270 */
/*0410*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fe40000706670 */
/*0420*/ SHF.R.S32.HI R13, RZ, 0x1f, R11 ; /* 0x0000001fff0d7819 */
/* 0x000fd6000001140b */
/*0430*/ @P0 BRA 0x5f0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0450*/ BSSY B1, 0x5e0 ; /* 0x0000018000017945 */
/* 0x000fd80003800000 */
/*0460*/ @P0 BRA 0x5d0 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD R10, R7, c[0x0][0x17c], R12 ; /* 0x00005f00070a7a24 */
/* 0x000fe200078e020c */
/*0480*/ IADD3 R19, P2, R2, R11, RZ ; /* 0x0000000b02137210 */
/* 0x000fe20007f5e0ff */
/*0490*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0000 */
/*04a0*/ IMAD R10, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0a7a24 */
/* 0x000fe400078e02ff */
/*04b0*/ IMAD.X R21, R8, 0x1, R13, P2 ; /* 0x0000000108157824 */
/* 0x000fc600010e060d */
/*04c0*/ IADD3 R15, P0, R9, R10, RZ ; /* 0x0000000a090f7210 */
/* 0x000fe40007f1e0ff */
/*04d0*/ SHF.R.S32.HI R10, RZ, 0x1f, R10 ; /* 0x0000001fff0a7819 */
/* 0x000fc8000001140a */
/*04e0*/ LEA.HI.X.SX32 R17, R9, R10, 0x1, P0 ; /* 0x0000000a09117211 */
/* 0x000fe400000f0eff */
/*04f0*/ SHF.R.S32.HI R12, RZ, 0x1f, R14 ; /* 0x0000001fff0c7819 */
/* 0x001fe4000001140e */
/*0500*/ IADD3 R11, P0, R14, R15, RZ ; /* 0x0000000f0e0b7210 */
/* 0x000fca0007f1e0ff */
/*0510*/ IMAD.X R16, R12, 0x1, R17, P0 ; /* 0x000000010c107824 */
/* 0x000fe200000e0611 */
/*0520*/ LEA R10, P0, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b0a7a11 */
/* 0x000fc800078010ff */
/*0530*/ LEA.HI.X R11, R11, c[0x0][0x164], R16, 0x2, P0 ; /* 0x000059000b0b7a11 */
/* 0x000fcc00000f1410 */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R13, P0, R14.reuse, R19, RZ ; /* 0x000000130e0d7210 */
/* 0x040fe40007f1e0ff */
/*0560*/ IADD3 R14, R14, c[0x0][0x0], RZ ; /* 0x000000000e0e7a10 */
/* 0x000fc60007ffe0ff */
/*0570*/ IMAD.X R16, R12, 0x1, R21, P0 ; /* 0x000000010c107824 */
/* 0x000fe200000e0615 */
/*0580*/ LEA R12, P0, R13, c[0x0][0x168], 0x2 ; /* 0x00005a000d0c7a11 */
/* 0x000fc800078010ff */
/*0590*/ LEA.HI.X R13, R13, c[0x0][0x16c], R16, 0x2, P0 ; /* 0x00005b000d0d7a11 */
/* 0x000fe400000f1410 */
/*05a0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x170], PT ; /* 0x00005c000e007a0c */
/* 0x000fc60003f06270 */
/*05b0*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0041f4000c101906 */
/*05c0*/ @!P0 BRA 0x4f0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x6c0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x6c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R15, P0, R2, R11, RZ ; /* 0x0000000b020f7210 */
/* 0x000fe20007f1e0ff */
/*0620*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0000 */
/*0630*/ IMAD.X R13, R8, 0x1, R13, P0 ; /* 0x00000001080d7824 */
/* 0x000fe400000e060d */
/*0640*/ IADD3 R11, P0, R12, R15, RZ ; /* 0x0000000f0c0b7210 */
/* 0x000fc80007f1e0ff */
/*0650*/ LEA.HI.X.SX32 R14, R12.reuse, R13, 0x1, P0 ; /* 0x0000000d0c0e7211 */
/* 0x040fe400000f0eff */
/*0660*/ LEA R10, P0, R11.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a000b0a7a11 */
/* 0x040fe400078010ff */
/*0670*/ IADD3 R12, R12, c[0x0][0x0], RZ ; /* 0x000000000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0680*/ LEA.HI.X R11, R11, c[0x0][0x16c], R14, 0x2, P0 ; /* 0x00005b000b0b7a11 */
/* 0x000fe400000f140e */
/*0690*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fc60003f06270 */
/*06a0*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0001f4000c101906 */
/*06b0*/ @!P0 BRA 0x640 ; /* 0xffffff8000008947 */
/* 0x001fea000383ffff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06e0*/ @!P1 BRA 0x350 ; /* 0xfffffc6000009947 */
/* 0x000fea000383ffff */
/*06f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*0700*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x188], PT ; /* 0x0000620006007a0c */
/* 0x000fda0003f06270 */
/*0710*/ @!P0 BRA 0x300 ; /* 0xfffffbe000008947 */
/* 0x000fea000383ffff */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kExpandPfS_iiiiiiiiiiiiii
.globl _Z7kExpandPfS_iiiiiiiiiiiiii
.p2align 8
.type _Z7kExpandPfS_iiiiiiiiiiiiii,@function
_Z7kExpandPfS_iiiiiiiiiiiiii:
s_load_b64 s[2:3], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s18, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s2, s18
s_xor_b32 s17, s4, s18
s_cmp_lt_i32 s3, 1
v_cvt_f32_u32_e32 v1, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s19, v1
s_cbranch_scc1 .LBB0_17
s_clause 0x4
s_load_b32 s22, s[0:1], 0x44
s_load_b32 s16, s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x2c
s_load_b64 s[12:13], s[0:1], 0x18
s_sub_i32 s23, 0, s17
s_load_b64 s[20:21], s[0:1], 0x3c
s_mul_i32 s23, s23, s19
v_mov_b32_e32 v3, 0
s_mul_hi_u32 s23, s19, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s19, s19, s23
s_waitcnt lgkmcnt(0)
s_add_i32 s22, s14, s22
s_ashr_i32 s24, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s25, s22, s24
s_xor_b32 s23, s25, s24
s_xor_b32 s24, s24, s18
s_mul_hi_u32 s19, s23, s19
s_mul_i32 s25, s15, s3
s_mul_i32 s26, s19, s17
s_mul_i32 s15, s15, s16
s_sub_i32 s18, s23, s26
s_add_i32 s23, s19, 1
s_sub_i32 s26, s18, s17
s_cmp_ge_u32 s18, s17
s_mul_i32 s15, s15, s12
s_cselect_b32 s19, s23, s19
s_cselect_b32 s18, s26, s18
s_add_i32 s23, s19, 1
s_cmp_ge_u32 s18, s17
s_mul_i32 s18, s15, s13
s_cselect_b32 s17, s23, s19
s_ashr_i32 s19, s18, 31
s_xor_b32 s17, s17, s24
s_mul_i32 s25, s25, s4
s_sub_i32 s15, s17, s24
s_lshl_b64 s[18:19], s[18:19], 2
s_mul_i32 s2, s15, s2
s_mul_i32 s7, s15, s7
s_sub_i32 s2, s22, s2
s_mul_i32 s23, s25, s21
s_mul_i32 s15, s2, s20
s_add_i32 s5, s7, s5
s_add_i32 s15, s15, s6
s_add_u32 s17, s8, s18
s_addc_u32 s18, s9, s19
s_add_i32 s2, s23, s14
s_mov_b32 s14, 0
s_mul_i32 s6, s2, s16
v_cmp_gt_i32_e64 s2, s16, v0
s_ashr_i32 s7, s6, 31
s_mul_i32 s20, s21, s16
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s10, s6
s_addc_u32 s11, s11, s7
s_cmp_gt_i32 s4, 0
s_cselect_b32 s19, -1, 0
s_add_u32 s6, s0, 0x48
s_addc_u32 s7, s1, 0
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s3
s_cbranch_scc1 .LBB0_17
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s19
s_cbranch_vccnz .LBB0_2
s_add_i32 s0, s5, s14
s_mul_i32 s1, s14, s4
s_cmp_gt_i32 s0, -1
s_mul_i32 s21, s0, s13
s_cselect_b32 s22, -1, 0
s_cmp_lt_i32 s0, s12
s_mov_b32 s23, 0
s_cselect_b32 s24, -1, 0
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s25
.LBB0_6:
s_add_i32 s23, s23, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s23, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_7:
s_add_i32 s0, s23, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s20, s0
s_add_i32 s0, s15, s23
s_ashr_i32 s9, s8, 31
s_cmp_lt_i32 s0, 0
s_cselect_b32 s25, -1, 0
s_and_b32 vcc_lo, exec_lo, s25
s_cbranch_vccnz .LBB0_13
s_cmp_lt_i32 s0, s13
s_cselect_b32 s25, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s25, s25, s22
s_and_b32 s25, s25, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s25
s_mov_b32 s25, -1
s_cbranch_vccz .LBB0_13
s_and_saveexec_b32 s25, s2
s_cbranch_execz .LBB0_12
s_load_b32 s30, s[6:7], 0xc
s_add_i32 s0, s0, s21
v_mov_b32_e32 v1, v0
s_mul_i32 s26, s0, s16
s_mov_b32 s31, 0
s_ashr_i32 s27, s26, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[26:27], 2
s_add_u32 s26, s17, s26
s_addc_u32 s27, s18, s27
s_lshl_b64 s[28:29], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s28, s10, s28
s_addc_u32 s29, s11, s29
s_waitcnt lgkmcnt(0)
s_and_b32 s30, s30, 0xffff
.p2align 6
.LBB0_11:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s30, v1
v_add_co_u32 v6, vcc_lo, s26, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s27, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s16, v1
v_add_co_u32 v4, s0, s28, v4
global_load_b32 v2, v[6:7], off
v_add_co_ci_u32_e64 v5, s0, s29, v5, s0
s_or_b32 s31, vcc_lo, s31
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s31
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s25
s_mov_b32 s25, 0
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s25
s_cbranch_vccz .LBB0_6
s_and_saveexec_b32 s25, s2
s_cbranch_execz .LBB0_5
s_load_b32 s0, s[6:7], 0xc
s_lshl_b64 s[8:9], s[8:9], 2
v_mov_b32_e32 v1, v0
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s26, s0, 0xffff
.LBB0_16:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s26, v1
v_cmp_le_i32_e32 vcc_lo, s16, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
s_or_b32 s27, vcc_lo, s27
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB0_16
s_branch .LBB0_5
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kExpandPfS_iiiiiiiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kExpandPfS_iiiiiiiiiiiiii, .Lfunc_end0-_Z7kExpandPfS_iiiiiiiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kExpandPfS_iiiiiiiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z7kExpandPfS_iiiiiiiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000375ac_00000000-6_kExpand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii
.type _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii, @function
_Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 264
pushq 40(%rsp)
.cfi_def_cfa_offset 272
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kExpandPfS_iiiiiiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii, .-_Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii
.globl _Z7kExpandPfS_iiiiiiiiiiiiii
.type _Z7kExpandPfS_iiiiiiiiiiiiii, @function
_Z7kExpandPfS_iiiiiiiiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z42__device_stub__Z7kExpandPfS_iiiiiiiiiiiiiiPfS_iiiiiiiiiiiiii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kExpandPfS_iiiiiiiiiiiiii, .-_Z7kExpandPfS_iiiiiiiiiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kExpandPfS_iiiiiiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kExpandPfS_iiiiiiiiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kExpand.hip"
.globl _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii # -- Begin function _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.p2align 4, 0x90
.type _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii,@function
_Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii: # @_Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kExpandPfS_iiiiiiiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii, .Lfunc_end0-_Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kExpandPfS_iiiiiiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kExpandPfS_iiiiiiiiiiiiii,@object # @_Z7kExpandPfS_iiiiiiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z7kExpandPfS_iiiiiiiiiiiiii
.p2align 3, 0x0
_Z7kExpandPfS_iiiiiiiiiiiiii:
.quad _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.size _Z7kExpandPfS_iiiiiiiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kExpandPfS_iiiiiiiiiiiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kExpandPfS_iiiiiiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kExpandPfS_iiiiiiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Time-stamp: <2013-12-04 13:20:59 hamada>
#include <iostream>
#include <string.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
//#define NUM (1024*1024*1024/4) // 1GB
//#define NUM ((1024*1024/4)*(1024 + 512)) // 1.5GB
//#define NUM ((1024*1024/4)*(1024*2) -1) // 2GB-1
//#define NUM ((1024*1024/4)*(1024*2) ) // 2GB
//#define NUM ((1024*1024/4)) // 1MB
#define NUM ((1024*1024/4)*(1024*6-100) ) // 6GB-100MB
using namespace std;
__global__ void kernel(int* x, int n)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int wid = blockDim.x*bid + tid;
if(wid > 1) return;
int z = 0;
for(size_t i = 0; i<n ; i++) z += x[i];
x[0] = z;
}
#include <sys/time.h>
#include <sys/resource.h>
extern "C" double get_time(void)
{
static struct timeval tv;
static struct timezone tz;
gettimeofday(&tv, &tz);
return ((double)(tv.tv_sec + tv.tv_usec*1.0e-6));
}
void myCudaMalloc(void** val, size_t mem_size)
{
double t = get_time();
cudaError_t err = cudaMalloc(val, mem_size);
assert(cudaSuccess == err);
cout << "cudaMalloc: " << get_time() - t << endl;
}
void myCudaMemcpy(void* dst, const void* src, size_t size, enum cudaMemcpyKind kind)
{
double t = get_time();
cudaError_t err = cudaMemcpy(dst, src, size, kind);
assert(cudaSuccess == err);
cout << "cudaMemcpy: " << get_time() - t << endl;
}
int main( int argc, char** argv)
{
int nb = 512; // max 65535
int nthre = 128; // max 512
size_t nword = NUM;
size_t mem_size = sizeof(int) * nword;
printf("# nword: %zd \n", nword);
printf("# threads: %d \n", nb*nthre);
printf("mem_size: %zd Kbyte\n", mem_size >> 10);
double t=0.;
cudaError_t err;
int* hval = (int*) malloc(mem_size);
int* hval2 = (int*) malloc(mem_size);
int* dval = NULL;
cout << "mem_size: " <<mem_size << endl;
cout << "(size_t)mem_size:" <<(size_t)mem_size << endl;
cout << sizeof(size_t) << endl;
myCudaMalloc((void**)&dval, mem_size);
int z = 0;
for(size_t i=0; i<nword; i++){hval[i] = 1; z += hval[i];}
myCudaMemcpy(dval, hval, mem_size, cudaMemcpyHostToDevice);
t = get_time();
kernel<<< nb, nthre >>>(dval, nword);
err = cudaThreadSynchronize();
assert(cudaSuccess == err);
cout << "GPU calc: " << get_time() - t << endl;
myCudaMemcpy(hval, dval, mem_size, cudaMemcpyDeviceToHost);
printf("GPU: %d\n", hval[0]);
printf("HOS: %d\n", z);
free(hval);
cudaFree(dval);
return (0);
} | code for sm_80
Function : _Z6kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd600078e00ff */
/*0090*/ @!P0 BRA 0x440 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00d0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fc80000011403 */
/*0100*/ ISETP.GT.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80003f04100 */
/*0110*/ SEL R3, R3, 0x1, P0 ; /* 0x0000000103037807 */
/* 0x000fe40000000000 */
/*0120*/ SEL R0, R0, RZ, P0 ; /* 0x000000ff00007207 */
/* 0x000fe40000000000 */
/*0130*/ IADD3 R2, P2, R3.reuse, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x040fe40007f5e0ff */
/*0140*/ LOP3.LUT R12, R3, 0x3, RZ, 0xc0, !PT ; /* 0x00000003030c7812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0160*/ IADD3.X R2, R0, -0x1, RZ, P2, !PT ; /* 0xffffffff00027810 */
/* 0x000fc400017fe4ff */
/*0170*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05070 */
/*0180*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fe40003f26110 */
/*0190*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*01a0*/ @!P1 BRA 0x330 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R10, P1, R12, -R3, RZ ; /* 0x800000030c0a7210 */
/* 0x000fe20007f3e0ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*01f0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.X R11, RZ, RZ, ~R0, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e0e00 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0009 */
/*0240*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040802047981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080802077981 */
/* 0x000ee8000c1e1900 */
/*0270*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0802067981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0290*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02a0*/ IADD3 R8, P2, R10, UR4, RZ ; /* 0x000000040a087c10 */
/* 0x000fc8000ff5e0ff */
/*02b0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25070 */
/*02c0*/ IADD3.X R8, R11, UR5, RZ, P2, !PT ; /* 0x000000050b087c10 */
/* 0x000fc800097fe4ff */
/*02d0*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40003f25310 */
/*02e0*/ IADD3 R8, P2, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fca0007f5e0ff */
/*02f0*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0603 */
/*0300*/ IADD3 R0, R4, R0, R5 ; /* 0x0000000004007210 */
/* 0x004fc80007ffe005 */
/*0310*/ IADD3 R5, R6, R7, R0 ; /* 0x0000000706057210 */
/* 0x008fe20007ffe000 */
/*0320*/ @P1 BRA 0x220 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*0330*/ @!P0 BRA 0x440 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, P0, RZ, -R12, RZ ; /* 0x8000000cff007210 */
/* 0x000fe20007f1e0ff */
/*0350*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0360*/ ULEA UR6, UP0, UR4, UR6, 0x2 ; /* 0x0000000604067291 */
/* 0x000fe4000f80103f */
/*0370*/ IMAD.X R4, RZ, RZ, -0x1, P0 ; /* 0xffffffffff047424 */
/* 0x000fe400000e06ff */
/*0380*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x2, UP0 ; /* 0x0000000704047291 */
/* 0x000fc800080f1405 */
/*0390*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe4000f8e00ff */
/*03a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*03b0*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fc8000ff1e03f */
/*03e0*/ IMAD.X R4, RZ, RZ, R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0604 */
/*03f0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0400*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fc600087fe43f */
/*0410*/ ISETP.NE.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe20003f05300 */
/*0420*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x004fd800078e0205 */
/*0430*/ @P0 BRA 0x390 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0440*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0460*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Time-stamp: <2013-12-04 13:20:59 hamada>
#include <iostream>
#include <string.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
//#define NUM (1024*1024*1024/4) // 1GB
//#define NUM ((1024*1024/4)*(1024 + 512)) // 1.5GB
//#define NUM ((1024*1024/4)*(1024*2) -1) // 2GB-1
//#define NUM ((1024*1024/4)*(1024*2) ) // 2GB
//#define NUM ((1024*1024/4)) // 1MB
#define NUM ((1024*1024/4)*(1024*6-100) ) // 6GB-100MB
using namespace std;
__global__ void kernel(int* x, int n)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int wid = blockDim.x*bid + tid;
if(wid > 1) return;
int z = 0;
for(size_t i = 0; i<n ; i++) z += x[i];
x[0] = z;
}
#include <sys/time.h>
#include <sys/resource.h>
extern "C" double get_time(void)
{
static struct timeval tv;
static struct timezone tz;
gettimeofday(&tv, &tz);
return ((double)(tv.tv_sec + tv.tv_usec*1.0e-6));
}
void myCudaMalloc(void** val, size_t mem_size)
{
double t = get_time();
cudaError_t err = cudaMalloc(val, mem_size);
assert(cudaSuccess == err);
cout << "cudaMalloc: " << get_time() - t << endl;
}
void myCudaMemcpy(void* dst, const void* src, size_t size, enum cudaMemcpyKind kind)
{
double t = get_time();
cudaError_t err = cudaMemcpy(dst, src, size, kind);
assert(cudaSuccess == err);
cout << "cudaMemcpy: " << get_time() - t << endl;
}
int main( int argc, char** argv)
{
int nb = 512; // max 65535
int nthre = 128; // max 512
size_t nword = NUM;
size_t mem_size = sizeof(int) * nword;
printf("# nword: %zd \n", nword);
printf("# threads: %d \n", nb*nthre);
printf("mem_size: %zd Kbyte\n", mem_size >> 10);
double t=0.;
cudaError_t err;
int* hval = (int*) malloc(mem_size);
int* hval2 = (int*) malloc(mem_size);
int* dval = NULL;
cout << "mem_size: " <<mem_size << endl;
cout << "(size_t)mem_size:" <<(size_t)mem_size << endl;
cout << sizeof(size_t) << endl;
myCudaMalloc((void**)&dval, mem_size);
int z = 0;
for(size_t i=0; i<nword; i++){hval[i] = 1; z += hval[i];}
myCudaMemcpy(dval, hval, mem_size, cudaMemcpyHostToDevice);
t = get_time();
kernel<<< nb, nthre >>>(dval, nword);
err = cudaThreadSynchronize();
assert(cudaSuccess == err);
cout << "GPU calc: " << get_time() - t << endl;
myCudaMemcpy(hval, dval, mem_size, cudaMemcpyDeviceToHost);
printf("GPU: %d\n", hval[0]);
printf("HOS: %d\n", z);
free(hval);
cudaFree(dval);
return (0);
} | .file "tmpxft_00059fd7_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl get_time
.type get_time, @function
get_time:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZZ8get_timeE2tz(%rip), %rsi
leaq _ZZ8get_timeE2tv(%rip), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8+_ZZ8get_timeE2tv(%rip), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size get_time, .-get_time
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc: "
.text
.globl _Z12myCudaMallocPPvm
.type _Z12myCudaMallocPPvm, @function
_Z12myCudaMallocPPvm:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %rbp
call get_time
movsd %xmm0, 8(%rsp)
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
movl $12, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call get_time
subsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L10
cmpb $0, 56(%rbp)
je .L7
movzbl 67(%rbp), %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.cfi_endproc
.LFE3670:
.size _Z12myCudaMallocPPvm, .-_Z12myCudaMallocPPvm
.section .rodata.str1.1
.LC2:
.string "cudaMemcpy: "
.text
.globl _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
.type _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind, @function
_Z12myCudaMemcpyPvPKvm14cudaMemcpyKind:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
call get_time
movsd %xmm0, 8(%rsp)
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $12, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call get_time
subsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L16
cmpb $0, 56(%rbp)
je .L13
movzbl 67(%rbp), %esi
.L14:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L13:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L14
.cfi_endproc
.LFE3671:
.size _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind, .-_Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl _Z6kernelPii
.type _Z6kernelPii, @function
_Z6kernelPii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6kernelPii, .-_Z6kernelPii
.section .rodata.str1.1
.LC3:
.string "# nword: %zd \n"
.LC4:
.string "# threads: %d \n"
.LC5:
.string "mem_size: %zd Kbyte\n"
.LC6:
.string "mem_size: "
.LC7:
.string "(size_t)mem_size:"
.LC8:
.string "GPU calc: "
.LC9:
.string "GPU: %d\n"
.LC10:
.string "HOS: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1584398336, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $65536, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $6189056, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movabsq $6337593344, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq $0, 24(%rsp)
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %esi
movq %r12, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call _Z12myCudaMallocPPvm
movq %rbp, %rax
leaq 0(%rbp,%rbx), %rdx
.L26:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
movl $1, %ecx
movabsq $6337593344, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
call get_time
movsd %xmm0, 8(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
call cudaThreadSynchronize@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call get_time
subsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movabsq $6337593344, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
movl 0(%rbp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1584398336, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl $1584398336, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6kernelPiiPii
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ8get_timeE2tz
.comm _ZZ8get_timeE2tz,8,8
.local _ZZ8get_timeE2tv
.comm _ZZ8get_timeE2tv,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Time-stamp: <2013-12-04 13:20:59 hamada>
#include <iostream>
#include <string.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
//#define NUM (1024*1024*1024/4) // 1GB
//#define NUM ((1024*1024/4)*(1024 + 512)) // 1.5GB
//#define NUM ((1024*1024/4)*(1024*2) -1) // 2GB-1
//#define NUM ((1024*1024/4)*(1024*2) ) // 2GB
//#define NUM ((1024*1024/4)) // 1MB
#define NUM ((1024*1024/4)*(1024*6-100) ) // 6GB-100MB
using namespace std;
__global__ void kernel(int* x, int n)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int wid = blockDim.x*bid + tid;
if(wid > 1) return;
int z = 0;
for(size_t i = 0; i<n ; i++) z += x[i];
x[0] = z;
}
#include <sys/time.h>
#include <sys/resource.h>
extern "C" double get_time(void)
{
static struct timeval tv;
static struct timezone tz;
gettimeofday(&tv, &tz);
return ((double)(tv.tv_sec + tv.tv_usec*1.0e-6));
}
void myCudaMalloc(void** val, size_t mem_size)
{
double t = get_time();
cudaError_t err = cudaMalloc(val, mem_size);
assert(cudaSuccess == err);
cout << "cudaMalloc: " << get_time() - t << endl;
}
void myCudaMemcpy(void* dst, const void* src, size_t size, enum cudaMemcpyKind kind)
{
double t = get_time();
cudaError_t err = cudaMemcpy(dst, src, size, kind);
assert(cudaSuccess == err);
cout << "cudaMemcpy: " << get_time() - t << endl;
}
int main( int argc, char** argv)
{
int nb = 512; // max 65535
int nthre = 128; // max 512
size_t nword = NUM;
size_t mem_size = sizeof(int) * nword;
printf("# nword: %zd \n", nword);
printf("# threads: %d \n", nb*nthre);
printf("mem_size: %zd Kbyte\n", mem_size >> 10);
double t=0.;
cudaError_t err;
int* hval = (int*) malloc(mem_size);
int* hval2 = (int*) malloc(mem_size);
int* dval = NULL;
cout << "mem_size: " <<mem_size << endl;
cout << "(size_t)mem_size:" <<(size_t)mem_size << endl;
cout << sizeof(size_t) << endl;
myCudaMalloc((void**)&dval, mem_size);
int z = 0;
for(size_t i=0; i<nword; i++){hval[i] = 1; z += hval[i];}
myCudaMemcpy(dval, hval, mem_size, cudaMemcpyHostToDevice);
t = get_time();
kernel<<< nb, nthre >>>(dval, nword);
err = cudaThreadSynchronize();
assert(cudaSuccess == err);
cout << "GPU calc: " << get_time() - t << endl;
myCudaMemcpy(hval, dval, mem_size, cudaMemcpyDeviceToHost);
printf("GPU: %d\n", hval[0]);
printf("HOS: %d\n", z);
free(hval);
cudaFree(dval);
return (0);
} | //Time-stamp: <2013-12-04 13:20:59 hamada>
#include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
//#define NUM (1024*1024*1024/4) // 1GB
//#define NUM ((1024*1024/4)*(1024 + 512)) // 1.5GB
//#define NUM ((1024*1024/4)*(1024*2) -1) // 2GB-1
//#define NUM ((1024*1024/4)*(1024*2) ) // 2GB
//#define NUM ((1024*1024/4)) // 1MB
#define NUM ((1024*1024/4)*(1024*6-100) ) // 6GB-100MB
using namespace std;
__global__ void kernel(int* x, int n)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int wid = blockDim.x*bid + tid;
if(wid > 1) return;
int z = 0;
for(size_t i = 0; i<n ; i++) z += x[i];
x[0] = z;
}
#include <sys/time.h>
#include <sys/resource.h>
extern "C" double get_time(void)
{
static struct timeval tv;
static struct timezone tz;
gettimeofday(&tv, &tz);
return ((double)(tv.tv_sec + tv.tv_usec*1.0e-6));
}
void myCudaMalloc(void** val, size_t mem_size)
{
double t = get_time();
hipError_t err = hipMalloc(val, mem_size);
assert(hipSuccess == err);
cout << "cudaMalloc: " << get_time() - t << endl;
}
void myCudaMemcpy(void* dst, const void* src, size_t size, enum hipMemcpyKind kind)
{
double t = get_time();
hipError_t err = hipMemcpy(dst, src, size, kind);
assert(hipSuccess == err);
cout << "cudaMemcpy: " << get_time() - t << endl;
}
int main( int argc, char** argv)
{
int nb = 512; // max 65535
int nthre = 128; // max 512
size_t nword = NUM;
size_t mem_size = sizeof(int) * nword;
printf("# nword: %zd \n", nword);
printf("# threads: %d \n", nb*nthre);
printf("mem_size: %zd Kbyte\n", mem_size >> 10);
double t=0.;
hipError_t err;
int* hval = (int*) malloc(mem_size);
int* hval2 = (int*) malloc(mem_size);
int* dval = NULL;
cout << "mem_size: " <<mem_size << endl;
cout << "(size_t)mem_size:" <<(size_t)mem_size << endl;
cout << sizeof(size_t) << endl;
myCudaMalloc((void**)&dval, mem_size);
int z = 0;
for(size_t i=0; i<nword; i++){hval[i] = 1; z += hval[i];}
myCudaMemcpy(dval, hval, mem_size, hipMemcpyHostToDevice);
t = get_time();
kernel<<< nb, nthre >>>(dval, nword);
err = hipDeviceSynchronize();
assert(hipSuccess == err);
cout << "GPU calc: " << get_time() - t << endl;
myCudaMemcpy(hval, dval, mem_size, hipMemcpyDeviceToHost);
printf("GPU: %d\n", hval[0]);
printf("HOS: %d\n", z);
free(hval);
hipFree(dval);
return (0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Time-stamp: <2013-12-04 13:20:59 hamada>
#include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
//#define NUM (1024*1024*1024/4) // 1GB
//#define NUM ((1024*1024/4)*(1024 + 512)) // 1.5GB
//#define NUM ((1024*1024/4)*(1024*2) -1) // 2GB-1
//#define NUM ((1024*1024/4)*(1024*2) ) // 2GB
//#define NUM ((1024*1024/4)) // 1MB
#define NUM ((1024*1024/4)*(1024*6-100) ) // 6GB-100MB
using namespace std;
__global__ void kernel(int* x, int n)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int wid = blockDim.x*bid + tid;
if(wid > 1) return;
int z = 0;
for(size_t i = 0; i<n ; i++) z += x[i];
x[0] = z;
}
#include <sys/time.h>
#include <sys/resource.h>
extern "C" double get_time(void)
{
static struct timeval tv;
static struct timezone tz;
gettimeofday(&tv, &tz);
return ((double)(tv.tv_sec + tv.tv_usec*1.0e-6));
}
void myCudaMalloc(void** val, size_t mem_size)
{
double t = get_time();
hipError_t err = hipMalloc(val, mem_size);
assert(hipSuccess == err);
cout << "cudaMalloc: " << get_time() - t << endl;
}
void myCudaMemcpy(void* dst, const void* src, size_t size, enum hipMemcpyKind kind)
{
double t = get_time();
hipError_t err = hipMemcpy(dst, src, size, kind);
assert(hipSuccess == err);
cout << "cudaMemcpy: " << get_time() - t << endl;
}
int main( int argc, char** argv)
{
int nb = 512; // max 65535
int nthre = 128; // max 512
size_t nword = NUM;
size_t mem_size = sizeof(int) * nword;
printf("# nword: %zd \n", nword);
printf("# threads: %d \n", nb*nthre);
printf("mem_size: %zd Kbyte\n", mem_size >> 10);
double t=0.;
hipError_t err;
int* hval = (int*) malloc(mem_size);
int* hval2 = (int*) malloc(mem_size);
int* dval = NULL;
cout << "mem_size: " <<mem_size << endl;
cout << "(size_t)mem_size:" <<(size_t)mem_size << endl;
cout << sizeof(size_t) << endl;
myCudaMalloc((void**)&dval, mem_size);
int z = 0;
for(size_t i=0; i<nword; i++){hval[i] = 1; z += hval[i];}
myCudaMemcpy(dval, hval, mem_size, hipMemcpyHostToDevice);
t = get_time();
kernel<<< nb, nthre >>>(dval, nword);
err = hipDeviceSynchronize();
assert(hipSuccess == err);
cout << "GPU calc: " << get_time() - t << endl;
myCudaMemcpy(hval, dval, mem_size, hipMemcpyDeviceToHost);
printf("GPU: %d\n", hval[0]);
printf("HOS: %d\n", z);
free(hval);
hipFree(dval);
return (0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPii
.globl _Z6kernelPii
.p2align 8
.type _Z6kernelPii,@function
_Z6kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 2, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_mov_b64 s[4:5], s[0:1]
.LBB0_3:
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s7, s6
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6
global_store_b32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPii, .Lfunc_end0-_Z6kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Time-stamp: <2013-12-04 13:20:59 hamada>
#include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
//#define NUM (1024*1024*1024/4) // 1GB
//#define NUM ((1024*1024/4)*(1024 + 512)) // 1.5GB
//#define NUM ((1024*1024/4)*(1024*2) -1) // 2GB-1
//#define NUM ((1024*1024/4)*(1024*2) ) // 2GB
//#define NUM ((1024*1024/4)) // 1MB
#define NUM ((1024*1024/4)*(1024*6-100) ) // 6GB-100MB
using namespace std;
__global__ void kernel(int* x, int n)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int wid = blockDim.x*bid + tid;
if(wid > 1) return;
int z = 0;
for(size_t i = 0; i<n ; i++) z += x[i];
x[0] = z;
}
#include <sys/time.h>
#include <sys/resource.h>
extern "C" double get_time(void)
{
static struct timeval tv;
static struct timezone tz;
gettimeofday(&tv, &tz);
return ((double)(tv.tv_sec + tv.tv_usec*1.0e-6));
}
void myCudaMalloc(void** val, size_t mem_size)
{
double t = get_time();
hipError_t err = hipMalloc(val, mem_size);
assert(hipSuccess == err);
cout << "cudaMalloc: " << get_time() - t << endl;
}
void myCudaMemcpy(void* dst, const void* src, size_t size, enum hipMemcpyKind kind)
{
double t = get_time();
hipError_t err = hipMemcpy(dst, src, size, kind);
assert(hipSuccess == err);
cout << "cudaMemcpy: " << get_time() - t << endl;
}
int main( int argc, char** argv)
{
int nb = 512; // max 65535
int nthre = 128; // max 512
size_t nword = NUM;
size_t mem_size = sizeof(int) * nword;
printf("# nword: %zd \n", nword);
printf("# threads: %d \n", nb*nthre);
printf("mem_size: %zd Kbyte\n", mem_size >> 10);
double t=0.;
hipError_t err;
int* hval = (int*) malloc(mem_size);
int* hval2 = (int*) malloc(mem_size);
int* dval = NULL;
cout << "mem_size: " <<mem_size << endl;
cout << "(size_t)mem_size:" <<(size_t)mem_size << endl;
cout << sizeof(size_t) << endl;
myCudaMalloc((void**)&dval, mem_size);
int z = 0;
for(size_t i=0; i<nword; i++){hval[i] = 1; z += hval[i];}
myCudaMemcpy(dval, hval, mem_size, hipMemcpyHostToDevice);
t = get_time();
kernel<<< nb, nthre >>>(dval, nword);
err = hipDeviceSynchronize();
assert(hipSuccess == err);
cout << "GPU calc: " << get_time() - t << endl;
myCudaMemcpy(hval, dval, mem_size, hipMemcpyDeviceToHost);
printf("GPU: %d\n", hval[0]);
printf("HOS: %d\n", z);
free(hval);
hipFree(dval);
return (0);
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPii # -- Begin function _Z21__device_stub__kernelPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPii,@function
_Z21__device_stub__kernelPii: # @_Z21__device_stub__kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPii, .Lfunc_end0-_Z21__device_stub__kernelPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function get_time
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl get_time
.p2align 4, 0x90
.type get_time,@function
get_time: # @get_time
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size get_time, .Lfunc_end1-get_time
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12myCudaMallocPPvm
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z12myCudaMallocPPvm
.p2align 4, 0x90
.type _Z12myCudaMallocPPvm,@function
_Z12myCudaMallocPPvm: # @_Z12myCudaMallocPPvm
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB2_5:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z12myCudaMallocPPvm, .Lfunc_end2-_Z12myCudaMallocPPvm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.p2align 4, 0x90
.type _Z12myCudaMemcpyPvPKvm13hipMemcpyKind,@function
_Z12myCudaMemcpyPvPKvm13hipMemcpyKind: # @_Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl %ebx, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB3_5:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z12myCudaMemcpyPvPKvm13hipMemcpyKind, .Lfunc_end3-_Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $6337593344, %rbx # imm = 0x179C00000
movl $.L.str.2, %edi
movl $1584398336, %esi # imm = 0x5E700000
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $65536, %esi # imm = 0x10000
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl $6189056, %esi # imm = 0x5E7000
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq $0, (%rsp)
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB4_3
# %bb.2:
movzbl 67(%r15), %ecx
jmp .LBB4_4
.LBB4_3:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%r15)
je .LBB4_7
# %bb.6:
movzbl 67(%r15), %ecx
jmp .LBB4_8
.LBB4_7:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $8, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%r15)
je .LBB4_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB4_12
.LBB4_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %rbx, %rsi
callq _Z12myCudaMallocPPvm
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_13: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
incq %rax
cmpq $1584398336, %rax # imm = 0x5E700000
jne .LBB4_13
# %bb.14:
movq (%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm1
mulsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
leaq -2042625920(%rbx), %rdx
leaq -2042625536(%rbx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1584398336, 12(%rsp) # imm = 0x5E700000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%r15)
je .LBB4_19
# %bb.18:
movzbl 67(%r15), %ecx
jmp .LBB4_20
.LBB4_19:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
movl (%r14), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.9, %edi
movl $1584398336, %esi # imm = 0x5E700000
xorl %eax, %eax
callq printf
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_21:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPii,@object # @_Z6kernelPii
.section .rodata,"a",@progbits
.globl _Z6kernelPii
.p2align 3, 0x0
_Z6kernelPii:
.quad _Z21__device_stub__kernelPii
.size _Z6kernelPii, 8
.type _ZZ8get_timeE2tv,@object # @_ZZ8get_timeE2tv
.local _ZZ8get_timeE2tv
.comm _ZZ8get_timeE2tv,16,8
.type _ZZ8get_timeE2tz,@object # @_ZZ8get_timeE2tz
.local _ZZ8get_timeE2tz
.comm _ZZ8get_timeE2tz,8,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaMalloc: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaMemcpy: "
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# nword: %zd \n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "# threads: %d \n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "mem_size: %zd Kbyte\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "mem_size: "
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "(size_t)mem_size:"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU calc: "
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU: %d\n"
.size .L.str.8, 9
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "HOS: %d\n"
.size .L.str.9, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPii
.addrsig_sym _ZZ8get_timeE2tv
.addrsig_sym _ZZ8get_timeE2tz
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd600078e00ff */
/*0090*/ @!P0 BRA 0x440 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00d0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fc80000011403 */
/*0100*/ ISETP.GT.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80003f04100 */
/*0110*/ SEL R3, R3, 0x1, P0 ; /* 0x0000000103037807 */
/* 0x000fe40000000000 */
/*0120*/ SEL R0, R0, RZ, P0 ; /* 0x000000ff00007207 */
/* 0x000fe40000000000 */
/*0130*/ IADD3 R2, P2, R3.reuse, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x040fe40007f5e0ff */
/*0140*/ LOP3.LUT R12, R3, 0x3, RZ, 0xc0, !PT ; /* 0x00000003030c7812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0160*/ IADD3.X R2, R0, -0x1, RZ, P2, !PT ; /* 0xffffffff00027810 */
/* 0x000fc400017fe4ff */
/*0170*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05070 */
/*0180*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fe40003f26110 */
/*0190*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*01a0*/ @!P1 BRA 0x330 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R10, P1, R12, -R3, RZ ; /* 0x800000030c0a7210 */
/* 0x000fe20007f3e0ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*01f0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.X R11, RZ, RZ, ~R0, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e0e00 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0009 */
/*0240*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040802047981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080802077981 */
/* 0x000ee8000c1e1900 */
/*0270*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0802067981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0290*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02a0*/ IADD3 R8, P2, R10, UR4, RZ ; /* 0x000000040a087c10 */
/* 0x000fc8000ff5e0ff */
/*02b0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25070 */
/*02c0*/ IADD3.X R8, R11, UR5, RZ, P2, !PT ; /* 0x000000050b087c10 */
/* 0x000fc800097fe4ff */
/*02d0*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40003f25310 */
/*02e0*/ IADD3 R8, P2, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fca0007f5e0ff */
/*02f0*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0603 */
/*0300*/ IADD3 R0, R4, R0, R5 ; /* 0x0000000004007210 */
/* 0x004fc80007ffe005 */
/*0310*/ IADD3 R5, R6, R7, R0 ; /* 0x0000000706057210 */
/* 0x008fe20007ffe000 */
/*0320*/ @P1 BRA 0x220 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*0330*/ @!P0 BRA 0x440 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, P0, RZ, -R12, RZ ; /* 0x8000000cff007210 */
/* 0x000fe20007f1e0ff */
/*0350*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0360*/ ULEA UR6, UP0, UR4, UR6, 0x2 ; /* 0x0000000604067291 */
/* 0x000fe4000f80103f */
/*0370*/ IMAD.X R4, RZ, RZ, -0x1, P0 ; /* 0xffffffffff047424 */
/* 0x000fe400000e06ff */
/*0380*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x2, UP0 ; /* 0x0000000704047291 */
/* 0x000fc800080f1405 */
/*0390*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe4000f8e00ff */
/*03a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*03b0*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fc8000ff1e03f */
/*03e0*/ IMAD.X R4, RZ, RZ, R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0604 */
/*03f0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0400*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fc600087fe43f */
/*0410*/ ISETP.NE.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe20003f05300 */
/*0420*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x004fd800078e0205 */
/*0430*/ @P0 BRA 0x390 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0440*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0460*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPii
.globl _Z6kernelPii
.p2align 8
.type _Z6kernelPii,@function
_Z6kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 2, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_mov_b64 s[4:5], s[0:1]
.LBB0_3:
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s7, s6
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6
global_store_b32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPii, .Lfunc_end0-_Z6kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00059fd7_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl get_time
.type get_time, @function
get_time:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZZ8get_timeE2tz(%rip), %rsi
leaq _ZZ8get_timeE2tv(%rip), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8+_ZZ8get_timeE2tv(%rip), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size get_time, .-get_time
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc: "
.text
.globl _Z12myCudaMallocPPvm
.type _Z12myCudaMallocPPvm, @function
_Z12myCudaMallocPPvm:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %rbp
call get_time
movsd %xmm0, 8(%rsp)
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
movl $12, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call get_time
subsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L10
cmpb $0, 56(%rbp)
je .L7
movzbl 67(%rbp), %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.cfi_endproc
.LFE3670:
.size _Z12myCudaMallocPPvm, .-_Z12myCudaMallocPPvm
.section .rodata.str1.1
.LC2:
.string "cudaMemcpy: "
.text
.globl _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
.type _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind, @function
_Z12myCudaMemcpyPvPKvm14cudaMemcpyKind:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
call get_time
movsd %xmm0, 8(%rsp)
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $12, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call get_time
subsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L16
cmpb $0, 56(%rbp)
je .L13
movzbl 67(%rbp), %esi
.L14:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L13:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L14
.cfi_endproc
.LFE3671:
.size _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind, .-_Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl _Z6kernelPii
.type _Z6kernelPii, @function
_Z6kernelPii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6kernelPii, .-_Z6kernelPii
.section .rodata.str1.1
.LC3:
.string "# nword: %zd \n"
.LC4:
.string "# threads: %d \n"
.LC5:
.string "mem_size: %zd Kbyte\n"
.LC6:
.string "mem_size: "
.LC7:
.string "(size_t)mem_size:"
.LC8:
.string "GPU calc: "
.LC9:
.string "GPU: %d\n"
.LC10:
.string "HOS: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1584398336, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $65536, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $6189056, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movabsq $6337593344, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq $0, 24(%rsp)
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %esi
movq %r12, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call _Z12myCudaMallocPPvm
movq %rbp, %rax
leaq 0(%rbp,%rbx), %rdx
.L26:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
movl $1, %ecx
movabsq $6337593344, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
call get_time
movsd %xmm0, 8(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
call cudaThreadSynchronize@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call get_time
subsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movabsq $6337593344, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z12myCudaMemcpyPvPKvm14cudaMemcpyKind
movl 0(%rbp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1584398336, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl $1584398336, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6kernelPiiPii
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ8get_timeE2tz
.comm _ZZ8get_timeE2tz,8,8
.local _ZZ8get_timeE2tv
.comm _ZZ8get_timeE2tv,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPii # -- Begin function _Z21__device_stub__kernelPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPii,@function
_Z21__device_stub__kernelPii: # @_Z21__device_stub__kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPii, .Lfunc_end0-_Z21__device_stub__kernelPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function get_time
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl get_time
.p2align 4, 0x90
.type get_time,@function
get_time: # @get_time
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size get_time, .Lfunc_end1-get_time
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12myCudaMallocPPvm
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z12myCudaMallocPPvm
.p2align 4, 0x90
.type _Z12myCudaMallocPPvm,@function
_Z12myCudaMallocPPvm: # @_Z12myCudaMallocPPvm
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB2_5:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z12myCudaMallocPPvm, .Lfunc_end2-_Z12myCudaMallocPPvm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.p2align 4, 0x90
.type _Z12myCudaMemcpyPvPKvm13hipMemcpyKind,@function
_Z12myCudaMemcpyPvPKvm13hipMemcpyKind: # @_Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl %ebx, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB3_5:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z12myCudaMemcpyPvPKvm13hipMemcpyKind, .Lfunc_end3-_Z12myCudaMemcpyPvPKvm13hipMemcpyKind
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $6337593344, %rbx # imm = 0x179C00000
movl $.L.str.2, %edi
movl $1584398336, %esi # imm = 0x5E700000
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $65536, %esi # imm = 0x10000
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl $6189056, %esi # imm = 0x5E7000
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq $0, (%rsp)
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB4_3
# %bb.2:
movzbl 67(%r15), %ecx
jmp .LBB4_4
.LBB4_3:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%r15)
je .LBB4_7
# %bb.6:
movzbl 67(%r15), %ecx
jmp .LBB4_8
.LBB4_7:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $8, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%r15)
je .LBB4_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB4_12
.LBB4_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %rbx, %rsi
callq _Z12myCudaMallocPPvm
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_13: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
incq %rax
cmpq $1584398336, %rax # imm = 0x5E700000
jne .LBB4_13
# %bb.14:
movq (%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm1
mulsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
leaq -2042625920(%rbx), %rdx
leaq -2042625536(%rbx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1584398336, 12(%rsp) # imm = 0x5E700000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZZ8get_timeE2tv, %edi
movl $_ZZ8get_timeE2tz, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8get_timeE2tv(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8get_timeE2tv+8(%rip), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%r15)
je .LBB4_19
# %bb.18:
movzbl 67(%r15), %ecx
jmp .LBB4_20
.LBB4_19:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq _Z12myCudaMemcpyPvPKvm13hipMemcpyKind
movl (%r14), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.9, %edi
movl $1584398336, %esi # imm = 0x5E700000
xorl %eax, %eax
callq printf
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_21:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPii,@object # @_Z6kernelPii
.section .rodata,"a",@progbits
.globl _Z6kernelPii
.p2align 3, 0x0
_Z6kernelPii:
.quad _Z21__device_stub__kernelPii
.size _Z6kernelPii, 8
.type _ZZ8get_timeE2tv,@object # @_ZZ8get_timeE2tv
.local _ZZ8get_timeE2tv
.comm _ZZ8get_timeE2tv,16,8
.type _ZZ8get_timeE2tz,@object # @_ZZ8get_timeE2tz
.local _ZZ8get_timeE2tz
.comm _ZZ8get_timeE2tz,8,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaMalloc: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaMemcpy: "
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# nword: %zd \n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "# threads: %d \n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "mem_size: %zd Kbyte\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "mem_size: "
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "(size_t)mem_size:"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU calc: "
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU: %d\n"
.size .L.str.8, 9
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "HOS: %d\n"
.size .L.str.9, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPii
.addrsig_sym _ZZ8get_timeE2tv
.addrsig_sym _ZZ8get_timeE2tz
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2
// Execute: ./assignment5-p2
#include <algorithm>
#include <cuda.h>
#include <iostream>
#include <sys/time.h>
#define THRESHOLD (0.000001)
#define N (1 << 24)
#define CHUNK_SIZE 2048
#define CHUNK_SIZE2 2048
using std::cerr;
using std::cout;
using std::endl;
__host__ void host_excl_prefix_sum(float* h_A, float* h_O) {
h_O[0] = 0;
for (int i = 1; i < N; i++) {
h_O[i] = h_O[i - 1] + h_A[i - 1];
}
}
__global__ void kernel_excl_prefix_sum_ver1_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver1_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE;
if(i < N){
for(int j = i; j < upper_limit; j++){
d_out[j] += sum;
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE2;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE2; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE2;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE2;
if(i < N){
for(int j = i; j + 3 < upper_limit; j += 4){
d_out[j] += sum;
d_out[j+1] += sum;
d_out[j+2] += sum;
d_out[j+3] += sum;
}
}
}
__host__ void check_result(float* w_ref, float* w_opt) {
double maxdiff = 0.0, this_diff = 0.0;
int numdiffs = 0;
for (int i = 0; i < N; i++) {
this_diff = w_ref[i] - w_opt[i];
if (fabs(this_diff) > THRESHOLD) {
numdiffs++;
if (this_diff > maxdiff)
maxdiff = this_diff;
}
}
if (numdiffs > 0) {
cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
<< endl;
} else {
cout << "No differences found between base and test versions\n";
}
}
__host__ double rtclock() { // Seconds
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) {
cout << "Error return from gettimeofday: " << stat << "\n";
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
int main() {
size_t size = N * sizeof(float);
float* h_in = (float*)malloc(size);
std::fill_n(h_in, N, 1);
float* h_excl_sum_out = (float*)malloc(size);
std::fill_n(h_excl_sum_out, N, 0);
double clkbegin = rtclock();
host_excl_prefix_sum(h_in, h_excl_sum_out);
double clkend = rtclock();
double time = clkend - clkbegin; // seconds
cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;
float* h_dev_result = (float*)malloc(size);
std::fill_n(h_dev_result, N, 0);
float* d_k1_in;
float* d_k1_out;
cudaError_t status;
cudaEvent_t start, end;
// TODO: Fill in
status = cudaMalloc(&d_k1_in, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = cudaMalloc(&d_k1_out, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, 0);
status = cudaMemcpy(d_k1_in, h_in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = cudaMemcpy(d_k1_out, h_dev_result, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
dim3 threadsPerBlock(256);
dim3 numBlocks(((N/CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver1_1<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out);
numBlocks = dim3((N/(2*CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
long long int curr_chunk = CHUNK_SIZE;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver1_2<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out, curr_chunk);
curr_chunk *= 2;
}
status = cudaMemcpy(h_dev_result, d_k1_out, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
float k_time; // ms
cudaEventElapsedTime(&k_time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel1 time on GPU: " << k_time << " msec" << endl;
// kernel 2
std::fill_n(h_dev_result, N, 0);
float* d_k2_in;
float* d_k2_out;
status = cudaMalloc(&d_k2_in, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = cudaMalloc(&d_k2_out, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, 0);
status = cudaMemcpy(d_k2_in, h_in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = cudaMemcpy(d_k2_out, h_dev_result, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
threadsPerBlock = dim3(256);
numBlocks = dim3(((N/CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver2_1<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out);
threadsPerBlock = dim3(256);
numBlocks = dim3((N/(2*CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
curr_chunk = CHUNK_SIZE2;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver2_2<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out, curr_chunk);
curr_chunk *= 2;
}
status = cudaMemcpy(h_dev_result, d_k2_out, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&k_time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel2 time on GPU: " << k_time << " msec" << endl;
// Free device memory
cudaFree(d_k1_in);
cudaFree(d_k1_out);
cudaFree(d_k2_in);
cudaFree(d_k2_out);
free(h_in);
free(h_excl_sum_out);
free(h_dev_result);
return EXIT_SUCCESS;
} | .file "tmpxft_000cc34a_00000000-6_assignment5-p2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20host_excl_prefix_sumPfS_
.type _Z20host_excl_prefix_sumPfS_, @function
_Z20host_excl_prefix_sumPfS_:
.LFB3923:
.cfi_startproc
endbr64
movl $0x00000000, (%rsi)
movl $0, %eax
.L4:
movss (%rsi,%rax), %xmm0
addss (%rdi,%rax), %xmm0
movss %xmm0, 4(%rsi,%rax)
addq $4, %rax
cmpq $67108860, %rax
jne .L4
ret
.cfi_endproc
.LFE3923:
.size _Z20host_excl_prefix_sumPfS_, .-_Z20host_excl_prefix_sumPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string " Diffs found over threshold "
.LC5:
.string "; Max Diff = "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "No differences found between base and test versions\n"
.text
.globl _Z12check_resultPfS_
.type _Z12check_resultPfS_, @function
_Z12check_resultPfS_:
.LFB3924:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movl $0, %eax
movl $0, %edx
movq $0x000000000, 8(%rsp)
movq .LC2(%rip), %xmm3
movsd .LC3(%rip), %xmm2
jmp .L9
.L7:
addq $4, %rax
cmpq $67108864, %rax
je .L19
.L9:
movss (%rdi,%rax), %xmm0
subss (%rsi,%rax), %xmm0
cvtss2sd %xmm0, %xmm0
movapd %xmm0, %xmm1
andpd %xmm3, %xmm1
comisd %xmm2, %xmm1
jbe .L7
addl $1, %edx
maxsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
jmp .L7
.L19:
testl %edx, %edx
jle .L10
movl %edx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $28, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd .LC3(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $13, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L20
cmpb $0, 56(%rbp)
je .L12
movzbl 67(%rbp), %esi
.L13:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L6:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L12:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L10:
movl $52, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L6
.cfi_endproc
.LFE3924:
.size _Z12check_resultPfS_, .-_Z12check_resultPfS_
.section .rodata.str1.8
.align 8
.LC7:
.string "Error return from gettimeofday: "
.section .rodata.str1.1
.LC8:
.string "\n"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB3925:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L25
.L22:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC3(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %eax, %ebx
movl $32, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC8(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3925:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_
.type _Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_, @function
_Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_:
.LFB3951:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29kernel_excl_prefix_sum_ver1_1PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3951:
.size _Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_, .-_Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_
.globl _Z29kernel_excl_prefix_sum_ver1_1PfS_
.type _Z29kernel_excl_prefix_sum_ver1_1PfS_, @function
_Z29kernel_excl_prefix_sum_ver1_1PfS_:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _Z29kernel_excl_prefix_sum_ver1_1PfS_, .-_Z29kernel_excl_prefix_sum_ver1_1PfS_
.globl _Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x
.type _Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x, @function
_Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x:
.LFB3953:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29kernel_excl_prefix_sum_ver1_2PfS_x(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3953:
.size _Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x, .-_Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x
.globl _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.type _Z29kernel_excl_prefix_sum_ver1_2PfS_x, @function
_Z29kernel_excl_prefix_sum_ver1_2PfS_x:
.LFB3954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3954:
.size _Z29kernel_excl_prefix_sum_ver1_2PfS_x, .-_Z29kernel_excl_prefix_sum_ver1_2PfS_x
.globl _Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_
.type _Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_, @function
_Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_:
.LFB3955:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29kernel_excl_prefix_sum_ver2_1PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3955:
.size _Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_, .-_Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_
.globl _Z29kernel_excl_prefix_sum_ver2_1PfS_
.type _Z29kernel_excl_prefix_sum_ver2_1PfS_, @function
_Z29kernel_excl_prefix_sum_ver2_1PfS_:
.LFB3956:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3956:
.size _Z29kernel_excl_prefix_sum_ver2_1PfS_, .-_Z29kernel_excl_prefix_sum_ver2_1PfS_
.globl _Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x
.type _Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x, @function
_Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x:
.LFB3957:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29kernel_excl_prefix_sum_ver2_2PfS_x(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3957:
.size _Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x, .-_Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x
.globl _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.type _Z29kernel_excl_prefix_sum_ver2_2PfS_x, @function
_Z29kernel_excl_prefix_sum_ver2_2PfS_x:
.LFB3958:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3958:
.size _Z29kernel_excl_prefix_sum_ver2_2PfS_x, .-_Z29kernel_excl_prefix_sum_ver2_2PfS_x
.section .rodata.str1.1
.LC10:
.string "Serial time on CPU: "
.LC12:
.string " msec"
.LC13:
.string "cudaMalloc() failed"
.LC14:
.string "cudaMemcpy() failed"
.LC15:
.string "Kernel1 time on GPU: "
.LC16:
.string "Kernel2 time on GPU: "
.text
.globl main
.type main, @function
main:
.LFB3926:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
leaq 67108864(%rax), %rdx
movss .LC9(%rip), %xmm0
.L60:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L60
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
leaq 67108864(%rax), %rdx
.L61:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L61
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movq %r12, %rsi
movq %rbp, %rdi
call _Z20host_excl_prefix_sumPfS_
call _Z7rtclockv
movapd %xmm0, %xmm1
subsd 8(%rsp), %xmm1
movq %xmm1, %rbx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
mulsd .LC11(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r14
leaq 67108864(%rax), %rbx
.L62:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L62
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L89
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L90
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L91
movl $1, %ecx
movl $67108864, %edx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L92
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $32, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $256, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L68:
movl $16, 92(%rsp)
movl $13, %r13d
movl $2048, %r15d
jmp .L70
.L89:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
.L59:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L94
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L91:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L92:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L93:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z29kernel_excl_prefix_sum_ver1_1PfS_PfS_
jmp .L68
.L69:
addq %r15, %r15
subl $1, %r13d
je .L95
.L70:
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L69
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z52__device_stub__Z29kernel_excl_prefix_sum_ver1_2PfS_xPfS_x
jmp .L69
.L95:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L96
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq %r14, %rsi
movq %r12, %rdi
call _Z12check_resultPfS_
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rax
.L72:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L72
leaq 64(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L97
leaq 72(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L98
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L99
movl $1, %ecx
movl $67108864, %edx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L100
movl $32, 92(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L77:
movl $16, 92(%rsp)
movl $13, %r13d
movl $2048, %ebx
jmp .L79
.L96:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L97:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L98:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L99:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L100:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L101:
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z51__device_stub__Z29kernel_excl_prefix_sum_ver2_1PfS_PfS_
jmp .L77
.L78:
addq %rbx, %rbx
subl $1, %r13d
je .L102
.L79:
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L78
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z52__device_stub__Z29kernel_excl_prefix_sum_ver2_2PfS_xPfS_x
jmp .L78
.L102:
movl $2, %ecx
movl $67108864, %edx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L103
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq %r14, %rsi
movq %r12, %rdi
call _Z12check_resultPfS_
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movl $0, %eax
jmp .L59
.L103:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L59
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3926:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z29kernel_excl_prefix_sum_ver2_2PfS_x"
.align 8
.LC18:
.string "_Z29kernel_excl_prefix_sum_ver2_1PfS_"
.align 8
.LC19:
.string "_Z29kernel_excl_prefix_sum_ver1_2PfS_x"
.align 8
.LC20:
.string "_Z29kernel_excl_prefix_sum_ver1_1PfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3960:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z29kernel_excl_prefix_sum_ver2_2PfS_x(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z29kernel_excl_prefix_sum_ver2_1PfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z29kernel_excl_prefix_sum_ver1_2PfS_x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z29kernel_excl_prefix_sum_ver1_1PfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3960:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1065353216
.section .rodata.cst8
.align 8
.LC11:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2
// Execute: ./assignment5-p2
#include <algorithm>
#include <cuda.h>
#include <iostream>
#include <sys/time.h>
#define THRESHOLD (0.000001)
#define N (1 << 24)
#define CHUNK_SIZE 2048
#define CHUNK_SIZE2 2048
using std::cerr;
using std::cout;
using std::endl;
__host__ void host_excl_prefix_sum(float* h_A, float* h_O) {
h_O[0] = 0;
for (int i = 1; i < N; i++) {
h_O[i] = h_O[i - 1] + h_A[i - 1];
}
}
__global__ void kernel_excl_prefix_sum_ver1_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver1_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE;
if(i < N){
for(int j = i; j < upper_limit; j++){
d_out[j] += sum;
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE2;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE2; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE2;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE2;
if(i < N){
for(int j = i; j + 3 < upper_limit; j += 4){
d_out[j] += sum;
d_out[j+1] += sum;
d_out[j+2] += sum;
d_out[j+3] += sum;
}
}
}
__host__ void check_result(float* w_ref, float* w_opt) {
double maxdiff = 0.0, this_diff = 0.0;
int numdiffs = 0;
for (int i = 0; i < N; i++) {
this_diff = w_ref[i] - w_opt[i];
if (fabs(this_diff) > THRESHOLD) {
numdiffs++;
if (this_diff > maxdiff)
maxdiff = this_diff;
}
}
if (numdiffs > 0) {
cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
<< endl;
} else {
cout << "No differences found between base and test versions\n";
}
}
__host__ double rtclock() { // Seconds
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) {
cout << "Error return from gettimeofday: " << stat << "\n";
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
int main() {
size_t size = N * sizeof(float);
float* h_in = (float*)malloc(size);
std::fill_n(h_in, N, 1);
float* h_excl_sum_out = (float*)malloc(size);
std::fill_n(h_excl_sum_out, N, 0);
double clkbegin = rtclock();
host_excl_prefix_sum(h_in, h_excl_sum_out);
double clkend = rtclock();
double time = clkend - clkbegin; // seconds
cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;
float* h_dev_result = (float*)malloc(size);
std::fill_n(h_dev_result, N, 0);
float* d_k1_in;
float* d_k1_out;
cudaError_t status;
cudaEvent_t start, end;
// TODO: Fill in
status = cudaMalloc(&d_k1_in, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = cudaMalloc(&d_k1_out, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, 0);
status = cudaMemcpy(d_k1_in, h_in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = cudaMemcpy(d_k1_out, h_dev_result, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
dim3 threadsPerBlock(256);
dim3 numBlocks(((N/CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver1_1<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out);
numBlocks = dim3((N/(2*CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
long long int curr_chunk = CHUNK_SIZE;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver1_2<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out, curr_chunk);
curr_chunk *= 2;
}
status = cudaMemcpy(h_dev_result, d_k1_out, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
float k_time; // ms
cudaEventElapsedTime(&k_time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel1 time on GPU: " << k_time << " msec" << endl;
// kernel 2
std::fill_n(h_dev_result, N, 0);
float* d_k2_in;
float* d_k2_out;
status = cudaMalloc(&d_k2_in, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = cudaMalloc(&d_k2_out, size);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, 0);
status = cudaMemcpy(d_k2_in, h_in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = cudaMemcpy(d_k2_out, h_dev_result, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
threadsPerBlock = dim3(256);
numBlocks = dim3(((N/CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver2_1<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out);
threadsPerBlock = dim3(256);
numBlocks = dim3((N/(2*CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
curr_chunk = CHUNK_SIZE2;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver2_2<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out, curr_chunk);
curr_chunk *= 2;
}
status = cudaMemcpy(h_dev_result, d_k2_out, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&k_time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel2 time on GPU: " << k_time << " msec" << endl;
// Free device memory
cudaFree(d_k1_in);
cudaFree(d_k1_out);
cudaFree(d_k2_in);
cudaFree(d_k2_out);
free(h_in);
free(h_excl_sum_out);
free(h_dev_result);
return EXIT_SUCCESS;
} | // Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2
// Execute: ./assignment5-p2
#include <algorithm>
#include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define THRESHOLD (0.000001)
#define N (1 << 24)
#define CHUNK_SIZE 2048
#define CHUNK_SIZE2 2048
using std::cerr;
using std::cout;
using std::endl;
__host__ void host_excl_prefix_sum(float* h_A, float* h_O) {
h_O[0] = 0;
for (int i = 1; i < N; i++) {
h_O[i] = h_O[i - 1] + h_A[i - 1];
}
}
__global__ void kernel_excl_prefix_sum_ver1_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver1_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE;
if(i < N){
for(int j = i; j < upper_limit; j++){
d_out[j] += sum;
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE2;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE2; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE2;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE2;
if(i < N){
for(int j = i; j + 3 < upper_limit; j += 4){
d_out[j] += sum;
d_out[j+1] += sum;
d_out[j+2] += sum;
d_out[j+3] += sum;
}
}
}
__host__ void check_result(float* w_ref, float* w_opt) {
double maxdiff = 0.0, this_diff = 0.0;
int numdiffs = 0;
for (int i = 0; i < N; i++) {
this_diff = w_ref[i] - w_opt[i];
if (fabs(this_diff) > THRESHOLD) {
numdiffs++;
if (this_diff > maxdiff)
maxdiff = this_diff;
}
}
if (numdiffs > 0) {
cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
<< endl;
} else {
cout << "No differences found between base and test versions\n";
}
}
__host__ double rtclock() { // Seconds
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) {
cout << "Error return from gettimeofday: " << stat << "\n";
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
int main() {
size_t size = N * sizeof(float);
float* h_in = (float*)malloc(size);
std::fill_n(h_in, N, 1);
float* h_excl_sum_out = (float*)malloc(size);
std::fill_n(h_excl_sum_out, N, 0);
double clkbegin = rtclock();
host_excl_prefix_sum(h_in, h_excl_sum_out);
double clkend = rtclock();
double time = clkend - clkbegin; // seconds
cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;
float* h_dev_result = (float*)malloc(size);
std::fill_n(h_dev_result, N, 0);
float* d_k1_in;
float* d_k1_out;
hipError_t status;
hipEvent_t start, end;
// TODO: Fill in
status = hipMalloc(&d_k1_in, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = hipMalloc(&d_k1_out, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
status = hipMemcpy(d_k1_in, h_in, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = hipMemcpy(d_k1_out, h_dev_result, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
dim3 threadsPerBlock(256);
dim3 numBlocks(((N/CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver1_1<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out);
numBlocks = dim3((N/(2*CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
long long int curr_chunk = CHUNK_SIZE;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver1_2<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out, curr_chunk);
curr_chunk *= 2;
}
status = hipMemcpy(h_dev_result, d_k1_out, size, hipMemcpyDeviceToHost);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
float k_time; // ms
hipEventElapsedTime(&k_time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel1 time on GPU: " << k_time << " msec" << endl;
// kernel 2
std::fill_n(h_dev_result, N, 0);
float* d_k2_in;
float* d_k2_out;
status = hipMalloc(&d_k2_in, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = hipMalloc(&d_k2_out, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
status = hipMemcpy(d_k2_in, h_in, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = hipMemcpy(d_k2_out, h_dev_result, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
threadsPerBlock = dim3(256);
numBlocks = dim3(((N/CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver2_1<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out);
threadsPerBlock = dim3(256);
numBlocks = dim3((N/(2*CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
curr_chunk = CHUNK_SIZE2;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver2_2<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out, curr_chunk);
curr_chunk *= 2;
}
status = hipMemcpy(h_dev_result, d_k2_out, size, hipMemcpyDeviceToHost);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&k_time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel2 time on GPU: " << k_time << " msec" << endl;
// Free device memory
hipFree(d_k1_in);
hipFree(d_k1_out);
hipFree(d_k2_in);
hipFree(d_k2_out);
free(h_in);
free(h_excl_sum_out);
free(h_dev_result);
return EXIT_SUCCESS;
} |
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