system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>
#include <chrono>
#include <iomanip>
#include <fstream>
using namespace std;
using namespace std::chrono;
typedef unsigned long long ULL;
ofstream primeresult;
ofstream timeresult;
__global__ void cuda_erastothenes_sieve (ULL *marked, ULL *limit, ULL *n, int *totalThreads) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
//printf("block %d, thread %d \n", blockIdx.x, threadIdx.x);
marked[0]=1;
marked[1]=1;
index=index+2;
if(*totalThreads>*n || index >*limit){
return ;
}else if(*totalThreads ==1){
for(ULL p=2;p<=*limit;p++){
for(ULL multiple=2*p; multiple<*n; multiple+=p){
marked[multiple]=1;
}
}
}
else{
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
for(ULL p=index;p<=*limit;p+=*totalThreads){
if(marked[p]==1 || p%2==0 && p>2) return;
//printf("index %d , p%llu \n",index,p);
for(ULL multiple=2*p; multiple<*n; multiple+=p){
//printf("multiple %llu \n",multiple);
marked[multiple]=1;
}
}
}
__syncthreads();
}
int main(int argc, char **argv){
ULL size;
ULL *list,*d_list,limit,*d_limit,*d_n,n;
n=atoi(argv[1]);
int threads=atoi(argv[2]);
//int thread_per_block=atoi(argv[3]);
int blocks= floor(n/threads);
int totalThreads = threads;
int *d_totalThreads;
primeresult.open("cudaSieveList.txt");
timeresult.open("cudaSieveResult.txt",ios::out | ios::app );
size = n*sizeof(ULL);
limit = floor(sqrt(n));
hipMalloc((void**)&d_list,size);
hipMalloc((void**)&d_limit,sizeof(ULL));
hipMalloc((void**)&d_n,sizeof(ULL));
hipMalloc((void**)&d_totalThreads,sizeof(int));
list = (ULL*) malloc(size);
memset(list,0,size);
hipMemset(d_list, 0, size);
hipMemcpy(d_list ,list ,size ,hipMemcpyHostToDevice);
hipMemcpy(d_limit ,&limit ,sizeof(ULL) ,hipMemcpyHostToDevice);
hipMemcpy(d_n ,&n ,sizeof(ULL) ,hipMemcpyHostToDevice);
hipMemcpy(d_totalThreads ,&totalThreads ,sizeof(int) ,hipMemcpyHostToDevice);
auto begin= std::chrono::high_resolution_clock::now();
cuda_erastothenes_sieve<<<blocks,threads>>>(d_list,d_limit,d_n,d_totalThreads);
auto end = std::chrono::high_resolution_clock::now();
auto duration = duration_cast<std::chrono::microseconds>(end - begin);
timeresult<<duration.count()<<endl;
hipMemcpy(list,d_list, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// check for error
hipError_t error = hipGetLastError();
if(error != hipSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", hipGetErrorString(error));
return 0;
}
for(ULL i=0;i<n;i++){
if(list[i]==0){
primeresult<<i<<endl;
//cout<<i<<endl;
};
}
//cout<<duration.count()<<endl;
free(list);
hipFree(d_list);
hipFree(d_limit);
hipFree(d_n);
primeresult.close();
timeresult.close();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuda_erastothenes_sievePyS_S_Pi
.globl _Z23cuda_erastothenes_sievePyS_S_Pi
.p2align 8
.type _Z23cuda_erastothenes_sievePyS_S_Pi,@function
_Z23cuda_erastothenes_sievePyS_S_Pi:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v5, v3
s_waitcnt lgkmcnt(0)
global_store_b128 v1, v[2:5], s[8:9]
global_load_b64 v[2:3], v1, s[4:5]
s_load_b32 s6, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[2:3]
s_cbranch_vccnz .LBB0_24
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
global_load_b64 v[4:5], v1, s[2:3]
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s0
s_mov_b32 s0, exec_lo
v_add3_u32 v2, v0, s15, 2
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u64_e64 v[4:5], v[2:3]
s_cbranch_execz .LBB0_24
v_mov_b32_e32 v0, 0
s_cmp_eq_u32 s6, 1
global_load_b64 v[0:1], v0, s[2:3]
s_cbranch_scc1 .LBB0_13
s_mov_b32 s0, -1
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ge_u64_e64 v[0:1], v[2:3]
s_cbranch_execz .LBB0_15
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v12, 0
s_lshl_b64 s[10:11], s[6:7], 4
s_lshl_b64 s[12:13], s[6:7], 3
s_mov_b32 s14, 0
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_branch .LBB0_8
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s20
global_load_b64 v[8:9], v12, s[2:3]
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v4, s0, v4, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s13, v5, s0
s_xor_b32 s0, exec_lo, -1
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[8:9]
s_or_not1_b32 s20, vcc_lo, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s0, s0, exec_lo
s_and_not1_b32 s16, s16, exec_lo
s_and_b32 s19, s20, exec_lo
s_or_b32 s17, s17, s0
s_or_b32 s16, s16, s19
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s18
s_xor_b32 s0, s17, -1
s_and_b32 s18, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s14, s18, s14
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s15, s15, s0
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_14
.LBB0_8:
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_or_b32 s17, s17, exec_lo
s_or_b32 s16, s16, exec_lo
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e32 1, v[8:9]
s_cbranch_execz .LBB0_7
v_and_b32_e32 v8, 1, v2
v_cmp_gt_u64_e32 vcc_lo, 3, v[2:3]
s_mov_b32 s20, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 1, v8
s_or_b32 s21, vcc_lo, s0
s_mov_b32 s0, -1
s_and_saveexec_b32 s19, s21
s_cbranch_execz .LBB0_6
global_load_b64 v[10:11], v12, s[4:5]
v_lshlrev_b64 v[8:9], 1, v[2:3]
s_mov_b32 s20, exec_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u64_e64 v[8:9], v[10:11]
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
s_mov_b32 s21, 0
.p2align 6
.LBB0_12:
v_dual_mov_b32 v13, 1 :: v_dual_mov_b32 v14, 0
v_add_co_u32 v8, vcc_lo, v8, v2
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo
global_store_b64 v[10:11], v[13:14], off
global_load_b64 v[13:14], v12, s[4:5]
v_add_co_u32 v10, s0, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v11, s0, v11, v5, s0
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, v[8:9], v[13:14]
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_12
s_branch .LBB0_5
.LBB0_13:
s_mov_b32 s0, 0
s_cbranch_execnz .LBB0_16
s_branch .LBB0_22
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, s15, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
s_branch .LBB0_22
.LBB0_16:
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, 2, v[0:1]
s_mov_b64 s[0:1], 2
s_cbranch_vccnz .LBB0_21
v_mov_b32_e32 v0, 0
s_add_u32 s6, s8, 32
s_addc_u32 s7, s9, 0
s_mov_b64 s[8:9], 16
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_19
.p2align 6
.LBB0_18:
global_load_b64 v[1:2], v0, s[2:3]
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_add_u32 s6, s6, 16
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[1:2]
s_cbranch_vccnz .LBB0_21
.LBB0_19:
global_load_b64 v[1:2], v0, s[4:5]
s_lshl_b64 s[10:11], s[0:1], 1
s_mov_b64 s[12:13], s[6:7]
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, s[10:11], v[1:2]
s_cbranch_vccnz .LBB0_18
.LBB0_20:
v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 0
s_add_u32 s10, s10, s0
s_addc_u32 s11, s11, s1
global_store_b64 v0, v[1:2], s[12:13]
global_load_b64 v[1:2], v0, s[4:5]
s_add_u32 s12, s12, s8
s_addc_u32 s13, s13, s9
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, s[10:11], v[1:2]
s_cbranch_vccz .LBB0_20
s_branch .LBB0_18
.LBB0_21:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s0, -1
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_24
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuda_erastothenes_sievePyS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuda_erastothenes_sievePyS_S_Pi, .Lfunc_end0-_Z23cuda_erastothenes_sievePyS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuda_erastothenes_sievePyS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z23cuda_erastothenes_sievePyS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>
#include <chrono>
#include <iomanip>
#include <fstream>
using namespace std;
using namespace std::chrono;
typedef unsigned long long ULL;
ofstream primeresult;
ofstream timeresult;
__global__ void cuda_erastothenes_sieve (ULL *marked, ULL *limit, ULL *n, int *totalThreads) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
//printf("block %d, thread %d \n", blockIdx.x, threadIdx.x);
marked[0]=1;
marked[1]=1;
index=index+2;
if(*totalThreads>*n || index >*limit){
return ;
}else if(*totalThreads ==1){
for(ULL p=2;p<=*limit;p++){
for(ULL multiple=2*p; multiple<*n; multiple+=p){
marked[multiple]=1;
}
}
}
else{
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
for(ULL p=index;p<=*limit;p+=*totalThreads){
if(marked[p]==1 || p%2==0 && p>2) return;
//printf("index %d , p%llu \n",index,p);
for(ULL multiple=2*p; multiple<*n; multiple+=p){
//printf("multiple %llu \n",multiple);
marked[multiple]=1;
}
}
}
__syncthreads();
}
int main(int argc, char **argv){
ULL size;
ULL *list,*d_list,limit,*d_limit,*d_n,n;
n=atoi(argv[1]);
int threads=atoi(argv[2]);
//int thread_per_block=atoi(argv[3]);
int blocks= floor(n/threads);
int totalThreads = threads;
int *d_totalThreads;
primeresult.open("cudaSieveList.txt");
timeresult.open("cudaSieveResult.txt",ios::out | ios::app );
size = n*sizeof(ULL);
limit = floor(sqrt(n));
hipMalloc((void**)&d_list,size);
hipMalloc((void**)&d_limit,sizeof(ULL));
hipMalloc((void**)&d_n,sizeof(ULL));
hipMalloc((void**)&d_totalThreads,sizeof(int));
list = (ULL*) malloc(size);
memset(list,0,size);
hipMemset(d_list, 0, size);
hipMemcpy(d_list ,list ,size ,hipMemcpyHostToDevice);
hipMemcpy(d_limit ,&limit ,sizeof(ULL) ,hipMemcpyHostToDevice);
hipMemcpy(d_n ,&n ,sizeof(ULL) ,hipMemcpyHostToDevice);
hipMemcpy(d_totalThreads ,&totalThreads ,sizeof(int) ,hipMemcpyHostToDevice);
auto begin= std::chrono::high_resolution_clock::now();
cuda_erastothenes_sieve<<<blocks,threads>>>(d_list,d_limit,d_n,d_totalThreads);
auto end = std::chrono::high_resolution_clock::now();
auto duration = duration_cast<std::chrono::microseconds>(end - begin);
timeresult<<duration.count()<<endl;
hipMemcpy(list,d_list, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// check for error
hipError_t error = hipGetLastError();
if(error != hipSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", hipGetErrorString(error));
return 0;
}
for(ULL i=0;i<n;i++){
if(list[i]==0){
primeresult<<i<<endl;
//cout<<i<<endl;
};
}
//cout<<duration.count()<<endl;
free(list);
hipFree(d_list);
hipFree(d_limit);
hipFree(d_n);
primeresult.close();
timeresult.close();
return 0;
} | .text
.file "cudaSieve.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi # -- Begin function _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.p2align 4, 0x90
.type _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi,@function
_Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi: # @_Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23cuda_erastothenes_sievePyS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi, .Lfunc_end0-_Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %r12
movq %r12, 16(%rsp)
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movslq %r15d, %rcx
movq %r12, %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r12
movl %ecx, 44(%rsp)
movl $primeresult+8, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
movl $primeresult, %edi
movq primeresult(%rip), %rcx
addq -24(%rcx), %rdi
movl $0, %esi
testq %rax, %rax
jne .LBB1_2
# %bb.1:
movl 32(%rdi), %esi
orl $4, %esi
.LBB1_2: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
movl $timeresult+8, %edi
movl $.L.str.2, %esi
movl $17, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
movl $timeresult, %edi
movq timeresult(%rip), %rcx
addq -24(%rcx), %rdi
testq %rax, %rax
jne .LBB1_4
# %bb.3:
movl 32(%rdi), %ebx
orl $4, %ebx
.LBB1_4: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit29
movabsq $4294967296, %rbp # imm = 0x100000000
movl %ebx, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
movq 16(%rsp), %r14
movq %r14, %xmm1
shlq $3, %r14
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_6
# %bb.5:
sqrtsd %xmm0, %xmm0
jmp .LBB1_7
.LBB1_6: # %call.sqrt
callq sqrt
.LBB1_7: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit29.split
callq floor@PLT
cvttsd2si %xmm0, %rax
movq %rax, %rcx
subsd .LCPI1_2(%rip), %xmm0
cvttsd2si %xmm0, %rdx
sarq $63, %rcx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, 56(%rsp)
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 56(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 44(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl %r12d, %edi
orq %rbp, %rdi
movl %r15d, %edx
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z23cuda_erastothenes_sievePyS_S_Pi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r13, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $timeresult, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_29
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_12
# %bb.11:
movzbl 67(%r15), %ecx
jmp .LBB1_13
.LBB1_12:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_14
# %bb.27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB1_28
.LBB1_14: # %.preheader
cmpq $0, 16(%rsp)
je .LBB1_20
# %bb.15: # %.lr.ph.preheader
xorl %r14d, %r14d
jmp .LBB1_16
.LBB1_24: # in Loop: Header=BB1_16 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
# in Loop: Header=BB1_16 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_26: # in Loop: Header=BB1_16 Depth=1
incq %r14
cmpq 16(%rsp), %r14
jae .LBB1_20
.LBB1_16: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $0, (%rbx,%r14,8)
jne .LBB1_26
# %bb.17: # in Loop: Header=BB1_16 Depth=1
movl $primeresult, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_29
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
# in Loop: Header=BB1_16 Depth=1
cmpb $0, 56(%r15)
je .LBB1_24
# %bb.19: # in Loop: Header=BB1_16 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_25
.LBB1_20: # %._crit_edge
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $primeresult+8, %edi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
testq %rax, %rax
jne .LBB1_22
# %bb.21:
movq primeresult(%rip), %rax
movq -24(%rax), %rax
leaq primeresult(%rax), %rdi
movl primeresult+32(%rax), %esi
orl $4, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_22: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movl $timeresult+8, %edi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
testq %rax, %rax
jne .LBB1_28
# %bb.23:
movq timeresult(%rip), %rax
movq -24(%rax), %rax
leaq timeresult(%rax), %rdi
movl timeresult+32(%rax), %esi
orl $4, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_28: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit32
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_29:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_cudaSieve.hip
.type _GLOBAL__sub_I_cudaSieve.hip,@function
_GLOBAL__sub_I_cudaSieve.hip: # @_GLOBAL__sub_I_cudaSieve.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $primeresult, %edi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
movl $_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev, %edi
movl $primeresult, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $timeresult, %edi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
movl $_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev, %edi
movl $timeresult, %esi
movl $__dso_handle, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end2:
.size _GLOBAL__sub_I_cudaSieve.hip, .Lfunc_end2-_GLOBAL__sub_I_cudaSieve.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuda_erastothenes_sievePyS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type primeresult,@object # @primeresult
.bss
.globl primeresult
.p2align 3, 0x0
primeresult:
.zero 512
.size primeresult, 512
.hidden __dso_handle
.type timeresult,@object # @timeresult
.globl timeresult
.p2align 3, 0x0
timeresult:
.zero 512
.size timeresult, 512
.type _Z23cuda_erastothenes_sievePyS_S_Pi,@object # @_Z23cuda_erastothenes_sievePyS_S_Pi
.section .rodata,"a",@progbits
.globl _Z23cuda_erastothenes_sievePyS_S_Pi
.p2align 3, 0x0
_Z23cuda_erastothenes_sievePyS_S_Pi:
.quad _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.size _Z23cuda_erastothenes_sievePyS_S_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaSieveList.txt"
.size .L.str, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSieveResult.txt"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA error: %s\n"
.size .L.str.3, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23cuda_erastothenes_sievePyS_S_Pi"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_cudaSieve.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.addrsig_sym _GLOBAL__sub_I_cudaSieve.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym primeresult
.addrsig_sym __dso_handle
.addrsig_sym timeresult
.addrsig_sym _Z23cuda_erastothenes_sievePyS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23cuda_erastothenes_sievePyS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e2000c101b0c */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fc400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ STG.E.64 [R6.64+0x8], R8 ; /* 0x0000080806007986 */
/* 0x0001e8000c101b0c */
/*00c0*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E.64 R12, [R2.64] ; /* 0x0000000c020c7981 */
/* 0x000ee2000c1e1b00 */
/*00e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R10 ; /* 0x0000001fff007819 */
/* 0x004fc4000001140a */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R12, R10, PT ; /* 0x0000000a0c00720c */
/* 0x008fc80003f06070 */
/*0100*/ ISETP.GE.U32.AND.EX P0, PT, R13, R0, PT, P0 ; /* 0x000000000d00720c */
/* 0x000fda0003f06100 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fca00078e00ff */
/*0140*/ LDG.E.64 R14, [R6.64] ; /* 0x0000000c060e7981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0160*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0170*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x001fca00078e0200 */
/*0180*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc80007ffe0ff */
/*0190*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011400 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R14, R0, PT ; /* 0x000000000e00720c */
/* 0x004fc80003f06070 */
/*01b0*/ ISETP.GE.U32.AND.EX P0, PT, R15, R11, PT, P0 ; /* 0x0000000b0f00720c */
/* 0x000fda0003f06100 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000e */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fd400078e000f */
/*0200*/ @!P0 BRA 0x520 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*0210*/ LEA R14, P0, R0, c[0x0][0x160], 0x3 ; /* 0x00005800000e7a11 */
/* 0x000fc800078018ff */
/*0220*/ LEA.HI.X R15, R0, c[0x0][0x164], R11, 0x3, P0 ; /* 0x00005900000f7a11 */
/* 0x000fcc00000f1c0b */
/*0230*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0240*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fc80003f05070 */
/*0250*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ LOP3.LUT R14, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x00000001000e7812 */
/* 0x040fe400078ec0ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f04070 */
/*0290*/ ISETP.NE.U32.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003f25070 */
/*02a0*/ ISETP.GT.U32.AND.EX P0, PT, R11, RZ, PT, P0 ; /* 0x000000ff0b00720c */
/* 0x000fe40003f04100 */
/*02b0*/ ISETP.NE.U32.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fda0003f25110 */
/*02c0*/ @P1 EXIT P0 ; /* 0x000000000000194d */
/* 0x001fea0000000000 */
/*02d0*/ IMAD.SHL.U32 R15, R0.reuse, 0x2, RZ ; /* 0x00000002000f7824 */
/* 0x040fe200078e00ff */
/*02e0*/ SHF.L.U64.HI R14, R0, 0x1, R11 ; /* 0x00000001000e7819 */
/* 0x000fe2000001020b */
/*02f0*/ BSSY B0, 0x460 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x000fc80003f06070 */
/*0310*/ ISETP.GE.U32.AND.EX P0, PT, R14, R13, PT, P0 ; /* 0x0000000d0e00720c */
/* 0x000fda0003f06100 */
/*0320*/ @P0 BRA 0x450 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0330*/ BSSY B1, 0x410 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0340*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0350*/ LEA R8, P0, R15.reuse, c[0x0][0x160], 0x3 ; /* 0x000058000f087a11 */
/* 0x040fe200078018ff */
/*0360*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe400078e00ff */
/*0370*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe200078e00ff */
/*0380*/ LEA.HI.X R9, R15, c[0x0][0x164], R10, 0x3, P0 ; /* 0x000059000f097a11 */
/* 0x000fca00000f1c0a */
/*0390*/ STG.E.64 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x0001e8000c101b0c */
/*03a0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000c02107981 */
/* 0x000ea2000c1e1b00 */
/*03b0*/ IADD3 R15, P0, R0, R15, RZ ; /* 0x0000000f000f7210 */
/* 0x000fca0007f1e0ff */
/*03c0*/ IMAD.X R10, R11, 0x1, R10, P0 ; /* 0x000000010b0a7824 */
/* 0x000fe200000e060a */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x004fc80003f06070 */
/*03e0*/ ISETP.GE.U32.AND.EX P0, PT, R10, R17, PT, P0 ; /* 0x000000110a00720c */
/* 0x000fda0003f06100 */
/*03f0*/ @!P0 BRA 0x350 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*0400*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000168000c1e1900 */
/*0420*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000c06087981 */
/* 0x000162000c1e1b00 */
/*0430*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0010 */
/*0440*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0011 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R0, P0, R10, R0, RZ ; /* 0x000000000a007210 */
/* 0x020fc80007f1e0ff */
/*0470*/ LEA.HI.X.SX32 R11, R10, R11, 0x1, P0 ; /* 0x0000000b0a0b7211 */
/* 0x000fe400000f0eff */
/*0480*/ ISETP.GT.U32.AND P0, PT, R0, R8, PT ; /* 0x000000080000720c */
/* 0x000fc80003f04070 */
/*0490*/ ISETP.GT.U32.AND.EX P0, PT, R11, R9, PT, P0 ; /* 0x000000090b00720c */
/* 0x000fda0003f04100 */
/*04a0*/ @P0 BRA 0x730 ; /* 0x0000028000000947 */
/* 0x000fea0003800000 */
/*04b0*/ LEA R14, P0, R0, c[0x0][0x160], 0x3 ; /* 0x00005800000e7a11 */
/* 0x000fc800078018ff */
/*04c0*/ LEA.HI.X R15, R0, c[0x0][0x164], R11, 0x3, P0 ; /* 0x00005900000f7a11 */
/* 0x000fcc00000f1c0b */
/*04d0*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000ea4000c1e1b00 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fc80003f05070 */
/*04f0*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*0500*/ @P0 BRA 0x270 ; /* 0xfffffd6000000947 */
/* 0x000fea000383ffff */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc80003f06070 */
/*0530*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06100 */
/*0540*/ @!P0 BRA 0x730 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0550*/ UMOV UR9, 0x2 ; /* 0x0000000200097882 */
/* 0x000fe40000000000 */
/*0560*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0570*/ USHF.L.U64.HI UR8, UR9, 0x1, UR4 ; /* 0x0000000109087899 */
/* 0x000fe40008010204 */
/*0580*/ USHF.L.U32 UR7, UR9, 0x1, URZ ; /* 0x0000000109077899 */
/* 0x000fc8000800063f */
/*0590*/ IMAD.U32 R0, RZ, RZ, UR8 ; /* 0x00000008ff007e24 */
/* 0x000fe4000f8e00ff */
/*05a0*/ ISETP.LE.U32.AND P0, PT, R12, UR7, PT ; /* 0x000000070c007c0c */
/* 0x000fc8000bf03070 */
/*05b0*/ ISETP.GE.U32.AND.EX P0, PT, R0, R13, PT, P0 ; /* 0x0000000d0000720c */
/* 0x000fda0003f06100 */
/*05c0*/ @P0 BRA 0x6d0 ; /* 0x0000010000000947 */
/* 0x001fea0003800000 */
/*05d0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe20000000a00 */
/*05e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*05f0*/ ULEA UR5, UP0, UR7, UR10, 0x3 ; /* 0x0000000a07057291 */
/* 0x000fe2000f80183f */
/*0600*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc600078e00ff */
/*0610*/ ULEA.HI.X UR6, UR7, UR11, UR8, 0x3, UP0 ; /* 0x0000000b07067291 */
/* 0x000fe400080f1c08 */
/*0620*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x000fc8000f8e00ff */
/*0630*/ IMAD.U32 R5, RZ, RZ, UR6 ; /* 0x00000006ff057e24 */
/* 0x000fca000f8e00ff */
/*0640*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b0c */
/*0650*/ LDG.E.64 R12, [R2.64] ; /* 0x0000000c020c7981 */
/* 0x000ea2000c1e1b00 */
/*0660*/ UIADD3 UR7, UP0, UR9, UR7, URZ ; /* 0x0000000709077290 */
/* 0x000fc8000ff1e03f */
/*0670*/ UIADD3.X UR8, UR4, UR8, URZ, UP0, !UPT ; /* 0x0000000804087290 */
/* 0x000fcc00087fe43f */
/*0680*/ IMAD.U32 R0, RZ, RZ, UR8 ; /* 0x00000008ff007e24 */
/* 0x000fe2000f8e00ff */
/*0690*/ ISETP.LE.U32.AND P0, PT, R12, UR7, PT ; /* 0x000000070c007c0c */
/* 0x004fc8000bf03070 */
/*06a0*/ ISETP.GE.U32.AND.EX P0, PT, R0, R13, PT, P0 ; /* 0x0000000d0000720c */
/* 0x000fda0003f06100 */
/*06b0*/ @!P0 BRA 0x5d0 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*06c0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000c06087981 */
/* 0x000164000c1e1b00 */
/*06d0*/ UIADD3 UR9, UP0, UR9, 0x1, URZ ; /* 0x0000000109097890 */
/* 0x000fc8000ff1e03f */
/*06e0*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe400087fe43f */
/*06f0*/ ISETP.LT.U32.AND P0, PT, R8, UR9, PT ; /* 0x0000000908007c0c */
/* 0x020fc8000bf01070 */
/*0700*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fca000f8e00ff */
/*0710*/ ISETP.GT.U32.AND.EX P0, PT, R0, R9, PT, P0 ; /* 0x000000090000720c */
/* 0x000fda0003f04100 */
/*0720*/ @!P0 BRA 0x570 ; /* 0xfffffe4000008947 */
/* 0x000fea000383ffff */
/*0730*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0740*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuda_erastothenes_sievePyS_S_Pi
.globl _Z23cuda_erastothenes_sievePyS_S_Pi
.p2align 8
.type _Z23cuda_erastothenes_sievePyS_S_Pi,@function
_Z23cuda_erastothenes_sievePyS_S_Pi:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v5, v3
s_waitcnt lgkmcnt(0)
global_store_b128 v1, v[2:5], s[8:9]
global_load_b64 v[2:3], v1, s[4:5]
s_load_b32 s6, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[2:3]
s_cbranch_vccnz .LBB0_24
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
global_load_b64 v[4:5], v1, s[2:3]
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s0
s_mov_b32 s0, exec_lo
v_add3_u32 v2, v0, s15, 2
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u64_e64 v[4:5], v[2:3]
s_cbranch_execz .LBB0_24
v_mov_b32_e32 v0, 0
s_cmp_eq_u32 s6, 1
global_load_b64 v[0:1], v0, s[2:3]
s_cbranch_scc1 .LBB0_13
s_mov_b32 s0, -1
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ge_u64_e64 v[0:1], v[2:3]
s_cbranch_execz .LBB0_15
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v12, 0
s_lshl_b64 s[10:11], s[6:7], 4
s_lshl_b64 s[12:13], s[6:7], 3
s_mov_b32 s14, 0
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_branch .LBB0_8
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s20
global_load_b64 v[8:9], v12, s[2:3]
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v4, s0, v4, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s13, v5, s0
s_xor_b32 s0, exec_lo, -1
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[8:9]
s_or_not1_b32 s20, vcc_lo, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s0, s0, exec_lo
s_and_not1_b32 s16, s16, exec_lo
s_and_b32 s19, s20, exec_lo
s_or_b32 s17, s17, s0
s_or_b32 s16, s16, s19
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s18
s_xor_b32 s0, s17, -1
s_and_b32 s18, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s14, s18, s14
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s15, s15, s0
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_14
.LBB0_8:
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_or_b32 s17, s17, exec_lo
s_or_b32 s16, s16, exec_lo
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e32 1, v[8:9]
s_cbranch_execz .LBB0_7
v_and_b32_e32 v8, 1, v2
v_cmp_gt_u64_e32 vcc_lo, 3, v[2:3]
s_mov_b32 s20, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 1, v8
s_or_b32 s21, vcc_lo, s0
s_mov_b32 s0, -1
s_and_saveexec_b32 s19, s21
s_cbranch_execz .LBB0_6
global_load_b64 v[10:11], v12, s[4:5]
v_lshlrev_b64 v[8:9], 1, v[2:3]
s_mov_b32 s20, exec_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u64_e64 v[8:9], v[10:11]
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
s_mov_b32 s21, 0
.p2align 6
.LBB0_12:
v_dual_mov_b32 v13, 1 :: v_dual_mov_b32 v14, 0
v_add_co_u32 v8, vcc_lo, v8, v2
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo
global_store_b64 v[10:11], v[13:14], off
global_load_b64 v[13:14], v12, s[4:5]
v_add_co_u32 v10, s0, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v11, s0, v11, v5, s0
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, v[8:9], v[13:14]
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_12
s_branch .LBB0_5
.LBB0_13:
s_mov_b32 s0, 0
s_cbranch_execnz .LBB0_16
s_branch .LBB0_22
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, s15, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
s_branch .LBB0_22
.LBB0_16:
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, 2, v[0:1]
s_mov_b64 s[0:1], 2
s_cbranch_vccnz .LBB0_21
v_mov_b32_e32 v0, 0
s_add_u32 s6, s8, 32
s_addc_u32 s7, s9, 0
s_mov_b64 s[8:9], 16
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_19
.p2align 6
.LBB0_18:
global_load_b64 v[1:2], v0, s[2:3]
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_add_u32 s6, s6, 16
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
s_waitcnt vmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[1:2]
s_cbranch_vccnz .LBB0_21
.LBB0_19:
global_load_b64 v[1:2], v0, s[4:5]
s_lshl_b64 s[10:11], s[0:1], 1
s_mov_b64 s[12:13], s[6:7]
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, s[10:11], v[1:2]
s_cbranch_vccnz .LBB0_18
.LBB0_20:
v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v2, 0
s_add_u32 s10, s10, s0
s_addc_u32 s11, s11, s1
global_store_b64 v0, v[1:2], s[12:13]
global_load_b64 v[1:2], v0, s[4:5]
s_add_u32 s12, s12, s8
s_addc_u32 s13, s13, s9
s_waitcnt vmcnt(0)
v_cmp_ge_u64_e32 vcc_lo, s[10:11], v[1:2]
s_cbranch_vccz .LBB0_20
s_branch .LBB0_18
.LBB0_21:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s0, -1
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_24
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuda_erastothenes_sievePyS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuda_erastothenes_sievePyS_S_Pi, .Lfunc_end0-_Z23cuda_erastothenes_sievePyS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuda_erastothenes_sievePyS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z23cuda_erastothenes_sievePyS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005cbe5_00000000-6_cudaSieve.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4144:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4144:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
.type _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi, @function
_Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi:
.LFB4166:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23cuda_erastothenes_sievePyS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4166:
.size _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi, .-_Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
.globl _Z23cuda_erastothenes_sievePyS_S_Pi
.type _Z23cuda_erastothenes_sievePyS_S_Pi, @function
_Z23cuda_erastothenes_sievePyS_S_Pi:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _Z23cuda_erastothenes_sievePyS_S_Pi, .-_Z23cuda_erastothenes_sievePyS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaSieveList.txt"
.LC1:
.string "cudaSieveResult.txt"
.LC6:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB4138:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq %rax, 48(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movslq %eax, %rcx
movq 48(%rsp), %rax
movl $0, %edx
divq %rcx
testq %rax, %rax
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L13:
cvttsd2sil %xmm0, %r14d
movl %r12d, 12(%rsp)
movl $16, %edx
leaq .LC0(%rip), %rsi
leaq primeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $17, %edx
leaq .LC1(%rip), %rsi
leaq timeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq 48(%rsp), %rax
leaq 0(,%rax,8), %rbx
testq %rax, %rax
js .L14
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L15:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L37
sqrtsd %xmm0, %xmm0
.L18:
movapd %xmm0, %xmm1
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm3
andpd %xmm2, %xmm3
movsd .LC3(%rip), %xmm4
ucomisd %xmm3, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
movapd %xmm3, %xmm1
.L19:
comisd .LC5(%rip), %xmm1
jnb .L20
cvttsd2siq %xmm1, %rax
movq %rax, 24(%rsp)
.L21:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movq %rbx, %rdx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl %r12d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L22:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
leaq timeresult(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
movl $0, %ebx
leaq primeresult(%rip), %r13
cmpq $0, 48(%rsp)
jne .L24
.L25:
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq primeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq timeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.L26:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L14:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L15
.L37:
call sqrt@PLT
jmp .L18
.L20:
subsd .LC5(%rip), %xmm1
cvttsd2siq %xmm1, %rax
movq %rax, 24(%rsp)
btcq $63, 24(%rsp)
jmp .L21
.L39:
movq 56(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
jmp .L22
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L42:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L30:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L31:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L27:
addq $1, %rbx
cmpq 48(%rsp), %rbx
jnb .L25
.L24:
cmpq $0, 0(%rbp,%rbx,8)
jne .L27
movq %rbx, %rsi
movq %r13, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L42
cmpb $0, 56(%r14)
je .L30
movzbl 67(%r14), %esi
jmp .L31
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4138:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z23cuda_erastothenes_sievePyS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuda_erastothenes_sievePyS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_primeresult, @function
_GLOBAL__sub_I_primeresult:
.LFB4900:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq primeresult(%rip), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
leaq __dso_handle(%rip), %r12
movq %r12, %rdx
movq %rbx, %rsi
movq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GOTPCREL(%rip), %rbx
movq %rbx, %rdi
call __cxa_atexit@PLT
leaq timeresult(%rip), %rbp
movq %rbp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call __cxa_atexit@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4900:
.size _GLOBAL__sub_I_primeresult, .-_GLOBAL__sub_I_primeresult
.section .init_array
.align 8
.quad _GLOBAL__sub_I_primeresult
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl timeresult
.bss
.align 32
.type timeresult, @object
.size timeresult, 512
timeresult:
.zero 512
.globl primeresult
.align 32
.type primeresult, @object
.size primeresult, 512
primeresult:
.zero 512
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1138753536
.align 8
.LC7:
.long -1
.long 2147483647
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaSieve.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi # -- Begin function _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.p2align 4, 0x90
.type _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi,@function
_Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi: # @_Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23cuda_erastothenes_sievePyS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi, .Lfunc_end0-_Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %r12
movq %r12, 16(%rsp)
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movslq %r15d, %rcx
movq %r12, %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r12
movl %ecx, 44(%rsp)
movl $primeresult+8, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
movl $primeresult, %edi
movq primeresult(%rip), %rcx
addq -24(%rcx), %rdi
movl $0, %esi
testq %rax, %rax
jne .LBB1_2
# %bb.1:
movl 32(%rdi), %esi
orl $4, %esi
.LBB1_2: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
movl $timeresult+8, %edi
movl $.L.str.2, %esi
movl $17, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
movl $timeresult, %edi
movq timeresult(%rip), %rcx
addq -24(%rcx), %rdi
testq %rax, %rax
jne .LBB1_4
# %bb.3:
movl 32(%rdi), %ebx
orl $4, %ebx
.LBB1_4: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit29
movabsq $4294967296, %rbp # imm = 0x100000000
movl %ebx, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
movq 16(%rsp), %r14
movq %r14, %xmm1
shlq $3, %r14
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_6
# %bb.5:
sqrtsd %xmm0, %xmm0
jmp .LBB1_7
.LBB1_6: # %call.sqrt
callq sqrt
.LBB1_7: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit29.split
callq floor@PLT
cvttsd2si %xmm0, %rax
movq %rax, %rcx
subsd .LCPI1_2(%rip), %xmm0
cvttsd2si %xmm0, %rdx
sarq $63, %rcx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, 56(%rsp)
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 56(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 44(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl %r12d, %edi
orq %rbp, %rdi
movl %r15d, %edx
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z23cuda_erastothenes_sievePyS_S_Pi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r13, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $timeresult, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_29
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_12
# %bb.11:
movzbl 67(%r15), %ecx
jmp .LBB1_13
.LBB1_12:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_14
# %bb.27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB1_28
.LBB1_14: # %.preheader
cmpq $0, 16(%rsp)
je .LBB1_20
# %bb.15: # %.lr.ph.preheader
xorl %r14d, %r14d
jmp .LBB1_16
.LBB1_24: # in Loop: Header=BB1_16 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
# in Loop: Header=BB1_16 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_26: # in Loop: Header=BB1_16 Depth=1
incq %r14
cmpq 16(%rsp), %r14
jae .LBB1_20
.LBB1_16: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $0, (%rbx,%r14,8)
jne .LBB1_26
# %bb.17: # in Loop: Header=BB1_16 Depth=1
movl $primeresult, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_29
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
# in Loop: Header=BB1_16 Depth=1
cmpb $0, 56(%r15)
je .LBB1_24
# %bb.19: # in Loop: Header=BB1_16 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_25
.LBB1_20: # %._crit_edge
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $primeresult+8, %edi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
testq %rax, %rax
jne .LBB1_22
# %bb.21:
movq primeresult(%rip), %rax
movq -24(%rax), %rax
leaq primeresult(%rax), %rdi
movl primeresult+32(%rax), %esi
orl $4, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_22: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movl $timeresult+8, %edi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
testq %rax, %rax
jne .LBB1_28
# %bb.23:
movq timeresult(%rip), %rax
movq -24(%rax), %rax
leaq timeresult(%rax), %rdi
movl timeresult+32(%rax), %esi
orl $4, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_28: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit32
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_29:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_cudaSieve.hip
.type _GLOBAL__sub_I_cudaSieve.hip,@function
_GLOBAL__sub_I_cudaSieve.hip: # @_GLOBAL__sub_I_cudaSieve.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $primeresult, %edi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
movl $_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev, %edi
movl $primeresult, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $timeresult, %edi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
movl $_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev, %edi
movl $timeresult, %esi
movl $__dso_handle, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end2:
.size _GLOBAL__sub_I_cudaSieve.hip, .Lfunc_end2-_GLOBAL__sub_I_cudaSieve.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuda_erastothenes_sievePyS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type primeresult,@object # @primeresult
.bss
.globl primeresult
.p2align 3, 0x0
primeresult:
.zero 512
.size primeresult, 512
.hidden __dso_handle
.type timeresult,@object # @timeresult
.globl timeresult
.p2align 3, 0x0
timeresult:
.zero 512
.size timeresult, 512
.type _Z23cuda_erastothenes_sievePyS_S_Pi,@object # @_Z23cuda_erastothenes_sievePyS_S_Pi
.section .rodata,"a",@progbits
.globl _Z23cuda_erastothenes_sievePyS_S_Pi
.p2align 3, 0x0
_Z23cuda_erastothenes_sievePyS_S_Pi:
.quad _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.size _Z23cuda_erastothenes_sievePyS_S_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaSieveList.txt"
.size .L.str, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSieveResult.txt"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA error: %s\n"
.size .L.str.3, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23cuda_erastothenes_sievePyS_S_Pi"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_cudaSieve.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuda_erastothenes_sievePyS_S_Pi
.addrsig_sym _GLOBAL__sub_I_cudaSieve.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym primeresult
.addrsig_sym __dso_handle
.addrsig_sym timeresult
.addrsig_sym _Z23cuda_erastothenes_sievePyS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void expandKernel(double* values, int n_original, int factor, double* expanded){
int tid0 = threadIdx.x + blockIdx.x*blockDim.x ;
int stride = blockDim.x*gridDim.x ;
for ( int tid = tid0 ; tid < n_original*factor ; tid += stride){
int idx = floor(double(tid)/factor) ;
expanded[tid] = values[idx] ;
}
} | code for sm_80
Function : _Z12expandKernelPdiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R23, SR_CTAID.X ; /* 0x0000000000177919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R23, R23, c[0x0][0x0], R0 ; /* 0x0000000017177a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ I2F.F64 R8, c[0x0][0x16c] ; /* 0x00005b0000087b12 */
/* 0x000e220000201c00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ BSSY B0, 0x490 ; /* 0x000003d000007945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.IADD R2, R0.reuse, 0x1, R23 ; /* 0x0000000100027824 */
/* 0x040fe200078e0217 */
/*00e0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e620000209000 */
/*00f0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*0100*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*0110*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0130*/ IADD3 R5, R5, UR4, R0 ; /* 0x0000000405057c10 */
/* 0x000fe2000fffe000 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*0150*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x002fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e64000021f000 */
/*0170*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x002fc800078e02ff */
/*0180*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0190*/ IMAD.HI.U32 R24, R2, R5, RZ ; /* 0x0000000502187227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R2, RZ, RZ, -R24 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a18 */
/*01b0*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*01d0*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*01e0*/ @P0 IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118180810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118181810 */
/* 0x000fe40007ffe0ff */
/*0210*/ @!P2 LOP3.LUT R24, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff18a212 */
/* 0x000fc800078e33ff */
/*0220*/ IADD3 R2, R24, 0x1, RZ ; /* 0x0000000118027810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LOP3.LUT P0, R25, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302197812 */
/* 0x000fda000780c0ff */
/*0240*/ @!P0 BRA 0x480 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R20, RZ, RZ, 0x8 ; /* 0x00000008ff147424 */
/* 0x001fc800078e00ff */
/*0260*/ IMAD.WIDE R20, R23, R20, c[0x0][0x170] ; /* 0x00005c0017147625 */
/* 0x000fc800078e0214 */
/*0270*/ MUFU.RCP64H R3, R9 ; /* 0x0000000900037308 */
/* 0x000e220000001800 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0290*/ BSSY B1, 0x3e0 ; /* 0x0000014000017945 */
/* 0x000fec0003800000 */
/*02a0*/ I2F.F64 R14, R23 ; /* 0x00000017000e7312 */
/* 0x000e620000201c00 */
/*02b0*/ DFMA R4, -R8, R2, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c0000000102 */
/*02c0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e220000000004 */
/*02d0*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fca0003f2e200 */
/*02e0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*02f0*/ DFMA R2, -R8, R4, 1 ; /* 0x3ff000000802742b */
/* 0x001e0c0000000104 */
/*0300*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0310*/ DMUL R4, R14, R2 ; /* 0x000000020e047228 */
/* 0x001e0c0000000000 */
/*0320*/ DFMA R6, -R8, R4, R14 ; /* 0x000000040806722b */
/* 0x001e0c000000010e */
/*0330*/ DFMA R2, R2, R6, R4 ; /* 0x000000060202722b */
/* 0x001e140000000004 */
/*0340*/ FFMA R4, RZ, R9, R3 ; /* 0x00000009ff047223 */
/* 0x001fca0000000003 */
/*0350*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*0360*/ @P0 BRA P1, 0x3d0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0380*/ MOV R2, 0x3b0 ; /* 0x000003b000027802 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*03a0*/ CALL.REL.NOINC 0xbe0 ; /* 0x0000083000007944 */
/* 0x000fea0003c00000 */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*03c0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ F2I.F64.FLOOR R4, R2 ; /* 0x0000000200047311 */
/* 0x000e220000305100 */
/*03f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0400*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x001fcc00078e0205 */
/*0410*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IADD3 R25, R25, -0x1, RZ ; /* 0xffffffff19197810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R23, R0.reuse, R23, RZ ; /* 0x0000001700177210 */
/* 0x040fe40007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fe20003f05270 */
/*0450*/ STG.E.64 [R20.64], R4 ; /* 0x0000000414007986 */
/* 0x0041e4000c101b06 */
/*0460*/ IMAD.WIDE R20, R0, 0x8, R20 ; /* 0x0000000800147825 */
/* 0x001fd400078e0214 */
/*0470*/ @P0 BRA 0x270 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0490*/ ISETP.GE.U32.AND P0, PT, R24, 0x3, PT ; /* 0x000000031800780c */
/* 0x000fda0003f06070 */
/*04a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04b0*/ MUFU.RCP64H R3, R9 ; /* 0x0000000900037308 */
/* 0x001e220000001800 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*04d0*/ BSSY B0, 0x600 ; /* 0x0000012000007945 */
/* 0x000fec0003800000 */
/*04e0*/ I2F.F64 R14, R23 ; /* 0x00000017000e7312 */
/* 0x000e620000201c00 */
/*04f0*/ DFMA R4, -R8, R2, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c0000000102 */
/*0500*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e220000000004 */
/*0510*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fca0003f2e200 */
/*0520*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0530*/ DFMA R2, -R8, R4, 1 ; /* 0x3ff000000802742b */
/* 0x001e0c0000000104 */
/*0540*/ DFMA R6, R4, R2, R4 ; /* 0x000000020406722b */
/* 0x001e0c0000000004 */
/*0550*/ DMUL R2, R6, R14 ; /* 0x0000000e06027228 */
/* 0x001e0c0000000000 */
/*0560*/ DFMA R4, -R8, R2, R14 ; /* 0x000000020804722b */
/* 0x001e0c000000010e */
/*0570*/ DFMA R4, R6, R4, R2 ; /* 0x000000040604722b */
/* 0x001e140000000002 */
/*0580*/ FFMA R2, RZ, R9, R5 ; /* 0x00000009ff027223 */
/* 0x001fca0000000005 */
/*0590*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fda0003f04200 */
/*05a0*/ @P0 BRA P1, 0x5f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*05b0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*05c0*/ MOV R2, 0x5f0 ; /* 0x000005f000027802 */
/* 0x000fe20000000f00 */
/*05d0*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*05e0*/ CALL.REL.NOINC 0xbe0 ; /* 0x000005f000007944 */
/* 0x000fea0003c00000 */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ F2I.F64.FLOOR R2, R4 ; /* 0x0000000400027311 */
/* 0x000e220000305100 */
/*0610*/ IMAD.MOV.U32 R20, RZ, RZ, 0x8 ; /* 0x00000008ff147424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R2, R2, R20, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0214 */
/*0630*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0640*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001800 */
/*0650*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0660*/ BSSY B0, 0x7c0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0670*/ IMAD.IADD R25, R0, 0x1, R23 ; /* 0x0000000100197824 */
/* 0x000fe400078e0217 */
/*0680*/ IMAD.WIDE R20, R23, R20, c[0x0][0x170] ; /* 0x00005c0017147625 */
/* 0x000fc600078e0214 */
/*0690*/ I2F.F64 R14, R25 ; /* 0x00000019000e7312 */
/* 0x000e620000201c00 */
/*06a0*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*06b0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e22000000000a */
/*06c0*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fca0003f2e200 */
/*06d0*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*06e0*/ DFMA R4, -R8, R10, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c000000010a */
/*06f0*/ DFMA R10, R10, R4, R10 ; /* 0x000000040a0a722b */
/* 0x001e0c000000000a */
/*0700*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x001e0c0000000000 */
/*0710*/ DFMA R6, -R8, R4, R14 ; /* 0x000000040806722b */
/* 0x001e0c000000010e */
/*0720*/ DFMA R4, R10, R6, R4 ; /* 0x000000060a04722b */
/* 0x001e140000000004 */
/*0730*/ FFMA R6, RZ, R9, R5 ; /* 0x00000009ff067223 */
/* 0x001fca0000000005 */
/*0740*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fe20003f04200 */
/*0750*/ STG.E.64 [R20.64], R2 ; /* 0x0000000214007986 */
/* 0x0041d8000c101b06 */
/*0760*/ @P0 BRA P1, 0x7b0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0770*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0780*/ MOV R2, 0x7b0 ; /* 0x000007b000027802 */
/* 0x001fe20000000f00 */
/*0790*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*07a0*/ CALL.REL.NOINC 0xbe0 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ F2I.F64.FLOOR R2, R4 ; /* 0x0000000400027311 */
/* 0x001e220000305100 */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*07e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0203 */
/*07f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0800*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001800 */
/*0810*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0820*/ IADD3 R23, R0.reuse, R25, RZ ; /* 0x0000001900177210 */
/* 0x040fe20007ffe0ff */
/*0830*/ IMAD.WIDE R20, R0, 0x8, R20 ; /* 0x0000000800147825 */
/* 0x000fe200078e0214 */
/*0840*/ BSSY B0, 0x980 ; /* 0x0000013000007945 */
/* 0x000fe80003800000 */
/*0850*/ I2F.F64 R14, R23 ; /* 0x00000017000e7312 */
/* 0x000e620000201c00 */
/*0860*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*0870*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e22000000000a */
/*0880*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fca0003f2e200 */
/*0890*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*08a0*/ DFMA R4, -R8, R10, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c000000010a */
/*08b0*/ DFMA R10, R10, R4, R10 ; /* 0x000000040a0a722b */
/* 0x001e0c000000000a */
/*08c0*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x001e0c0000000000 */
/*08d0*/ DFMA R6, -R8, R4, R14 ; /* 0x000000040806722b */
/* 0x001e0c000000010e */
/*08e0*/ DFMA R4, R10, R6, R4 ; /* 0x000000060a04722b */
/* 0x001e140000000004 */
/*08f0*/ FFMA R6, RZ, R9, R5 ; /* 0x00000009ff067223 */
/* 0x001fca0000000005 */
/*0900*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fe20003f04200 */
/*0910*/ STG.E.64 [R20.64], R2 ; /* 0x0000000214007986 */
/* 0x0041d8000c101b06 */
/*0920*/ @P0 BRA P1, 0x970 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0930*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0940*/ MOV R2, 0x970 ; /* 0x0000097000027802 */
/* 0x001fe20000000f00 */
/*0950*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*0960*/ CALL.REL.NOINC 0xbe0 ; /* 0x0000027000007944 */
/* 0x000fea0003c00000 */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0980*/ F2I.F64.FLOOR R2, R4 ; /* 0x0000000400027311 */
/* 0x001e220000305100 */
/*0990*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*09a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0203 */
/*09b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*09c0*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001800 */
/*09d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*09e0*/ BSSY B0, 0xb40 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*09f0*/ IMAD.IADD R23, R0.reuse, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x040fe400078e0217 */
/*0a00*/ IMAD.WIDE R20, R0, 0x8, R20 ; /* 0x0000000800147825 */
/* 0x000fc600078e0214 */
/*0a10*/ I2F.F64 R14, R23 ; /* 0x00000017000e7312 */
/* 0x000e620000201c00 */
/*0a20*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*0a30*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e22000000000a */
/*0a40*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fca0003f2e200 */
/*0a50*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*0a60*/ DFMA R4, -R8, R10, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c000000010a */
/*0a70*/ DFMA R10, R10, R4, R10 ; /* 0x000000040a0a722b */
/* 0x001e0c000000000a */
/*0a80*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x001e0c0000000000 */
/*0a90*/ DFMA R6, -R8, R4, R14 ; /* 0x000000040806722b */
/* 0x001e0c000000010e */
/*0aa0*/ DFMA R4, R10, R6, R4 ; /* 0x000000060a04722b */
/* 0x001e140000000004 */
/*0ab0*/ FFMA R6, RZ, R9, R5 ; /* 0x00000009ff067223 */
/* 0x001fca0000000005 */
/*0ac0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fe20003f04200 */
/*0ad0*/ STG.E.64 [R20.64], R2 ; /* 0x0000000214007986 */
/* 0x0041d8000c101b06 */
/*0ae0*/ @P0 BRA P1, 0xb30 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0af0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0b00*/ MOV R2, 0xb30 ; /* 0x00000b3000027802 */
/* 0x001fe20000000f00 */
/*0b10*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*0b20*/ CALL.REL.NOINC 0xbe0 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0b30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b40*/ F2I.F64.FLOOR R2, R4 ; /* 0x0000000400027311 */
/* 0x001e220000305100 */
/*0b50*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0b60*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0203 */
/*0b70*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0b80*/ IMAD.WIDE R20, R0, 0x8, R20 ; /* 0x0000000800147825 */
/* 0x000fc800078e0214 */
/*0b90*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fca00078e0217 */
/*0ba0*/ ISETP.GE.AND P0, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fe2000bf06270 */
/*0bb0*/ STG.E.64 [R20.64], R2 ; /* 0x0000000214007986 */
/* 0x0041d8000c101b06 */
/*0bc0*/ @!P0 BRA 0x4b0 ; /* 0xfffff8e000008947 */
/* 0x000fea000383ffff */
/*0bd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0be0*/ FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f0e200 */
/*0bf0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*0c00*/ LOP3.LUT R10, R13, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0d0a7812 */
/* 0x000fe200078ec0ff */
/*0c10*/ BSSY B2, 0x1170 ; /* 0x0000055000027945 */
/* 0x000fe20003800000 */
/*0c20*/ FSETP.GEU.AND P2, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe40003f4e200 */
/*0c30*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0c40*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0c50*/ MOV R26, 0x1 ; /* 0x00000001001a7802 */
/* 0x000fe40000000f00 */
/*0c60*/ LOP3.LUT R3, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f037812 */
/* 0x000fc400078ec0ff */
/*0c70*/ LOP3.LUT R6, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d067812 */
/* 0x000fe200078ec0ff */
/*0c80*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e060000000000 */
/*0c90*/ ISETP.GE.U32.AND P1, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f26070 */
/*0ca0*/ @!P2 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d04a812 */
/* 0x000fe200078ec0ff */
/*0cb0*/ MUFU.RCP64H R27, R11 ; /* 0x0000000b001b7308 */
/* 0x001e260000001800 */
/*0cc0*/ @!P2 ISETP.GE.U32.AND P3, PT, R3, R4, PT ; /* 0x000000040300a20c */
/* 0x000fe20003f66070 */
/*0cd0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff047424 */
/* 0x000fe200078e00ff */
/*0ce0*/ @!P0 LOP3.LUT R6, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b068812 */
/* 0x000fc800078ec0ff */
/*0cf0*/ @!P2 SEL R5, R4.reuse, 0x63400000, !P3 ; /* 0x634000000405a807 */
/* 0x040fe40005800000 */
/*0d00*/ SEL R17, R4, 0x63400000, !P1 ; /* 0x6340000004117807 */
/* 0x000fe40004800000 */
/*0d10*/ @!P2 LOP3.LUT R5, R5, 0x80000000, R15.reuse, 0xf8, !PT ; /* 0x800000000505a812 */
/* 0x100fe400078ef80f */
/*0d20*/ LOP3.LUT R17, R17, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff11117812 */
/* 0x000fe200078ef80f */
/*0d30*/ DFMA R18, R26, -R10, 1 ; /* 0x3ff000001a12742b */
/* 0x001e22000000080a */
/*0d40*/ IADD3 R22, R6, -0x1, RZ ; /* 0xffffffff06167810 */
/* 0x000fca0007ffe0ff */
/*0d50*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0d60*/ DFMA R18, R26, R18, R26 ; /* 0x000000121a12722b */
/* 0x001064000000001a */
/*0d70*/ @!P2 LOP3.LUT R27, R5, 0x100000, RZ, 0xfc, !PT ; /* 0x00100000051ba812 */
/* 0x001fe200078efcff */
/*0d80*/ @!P2 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1aa224 */
/* 0x000fe400078e00ff */
/*0d90*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*0da0*/ DFMA R28, R18, -R10, 1 ; /* 0x3ff00000121c742b */
/* 0x002e08000000080a */
/*0db0*/ @!P2 DFMA R16, R16, 2, -R26 ; /* 0x400000001010a82b */
/* 0x000e48000000081a */
/*0dc0*/ DFMA R28, R18, R28, R18 ; /* 0x0000001c121c722b */
/* 0x001e0c0000000012 */
/*0dd0*/ @!P2 LOP3.LUT R5, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001105a812 */
/* 0x002fe200078ec0ff */
/*0de0*/ DMUL R26, R28, R16 ; /* 0x000000101c1a7228 */
/* 0x001e060000000000 */
/*0df0*/ IADD3 R7, R5, -0x1, RZ ; /* 0xffffffff05077810 */
/* 0x000fc60007ffe0ff */
/*0e00*/ DFMA R18, R26, -R10, R16 ; /* 0x8000000a1a12722b */
/* 0x001e220000000010 */
/*0e10*/ ISETP.GT.U32.AND P0, PT, R7, 0x7feffffe, PT ; /* 0x7feffffe0700780c */
/* 0x000fc80003f04070 */
/*0e20*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*0e30*/ DFMA R18, R28, R18, R26 ; /* 0x000000121c12722b */
/* 0x001058000000001a */
/*0e40*/ @P0 BRA 0x1010 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0e50*/ LOP3.LUT R6, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d067812 */
/* 0x003fc800078ec0ff */
/*0e60*/ ISETP.GE.U32.AND P0, PT, R3.reuse, R6, PT ; /* 0x000000060300720c */
/* 0x040fe20003f06070 */
/*0e70*/ IMAD.IADD R5, R3, 0x1, -R6 ; /* 0x0000000103057824 */
/* 0x000fc600078e0a06 */
/*0e80*/ SEL R4, R4, 0x63400000, !P0 ; /* 0x6340000004047807 */
/* 0x000fe40004000000 */
/*0e90*/ IMNMX R5, R5, -0x46a00000, !PT ; /* 0xb960000005057817 */
/* 0x000fc80007800200 */
/*0ea0*/ IMNMX R3, R5, 0x46a00000, PT ; /* 0x46a0000005037817 */
/* 0x000fca0003800200 */
/*0eb0*/ IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a04 */
/*0ec0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0ed0*/ IADD3 R5, R3, 0x7fe00000, RZ ; /* 0x7fe0000003057810 */
/* 0x000fcc0007ffe0ff */
/*0ee0*/ DMUL R26, R18, R4 ; /* 0x00000004121a7228 */
/* 0x000e140000000000 */
/*0ef0*/ FSETP.GTU.AND P0, PT, |R27|, 1.469367938527859385e-39, PT ; /* 0x001000001b00780b */
/* 0x001fda0003f0c200 */
/*0f00*/ @P0 BRA 0x1160 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0f10*/ DFMA R10, R18, -R10, R16 ; /* 0x8000000a120a722b */
/* 0x000e220000000010 */
/*0f20*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0f30*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x041fe40003f0d000 */
/*0f40*/ LOP3.LUT R13, R11, 0x80000000, R13, 0x48, !PT ; /* 0x800000000b0d7812 */
/* 0x000fc800078e480d */
/*0f50*/ LOP3.LUT R7, R13, R5, RZ, 0xfc, !PT ; /* 0x000000050d077212 */
/* 0x000fce00078efcff */
/*0f60*/ @!P0 BRA 0x1160 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0f70*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*0f80*/ DMUL.RP R6, R18, R6 ; /* 0x0000000612067228 */
/* 0x000e220000008000 */
/*0f90*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0fa0*/ IADD3 R3, -R3, -0x43300000, RZ ; /* 0xbcd0000003037810 */
/* 0x000fca0007ffe1ff */
/*0fb0*/ DFMA R4, R26, -R4, R18 ; /* 0x800000041a04722b */
/* 0x000e460000000012 */
/*0fc0*/ LOP3.LUT R13, R7, R13, RZ, 0x3c, !PT ; /* 0x0000000d070d7212 */
/* 0x001fce00078e3cff */
/*0fd0*/ FSETP.NEU.AND P0, PT, |R5|, R3, PT ; /* 0x000000030500720b */
/* 0x002fc80003f0d200 */
/*0fe0*/ FSEL R26, R6, R26, !P0 ; /* 0x0000001a061a7208 */
/* 0x000fe40004000000 */
/*0ff0*/ FSEL R27, R13, R27, !P0 ; /* 0x0000001b0d1b7208 */
/* 0x000fe20004000000 */
/*1000*/ BRA 0x1160 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*1010*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x003e1c0003f08000 */
/*1020*/ @P0 BRA 0x1140 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*1030*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e1c0003f08000 */
/*1040*/ @P0 BRA 0x1110 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*1050*/ ISETP.NE.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fe20003f05270 */
/*1060*/ IMAD.MOV.U32 R27, RZ, RZ, -0x80000 ; /* 0xfff80000ff1b7424 */
/* 0x000fe200078e00ff */
/*1070*/ MOV R26, 0x0 ; /* 0x00000000001a7802 */
/* 0x000fd60000000f00 */
/*1080*/ @!P0 BRA 0x1160 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1090*/ ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ; /* 0x7ff000000500780c */
/* 0x000fe40003f05270 */
/*10a0*/ LOP3.LUT R27, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f1b7812 */
/* 0x000fe400078e480d */
/*10b0*/ ISETP.EQ.OR P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fda0004702670 */
/*10c0*/ @P0 LOP3.LUT R3, R27, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000001b030812 */
/* 0x000fe200078efcff */
/*10d0*/ @!P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a8224 */
/* 0x000fe400078e00ff */
/*10e0*/ @P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a0224 */
/* 0x000fe400078e00ff */
/*10f0*/ @P0 IMAD.MOV.U32 R27, RZ, RZ, R3 ; /* 0x000000ffff1b0224 */
/* 0x000fe200078e0003 */
/*1100*/ BRA 0x1160 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1110*/ LOP3.LUT R27, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d1b7812 */
/* 0x000fe200078efcff */
/*1120*/ IMAD.MOV.U32 R26, RZ, RZ, R12 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e000c */
/*1130*/ BRA 0x1160 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1140*/ LOP3.LUT R27, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f1b7812 */
/* 0x000fe200078efcff */
/*1150*/ IMAD.MOV.U32 R26, RZ, RZ, R14 ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e000e */
/*1160*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe400078e00ff */
/*1180*/ IMAD.MOV.U32 R4, RZ, RZ, R26 ; /* 0x000000ffff047224 */
/* 0x000fc400078e001a */
/*1190*/ IMAD.MOV.U32 R5, RZ, RZ, R27 ; /* 0x000000ffff057224 */
/* 0x000fe200078e001b */
/*11a0*/ RET.REL.NODEC R2 0x0 ; /* 0xffffee5002007950 */
/* 0x000fec0003c3ffff */
/*11b0*/ BRA 0x11b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void expandKernel(double* values, int n_original, int factor, double* expanded){
int tid0 = threadIdx.x + blockIdx.x*blockDim.x ;
int stride = blockDim.x*gridDim.x ;
for ( int tid = tid0 ; tid < n_original*factor ; tid += stride){
int idx = floor(double(tid)/factor) ;
expanded[tid] = values[idx] ;
}
} | .file "tmpxft_0015523b_00000000-6_expandKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_
.type _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_, @function
_Z36__device_stub__Z12expandKernelPdiiS_PdiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12expandKernelPdiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_, .-_Z36__device_stub__Z12expandKernelPdiiS_PdiiS_
.globl _Z12expandKernelPdiiS_
.type _Z12expandKernelPdiiS_, @function
_Z12expandKernelPdiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12expandKernelPdiiS_, .-_Z12expandKernelPdiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12expandKernelPdiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12expandKernelPdiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void expandKernel(double* values, int n_original, int factor, double* expanded){
int tid0 = threadIdx.x + blockIdx.x*blockDim.x ;
int stride = blockDim.x*gridDim.x ;
for ( int tid = tid0 ; tid < n_original*factor ; tid += stride){
int idx = floor(double(tid)/factor) ;
expanded[tid] = values[idx] ;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void expandKernel(double* values, int n_original, int factor, double* expanded){
int tid0 = threadIdx.x + blockIdx.x*blockDim.x ;
int stride = blockDim.x*gridDim.x ;
for ( int tid = tid0 ; tid < n_original*factor ; tid += stride){
int idx = floor(double(tid)/factor) ;
expanded[tid] = values[idx] ;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void expandKernel(double* values, int n_original, int factor, double* expanded){
int tid0 = threadIdx.x + blockIdx.x*blockDim.x ;
int stride = blockDim.x*gridDim.x ;
for ( int tid = tid0 ; tid < n_original*factor ; tid += stride){
int idx = floor(double(tid)/factor) ;
expanded[tid] = values[idx] ;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12expandKernelPdiiS_
.globl _Z12expandKernelPdiiS_
.p2align 8
.type _Z12expandKernelPdiiS_,@function
_Z12expandKernelPdiiS_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_mul_i32 s8, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
v_cvt_f64_i32_e32 v[3:4], s5
s_load_b32 s4, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
v_add_co_u32 v5, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_cvt_f64_i32_e32 v[7:8], v1
v_add_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[9:10], null, v[3:4], v[3:4], v[7:8]
v_div_scale_f64 v[15:16], vcc_lo, v[7:8], v[3:4], v[7:8]
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_mul_f64 v[13:14], v[15:16], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[7:8], v[9:10], v[3:4], v[7:8]
v_floor_f64_e32 v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v7, v[7:8]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[7:8], v[7:8], off
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[7:8], off
v_add_co_u32 v5, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12expandKernelPdiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12expandKernelPdiiS_, .Lfunc_end0-_Z12expandKernelPdiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12expandKernelPdiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12expandKernelPdiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void expandKernel(double* values, int n_original, int factor, double* expanded){
int tid0 = threadIdx.x + blockIdx.x*blockDim.x ;
int stride = blockDim.x*gridDim.x ;
for ( int tid = tid0 ; tid < n_original*factor ; tid += stride){
int idx = floor(double(tid)/factor) ;
expanded[tid] = values[idx] ;
}
} | .text
.file "expandKernel.hip"
.globl _Z27__device_stub__expandKernelPdiiS_ # -- Begin function _Z27__device_stub__expandKernelPdiiS_
.p2align 4, 0x90
.type _Z27__device_stub__expandKernelPdiiS_,@function
_Z27__device_stub__expandKernelPdiiS_: # @_Z27__device_stub__expandKernelPdiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12expandKernelPdiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__expandKernelPdiiS_, .Lfunc_end0-_Z27__device_stub__expandKernelPdiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12expandKernelPdiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12expandKernelPdiiS_,@object # @_Z12expandKernelPdiiS_
.section .rodata,"a",@progbits
.globl _Z12expandKernelPdiiS_
.p2align 3, 0x0
_Z12expandKernelPdiiS_:
.quad _Z27__device_stub__expandKernelPdiiS_
.size _Z12expandKernelPdiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12expandKernelPdiiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__expandKernelPdiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12expandKernelPdiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015523b_00000000-6_expandKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_
.type _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_, @function
_Z36__device_stub__Z12expandKernelPdiiS_PdiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12expandKernelPdiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_, .-_Z36__device_stub__Z12expandKernelPdiiS_PdiiS_
.globl _Z12expandKernelPdiiS_
.type _Z12expandKernelPdiiS_, @function
_Z12expandKernelPdiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12expandKernelPdiiS_PdiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12expandKernelPdiiS_, .-_Z12expandKernelPdiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12expandKernelPdiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12expandKernelPdiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "expandKernel.hip"
.globl _Z27__device_stub__expandKernelPdiiS_ # -- Begin function _Z27__device_stub__expandKernelPdiiS_
.p2align 4, 0x90
.type _Z27__device_stub__expandKernelPdiiS_,@function
_Z27__device_stub__expandKernelPdiiS_: # @_Z27__device_stub__expandKernelPdiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12expandKernelPdiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__expandKernelPdiiS_, .Lfunc_end0-_Z27__device_stub__expandKernelPdiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12expandKernelPdiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12expandKernelPdiiS_,@object # @_Z12expandKernelPdiiS_
.section .rodata,"a",@progbits
.globl _Z12expandKernelPdiiS_
.p2align 3, 0x0
_Z12expandKernelPdiiS_:
.quad _Z27__device_stub__expandKernelPdiiS_
.size _Z12expandKernelPdiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12expandKernelPdiiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__expandKernelPdiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12expandKernelPdiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Exemplo para o curso de Super Computacao
// Criado por: Luciano P. Soares (10 de Abril de 2018)
#include <stdio.h>
#include <stdlib.h>
//#include <cuda.h>
//#include <cuda_runtime.h>
/* Informacoes da GPU */
int main() {
int dev_count;
cudaGetDeviceCount(&dev_count);
printf("Numero de devices (GPU) = %d\n\n", dev_count );
cudaDeviceProp dev_prop;
for (int i = 0; i < dev_count; i++) {
printf("\tDevice (%d)\n", i);
cudaGetDeviceProperties(&dev_prop, i);
printf("\t\tNumero maximo de Bloco\n");
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxGridSize[0],dev_prop.maxGridSize[1],dev_prop.maxGridSize[2] );
printf("\t\tNumero maximo de Threads por Bloco = %d\n", dev_prop.maxThreadsPerBlock );
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxThreadsDim[0],dev_prop.maxThreadsDim[1],dev_prop.maxThreadsDim[2] );
printf("\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n", dev_prop.multiProcessorCount );
printf("\t\tFrequencia de Clock = %d\n", dev_prop.clockRate );
printf("\t\tTamanho do Warp = %d\n", dev_prop.warpSize );
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Exemplo para o curso de Super Computacao
// Criado por: Luciano P. Soares (10 de Abril de 2018)
#include <stdio.h>
#include <stdlib.h>
//#include <cuda.h>
//#include <cuda_runtime.h>
/* Informacoes da GPU */
int main() {
int dev_count;
cudaGetDeviceCount(&dev_count);
printf("Numero de devices (GPU) = %d\n\n", dev_count );
cudaDeviceProp dev_prop;
for (int i = 0; i < dev_count; i++) {
printf("\tDevice (%d)\n", i);
cudaGetDeviceProperties(&dev_prop, i);
printf("\t\tNumero maximo de Bloco\n");
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxGridSize[0],dev_prop.maxGridSize[1],dev_prop.maxGridSize[2] );
printf("\t\tNumero maximo de Threads por Bloco = %d\n", dev_prop.maxThreadsPerBlock );
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxThreadsDim[0],dev_prop.maxThreadsDim[1],dev_prop.maxThreadsDim[2] );
printf("\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n", dev_prop.multiProcessorCount );
printf("\t\tFrequencia de Clock = %d\n", dev_prop.clockRate );
printf("\t\tTamanho do Warp = %d\n", dev_prop.warpSize );
}
return 0;
} | .file "tmpxft_000005ef_00000000-6_GPUinfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Numero de devices (GPU) = %d\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\tDevice (%d)\n"
.LC2:
.string "\t\tNumero maximo de Bloco\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n"
.align 8
.LC4:
.string "\t\tNumero maximo de Threads por Bloco = %d\n"
.align 8
.LC5:
.string "\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n"
.section .rodata.str1.1
.LC6:
.string "\t\tFrequencia de Clock = %d\n"
.LC7:
.string "\t\tTamanho do Warp = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %rbp
leaq .LC4(%rip), %r12
.L5:
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Exemplo para o curso de Super Computacao
// Criado por: Luciano P. Soares (10 de Abril de 2018)
#include <stdio.h>
#include <stdlib.h>
//#include <cuda.h>
//#include <cuda_runtime.h>
/* Informacoes da GPU */
int main() {
int dev_count;
cudaGetDeviceCount(&dev_count);
printf("Numero de devices (GPU) = %d\n\n", dev_count );
cudaDeviceProp dev_prop;
for (int i = 0; i < dev_count; i++) {
printf("\tDevice (%d)\n", i);
cudaGetDeviceProperties(&dev_prop, i);
printf("\t\tNumero maximo de Bloco\n");
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxGridSize[0],dev_prop.maxGridSize[1],dev_prop.maxGridSize[2] );
printf("\t\tNumero maximo de Threads por Bloco = %d\n", dev_prop.maxThreadsPerBlock );
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxThreadsDim[0],dev_prop.maxThreadsDim[1],dev_prop.maxThreadsDim[2] );
printf("\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n", dev_prop.multiProcessorCount );
printf("\t\tFrequencia de Clock = %d\n", dev_prop.clockRate );
printf("\t\tTamanho do Warp = %d\n", dev_prop.warpSize );
}
return 0;
} | // Exemplo para o curso de Super Computacao
// Criado por: Luciano P. Soares (10 de Abril de 2018)
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
//#include <cuda.h>
//#include <cuda_runtime.h>
/* Informacoes da GPU */
int main() {
int dev_count;
hipGetDeviceCount(&dev_count);
printf("Numero de devices (GPU) = %d\n\n", dev_count );
hipDeviceProp_t dev_prop;
for (int i = 0; i < dev_count; i++) {
printf("\tDevice (%d)\n", i);
hipGetDeviceProperties(&dev_prop, i);
printf("\t\tNumero maximo de Bloco\n");
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxGridSize[0],dev_prop.maxGridSize[1],dev_prop.maxGridSize[2] );
printf("\t\tNumero maximo de Threads por Bloco = %d\n", dev_prop.maxThreadsPerBlock );
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxThreadsDim[0],dev_prop.maxThreadsDim[1],dev_prop.maxThreadsDim[2] );
printf("\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n", dev_prop.multiProcessorCount );
printf("\t\tFrequencia de Clock = %d\n", dev_prop.clockRate );
printf("\t\tTamanho do Warp = %d\n", dev_prop.warpSize );
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Exemplo para o curso de Super Computacao
// Criado por: Luciano P. Soares (10 de Abril de 2018)
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
//#include <cuda.h>
//#include <cuda_runtime.h>
/* Informacoes da GPU */
int main() {
int dev_count;
hipGetDeviceCount(&dev_count);
printf("Numero de devices (GPU) = %d\n\n", dev_count );
hipDeviceProp_t dev_prop;
for (int i = 0; i < dev_count; i++) {
printf("\tDevice (%d)\n", i);
hipGetDeviceProperties(&dev_prop, i);
printf("\t\tNumero maximo de Bloco\n");
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxGridSize[0],dev_prop.maxGridSize[1],dev_prop.maxGridSize[2] );
printf("\t\tNumero maximo de Threads por Bloco = %d\n", dev_prop.maxThreadsPerBlock );
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxThreadsDim[0],dev_prop.maxThreadsDim[1],dev_prop.maxThreadsDim[2] );
printf("\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n", dev_prop.multiProcessorCount );
printf("\t\tFrequencia de Clock = %d\n", dev_prop.clockRate );
printf("\t\tTamanho do Warp = %d\n", dev_prop.warpSize );
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Exemplo para o curso de Super Computacao
// Criado por: Luciano P. Soares (10 de Abril de 2018)
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
//#include <cuda.h>
//#include <cuda_runtime.h>
/* Informacoes da GPU */
int main() {
int dev_count;
hipGetDeviceCount(&dev_count);
printf("Numero de devices (GPU) = %d\n\n", dev_count );
hipDeviceProp_t dev_prop;
for (int i = 0; i < dev_count; i++) {
printf("\tDevice (%d)\n", i);
hipGetDeviceProperties(&dev_prop, i);
printf("\t\tNumero maximo de Bloco\n");
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxGridSize[0],dev_prop.maxGridSize[1],dev_prop.maxGridSize[2] );
printf("\t\tNumero maximo de Threads por Bloco = %d\n", dev_prop.maxThreadsPerBlock );
printf("\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n", dev_prop.maxThreadsDim[0],dev_prop.maxThreadsDim[1],dev_prop.maxThreadsDim[2] );
printf("\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n", dev_prop.multiProcessorCount );
printf("\t\tFrequencia de Clock = %d\n", dev_prop.clockRate );
printf("\t\tTamanho do Warp = %d\n", dev_prop.warpSize );
}
return 0;
} | .text
.file "GPUinfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.Lstr, %edi
callq puts@PLT
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Numero de devices (GPU) = %d\n\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\tDevice (%d)\n"
.size .L.str.1, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n"
.size .L.str.3, 47
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\t\tNumero maximo de Threads por Bloco = %d\n"
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n"
.size .L.str.5, 57
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\t\tFrequencia de Clock = %d\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\t\tTamanho do Warp = %d\n"
.size .L.str.7, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\t\tNumero maximo de Bloco"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000005ef_00000000-6_GPUinfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Numero de devices (GPU) = %d\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\tDevice (%d)\n"
.LC2:
.string "\t\tNumero maximo de Bloco\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n"
.align 8
.LC4:
.string "\t\tNumero maximo de Threads por Bloco = %d\n"
.align 8
.LC5:
.string "\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n"
.section .rodata.str1.1
.LC6:
.string "\t\tFrequencia de Clock = %d\n"
.LC7:
.string "\t\tTamanho do Warp = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %rbp
leaq .LC4(%rip), %r12
.L5:
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GPUinfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.Lstr, %edi
callq puts@PLT
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Numero de devices (GPU) = %d\n\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\tDevice (%d)\n"
.size .L.str.1, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\t\t\t Dimensao maxima em x = %d, y = %d, z = %d\n"
.size .L.str.3, 47
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\t\tNumero maximo de Threads por Bloco = %d\n"
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\t\tNumero maximo de Streaming Multiprocessors (SMs) = %d\n"
.size .L.str.5, 57
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\t\tFrequencia de Clock = %d\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\t\tTamanho do Warp = %d\n"
.size .L.str.7, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\t\tNumero maximo de Bloco"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
***** vecadd.cu *****
CUDA program to add two vectors.
Compile: nvcc -o vecadd vecadd.cu
Usage: vecadd [N], where N is vector length
Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.
Modifications:
*/
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;
// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
for ( int i = 0; i < n; i++ )
c[i] = a[i] + b[i];
}
// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if ( i < n ) c[i] = a[i] + b[i];
}
// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
for ( int i = 0; i < n; i++ )
array[i] = rand() % n;
}
int main( int argc, char** argv )
{
int n = 1024;
if ( argc > 1 ) n = atoi( argv[1] );
// alloc host memory for vectors a, b, c
int size = n * sizeof( int );
int *a = ( int * )malloc( size );
int *b = ( int * )malloc( size );
int *c_seq = ( int * )malloc( size );
int *c_par = ( int * )malloc( size );
// fill arrays a and b with random ints
srand( time( NULL ) );
random_ints( a, n );
random_ints( b, n );
// add vectors sequentially
auto c = chrono::system_clock::now();
add_seq( a, b, c_seq, n );
chrono::duration<double> d_cpu = chrono::system_clock::now() - c;
// alloc device memory for vectors a, b, c
int *d_a, *d_b, *d_c;
cudaMalloc( ( void ** )&d_a, size );
cudaMalloc( ( void ** )&d_b, size );
cudaMalloc( ( void ** )&d_c, size );
// copy vectors a and b to device
cudaMemcpy( d_a, a, size, cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, size, cudaMemcpyHostToDevice );
// launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
int nThreads = 64; // should be multiple of 32 (up to 1024)
int nBlocks = ( n + nThreads - 1 ) / nThreads;
c = chrono::system_clock::now();
add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
chrono::duration<double> d_gpu = chrono::system_clock::now() - c;
// copy vector sum back to host
cudaMemcpy( c_par, d_c, size, cudaMemcpyDeviceToHost );
#if 0
cout << "\na: ";
for ( int i = 0; i < n; i++ ) cout << " " << a[i];
cout << "\nb: ";
for ( int i = 0; i < n; i++ ) cout << " " << b[i];
cout << "\nc_seq:";
for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
cout << "\nc_par:";
for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
#endif
cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";
// cleanup
free( a ); free( b ); free( c_seq ); free( c_par );
cudaFree( d_a ); cudaFree( d_b ); cudaFree( d_c );
return 0;
} | code for sm_80
Function : _Z7add_parPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
***** vecadd.cu *****
CUDA program to add two vectors.
Compile: nvcc -o vecadd vecadd.cu
Usage: vecadd [N], where N is vector length
Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.
Modifications:
*/
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;
// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
for ( int i = 0; i < n; i++ )
c[i] = a[i] + b[i];
}
// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if ( i < n ) c[i] = a[i] + b[i];
}
// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
for ( int i = 0; i < n; i++ )
array[i] = rand() % n;
}
int main( int argc, char** argv )
{
int n = 1024;
if ( argc > 1 ) n = atoi( argv[1] );
// alloc host memory for vectors a, b, c
int size = n * sizeof( int );
int *a = ( int * )malloc( size );
int *b = ( int * )malloc( size );
int *c_seq = ( int * )malloc( size );
int *c_par = ( int * )malloc( size );
// fill arrays a and b with random ints
srand( time( NULL ) );
random_ints( a, n );
random_ints( b, n );
// add vectors sequentially
auto c = chrono::system_clock::now();
add_seq( a, b, c_seq, n );
chrono::duration<double> d_cpu = chrono::system_clock::now() - c;
// alloc device memory for vectors a, b, c
int *d_a, *d_b, *d_c;
cudaMalloc( ( void ** )&d_a, size );
cudaMalloc( ( void ** )&d_b, size );
cudaMalloc( ( void ** )&d_c, size );
// copy vectors a and b to device
cudaMemcpy( d_a, a, size, cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, size, cudaMemcpyHostToDevice );
// launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
int nThreads = 64; // should be multiple of 32 (up to 1024)
int nBlocks = ( n + nThreads - 1 ) / nThreads;
c = chrono::system_clock::now();
add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
chrono::duration<double> d_gpu = chrono::system_clock::now() - c;
// copy vector sum back to host
cudaMemcpy( c_par, d_c, size, cudaMemcpyDeviceToHost );
#if 0
cout << "\na: ";
for ( int i = 0; i < n; i++ ) cout << " " << a[i];
cout << "\nb: ";
for ( int i = 0; i < n; i++ ) cout << " " << b[i];
cout << "\nc_seq:";
for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
cout << "\nc_par:";
for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
#endif
cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";
// cleanup
free( a ); free( b ); free( c_seq ); free( c_par );
cudaFree( d_a ); cudaFree( d_b ); cudaFree( d_c );
return 0;
} | .file "tmpxft_0001ec44_00000000-6_vecadd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7add_seqPiS_S_i
.type _Z7add_seqPiS_S_i, @function
_Z7add_seqPiS_S_i:
.LFB3768:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3768:
.size _Z7add_seqPiS_S_i, .-_Z7add_seqPiS_S_i
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3769:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq (%rdi,%rax,4), %r12
.L9:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3769:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
.type _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i, @function
_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i:
.LFB3797:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7add_parPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i, .-_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
.globl _Z7add_parPiS_S_i
.type _Z7add_parPiS_S_i, @function
_Z7add_parPiS_S_i:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z7add_parPiS_S_i, .-_Z7add_parPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n\nBenchmarks: CPU "
.LC2:
.string " sec, GPU "
.LC3:
.string " sec\n\n"
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1024, %ebp
cmpl $1, %edi
jg .L29
.L24:
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z11random_intsPii
movl %ebp, %esi
movq %r12, %rdi
call _Z11random_intsPii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
movl %ebp, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z7add_seqPiS_S_i
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
movl $64, 60(%rsp)
movl $1, 64(%rsp)
leal 126(%rbp), %eax
movl %ebp, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L24
.L30:
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7add_parPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_parPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
***** vecadd.cu *****
CUDA program to add two vectors.
Compile: nvcc -o vecadd vecadd.cu
Usage: vecadd [N], where N is vector length
Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.
Modifications:
*/
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;
// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
for ( int i = 0; i < n; i++ )
c[i] = a[i] + b[i];
}
// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if ( i < n ) c[i] = a[i] + b[i];
}
// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
for ( int i = 0; i < n; i++ )
array[i] = rand() % n;
}
int main( int argc, char** argv )
{
int n = 1024;
if ( argc > 1 ) n = atoi( argv[1] );
// alloc host memory for vectors a, b, c
int size = n * sizeof( int );
int *a = ( int * )malloc( size );
int *b = ( int * )malloc( size );
int *c_seq = ( int * )malloc( size );
int *c_par = ( int * )malloc( size );
// fill arrays a and b with random ints
srand( time( NULL ) );
random_ints( a, n );
random_ints( b, n );
// add vectors sequentially
auto c = chrono::system_clock::now();
add_seq( a, b, c_seq, n );
chrono::duration<double> d_cpu = chrono::system_clock::now() - c;
// alloc device memory for vectors a, b, c
int *d_a, *d_b, *d_c;
cudaMalloc( ( void ** )&d_a, size );
cudaMalloc( ( void ** )&d_b, size );
cudaMalloc( ( void ** )&d_c, size );
// copy vectors a and b to device
cudaMemcpy( d_a, a, size, cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, size, cudaMemcpyHostToDevice );
// launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
int nThreads = 64; // should be multiple of 32 (up to 1024)
int nBlocks = ( n + nThreads - 1 ) / nThreads;
c = chrono::system_clock::now();
add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
chrono::duration<double> d_gpu = chrono::system_clock::now() - c;
// copy vector sum back to host
cudaMemcpy( c_par, d_c, size, cudaMemcpyDeviceToHost );
#if 0
cout << "\na: ";
for ( int i = 0; i < n; i++ ) cout << " " << a[i];
cout << "\nb: ";
for ( int i = 0; i < n; i++ ) cout << " " << b[i];
cout << "\nc_seq:";
for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
cout << "\nc_par:";
for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
#endif
cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";
// cleanup
free( a ); free( b ); free( c_seq ); free( c_par );
cudaFree( d_a ); cudaFree( d_b ); cudaFree( d_c );
return 0;
} | /*
***** vecadd.cu *****
CUDA program to add two vectors.
Compile: nvcc -o vecadd vecadd.cu
Usage: vecadd [N], where N is vector length
Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.
Modifications:
*/
#include <hip/hip_runtime.h>
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;
// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
for ( int i = 0; i < n; i++ )
c[i] = a[i] + b[i];
}
// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if ( i < n ) c[i] = a[i] + b[i];
}
// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
for ( int i = 0; i < n; i++ )
array[i] = rand() % n;
}
int main( int argc, char** argv )
{
int n = 1024;
if ( argc > 1 ) n = atoi( argv[1] );
// alloc host memory for vectors a, b, c
int size = n * sizeof( int );
int *a = ( int * )malloc( size );
int *b = ( int * )malloc( size );
int *c_seq = ( int * )malloc( size );
int *c_par = ( int * )malloc( size );
// fill arrays a and b with random ints
srand( time( NULL ) );
random_ints( a, n );
random_ints( b, n );
// add vectors sequentially
auto c = chrono::system_clock::now();
add_seq( a, b, c_seq, n );
chrono::duration<double> d_cpu = chrono::system_clock::now() - c;
// alloc device memory for vectors a, b, c
int *d_a, *d_b, *d_c;
hipMalloc( ( void ** )&d_a, size );
hipMalloc( ( void ** )&d_b, size );
hipMalloc( ( void ** )&d_c, size );
// copy vectors a and b to device
hipMemcpy( d_a, a, size, hipMemcpyHostToDevice );
hipMemcpy( d_b, b, size, hipMemcpyHostToDevice );
// launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
int nThreads = 64; // should be multiple of 32 (up to 1024)
int nBlocks = ( n + nThreads - 1 ) / nThreads;
c = chrono::system_clock::now();
add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
chrono::duration<double> d_gpu = chrono::system_clock::now() - c;
// copy vector sum back to host
hipMemcpy( c_par, d_c, size, hipMemcpyDeviceToHost );
#if 0
cout << "\na: ";
for ( int i = 0; i < n; i++ ) cout << " " << a[i];
cout << "\nb: ";
for ( int i = 0; i < n; i++ ) cout << " " << b[i];
cout << "\nc_seq:";
for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
cout << "\nc_par:";
for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
#endif
cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";
// cleanup
free( a ); free( b ); free( c_seq ); free( c_par );
hipFree( d_a ); hipFree( d_b ); hipFree( d_c );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
***** vecadd.cu *****
CUDA program to add two vectors.
Compile: nvcc -o vecadd vecadd.cu
Usage: vecadd [N], where N is vector length
Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.
Modifications:
*/
#include <hip/hip_runtime.h>
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;
// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
for ( int i = 0; i < n; i++ )
c[i] = a[i] + b[i];
}
// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if ( i < n ) c[i] = a[i] + b[i];
}
// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
for ( int i = 0; i < n; i++ )
array[i] = rand() % n;
}
int main( int argc, char** argv )
{
int n = 1024;
if ( argc > 1 ) n = atoi( argv[1] );
// alloc host memory for vectors a, b, c
int size = n * sizeof( int );
int *a = ( int * )malloc( size );
int *b = ( int * )malloc( size );
int *c_seq = ( int * )malloc( size );
int *c_par = ( int * )malloc( size );
// fill arrays a and b with random ints
srand( time( NULL ) );
random_ints( a, n );
random_ints( b, n );
// add vectors sequentially
auto c = chrono::system_clock::now();
add_seq( a, b, c_seq, n );
chrono::duration<double> d_cpu = chrono::system_clock::now() - c;
// alloc device memory for vectors a, b, c
int *d_a, *d_b, *d_c;
hipMalloc( ( void ** )&d_a, size );
hipMalloc( ( void ** )&d_b, size );
hipMalloc( ( void ** )&d_c, size );
// copy vectors a and b to device
hipMemcpy( d_a, a, size, hipMemcpyHostToDevice );
hipMemcpy( d_b, b, size, hipMemcpyHostToDevice );
// launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
int nThreads = 64; // should be multiple of 32 (up to 1024)
int nBlocks = ( n + nThreads - 1 ) / nThreads;
c = chrono::system_clock::now();
add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
chrono::duration<double> d_gpu = chrono::system_clock::now() - c;
// copy vector sum back to host
hipMemcpy( c_par, d_c, size, hipMemcpyDeviceToHost );
#if 0
cout << "\na: ";
for ( int i = 0; i < n; i++ ) cout << " " << a[i];
cout << "\nb: ";
for ( int i = 0; i < n; i++ ) cout << " " << b[i];
cout << "\nc_seq:";
for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
cout << "\nc_par:";
for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
#endif
cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";
// cleanup
free( a ); free( b ); free( c_seq ); free( c_par );
hipFree( d_a ); hipFree( d_b ); hipFree( d_c );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_parPiS_S_i
.globl _Z7add_parPiS_S_i
.p2align 8
.type _Z7add_parPiS_S_i,@function
_Z7add_parPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_parPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_parPiS_S_i, .Lfunc_end0-_Z7add_parPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_parPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7add_parPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
***** vecadd.cu *****
CUDA program to add two vectors.
Compile: nvcc -o vecadd vecadd.cu
Usage: vecadd [N], where N is vector length
Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.
Modifications:
*/
#include <hip/hip_runtime.h>
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;
// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
for ( int i = 0; i < n; i++ )
c[i] = a[i] + b[i];
}
// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if ( i < n ) c[i] = a[i] + b[i];
}
// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
for ( int i = 0; i < n; i++ )
array[i] = rand() % n;
}
int main( int argc, char** argv )
{
int n = 1024;
if ( argc > 1 ) n = atoi( argv[1] );
// alloc host memory for vectors a, b, c
int size = n * sizeof( int );
int *a = ( int * )malloc( size );
int *b = ( int * )malloc( size );
int *c_seq = ( int * )malloc( size );
int *c_par = ( int * )malloc( size );
// fill arrays a and b with random ints
srand( time( NULL ) );
random_ints( a, n );
random_ints( b, n );
// add vectors sequentially
auto c = chrono::system_clock::now();
add_seq( a, b, c_seq, n );
chrono::duration<double> d_cpu = chrono::system_clock::now() - c;
// alloc device memory for vectors a, b, c
int *d_a, *d_b, *d_c;
hipMalloc( ( void ** )&d_a, size );
hipMalloc( ( void ** )&d_b, size );
hipMalloc( ( void ** )&d_c, size );
// copy vectors a and b to device
hipMemcpy( d_a, a, size, hipMemcpyHostToDevice );
hipMemcpy( d_b, b, size, hipMemcpyHostToDevice );
// launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
int nThreads = 64; // should be multiple of 32 (up to 1024)
int nBlocks = ( n + nThreads - 1 ) / nThreads;
c = chrono::system_clock::now();
add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
chrono::duration<double> d_gpu = chrono::system_clock::now() - c;
// copy vector sum back to host
hipMemcpy( c_par, d_c, size, hipMemcpyDeviceToHost );
#if 0
cout << "\na: ";
for ( int i = 0; i < n; i++ ) cout << " " << a[i];
cout << "\nb: ";
for ( int i = 0; i < n; i++ ) cout << " " << b[i];
cout << "\nc_seq:";
for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
cout << "\nc_par:";
for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
#endif
cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";
// cleanup
free( a ); free( b ); free( c_seq ); free( c_par );
hipFree( d_a ); hipFree( d_b ); hipFree( d_c );
return 0;
} | .text
.file "vecadd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7add_seqPiS_S_i # -- Begin function _Z7add_seqPiS_S_i
.p2align 4, 0x90
.type _Z7add_seqPiS_S_i,@function
_Z7add_seqPiS_S_i: # @_Z7add_seqPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7add_seqPiS_S_i, .Lfunc_end0-_Z7add_seqPiS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__add_parPiS_S_i # -- Begin function _Z22__device_stub__add_parPiS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__add_parPiS_S_i,@function
_Z22__device_stub__add_parPiS_S_i: # @_Z22__device_stub__add_parPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7add_parPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__add_parPiS_S_i, .Lfunc_end1-_Z22__device_stub__add_parPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1024, %r13d # imm = 0x400
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB3_2:
leal (,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r13d, %r13d
jle .LBB3_8
# %bb.3: # %.lr.ph.preheader.i
movl %r13d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r13d
movl %edx, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r15
jne .LBB3_4
# %bb.5: # %_Z11random_intsPii.exit
testl %r13d, %r13d
jle .LBB3_8
# %bb.6: # %.lr.ph.preheader.i36
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i38
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r13d
movl %edx, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r15
jne .LBB3_7
.LBB3_8: # %_Z11random_intsPii.exit42
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 8(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 63(%r13), %eax
leal 126(%r13), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $6, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 56(%rsp) # 8-byte Spill
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rbp
orq $64, %rdx
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r13d, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7add_parPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
subq 8(%rsp), %r15 # 8-byte Folded Reload
cvtsi2sd %r15, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 56(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rsi
movq 64(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_parPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7add_parPiS_S_i,@object # @_Z7add_parPiS_S_i
.section .rodata,"a",@progbits
.globl _Z7add_parPiS_S_i
.p2align 3, 0x0
_Z7add_parPiS_S_i:
.quad _Z22__device_stub__add_parPiS_S_i
.size _Z7add_parPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nBenchmarks: CPU "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " sec, GPU "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " sec\n\n"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7add_parPiS_S_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_parPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7add_parPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7add_parPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_parPiS_S_i
.globl _Z7add_parPiS_S_i
.p2align 8
.type _Z7add_parPiS_S_i,@function
_Z7add_parPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_parPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_parPiS_S_i, .Lfunc_end0-_Z7add_parPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_parPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7add_parPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001ec44_00000000-6_vecadd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7add_seqPiS_S_i
.type _Z7add_seqPiS_S_i, @function
_Z7add_seqPiS_S_i:
.LFB3768:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3768:
.size _Z7add_seqPiS_S_i, .-_Z7add_seqPiS_S_i
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3769:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq (%rdi,%rax,4), %r12
.L9:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3769:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
.type _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i, @function
_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i:
.LFB3797:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7add_parPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i, .-_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
.globl _Z7add_parPiS_S_i
.type _Z7add_parPiS_S_i, @function
_Z7add_parPiS_S_i:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z7add_parPiS_S_i, .-_Z7add_parPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n\nBenchmarks: CPU "
.LC2:
.string " sec, GPU "
.LC3:
.string " sec\n\n"
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1024, %ebp
cmpl $1, %edi
jg .L29
.L24:
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z11random_intsPii
movl %ebp, %esi
movq %r12, %rdi
call _Z11random_intsPii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
movl %ebp, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z7add_seqPiS_S_i
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
movl $64, 60(%rsp)
movl $1, 64(%rsp)
leal 126(%rbp), %eax
movl %ebp, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L24
.L30:
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7add_parPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_parPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecadd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7add_seqPiS_S_i # -- Begin function _Z7add_seqPiS_S_i
.p2align 4, 0x90
.type _Z7add_seqPiS_S_i,@function
_Z7add_seqPiS_S_i: # @_Z7add_seqPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7add_seqPiS_S_i, .Lfunc_end0-_Z7add_seqPiS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__add_parPiS_S_i # -- Begin function _Z22__device_stub__add_parPiS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__add_parPiS_S_i,@function
_Z22__device_stub__add_parPiS_S_i: # @_Z22__device_stub__add_parPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7add_parPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__add_parPiS_S_i, .Lfunc_end1-_Z22__device_stub__add_parPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1024, %r13d # imm = 0x400
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB3_2:
leal (,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r13d, %r13d
jle .LBB3_8
# %bb.3: # %.lr.ph.preheader.i
movl %r13d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r13d
movl %edx, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r15
jne .LBB3_4
# %bb.5: # %_Z11random_intsPii.exit
testl %r13d, %r13d
jle .LBB3_8
# %bb.6: # %.lr.ph.preheader.i36
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i38
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r13d
movl %edx, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r15
jne .LBB3_7
.LBB3_8: # %_Z11random_intsPii.exit42
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 8(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 63(%r13), %eax
leal 126(%r13), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $6, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 56(%rsp) # 8-byte Spill
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rbp
orq $64, %rdx
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r13d, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7add_parPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
subq 8(%rsp), %r15 # 8-byte Folded Reload
cvtsi2sd %r15, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 56(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rsi
movq 64(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_parPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7add_parPiS_S_i,@object # @_Z7add_parPiS_S_i
.section .rodata,"a",@progbits
.globl _Z7add_parPiS_S_i
.p2align 3, 0x0
_Z7add_parPiS_S_i:
.quad _Z22__device_stub__add_parPiS_S_i
.size _Z7add_parPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nBenchmarks: CPU "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " sec, GPU "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " sec\n\n"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7add_parPiS_S_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_parPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7add_parPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void chooseDistance ( const int nwl, const int *kex, const float *didi11, float *didi1 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
didi1[i] = didi11[i+kex[i]*nwl];
}
} | code for sm_80
Function : _Z14chooseDistanceiPKiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R4, R3, c[0x0][0x160], R6 ; /* 0x0000580003047a24 */
/* 0x004fc800078e0206 */
/*00b0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0207 */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fca00078e0207 */
/*00e0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void chooseDistance ( const int nwl, const int *kex, const float *didi11, float *didi1 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
didi1[i] = didi11[i+kex[i]*nwl];
}
} | .file "tmpxft_00193ab2_00000000-6_chooseDistance.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf
.type _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf, @function
_Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14chooseDistanceiPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf, .-_Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf
.globl _Z14chooseDistanceiPKiPKfPf
.type _Z14chooseDistanceiPKiPKfPf, @function
_Z14chooseDistanceiPKiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14chooseDistanceiPKiPKfPf, .-_Z14chooseDistanceiPKiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14chooseDistanceiPKiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14chooseDistanceiPKiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void chooseDistance ( const int nwl, const int *kex, const float *didi11, float *didi1 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
didi1[i] = didi11[i+kex[i]*nwl];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chooseDistance ( const int nwl, const int *kex, const float *didi11, float *didi1 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
didi1[i] = didi11[i+kex[i]*nwl];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chooseDistance ( const int nwl, const int *kex, const float *didi11, float *didi1 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
didi1[i] = didi11[i+kex[i]*nwl];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14chooseDistanceiPKiPKfPf
.globl _Z14chooseDistanceiPKiPKfPf
.p2align 8
.type _Z14chooseDistanceiPKiPKfPf,@function
_Z14chooseDistanceiPKiPKfPf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14chooseDistanceiPKiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14chooseDistanceiPKiPKfPf, .Lfunc_end0-_Z14chooseDistanceiPKiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14chooseDistanceiPKiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14chooseDistanceiPKiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chooseDistance ( const int nwl, const int *kex, const float *didi11, float *didi1 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
didi1[i] = didi11[i+kex[i]*nwl];
}
} | .text
.file "chooseDistance.hip"
.globl _Z29__device_stub__chooseDistanceiPKiPKfPf # -- Begin function _Z29__device_stub__chooseDistanceiPKiPKfPf
.p2align 4, 0x90
.type _Z29__device_stub__chooseDistanceiPKiPKfPf,@function
_Z29__device_stub__chooseDistanceiPKiPKfPf: # @_Z29__device_stub__chooseDistanceiPKiPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14chooseDistanceiPKiPKfPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__chooseDistanceiPKiPKfPf, .Lfunc_end0-_Z29__device_stub__chooseDistanceiPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14chooseDistanceiPKiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14chooseDistanceiPKiPKfPf,@object # @_Z14chooseDistanceiPKiPKfPf
.section .rodata,"a",@progbits
.globl _Z14chooseDistanceiPKiPKfPf
.p2align 3, 0x0
_Z14chooseDistanceiPKiPKfPf:
.quad _Z29__device_stub__chooseDistanceiPKiPKfPf
.size _Z14chooseDistanceiPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14chooseDistanceiPKiPKfPf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__chooseDistanceiPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14chooseDistanceiPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14chooseDistanceiPKiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R4, R3, c[0x0][0x160], R6 ; /* 0x0000580003047a24 */
/* 0x004fc800078e0206 */
/*00b0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0207 */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fca00078e0207 */
/*00e0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14chooseDistanceiPKiPKfPf
.globl _Z14chooseDistanceiPKiPKfPf
.p2align 8
.type _Z14chooseDistanceiPKiPKfPf,@function
_Z14chooseDistanceiPKiPKfPf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14chooseDistanceiPKiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14chooseDistanceiPKiPKfPf, .Lfunc_end0-_Z14chooseDistanceiPKiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14chooseDistanceiPKiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14chooseDistanceiPKiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193ab2_00000000-6_chooseDistance.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf
.type _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf, @function
_Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14chooseDistanceiPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf, .-_Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf
.globl _Z14chooseDistanceiPKiPKfPf
.type _Z14chooseDistanceiPKiPKfPf, @function
_Z14chooseDistanceiPKiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14chooseDistanceiPKiPKfPfiPKiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14chooseDistanceiPKiPKfPf, .-_Z14chooseDistanceiPKiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14chooseDistanceiPKiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14chooseDistanceiPKiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "chooseDistance.hip"
.globl _Z29__device_stub__chooseDistanceiPKiPKfPf # -- Begin function _Z29__device_stub__chooseDistanceiPKiPKfPf
.p2align 4, 0x90
.type _Z29__device_stub__chooseDistanceiPKiPKfPf,@function
_Z29__device_stub__chooseDistanceiPKiPKfPf: # @_Z29__device_stub__chooseDistanceiPKiPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14chooseDistanceiPKiPKfPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__chooseDistanceiPKiPKfPf, .Lfunc_end0-_Z29__device_stub__chooseDistanceiPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14chooseDistanceiPKiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14chooseDistanceiPKiPKfPf,@object # @_Z14chooseDistanceiPKiPKfPf
.section .rodata,"a",@progbits
.globl _Z14chooseDistanceiPKiPKfPf
.p2align 3, 0x0
_Z14chooseDistanceiPKiPKfPf:
.quad _Z29__device_stub__chooseDistanceiPKiPKfPf
.size _Z14chooseDistanceiPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14chooseDistanceiPKiPKfPf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__chooseDistanceiPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14chooseDistanceiPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_2dfd(float *g_u1, float *g_u2, const int nx, const int iStart, const int iEnd)
{
// global to line index
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
// smem idx for current point
unsigned int stx = threadIdx.x + NPAD;
unsigned int idx = ix + iStart * nx;
// shared memory for x dimension
__shared__ float line[BDIMX + NPAD2];
// a coefficient related to physical properties
const float alpha = 0.12f;
// register for y value
float yval[9];
for (int i = 0; i < 8; i++) yval[i] = g_u2[idx + (i - 4) * nx];
// skip for the bottom most y value
int iskip = NPAD * nx;
#pragma unroll 9
for (int iy = iStart; iy < iEnd; iy++)
{
// get yval[8] here
yval[8] = g_u2[idx + iskip];
// read halo part
if(threadIdx.x < NPAD)
{
line[threadIdx.x] = g_u2[idx - NPAD];
line[stx + BDIMX] = g_u2[idx + BDIMX];
}
line[stx] = yval[4];
__syncthreads();
// 8rd fd operator
if ( (ix >= NPAD) && (ix < nx - NPAD) )
{
// center point
float tmp = coef[0] * line[stx] * 2.0f;
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * ( line[stx - d] + line[stx + d]);
}
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * (yval[4 - d] + yval[4 + d]);
}
// time dimension
g_u1[idx] = yval[4] + yval[4] - g_u1[idx] + alpha * tmp;
}
#pragma unroll 8
for (int i = 0; i < 8 ; i++)
{
yval[i] = yval[i + 1];
}
// advancd on global idx
idx += nx;
__syncthreads();
}
} | .file "tmpxft_001a5ef9_00000000-6_kernel_2dfd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii
.type _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii, @function
_Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kernel_2dfdPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii, .-_Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii
.globl _Z11kernel_2dfdPfS_iii
.type _Z11kernel_2dfdPfS_iii, @function
_Z11kernel_2dfdPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kernel_2dfdPfS_iii, .-_Z11kernel_2dfdPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kernel_2dfdPfS_iii"
.LC1:
.string "coef"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kernel_2dfdPfS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4coef(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4coef
.comm _ZL4coef,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_2dfd(float *g_u1, float *g_u2, const int nx, const int iStart, const int iEnd)
{
// global to line index
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
// smem idx for current point
unsigned int stx = threadIdx.x + NPAD;
unsigned int idx = ix + iStart * nx;
// shared memory for x dimension
__shared__ float line[BDIMX + NPAD2];
// a coefficient related to physical properties
const float alpha = 0.12f;
// register for y value
float yval[9];
for (int i = 0; i < 8; i++) yval[i] = g_u2[idx + (i - 4) * nx];
// skip for the bottom most y value
int iskip = NPAD * nx;
#pragma unroll 9
for (int iy = iStart; iy < iEnd; iy++)
{
// get yval[8] here
yval[8] = g_u2[idx + iskip];
// read halo part
if(threadIdx.x < NPAD)
{
line[threadIdx.x] = g_u2[idx - NPAD];
line[stx + BDIMX] = g_u2[idx + BDIMX];
}
line[stx] = yval[4];
__syncthreads();
// 8rd fd operator
if ( (ix >= NPAD) && (ix < nx - NPAD) )
{
// center point
float tmp = coef[0] * line[stx] * 2.0f;
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * ( line[stx - d] + line[stx + d]);
}
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * (yval[4 - d] + yval[4 + d]);
}
// time dimension
g_u1[idx] = yval[4] + yval[4] - g_u1[idx] + alpha * tmp;
}
#pragma unroll 8
for (int i = 0; i < 8 ; i++)
{
yval[i] = yval[i + 1];
}
// advancd on global idx
idx += nx;
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_2dfd(float *g_u1, float *g_u2, const int nx, const int iStart, const int iEnd)
{
// global to line index
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
// smem idx for current point
unsigned int stx = threadIdx.x + NPAD;
unsigned int idx = ix + iStart * nx;
// shared memory for x dimension
__shared__ float line[BDIMX + NPAD2];
// a coefficient related to physical properties
const float alpha = 0.12f;
// register for y value
float yval[9];
for (int i = 0; i < 8; i++) yval[i] = g_u2[idx + (i - 4) * nx];
// skip for the bottom most y value
int iskip = NPAD * nx;
#pragma unroll 9
for (int iy = iStart; iy < iEnd; iy++)
{
// get yval[8] here
yval[8] = g_u2[idx + iskip];
// read halo part
if(threadIdx.x < NPAD)
{
line[threadIdx.x] = g_u2[idx - NPAD];
line[stx + BDIMX] = g_u2[idx + BDIMX];
}
line[stx] = yval[4];
__syncthreads();
// 8rd fd operator
if ( (ix >= NPAD) && (ix < nx - NPAD) )
{
// center point
float tmp = coef[0] * line[stx] * 2.0f;
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * ( line[stx - d] + line[stx + d]);
}
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * (yval[4 - d] + yval[4 + d]);
}
// time dimension
g_u1[idx] = yval[4] + yval[4] - g_u1[idx] + alpha * tmp;
}
#pragma unroll 8
for (int i = 0; i < 8 ; i++)
{
yval[i] = yval[i + 1];
}
// advancd on global idx
idx += nx;
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_2dfd(float *g_u1, float *g_u2, const int nx, const int iStart, const int iEnd)
{
// global to line index
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
// smem idx for current point
unsigned int stx = threadIdx.x + NPAD;
unsigned int idx = ix + iStart * nx;
// shared memory for x dimension
__shared__ float line[BDIMX + NPAD2];
// a coefficient related to physical properties
const float alpha = 0.12f;
// register for y value
float yval[9];
for (int i = 0; i < 8; i++) yval[i] = g_u2[idx + (i - 4) * nx];
// skip for the bottom most y value
int iskip = NPAD * nx;
#pragma unroll 9
for (int iy = iStart; iy < iEnd; iy++)
{
// get yval[8] here
yval[8] = g_u2[idx + iskip];
// read halo part
if(threadIdx.x < NPAD)
{
line[threadIdx.x] = g_u2[idx - NPAD];
line[stx + BDIMX] = g_u2[idx + BDIMX];
}
line[stx] = yval[4];
__syncthreads();
// 8rd fd operator
if ( (ix >= NPAD) && (ix < nx - NPAD) )
{
// center point
float tmp = coef[0] * line[stx] * 2.0f;
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * ( line[stx - d] + line[stx + d]);
}
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * (yval[4 - d] + yval[4 + d]);
}
// time dimension
g_u1[idx] = yval[4] + yval[4] - g_u1[idx] + alpha * tmp;
}
#pragma unroll 8
for (int i = 0; i < 8 ; i++)
{
yval[i] = yval[i + 1];
}
// advancd on global idx
idx += nx;
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kernel_2dfdPfS_iii
.globl _Z11kernel_2dfdPfS_iii
.p2align 8
.type _Z11kernel_2dfdPfS_iii,@function
_Z11kernel_2dfdPfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v11, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s7, -4
s_mul_i32 s15, s15, s2
s_mul_i32 s2, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v10, s15, s2, v0
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[10:11]
v_add_nc_u32_e32 v10, s6, v10
s_mov_b32 m0, s2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 8
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
v_movreld_b32_e32 v1, v12
s_cbranch_scc0 .LBB0_1
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s7, s8
s_cbranch_scc1 .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, coef@rel32@lo+4
s_addc_u32 s1, s1, coef@rel32@hi+12
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, coef@rel32@lo+8
s_addc_u32 s11, s11, coef@rel32@hi+16
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, coef@rel32@lo+12
s_addc_u32 s13, s13, coef@rel32@hi+20
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, s15, v0
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, coef@rel32@lo+16
s_addc_u32 s15, s15, coef@rel32@hi+24
s_getpc_b64 s[16:17]
s_add_u32 s16, s16, coef@rel32@lo+20
s_addc_u32 s17, s17, coef@rel32@hi+28
s_clause 0x4
s_load_b32 s9, s[0:1], 0x0
s_load_b32 s10, s[10:11], 0x0
s_load_b32 s11, s[12:13], 0x0
s_load_b32 s12, s[14:15], 0x0
s_load_b32 s13, s[16:17], 0x0
v_lshlrev_b32_e32 v12, 2, v0
s_add_i32 s1, s6, -4
v_cmp_lt_u32_e64 s0, 3, v11
v_cmp_gt_u32_e64 s1, s1, v11
v_cmp_gt_u32_e32 vcc_lo, 4, v0
v_add_nc_u32_e32 v0, 0x50, v12
v_add_nc_u32_e32 v13, 16, v12
v_add_nc_u32_e32 v14, 12, v12
v_add_nc_u32_e32 v15, 20, v12
v_add_nc_u32_e32 v16, 8, v12
v_add_nc_u32_e32 v17, 24, v12
v_add_nc_u32_e32 v18, 4, v12
v_add_nc_u32_e32 v19, 28, v12
v_add_nc_u32_e32 v20, 32, v12
s_add_i32 s15, s7, 4
s_mul_i32 s14, s7, s6
s_and_b32 s1, s0, s1
s_mul_i32 s15, s6, s15
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v11, s6, v11
v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v5
v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
v_dual_mov_b32 v7, v8 :: v_dual_mov_b32 v8, v21
s_add_i32 s7, s7, 1
s_waitcnt_vscnt null, 0x0
s_cmp_ge_i32 s7, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_5:
v_add_nc_u32_e32 v9, s15, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[21:22], 2, v[9:10]
v_add_nc_u32_e32 v9, s14, v11
v_add_co_u32 v21, s0, s4, v21
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s0, s5, v22, s0
global_load_b32 v21, v[21:22], off
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v23, 0 :: v_dual_add_nc_u32 v22, -4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[24:25], 2, v[22:23]
v_add_nc_u32_e32 v22, 16, v9
v_lshlrev_b64 v[22:23], 2, v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v24, s0, s4, v24
v_add_co_ci_u32_e64 v25, s0, s5, v25, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v22, s0, s4, v22
v_add_co_ci_u32_e64 v23, s0, s5, v23, s0
s_clause 0x1
global_load_b32 v24, v[24:25], off
global_load_b32 v22, v[22:23], off
s_waitcnt vmcnt(1)
ds_store_b32 v12, v24
s_waitcnt vmcnt(0)
ds_store_b32 v0, v22
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s16
ds_store_b32 v13, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s16, s1
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[22:23], 2, v[9:10]
v_add_f32_e32 v1, v1, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v22, s0, s2, v22
v_add_co_ci_u32_e64 v23, s0, s3, v23, s0
global_load_b32 v9, v[22:23], off
ds_load_b32 v24, v14
ds_load_b32 v25, v15
ds_load_b32 v26, v13
ds_load_b32 v27, v16
ds_load_b32 v28, v17
ds_load_b32 v29, v18
ds_load_b32 v30, v19
s_waitcnt lgkmcnt(5)
v_add_f32_e32 v24, v24, v25
ds_load_b32 v25, v12
ds_load_b32 v31, v20
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v26, s9, v26 :: v_dual_add_f32 v25, v25, v31
v_mul_f32_e32 v24, s10, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v24, 2.0, v26
v_add_f32_e32 v26, v27, v28
v_fmac_f32_e32 v24, s11, v26
v_add_f32_e32 v26, v29, v30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v24, s12, v26
v_dual_fmac_f32 v24, s13, v25 :: v_dual_add_f32 v25, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v24, s10, v25 :: v_dual_add_f32 v25, v3, v7
v_dual_fmac_f32 v24, s11, v25 :: v_dual_add_f32 v25, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v24, s12, v25
v_fmac_f32_e32 v24, s13, v1
s_waitcnt vmcnt(0)
v_fma_f32 v1, v5, 2.0, -v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v1, 0x3df5c28f, v24
global_store_b32 v[22:23], v1, off
s_branch .LBB0_4
.LBB0_9:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kernel_2dfdPfS_iii
.amdhsa_group_segment_fixed_size 96
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kernel_2dfdPfS_iii, .Lfunc_end0-_Z11kernel_2dfdPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected coef
.type coef,@object
.section .bss,"aw",@nobits
.globl coef
.p2align 4, 0x0
coef:
.zero 20
.size coef, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym coef
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 96
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kernel_2dfdPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11kernel_2dfdPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_2dfd(float *g_u1, float *g_u2, const int nx, const int iStart, const int iEnd)
{
// global to line index
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
// smem idx for current point
unsigned int stx = threadIdx.x + NPAD;
unsigned int idx = ix + iStart * nx;
// shared memory for x dimension
__shared__ float line[BDIMX + NPAD2];
// a coefficient related to physical properties
const float alpha = 0.12f;
// register for y value
float yval[9];
for (int i = 0; i < 8; i++) yval[i] = g_u2[idx + (i - 4) * nx];
// skip for the bottom most y value
int iskip = NPAD * nx;
#pragma unroll 9
for (int iy = iStart; iy < iEnd; iy++)
{
// get yval[8] here
yval[8] = g_u2[idx + iskip];
// read halo part
if(threadIdx.x < NPAD)
{
line[threadIdx.x] = g_u2[idx - NPAD];
line[stx + BDIMX] = g_u2[idx + BDIMX];
}
line[stx] = yval[4];
__syncthreads();
// 8rd fd operator
if ( (ix >= NPAD) && (ix < nx - NPAD) )
{
// center point
float tmp = coef[0] * line[stx] * 2.0f;
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * ( line[stx - d] + line[stx + d]);
}
#pragma unroll
for(int d = 1; d <= 4; d++)
{
tmp += coef[d] * (yval[4 - d] + yval[4 + d]);
}
// time dimension
g_u1[idx] = yval[4] + yval[4] - g_u1[idx] + alpha * tmp;
}
#pragma unroll 8
for (int i = 0; i < 8 ; i++)
{
yval[i] = yval[i + 1];
}
// advancd on global idx
idx += nx;
__syncthreads();
}
} | .text
.file "kernel_2dfd.hip"
.globl _Z26__device_stub__kernel_2dfdPfS_iii # -- Begin function _Z26__device_stub__kernel_2dfdPfS_iii
.p2align 4, 0x90
.type _Z26__device_stub__kernel_2dfdPfS_iii,@function
_Z26__device_stub__kernel_2dfdPfS_iii: # @_Z26__device_stub__kernel_2dfdPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kernel_2dfdPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kernel_2dfdPfS_iii, .Lfunc_end0-_Z26__device_stub__kernel_2dfdPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kernel_2dfdPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $coef, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type coef,@object # @coef
.local coef
.comm coef,20,16
.type _Z11kernel_2dfdPfS_iii,@object # @_Z11kernel_2dfdPfS_iii
.section .rodata,"a",@progbits
.globl _Z11kernel_2dfdPfS_iii
.p2align 3, 0x0
_Z11kernel_2dfdPfS_iii:
.quad _Z26__device_stub__kernel_2dfdPfS_iii
.size _Z11kernel_2dfdPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kernel_2dfdPfS_iii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "coef"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kernel_2dfdPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym coef
.addrsig_sym _Z11kernel_2dfdPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a5ef9_00000000-6_kernel_2dfd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii
.type _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii, @function
_Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kernel_2dfdPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii, .-_Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii
.globl _Z11kernel_2dfdPfS_iii
.type _Z11kernel_2dfdPfS_iii, @function
_Z11kernel_2dfdPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11kernel_2dfdPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kernel_2dfdPfS_iii, .-_Z11kernel_2dfdPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kernel_2dfdPfS_iii"
.LC1:
.string "coef"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kernel_2dfdPfS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4coef(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4coef
.comm _ZL4coef,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_2dfd.hip"
.globl _Z26__device_stub__kernel_2dfdPfS_iii # -- Begin function _Z26__device_stub__kernel_2dfdPfS_iii
.p2align 4, 0x90
.type _Z26__device_stub__kernel_2dfdPfS_iii,@function
_Z26__device_stub__kernel_2dfdPfS_iii: # @_Z26__device_stub__kernel_2dfdPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kernel_2dfdPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kernel_2dfdPfS_iii, .Lfunc_end0-_Z26__device_stub__kernel_2dfdPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kernel_2dfdPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $coef, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type coef,@object # @coef
.local coef
.comm coef,20,16
.type _Z11kernel_2dfdPfS_iii,@object # @_Z11kernel_2dfdPfS_iii
.section .rodata,"a",@progbits
.globl _Z11kernel_2dfdPfS_iii
.p2align 3, 0x0
_Z11kernel_2dfdPfS_iii:
.quad _Z26__device_stub__kernel_2dfdPfS_iii
.size _Z11kernel_2dfdPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kernel_2dfdPfS_iii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "coef"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kernel_2dfdPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym coef
.addrsig_sym _Z11kernel_2dfdPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 2018 Foundation for Research and Technology - Hellas
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0 [1] [1]
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Links:
* ------
* [1] http://www.apache.org/licenses/LICENSE-2.0 [1]
*/
#include <stdio.h>
#include <iostream>
#include <fstream>
using namespace ::std;
int main() {
ifstream fin;
fin.open("/proc/cpuinfo", ios::in);
ofstream fout;
fout.open("new.txt", ios::out);
char ch;
char *model_name, *cpu_cores;
char line[75];
while (fin.get(ch))
{
fin.get(line, 75, '\n');
model_name = strstr(line, "model name");
cpu_cores = strstr(line, "cpu cores");
if (model_name != NULL)
{
fout << "Accelerator type is CPU \n" << model_name << endl;
} else if (cpu_cores != NULL) {
fout << cpu_cores << endl << "--------------------" << endl;
}
}
// Number of CUDA devices
int devCount;
cudaGetDeviceCount(&devCount);
if (devCount > 0)
{
fout << "Accelerator type is NVIDIA GPU" << endl;
fout << "Number of NVIDIA GPUs: " << devCount << endl;
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
fout << "model name " << devProp.name << endl;
fout << "Multi-Processors " << devProp.multiProcessorCount << endl;
cudaSetDevice(i);
}
} else
{
cout << "There is no CUDA device" << endl;
}
fin.close();
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2018 Foundation for Research and Technology - Hellas
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0 [1] [1]
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Links:
* ------
* [1] http://www.apache.org/licenses/LICENSE-2.0 [1]
*/
#include <stdio.h>
#include <iostream>
#include <fstream>
using namespace ::std;
int main() {
ifstream fin;
fin.open("/proc/cpuinfo", ios::in);
ofstream fout;
fout.open("new.txt", ios::out);
char ch;
char *model_name, *cpu_cores;
char line[75];
while (fin.get(ch))
{
fin.get(line, 75, '\n');
model_name = strstr(line, "model name");
cpu_cores = strstr(line, "cpu cores");
if (model_name != NULL)
{
fout << "Accelerator type is CPU \n" << model_name << endl;
} else if (cpu_cores != NULL) {
fout << cpu_cores << endl << "--------------------" << endl;
}
}
// Number of CUDA devices
int devCount;
cudaGetDeviceCount(&devCount);
if (devCount > 0)
{
fout << "Accelerator type is NVIDIA GPU" << endl;
fout << "Number of NVIDIA GPUs: " << devCount << endl;
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
fout << "model name " << devProp.name << endl;
fout << "Multi-Processors " << devProp.multiProcessorCount << endl;
cudaSetDevice(i);
}
} else
{
cout << "There is no CUDA device" << endl;
}
fin.close();
return 0;
} | .file "tmpxft_00187c2e_00000000-6_creatConfig.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "/proc/cpuinfo"
.LC1:
.string "new.txt"
.LC2:
.string "model name"
.LC3:
.string "cpu cores"
.LC4:
.string "Accelerator type is CPU \n"
.LC5:
.string "--------------------"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Accelerator type is NVIDIA GPU"
.section .rodata.str1.1
.LC7:
.string "Number of NVIDIA GPUs: "
.LC8:
.string "model name "
.LC9:
.string "Multi-Processors "
.LC10:
.string "There is no CUDA device"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2200, %rsp
.cfi_def_cfa_offset 2256
movq %fs:40, %rax
movq %rax, 2184(%rsp)
xorl %eax, %eax
leaq 528(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $8, %edx
leaq .LC0(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 16(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq .LC2(%rip), %rbx
leaq .LC3(%rip), %rbp
leaq .LC5(%rip), %r13
leaq .LC4(%rip), %r12
.L6:
leaq 11(%rsp), %rsi
leaq 528(%rsp), %rdi
call _ZNSi3getERc@PLT
jmp .L42
.L53:
leaq 2096(%rsp), %r15
movq %rbx, %rsi
movq %r15, %rdi
call strstr@PLT
movq %rax, %r14
movq %rbp, %rsi
movq %r15, %rdi
call strstr@PLT
movq %rax, %r15
testq %r14, %r14
je .L7
leaq 16(%rsp), %rdi
movl $25, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 16(%rsp), %rdi
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %r14
testq %r14, %r14
je .L43
cmpb $0, 56(%r14)
je .L10
movzbl 67(%r14), %esi
.L11:
movsbl %sil, %esi
leaq 16(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L44
.L43:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L10:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L11
.L44:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L6
.L7:
testq %rax, %rax
je .L6
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 16(%rsp), %rdi
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %r14
testq %r14, %r14
je .L46
cmpb $0, 56(%r14)
je .L15
movzbl 67(%r14), %esi
.L16:
movsbl %sil, %esi
leaq 16(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L47
.L46:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L15:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L47:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %r14
movl $20, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L49
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L50
.L49:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L50:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L6
.L42:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L52
leaq 2096(%rsp), %rsi
leaq 528(%rsp), %rdi
movl $10, %ecx
movl $75, %edx
call _ZNSi3getEPclc@PLT
jmp .L53
.L52:
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L22
leaq 16(%rsp), %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L23
movl $0, %ebp
leaq 1056(%rsp), %r14
leaq 16(%rsp), %r12
leaq .LC9(%rip), %r15
jmp .L32
.L60:
movl $17, %edx
leaq .LC8(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L54
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L55
.L54:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L38:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L34:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2184(%rsp), %rax
subq %fs:40, %rax
je .L35
call __stack_chk_fail@PLT
.L56:
call __stack_chk_fail@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L55:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $17, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 1444(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L57
cmpb $0, 56(%r13)
je .L30
movzbl 67(%r13), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L58
.L57:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L30:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L58:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl %ebp, %edi
call cudaSetDevice@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L23
.L32:
movl %ebp, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
jmp .L60
.L22:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L23:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE2:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $2200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L34
.L35:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L37-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 .L38-.LFB3800
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2018 Foundation for Research and Technology - Hellas
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0 [1] [1]
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Links:
* ------
* [1] http://www.apache.org/licenses/LICENSE-2.0 [1]
*/
#include <stdio.h>
#include <iostream>
#include <fstream>
using namespace ::std;
int main() {
ifstream fin;
fin.open("/proc/cpuinfo", ios::in);
ofstream fout;
fout.open("new.txt", ios::out);
char ch;
char *model_name, *cpu_cores;
char line[75];
while (fin.get(ch))
{
fin.get(line, 75, '\n');
model_name = strstr(line, "model name");
cpu_cores = strstr(line, "cpu cores");
if (model_name != NULL)
{
fout << "Accelerator type is CPU \n" << model_name << endl;
} else if (cpu_cores != NULL) {
fout << cpu_cores << endl << "--------------------" << endl;
}
}
// Number of CUDA devices
int devCount;
cudaGetDeviceCount(&devCount);
if (devCount > 0)
{
fout << "Accelerator type is NVIDIA GPU" << endl;
fout << "Number of NVIDIA GPUs: " << devCount << endl;
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
fout << "model name " << devProp.name << endl;
fout << "Multi-Processors " << devProp.multiProcessorCount << endl;
cudaSetDevice(i);
}
} else
{
cout << "There is no CUDA device" << endl;
}
fin.close();
return 0;
} | /*
* Copyright 2018 Foundation for Research and Technology - Hellas
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0 [1] [1]
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Links:
* ------
* [1] http://www.apache.org/licenses/LICENSE-2.0 [1]
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
using namespace ::std;
int main() {
ifstream fin;
fin.open("/proc/cpuinfo", ios::in);
ofstream fout;
fout.open("new.txt", ios::out);
char ch;
char *model_name, *cpu_cores;
char line[75];
while (fin.get(ch))
{
fin.get(line, 75, '\n');
model_name = strstr(line, "model name");
cpu_cores = strstr(line, "cpu cores");
if (model_name != NULL)
{
fout << "Accelerator type is CPU \n" << model_name << endl;
} else if (cpu_cores != NULL) {
fout << cpu_cores << endl << "--------------------" << endl;
}
}
// Number of CUDA devices
int devCount;
hipGetDeviceCount(&devCount);
if (devCount > 0)
{
fout << "Accelerator type is NVIDIA GPU" << endl;
fout << "Number of NVIDIA GPUs: " << devCount << endl;
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
fout << "model name " << devProp.name << endl;
fout << "Multi-Processors " << devProp.multiProcessorCount << endl;
hipSetDevice(i);
}
} else
{
cout << "There is no CUDA device" << endl;
}
fin.close();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 2018 Foundation for Research and Technology - Hellas
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0 [1] [1]
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Links:
* ------
* [1] http://www.apache.org/licenses/LICENSE-2.0 [1]
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
using namespace ::std;
int main() {
ifstream fin;
fin.open("/proc/cpuinfo", ios::in);
ofstream fout;
fout.open("new.txt", ios::out);
char ch;
char *model_name, *cpu_cores;
char line[75];
while (fin.get(ch))
{
fin.get(line, 75, '\n');
model_name = strstr(line, "model name");
cpu_cores = strstr(line, "cpu cores");
if (model_name != NULL)
{
fout << "Accelerator type is CPU \n" << model_name << endl;
} else if (cpu_cores != NULL) {
fout << cpu_cores << endl << "--------------------" << endl;
}
}
// Number of CUDA devices
int devCount;
hipGetDeviceCount(&devCount);
if (devCount > 0)
{
fout << "Accelerator type is NVIDIA GPU" << endl;
fout << "Number of NVIDIA GPUs: " << devCount << endl;
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
fout << "model name " << devProp.name << endl;
fout << "Multi-Processors " << devProp.multiProcessorCount << endl;
hipSetDevice(i);
}
} else
{
cout << "There is no CUDA device" << endl;
}
fin.close();
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 2018 Foundation for Research and Technology - Hellas
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0 [1] [1]
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Links:
* ------
* [1] http://www.apache.org/licenses/LICENSE-2.0 [1]
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
using namespace ::std;
int main() {
ifstream fin;
fin.open("/proc/cpuinfo", ios::in);
ofstream fout;
fout.open("new.txt", ios::out);
char ch;
char *model_name, *cpu_cores;
char line[75];
while (fin.get(ch))
{
fin.get(line, 75, '\n');
model_name = strstr(line, "model name");
cpu_cores = strstr(line, "cpu cores");
if (model_name != NULL)
{
fout << "Accelerator type is CPU \n" << model_name << endl;
} else if (cpu_cores != NULL) {
fout << cpu_cores << endl << "--------------------" << endl;
}
}
// Number of CUDA devices
int devCount;
hipGetDeviceCount(&devCount);
if (devCount > 0)
{
fout << "Accelerator type is NVIDIA GPU" << endl;
fout << "Number of NVIDIA GPUs: " << devCount << endl;
// Iterate through devices
for (int i = 0; i < devCount; ++i)
{
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
fout << "model name " << devProp.name << endl;
fout << "Multi-Processors " << devProp.multiProcessorCount << endl;
hipSetDevice(i);
}
} else
{
cout << "There is no CUDA device" << endl;
}
fin.close();
return 0;
} | .text
.file "creatConfig.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2600, %rsp # imm = 0xA28
.cfi_def_cfa_offset 2656
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 520(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 536(%rsp), %rdi
.Ltmp0:
movl $.L.str, %esi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 520(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB0_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB0_3: # %.invoke
.Ltmp2:
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp5:
leaq 8(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp6:
# %bb.5:
leaq 16(%rsp), %rdi
.Ltmp8:
movl $.L.str.1, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp9:
# %bb.6: # %.noexc28
movq 8(%rsp), %rcx
movq -24(%rcx), %rdi
addq %r14, %rdi
xorl %esi, %esi
testq %rax, %rax
jne .LBB0_8
# %bb.7:
movl 32(%rdi), %esi
orl $4, %esi
.LBB0_8: # %.invoke166
.Ltmp10:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp11:
# %bb.9: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 520(%rsp), %r15
leaq 7(%rsp), %r12
leaq 1040(%rsp), %r13
.p2align 4, 0x90
.LBB0_10: # %_ZNSolsEPFRSoS_E.exit
# =>This Inner Loop Header: Depth=1
.Ltmp13:
movq %r15, %rdi
movq %r12, %rsi
callq _ZNSi3getERc
.Ltmp14:
# %bb.11: # in Loop: Header=BB0_10 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB0_46
# %bb.12: # in Loop: Header=BB0_10 Depth=1
.Ltmp88:
movl $75, %edx
movq %r15, %rdi
movq %r13, %rsi
movl $10, %ecx
callq _ZNSi3getEPclc
.Ltmp89:
# %bb.13: # in Loop: Header=BB0_10 Depth=1
movl $.L.str.2, %esi
movq %r13, %rdi
callq strstr
movq %rax, %rbx
movl $.L.str.3, %esi
movq %r13, %rdi
callq strstr
testq %rbx, %rbx
je .LBB0_32
# %bb.14: # in Loop: Header=BB0_10 Depth=1
.Ltmp90:
movl $.L.str.4, %esi
movl $25, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp91:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_10 Depth=1
movq %rbx, %rdi
callq strlen
.Ltmp92:
movq %r14, %rdi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp93:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit36
# in Loop: Header=BB0_10 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_10 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_22
# %bb.20: # in Loop: Header=BB0_10 Depth=1
movq %r14, %rbp
jmp .LBB0_21
.p2align 4, 0x90
.LBB0_32: # in Loop: Header=BB0_10 Depth=1
testq %rax, %rax
je .LBB0_10
# %bb.33: # in Loop: Header=BB0_10 Depth=1
movq %rax, %rdi
movq %rax, %rbx
callq strlen
.Ltmp98:
movq %r14, %rdi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp99:
# %bb.34: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit41
# in Loop: Header=BB0_10 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
# in Loop: Header=BB0_10 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_37
# %bb.36: # in Loop: Header=BB0_10 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_10 Depth=1
.Ltmp94:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp95:
# %bb.23: # %.noexc75
# in Loop: Header=BB0_10 Depth=1
movq (%rbx), %rax
.Ltmp96:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp97:
# %bb.24: # in Loop: Header=BB0_10 Depth=1
movq %r14, %rbp
jmp .LBB0_25
.LBB0_37: # in Loop: Header=BB0_10 Depth=1
.Ltmp100:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp101:
# %bb.38: # %.noexc85
# in Loop: Header=BB0_10 Depth=1
movq (%rbx), %rax
.Ltmp102:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp103:
.LBB0_39: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i82
# in Loop: Header=BB0_10 Depth=1
.Ltmp104:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp105:
# %bb.40: # %.noexc87
# in Loop: Header=BB0_10 Depth=1
.Ltmp106:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp107:
# %bb.41: # %_ZNSolsEPFRSoS_E.exit43
# in Loop: Header=BB0_10 Depth=1
.Ltmp108:
movq %rax, %rbp
movl $.L.str.5, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp109:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45
# in Loop: Header=BB0_10 Depth=1
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
# in Loop: Header=BB0_10 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_44
.LBB0_21: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i.invoke.sink.split
# in Loop: Header=BB0_10 Depth=1
movzbl 67(%rbx), %eax
.LBB0_25: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i.invoke
# in Loop: Header=BB0_10 Depth=1
.Ltmp114:
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
.Ltmp115:
# %bb.26: # %.noexc77.invoke
# in Loop: Header=BB0_10 Depth=1
.Ltmp116:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp117:
jmp .LBB0_10
.LBB0_44: # in Loop: Header=BB0_10 Depth=1
.Ltmp110:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp111:
# %bb.45: # %.noexc96
# in Loop: Header=BB0_10 Depth=1
movq (%rbx), %rax
.Ltmp112:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp113:
jmp .LBB0_25
.LBB0_46:
.Ltmp15:
movq %rsp, %rdi
callq hipGetDeviceCount
.Ltmp16:
# %bb.47:
cmpl $0, (%rsp)
jle .LBB0_92
# %bb.48:
.Ltmp27:
leaq 8(%rsp), %rdi
movl $.L.str.6, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit49
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_94
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i102
cmpb $0, 56(%rbx)
je .LBB0_52
# %bb.51:
movzbl 67(%rbx), %eax
jmp .LBB0_54
.LBB0_92:
.Ltmp17:
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.93: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit68
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_94
# %bb.96: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i146
cmpb $0, 56(%rbx)
je .LBB0_98
# %bb.97:
movzbl 67(%rbx), %eax
jmp .LBB0_100
.LBB0_52:
.Ltmp29:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp30:
# %bb.53: # %.noexc107
movq (%rbx), %rax
.Ltmp31:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp32:
.LBB0_54: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i104
.Ltmp33:
movsbl %al, %esi
leaq 8(%rsp), %rdi
callq _ZNSo3putEc
.Ltmp34:
# %bb.55: # %.noexc109
.Ltmp35:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp36:
# %bb.56: # %_ZNSolsEPFRSoS_E.exit51
.Ltmp37:
leaq 8(%rsp), %rdi
movl $.L.str.7, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.57: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
movl (%rsp), %esi
.Ltmp39:
leaq 8(%rsp), %rdi
callq _ZNSolsEi
.Ltmp40:
# %bb.58:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_94
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i113
cmpb $0, 56(%r14)
je .LBB0_61
# %bb.60:
movzbl 67(%r14), %eax
jmp .LBB0_63
.LBB0_61:
.Ltmp41:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp42:
# %bb.62: # %.noexc118
movq (%r14), %rax
.Ltmp43:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp44:
.LBB0_63: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i115
.Ltmp45:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp46:
# %bb.64: # %.noexc120
.Ltmp47:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp48:
# %bb.65: # %_ZNSolsEPFRSoS_E.exit55.preheader
cmpl $0, (%rsp)
jle .LBB0_102
# %bb.66: # %.lr.ph
xorl %ebp, %ebp
leaq 1128(%rsp), %r14
leaq 8(%rsp), %r15
.p2align 4, 0x90
.LBB0_67: # =>This Inner Loop Header: Depth=1
.Ltmp49:
movq %r14, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
.Ltmp50:
# %bb.68: # in Loop: Header=BB0_67 Depth=1
.Ltmp51:
movl $.L.str.8, %esi
movl $17, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp52:
# %bb.69: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
# in Loop: Header=BB0_67 Depth=1
movq %r14, %rdi
callq strlen
.Ltmp53:
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp54:
# %bb.70: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60
# in Loop: Header=BB0_67 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_71
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
# in Loop: Header=BB0_67 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_75
# %bb.74: # in Loop: Header=BB0_67 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB0_77
.p2align 4, 0x90
.LBB0_75: # in Loop: Header=BB0_67 Depth=1
.Ltmp55:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp56:
# %bb.76: # %.noexc129
# in Loop: Header=BB0_67 Depth=1
movq (%rbx), %rax
.Ltmp57:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp58:
.LBB0_77: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i126
# in Loop: Header=BB0_67 Depth=1
.Ltmp59:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp60:
# %bb.78: # %.noexc131
# in Loop: Header=BB0_67 Depth=1
.Ltmp61:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp62:
# %bb.79: # %_ZNSolsEPFRSoS_E.exit62
# in Loop: Header=BB0_67 Depth=1
.Ltmp63:
movl $.L.str.9, %esi
movl $17, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp64:
# %bb.80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
# in Loop: Header=BB0_67 Depth=1
movl 1516(%rsp), %esi
.Ltmp65:
movq %r15, %rdi
callq _ZNSolsEi
.Ltmp66:
# %bb.81: # in Loop: Header=BB0_67 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .LBB0_71
# %bb.82: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
# in Loop: Header=BB0_67 Depth=1
cmpb $0, 56(%r12)
je .LBB0_84
# %bb.83: # in Loop: Header=BB0_67 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_86
.p2align 4, 0x90
.LBB0_84: # in Loop: Header=BB0_67 Depth=1
.Ltmp67:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp68:
# %bb.85: # %.noexc140
# in Loop: Header=BB0_67 Depth=1
movq (%r12), %rax
.Ltmp69:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp70:
.LBB0_86: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i137
# in Loop: Header=BB0_67 Depth=1
.Ltmp71:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp72:
# %bb.87: # %.noexc142
# in Loop: Header=BB0_67 Depth=1
.Ltmp73:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp74:
# %bb.88: # %_ZNSolsEPFRSoS_E.exit66
# in Loop: Header=BB0_67 Depth=1
.Ltmp75:
movl %ebp, %edi
callq hipSetDevice
.Ltmp76:
# %bb.89: # %_ZNSolsEPFRSoS_E.exit55
# in Loop: Header=BB0_67 Depth=1
incl %ebp
cmpl (%rsp), %ebp
jl .LBB0_67
jmp .LBB0_102
.LBB0_98:
.Ltmp19:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp20:
# %bb.99: # %.noexc151
movq (%rbx), %rax
.Ltmp21:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp22:
.LBB0_100: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i148
.Ltmp23:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp24:
# %bb.101: # %.noexc153
.Ltmp25:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp26:
.LBB0_102: # %_ZNSolsEPFRSoS_E.exit70
.Ltmp78:
leaq 536(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp79:
# %bb.103: # %.noexc72
testq %rax, %rax
jne .LBB0_105
# %bb.104:
movq 520(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $520, %rdi # imm = 0x208
movl 552(%rsp,%rax), %esi
orl $4, %esi
.Ltmp80:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp81:
.LBB0_105: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 520(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 776(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $2600, %rsp # imm = 0xA28
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17: # %.invoke167
.cfi_def_cfa_offset 2656
.Ltmp119:
callq _ZSt16__throw_bad_castv
.Ltmp120:
# %bb.18: # %.cont
.LBB0_71: # %.invoke170
.Ltmp82:
callq _ZSt16__throw_bad_castv
.Ltmp83:
# %bb.72: # %.cont171
.LBB0_94: # %.invoke168
.Ltmp85:
callq _ZSt16__throw_bad_castv
.Ltmp86:
# %bb.95: # %.cont169
.LBB0_28:
.Ltmp7:
movq %rax, %rbx
jmp .LBB0_108
.LBB0_29:
.Ltmp12:
jmp .LBB0_107
.LBB0_27:
.Ltmp4:
movq %rax, %rbx
jmp .LBB0_108
.LBB0_106:
.Ltmp87:
jmp .LBB0_107
.LBB0_91: # %.loopexit.split-lp
.Ltmp84:
jmp .LBB0_107
.LBB0_31: # %.loopexit.split-lp157
.Ltmp121:
jmp .LBB0_107
.LBB0_90: # %.loopexit
.Ltmp77:
jmp .LBB0_107
.LBB0_30: # %.loopexit156
.Ltmp118:
.LBB0_107:
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB0_108:
leaq 520(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 776(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp8 # Call between .Ltmp8 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp113-.Ltmp13 # Call between .Ltmp13 and .Ltmp113
.uleb128 .Ltmp118-.Lfunc_begin0 # jumps to .Ltmp118
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp48-.Ltmp15 # Call between .Ltmp15 and .Ltmp48
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp76-.Ltmp49 # Call between .Ltmp49 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp81-.Ltmp19 # Call between .Ltmp19 and .Ltmp81
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp119-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp120-.Ltmp119 # Call between .Ltmp119 and .Ltmp120
.uleb128 .Ltmp121-.Lfunc_begin0 # jumps to .Ltmp121
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp83-.Ltmp82 # Call between .Ltmp82 and .Ltmp83
.uleb128 .Ltmp84-.Lfunc_begin0 # jumps to .Ltmp84
.byte 0 # On action: cleanup
.uleb128 .Ltmp85-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp86-.Ltmp85 # Call between .Ltmp85 and .Ltmp86
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end0-.Ltmp86 # Call between .Ltmp86 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/proc/cpuinfo"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "new.txt"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "model name"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cpu cores"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Accelerator type is CPU \n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "--------------------"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Accelerator type is NVIDIA GPU"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Number of NVIDIA GPUs: "
.size .L.str.7, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "model name "
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Multi-Processors "
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "There is no CUDA device"
.size .L.str.10, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187c2e_00000000-6_creatConfig.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "/proc/cpuinfo"
.LC1:
.string "new.txt"
.LC2:
.string "model name"
.LC3:
.string "cpu cores"
.LC4:
.string "Accelerator type is CPU \n"
.LC5:
.string "--------------------"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Accelerator type is NVIDIA GPU"
.section .rodata.str1.1
.LC7:
.string "Number of NVIDIA GPUs: "
.LC8:
.string "model name "
.LC9:
.string "Multi-Processors "
.LC10:
.string "There is no CUDA device"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2200, %rsp
.cfi_def_cfa_offset 2256
movq %fs:40, %rax
movq %rax, 2184(%rsp)
xorl %eax, %eax
leaq 528(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $8, %edx
leaq .LC0(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 16(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq .LC2(%rip), %rbx
leaq .LC3(%rip), %rbp
leaq .LC5(%rip), %r13
leaq .LC4(%rip), %r12
.L6:
leaq 11(%rsp), %rsi
leaq 528(%rsp), %rdi
call _ZNSi3getERc@PLT
jmp .L42
.L53:
leaq 2096(%rsp), %r15
movq %rbx, %rsi
movq %r15, %rdi
call strstr@PLT
movq %rax, %r14
movq %rbp, %rsi
movq %r15, %rdi
call strstr@PLT
movq %rax, %r15
testq %r14, %r14
je .L7
leaq 16(%rsp), %rdi
movl $25, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 16(%rsp), %rdi
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %r14
testq %r14, %r14
je .L43
cmpb $0, 56(%r14)
je .L10
movzbl 67(%r14), %esi
.L11:
movsbl %sil, %esi
leaq 16(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L44
.L43:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L10:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L11
.L44:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L6
.L7:
testq %rax, %rax
je .L6
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 16(%rsp), %rdi
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %r14
testq %r14, %r14
je .L46
cmpb $0, 56(%r14)
je .L15
movzbl 67(%r14), %esi
.L16:
movsbl %sil, %esi
leaq 16(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L47
.L46:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L15:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L47:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %r14
movl $20, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L49
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L50
.L49:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L50:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L6
.L42:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L52
leaq 2096(%rsp), %rsi
leaq 528(%rsp), %rdi
movl $10, %ecx
movl $75, %edx
call _ZNSi3getEPclc@PLT
jmp .L53
.L52:
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L22
leaq 16(%rsp), %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L23
movl $0, %ebp
leaq 1056(%rsp), %r14
leaq 16(%rsp), %r12
leaq .LC9(%rip), %r15
jmp .L32
.L60:
movl $17, %edx
leaq .LC8(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L54
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L55
.L54:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L38:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L34:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2184(%rsp), %rax
subq %fs:40, %rax
je .L35
call __stack_chk_fail@PLT
.L56:
call __stack_chk_fail@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L55:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $17, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 1444(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L57
cmpb $0, 56(%r13)
je .L30
movzbl 67(%r13), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L58
.L57:
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L30:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L58:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl %ebp, %edi
call cudaSetDevice@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L23
.L32:
movl %ebp, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
jmp .L60
.L22:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L23:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE2:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2184(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $2200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L34
.L35:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L37-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 .L38-.LFB3800
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "creatConfig.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2600, %rsp # imm = 0xA28
.cfi_def_cfa_offset 2656
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 520(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 536(%rsp), %rdi
.Ltmp0:
movl $.L.str, %esi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 520(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB0_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB0_3: # %.invoke
.Ltmp2:
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp5:
leaq 8(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp6:
# %bb.5:
leaq 16(%rsp), %rdi
.Ltmp8:
movl $.L.str.1, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp9:
# %bb.6: # %.noexc28
movq 8(%rsp), %rcx
movq -24(%rcx), %rdi
addq %r14, %rdi
xorl %esi, %esi
testq %rax, %rax
jne .LBB0_8
# %bb.7:
movl 32(%rdi), %esi
orl $4, %esi
.LBB0_8: # %.invoke166
.Ltmp10:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp11:
# %bb.9: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 520(%rsp), %r15
leaq 7(%rsp), %r12
leaq 1040(%rsp), %r13
.p2align 4, 0x90
.LBB0_10: # %_ZNSolsEPFRSoS_E.exit
# =>This Inner Loop Header: Depth=1
.Ltmp13:
movq %r15, %rdi
movq %r12, %rsi
callq _ZNSi3getERc
.Ltmp14:
# %bb.11: # in Loop: Header=BB0_10 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB0_46
# %bb.12: # in Loop: Header=BB0_10 Depth=1
.Ltmp88:
movl $75, %edx
movq %r15, %rdi
movq %r13, %rsi
movl $10, %ecx
callq _ZNSi3getEPclc
.Ltmp89:
# %bb.13: # in Loop: Header=BB0_10 Depth=1
movl $.L.str.2, %esi
movq %r13, %rdi
callq strstr
movq %rax, %rbx
movl $.L.str.3, %esi
movq %r13, %rdi
callq strstr
testq %rbx, %rbx
je .LBB0_32
# %bb.14: # in Loop: Header=BB0_10 Depth=1
.Ltmp90:
movl $.L.str.4, %esi
movl $25, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp91:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_10 Depth=1
movq %rbx, %rdi
callq strlen
.Ltmp92:
movq %r14, %rdi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp93:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit36
# in Loop: Header=BB0_10 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_10 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_22
# %bb.20: # in Loop: Header=BB0_10 Depth=1
movq %r14, %rbp
jmp .LBB0_21
.p2align 4, 0x90
.LBB0_32: # in Loop: Header=BB0_10 Depth=1
testq %rax, %rax
je .LBB0_10
# %bb.33: # in Loop: Header=BB0_10 Depth=1
movq %rax, %rdi
movq %rax, %rbx
callq strlen
.Ltmp98:
movq %r14, %rdi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp99:
# %bb.34: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit41
# in Loop: Header=BB0_10 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
# in Loop: Header=BB0_10 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_37
# %bb.36: # in Loop: Header=BB0_10 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_10 Depth=1
.Ltmp94:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp95:
# %bb.23: # %.noexc75
# in Loop: Header=BB0_10 Depth=1
movq (%rbx), %rax
.Ltmp96:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp97:
# %bb.24: # in Loop: Header=BB0_10 Depth=1
movq %r14, %rbp
jmp .LBB0_25
.LBB0_37: # in Loop: Header=BB0_10 Depth=1
.Ltmp100:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp101:
# %bb.38: # %.noexc85
# in Loop: Header=BB0_10 Depth=1
movq (%rbx), %rax
.Ltmp102:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp103:
.LBB0_39: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i82
# in Loop: Header=BB0_10 Depth=1
.Ltmp104:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp105:
# %bb.40: # %.noexc87
# in Loop: Header=BB0_10 Depth=1
.Ltmp106:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp107:
# %bb.41: # %_ZNSolsEPFRSoS_E.exit43
# in Loop: Header=BB0_10 Depth=1
.Ltmp108:
movq %rax, %rbp
movl $.L.str.5, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp109:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45
# in Loop: Header=BB0_10 Depth=1
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
# in Loop: Header=BB0_10 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_44
.LBB0_21: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i.invoke.sink.split
# in Loop: Header=BB0_10 Depth=1
movzbl 67(%rbx), %eax
.LBB0_25: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i.invoke
# in Loop: Header=BB0_10 Depth=1
.Ltmp114:
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
.Ltmp115:
# %bb.26: # %.noexc77.invoke
# in Loop: Header=BB0_10 Depth=1
.Ltmp116:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp117:
jmp .LBB0_10
.LBB0_44: # in Loop: Header=BB0_10 Depth=1
.Ltmp110:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp111:
# %bb.45: # %.noexc96
# in Loop: Header=BB0_10 Depth=1
movq (%rbx), %rax
.Ltmp112:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp113:
jmp .LBB0_25
.LBB0_46:
.Ltmp15:
movq %rsp, %rdi
callq hipGetDeviceCount
.Ltmp16:
# %bb.47:
cmpl $0, (%rsp)
jle .LBB0_92
# %bb.48:
.Ltmp27:
leaq 8(%rsp), %rdi
movl $.L.str.6, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit49
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_94
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i102
cmpb $0, 56(%rbx)
je .LBB0_52
# %bb.51:
movzbl 67(%rbx), %eax
jmp .LBB0_54
.LBB0_92:
.Ltmp17:
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.93: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit68
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_94
# %bb.96: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i146
cmpb $0, 56(%rbx)
je .LBB0_98
# %bb.97:
movzbl 67(%rbx), %eax
jmp .LBB0_100
.LBB0_52:
.Ltmp29:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp30:
# %bb.53: # %.noexc107
movq (%rbx), %rax
.Ltmp31:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp32:
.LBB0_54: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i104
.Ltmp33:
movsbl %al, %esi
leaq 8(%rsp), %rdi
callq _ZNSo3putEc
.Ltmp34:
# %bb.55: # %.noexc109
.Ltmp35:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp36:
# %bb.56: # %_ZNSolsEPFRSoS_E.exit51
.Ltmp37:
leaq 8(%rsp), %rdi
movl $.L.str.7, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.57: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
movl (%rsp), %esi
.Ltmp39:
leaq 8(%rsp), %rdi
callq _ZNSolsEi
.Ltmp40:
# %bb.58:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_94
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i113
cmpb $0, 56(%r14)
je .LBB0_61
# %bb.60:
movzbl 67(%r14), %eax
jmp .LBB0_63
.LBB0_61:
.Ltmp41:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp42:
# %bb.62: # %.noexc118
movq (%r14), %rax
.Ltmp43:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp44:
.LBB0_63: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i115
.Ltmp45:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp46:
# %bb.64: # %.noexc120
.Ltmp47:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp48:
# %bb.65: # %_ZNSolsEPFRSoS_E.exit55.preheader
cmpl $0, (%rsp)
jle .LBB0_102
# %bb.66: # %.lr.ph
xorl %ebp, %ebp
leaq 1128(%rsp), %r14
leaq 8(%rsp), %r15
.p2align 4, 0x90
.LBB0_67: # =>This Inner Loop Header: Depth=1
.Ltmp49:
movq %r14, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
.Ltmp50:
# %bb.68: # in Loop: Header=BB0_67 Depth=1
.Ltmp51:
movl $.L.str.8, %esi
movl $17, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp52:
# %bb.69: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
# in Loop: Header=BB0_67 Depth=1
movq %r14, %rdi
callq strlen
.Ltmp53:
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp54:
# %bb.70: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60
# in Loop: Header=BB0_67 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB0_71
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
# in Loop: Header=BB0_67 Depth=1
cmpb $0, 56(%rbx)
je .LBB0_75
# %bb.74: # in Loop: Header=BB0_67 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB0_77
.p2align 4, 0x90
.LBB0_75: # in Loop: Header=BB0_67 Depth=1
.Ltmp55:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp56:
# %bb.76: # %.noexc129
# in Loop: Header=BB0_67 Depth=1
movq (%rbx), %rax
.Ltmp57:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp58:
.LBB0_77: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i126
# in Loop: Header=BB0_67 Depth=1
.Ltmp59:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp60:
# %bb.78: # %.noexc131
# in Loop: Header=BB0_67 Depth=1
.Ltmp61:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp62:
# %bb.79: # %_ZNSolsEPFRSoS_E.exit62
# in Loop: Header=BB0_67 Depth=1
.Ltmp63:
movl $.L.str.9, %esi
movl $17, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp64:
# %bb.80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
# in Loop: Header=BB0_67 Depth=1
movl 1516(%rsp), %esi
.Ltmp65:
movq %r15, %rdi
callq _ZNSolsEi
.Ltmp66:
# %bb.81: # in Loop: Header=BB0_67 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .LBB0_71
# %bb.82: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
# in Loop: Header=BB0_67 Depth=1
cmpb $0, 56(%r12)
je .LBB0_84
# %bb.83: # in Loop: Header=BB0_67 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_86
.p2align 4, 0x90
.LBB0_84: # in Loop: Header=BB0_67 Depth=1
.Ltmp67:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp68:
# %bb.85: # %.noexc140
# in Loop: Header=BB0_67 Depth=1
movq (%r12), %rax
.Ltmp69:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp70:
.LBB0_86: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i137
# in Loop: Header=BB0_67 Depth=1
.Ltmp71:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp72:
# %bb.87: # %.noexc142
# in Loop: Header=BB0_67 Depth=1
.Ltmp73:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp74:
# %bb.88: # %_ZNSolsEPFRSoS_E.exit66
# in Loop: Header=BB0_67 Depth=1
.Ltmp75:
movl %ebp, %edi
callq hipSetDevice
.Ltmp76:
# %bb.89: # %_ZNSolsEPFRSoS_E.exit55
# in Loop: Header=BB0_67 Depth=1
incl %ebp
cmpl (%rsp), %ebp
jl .LBB0_67
jmp .LBB0_102
.LBB0_98:
.Ltmp19:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp20:
# %bb.99: # %.noexc151
movq (%rbx), %rax
.Ltmp21:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp22:
.LBB0_100: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i148
.Ltmp23:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp24:
# %bb.101: # %.noexc153
.Ltmp25:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp26:
.LBB0_102: # %_ZNSolsEPFRSoS_E.exit70
.Ltmp78:
leaq 536(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp79:
# %bb.103: # %.noexc72
testq %rax, %rax
jne .LBB0_105
# %bb.104:
movq 520(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $520, %rdi # imm = 0x208
movl 552(%rsp,%rax), %esi
orl $4, %esi
.Ltmp80:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp81:
.LBB0_105: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 520(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 776(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $2600, %rsp # imm = 0xA28
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17: # %.invoke167
.cfi_def_cfa_offset 2656
.Ltmp119:
callq _ZSt16__throw_bad_castv
.Ltmp120:
# %bb.18: # %.cont
.LBB0_71: # %.invoke170
.Ltmp82:
callq _ZSt16__throw_bad_castv
.Ltmp83:
# %bb.72: # %.cont171
.LBB0_94: # %.invoke168
.Ltmp85:
callq _ZSt16__throw_bad_castv
.Ltmp86:
# %bb.95: # %.cont169
.LBB0_28:
.Ltmp7:
movq %rax, %rbx
jmp .LBB0_108
.LBB0_29:
.Ltmp12:
jmp .LBB0_107
.LBB0_27:
.Ltmp4:
movq %rax, %rbx
jmp .LBB0_108
.LBB0_106:
.Ltmp87:
jmp .LBB0_107
.LBB0_91: # %.loopexit.split-lp
.Ltmp84:
jmp .LBB0_107
.LBB0_31: # %.loopexit.split-lp157
.Ltmp121:
jmp .LBB0_107
.LBB0_90: # %.loopexit
.Ltmp77:
jmp .LBB0_107
.LBB0_30: # %.loopexit156
.Ltmp118:
.LBB0_107:
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB0_108:
leaq 520(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 776(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp8 # Call between .Ltmp8 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp113-.Ltmp13 # Call between .Ltmp13 and .Ltmp113
.uleb128 .Ltmp118-.Lfunc_begin0 # jumps to .Ltmp118
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp48-.Ltmp15 # Call between .Ltmp15 and .Ltmp48
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp76-.Ltmp49 # Call between .Ltmp49 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp81-.Ltmp19 # Call between .Ltmp19 and .Ltmp81
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp119-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp120-.Ltmp119 # Call between .Ltmp119 and .Ltmp120
.uleb128 .Ltmp121-.Lfunc_begin0 # jumps to .Ltmp121
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp83-.Ltmp82 # Call between .Ltmp82 and .Ltmp83
.uleb128 .Ltmp84-.Lfunc_begin0 # jumps to .Ltmp84
.byte 0 # On action: cleanup
.uleb128 .Ltmp85-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp86-.Ltmp85 # Call between .Ltmp85 and .Ltmp86
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end0-.Ltmp86 # Call between .Ltmp86 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/proc/cpuinfo"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "new.txt"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "model name"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cpu cores"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Accelerator type is CPU \n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "--------------------"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Accelerator type is NVIDIA GPU"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Number of NVIDIA GPUs: "
.size .L.str.7, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "model name "
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Multi-Processors "
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "There is no CUDA device"
.size .L.str.10, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <errno.h>
#include <float.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <vector>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
typedef unsigned char uchar;
typedef unsigned uint;
typedef float flt;
using namespace std;
#define FLT_1_PHI (0.61803398874989485F)
#define FLT_PHI (1.61803398874989484F)
#define FLT_PI (3.14159265358979323F)
#define FLT_SQRT3 (1.73205080756887729F)
#define FLT_SQRT_PHI_2 (1.90211303259030714F)
#define exit_if(cnd_value, msg) \
do { \
if ((cnd_value)) { \
if (errno) \
perror((msg)); \
else \
fprintf(stderr, "error: %s\n", (msg)); \
exit(EXIT_FAILURE); \
} \
} while (0)
#define cudaErrorCheck(error) \
do { \
cudaError_t result = (error); \
if (res != cudaSuccess) { \
fprintf(stderr, "cuda %s:%d error: %s\n", __FILE__, __LINE__, \
cudaGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while(0)
struct triangle {
float3 a, b, c;
uchar4 color;
};
static const uchar4
// aqua = { 0, 255, 255, 0 },
darkgreen = { 0, 100, 0, 0 },
darkred = { 139, 0, 0, 0 },
gold = { 255, 215, 0, 0 },
green = { 0, 255, 0, 0 },
// khaki = { 240, 230, 140, 0 },
// magenta = { 255, 0, 255, 0 },
maroon = { 128, 0, 0, 0 },
midnightblue = { 25, 25, 112, 0 },
purple = { 128, 0, 128, 0 },
red = { 255, 0, 0, 0 },
teal = { 0, 128, 128, 0 },
yellow = { 255, 255, 0, 0 };
__device__ __host__ static float3 cross(const float3 a, const float3 b) {
return {
a.y * b.z - a.z * b.y,
a.z * b.x - a.x * b.z,
a.x * b.y - a.y * b.x
};
}
__device__ __host__ static flt dot(const float3 a, const float3 b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
__device__ __host__ static float3 float3_multiplies(
const float3 a,
const flt alpha
) {
return { a.x * alpha, a.y * alpha, a.z * alpha };
}
__device__ __host__ static float3 float3_plus(
const float3 a,
const float3 b
) {
return { a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ __host__ static float3 float3_fma(
const float3 a,
const flt radius,
const float3 center
) {
return float3_plus(float3_multiplies(a, radius), center);
}
__device__ __host__ static flt length(const float3 a) {
return sqrtf(dot(a, a));
}
__device__ __host__ static float3 float3_minus(const float3 a, const float3 b) {
return { a.x - b.x, a.y - b.y, a.z - b.z };
}
__device__ __host__ static float3 float3_multiplies(
const float3 a,
const float3 b
) {
return { a.x * b.x, a.y * b.y, a.z * b.z };
}
__device__ __host__ static float3 normalize(const float3 a) {
const flt a_length = length(a);
return { a.x / a_length, a.y / a_length, a.z / a_length };
}
__device__ __host__ float3 mult(
const float3 a,
const float3 b,
const float3 c,
const float3 all
) {
return {
a.x * all.x + b.x * all.y + c.x * all.z,
a.y * all.x + b.y * all.y + c.y * all.z,
a.z * all.x + b.z * all.y + c.z * all.z
};
}
static void make_dodecahedron(
vector<triangle> &triangles,
const flt radius,
const float3 center
) {
static const float3
point_1 = { -FLT_1_PHI / FLT_SQRT3, 0.0F, FLT_PHI / FLT_SQRT3 },
point_2 = { FLT_1_PHI / FLT_SQRT3, 0.0F, FLT_PHI / FLT_SQRT3 },
point_3 = { -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_4 = { 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_5 = { 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_6 = { -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_7 = { 0.0F, -FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3 },
point_8 = { 0.0F, FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3 },
point_9 = { -FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3, 0.0F },
point_10 = { -FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3, 0.0F },
point_11 = { FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3, 0.0F },
point_12 = { FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3, 0.0F },
point_13 = { 0.0F, -FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3 },
point_14 = { 0.0F, FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3 },
point_15 = { 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_16 = { 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_17 = { -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_18 = { -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_19 = { FLT_1_PHI / FLT_SQRT3, 0.0F, -FLT_PHI / FLT_SQRT3 },
point_20 = { -FLT_1_PHI / FLT_SQRT3 , 0.0F, -FLT_PHI / FLT_SQRT3 };
triangles.push_back({ point_5, point_1, point_7, green });
triangles.push_back({ point_1, point_6, point_7, darkgreen });
triangles.push_back({ point_1, point_5, point_2, maroon });
triangles.push_back({ point_1, point_4, point_8, purple });
triangles.push_back({ point_3, point_1, point_8, red });
triangles.push_back({ point_1, point_2, point_4, yellow });
triangles.push_back({ point_11, point_2, point_12, green });
triangles.push_back({ point_4, point_2, point_11, darkgreen });
triangles.push_back({ point_2, point_5, point_12, maroon });
triangles.push_back({ point_6, point_1, point_9, purple });
triangles.push_back({ point_1, point_3, point_10, red });
triangles.push_back({ point_9, point_1, point_10, yellow });
triangles.push_back({ point_6, point_9, point_17, green });
triangles.push_back({ point_7, point_6, point_13, darkgreen });
triangles.push_back({ point_13, point_6, point_17, maroon });
triangles.push_back({ point_5, point_13, point_16, purple });
triangles.push_back({ point_5, point_7, point_13, red });
triangles.push_back({ point_12, point_5, point_16, green });
triangles.push_back({ point_3, point_14, point_18, darkgreen });
triangles.push_back({ point_3, point_8, point_14, maroon });
triangles.push_back({ point_10, point_3, point_18, purple });
triangles.push_back({ point_14, point_4, point_15, red });
triangles.push_back({ point_8, point_4, point_14, yellow });
triangles.push_back({ point_4, point_11, point_15, green });
triangles.push_back({ point_9, point_18, point_20, darkgreen });
triangles.push_back({ point_17, point_9, point_20, maroon });
triangles.push_back({ point_9, point_10, point_18, purple });
triangles.push_back({ point_15, point_12, point_19, red });
triangles.push_back({ point_12, point_16, point_19, green });
triangles.push_back({ point_11, point_12, point_15, darkgreen });
triangles.push_back({ point_13, point_20, point_19, maroon });
triangles.push_back({ point_16, point_13, point_19, purple });
triangles.push_back({ point_13, point_17, point_20, yellow });
triangles.push_back({ point_20, point_14, point_19, maroon });
triangles.push_back({ point_18, point_14, point_20, darkgreen });
triangles.push_back({ point_14, point_15, point_19, yellow });
for (size_t i = 0; i < 36U; ++i) {
triangle &triangle_ref = triangles[triangles.size() - i - 1U];
triangle_ref.a = float3_fma(triangle_ref.a, radius, center);
triangle_ref.b = float3_fma(triangle_ref.b, radius, center);
triangle_ref.c = float3_fma(triangle_ref.c, radius, center);
}
}
static void make_icosagedron(
vector<triangle> &triangles,
const flt radius,
const float3 center
) {
static const float3
point_1 = { 0.0F, -1.0F / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2 },
point_2 = { 0.0F, 1.0 / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2 },
point_3 = { -FLT_PHI / FLT_SQRT_PHI_2, 0.0, 1.0 / FLT_SQRT_PHI_2 },
point_4 = { FLT_PHI / FLT_SQRT_PHI_2, 0.0, 1.0 / FLT_SQRT_PHI_2 },
point_5 = { -1.0 / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_6 = { 1.0 / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_7 = { 1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_8 = { -1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_9 = { -FLT_PHI / FLT_SQRT_PHI_2, 0.0, -1.0 / FLT_SQRT_PHI_2 },
point_10 = { FLT_PHI / FLT_SQRT_PHI_2, 0.0, -1.0 / FLT_SQRT_PHI_2 },
point_11 = { 0.0, -1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2 },
point_12 = { 0.0, 1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2 };
triangles.push_back({ point_1, point_2, point_3, purple });
triangles.push_back({ point_2, point_1, point_4, red });
triangles.push_back({ point_1, point_3, point_8, yellow });
triangles.push_back({ point_3, point_2, point_5, green });
triangles.push_back({ point_5, point_2, point_6, darkgreen });
triangles.push_back({ point_7, point_1, point_8, maroon });
triangles.push_back({ point_4, point_1, point_7, purple });
triangles.push_back({ point_2, point_4, point_6, red });
triangles.push_back({ point_5, point_6, point_12, yellow });
triangles.push_back({ point_7, point_8, point_11, green });
triangles.push_back({ point_4, point_7, point_10, darkgreen });
triangles.push_back({ point_6, point_4, point_10, maroon });
triangles.push_back({ point_8, point_3, point_9, purple });
triangles.push_back({ point_3, point_5, point_9, red });
triangles.push_back({ point_10, point_11, point_12, yellow });
triangles.push_back({ point_11, point_9, point_12, green });
triangles.push_back({ point_6, point_10, point_12, darkgreen });
triangles.push_back({ point_10, point_7, point_11, maroon });
triangles.push_back({ point_8, point_9, point_11, purple });
triangles.push_back({ point_9, point_5, point_12, red });
for (size_t i = 0; i < 20U; ++i) {
triangle &triangle_ref = triangles[triangles.size() - i - 1U];
triangle_ref.a = float3_fma(triangle_ref.a, radius, center);
triangle_ref.b = float3_fma(triangle_ref.b, radius, center);
triangle_ref.c = float3_fma(triangle_ref.c, radius, center);
}
}
static void make_tetrahedron(
vector<triangle> &triangles,
const flt radius,
const float3 center
) {
static const float3
point_1 = { sqrtf(8.0F / 9.0F), 0.0F, -1.0F / 3.0F },
point_2 = { -sqrtf(2.0F / 9.0F), sqrtf(2.0F / 3.0F), -1.0F / 3.0F },
point_3 = { -sqrtf(2.0F / 9.0F), -sqrtf(2.0F / 3.0F), -1.0F / 3.0F },
point_4 = { 0.0F, 0.0F, 1.0F };
triangles.push_back({ point_2, point_1, point_3, gold });
triangles.push_back({ point_1, point_2, point_4, darkred });
triangles.push_back({ point_3, point_1, point_4, teal });
triangles.push_back({ point_2, point_3, point_4, midnightblue });
for (size_t i = 0; i < 4U; ++i) {
triangle &triangle_ref = triangles[triangles.size() - i - 1U];
triangle_ref.a = float3_fma(triangle_ref.a, radius, center);
triangle_ref.b = float3_fma(triangle_ref.b, radius, center);
triangle_ref.c = float3_fma(triangle_ref.c, radius, center);
}
}
static void create_field(
vector<triangle> &triangles,
const float3 point_a,
const float3 point_b,
const float3 point_c,
const float3 point_d,
const float3 texture_color
) {
const uchar4 color = {
(uchar) (texture_color.x * UCHAR_MAX),
(uchar) (texture_color.y * UCHAR_MAX),
(uchar) (texture_color.z * UCHAR_MAX),
0
};
triangles.push_back({ point_a, point_b, point_c, color });
triangles.push_back({ point_a, point_c, point_d, color });
}
__device__ __host__ static uchar4 ray(
float3 pos,
float3 dir,
const float3 sunshine,
const float3 sunshine_c,
triangle * const triangles,
const size_t count
) {
ptrdiff_t min_value = -1;
flt ts_min;
for (size_t i = 0; i < count; ++i) {
const float3
e1 = float3_minus(triangles[i].b, triangles[i].a),
e2 = float3_minus(triangles[i].c, triangles[i].a),
p = cross(dir, e2);
const flt div = dot(p, e1);
if (fabsf(div) < FLT_EPSILON)
continue;
const float3 t = float3_minus(pos, triangles[i].a);
const flt u = dot(p, t) / div;
if (u < 0.0F || u > 1.0F)
continue;
float3 q = cross(t, e1);
flt v = dot(q, dir) / div;
if (v < 0.0F || v + u > 1.0F)
continue;
flt ts = dot(q, e2) / div;
if (ts < 0.0F)
continue;
if (min_value == -1 || ts < ts_min) {
min_value = i;
ts_min = ts;
}
}
if (min_value == -1)
return { 0, 0, 0, 0 };
pos = float3_plus(float3_multiplies(dir, ts_min), pos);
dir = float3_minus(sunshine, pos);
const flt dir_length = length(dir);
dir = normalize(dir);
for (size_t i = 0; i < count; ++i) {
const float3
e1 = float3_minus(triangles[i].b, triangles[i].a),
e2 = float3_minus(triangles[i].c, triangles[i].a),
p = cross(dir, e2);
const flt div = dot(p, e1);
if (fabsf(div) < FLT_EPSILON)
continue;
float3 t = float3_minus(pos, triangles[i].a);
const flt u = dot(p, t) / div;
if (u < 0.0F || u > 1.0F)
continue;
float3 q = cross(t, e1);
const flt v = dot(q, dir) / div;
if (v < 0.0F || v + u > 1.0F)
continue;
const flt ts = dot(q, e2) / div;
if (ts > 0.0F && ts < dir_length && i != min_value)
return { 0, 0, 0, 0 };
}
const uchar4 color_min = triangles[min_value].color;
const float3 result = float3_multiplies(
make_float3(color_min.x, color_min.y, color_min.z),
sunshine_c
);
return make_uchar4(result.x, result.y, result.z, color_min.w);
}
static void render_cpu(
float3 pc, float3 pv,
const uint w, const uint h,
flt angle,
uchar4 * const data,
float3 sunshine, float3 sunshine_c,
triangle * const triangles, const size_t count
) {
const flt dw = 2.0F / (w - 1), dh = 2.0F / (h - 1),
z = 1.0F / tanf(angle * FLT_PI / 360.0F);
const float3
bz = normalize(float3_minus(pv, pc)),
bx = normalize(cross(bz, { 0.0F, 0.0F, 1.0F })),
by = normalize(cross(bx, bz));
for (uint i = 0; i < w; ++i)
for (uint j = 0; j < h; ++j) {
const float3 v = { -1.0F + dw * i, (-1.0F + dh * j) * h / w, z };
const float3 dir = mult(bx, by, bz, v);
data[(h - 1 - j) * w + i] = ray(pc, normalize(dir), sunshine, sunshine_c, triangles, count);
}
}
__global__ static void render(
const float3 pc, const float3 pv,
const uint w, const uint h,
const flt angle,
uchar4 * const data,
const float3 sunshine, const float3 sunshine_c,
triangle * const triangles, const size_t count
) {
const uint
idx = blockDim.x * blockIdx.x + threadIdx.x,
idy = blockDim.y * blockIdx.y + threadIdx.y,
offsetx = blockDim.x * gridDim.x,
offsety = blockDim.y * gridDim.y;
const flt dw = 2.0F / (w - 1), dh = 2.0F / (h - 1),
z = 1.0F / tanf(angle * FLT_PI / 360.0F);
const float3
bz = normalize(float3_minus(pv, pc)),
bx = normalize(cross(bz, { 0.0F, 0.0F, 1.0F })),
by = normalize(cross(bx, bz));
for (uint i = idx; i < w; i += offsetx)
for (uint j = idy; j < h; j += offsety) {
const float3 v = { -1.0F + dw * i, (-1.0F + dh * j) * h / w, z },
dir = mult(bx, by, bz, v);
data[(h - 1 - j) * w + i] = ray(pc, normalize(dir), sunshine, sunshine_c, triangles, count);
}
}
int main(const int argc, char ** const argv) {
int flag_cuda, numbers_data, width, height, iter, light;
float three_points_1, three_points_2, phi, r_first_0, z_first_0, f_first_0, A_first_r, A_first_z, w_first_r,
w_first_z, w_first_f, p_first_r, p_first_z, r_second_0, z_second_0, f_second_0, A_second_r, A_second_z, w_second_r,
w_second_z, w_second_f, p_second_r, p_second_z, rds, r_, trs, lght, tro;
float3 cntr, clr, tp_1, tp_2, tp_3, tp_4, tc, pc, pv, sunshine, sunshine_c;
string trash;
char bffr[256];
string exit_place;
if (argc >= 3) {
cout << "SOMETHING WENT WRONG......\nYOU CAN USE EQUAL OR LESS THEN 2 ARGUMENTS!\n";
return 0;
}
if (argc == 1)
flag_cuda = 1;
else if (!strcmp(argv[1], "--gpu"))
flag_cuda = 1;
else if (!strcmp(argv[1], "--default")) {
cout << "99"
"./images_data/"
"640 480 120\n"
"6.8 2.7 0.1 2.2 1.1 2.1 6.1 1.1 0.0 0.0\n"
"2.2 0.001 0.01 0.54 0.12 1.1 4.2 1.1 0.0 0.0\n"
"3.0 0.0 0.0 255 255 255 1.0 42 42 42\n"
"0.0 3.0 0.0 255 255 255 0.75 42 42 42\n"
"0.0 0.0 0.0 255 255 255 1.0 42 42 42\n"
"-5.0 -5.0 -1.0 -5.0 5.0 -1.0 5.0 5.0 -1.0 5.0 -5.0 -1.0 ~/textures 0.0 1.0 0.0 0.5\n"
"1\n"
"-8.0 0.0 8.0 1.0 1.0 1.0\n"
"100 100\n";
return 0;
}
else if (!strcmp(argv[1], "--cpu"))
flag_cuda = 0;
cin >> numbers_data >> exit_place >> width >> height >> phi;
cin >> r_first_0 >> z_first_0 >> f_first_0 >> A_first_r >> A_first_z >> w_first_r >> w_first_z >> w_first_f >> p_first_r >> p_first_z >>
r_second_0 >> z_second_0 >> f_second_0 >> A_second_r >> A_second_z >> w_second_r >> w_second_z >> w_second_f >> p_second_r >> p_second_z;
uchar4 *data = (uchar4 *) malloc(width * height * sizeof(uchar4));
uchar4 *deviceData;
cudaMalloc(&deviceData, width * height * sizeof(uchar4));
cudaMemset(deviceData, 0, width * height * sizeof(uchar4));
vector <triangle> triangles;
cin >> cntr.x >> cntr.y >> cntr.z >> clr.x >> clr.y >> clr.z >> rds >> r_ >> trs >> lght;
make_tetrahedron(triangles, rds, cntr);
cin >> cntr.x >> cntr.y >> cntr.z >> clr.x >> clr.y >> clr.z >> rds >> r_ >> trs >> lght;
make_dodecahedron(triangles, rds, cntr);
cin >> cntr.x >> cntr.y >> cntr.z >> clr.x >> clr.y >> clr.z >> rds >> r_ >> trs >> lght;
make_icosagedron(triangles, rds, cntr);
cin >> tp_1.x >> tp_1.y >> tp_1.z >> tp_2.x >> tp_2.y >> tp_2.z >> tp_3.x >> tp_3.y >> tp_3.z >> tp_4.x >> tp_4.y >> tp_4.z;
cin >> trash >> tc.x >> tc.y >> tc.z >> tro;
create_field(triangles, tp_1, tp_2, tp_3, tp_4, tc);
cin >> light;
if (light != 1) {
cout << "I need in only 3 points for this project!\n";
return 0;
}
cin >> sunshine.x >> sunshine.y >> sunshine.z >> sunshine_c.x >> sunshine_c.y >> sunshine_c.z >> three_points_1 >> three_points_2;
sunshine.x = 100;
sunshine.y = 100;
sunshine.z = 100;
triangle *deviceTriangles;
cudaMalloc(&deviceTriangles, triangles.size() * sizeof(triangle));
cudaMemcpy(deviceTriangles, triangles.data(), triangles.size() * sizeof(triangle),
cudaMemcpyHostToDevice
);
iter = 0;
while (iter < numbers_data) {
float step = 2 * FLT_PI * iter / numbers_data;
float r_first = A_first_r * sin(w_first_r * step + p_first_r) + r_first_0;
float z_first = A_first_z * sin(w_first_z * step + p_first_z) + z_first_0;
float f_first = w_first_f * step + f_first_0;
float r_second = A_second_r * sin(w_second_r * step + p_second_r) + r_second_0;
float z_second = A_second_z * sin(w_second_z * step + p_second_z) + z_second_0;
float f_second = w_second_f * step + f_second_0;
pc.x = cos(f_first) * r_first;
pc.y = sin(f_first) * r_first;
pc.z = z_first;
pv.x = cos(f_second) * r_second;
pv.y = sin(f_second) * r_second;
pv.z = z_second;
if (flag_cuda == 1) {
render<<<dim3(16, 16), dim3(16, 16)>>>(pc, pv, width, height, phi, deviceData, sunshine, sunshine_c, deviceTriangles, triangles.size());
cudaMemcpy(data, deviceData, sizeof(uchar4) * width * height, cudaMemcpyDeviceToHost);
}
else
render_cpu(pc, pv, width, height, phi, data, sunshine, sunshine_c, triangles.data(), triangles.size());
sprintf(bffr, "%d.data", iter);
const string result_show(exit_place + "/" + string(bffr));
cout << iter << ": " << bffr << endl;
FILE* out = fopen(result_show.c_str(), "wb");
fwrite(&width, sizeof(int), 1, out);
fwrite(&height, sizeof(int), 1, out);
fwrite(data, sizeof(uchar4), width * height, out);
fclose(out);
++iter;
}
cudaFree(deviceData);
cudaFree(deviceTriangles);
free(data);
return 0;
} | #include <errno.h>
#include <float.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <vector>
#include "hip/hip_runtime.h"
typedef unsigned char uchar;
typedef unsigned uint;
typedef float flt;
using namespace std;
#define FLT_1_PHI (0.61803398874989485F)
#define FLT_PHI (1.61803398874989484F)
#define FLT_PI (3.14159265358979323F)
#define FLT_SQRT3 (1.73205080756887729F)
#define FLT_SQRT_PHI_2 (1.90211303259030714F)
#define exit_if(cnd_value, msg) \
do { \
if ((cnd_value)) { \
if (errno) \
perror((msg)); \
else \
fprintf(stderr, "error: %s\n", (msg)); \
exit(EXIT_FAILURE); \
} \
} while (0)
#define cudaErrorCheck(error) \
do { \
hipError_t result = (error); \
if (res != hipSuccess) { \
fprintf(stderr, "cuda %s:%d error: %s\n", __FILE__, __LINE__, \
hipGetErrorString(res)); \
exit(EXIT_FAILURE); \
} \
} while(0)
struct triangle {
float3 a, b, c;
uchar4 color;
};
static const uchar4
// aqua = { 0, 255, 255, 0 },
darkgreen = { 0, 100, 0, 0 },
darkred = { 139, 0, 0, 0 },
gold = { 255, 215, 0, 0 },
green = { 0, 255, 0, 0 },
// khaki = { 240, 230, 140, 0 },
// magenta = { 255, 0, 255, 0 },
maroon = { 128, 0, 0, 0 },
midnightblue = { 25, 25, 112, 0 },
purple = { 128, 0, 128, 0 },
red = { 255, 0, 0, 0 },
teal = { 0, 128, 128, 0 },
yellow = { 255, 255, 0, 0 };
__device__ __host__ static float3 cross(const float3 a, const float3 b) {
return {
a.y * b.z - a.z * b.y,
a.z * b.x - a.x * b.z,
a.x * b.y - a.y * b.x
};
}
__device__ __host__ static flt dot(const float3 a, const float3 b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
__device__ __host__ static float3 float3_multiplies(
const float3 a,
const flt alpha
) {
return { a.x * alpha, a.y * alpha, a.z * alpha };
}
__device__ __host__ static float3 float3_plus(
const float3 a,
const float3 b
) {
return { a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ __host__ static float3 float3_fma(
const float3 a,
const flt radius,
const float3 center
) {
return float3_plus(float3_multiplies(a, radius), center);
}
__device__ __host__ static flt length(const float3 a) {
return sqrtf(dot(a, a));
}
__device__ __host__ static float3 float3_minus(const float3 a, const float3 b) {
return { a.x - b.x, a.y - b.y, a.z - b.z };
}
__device__ __host__ static float3 float3_multiplies(
const float3 a,
const float3 b
) {
return { a.x * b.x, a.y * b.y, a.z * b.z };
}
__device__ __host__ static float3 normalize(const float3 a) {
const flt a_length = length(a);
return { a.x / a_length, a.y / a_length, a.z / a_length };
}
__device__ __host__ float3 mult(
const float3 a,
const float3 b,
const float3 c,
const float3 all
) {
return {
a.x * all.x + b.x * all.y + c.x * all.z,
a.y * all.x + b.y * all.y + c.y * all.z,
a.z * all.x + b.z * all.y + c.z * all.z
};
}
static void make_dodecahedron(
vector<triangle> &triangles,
const flt radius,
const float3 center
) {
static const float3
point_1 = { -FLT_1_PHI / FLT_SQRT3, 0.0F, FLT_PHI / FLT_SQRT3 },
point_2 = { FLT_1_PHI / FLT_SQRT3, 0.0F, FLT_PHI / FLT_SQRT3 },
point_3 = { -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_4 = { 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_5 = { 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_6 = { -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3 },
point_7 = { 0.0F, -FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3 },
point_8 = { 0.0F, FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3 },
point_9 = { -FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3, 0.0F },
point_10 = { -FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3, 0.0F },
point_11 = { FLT_PHI / FLT_SQRT3, FLT_1_PHI / FLT_SQRT3, 0.0F },
point_12 = { FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3, 0.0F },
point_13 = { 0.0F, -FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3 },
point_14 = { 0.0F, FLT_PHI / FLT_SQRT3, -FLT_1_PHI / FLT_SQRT3 },
point_15 = { 1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_16 = { 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_17 = { -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_18 = { -1.0F / FLT_SQRT3, 1.0F / FLT_SQRT3, -1.0F / FLT_SQRT3 },
point_19 = { FLT_1_PHI / FLT_SQRT3, 0.0F, -FLT_PHI / FLT_SQRT3 },
point_20 = { -FLT_1_PHI / FLT_SQRT3 , 0.0F, -FLT_PHI / FLT_SQRT3 };
triangles.push_back({ point_5, point_1, point_7, green });
triangles.push_back({ point_1, point_6, point_7, darkgreen });
triangles.push_back({ point_1, point_5, point_2, maroon });
triangles.push_back({ point_1, point_4, point_8, purple });
triangles.push_back({ point_3, point_1, point_8, red });
triangles.push_back({ point_1, point_2, point_4, yellow });
triangles.push_back({ point_11, point_2, point_12, green });
triangles.push_back({ point_4, point_2, point_11, darkgreen });
triangles.push_back({ point_2, point_5, point_12, maroon });
triangles.push_back({ point_6, point_1, point_9, purple });
triangles.push_back({ point_1, point_3, point_10, red });
triangles.push_back({ point_9, point_1, point_10, yellow });
triangles.push_back({ point_6, point_9, point_17, green });
triangles.push_back({ point_7, point_6, point_13, darkgreen });
triangles.push_back({ point_13, point_6, point_17, maroon });
triangles.push_back({ point_5, point_13, point_16, purple });
triangles.push_back({ point_5, point_7, point_13, red });
triangles.push_back({ point_12, point_5, point_16, green });
triangles.push_back({ point_3, point_14, point_18, darkgreen });
triangles.push_back({ point_3, point_8, point_14, maroon });
triangles.push_back({ point_10, point_3, point_18, purple });
triangles.push_back({ point_14, point_4, point_15, red });
triangles.push_back({ point_8, point_4, point_14, yellow });
triangles.push_back({ point_4, point_11, point_15, green });
triangles.push_back({ point_9, point_18, point_20, darkgreen });
triangles.push_back({ point_17, point_9, point_20, maroon });
triangles.push_back({ point_9, point_10, point_18, purple });
triangles.push_back({ point_15, point_12, point_19, red });
triangles.push_back({ point_12, point_16, point_19, green });
triangles.push_back({ point_11, point_12, point_15, darkgreen });
triangles.push_back({ point_13, point_20, point_19, maroon });
triangles.push_back({ point_16, point_13, point_19, purple });
triangles.push_back({ point_13, point_17, point_20, yellow });
triangles.push_back({ point_20, point_14, point_19, maroon });
triangles.push_back({ point_18, point_14, point_20, darkgreen });
triangles.push_back({ point_14, point_15, point_19, yellow });
for (size_t i = 0; i < 36U; ++i) {
triangle &triangle_ref = triangles[triangles.size() - i - 1U];
triangle_ref.a = float3_fma(triangle_ref.a, radius, center);
triangle_ref.b = float3_fma(triangle_ref.b, radius, center);
triangle_ref.c = float3_fma(triangle_ref.c, radius, center);
}
}
static void make_icosagedron(
vector<triangle> &triangles,
const flt radius,
const float3 center
) {
static const float3
point_1 = { 0.0F, -1.0F / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2 },
point_2 = { 0.0F, 1.0 / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2 },
point_3 = { -FLT_PHI / FLT_SQRT_PHI_2, 0.0, 1.0 / FLT_SQRT_PHI_2 },
point_4 = { FLT_PHI / FLT_SQRT_PHI_2, 0.0, 1.0 / FLT_SQRT_PHI_2 },
point_5 = { -1.0 / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_6 = { 1.0 / FLT_SQRT_PHI_2, FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_7 = { 1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_8 = { -1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2, 0.0 },
point_9 = { -FLT_PHI / FLT_SQRT_PHI_2, 0.0, -1.0 / FLT_SQRT_PHI_2 },
point_10 = { FLT_PHI / FLT_SQRT_PHI_2, 0.0, -1.0 / FLT_SQRT_PHI_2 },
point_11 = { 0.0, -1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2 },
point_12 = { 0.0, 1.0 / FLT_SQRT_PHI_2, -FLT_PHI / FLT_SQRT_PHI_2 };
triangles.push_back({ point_1, point_2, point_3, purple });
triangles.push_back({ point_2, point_1, point_4, red });
triangles.push_back({ point_1, point_3, point_8, yellow });
triangles.push_back({ point_3, point_2, point_5, green });
triangles.push_back({ point_5, point_2, point_6, darkgreen });
triangles.push_back({ point_7, point_1, point_8, maroon });
triangles.push_back({ point_4, point_1, point_7, purple });
triangles.push_back({ point_2, point_4, point_6, red });
triangles.push_back({ point_5, point_6, point_12, yellow });
triangles.push_back({ point_7, point_8, point_11, green });
triangles.push_back({ point_4, point_7, point_10, darkgreen });
triangles.push_back({ point_6, point_4, point_10, maroon });
triangles.push_back({ point_8, point_3, point_9, purple });
triangles.push_back({ point_3, point_5, point_9, red });
triangles.push_back({ point_10, point_11, point_12, yellow });
triangles.push_back({ point_11, point_9, point_12, green });
triangles.push_back({ point_6, point_10, point_12, darkgreen });
triangles.push_back({ point_10, point_7, point_11, maroon });
triangles.push_back({ point_8, point_9, point_11, purple });
triangles.push_back({ point_9, point_5, point_12, red });
for (size_t i = 0; i < 20U; ++i) {
triangle &triangle_ref = triangles[triangles.size() - i - 1U];
triangle_ref.a = float3_fma(triangle_ref.a, radius, center);
triangle_ref.b = float3_fma(triangle_ref.b, radius, center);
triangle_ref.c = float3_fma(triangle_ref.c, radius, center);
}
}
static void make_tetrahedron(
vector<triangle> &triangles,
const flt radius,
const float3 center
) {
static const float3
point_1 = { sqrtf(8.0F / 9.0F), 0.0F, -1.0F / 3.0F },
point_2 = { -sqrtf(2.0F / 9.0F), sqrtf(2.0F / 3.0F), -1.0F / 3.0F },
point_3 = { -sqrtf(2.0F / 9.0F), -sqrtf(2.0F / 3.0F), -1.0F / 3.0F },
point_4 = { 0.0F, 0.0F, 1.0F };
triangles.push_back({ point_2, point_1, point_3, gold });
triangles.push_back({ point_1, point_2, point_4, darkred });
triangles.push_back({ point_3, point_1, point_4, teal });
triangles.push_back({ point_2, point_3, point_4, midnightblue });
for (size_t i = 0; i < 4U; ++i) {
triangle &triangle_ref = triangles[triangles.size() - i - 1U];
triangle_ref.a = float3_fma(triangle_ref.a, radius, center);
triangle_ref.b = float3_fma(triangle_ref.b, radius, center);
triangle_ref.c = float3_fma(triangle_ref.c, radius, center);
}
}
static void create_field(
vector<triangle> &triangles,
const float3 point_a,
const float3 point_b,
const float3 point_c,
const float3 point_d,
const float3 texture_color
) {
const uchar4 color = {
(uchar) (texture_color.x * UCHAR_MAX),
(uchar) (texture_color.y * UCHAR_MAX),
(uchar) (texture_color.z * UCHAR_MAX),
0
};
triangles.push_back({ point_a, point_b, point_c, color });
triangles.push_back({ point_a, point_c, point_d, color });
}
__device__ __host__ static uchar4 ray(
float3 pos,
float3 dir,
const float3 sunshine,
const float3 sunshine_c,
triangle * const triangles,
const size_t count
) {
ptrdiff_t min_value = -1;
flt ts_min;
for (size_t i = 0; i < count; ++i) {
const float3
e1 = float3_minus(triangles[i].b, triangles[i].a),
e2 = float3_minus(triangles[i].c, triangles[i].a),
p = cross(dir, e2);
const flt div = dot(p, e1);
if (fabsf(div) < FLT_EPSILON)
continue;
const float3 t = float3_minus(pos, triangles[i].a);
const flt u = dot(p, t) / div;
if (u < 0.0F || u > 1.0F)
continue;
float3 q = cross(t, e1);
flt v = dot(q, dir) / div;
if (v < 0.0F || v + u > 1.0F)
continue;
flt ts = dot(q, e2) / div;
if (ts < 0.0F)
continue;
if (min_value == -1 || ts < ts_min) {
min_value = i;
ts_min = ts;
}
}
if (min_value == -1)
return { 0, 0, 0, 0 };
pos = float3_plus(float3_multiplies(dir, ts_min), pos);
dir = float3_minus(sunshine, pos);
const flt dir_length = length(dir);
dir = normalize(dir);
for (size_t i = 0; i < count; ++i) {
const float3
e1 = float3_minus(triangles[i].b, triangles[i].a),
e2 = float3_minus(triangles[i].c, triangles[i].a),
p = cross(dir, e2);
const flt div = dot(p, e1);
if (fabsf(div) < FLT_EPSILON)
continue;
float3 t = float3_minus(pos, triangles[i].a);
const flt u = dot(p, t) / div;
if (u < 0.0F || u > 1.0F)
continue;
float3 q = cross(t, e1);
const flt v = dot(q, dir) / div;
if (v < 0.0F || v + u > 1.0F)
continue;
const flt ts = dot(q, e2) / div;
if (ts > 0.0F && ts < dir_length && i != min_value)
return { 0, 0, 0, 0 };
}
const uchar4 color_min = triangles[min_value].color;
const float3 result = float3_multiplies(
make_float3(color_min.x, color_min.y, color_min.z),
sunshine_c
);
return make_uchar4(result.x, result.y, result.z, color_min.w);
}
static void render_cpu(
float3 pc, float3 pv,
const uint w, const uint h,
flt angle,
uchar4 * const data,
float3 sunshine, float3 sunshine_c,
triangle * const triangles, const size_t count
) {
const flt dw = 2.0F / (w - 1), dh = 2.0F / (h - 1),
z = 1.0F / tanf(angle * FLT_PI / 360.0F);
const float3
bz = normalize(float3_minus(pv, pc)),
bx = normalize(cross(bz, { 0.0F, 0.0F, 1.0F })),
by = normalize(cross(bx, bz));
for (uint i = 0; i < w; ++i)
for (uint j = 0; j < h; ++j) {
const float3 v = { -1.0F + dw * i, (-1.0F + dh * j) * h / w, z };
const float3 dir = mult(bx, by, bz, v);
data[(h - 1 - j) * w + i] = ray(pc, normalize(dir), sunshine, sunshine_c, triangles, count);
}
}
__global__ static void render(
const float3 pc, const float3 pv,
const uint w, const uint h,
const flt angle,
uchar4 * const data,
const float3 sunshine, const float3 sunshine_c,
triangle * const triangles, const size_t count
) {
const uint
idx = blockDim.x * blockIdx.x + threadIdx.x,
idy = blockDim.y * blockIdx.y + threadIdx.y,
offsetx = blockDim.x * gridDim.x,
offsety = blockDim.y * gridDim.y;
const flt dw = 2.0F / (w - 1), dh = 2.0F / (h - 1),
z = 1.0F / tanf(angle * FLT_PI / 360.0F);
const float3
bz = normalize(float3_minus(pv, pc)),
bx = normalize(cross(bz, { 0.0F, 0.0F, 1.0F })),
by = normalize(cross(bx, bz));
for (uint i = idx; i < w; i += offsetx)
for (uint j = idy; j < h; j += offsety) {
const float3 v = { -1.0F + dw * i, (-1.0F + dh * j) * h / w, z },
dir = mult(bx, by, bz, v);
data[(h - 1 - j) * w + i] = ray(pc, normalize(dir), sunshine, sunshine_c, triangles, count);
}
}
int main(const int argc, char ** const argv) {
int flag_cuda, numbers_data, width, height, iter, light;
float three_points_1, three_points_2, phi, r_first_0, z_first_0, f_first_0, A_first_r, A_first_z, w_first_r,
w_first_z, w_first_f, p_first_r, p_first_z, r_second_0, z_second_0, f_second_0, A_second_r, A_second_z, w_second_r,
w_second_z, w_second_f, p_second_r, p_second_z, rds, r_, trs, lght, tro;
float3 cntr, clr, tp_1, tp_2, tp_3, tp_4, tc, pc, pv, sunshine, sunshine_c;
string trash;
char bffr[256];
string exit_place;
if (argc >= 3) {
cout << "SOMETHING WENT WRONG......\nYOU CAN USE EQUAL OR LESS THEN 2 ARGUMENTS!\n";
return 0;
}
if (argc == 1)
flag_cuda = 1;
else if (!strcmp(argv[1], "--gpu"))
flag_cuda = 1;
else if (!strcmp(argv[1], "--default")) {
cout << "99"
"./images_data/"
"640 480 120\n"
"6.8 2.7 0.1 2.2 1.1 2.1 6.1 1.1 0.0 0.0\n"
"2.2 0.001 0.01 0.54 0.12 1.1 4.2 1.1 0.0 0.0\n"
"3.0 0.0 0.0 255 255 255 1.0 42 42 42\n"
"0.0 3.0 0.0 255 255 255 0.75 42 42 42\n"
"0.0 0.0 0.0 255 255 255 1.0 42 42 42\n"
"-5.0 -5.0 -1.0 -5.0 5.0 -1.0 5.0 5.0 -1.0 5.0 -5.0 -1.0 ~/textures 0.0 1.0 0.0 0.5\n"
"1\n"
"-8.0 0.0 8.0 1.0 1.0 1.0\n"
"100 100\n";
return 0;
}
else if (!strcmp(argv[1], "--cpu"))
flag_cuda = 0;
cin >> numbers_data >> exit_place >> width >> height >> phi;
cin >> r_first_0 >> z_first_0 >> f_first_0 >> A_first_r >> A_first_z >> w_first_r >> w_first_z >> w_first_f >> p_first_r >> p_first_z >>
r_second_0 >> z_second_0 >> f_second_0 >> A_second_r >> A_second_z >> w_second_r >> w_second_z >> w_second_f >> p_second_r >> p_second_z;
uchar4 *data = (uchar4 *) malloc(width * height * sizeof(uchar4));
uchar4 *deviceData;
hipMalloc(&deviceData, width * height * sizeof(uchar4));
hipMemset(deviceData, 0, width * height * sizeof(uchar4));
vector <triangle> triangles;
cin >> cntr.x >> cntr.y >> cntr.z >> clr.x >> clr.y >> clr.z >> rds >> r_ >> trs >> lght;
make_tetrahedron(triangles, rds, cntr);
cin >> cntr.x >> cntr.y >> cntr.z >> clr.x >> clr.y >> clr.z >> rds >> r_ >> trs >> lght;
make_dodecahedron(triangles, rds, cntr);
cin >> cntr.x >> cntr.y >> cntr.z >> clr.x >> clr.y >> clr.z >> rds >> r_ >> trs >> lght;
make_icosagedron(triangles, rds, cntr);
cin >> tp_1.x >> tp_1.y >> tp_1.z >> tp_2.x >> tp_2.y >> tp_2.z >> tp_3.x >> tp_3.y >> tp_3.z >> tp_4.x >> tp_4.y >> tp_4.z;
cin >> trash >> tc.x >> tc.y >> tc.z >> tro;
create_field(triangles, tp_1, tp_2, tp_3, tp_4, tc);
cin >> light;
if (light != 1) {
cout << "I need in only 3 points for this project!\n";
return 0;
}
cin >> sunshine.x >> sunshine.y >> sunshine.z >> sunshine_c.x >> sunshine_c.y >> sunshine_c.z >> three_points_1 >> three_points_2;
sunshine.x = 100;
sunshine.y = 100;
sunshine.z = 100;
triangle *deviceTriangles;
hipMalloc(&deviceTriangles, triangles.size() * sizeof(triangle));
hipMemcpy(deviceTriangles, triangles.data(), triangles.size() * sizeof(triangle),
hipMemcpyHostToDevice
);
iter = 0;
while (iter < numbers_data) {
float step = 2 * FLT_PI * iter / numbers_data;
float r_first = A_first_r * sin(w_first_r * step + p_first_r) + r_first_0;
float z_first = A_first_z * sin(w_first_z * step + p_first_z) + z_first_0;
float f_first = w_first_f * step + f_first_0;
float r_second = A_second_r * sin(w_second_r * step + p_second_r) + r_second_0;
float z_second = A_second_z * sin(w_second_z * step + p_second_z) + z_second_0;
float f_second = w_second_f * step + f_second_0;
pc.x = cos(f_first) * r_first;
pc.y = sin(f_first) * r_first;
pc.z = z_first;
pv.x = cos(f_second) * r_second;
pv.y = sin(f_second) * r_second;
pv.z = z_second;
if (flag_cuda == 1) {
render<<<dim3(16, 16), dim3(16, 16)>>>(pc, pv, width, height, phi, deviceData, sunshine, sunshine_c, deviceTriangles, triangles.size());
hipMemcpy(data, deviceData, sizeof(uchar4) * width * height, hipMemcpyDeviceToHost);
}
else
render_cpu(pc, pv, width, height, phi, data, sunshine, sunshine_c, triangles.data(), triangles.size());
sprintf(bffr, "%d.data", iter);
const string result_show(exit_place + "/" + string(bffr));
cout << iter << ": " << bffr << endl;
FILE* out = fopen(result_show.c_str(), "wb");
fwrite(&width, sizeof(int), 1, out);
fwrite(&height, sizeof(int), 1, out);
fwrite(data, sizeof(uchar4), width * height, out);
fclose(out);
++iter;
}
hipFree(deviceData);
hipFree(deviceTriangles);
free(data);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C"
{
}
__global__ void A_emult_Bg0(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
} | code for sm_80
Function : _Z11A_emult_Bg0iPKdS0_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ DSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x004e1c0003f04000 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x001fea0003800000 */
/*00e0*/ LDG.E.64 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1b00 */
/*00f0*/ DADD R2, RZ, R2 ; /* 0x00000000ff027229 */
/* 0x004e0e0000000002 */
/*0100*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ LEA R6, P0, R0.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0000067a11 */
/* 0x040fe200078018ff */
/*0130*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ LEA.HI.X R7, R0, c[0x0][0x16c], R7, 0x3, P0 ; /* 0x00005b0000077a11 */
/* 0x000fca00000f1c07 */
/*0150*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ DADD R2, R2, R8 ; /* 0x0000000002027229 */
/* 0x004e0e0000000008 */
/*0170*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
{
}
__global__ void A_emult_Bg0(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
} | .file "tmpxft_00130a0f_00000000-6_A_emult_Bg0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd
.type _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd, @function
_Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11A_emult_Bg0iPKdS0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd, .-_Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd
.globl _Z11A_emult_Bg0iPKdS0_Pd
.type _Z11A_emult_Bg0iPKdS0_Pd, @function
_Z11A_emult_Bg0iPKdS0_Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11A_emult_Bg0iPKdS0_Pd, .-_Z11A_emult_Bg0iPKdS0_Pd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11A_emult_Bg0iPKdS0_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11A_emult_Bg0iPKdS0_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
{
}
__global__ void A_emult_Bg0(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void A_emult_Bg0(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void A_emult_Bg0(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11A_emult_Bg0iPKdS0_Pd
.globl _Z11A_emult_Bg0iPKdS0_Pd
.p2align 8
.type _Z11A_emult_Bg0iPKdS0_Pd,@function
_Z11A_emult_Bg0iPKdS0_Pd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_nlt_f64_e32 vcc_lo, 0, v[3:4]
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
s_or_saveexec_b32 s4, s4
v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v7, s2
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[7:8], v[5:6], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
global_load_b64 v[0:1], v[3:4], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[7:8]
global_store_b64 v[5:6], v[0:1], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11A_emult_Bg0iPKdS0_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11A_emult_Bg0iPKdS0_Pd, .Lfunc_end0-_Z11A_emult_Bg0iPKdS0_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11A_emult_Bg0iPKdS0_Pd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11A_emult_Bg0iPKdS0_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void A_emult_Bg0(const int n, const double *a, const double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
} | .text
.file "A_emult_Bg0.hip"
.globl _Z26__device_stub__A_emult_Bg0iPKdS0_Pd # -- Begin function _Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.p2align 4, 0x90
.type _Z26__device_stub__A_emult_Bg0iPKdS0_Pd,@function
_Z26__device_stub__A_emult_Bg0iPKdS0_Pd: # @_Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11A_emult_Bg0iPKdS0_Pd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__A_emult_Bg0iPKdS0_Pd, .Lfunc_end0-_Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11A_emult_Bg0iPKdS0_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11A_emult_Bg0iPKdS0_Pd,@object # @_Z11A_emult_Bg0iPKdS0_Pd
.section .rodata,"a",@progbits
.globl _Z11A_emult_Bg0iPKdS0_Pd
.p2align 3, 0x0
_Z11A_emult_Bg0iPKdS0_Pd:
.quad _Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.size _Z11A_emult_Bg0iPKdS0_Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11A_emult_Bg0iPKdS0_Pd"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11A_emult_Bg0iPKdS0_Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11A_emult_Bg0iPKdS0_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ DSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x004e1c0003f04000 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x001fea0003800000 */
/*00e0*/ LDG.E.64 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1b00 */
/*00f0*/ DADD R2, RZ, R2 ; /* 0x00000000ff027229 */
/* 0x004e0e0000000002 */
/*0100*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ LEA R6, P0, R0.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0000067a11 */
/* 0x040fe200078018ff */
/*0130*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ LEA.HI.X R7, R0, c[0x0][0x16c], R7, 0x3, P0 ; /* 0x00005b0000077a11 */
/* 0x000fca00000f1c07 */
/*0150*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ DADD R2, R2, R8 ; /* 0x0000000002027229 */
/* 0x004e0e0000000008 */
/*0170*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11A_emult_Bg0iPKdS0_Pd
.globl _Z11A_emult_Bg0iPKdS0_Pd
.p2align 8
.type _Z11A_emult_Bg0iPKdS0_Pd,@function
_Z11A_emult_Bg0iPKdS0_Pd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_nlt_f64_e32 vcc_lo, 0, v[3:4]
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
s_or_saveexec_b32 s4, s4
v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v7, s2
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[7:8], v[5:6], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
global_load_b64 v[0:1], v[3:4], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[7:8]
global_store_b64 v[5:6], v[0:1], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11A_emult_Bg0iPKdS0_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11A_emult_Bg0iPKdS0_Pd, .Lfunc_end0-_Z11A_emult_Bg0iPKdS0_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11A_emult_Bg0iPKdS0_Pd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11A_emult_Bg0iPKdS0_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00130a0f_00000000-6_A_emult_Bg0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd
.type _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd, @function
_Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11A_emult_Bg0iPKdS0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd, .-_Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd
.globl _Z11A_emult_Bg0iPKdS0_Pd
.type _Z11A_emult_Bg0iPKdS0_Pd, @function
_Z11A_emult_Bg0iPKdS0_Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11A_emult_Bg0iPKdS0_PdiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11A_emult_Bg0iPKdS0_Pd, .-_Z11A_emult_Bg0iPKdS0_Pd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11A_emult_Bg0iPKdS0_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11A_emult_Bg0iPKdS0_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "A_emult_Bg0.hip"
.globl _Z26__device_stub__A_emult_Bg0iPKdS0_Pd # -- Begin function _Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.p2align 4, 0x90
.type _Z26__device_stub__A_emult_Bg0iPKdS0_Pd,@function
_Z26__device_stub__A_emult_Bg0iPKdS0_Pd: # @_Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11A_emult_Bg0iPKdS0_Pd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__A_emult_Bg0iPKdS0_Pd, .Lfunc_end0-_Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11A_emult_Bg0iPKdS0_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11A_emult_Bg0iPKdS0_Pd,@object # @_Z11A_emult_Bg0iPKdS0_Pd
.section .rodata,"a",@progbits
.globl _Z11A_emult_Bg0iPKdS0_Pd
.p2align 3, 0x0
_Z11A_emult_Bg0iPKdS0_Pd:
.quad _Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.size _Z11A_emult_Bg0iPKdS0_Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11A_emult_Bg0iPKdS0_Pd"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__A_emult_Bg0iPKdS0_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11A_emult_Bg0iPKdS0_Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
int main(){
int deviceCount; cudaGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has compute capability %d.%d.\n", device, deviceProp.name, deviceProp.major, deviceProp.minor);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
int main(){
int deviceCount; cudaGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has compute capability %d.%d.\n", device, deviceProp.name, deviceProp.major, deviceProp.minor);
}
} | .file "tmpxft_0010dfe8_00000000-6_DeviceList.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device %d (%s) has compute capability %d.%d.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 380(%rsp), %r9d
movl 376(%rsp), %r8d
movq %rbp, %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
int main(){
int deviceCount; cudaGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has compute capability %d.%d.\n", device, deviceProp.name, deviceProp.major, deviceProp.minor);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
int deviceCount; hipGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has compute capability %d.%d.\n", device, deviceProp.name, deviceProp.major, deviceProp.minor);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
int deviceCount; hipGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has compute capability %d.%d.\n", device, deviceProp.name, deviceProp.major, deviceProp.minor);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
int deviceCount; hipGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has compute capability %d.%d.\n", device, deviceProp.name, deviceProp.major, deviceProp.minor);
}
} | .text
.file "DeviceList.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 368(%rsp), %ecx
movl 372(%rsp), %r8d
movl $.L.str, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device %d (%s) has compute capability %d.%d.\n"
.size .L.str, 46
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010dfe8_00000000-6_DeviceList.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device %d (%s) has compute capability %d.%d.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 380(%rsp), %r9d
movl 376(%rsp), %r8d
movq %rbp, %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DeviceList.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 368(%rsp), %ecx
movl 372(%rsp), %r8d
movl $.L.str, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device %d (%s) has compute capability %d.%d.\n"
.size .L.str, 46
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define MAX_NONCE 1000000000 // 100000000000
//char* tohexadecimal
void mine(long blockNum, char *trans, char *preHash, int prefixZero){
//char prefix[] = "0000" ;
for(int i = 0; i < MAX_NONCE; i++){
//printf("mining...\n") ;
srand(i*blockNum*(trans[0])*(preHash[0]));
int count = 0 ;
for(int j = 0; j < prefixZero; j++){
if(rand() % 10 == 0){
count++ ;
}
}
if (count == prefixZero){
//printf("found, nonce = %d\n", i) ;
}
//printf("%d\n", rand() % 10);
}
}
int main(){
char trans[] = "A-20->B,b-10->C" ;
char preHash[] = "0000000xa036944e29568d0cff17edbe038f81208fecf9a66be9a2b8321c6ec7" ;
int difficulty = 4 ;
cudaEvent_t start, stop ;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start) ;
mine(1, trans, preHash, difficulty) ;
cudaEventRecord(stop) ;
cudaEventSynchronize(stop) ;
float millisec = 0 ;
cudaEventElapsedTime(&millisec, start, stop) ;
printf("Time used: %f\n", millisec) ;
printf("end\n") ;
return 0 ;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define MAX_NONCE 1000000000 // 100000000000
//char* tohexadecimal
void mine(long blockNum, char *trans, char *preHash, int prefixZero){
//char prefix[] = "0000" ;
for(int i = 0; i < MAX_NONCE; i++){
//printf("mining...\n") ;
srand(i*blockNum*(trans[0])*(preHash[0]));
int count = 0 ;
for(int j = 0; j < prefixZero; j++){
if(rand() % 10 == 0){
count++ ;
}
}
if (count == prefixZero){
//printf("found, nonce = %d\n", i) ;
}
//printf("%d\n", rand() % 10);
}
}
int main(){
char trans[] = "A-20->B,b-10->C" ;
char preHash[] = "0000000xa036944e29568d0cff17edbe038f81208fecf9a66be9a2b8321c6ec7" ;
int difficulty = 4 ;
cudaEvent_t start, stop ;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start) ;
mine(1, trans, preHash, difficulty) ;
cudaEventRecord(stop) ;
cudaEventSynchronize(stop) ;
float millisec = 0 ;
cudaEventElapsedTime(&millisec, start, stop) ;
printf("Time used: %f\n", millisec) ;
printf("end\n") ;
return 0 ;
} | .file "tmpxft_00054d78_00000000-6_mining.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4minelPcS_i
.type _Z4minelPcS_i, @function
_Z4minelPcS_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %ebp
movl $0, %r12d
jmp .L6
.L4:
addl $1, %r12d
cmpl $1000000000, %r12d
je .L10
.L6:
movsbl (%r14), %edi
imull %r15d, %edi
movsbl 0(%r13), %eax
imull %eax, %edi
imull %r12d, %edi
call srand@PLT
testl %ebp, %ebp
jle .L4
movl $0, %ebx
.L5:
call rand@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L5
jmp .L4
.L10:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4minelPcS_i, .-_Z4minelPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time used: %f\n"
.LC2:
.string "end\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movabsq $3189179849934777665, %rax
movabsq $18927187242593634, %rdx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movabsq $8660475066958491696, %rax
movabsq $7292511116946780257, %rdx
movq %rax, 48(%rsp)
movq %rdx, 56(%rsp)
movabsq $7147322801227381042, %rax
movabsq $7305511931428824678, %rdx
movq %rax, 64(%rsp)
movq %rdx, 72(%rsp)
movabsq $3472892380958962480, %rax
movabsq $3918476262706079288, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movabsq $4062865206997770806, %rax
movabsq $3991144979047199283, %rdx
movq %rax, 96(%rsp)
movq %rdx, 104(%rsp)
movb $0, 112(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdx
leaq 32(%rsp), %rsi
movl $4, %ecx
movl $1, %edi
call _Z4minelPcS_i
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define MAX_NONCE 1000000000 // 100000000000
//char* tohexadecimal
void mine(long blockNum, char *trans, char *preHash, int prefixZero){
//char prefix[] = "0000" ;
for(int i = 0; i < MAX_NONCE; i++){
//printf("mining...\n") ;
srand(i*blockNum*(trans[0])*(preHash[0]));
int count = 0 ;
for(int j = 0; j < prefixZero; j++){
if(rand() % 10 == 0){
count++ ;
}
}
if (count == prefixZero){
//printf("found, nonce = %d\n", i) ;
}
//printf("%d\n", rand() % 10);
}
}
int main(){
char trans[] = "A-20->B,b-10->C" ;
char preHash[] = "0000000xa036944e29568d0cff17edbe038f81208fecf9a66be9a2b8321c6ec7" ;
int difficulty = 4 ;
cudaEvent_t start, stop ;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start) ;
mine(1, trans, preHash, difficulty) ;
cudaEventRecord(stop) ;
cudaEventSynchronize(stop) ;
float millisec = 0 ;
cudaEventElapsedTime(&millisec, start, stop) ;
printf("Time used: %f\n", millisec) ;
printf("end\n") ;
return 0 ;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define MAX_NONCE 1000000000 // 100000000000
//char* tohexadecimal
void mine(long blockNum, char *trans, char *preHash, int prefixZero){
//char prefix[] = "0000" ;
for(int i = 0; i < MAX_NONCE; i++){
//printf("mining...\n") ;
srand(i*blockNum*(trans[0])*(preHash[0]));
int count = 0 ;
for(int j = 0; j < prefixZero; j++){
if(rand() % 10 == 0){
count++ ;
}
}
if (count == prefixZero){
//printf("found, nonce = %d\n", i) ;
}
//printf("%d\n", rand() % 10);
}
}
int main(){
char trans[] = "A-20->B,b-10->C" ;
char preHash[] = "0000000xa036944e29568d0cff17edbe038f81208fecf9a66be9a2b8321c6ec7" ;
int difficulty = 4 ;
hipEvent_t start, stop ;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start) ;
mine(1, trans, preHash, difficulty) ;
hipEventRecord(stop) ;
hipEventSynchronize(stop) ;
float millisec = 0 ;
hipEventElapsedTime(&millisec, start, stop) ;
printf("Time used: %f\n", millisec) ;
printf("end\n") ;
return 0 ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define MAX_NONCE 1000000000 // 100000000000
//char* tohexadecimal
void mine(long blockNum, char *trans, char *preHash, int prefixZero){
//char prefix[] = "0000" ;
for(int i = 0; i < MAX_NONCE; i++){
//printf("mining...\n") ;
srand(i*blockNum*(trans[0])*(preHash[0]));
int count = 0 ;
for(int j = 0; j < prefixZero; j++){
if(rand() % 10 == 0){
count++ ;
}
}
if (count == prefixZero){
//printf("found, nonce = %d\n", i) ;
}
//printf("%d\n", rand() % 10);
}
}
int main(){
char trans[] = "A-20->B,b-10->C" ;
char preHash[] = "0000000xa036944e29568d0cff17edbe038f81208fecf9a66be9a2b8321c6ec7" ;
int difficulty = 4 ;
hipEvent_t start, stop ;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start) ;
mine(1, trans, preHash, difficulty) ;
hipEventRecord(stop) ;
hipEventSynchronize(stop) ;
float millisec = 0 ;
hipEventElapsedTime(&millisec, start, stop) ;
printf("Time used: %f\n", millisec) ;
printf("end\n") ;
return 0 ;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define MAX_NONCE 1000000000 // 100000000000
//char* tohexadecimal
void mine(long blockNum, char *trans, char *preHash, int prefixZero){
//char prefix[] = "0000" ;
for(int i = 0; i < MAX_NONCE; i++){
//printf("mining...\n") ;
srand(i*blockNum*(trans[0])*(preHash[0]));
int count = 0 ;
for(int j = 0; j < prefixZero; j++){
if(rand() % 10 == 0){
count++ ;
}
}
if (count == prefixZero){
//printf("found, nonce = %d\n", i) ;
}
//printf("%d\n", rand() % 10);
}
}
int main(){
char trans[] = "A-20->B,b-10->C" ;
char preHash[] = "0000000xa036944e29568d0cff17edbe038f81208fecf9a66be9a2b8321c6ec7" ;
int difficulty = 4 ;
hipEvent_t start, stop ;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start) ;
mine(1, trans, preHash, difficulty) ;
hipEventRecord(stop) ;
hipEventSynchronize(stop) ;
float millisec = 0 ;
hipEventElapsedTime(&millisec, start, stop) ;
printf("Time used: %f\n", millisec) ;
printf("end\n") ;
return 0 ;
} | .text
.file "mining.hip"
.globl _Z4minelPcS_i # -- Begin function _Z4minelPcS_i
.p2align 4, 0x90
.type _Z4minelPcS_i,@function
_Z4minelPcS_i: # @_Z4minelPcS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
xorl %r13d, %r13d
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_2: # %._crit_edge
# in Loop: Header=BB0_1 Depth=1
incq %r13
cmpq $1000000000, %r13 # imm = 0x3B9ACA00
je .LBB0_3
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl %r13d, %eax
imull %r12d, %eax
movsbl (%r15), %ecx
imull %eax, %ecx
movsbl (%r14), %edi
imull %ecx, %edi
callq srand
movl %ebx, %ebp
testl %ebx, %ebx
jle .LBB0_2
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decl %ebp
jne .LBB0_4
jmp .LBB0_2
.LBB0_3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z4minelPcS_i, .Lfunc_end0-_Z4minelPcS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
imull $3120, %ebx, %edi # imm = 0xC30
callq srand
movl $4, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph.i
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decl %ebp
jne .LBB1_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB1_1 Depth=1
incq %rbx
cmpq $1000000000, %rbx # imm = 0x3B9ACA00
jne .LBB1_1
# %bb.4: # %_Z4minelPcS_i.exit
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time used: %f\n"
.size .L.str, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "end"
.size .Lstr, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054d78_00000000-6_mining.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4minelPcS_i
.type _Z4minelPcS_i, @function
_Z4minelPcS_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %ebp
movl $0, %r12d
jmp .L6
.L4:
addl $1, %r12d
cmpl $1000000000, %r12d
je .L10
.L6:
movsbl (%r14), %edi
imull %r15d, %edi
movsbl 0(%r13), %eax
imull %eax, %edi
imull %r12d, %edi
call srand@PLT
testl %ebp, %ebp
jle .L4
movl $0, %ebx
.L5:
call rand@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L5
jmp .L4
.L10:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4minelPcS_i, .-_Z4minelPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time used: %f\n"
.LC2:
.string "end\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movabsq $3189179849934777665, %rax
movabsq $18927187242593634, %rdx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movabsq $8660475066958491696, %rax
movabsq $7292511116946780257, %rdx
movq %rax, 48(%rsp)
movq %rdx, 56(%rsp)
movabsq $7147322801227381042, %rax
movabsq $7305511931428824678, %rdx
movq %rax, 64(%rsp)
movq %rdx, 72(%rsp)
movabsq $3472892380958962480, %rax
movabsq $3918476262706079288, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movabsq $4062865206997770806, %rax
movabsq $3991144979047199283, %rdx
movq %rax, 96(%rsp)
movq %rdx, 104(%rsp)
movb $0, 112(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdx
leaq 32(%rsp), %rsi
movl $4, %ecx
movl $1, %edi
call _Z4minelPcS_i
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mining.hip"
.globl _Z4minelPcS_i # -- Begin function _Z4minelPcS_i
.p2align 4, 0x90
.type _Z4minelPcS_i,@function
_Z4minelPcS_i: # @_Z4minelPcS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
xorl %r13d, %r13d
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_2: # %._crit_edge
# in Loop: Header=BB0_1 Depth=1
incq %r13
cmpq $1000000000, %r13 # imm = 0x3B9ACA00
je .LBB0_3
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl %r13d, %eax
imull %r12d, %eax
movsbl (%r15), %ecx
imull %eax, %ecx
movsbl (%r14), %edi
imull %ecx, %edi
callq srand
movl %ebx, %ebp
testl %ebx, %ebx
jle .LBB0_2
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decl %ebp
jne .LBB0_4
jmp .LBB0_2
.LBB0_3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z4minelPcS_i, .Lfunc_end0-_Z4minelPcS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
imull $3120, %ebx, %edi # imm = 0xC30
callq srand
movl $4, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph.i
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decl %ebp
jne .LBB1_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB1_1 Depth=1
incq %rbx
cmpq $1000000000, %rbx # imm = 0x3B9ACA00
jne .LBB1_1
# %bb.4: # %_Z4minelPcS_i.exit
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time used: %f\n"
.size .L.str, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "end"
.size .Lstr, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void setWalkersAtLast ( const int dim, const int nwl, const float *lst, float *xx ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
xx[t] = lst[i+j*(dim+1+1+1+1)];
}
} | code for sm_80
Function : _Z16setWalkersAtLastiiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ LEA R3, R3, R0, 0x2 ; /* 0x0000000003037211 */
/* 0x000fcc00078e10ff */
/*00e0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0204 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void setWalkersAtLast ( const int dim, const int nwl, const float *lst, float *xx ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
xx[t] = lst[i+j*(dim+1+1+1+1)];
}
} | .file "tmpxft_000dba9a_00000000-6_setWalkersAtLast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf
.type _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf, @function
_Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16setWalkersAtLastiiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf, .-_Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf
.globl _Z16setWalkersAtLastiiPKfPf
.type _Z16setWalkersAtLastiiPKfPf, @function
_Z16setWalkersAtLastiiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16setWalkersAtLastiiPKfPf, .-_Z16setWalkersAtLastiiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16setWalkersAtLastiiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16setWalkersAtLastiiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void setWalkersAtLast ( const int dim, const int nwl, const float *lst, float *xx ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
xx[t] = lst[i+j*(dim+1+1+1+1)];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void setWalkersAtLast ( const int dim, const int nwl, const float *lst, float *xx ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
xx[t] = lst[i+j*(dim+1+1+1+1)];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void setWalkersAtLast ( const int dim, const int nwl, const float *lst, float *xx ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
xx[t] = lst[i+j*(dim+1+1+1+1)];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16setWalkersAtLastiiPKfPf
.globl _Z16setWalkersAtLastiiPKfPf
.p2align 8
.type _Z16setWalkersAtLastiiPKfPf,@function
_Z16setWalkersAtLastiiPKfPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_add_i32 s5, s4, 4
s_load_b128 s[0:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16setWalkersAtLastiiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16setWalkersAtLastiiPKfPf, .Lfunc_end0-_Z16setWalkersAtLastiiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16setWalkersAtLastiiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16setWalkersAtLastiiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void setWalkersAtLast ( const int dim, const int nwl, const float *lst, float *xx ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int t = i + j * dim;
if ( i < dim && j < nwl ) {
xx[t] = lst[i+j*(dim+1+1+1+1)];
}
} | .text
.file "setWalkersAtLast.hip"
.globl _Z31__device_stub__setWalkersAtLastiiPKfPf # -- Begin function _Z31__device_stub__setWalkersAtLastiiPKfPf
.p2align 4, 0x90
.type _Z31__device_stub__setWalkersAtLastiiPKfPf,@function
_Z31__device_stub__setWalkersAtLastiiPKfPf: # @_Z31__device_stub__setWalkersAtLastiiPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16setWalkersAtLastiiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__setWalkersAtLastiiPKfPf, .Lfunc_end0-_Z31__device_stub__setWalkersAtLastiiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16setWalkersAtLastiiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16setWalkersAtLastiiPKfPf,@object # @_Z16setWalkersAtLastiiPKfPf
.section .rodata,"a",@progbits
.globl _Z16setWalkersAtLastiiPKfPf
.p2align 3, 0x0
_Z16setWalkersAtLastiiPKfPf:
.quad _Z31__device_stub__setWalkersAtLastiiPKfPf
.size _Z16setWalkersAtLastiiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16setWalkersAtLastiiPKfPf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__setWalkersAtLastiiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16setWalkersAtLastiiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16setWalkersAtLastiiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ LEA R3, R3, R0, 0x2 ; /* 0x0000000003037211 */
/* 0x000fcc00078e10ff */
/*00e0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0204 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16setWalkersAtLastiiPKfPf
.globl _Z16setWalkersAtLastiiPKfPf
.p2align 8
.type _Z16setWalkersAtLastiiPKfPf,@function
_Z16setWalkersAtLastiiPKfPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_add_i32 s5, s4, 4
s_load_b128 s[0:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16setWalkersAtLastiiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16setWalkersAtLastiiPKfPf, .Lfunc_end0-_Z16setWalkersAtLastiiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16setWalkersAtLastiiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16setWalkersAtLastiiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dba9a_00000000-6_setWalkersAtLast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf
.type _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf, @function
_Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16setWalkersAtLastiiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf, .-_Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf
.globl _Z16setWalkersAtLastiiPKfPf
.type _Z16setWalkersAtLastiiPKfPf, @function
_Z16setWalkersAtLastiiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16setWalkersAtLastiiPKfPfiiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16setWalkersAtLastiiPKfPf, .-_Z16setWalkersAtLastiiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16setWalkersAtLastiiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16setWalkersAtLastiiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setWalkersAtLast.hip"
.globl _Z31__device_stub__setWalkersAtLastiiPKfPf # -- Begin function _Z31__device_stub__setWalkersAtLastiiPKfPf
.p2align 4, 0x90
.type _Z31__device_stub__setWalkersAtLastiiPKfPf,@function
_Z31__device_stub__setWalkersAtLastiiPKfPf: # @_Z31__device_stub__setWalkersAtLastiiPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16setWalkersAtLastiiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__setWalkersAtLastiiPKfPf, .Lfunc_end0-_Z31__device_stub__setWalkersAtLastiiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16setWalkersAtLastiiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16setWalkersAtLastiiPKfPf,@object # @_Z16setWalkersAtLastiiPKfPf
.section .rodata,"a",@progbits
.globl _Z16setWalkersAtLastiiPKfPf
.p2align 3, 0x0
_Z16setWalkersAtLastiiPKfPf:
.quad _Z31__device_stub__setWalkersAtLastiiPKfPf
.size _Z16setWalkersAtLastiiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16setWalkersAtLastiiPKfPf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__setWalkersAtLastiiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16setWalkersAtLastiiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void doubling(int n, float *a) {
int tid = blockDim.x*blockIdx.x + threadIdx.x;
int i;
while(tid < n) {
a[tid] *= 2;
for(i=0; i<1000; i++) a[tid] *= 1;
tid += blockDim.x * gridDim.x;
}
}
int main() {
int i;
int n=65535*3500;
float *a, *a_dev;
a = (float *)malloc(n*sizeof(float));
cudaMalloc((void**)&a_dev, n*sizeof(float));
for(i=0; i<n; i++) a[i] = 1.;
cudaMemcpy(a_dev, a, n*sizeof(float), cudaMemcpyHostToDevice);
doubling<<<65535, 256>>>(n, a_dev);
cudaMemcpy(a, a_dev, n*sizeof(float), cudaMemcpyDeviceToHost);
for(i=0; i<n; i++) {
if(abs(a[i] - 2.) > 1e-5) printf("a[%d] = %g\n", i, a[i]);
}
free(a);
cudaFree(a_dev);
return 0;
} | code for sm_80
Function : _Z8doublingiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*00d0*/ FADD R5, R4, R4 ; /* 0x0000000404057221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*00f0*/ @!P0 BRA 0x70 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void doubling(int n, float *a) {
int tid = blockDim.x*blockIdx.x + threadIdx.x;
int i;
while(tid < n) {
a[tid] *= 2;
for(i=0; i<1000; i++) a[tid] *= 1;
tid += blockDim.x * gridDim.x;
}
}
int main() {
int i;
int n=65535*3500;
float *a, *a_dev;
a = (float *)malloc(n*sizeof(float));
cudaMalloc((void**)&a_dev, n*sizeof(float));
for(i=0; i<n; i++) a[i] = 1.;
cudaMemcpy(a_dev, a, n*sizeof(float), cudaMemcpyHostToDevice);
doubling<<<65535, 256>>>(n, a_dev);
cudaMemcpy(a, a_dev, n*sizeof(float), cudaMemcpyDeviceToHost);
for(i=0; i<n; i++) {
if(abs(a[i] - 2.) > 1e-5) printf("a[%d] = %g\n", i, a[i]);
}
free(a);
cudaFree(a_dev);
return 0;
} | .file "tmpxft_0007d297_00000000-6_doubling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8doublingiPfiPf
.type _Z28__device_stub__Z8doublingiPfiPf, @function
_Z28__device_stub__Z8doublingiPfiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8doublingiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8doublingiPfiPf, .-_Z28__device_stub__Z8doublingiPfiPf
.globl _Z8doublingiPf
.type _Z8doublingiPf, @function
_Z8doublingiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8doublingiPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8doublingiPf, .-_Z8doublingiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "a[%d] = %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $917490000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $917490000, %esi
call cudaMalloc@PLT
movq %rbp, %rax
leaq 917490000(%rbp), %rdx
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $1, %ecx
movl $917490000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $65535, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $2, %ecx
movl $917490000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %r12
jmp .L16
.L22:
movq 8(%rsp), %rsi
movl $229372500, %edi
call _Z28__device_stub__Z8doublingiPfiPf
jmp .L13
.L14:
addq $1, %rbx
cmpq $229372500, %rbx
je .L23
.L16:
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx,4), %xmm1
movapd %xmm1, %xmm0
subsd .LC1(%rip), %xmm0
andpd .LC2(%rip), %xmm0
comisd .LC3(%rip), %xmm0
jbe .L14
movapd %xmm1, %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L14
.L23:
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8doublingiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8doublingiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void doubling(int n, float *a) {
int tid = blockDim.x*blockIdx.x + threadIdx.x;
int i;
while(tid < n) {
a[tid] *= 2;
for(i=0; i<1000; i++) a[tid] *= 1;
tid += blockDim.x * gridDim.x;
}
}
int main() {
int i;
int n=65535*3500;
float *a, *a_dev;
a = (float *)malloc(n*sizeof(float));
cudaMalloc((void**)&a_dev, n*sizeof(float));
for(i=0; i<n; i++) a[i] = 1.;
cudaMemcpy(a_dev, a, n*sizeof(float), cudaMemcpyHostToDevice);
doubling<<<65535, 256>>>(n, a_dev);
cudaMemcpy(a, a_dev, n*sizeof(float), cudaMemcpyDeviceToHost);
for(i=0; i<n; i++) {
if(abs(a[i] - 2.) > 1e-5) printf("a[%d] = %g\n", i, a[i]);
}
free(a);
cudaFree(a_dev);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void doubling(int n, float *a) {
int tid = blockDim.x*blockIdx.x + threadIdx.x;
int i;
while(tid < n) {
a[tid] *= 2;
for(i=0; i<1000; i++) a[tid] *= 1;
tid += blockDim.x * gridDim.x;
}
}
int main() {
int i;
int n=65535*3500;
float *a, *a_dev;
a = (float *)malloc(n*sizeof(float));
hipMalloc((void**)&a_dev, n*sizeof(float));
for(i=0; i<n; i++) a[i] = 1.;
hipMemcpy(a_dev, a, n*sizeof(float), hipMemcpyHostToDevice);
doubling<<<65535, 256>>>(n, a_dev);
hipMemcpy(a, a_dev, n*sizeof(float), hipMemcpyDeviceToHost);
for(i=0; i<n; i++) {
if(abs(a[i] - 2.) > 1e-5) printf("a[%d] = %g\n", i, a[i]);
}
free(a);
hipFree(a_dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void doubling(int n, float *a) {
int tid = blockDim.x*blockIdx.x + threadIdx.x;
int i;
while(tid < n) {
a[tid] *= 2;
for(i=0; i<1000; i++) a[tid] *= 1;
tid += blockDim.x * gridDim.x;
}
}
int main() {
int i;
int n=65535*3500;
float *a, *a_dev;
a = (float *)malloc(n*sizeof(float));
hipMalloc((void**)&a_dev, n*sizeof(float));
for(i=0; i<n; i++) a[i] = 1.;
hipMemcpy(a_dev, a, n*sizeof(float), hipMemcpyHostToDevice);
doubling<<<65535, 256>>>(n, a_dev);
hipMemcpy(a, a_dev, n*sizeof(float), hipMemcpyDeviceToHost);
for(i=0; i<n; i++) {
if(abs(a[i] - 2.) > 1e-5) printf("a[%d] = %g\n", i, a[i]);
}
free(a);
hipFree(a_dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8doublingiPf
.globl _Z8doublingiPf
.p2align 8
.type _Z8doublingiPf,@function
_Z8doublingiPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s5
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v0 :: v_dual_add_nc_u32 v1, s2, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8doublingiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8doublingiPf, .Lfunc_end0-_Z8doublingiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8doublingiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8doublingiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void doubling(int n, float *a) {
int tid = blockDim.x*blockIdx.x + threadIdx.x;
int i;
while(tid < n) {
a[tid] *= 2;
for(i=0; i<1000; i++) a[tid] *= 1;
tid += blockDim.x * gridDim.x;
}
}
int main() {
int i;
int n=65535*3500;
float *a, *a_dev;
a = (float *)malloc(n*sizeof(float));
hipMalloc((void**)&a_dev, n*sizeof(float));
for(i=0; i<n; i++) a[i] = 1.;
hipMemcpy(a_dev, a, n*sizeof(float), hipMemcpyHostToDevice);
doubling<<<65535, 256>>>(n, a_dev);
hipMemcpy(a, a_dev, n*sizeof(float), hipMemcpyDeviceToHost);
for(i=0; i<n; i++) {
if(abs(a[i] - 2.) > 1e-5) printf("a[%d] = %g\n", i, a[i]);
}
free(a);
hipFree(a_dev);
return 0;
} | .text
.file "doubling.hip"
.globl _Z23__device_stub__doublingiPf # -- Begin function _Z23__device_stub__doublingiPf
.p2align 4, 0x90
.type _Z23__device_stub__doublingiPf,@function
_Z23__device_stub__doublingiPf: # @_Z23__device_stub__doublingiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8doublingiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__doublingiPf, .Lfunc_end0-_Z23__device_stub__doublingiPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xc000000000000000 # double -2
.LCPI1_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $917490000, %edi # imm = 0x36AFC950
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $917490000, %esi # imm = 0x36AFC950
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $229372500, %rax # imm = 0xDABF254
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $917490000, %edx # imm = 0x36AFC950
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 65279(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movl $229372500, 20(%rsp) # imm = 0xDABF254
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8doublingiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $917490000, %edx # imm = 0x36AFC950
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI1_2(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r14
cmpq $229372500, %r14 # imm = 0xDABF254
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm2, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
jbe .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movsd .LCPI1_2(%rip), %xmm4 # xmm4 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB1_7
.LBB1_8:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8doublingiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8doublingiPf,@object # @_Z8doublingiPf
.section .rodata,"a",@progbits
.globl _Z8doublingiPf
.p2align 3, 0x0
_Z8doublingiPf:
.quad _Z23__device_stub__doublingiPf
.size _Z8doublingiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d] = %g\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8doublingiPf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__doublingiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8doublingiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8doublingiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*00d0*/ FADD R5, R4, R4 ; /* 0x0000000404057221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*00f0*/ @!P0 BRA 0x70 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8doublingiPf
.globl _Z8doublingiPf
.p2align 8
.type _Z8doublingiPf,@function
_Z8doublingiPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s5
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v0 :: v_dual_add_nc_u32 v1, s2, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8doublingiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8doublingiPf, .Lfunc_end0-_Z8doublingiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8doublingiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8doublingiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007d297_00000000-6_doubling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8doublingiPfiPf
.type _Z28__device_stub__Z8doublingiPfiPf, @function
_Z28__device_stub__Z8doublingiPfiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8doublingiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8doublingiPfiPf, .-_Z28__device_stub__Z8doublingiPfiPf
.globl _Z8doublingiPf
.type _Z8doublingiPf, @function
_Z8doublingiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8doublingiPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8doublingiPf, .-_Z8doublingiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "a[%d] = %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $917490000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $917490000, %esi
call cudaMalloc@PLT
movq %rbp, %rax
leaq 917490000(%rbp), %rdx
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $1, %ecx
movl $917490000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $65535, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $2, %ecx
movl $917490000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %r12
jmp .L16
.L22:
movq 8(%rsp), %rsi
movl $229372500, %edi
call _Z28__device_stub__Z8doublingiPfiPf
jmp .L13
.L14:
addq $1, %rbx
cmpq $229372500, %rbx
je .L23
.L16:
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx,4), %xmm1
movapd %xmm1, %xmm0
subsd .LC1(%rip), %xmm0
andpd .LC2(%rip), %xmm0
comisd .LC3(%rip), %xmm0
jbe .L14
movapd %xmm1, %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L14
.L23:
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8doublingiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8doublingiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "doubling.hip"
.globl _Z23__device_stub__doublingiPf # -- Begin function _Z23__device_stub__doublingiPf
.p2align 4, 0x90
.type _Z23__device_stub__doublingiPf,@function
_Z23__device_stub__doublingiPf: # @_Z23__device_stub__doublingiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8doublingiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__doublingiPf, .Lfunc_end0-_Z23__device_stub__doublingiPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xc000000000000000 # double -2
.LCPI1_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $917490000, %edi # imm = 0x36AFC950
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $917490000, %esi # imm = 0x36AFC950
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $229372500, %rax # imm = 0xDABF254
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $917490000, %edx # imm = 0x36AFC950
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 65279(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movl $229372500, 20(%rsp) # imm = 0xDABF254
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8doublingiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $917490000, %edx # imm = 0x36AFC950
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI1_2(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r14
cmpq $229372500, %r14 # imm = 0xDABF254
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm2, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
jbe .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movsd .LCPI1_2(%rip), %xmm4 # xmm4 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB1_7
.LBB1_8:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8doublingiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8doublingiPf,@object # @_Z8doublingiPf
.section .rodata,"a",@progbits
.globl _Z8doublingiPf
.p2align 3, 0x0
_Z8doublingiPf:
.quad _Z23__device_stub__doublingiPf
.size _Z8doublingiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d] = %g\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8doublingiPf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__doublingiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8doublingiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void DataPointMap(int size, const double *inputX, const double *inputY, double *output, const double *inFreeArray, int length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < size) {
// copy int array
const double *inArrayBody = &inputX[ix* length];
double *outArrayBody = &output[ix* length];
for (long i = 0; i < length; i++) {
outArrayBody[i] = inArrayBody[i] + inFreeArray[i];
}
}
} | code for sm_80
Function : _Z12DataPointMapiPKdS0_PdS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0060*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a25 */
/* 0x001fca00078e0002 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fc80003f06070 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R3, UR4, PT, P0 ; /* 0x0000000403007c0c */
/* 0x000fda000bf06300 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fca00078e00ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, P0, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007f1e0ff */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0100*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0120*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IADD3.X R4, R9, -0x1, RZ, P0, !PT ; /* 0xffffffff09047810 */
/* 0x000fe400007fe4ff */
/*0140*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND.EX P1, PT, R4, RZ, PT, P1 ; /* 0x000000ff0400720c */
/* 0x000fc40003f26110 */
/*0160*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05070 */
/*0170*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fce0003f05300 */
/*0180*/ @!P1 BRA 0x490 ; /* 0x0000030000009947 */
/* 0x000fec0003800000 */
/*0190*/ IMAD R6, R3, c[0x0][0x188], RZ ; /* 0x0000620003067a24 */
/* 0x000fe200078e02ff */
/*01a0*/ IADD3 R8, P1, R0, -c[0x0][0x188], RZ ; /* 0x8000620000087a10 */
/* 0x000fe20007f3e0ff */
/*01b0*/ IMAD.WIDE.U32 R4, R2.reuse, c[0x0][0x188], RZ ; /* 0x0000620002047a25 */
/* 0x040fe200078e00ff */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01d0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01e0*/ IMAD R7, R2, R9, R6 ; /* 0x0000000902077224 */
/* 0x000fe200078e0206 */
/*01f0*/ LEA R14, P2, R4, 0x10, 0x3 ; /* 0x00000010040e7811 */
/* 0x000fe200078418ff */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.IADD R5, R5, 0x1, R7 ; /* 0x0000000105057824 */
/* 0x000fe200078e0207 */
/*0220*/ IADD3 R13, P3, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0d7a10 */
/* 0x000fe20007f7e0ff */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fc400078e00ff */
/*0240*/ IMAD.X R20, RZ, RZ, ~R9, P1 ; /* 0x000000ffff147224 */
/* 0x000fe200008e0e09 */
/*0250*/ LEA.HI.X R4, R4, RZ, R5, 0x3, P2 ; /* 0x000000ff04047211 */
/* 0x000fe400010f1c05 */
/*0260*/ IADD3 R14, P2, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0e7a10 */
/* 0x000fe40007f5e0ff */
/*0270*/ IADD3.X R5, R4.reuse, c[0x0][0x16c], RZ, P3, !PT ; /* 0x00005b0004057a10 */
/* 0x040fe40001ffe4ff */
/*0280*/ IADD3.X R15, R4, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00040f7a10 */
/* 0x000fe400017fe4ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R13 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000d */
/*02a0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000008060a7981 */
/* 0x004ea8000c1e1b00 */
/*02b0*/ LDG.E.64 R12, [R4.64+-0x10] ; /* 0xfffff008040c7981 */
/* 0x000ea4000c1e1b00 */
/*02c0*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x004044000000000c */
/*02d0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000e */
/*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e000f */
/*02f0*/ STG.E.64 [R10.64+-0x10], R12 ; /* 0xfffff00c0a007986 */
/* 0x0021e8000c101b08 */
/*0300*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000808060e7981 */
/* 0x000ea8000c1e1b00 */
/*0310*/ LDG.E.64 R16, [R4.64+-0x8] ; /* 0xfffff80804107981 */
/* 0x000ea4000c1e1b00 */
/*0320*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x004e4e0000000010 */
/*0330*/ STG.E.64 [R10.64+-0x8], R14 ; /* 0xfffff80e0a007986 */
/* 0x0023e8000c101b08 */
/*0340*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100806107981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000804127981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0370*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0380*/ DADD R16, R16, R18 ; /* 0x0000000010107229 */
/* 0x004e8e0000000012 */
/*0390*/ STG.E.64 [R10.64], R16 ; /* 0x000000100a007986 */
/* 0x0045e8000c101b08 */
/*03a0*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180806127981 */
/* 0x000728000c1e1b00 */
/*03b0*/ LDG.E.64 R22, [R4.64+0x8] ; /* 0x0000080804167981 */
/* 0x000b22000c1e1b00 */
/*03c0*/ IADD3 R12, P2, R8, UR4, RZ ; /* 0x00000004080c7c10 */
/* 0x001fe4000ff5e0ff */
/*03d0*/ IADD3 R14, P3, R10, 0x20, RZ ; /* 0x000000200a0e7810 */
/* 0x002fc40007f7e0ff */
/*03e0*/ ISETP.NE.U32.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25070 */
/*03f0*/ IADD3.X R12, R20, UR5, RZ, P2, !PT ; /* 0x00000005140c7c10 */
/* 0x000fe200097fe4ff */
/*0400*/ IMAD.X R15, RZ, RZ, R11, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200018e060b */
/*0410*/ IADD3 R13, P2, R4, 0x20, RZ ; /* 0x00000020040d7810 */
/* 0x000fe40007f5e0ff */
/*0420*/ ISETP.NE.AND.EX P1, PT, R12, RZ, PT, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25310 */
/*0430*/ IADD3 R6, P4, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x008fe20007f9e0ff */
/*0440*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x020fc800010e0605 */
/*0450*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*0460*/ DADD R18, R18, R22 ; /* 0x0000000012127229 */
/* 0x010e0e0000000016 */
/*0470*/ STG.E.64 [R10.64+0x8], R18 ; /* 0x000008120a007986 */
/* 0x0015e2000c101b08 */
/*0480*/ @P1 BRA 0x290 ; /* 0xfffffe0000001947 */
/* 0x000fea000383ffff */
/*0490*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04a0*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fe200078e02ff */
/*04b0*/ IADD3 R0, P2, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fe20007f5e0ff */
/*04c0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*04d0*/ ULDC.64 UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe20000000a00 */
/*04e0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*04f0*/ ULEA UR6, UP0, UR4, UR6, 0x3 ; /* 0x0000000604067291 */
/* 0x000fe2000f80183f */
/*0500*/ IMAD R9, R2.reuse, R9, R3 ; /* 0x0000000902097224 */
/* 0x040fe400078e0203 */
/*0510*/ IMAD.WIDE.U32 R2, R2, c[0x0][0x188], R4 ; /* 0x0000620002027a25 */
/* 0x000fe200078e0004 */
/*0520*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ; /* 0x0000000704047291 */
/* 0x000fc600080f1c05 */
/*0530*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fe400078e0203 */
/*0540*/ IMAD.SHL.U32 R9, R2.reuse, 0x8, RZ ; /* 0x0000000802097824 */
/* 0x040fe400078e00ff */
/*0550*/ IMAD.X R8, RZ, RZ, -0x1, P2 ; /* 0xffffffffff087424 */
/* 0x000fe200010e06ff */
/*0560*/ SHF.L.U64.HI R2, R2, 0x3, R3 ; /* 0x0000000302027819 */
/* 0x000fe40000010203 */
/*0570*/ IADD3 R11, P0, R9.reuse, c[0x0][0x178], RZ ; /* 0x00005e00090b7a10 */
/* 0x044fe40007f1e0ff */
/*0580*/ IADD3 R9, P1, R9, c[0x0][0x168], RZ ; /* 0x00005a0009097a10 */
/* 0x000fe40007f3e0ff */
/*0590*/ IADD3.X R12, R2, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f00020c7a10 */
/* 0x000fc400007fe4ff */
/*05a0*/ IADD3.X R10, R2, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b00020a7a10 */
/* 0x000fc60000ffe4ff */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*05c0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*05d0*/ IMAD.U32 R6, RZ, RZ, UR6 ; /* 0x00000006ff067e24 */
/* 0x000fe4000f8e00ff */
/*05e0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe4000f8e00ff */
/*05f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea8000c1e1b00 */
/*0600*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000806027981 */
/* 0x000ea2000c1e1b00 */
/*0610*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R9, P2, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc60007f5e0ff */
/*0640*/ IMAD.X R8, RZ, RZ, R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0608 */
/*0650*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0660*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe200087fe43f */
/*0670*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400010e060a */
/*0680*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fe20003f05300 */
/*0690*/ DADD R2, R2, R4 ; /* 0x0000000002027229 */
/* 0x0040640000000004 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x001fe200078e000b */
/*06b0*/ IADD3 R11, P1, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe20007f3e0ff */
/*06c0*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fc800078e000c */
/*06d0*/ IMAD.X R12, RZ, RZ, R12, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe200008e060c */
/*06e0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0021e6000c101b08 */
/*06f0*/ @P0 BRA 0x5b0 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x710; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void DataPointMap(int size, const double *inputX, const double *inputY, double *output, const double *inFreeArray, int length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < size) {
// copy int array
const double *inArrayBody = &inputX[ix* length];
double *outArrayBody = &output[ix* length];
for (long i = 0; i < length; i++) {
outArrayBody[i] = inArrayBody[i] + inFreeArray[i];
}
}
} | .file "tmpxft_001a8240_00000000-6_DataPointMap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i
.type _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i, @function
_Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 40(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12DataPointMapiPKdS0_PdS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i, .-_Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i
.globl _Z12DataPointMapiPKdS0_PdS0_i
.type _Z12DataPointMapiPKdS0_PdS0_i, @function
_Z12DataPointMapiPKdS0_PdS0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12DataPointMapiPKdS0_PdS0_i, .-_Z12DataPointMapiPKdS0_PdS0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12DataPointMapiPKdS0_PdS0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12DataPointMapiPKdS0_PdS0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void DataPointMap(int size, const double *inputX, const double *inputY, double *output, const double *inFreeArray, int length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < size) {
// copy int array
const double *inArrayBody = &inputX[ix* length];
double *outArrayBody = &output[ix* length];
for (long i = 0; i < length; i++) {
outArrayBody[i] = inArrayBody[i] + inFreeArray[i];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DataPointMap(int size, const double *inputX, const double *inputY, double *output, const double *inFreeArray, int length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < size) {
// copy int array
const double *inArrayBody = &inputX[ix* length];
double *outArrayBody = &output[ix* length];
for (long i = 0; i < length; i++) {
outArrayBody[i] = inArrayBody[i] + inFreeArray[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DataPointMap(int size, const double *inputX, const double *inputY, double *output, const double *inFreeArray, int length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < size) {
// copy int array
const double *inArrayBody = &inputX[ix* length];
double *outArrayBody = &output[ix* length];
for (long i = 0; i < length; i++) {
outArrayBody[i] = inArrayBody[i] + inFreeArray[i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12DataPointMapiPKdS0_PdS0_i
.globl _Z12DataPointMapiPKdS0_PdS0_i
.p2align 8
.type _Z12DataPointMapiPKdS0_PdS0_i,@function
_Z12DataPointMapiPKdS0_PdS0_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b32 s4, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s5, s4, 31
s_load_b64 s[6:7], s[0:1], 0x8
v_mul_lo_u32 v3, v3, s4
v_mul_lo_u32 v4, v2, s5
v_mad_u64_u32 v[0:1], null, v2, s4, 0
s_load_b128 s[0:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v1, v1, v4, v3
v_mov_b32_e32 v4, 0
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b64 v[5:6], v[0:1], off
global_load_b64 v[7:8], v4, s[2:3]
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
global_store_b64 v[2:3], v[5:6], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12DataPointMapiPKdS0_PdS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12DataPointMapiPKdS0_PdS0_i, .Lfunc_end0-_Z12DataPointMapiPKdS0_PdS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12DataPointMapiPKdS0_PdS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12DataPointMapiPKdS0_PdS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DataPointMap(int size, const double *inputX, const double *inputY, double *output, const double *inFreeArray, int length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < size) {
// copy int array
const double *inArrayBody = &inputX[ix* length];
double *outArrayBody = &output[ix* length];
for (long i = 0; i < length; i++) {
outArrayBody[i] = inArrayBody[i] + inFreeArray[i];
}
}
} | .text
.file "DataPointMap.hip"
.globl _Z27__device_stub__DataPointMapiPKdS0_PdS0_i # -- Begin function _Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.p2align 4, 0x90
.type _Z27__device_stub__DataPointMapiPKdS0_PdS0_i,@function
_Z27__device_stub__DataPointMapiPKdS0_PdS0_i: # @_Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12DataPointMapiPKdS0_PdS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__DataPointMapiPKdS0_PdS0_i, .Lfunc_end0-_Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12DataPointMapiPKdS0_PdS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12DataPointMapiPKdS0_PdS0_i,@object # @_Z12DataPointMapiPKdS0_PdS0_i
.section .rodata,"a",@progbits
.globl _Z12DataPointMapiPKdS0_PdS0_i
.p2align 3, 0x0
_Z12DataPointMapiPKdS0_PdS0_i:
.quad _Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.size _Z12DataPointMapiPKdS0_PdS0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12DataPointMapiPKdS0_PdS0_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12DataPointMapiPKdS0_PdS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12DataPointMapiPKdS0_PdS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0060*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a25 */
/* 0x001fca00078e0002 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fc80003f06070 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R3, UR4, PT, P0 ; /* 0x0000000403007c0c */
/* 0x000fda000bf06300 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fca00078e00ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, P0, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007f1e0ff */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0100*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0120*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IADD3.X R4, R9, -0x1, RZ, P0, !PT ; /* 0xffffffff09047810 */
/* 0x000fe400007fe4ff */
/*0140*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND.EX P1, PT, R4, RZ, PT, P1 ; /* 0x000000ff0400720c */
/* 0x000fc40003f26110 */
/*0160*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05070 */
/*0170*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fce0003f05300 */
/*0180*/ @!P1 BRA 0x490 ; /* 0x0000030000009947 */
/* 0x000fec0003800000 */
/*0190*/ IMAD R6, R3, c[0x0][0x188], RZ ; /* 0x0000620003067a24 */
/* 0x000fe200078e02ff */
/*01a0*/ IADD3 R8, P1, R0, -c[0x0][0x188], RZ ; /* 0x8000620000087a10 */
/* 0x000fe20007f3e0ff */
/*01b0*/ IMAD.WIDE.U32 R4, R2.reuse, c[0x0][0x188], RZ ; /* 0x0000620002047a25 */
/* 0x040fe200078e00ff */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01d0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01e0*/ IMAD R7, R2, R9, R6 ; /* 0x0000000902077224 */
/* 0x000fe200078e0206 */
/*01f0*/ LEA R14, P2, R4, 0x10, 0x3 ; /* 0x00000010040e7811 */
/* 0x000fe200078418ff */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.IADD R5, R5, 0x1, R7 ; /* 0x0000000105057824 */
/* 0x000fe200078e0207 */
/*0220*/ IADD3 R13, P3, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0d7a10 */
/* 0x000fe20007f7e0ff */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fc400078e00ff */
/*0240*/ IMAD.X R20, RZ, RZ, ~R9, P1 ; /* 0x000000ffff147224 */
/* 0x000fe200008e0e09 */
/*0250*/ LEA.HI.X R4, R4, RZ, R5, 0x3, P2 ; /* 0x000000ff04047211 */
/* 0x000fe400010f1c05 */
/*0260*/ IADD3 R14, P2, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0e7a10 */
/* 0x000fe40007f5e0ff */
/*0270*/ IADD3.X R5, R4.reuse, c[0x0][0x16c], RZ, P3, !PT ; /* 0x00005b0004057a10 */
/* 0x040fe40001ffe4ff */
/*0280*/ IADD3.X R15, R4, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00040f7a10 */
/* 0x000fe400017fe4ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R13 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000d */
/*02a0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000008060a7981 */
/* 0x004ea8000c1e1b00 */
/*02b0*/ LDG.E.64 R12, [R4.64+-0x10] ; /* 0xfffff008040c7981 */
/* 0x000ea4000c1e1b00 */
/*02c0*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x004044000000000c */
/*02d0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000e */
/*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e000f */
/*02f0*/ STG.E.64 [R10.64+-0x10], R12 ; /* 0xfffff00c0a007986 */
/* 0x0021e8000c101b08 */
/*0300*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000808060e7981 */
/* 0x000ea8000c1e1b00 */
/*0310*/ LDG.E.64 R16, [R4.64+-0x8] ; /* 0xfffff80804107981 */
/* 0x000ea4000c1e1b00 */
/*0320*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x004e4e0000000010 */
/*0330*/ STG.E.64 [R10.64+-0x8], R14 ; /* 0xfffff80e0a007986 */
/* 0x0023e8000c101b08 */
/*0340*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100806107981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000804127981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0370*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0380*/ DADD R16, R16, R18 ; /* 0x0000000010107229 */
/* 0x004e8e0000000012 */
/*0390*/ STG.E.64 [R10.64], R16 ; /* 0x000000100a007986 */
/* 0x0045e8000c101b08 */
/*03a0*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180806127981 */
/* 0x000728000c1e1b00 */
/*03b0*/ LDG.E.64 R22, [R4.64+0x8] ; /* 0x0000080804167981 */
/* 0x000b22000c1e1b00 */
/*03c0*/ IADD3 R12, P2, R8, UR4, RZ ; /* 0x00000004080c7c10 */
/* 0x001fe4000ff5e0ff */
/*03d0*/ IADD3 R14, P3, R10, 0x20, RZ ; /* 0x000000200a0e7810 */
/* 0x002fc40007f7e0ff */
/*03e0*/ ISETP.NE.U32.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25070 */
/*03f0*/ IADD3.X R12, R20, UR5, RZ, P2, !PT ; /* 0x00000005140c7c10 */
/* 0x000fe200097fe4ff */
/*0400*/ IMAD.X R15, RZ, RZ, R11, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200018e060b */
/*0410*/ IADD3 R13, P2, R4, 0x20, RZ ; /* 0x00000020040d7810 */
/* 0x000fe40007f5e0ff */
/*0420*/ ISETP.NE.AND.EX P1, PT, R12, RZ, PT, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25310 */
/*0430*/ IADD3 R6, P4, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x008fe20007f9e0ff */
/*0440*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x020fc800010e0605 */
/*0450*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*0460*/ DADD R18, R18, R22 ; /* 0x0000000012127229 */
/* 0x010e0e0000000016 */
/*0470*/ STG.E.64 [R10.64+0x8], R18 ; /* 0x000008120a007986 */
/* 0x0015e2000c101b08 */
/*0480*/ @P1 BRA 0x290 ; /* 0xfffffe0000001947 */
/* 0x000fea000383ffff */
/*0490*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04a0*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fe200078e02ff */
/*04b0*/ IADD3 R0, P2, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fe20007f5e0ff */
/*04c0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*04d0*/ ULDC.64 UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe20000000a00 */
/*04e0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*04f0*/ ULEA UR6, UP0, UR4, UR6, 0x3 ; /* 0x0000000604067291 */
/* 0x000fe2000f80183f */
/*0500*/ IMAD R9, R2.reuse, R9, R3 ; /* 0x0000000902097224 */
/* 0x040fe400078e0203 */
/*0510*/ IMAD.WIDE.U32 R2, R2, c[0x0][0x188], R4 ; /* 0x0000620002027a25 */
/* 0x000fe200078e0004 */
/*0520*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ; /* 0x0000000704047291 */
/* 0x000fc600080f1c05 */
/*0530*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fe400078e0203 */
/*0540*/ IMAD.SHL.U32 R9, R2.reuse, 0x8, RZ ; /* 0x0000000802097824 */
/* 0x040fe400078e00ff */
/*0550*/ IMAD.X R8, RZ, RZ, -0x1, P2 ; /* 0xffffffffff087424 */
/* 0x000fe200010e06ff */
/*0560*/ SHF.L.U64.HI R2, R2, 0x3, R3 ; /* 0x0000000302027819 */
/* 0x000fe40000010203 */
/*0570*/ IADD3 R11, P0, R9.reuse, c[0x0][0x178], RZ ; /* 0x00005e00090b7a10 */
/* 0x044fe40007f1e0ff */
/*0580*/ IADD3 R9, P1, R9, c[0x0][0x168], RZ ; /* 0x00005a0009097a10 */
/* 0x000fe40007f3e0ff */
/*0590*/ IADD3.X R12, R2, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f00020c7a10 */
/* 0x000fc400007fe4ff */
/*05a0*/ IADD3.X R10, R2, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b00020a7a10 */
/* 0x000fc60000ffe4ff */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*05c0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*05d0*/ IMAD.U32 R6, RZ, RZ, UR6 ; /* 0x00000006ff067e24 */
/* 0x000fe4000f8e00ff */
/*05e0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe4000f8e00ff */
/*05f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea8000c1e1b00 */
/*0600*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000806027981 */
/* 0x000ea2000c1e1b00 */
/*0610*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R9, P2, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc60007f5e0ff */
/*0640*/ IMAD.X R8, RZ, RZ, R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0608 */
/*0650*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0660*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe200087fe43f */
/*0670*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400010e060a */
/*0680*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fe20003f05300 */
/*0690*/ DADD R2, R2, R4 ; /* 0x0000000002027229 */
/* 0x0040640000000004 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x001fe200078e000b */
/*06b0*/ IADD3 R11, P1, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe20007f3e0ff */
/*06c0*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fc800078e000c */
/*06d0*/ IMAD.X R12, RZ, RZ, R12, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe200008e060c */
/*06e0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0021e6000c101b08 */
/*06f0*/ @P0 BRA 0x5b0 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x710; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12DataPointMapiPKdS0_PdS0_i
.globl _Z12DataPointMapiPKdS0_PdS0_i
.p2align 8
.type _Z12DataPointMapiPKdS0_PdS0_i,@function
_Z12DataPointMapiPKdS0_PdS0_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b32 s4, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s5, s4, 31
s_load_b64 s[6:7], s[0:1], 0x8
v_mul_lo_u32 v3, v3, s4
v_mul_lo_u32 v4, v2, s5
v_mad_u64_u32 v[0:1], null, v2, s4, 0
s_load_b128 s[0:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v1, v1, v4, v3
v_mov_b32_e32 v4, 0
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b64 v[5:6], v[0:1], off
global_load_b64 v[7:8], v4, s[2:3]
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
global_store_b64 v[2:3], v[5:6], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12DataPointMapiPKdS0_PdS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12DataPointMapiPKdS0_PdS0_i, .Lfunc_end0-_Z12DataPointMapiPKdS0_PdS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12DataPointMapiPKdS0_PdS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12DataPointMapiPKdS0_PdS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a8240_00000000-6_DataPointMap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i
.type _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i, @function
_Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 40(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12DataPointMapiPKdS0_PdS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i, .-_Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i
.globl _Z12DataPointMapiPKdS0_PdS0_i
.type _Z12DataPointMapiPKdS0_PdS0_i, @function
_Z12DataPointMapiPKdS0_PdS0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12DataPointMapiPKdS0_PdS0_iiPKdS0_PdS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12DataPointMapiPKdS0_PdS0_i, .-_Z12DataPointMapiPKdS0_PdS0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12DataPointMapiPKdS0_PdS0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12DataPointMapiPKdS0_PdS0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DataPointMap.hip"
.globl _Z27__device_stub__DataPointMapiPKdS0_PdS0_i # -- Begin function _Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.p2align 4, 0x90
.type _Z27__device_stub__DataPointMapiPKdS0_PdS0_i,@function
_Z27__device_stub__DataPointMapiPKdS0_PdS0_i: # @_Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12DataPointMapiPKdS0_PdS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__DataPointMapiPKdS0_PdS0_i, .Lfunc_end0-_Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12DataPointMapiPKdS0_PdS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12DataPointMapiPKdS0_PdS0_i,@object # @_Z12DataPointMapiPKdS0_PdS0_i
.section .rodata,"a",@progbits
.globl _Z12DataPointMapiPKdS0_PdS0_i
.p2align 3, 0x0
_Z12DataPointMapiPKdS0_PdS0_i:
.quad _Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.size _Z12DataPointMapiPKdS0_PdS0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12DataPointMapiPKdS0_PdS0_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__DataPointMapiPKdS0_PdS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12DataPointMapiPKdS0_PdS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*author: Zeke Elkins
*date: 3/27/14
*description: a CUDA program to add two vectors of integers
*/
#define N 512 //the size of the vector
#include <iostream>
using namespace std;
//device code to add two arrays of numbers;
//each block handles a different element of the array
__global__ void add(int *a, int *b, int *c) {
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
//method that will generate n random integers between 0 and 99
//values are stored in the int array a
void random_ints(int* a, int n) {
int i;
for (i=0; i<n; ++i) {
a[i] = rand() % 100;
}
}
int main(void) {
int *a, *b, *c; //host copies of a, b, c NOTE THESE ARE NOW POINTERS
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int); //size of N integers
//allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
//allocate space for host copies of a, b, c and setup input vals
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
random_ints(b, N);
c = (int *)malloc(size);
//copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// launch add() kernel on GPU with N threads
add<<<1,N>>>(d_a, d_b, d_c);
//copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
//print out the results
for (int i=0; i<N; i++) {
cout << a[i] << " plus " << b[i] << " equals " << c[i] << endl;
}
//cleanup
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*author: Zeke Elkins
*date: 3/27/14
*description: a CUDA program to add two vectors of integers
*/
#define N 512 //the size of the vector
#include <iostream>
using namespace std;
//device code to add two arrays of numbers;
//each block handles a different element of the array
__global__ void add(int *a, int *b, int *c) {
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
//method that will generate n random integers between 0 and 99
//values are stored in the int array a
void random_ints(int* a, int n) {
int i;
for (i=0; i<n; ++i) {
a[i] = rand() % 100;
}
}
int main(void) {
int *a, *b, *c; //host copies of a, b, c NOTE THESE ARE NOW POINTERS
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int); //size of N integers
//allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
//allocate space for host copies of a, b, c and setup input vals
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
random_ints(b, N);
c = (int *)malloc(size);
//copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// launch add() kernel on GPU with N threads
add<<<1,N>>>(d_a, d_b, d_c);
//copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
//print out the results
for (int i=0; i<N; i++) {
cout << a[i] << " plus " << b[i] << " equals " << c[i] << endl;
}
//cleanup
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | .file "tmpxft_0014fbf9_00000000-6_VectorAddition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " plus "
.LC1:
.string " equals "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r14
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %r15
movl $1, %ecx
movl $2048, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L20:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
jmp .L25
.L29:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L33:
movzbl 67(%r12), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbx
cmpq $2048, %rbx
je .L31
.L25:
movl (%r14,%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L32
cmpb $0, 56(%r12)
jne .L33
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L31:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*author: Zeke Elkins
*date: 3/27/14
*description: a CUDA program to add two vectors of integers
*/
#define N 512 //the size of the vector
#include <iostream>
using namespace std;
//device code to add two arrays of numbers;
//each block handles a different element of the array
__global__ void add(int *a, int *b, int *c) {
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
//method that will generate n random integers between 0 and 99
//values are stored in the int array a
void random_ints(int* a, int n) {
int i;
for (i=0; i<n; ++i) {
a[i] = rand() % 100;
}
}
int main(void) {
int *a, *b, *c; //host copies of a, b, c NOTE THESE ARE NOW POINTERS
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int); //size of N integers
//allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
//allocate space for host copies of a, b, c and setup input vals
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
random_ints(b, N);
c = (int *)malloc(size);
//copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// launch add() kernel on GPU with N threads
add<<<1,N>>>(d_a, d_b, d_c);
//copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
//print out the results
for (int i=0; i<N; i++) {
cout << a[i] << " plus " << b[i] << " equals " << c[i] << endl;
}
//cleanup
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | /*author: Zeke Elkins
*date: 3/27/14
*description: a CUDA program to add two vectors of integers
*/
#define N 512 //the size of the vector
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
//device code to add two arrays of numbers;
//each block handles a different element of the array
__global__ void add(int *a, int *b, int *c) {
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
//method that will generate n random integers between 0 and 99
//values are stored in the int array a
void random_ints(int* a, int n) {
int i;
for (i=0; i<n; ++i) {
a[i] = rand() % 100;
}
}
int main(void) {
int *a, *b, *c; //host copies of a, b, c NOTE THESE ARE NOW POINTERS
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int); //size of N integers
//allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//allocate space for host copies of a, b, c and setup input vals
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
random_ints(b, N);
c = (int *)malloc(size);
//copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// launch add() kernel on GPU with N threads
add<<<1,N>>>(d_a, d_b, d_c);
//copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
//print out the results
for (int i=0; i<N; i++) {
cout << a[i] << " plus " << b[i] << " equals " << c[i] << endl;
}
//cleanup
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*author: Zeke Elkins
*date: 3/27/14
*description: a CUDA program to add two vectors of integers
*/
#define N 512 //the size of the vector
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
//device code to add two arrays of numbers;
//each block handles a different element of the array
__global__ void add(int *a, int *b, int *c) {
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
//method that will generate n random integers between 0 and 99
//values are stored in the int array a
void random_ints(int* a, int n) {
int i;
for (i=0; i<n; ++i) {
a[i] = rand() % 100;
}
}
int main(void) {
int *a, *b, *c; //host copies of a, b, c NOTE THESE ARE NOW POINTERS
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int); //size of N integers
//allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//allocate space for host copies of a, b, c and setup input vals
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
random_ints(b, N);
c = (int *)malloc(size);
//copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// launch add() kernel on GPU with N threads
add<<<1,N>>>(d_a, d_b, d_c);
//copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
//print out the results
for (int i=0; i<N; i++) {
cout << a[i] << " plus " << b[i] << " equals " << c[i] << endl;
}
//cleanup
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*author: Zeke Elkins
*date: 3/27/14
*description: a CUDA program to add two vectors of integers
*/
#define N 512 //the size of the vector
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
//device code to add two arrays of numbers;
//each block handles a different element of the array
__global__ void add(int *a, int *b, int *c) {
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
//method that will generate n random integers between 0 and 99
//values are stored in the int array a
void random_ints(int* a, int n) {
int i;
for (i=0; i<n; ++i) {
a[i] = rand() % 100;
}
}
int main(void) {
int *a, *b, *c; //host copies of a, b, c NOTE THESE ARE NOW POINTERS
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int); //size of N integers
//allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//allocate space for host copies of a, b, c and setup input vals
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
random_ints(b, N);
c = (int *)malloc(size);
//copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// launch add() kernel on GPU with N threads
add<<<1,N>>>(d_a, d_b, d_c);
//copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
//print out the results
for (int i=0; i<N; i++) {
cout << a[i] << " plus " << b[i] << " equals " << c[i] << endl;
}
//cleanup
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "VectorAddition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $512, %r14 # imm = 0x200
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit30
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_7 Depth=1
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $512, %r13 # imm = 0x200
je .LBB2_12
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_7 Depth=1
cmpb $0, 56(%r12)
je .LBB2_10
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_11
.LBB2_12:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " plus "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " equals "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014fbf9_00000000-6_VectorAddition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " plus "
.LC1:
.string " equals "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r14
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %r15
movl $1, %ecx
movl $2048, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L20:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
jmp .L25
.L29:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L33:
movzbl 67(%r12), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbx
cmpq $2048, %rbx
je .L31
.L25:
movl (%r14,%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L32
cmpb $0, 56(%r12)
jne .L33
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L31:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorAddition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $512, %r14 # imm = 0x200
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit30
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_7 Depth=1
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $512, %r13 # imm = 0x200
je .LBB2_12
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_7 Depth=1
cmpb $0, 56(%r12)
je .LBB2_10
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_11
.LBB2_12:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " plus "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " equals "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
mat_transpose(float *a, float *out, int size_x, int size_y)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
out[j * size_y + i] = a[i * size_y + j];
}
} | code for sm_80
Function : _Z13mat_transposePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x174], R5 ; /* 0x00005d0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
mat_transpose(float *a, float *out, int size_x, int size_y)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
out[j * size_y + i] = a[i * size_y + j];
}
} | .file "tmpxft_00143625_00000000-6_mat_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii
.type _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii, @function
_Z37__device_stub__Z13mat_transposePfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mat_transposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii, .-_Z37__device_stub__Z13mat_transposePfS_iiPfS_ii
.globl _Z13mat_transposePfS_ii
.type _Z13mat_transposePfS_ii, @function
_Z13mat_transposePfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13mat_transposePfS_ii, .-_Z13mat_transposePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13mat_transposePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mat_transposePfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
mat_transpose(float *a, float *out, int size_x, int size_y)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
out[j * size_y + i] = a[i * size_y + j];
}
} | #include <hip/hip_runtime.h>
__global__ void
mat_transpose(float *a, float *out, int size_x, int size_y)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
out[j * size_y + i] = a[i * size_y + j];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_transpose(float *a, float *out, int size_x, int size_y)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
out[j * size_y + i] = a[i * size_y + j];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13mat_transposePfS_ii
.globl _Z13mat_transposePfS_ii
.p2align 8
.type _Z13mat_transposePfS_ii,@function
_Z13mat_transposePfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13mat_transposePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13mat_transposePfS_ii, .Lfunc_end0-_Z13mat_transposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13mat_transposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13mat_transposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_transpose(float *a, float *out, int size_x, int size_y)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
out[j * size_y + i] = a[i * size_y + j];
}
} | .text
.file "mat_transpose.hip"
.globl _Z28__device_stub__mat_transposePfS_ii # -- Begin function _Z28__device_stub__mat_transposePfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__mat_transposePfS_ii,@function
_Z28__device_stub__mat_transposePfS_ii: # @_Z28__device_stub__mat_transposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13mat_transposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__mat_transposePfS_ii, .Lfunc_end0-_Z28__device_stub__mat_transposePfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mat_transposePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13mat_transposePfS_ii,@object # @_Z13mat_transposePfS_ii
.section .rodata,"a",@progbits
.globl _Z13mat_transposePfS_ii
.p2align 3, 0x0
_Z13mat_transposePfS_ii:
.quad _Z28__device_stub__mat_transposePfS_ii
.size _Z13mat_transposePfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13mat_transposePfS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__mat_transposePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13mat_transposePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13mat_transposePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x174], R5 ; /* 0x00005d0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13mat_transposePfS_ii
.globl _Z13mat_transposePfS_ii
.p2align 8
.type _Z13mat_transposePfS_ii,@function
_Z13mat_transposePfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13mat_transposePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13mat_transposePfS_ii, .Lfunc_end0-_Z13mat_transposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13mat_transposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13mat_transposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00143625_00000000-6_mat_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii
.type _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii, @function
_Z37__device_stub__Z13mat_transposePfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mat_transposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii, .-_Z37__device_stub__Z13mat_transposePfS_iiPfS_ii
.globl _Z13mat_transposePfS_ii
.type _Z13mat_transposePfS_ii, @function
_Z13mat_transposePfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13mat_transposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13mat_transposePfS_ii, .-_Z13mat_transposePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13mat_transposePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mat_transposePfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_transpose.hip"
.globl _Z28__device_stub__mat_transposePfS_ii # -- Begin function _Z28__device_stub__mat_transposePfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__mat_transposePfS_ii,@function
_Z28__device_stub__mat_transposePfS_ii: # @_Z28__device_stub__mat_transposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13mat_transposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__mat_transposePfS_ii, .Lfunc_end0-_Z28__device_stub__mat_transposePfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mat_transposePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13mat_transposePfS_ii,@object # @_Z13mat_transposePfS_ii
.section .rodata,"a",@progbits
.globl _Z13mat_transposePfS_ii
.p2align 3, 0x0
_Z13mat_transposePfS_ii:
.quad _Z28__device_stub__mat_transposePfS_ii
.size _Z13mat_transposePfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13mat_transposePfS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__mat_transposePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13mat_transposePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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