system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: Xu Chen (email: hello_master1954@163.com) 2018-09-17
*/
#ifndef __CROSSENTROPY_CUH__
#define __CROSSENTROPY_CUH__
#include "../XTensor.h"
#include "../XDevice.h"
#include "CrossEntropy.cuh"
#include "CrossEntropy.h"
#include "../core/arithmetic/Div.h"
#include "../core/arithmetic/Multiply.h"
#include "../core/arithmetic/MultiplyDim.h"
#include "../core/math/Unary.h"
#include "../core/math/ScaleAndShift.h"
#include "../core/reduce/ReduceSum.h"
#include "../core/reduce/ReduceSumAll.h"
#include "../core/shape/Transpose.h"
#include "../core/shape/Unsqueeze.h"
#include "../core/shape/IsSameShaped.h"
namespace nts{ // namespace nts(NiuTrans.Tensor)
/*
compute the cross entropy loss (cuda version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> loss - compute loss
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
XTensor * loss, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * interBuf1 = NewTensorBufV2(output, output->devID, output->mem);
XTensor * interBuf2 = NewTensorBufV2(output, output->devID, output->mem);
_Log(output, interBuf1);
_Multiply(gold, interBuf1, interBuf2);
if(weight != NULL)
_MultiplyDimMe(interBuf2, weight, n);
_NegateMe(interBuf2);
_ReduceSum(interBuf2, loss, n);
if(padding != NULL)
_MultiplyMe(loss, padding);
DelTensorBuf(interBuf2);
DelTensorBuf(interBuf1);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
}
/*
compute the cross entropy loss (scalar version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> reduceWay - loss compute way, sum or mean
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
<< return - the cross entropy loss that is a scalar
*/
DTYPE _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
LOSS_COMPUTE_WAY reduceWay, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
DTYPE loss = 0;
int order = output->order;
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
int leadingDimSize = output->GetDim(n);
CheckNTErrors(n >= 0 && n < output->order,
"Wrong leadingDim!");
CheckNTErrors(_IsSameShaped(output, gold),
"The output tensor and gold tensor must be of the same size!");
CheckNTErrors(weight == NULL || weight->unitNum == leadingDimSize,
"Wrong weight tensor!");
CheckNTErrors(padding == NULL || padding->order == output->order - 1,
"Wrong padding tensor!");
CheckNTErrors(gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE,
"TODO!");
int * dimSize = new int[output->order - 1];
for (int i = 0; i < order; i++) {
if(i < n)
dimSize[i] = output->dimSize[i];
else if(i > n)
dimSize[i - 1] = output->dimSize[i];
}
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * lossBuf = NewTensorBufV2(output->order - 1, dimSize, output->dataType, output->denseRatio,
output->devID, output->mem);
_CudaCrossEntropyFast(output, gold, lossBuf, weight, padding, leadingDim);
_ReduceSumAll(lossBuf, &loss);
if(reduceWay == REDUCE_MEAN) {
DTYPE nonZeroNum;
if(padding == NULL) {
nonZeroNum = (DTYPE)lossBuf->unitNum;
}
else {
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->LockBuf();
}
XTensor * tmp = NewTensorBufV2(padding, padding->devID, padding->mem);
_IsNonZero(padding, tmp);
_ReduceSumAll(tmp, &nonZeroNum);
DelTensorBuf(tmp);
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->UnlockBuf();
}
}
loss = loss / nonZeroNum;
}
else if(reduceWay == REDUCE_SUM) {
/* don't need to do anything */
}
else {
ShowNTErrors("TODO");
}
delete[] dimSize;
DelTensorBuf(lossBuf);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
return loss;
}
/*
backward computation of cross entropy function
loss = sum_{i} (-t_i * log(y_i))
dE/dy_i = -t_i / y_i
where E is the error(loss) function that measure the errors in y
with respect to gold standard, and y this the model output
>> dedy - dE/dy (for return)
>> output - model prediction
>> gold - gold standard
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyBackward(XTensor * dedy, const XTensor * output,
const XTensor * gold, const XTensor * weight,
XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
_Div(gold, output, dedy);
_NegateMe(dedy);
if(weight != NULL)
_MultiplyDimMe(dedy, weight, n);
if(padding != NULL) {
int paddingOrder = padding->order;
int * paddingDims = new int[paddingOrder];
memcpy(paddingDims, padding->dimSize, padding->order * sizeof(int));
padding->Reshape(padding->unitNum);
int order = dedy->order;
int * dims = new int[order];
memcpy(dims, dedy->dimSize, dedy->order * sizeof(int));
dedy->Reshape(dedy->unitNum/dedy->GetDim(n), dedy->GetDim(n));
_MultiplyDimMe(dedy, padding, 0);
padding->Reshape(paddingOrder, paddingDims);
dedy->Reshape(order, dims);
delete[] paddingDims;
delete[] dims;
}
if(padding != NULL) {
XTensor * tmp = NewTensor(padding);
_IsNonZero(padding, tmp);
DTYPE nonZeroNum;
_ReduceSumAll(tmp, &nonZeroNum);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/nonZeroNum);
delete tmp;
}
else {
int num = dedy->unitNum / dedy->GetDim(n);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/(DTYPE)num);
}
}
} // namespace nts(NiuTrans.Tensor)
#endif // __CROSSENTROPY_CUH__ | .text
.file "CrossEntropy.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.LCPI0_0:
.long 0x3f800000 # float 1
.text
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.p2align 4, 0x90
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i,@function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i: # @_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, %r13
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
testl %r9d, %r9d
jns .LBB0_2
# %bb.1:
movl 76(%rbx), %ebp
decl %ebp
.LBB0_2:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB0_4
# %bb.3:
callq _ZN3nts4XMem7LockBufEv
.LBB0_4:
movl 72(%rbx), %esi
movq 40(%rbx), %rdx
movq %rbx, %rdi
callq _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE
movq %rax, %r12
movl 72(%rbx), %esi
movq 40(%rbx), %rdx
movq %rbx, %rdi
callq _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE
movq %rax, %r14
movq %rbx, %rdi
movq %r12, %rsi
callq _ZN3nts4_LogEPKNS_7XTensorEPS0_
xorps %xmm0, %xmm0
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
xorl %ecx, %ecx
callq _ZN3nts9_MultiplyEPKNS_7XTensorES2_PS0_fi
testq %r13, %r13
je .LBB0_6
# %bb.5:
xorps %xmm0, %xmm0
movq %r14, %rdi
movq %r13, %rsi
movl %ebp, %edx
callq _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if
.LBB0_6:
movq %r14, %rdi
callq _ZN3nts9_NegateMeEPNS_7XTensorE
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r14, %rdi
movq 8(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movl %ebp, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq _ZN3nts10_ReduceSumEPKNS_7XTensorEPS0_iS2_fb
movq 16(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
je .LBB0_8
# %bb.7:
xorps %xmm0, %xmm0
movq %r15, %rdi
xorl %edx, %edx
callq _ZN3nts11_MultiplyMeEPNS_7XTensorEPKS0_fi
.LBB0_8:
movq %r14, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq %r12, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq 40(%rbx), %rdi
addq $24, %rsp
testq %rdi, %rdi
je .LBB0_9
# %bb.10:
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZN3nts4XMem9UnlockBufEv # TAILCALL
.LBB0_9:
.cfi_def_cfa_offset 80
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i, .Lfunc_end0-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.cfi_endproc
# -- End function
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i # -- Begin function _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.p2align 4, 0x90
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i,@function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i: # @_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, 16(%rsp) # 8-byte Spill
movl %edx, 12(%rsp) # 4-byte Spill
movq %rsi, %rbp
movq %rdi, %rbx
movl $0, (%rsp)
movl 76(%rdi), %r12d
leal -1(%r12), %r13d
testl %r9d, %r9d
movl %r9d, 8(%rsp) # 4-byte Spill
cmovnsl %r9d, %r13d
movl %r13d, %esi
callq _ZNK3nts7XTensor6GetDimEi
testl %r13d, %r13d
js .LBB1_2
# %bb.1:
cmpl 76(%rbx), %r13d
jge .LBB1_2
# %bb.4:
movl %eax, %r15d
movq %rbx, %rdi
movq %rbp, %rsi
callq _ZN3nts13_IsSameShapedEPKNS_7XTensorES2_
testb %al, %al
je .LBB1_5
# %bb.6:
movq 16(%rsp), %rax # 8-byte Reload
testq %rax, %rax
je .LBB1_9
# %bb.7:
cmpl %r15d, 120(%rax)
jne .LBB1_8
.LBB1_9:
testq %r14, %r14
je .LBB1_12
# %bb.10:
movl 76(%rbx), %eax
decl %eax
cmpl %eax, 76(%r14)
jne .LBB1_11
.LBB1_12:
cmpl $2, 112(%rbp)
jne .LBB1_14
# %bb.13:
cmpl $2, 112(%rbx)
jne .LBB1_14
# %bb.15:
movslq 76(%rbx), %rax
testq %rax, %rax
leaq -4(,%rax,4), %rax
movq $-1, %rdi
cmovgq %rax, %rdi
callq _Znam
movq %rax, %r15
testl %r12d, %r12d
jle .LBB1_21
# %bb.16: # %.lr.ph.preheader
movq %r15, %rax
addq $-4, %rax
movl %r13d, %ecx
xorl %edx, %edx
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_19: # %.sink.split
# in Loop: Header=BB1_17 Depth=1
movl 80(%rbx,%rdx,4), %edi
movl %edi, (%rsi,%rdx,4)
.LBB1_20: # in Loop: Header=BB1_17 Depth=1
incq %rdx
cmpq %rdx, %r12
je .LBB1_21
.LBB1_17: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r15, %rsi
cmpq %rcx, %rdx
jb .LBB1_19
# %bb.18: # in Loop: Header=BB1_17 Depth=1
movq %rax, %rsi
ja .LBB1_19
jmp .LBB1_20
.LBB1_21: # %._crit_edge
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZN3nts4XMem7LockBufEv
.LBB1_23:
movl 76(%rbx), %edi
decl %edi
movl 112(%rbx), %edx
movss 132(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl 72(%rbx), %ecx
movq 40(%rbx), %r8
movq %r15, %rsi
callq _ZN3nts14NewTensorBufV2EiPKiNS_16TENSOR_DATA_TYPEEfiPNS_4XMemE
movq %rax, %r13
movq %rbx, %rdi
movq %rbp, %rsi
movq %rax, %rdx
movq 16(%rsp), %rcx # 8-byte Reload
movq %r14, %r8
movl 8(%rsp), %r9d # 4-byte Reload
callq _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
movq %rsp, %rsi
movq %r13, %rdi
callq _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf
movl 12(%rsp), %eax # 4-byte Reload
testl %eax, %eax
je .LBB1_34
# %bb.24:
cmpl $1, %eax
jne .LBB1_37
# %bb.25:
testq %r14, %r14
je .LBB1_26
# %bb.27:
movq 40(%r14), %rdi
testq %rdi, %rdi
je .LBB1_30
# %bb.28:
cmpq 40(%rbx), %rdi
je .LBB1_30
# %bb.29:
callq _ZN3nts4XMem7LockBufEv
.LBB1_30:
movl 72(%r14), %esi
movq 40(%r14), %rdx
movq %r14, %rdi
callq _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE
movq %rax, %r12
movq %r14, %rdi
movq %rax, %rsi
callq _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_
leaq 4(%rsp), %rsi
movq %r12, %rdi
callq _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf
movq %r12, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq 40(%r14), %rdi
testq %rdi, %rdi
je .LBB1_33
# %bb.31:
cmpq 40(%rbx), %rdi
je .LBB1_33
# %bb.32:
callq _ZN3nts4XMem9UnlockBufEv
jmp .LBB1_33
.LBB1_26:
xorps %xmm0, %xmm0
cvtsi2ssl 120(%r13), %xmm0
movss %xmm0, 4(%rsp)
.LBB1_33:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 4(%rsp), %xmm0
movss %xmm0, (%rsp)
.LBB1_34:
movq %r15, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB1_36
# %bb.35:
callq _ZN3nts4XMem9UnlockBufEv
.LBB1_36:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.3, %r9d
movl $109, %r8d
jmp .LBB1_3
.LBB1_14:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.10, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.11, %r9d
movl $117, %r8d
jmp .LBB1_3
.LBB1_5:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.5, %r9d
movl $111, %r8d
jmp .LBB1_3
.LBB1_8:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.7, %r9d
movl $113, %r8d
jmp .LBB1_3
.LBB1_11:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.8, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.9, %r9d
movl $115, %r8d
.LBB1_3:
xorl %eax, %eax
callq fprintf
callq __cxa_rethrow
.LBB1_37:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
movl $.L.str.2+102, %edx
movl $.L.str.13, %r8d
movl $161, %ecx
xorl %eax, %eax
callq fprintf
callq __cxa_rethrow
.Lfunc_end1:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i, .Lfunc_end1-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.p2align 4, 0x90
.type _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i,@function
_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i: # @_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %r8, %r14
movq %rcx, %r15
movq %rdi, %rbx
testl %r9d, %r9d
jns .LBB2_2
# %bb.1:
movl 76(%rsi), %ebp
decl %ebp
.LBB2_2:
xorps %xmm0, %xmm0
movq %rdx, %rdi
movq %rbx, %rdx
xorl %ecx, %ecx
callq _ZN3nts4_DivEPKNS_7XTensorES2_PS0_fi
movq %rbx, %rdi
callq _ZN3nts9_NegateMeEPNS_7XTensorE
testq %r15, %r15
je .LBB2_4
# %bb.3:
xorps %xmm0, %xmm0
movq %rbx, %rdi
movq %r15, %rsi
movl %ebp, %edx
callq _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if
.LBB2_4:
testq %r14, %r14
je .LBB2_8
# %bb.5:
movslq 76(%r14), %rax
movq %rax, 32(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
testq %rax, %rax
movq $-1, %r12
movq %r15, %rdi
cmovsq %r12, %rdi
callq _Znam
movq %rax, 24(%rsp) # 8-byte Spill
leaq 80(%r14), %rsi
movq %rax, %rdi
movq %r15, %rdx
callq memcpy@PLT
movl 120(%r14), %esi
movq %r14, %rdi
callq _ZN3nts7XTensor7ReshapeEi
movslq 76(%rbx), %rax
movq %rax, 16(%rsp) # 8-byte Spill
leaq (,%rax,4), %r13
testq %rax, %rax
cmovnsq %r13, %r12
movq %r12, %rdi
callq _Znam
movq %rax, %r15
leaq 80(%rbx), %rsi
movq %rax, %rdi
movq %r13, %rdx
callq memcpy@PLT
movl 120(%rbx), %r12d
movq %rbx, %rdi
movl %ebp, %esi
callq _ZNK3nts7XTensor6GetDimEi
movl %eax, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %r12d
movq %rbx, %rdi
movl %ebp, %esi
callq _ZNK3nts7XTensor6GetDimEi
movq %rbx, %rdi
movl %r12d, %esi
movl %eax, %edx
callq _ZN3nts7XTensor7ReshapeEii
xorps %xmm0, %xmm0
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if
movq %r14, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq 24(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
callq _ZN3nts7XTensor7ReshapeEiPKi
movq %rbx, %rdi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq %r15, %rdx
callq _ZN3nts7XTensor7ReshapeEiPKi
movq %r12, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
movl $1, %esi
callq _ZN3nts9NewTensorEPKNS_7XTensorEb
movq %rax, %r15
movq %r14, %rdi
movq %rax, %rsi
callq _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_
leaq 12(%rsp), %rsi
movq %r15, %rdi
callq _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0
xorps %xmm1, %xmm1
movq %rbx, %rdi
callq _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff
testq %r15, %r15
je .LBB2_7
# %bb.6:
movq %r15, %rdi
callq _ZN3nts7XTensorD1Ev
movq %r15, %rdi
callq _ZdlPv
.LBB2_7:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8: # %.critedge
.cfi_def_cfa_offset 96
movl 120(%rbx), %r14d
movq %rbx, %rdi
movl %ebp, %esi
callq _ZNK3nts7XTensor6GetDimEi
movl %eax, %ecx
movl %r14d, %eax
cltd
idivl %ecx
cvtsi2ss %eax, %xmm1
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
xorps %xmm1, %xmm1
movq %rbx, %rdi
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff # TAILCALL
.Lfunc_end2:
.size _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i, .Lfunc_end2-_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ERROR] calling '%s' (%s line %d): %s\n"
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "n >= 0 && n < output->order"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/NiuTrans/NiuTensor/master/source/tensor/loss/CrossEntropy.hip"
.size .L.str.2, 119
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Wrong leadingDim!"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "_IsSameShaped(output, gold)"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The output tensor and gold tensor must be of the same size!"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "weight == NULL || weight->unitNum == leadingDimSize"
.size .L.str.6, 52
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Wrong weight tensor!"
.size .L.str.7, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "padding == NULL || padding->order == output->order - 1"
.size .L.str.8, 55
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Wrong padding tensor!"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE"
.size .L.str.10, 69
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "TODO!"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "[ERROR] (%s line %d): %s\n"
.size .L.str.12, 26
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "TODO"
.size .L.str.13, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155c56_00000000-6_CrossEntropy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3097:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i, @function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i:
.LFB3092:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %rcx, %r15
movq %r8, %r14
movl %r9d, %r12d
testl %r9d, %r9d
js .L10
.L4:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L5
call _ZN3nts4XMem7LockBufEv@PLT
.L5:
movq 40(%rbx), %rdx
movl 72(%rbx), %esi
movq %rbx, %rdi
call _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE@PLT
movq %rax, %r13
movq 40(%rbx), %rdx
movl 72(%rbx), %esi
movq %rbx, %rdi
call _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE@PLT
movq %rax, %rbp
movq %r13, %rsi
movq %rbx, %rdi
call _ZN3nts4_LogEPKNS_7XTensorEPS0_@PLT
movl $0, %ecx
pxor %xmm0, %xmm0
movq %rbp, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call _ZN3nts9_MultiplyEPKNS_7XTensorES2_PS0_fi@PLT
testq %r15, %r15
je .L6
pxor %xmm0, %xmm0
movl %r12d, %edx
movq %r15, %rsi
movq %rbp, %rdi
call _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if@PLT
.L6:
movq %rbp, %rdi
call _ZN3nts9_NegateMeEPNS_7XTensorE@PLT
movl $0, %r8d
movss .LC1(%rip), %xmm0
movl $0, %ecx
movl %r12d, %edx
movq 8(%rsp), %r15
movq %r15, %rsi
movq %rbp, %rdi
call _ZN3nts10_ReduceSumEPKNS_7XTensorEPS0_iS2_fb@PLT
testq %r14, %r14
je .L7
movl $0, %edx
pxor %xmm0, %xmm0
movq %r14, %rsi
movq %r15, %rdi
call _ZN3nts11_MultiplyMeEPNS_7XTensorEPKS0_fi@PLT
.L7:
movq %rbp, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq %r13, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L3
call _ZN3nts4XMem9UnlockBufEv@PLT
.L3:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl 76(%rdi), %eax
leal -1(%rax), %r12d
jmp .L4
.cfi_endproc
.LFE3092:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i, .-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/NiuTrans/NiuTensor/master/source/tensor/loss/CrossEntropy.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "n >= 0 && n < output->order"
.section .rodata.str1.8
.align 8
.LC4:
.string "[ERROR] calling '%s' (%s line %d): %s\n"
.section .rodata.str1.1
.LC5:
.string "Wrong leadingDim!"
.LC6:
.string "_IsSameShaped(output, gold)"
.section .rodata.str1.8
.align 8
.LC7:
.string "The output tensor and gold tensor must be of the same size!"
.align 8
.LC8:
.string "weight == NULL || weight->unitNum == leadingDimSize"
.section .rodata.str1.1
.LC9:
.string "Wrong weight tensor!"
.section .rodata.str1.8
.align 8
.LC10:
.string "padding == NULL || padding->order == output->order - 1"
.section .rodata.str1.1
.LC11:
.string "Wrong padding tensor!"
.section .rodata.str1.8
.align 8
.LC12:
.string "gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE"
.section .rodata.str1.1
.LC13:
.string "TODO!"
.LC14:
.string "TODO"
.LC15:
.string "[ERROR] (%s line %d): %s\n"
.text
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i, @function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i:
.LFB3093:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %rcx, %r14
movq %r8, %r13
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0x00000000, 16(%rsp)
movl 76(%rdi), %r15d
testl %r9d, %r9d
js .L46
movl 12(%rsp), %ebp
movl %ebp, %esi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %r12d
.L40:
cmpl %ebp, 76(%rbx)
jle .L13
movq (%rsp), %rsi
movq %rbx, %rdi
call _ZN3nts13_IsSameShapedEPKNS_7XTensorES2_@PLT
testb %al, %al
je .L47
testq %r14, %r14
je .L18
cmpl %r12d, 120(%r14)
jne .L48
.L18:
testq %r13, %r13
je .L20
movl 76(%rbx), %eax
subl $1, %eax
cmpl %eax, 76(%r13)
jne .L49
.L20:
movq (%rsp), %rax
cmpl $2, 112(%rax)
jne .L22
cmpl $2, 112(%rbx)
jne .L22
movl 76(%rbx), %eax
leal -1(%rax), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L25
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
movslq %r15d, %rdx
movl $0, %eax
testl %r15d, %r15d
jg .L31
.L27:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L32
call _ZN3nts4XMem7LockBufEv@PLT
.L32:
movl 72(%rbx), %ecx
movss 132(%rbx), %xmm0
movl 112(%rbx), %edx
movl 76(%rbx), %eax
leal -1(%rax), %edi
movq 40(%rbx), %r8
movq %r12, %rsi
call _ZN3nts14NewTensorBufV2EiPKiNS_16TENSOR_DATA_TYPEEfiPNS_4XMemE@PLT
movq %rax, %rbp
movl 12(%rsp), %r9d
movq %r13, %r8
movq %r14, %rcx
movq %rax, %rdx
movq (%rsp), %rsi
movq %rbx, %rdi
call _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
leaq 16(%rsp), %rsi
movq %rbp, %rdi
call _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf@PLT
cmpl $1, 8(%rsp)
je .L50
cmpl $0, 8(%rsp)
jne .L51
.L37:
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L39
call _ZN3nts4XMem9UnlockBufEv@PLT
.L39:
movss 16(%rsp), %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leal -1(%r15), %ebp
movl %ebp, %esi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %r12d
testl %ebp, %ebp
jns .L40
.L13:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC5(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $108, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L53
call __cxa_rethrow@PLT
.L53:
call __stack_chk_fail@PLT
.L47:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC7(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $110, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC6(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L54
call __cxa_rethrow@PLT
.L54:
call __stack_chk_fail@PLT
.L48:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC9(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $112, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC8(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L55
call __cxa_rethrow@PLT
.L55:
call __stack_chk_fail@PLT
.L49:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC11(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $114, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC10(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L56
call __cxa_rethrow@PLT
.L56:
call __stack_chk_fail@PLT
.L22:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC13(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $116, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC12(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L57
call __cxa_rethrow@PLT
.L57:
call __stack_chk_fail@PLT
.L25:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L28:
call __cxa_throw_bad_array_new_length@PLT
.L29:
jge .L30
movl 80(%rbx,%rax,4), %ecx
movl %ecx, -4(%r12,%rax,4)
.L30:
addq $1, %rax
cmpq %rdx, %rax
je .L27
.L31:
cmpl %eax, %ebp
jle .L29
movl 80(%rbx,%rax,4), %ecx
movl %ecx, (%r12,%rax,4)
jmp .L30
.L50:
testq %r13, %r13
je .L58
movq 40(%r13), %rdi
testq %rdi, %rdi
je .L36
cmpq 40(%rbx), %rdi
je .L36
call _ZN3nts4XMem7LockBufEv@PLT
.L36:
movq 40(%r13), %rdx
movl 72(%r13), %esi
movq %r13, %rdi
call _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE@PLT
movq %rax, %r14
movq %rax, %rsi
movq %r13, %rdi
call _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_@PLT
leaq 20(%rsp), %rsi
movq %r14, %rdi
call _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf@PLT
movq %r14, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq 40(%r13), %rdi
testq %rdi, %rdi
je .L35
cmpq 40(%rbx), %rdi
je .L35
call _ZN3nts4XMem9UnlockBufEv@PLT
jmp .L35
.L58:
pxor %xmm0, %xmm0
cvtsi2ssl 120(%rbp), %xmm0
movss %xmm0, 20(%rsp)
.L35:
movss 16(%rsp), %xmm0
divss 20(%rsp), %xmm0
movss %xmm0, 16(%rsp)
jmp .L37
.L51:
leaq .LC14(%rip), %r9
movl $161, %r8d
leaq 92+.LC2(%rip), %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L59
call __cxa_rethrow@PLT
.L59:
call __stack_chk_fail@PLT
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3093:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i, .-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.globl _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.type _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i, @function
_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i:
.LFB3094:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rdx, %rdi
movq %rcx, %r13
movq %r8, %rbp
movl %r9d, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testl %r9d, %r9d
js .L75
.L61:
movl $0, %ecx
pxor %xmm0, %xmm0
movq %rbx, %rdx
call _ZN3nts4_DivEPKNS_7XTensorES2_PS0_fi@PLT
movq %rbx, %rdi
call _ZN3nts9_NegateMeEPNS_7XTensorE@PLT
testq %r13, %r13
je .L62
pxor %xmm0, %xmm0
movl %r12d, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if@PLT
.L62:
testq %rbp, %rbp
je .L76
movl 76(%rbp), %r15d
movslq %r15d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L65
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movslq 76(%rbp), %rdx
salq $2, %rdx
leaq 80(%rbp), %rsi
movq %r13, %rcx
movq %rax, %rdi
call __memcpy_chk@PLT
movl 120(%rbp), %esi
movq %rbp, %rdi
call _ZN3nts7XTensor7ReshapeEi@PLT
movl 76(%rbx), %r14d
movslq %r14d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L77
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movslq 76(%rbx), %rdx
salq $2, %rdx
leaq 80(%rbx), %rsi
movq %r13, %rcx
movq %rax, 24(%rsp)
movq %rax, %rdi
call __memcpy_chk@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, 20(%rsp)
movl 120(%rbx), %r13d
movl %r12d, %esi
movq %rbx, %rdi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %ecx
movl %r13d, %eax
cltd
idivl %ecx
movl %eax, %esi
movl 20(%rsp), %edx
movq %rbx, %rdi
call _ZN3nts7XTensor7ReshapeEii@PLT
pxor %xmm0, %xmm0
movl $0, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if@PLT
movq 8(%rsp), %r12
movq %r12, %rdx
movl %r15d, %esi
movq %rbp, %rdi
call _ZN3nts7XTensor7ReshapeEiPKi@PLT
movq 24(%rsp), %r15
movq %r15, %rdx
movl %r14d, %esi
movq %rbx, %rdi
call _ZN3nts7XTensor7ReshapeEiPKi@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movl $1, %esi
movq %rbp, %rdi
call _ZN3nts9NewTensorEPKNS_7XTensorEb@PLT
movq %rax, %r12
movq %rax, %rsi
movq %rbp, %rdi
call _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_@PLT
leaq 36(%rsp), %rsi
movq %r12, %rdi
call _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf@PLT
movss .LC1(%rip), %xmm0
divss 36(%rsp), %xmm0
pxor %xmm1, %xmm1
movq %rbx, %rdi
call _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff@PLT
testq %r12, %r12
je .L60
movq %r12, %rdi
call _ZN3nts7XTensorD1Ev@PLT
movl $400, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
.L60:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
movl 76(%rsi), %eax
leal -1(%rax), %r12d
jmp .L61
.L76:
movl 120(%rbx), %ebp
movl %r12d, %esi
movq %rbx, %rdi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %ecx
movl %ebp, %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss .LC1(%rip), %xmm0
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
movq %rbx, %rdi
call _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff@PLT
jmp .L60
.L65:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L68
call __stack_chk_fail@PLT
.L68:
call __cxa_throw_bad_array_new_length@PLT
.L77:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L71
call __stack_chk_fail@PLT
.L71:
call __cxa_throw_bad_array_new_length@PLT
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3094:
.size _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i, .-_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3120:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3120:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CrossEntropy.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.LCPI0_0:
.long 0x3f800000 # float 1
.text
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.p2align 4, 0x90
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i,@function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i: # @_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, %r13
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
testl %r9d, %r9d
jns .LBB0_2
# %bb.1:
movl 76(%rbx), %ebp
decl %ebp
.LBB0_2:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB0_4
# %bb.3:
callq _ZN3nts4XMem7LockBufEv
.LBB0_4:
movl 72(%rbx), %esi
movq 40(%rbx), %rdx
movq %rbx, %rdi
callq _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE
movq %rax, %r12
movl 72(%rbx), %esi
movq 40(%rbx), %rdx
movq %rbx, %rdi
callq _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE
movq %rax, %r14
movq %rbx, %rdi
movq %r12, %rsi
callq _ZN3nts4_LogEPKNS_7XTensorEPS0_
xorps %xmm0, %xmm0
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
xorl %ecx, %ecx
callq _ZN3nts9_MultiplyEPKNS_7XTensorES2_PS0_fi
testq %r13, %r13
je .LBB0_6
# %bb.5:
xorps %xmm0, %xmm0
movq %r14, %rdi
movq %r13, %rsi
movl %ebp, %edx
callq _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if
.LBB0_6:
movq %r14, %rdi
callq _ZN3nts9_NegateMeEPNS_7XTensorE
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r14, %rdi
movq 8(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movl %ebp, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq _ZN3nts10_ReduceSumEPKNS_7XTensorEPS0_iS2_fb
movq 16(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
je .LBB0_8
# %bb.7:
xorps %xmm0, %xmm0
movq %r15, %rdi
xorl %edx, %edx
callq _ZN3nts11_MultiplyMeEPNS_7XTensorEPKS0_fi
.LBB0_8:
movq %r14, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq %r12, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq 40(%rbx), %rdi
addq $24, %rsp
testq %rdi, %rdi
je .LBB0_9
# %bb.10:
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZN3nts4XMem9UnlockBufEv # TAILCALL
.LBB0_9:
.cfi_def_cfa_offset 80
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i, .Lfunc_end0-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.cfi_endproc
# -- End function
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i # -- Begin function _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.p2align 4, 0x90
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i,@function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i: # @_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, 16(%rsp) # 8-byte Spill
movl %edx, 12(%rsp) # 4-byte Spill
movq %rsi, %rbp
movq %rdi, %rbx
movl $0, (%rsp)
movl 76(%rdi), %r12d
leal -1(%r12), %r13d
testl %r9d, %r9d
movl %r9d, 8(%rsp) # 4-byte Spill
cmovnsl %r9d, %r13d
movl %r13d, %esi
callq _ZNK3nts7XTensor6GetDimEi
testl %r13d, %r13d
js .LBB1_2
# %bb.1:
cmpl 76(%rbx), %r13d
jge .LBB1_2
# %bb.4:
movl %eax, %r15d
movq %rbx, %rdi
movq %rbp, %rsi
callq _ZN3nts13_IsSameShapedEPKNS_7XTensorES2_
testb %al, %al
je .LBB1_5
# %bb.6:
movq 16(%rsp), %rax # 8-byte Reload
testq %rax, %rax
je .LBB1_9
# %bb.7:
cmpl %r15d, 120(%rax)
jne .LBB1_8
.LBB1_9:
testq %r14, %r14
je .LBB1_12
# %bb.10:
movl 76(%rbx), %eax
decl %eax
cmpl %eax, 76(%r14)
jne .LBB1_11
.LBB1_12:
cmpl $2, 112(%rbp)
jne .LBB1_14
# %bb.13:
cmpl $2, 112(%rbx)
jne .LBB1_14
# %bb.15:
movslq 76(%rbx), %rax
testq %rax, %rax
leaq -4(,%rax,4), %rax
movq $-1, %rdi
cmovgq %rax, %rdi
callq _Znam
movq %rax, %r15
testl %r12d, %r12d
jle .LBB1_21
# %bb.16: # %.lr.ph.preheader
movq %r15, %rax
addq $-4, %rax
movl %r13d, %ecx
xorl %edx, %edx
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_19: # %.sink.split
# in Loop: Header=BB1_17 Depth=1
movl 80(%rbx,%rdx,4), %edi
movl %edi, (%rsi,%rdx,4)
.LBB1_20: # in Loop: Header=BB1_17 Depth=1
incq %rdx
cmpq %rdx, %r12
je .LBB1_21
.LBB1_17: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r15, %rsi
cmpq %rcx, %rdx
jb .LBB1_19
# %bb.18: # in Loop: Header=BB1_17 Depth=1
movq %rax, %rsi
ja .LBB1_19
jmp .LBB1_20
.LBB1_21: # %._crit_edge
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZN3nts4XMem7LockBufEv
.LBB1_23:
movl 76(%rbx), %edi
decl %edi
movl 112(%rbx), %edx
movss 132(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl 72(%rbx), %ecx
movq 40(%rbx), %r8
movq %r15, %rsi
callq _ZN3nts14NewTensorBufV2EiPKiNS_16TENSOR_DATA_TYPEEfiPNS_4XMemE
movq %rax, %r13
movq %rbx, %rdi
movq %rbp, %rsi
movq %rax, %rdx
movq 16(%rsp), %rcx # 8-byte Reload
movq %r14, %r8
movl 8(%rsp), %r9d # 4-byte Reload
callq _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
movq %rsp, %rsi
movq %r13, %rdi
callq _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf
movl 12(%rsp), %eax # 4-byte Reload
testl %eax, %eax
je .LBB1_34
# %bb.24:
cmpl $1, %eax
jne .LBB1_37
# %bb.25:
testq %r14, %r14
je .LBB1_26
# %bb.27:
movq 40(%r14), %rdi
testq %rdi, %rdi
je .LBB1_30
# %bb.28:
cmpq 40(%rbx), %rdi
je .LBB1_30
# %bb.29:
callq _ZN3nts4XMem7LockBufEv
.LBB1_30:
movl 72(%r14), %esi
movq 40(%r14), %rdx
movq %r14, %rdi
callq _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE
movq %rax, %r12
movq %r14, %rdi
movq %rax, %rsi
callq _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_
leaq 4(%rsp), %rsi
movq %r12, %rdi
callq _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf
movq %r12, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq 40(%r14), %rdi
testq %rdi, %rdi
je .LBB1_33
# %bb.31:
cmpq 40(%rbx), %rdi
je .LBB1_33
# %bb.32:
callq _ZN3nts4XMem9UnlockBufEv
jmp .LBB1_33
.LBB1_26:
xorps %xmm0, %xmm0
cvtsi2ssl 120(%r13), %xmm0
movss %xmm0, 4(%rsp)
.LBB1_33:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 4(%rsp), %xmm0
movss %xmm0, (%rsp)
.LBB1_34:
movq %r15, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZN3nts12DelTensorBufEPNS_7XTensorE
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB1_36
# %bb.35:
callq _ZN3nts4XMem9UnlockBufEv
.LBB1_36:
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.3, %r9d
movl $109, %r8d
jmp .LBB1_3
.LBB1_14:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.10, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.11, %r9d
movl $117, %r8d
jmp .LBB1_3
.LBB1_5:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.5, %r9d
movl $111, %r8d
jmp .LBB1_3
.LBB1_8:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.7, %r9d
movl $113, %r8d
jmp .LBB1_3
.LBB1_11:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.8, %edx
movl $.L.str.2+102, %ecx
movl $.L.str.9, %r9d
movl $115, %r8d
.LBB1_3:
xorl %eax, %eax
callq fprintf
callq __cxa_rethrow
.LBB1_37:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
movl $.L.str.2+102, %edx
movl $.L.str.13, %r8d
movl $161, %ecx
xorl %eax, %eax
callq fprintf
callq __cxa_rethrow
.Lfunc_end1:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i, .Lfunc_end1-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.p2align 4, 0x90
.type _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i,@function
_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i: # @_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %r8, %r14
movq %rcx, %r15
movq %rdi, %rbx
testl %r9d, %r9d
jns .LBB2_2
# %bb.1:
movl 76(%rsi), %ebp
decl %ebp
.LBB2_2:
xorps %xmm0, %xmm0
movq %rdx, %rdi
movq %rbx, %rdx
xorl %ecx, %ecx
callq _ZN3nts4_DivEPKNS_7XTensorES2_PS0_fi
movq %rbx, %rdi
callq _ZN3nts9_NegateMeEPNS_7XTensorE
testq %r15, %r15
je .LBB2_4
# %bb.3:
xorps %xmm0, %xmm0
movq %rbx, %rdi
movq %r15, %rsi
movl %ebp, %edx
callq _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if
.LBB2_4:
testq %r14, %r14
je .LBB2_8
# %bb.5:
movslq 76(%r14), %rax
movq %rax, 32(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
testq %rax, %rax
movq $-1, %r12
movq %r15, %rdi
cmovsq %r12, %rdi
callq _Znam
movq %rax, 24(%rsp) # 8-byte Spill
leaq 80(%r14), %rsi
movq %rax, %rdi
movq %r15, %rdx
callq memcpy@PLT
movl 120(%r14), %esi
movq %r14, %rdi
callq _ZN3nts7XTensor7ReshapeEi
movslq 76(%rbx), %rax
movq %rax, 16(%rsp) # 8-byte Spill
leaq (,%rax,4), %r13
testq %rax, %rax
cmovnsq %r13, %r12
movq %r12, %rdi
callq _Znam
movq %rax, %r15
leaq 80(%rbx), %rsi
movq %rax, %rdi
movq %r13, %rdx
callq memcpy@PLT
movl 120(%rbx), %r12d
movq %rbx, %rdi
movl %ebp, %esi
callq _ZNK3nts7XTensor6GetDimEi
movl %eax, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %r12d
movq %rbx, %rdi
movl %ebp, %esi
callq _ZNK3nts7XTensor6GetDimEi
movq %rbx, %rdi
movl %r12d, %esi
movl %eax, %edx
callq _ZN3nts7XTensor7ReshapeEii
xorps %xmm0, %xmm0
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if
movq %r14, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq 24(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
callq _ZN3nts7XTensor7ReshapeEiPKi
movq %rbx, %rdi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq %r15, %rdx
callq _ZN3nts7XTensor7ReshapeEiPKi
movq %r12, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
movl $1, %esi
callq _ZN3nts9NewTensorEPKNS_7XTensorEb
movq %rax, %r15
movq %r14, %rdi
movq %rax, %rsi
callq _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_
leaq 12(%rsp), %rsi
movq %r15, %rdi
callq _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0
xorps %xmm1, %xmm1
movq %rbx, %rdi
callq _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff
testq %r15, %r15
je .LBB2_7
# %bb.6:
movq %r15, %rdi
callq _ZN3nts7XTensorD1Ev
movq %r15, %rdi
callq _ZdlPv
.LBB2_7:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8: # %.critedge
.cfi_def_cfa_offset 96
movl 120(%rbx), %r14d
movq %rbx, %rdi
movl %ebp, %esi
callq _ZNK3nts7XTensor6GetDimEi
movl %eax, %ecx
movl %r14d, %eax
cltd
idivl %ecx
cvtsi2ss %eax, %xmm1
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
xorps %xmm1, %xmm1
movq %rbx, %rdi
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff # TAILCALL
.Lfunc_end2:
.size _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i, .Lfunc_end2-_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ERROR] calling '%s' (%s line %d): %s\n"
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "n >= 0 && n < output->order"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/NiuTrans/NiuTensor/master/source/tensor/loss/CrossEntropy.hip"
.size .L.str.2, 119
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Wrong leadingDim!"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "_IsSameShaped(output, gold)"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The output tensor and gold tensor must be of the same size!"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "weight == NULL || weight->unitNum == leadingDimSize"
.size .L.str.6, 52
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Wrong weight tensor!"
.size .L.str.7, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "padding == NULL || padding->order == output->order - 1"
.size .L.str.8, 55
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Wrong padding tensor!"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE"
.size .L.str.10, 69
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "TODO!"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "[ERROR] (%s line %d): %s\n"
.size .L.str.12, 26
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "TODO"
.size .L.str.13, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <cmath>
#include <ctime>
using namespace std;
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
static const long long SIZE = 4096*4096*4;
cudaError_t calaAddArray(const double* a, const double* b, double* res, const long SIZE);
__global__ void addArray(const double* a,const double *b, double* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
while (i < SIZE)
{
c[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
i += gridDim.x*blockDim.x;;
}
}
int main4444()
{
cout<<"Begin : "<<endl;
srand(time(0));
double* a = new double[SIZE];
double* b = new double[SIZE];
for (long i = 0; i < SIZE; i++)
{
a[i] = (double)rand() * (double)rand();
b[i] = (double)rand() * (double)rand();
}
double* res = new double[SIZE];
int count=2;
clock_t start, finish;
start = clock();
for(int i=0;i<count;i++)
{
for (long long i = 0; i < SIZE; i++)
res[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << res[i] << ", ";
cout << endl << endl << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i] )
{
cout << "*********** Failed CPU" << endl;
break;
}
}
cout << start << " " << finish << endl;
cout << "By CPU Array Mult: " << (double)(finish - start) / CLOCKS_PER_SEC << endl;
start = clock();
for(int i=0;i<count;i++)
{
cudaError_t cudaErrorRes = calaAddArray(a, b, res, SIZE);
if (cudaErrorRes != cudaSuccess)
{
cout << "************* CUDA Return Result Failed " << endl;
}
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i])
{
cout << "************* Failed GPU" << endl;
break;
}
}
cout << endl;
cout << start << " " << finish << endl;
cout << "By CUDA Array Mult: " << (double)(finish - start)/CLOCKS_PER_SEC << endl;
cout<<"Game Over!!!!"<<endl;
return 1;
}
cudaError_t calaAddArray(const double* a, const double* b, double* c, const long SIZE)
{
double* dev_a=0;
double* dev_b=0;
double* dev_c=0;
cudaError_t cudaStatus=cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
cout << "CUDA ADD Failed In Function cudaError_t calaAddArray " << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvA failed!" << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvB failed!" << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_c, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvC failed!" << endl;
goto Error;
}
cudaStatus = cudaMemcpy(dev_a,a,SIZE * sizeof(double),cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvA failed!" << endl;
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, SIZE * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvB failed!" << endl;
goto Error;
}
addArray <<<4096,1024>>>(dev_a, dev_b, dev_c);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
cout << "addKernel launch failed: " <<cudaGetErrorString(cudaStatus)<<endl;
goto Error;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
cout<<cudaStatus<<" cudaDeviceSynchronize returned error code %d after launching addKernel!"<<endl;
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, SIZE * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvC failed!" << endl;
goto Error;
}
Error:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return cudaStatus;
} | code for sm_80
Function : _Z8addArrayPKdS0_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R20, SR_CTAID.X ; /* 0x0000000000147919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R20, R20, c[0x0][0x0], R3 ; /* 0x0000000014147a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R20, 0x3ffffff, PT ; /* 0x03ffffff1400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R2, R20, R7, c[0x0][0x160] ; /* 0x0000580014027625 */
/* 0x001fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R20, R7, c[0x0][0x168] ; /* 0x00005a0014067625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x240 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R21, RZ, RZ, R20 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0014 */
/*00f0*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x004e260000001800 */
/*0100*/ DFMA R8, -R2, R4, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000104 */
/*0110*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0120*/ DFMA R4, R4, R8, R4 ; /* 0x000000080404722b */
/* 0x001e080000000004 */
/*0130*/ DMUL R8, R6, R2 ; /* 0x0000000206087228 */
/* 0x00ae480000000000 */
/*0140*/ DFMA R10, -R2, R4, 1 ; /* 0x3ff00000020a742b */
/* 0x001e080000000104 */
/*0150*/ DFMA R14, R6, c[0x2][0x0], R8 ; /* 0x00800000060e7a2b */
/* 0x002fc80000000008 */
/*0160*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x001e0c0000000004 */
/*0170*/ DMUL R4, R14, R10 ; /* 0x0000000a0e047228 */
/* 0x001e220000000000 */
/*0180*/ FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x000fca0003f4e200 */
/*0190*/ DFMA R12, -R2, R4, R14 ; /* 0x00000004020c722b */
/* 0x001e0c000000010e */
/*01a0*/ DFMA R4, R10, R12, R4 ; /* 0x0000000c0a04722b */
/* 0x0010640000000004 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */
/* 0x001fc800078e00ff */
/*01c0*/ IMAD R20, R11, c[0x0][0x0], R20 ; /* 0x000000000b147a24 */
/* 0x000fc800078e0214 */
/*01d0*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x002fe20000000005 */
/*01e0*/ ISETP.GE.AND P1, PT, R20, 0x4000000, PT ; /* 0x040000001400780c */
/* 0x000fc80003f26270 */
/*01f0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0200*/ @P0 BRA P2, 0x230 ; /* 0x0000002000000947 */
/* 0x000fea0001000000 */
/*0210*/ MOV R0, 0x230 ; /* 0x0000023000007802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x2b0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ DMUL R4, R6, R4 ; /* 0x0000000406047228 */
/* 0x000e220000000000 */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE R2, R21, R2, c[0x0][0x170] ; /* 0x00005c0015027625 */
/* 0x000fe200078e0202 */
/*0270*/ DFMA R4, R6, R4, -R8 ; /* 0x000000040604722b */
/* 0x001e0e0000000808 */
/*0280*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011e2000c101b04 */
/*0290*/ @!P1 BRA 0x70 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*02d0*/ LOP3.LUT R10, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff030a7812 */
/* 0x000fe200078ec0ff */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0003 */
/*02f0*/ FSETP.GEU.AND P3, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f6e200 */
/*0300*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0330*/ LOP3.LUT R22, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f167812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0350*/ LOP3.LUT R25, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003197812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*0370*/ BSSY B1, 0x860 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*0380*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*0390*/ ISETP.GE.U32.AND P2, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f46070 */
/*03a0*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fc400078e0016 */
/*03b0*/ @!P3 LOP3.LUT R17, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d11b812 */
/* 0x000fe200078ec0ff */
/*03c0*/ @!P3 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12b224 */
/* 0x000fe200078e00ff */
/*03d0*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e220000001800 */
/*03e0*/ SEL R3, R23, 0x63400000, !P2 ; /* 0x6340000017037807 */
/* 0x000fe40005000000 */
/*03f0*/ @!P3 ISETP.GE.U32.AND P4, PT, R22, R17, PT ; /* 0x000000111600b20c */
/* 0x000fe40003f86070 */
/*0400*/ LOP3.LUT R3, R3, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80f */
/*0410*/ @!P3 SEL R19, R23, 0x63400000, !P4 ; /* 0x634000001713b807 */
/* 0x000fe40006000000 */
/*0420*/ @!P0 LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b198812 */
/* 0x000fc400078ec0ff */
/*0430*/ @!P3 LOP3.LUT R19, R19, 0x80000000, R15, 0xf8, !PT ; /* 0x800000001313b812 */
/* 0x000fe400078ef80f */
/*0440*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fe40007ffe0ff */
/*0450*/ @!P3 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313b812 */
/* 0x000fe200078efcff */
/*0460*/ DFMA R16, R4, -R10, 1 ; /* 0x3ff000000410742b */
/* 0x001e0a000000080a */
/*0470*/ @!P3 DFMA R2, R2, 2, -R18 ; /* 0x400000000202b82b */
/* 0x000fc80000000812 */
/*0480*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0490*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e220000000004 */
/*04a0*/ @!P3 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000318b812 */
/* 0x000fc800078ec0ff */
/*04b0*/ IADD3 R18, R24, -0x1, RZ ; /* 0xffffffff18127810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DFMA R4, R16, -R10, 1 ; /* 0x3ff000001004742b */
/* 0x001e06000000080a */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*04e0*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x001e220000000010 */
/*04f0*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0500*/ DMUL R4, R16, R2 ; /* 0x0000000210047228 */
/* 0x001e0c0000000000 */
/*0510*/ DFMA R18, R4, -R10, R2 ; /* 0x8000000a0412722b */
/* 0x001e0c0000000002 */
/*0520*/ DFMA R18, R16, R18, R4 ; /* 0x000000121012722b */
/* 0x0010620000000004 */
/*0530*/ @P0 BRA 0x700 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R5, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d057812 */
/* 0x001fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R22.reuse, R5, PT ; /* 0x000000051600720c */
/* 0x040fe20003f06070 */
/*0570*/ IMAD.IADD R4, R22, 0x1, -R5 ; /* 0x0000000116047824 */
/* 0x000fc600078e0a05 */
/*0580*/ SEL R23, R23, 0x63400000, !P0 ; /* 0x6340000017177807 */
/* 0x000fe40004000000 */
/*0590*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*05a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*05b0*/ IMAD.IADD R14, R4, 0x1, -R23 ; /* 0x00000001040e7824 */
/* 0x000fca00078e0a17 */
/*05c0*/ IADD3 R17, R14, 0x7fe00000, RZ ; /* 0x7fe000000e117810 */
/* 0x000fcc0007ffe0ff */
/*05d0*/ DMUL R4, R18, R16 ; /* 0x0000001012047228 */
/* 0x002e140000000000 */
/*05e0*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*05f0*/ @P0 BRA 0x850 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0600*/ DFMA R2, R18, -R10, R2 ; /* 0x8000000a1202722b */
/* 0x000e220000000002 */
/*0610*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*0620*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0630*/ LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fc800078e480d */
/*0640*/ LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ; /* 0x000000110d117212 */
/* 0x000fce00078efcff */
/*0650*/ @!P0 BRA 0x850 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*0670*/ DMUL.RP R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x000e220000008000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0690*/ DFMA R2, R4, -R2, R18 ; /* 0x800000020402722b */
/* 0x000e460000000012 */
/*06a0*/ LOP3.LUT R13, R17, R13, RZ, 0x3c, !PT ; /* 0x0000000d110d7212 */
/* 0x001fc600078e3cff */
/*06b0*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*06c0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*06d0*/ FSEL R4, R16, R4, !P0 ; /* 0x0000000410047208 */
/* 0x000fe40004000000 */
/*06e0*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*06f0*/ BRA 0x850 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0700*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0710*/ @P0 BRA 0x830 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0730*/ @P0 BRA 0x800 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0770*/ @!P0 BRA 0x850 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*0790*/ LOP3.LUT R5, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f057812 */
/* 0x000fe400078e480d */
/*07a0*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*07b0*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x001fe200078efcff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R5, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f057812 */
/* 0x001fe200078efcff */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff77002007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <cmath>
#include <ctime>
using namespace std;
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
static const long long SIZE = 4096*4096*4;
cudaError_t calaAddArray(const double* a, const double* b, double* res, const long SIZE);
__global__ void addArray(const double* a,const double *b, double* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
while (i < SIZE)
{
c[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
i += gridDim.x*blockDim.x;;
}
}
int main4444()
{
cout<<"Begin : "<<endl;
srand(time(0));
double* a = new double[SIZE];
double* b = new double[SIZE];
for (long i = 0; i < SIZE; i++)
{
a[i] = (double)rand() * (double)rand();
b[i] = (double)rand() * (double)rand();
}
double* res = new double[SIZE];
int count=2;
clock_t start, finish;
start = clock();
for(int i=0;i<count;i++)
{
for (long long i = 0; i < SIZE; i++)
res[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << res[i] << ", ";
cout << endl << endl << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i] )
{
cout << "*********** Failed CPU" << endl;
break;
}
}
cout << start << " " << finish << endl;
cout << "By CPU Array Mult: " << (double)(finish - start) / CLOCKS_PER_SEC << endl;
start = clock();
for(int i=0;i<count;i++)
{
cudaError_t cudaErrorRes = calaAddArray(a, b, res, SIZE);
if (cudaErrorRes != cudaSuccess)
{
cout << "************* CUDA Return Result Failed " << endl;
}
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i])
{
cout << "************* Failed GPU" << endl;
break;
}
}
cout << endl;
cout << start << " " << finish << endl;
cout << "By CUDA Array Mult: " << (double)(finish - start)/CLOCKS_PER_SEC << endl;
cout<<"Game Over!!!!"<<endl;
return 1;
}
cudaError_t calaAddArray(const double* a, const double* b, double* c, const long SIZE)
{
double* dev_a=0;
double* dev_b=0;
double* dev_c=0;
cudaError_t cudaStatus=cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
cout << "CUDA ADD Failed In Function cudaError_t calaAddArray " << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvA failed!" << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvB failed!" << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_c, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvC failed!" << endl;
goto Error;
}
cudaStatus = cudaMemcpy(dev_a,a,SIZE * sizeof(double),cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvA failed!" << endl;
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, SIZE * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvB failed!" << endl;
goto Error;
}
addArray <<<4096,1024>>>(dev_a, dev_b, dev_c);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
cout << "addKernel launch failed: " <<cudaGetErrorString(cudaStatus)<<endl;
goto Error;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
cout<<cudaStatus<<" cudaDeviceSynchronize returned error code %d after launching addKernel!"<<endl;
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, SIZE * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvC failed!" << endl;
goto Error;
}
Error:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return cudaStatus;
} | .file "tmpxft_00183ba5_00000000-6_helloword.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd
.type _Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd, @function
_Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8addArrayPKdS0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd, .-_Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd
.globl _Z8addArrayPKdS0_Pd
.type _Z8addArrayPKdS0_Pd, @function
_Z8addArrayPKdS0_Pd:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z8addArrayPKdS0_Pd, .-_Z8addArrayPKdS0_Pd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUDA ADD Failed In Function cudaError_t calaAddArray "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc decvA failed!"
.LC2:
.string "cudaMalloc decvB failed!"
.LC3:
.string "cudaMalloc decvC failed!"
.LC4:
.string "cudaMemcpy decvA failed!"
.LC5:
.string "cudaMemcpy decvB failed!"
.LC6:
.string "addKernel launch failed: "
.section .rodata.str1.8
.align 8
.LC7:
.string " cudaDeviceSynchronize returned error code %d after launching addKernel!"
.section .rodata.str1.1
.LC8:
.string "cudaMemcpy decvC failed!"
.text
.globl _Z12calaAddArrayPKdS0_Pdl
.type _Z12calaAddArrayPKdS0_Pdl, @function
_Z12calaAddArrayPKdS0_Pdl:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L62
salq $3, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L66
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L67
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L43:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L69
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L70
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L17
movl $24, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L71
cmpb $0, 56(%rbp)
je .L58
movzbl 67(%rbp), %esi
.L59:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L62:
movl %eax, %ebx
movl $53, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L72
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %esi
.L16:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L17:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl %ebx, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L74
call _ZSt16__throw_bad_castv@PLT
.L74:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L63:
movl $24, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L75
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L75:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L76
call _ZSt16__throw_bad_castv@PLT
.L76:
call __stack_chk_fail@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L64:
movl $24, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L77
cmpb $0, 56(%rbp)
je .L26
movzbl 67(%rbp), %esi
.L27:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L77:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L78
call _ZSt16__throw_bad_castv@PLT
.L78:
call __stack_chk_fail@PLT
.L26:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L65:
movl $24, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L79
cmpb $0, 56(%rbp)
je .L31
movzbl 67(%rbp), %esi
.L32:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L79:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L80
call _ZSt16__throw_bad_castv@PLT
.L80:
call __stack_chk_fail@PLT
.L31:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L66:
movl $24, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L81
cmpb $0, 56(%rbp)
je .L36
movzbl 67(%rbp), %esi
.L37:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L81:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L82
call _ZSt16__throw_bad_castv@PLT
.L82:
call __stack_chk_fail@PLT
.L36:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L37
.L67:
movl $24, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L83
cmpb $0, 56(%rbp)
je .L41
movzbl 67(%rbp), %esi
.L42:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L83:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L84
call _ZSt16__throw_bad_castv@PLT
.L84:
call __stack_chk_fail@PLT
.L41:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L68:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z8addArrayPKdS0_PdPKdS0_Pd
jmp .L43
.L69:
movl $25, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
testq %rax, %rax
je .L85
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L46:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbp
testq %rbp, %rbp
je .L86
cmpb $0, 56(%rbp)
je .L49
movzbl 67(%rbp), %esi
.L50:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L85:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L46
.L86:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L87
call _ZSt16__throw_bad_castv@PLT
.L87:
call __stack_chk_fail@PLT
.L49:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L50
.L70:
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $72, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L88
cmpb $0, 56(%r12)
je .L54
movzbl 67(%r12), %esi
.L55:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L88:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L89:
call __stack_chk_fail@PLT
.L54:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L55
.L71:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L90
call _ZSt16__throw_bad_castv@PLT
.L90:
call __stack_chk_fail@PLT
.L58:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L59
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z12calaAddArrayPKdS0_Pdl, .-_Z12calaAddArrayPKdS0_Pdl
.section .rodata.str1.1
.LC9:
.string "Begin : "
.LC11:
.string "*********** Failed CPU"
.LC12:
.string " "
.LC13:
.string "By CPU Array Mult: "
.section .rodata.str1.8
.align 8
.LC15:
.string "************* CUDA Return Result Failed "
.section .rodata.str1.1
.LC16:
.string "************* Failed GPU"
.LC17:
.string "By CUDA Array Mult: "
.LC18:
.string "Game Over!!!!"
.text
.globl _Z8main4444v
.type _Z8main4444v, @function
_Z8main4444v:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $10, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L144
cmpb $0, 56(%rbx)
je .L93
movzbl 67(%rbx), %esi
.L94:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $536870912, %edi
call _Znam@PLT
movq %rax, %rbx
movl $536870912, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %r12d
.L95:
call rand@PLT
pxor %xmm6, %xmm6
cvtsi2sdl %eax, %xmm6
movsd %xmm6, 8(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
movsd %xmm0, (%rbx,%r12,8)
call rand@PLT
pxor %xmm7, %xmm7
cvtsi2sdl %eax, %xmm7
movsd %xmm7, 8(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
movsd %xmm0, 0(%rbp,%r12,8)
addq $1, %r12
cmpq $67108864, %r12
jne .L95
movl $536870912, %edi
call _Znam@PLT
movq %rax, %r12
call clock@PLT
movq %rax, %r14
movl $2, %edx
movsd .LC10(%rip), %xmm5
.L96:
movl $0, %eax
.L97:
movsd (%rbx,%rax,8), %xmm3
movsd 0(%rbp,%rax,8), %xmm1
movapd %xmm3, %xmm2
mulsd %xmm1, %xmm2
movapd %xmm1, %xmm4
mulsd %xmm5, %xmm4
movapd %xmm2, %xmm0
subsd %xmm4, %xmm0
divsd %xmm3, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, (%r12,%rax,8)
addq $1, %rax
cmpq $67108864, %rax
jne .L97
subl $1, %edx
jne .L96
call clock@PLT
movq %rax, 8(%rsp)
movl $0, %eax
movsd .LC10(%rip), %xmm5
.L105:
movsd (%rbx,%rax,8), %xmm3
movsd 0(%rbp,%rax,8), %xmm1
movapd %xmm3, %xmm2
mulsd %xmm1, %xmm2
movapd %xmm1, %xmm4
mulsd %xmm5, %xmm4
movapd %xmm2, %xmm0
subsd %xmm4, %xmm0
divsd %xmm3, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
subsd %xmm2, %xmm0
ucomisd (%r12,%rax,8), %xmm0
jp .L136
jne .L136
addq $1, %rax
cmpq $67108864, %rax
jne .L105
jmp .L104
.L144:
call _ZSt16__throw_bad_castv@PLT
.L93:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L94
.L136:
movl $23, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r13
testq %r13, %r13
je .L145
cmpb $0, 56(%r13)
je .L102
movzbl 67(%r13), %esi
.L103:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L104:
movq %r14, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %r13
movl $3, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rsi
movq %r13, %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r15
testq %r15, %r15
je .L146
cmpb $0, 56(%r15)
je .L107
movzbl 67(%r15), %esi
.L108:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $19, %edx
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC14(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L147
cmpb $0, 56(%r14)
je .L110
movzbl 67(%r14), %esi
.L111:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call clock@PLT
movq %rax, %r14
movl $2, %r13d
.L116:
movl $67108864, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z12calaAddArrayPKdS0_Pdl
testl %eax, %eax
jne .L148
.L112:
subl $1, %r13d
jne .L116
call clock@PLT
movq %rax, %r13
movl $0, %eax
movsd .LC10(%rip), %xmm5
.L123:
movsd (%rbx,%rax,8), %xmm3
movsd 0(%rbp,%rax,8), %xmm1
movapd %xmm3, %xmm2
mulsd %xmm1, %xmm2
movapd %xmm1, %xmm4
mulsd %xmm5, %xmm4
movapd %xmm2, %xmm0
subsd %xmm4, %xmm0
divsd %xmm3, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
subsd %xmm2, %xmm0
ucomisd (%r12,%rax,8), %xmm0
jp .L137
jne .L137
addq $1, %rax
cmpq $67108864, %rax
jne .L123
jmp .L122
.L145:
call _ZSt16__throw_bad_castv@PLT
.L102:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L103
.L146:
call _ZSt16__throw_bad_castv@PLT
.L107:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L108
.L147:
call _ZSt16__throw_bad_castv@PLT
.L110:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L111
.L148:
movl $42, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r15
testq %r15, %r15
je .L149
cmpb $0, 56(%r15)
je .L114
movzbl 67(%r15), %esi
.L115:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L112
.L149:
call _ZSt16__throw_bad_castv@PLT
.L114:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L115
.L137:
movl $26, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L150
cmpb $0, 56(%rbx)
je .L120
movzbl 67(%rbx), %esi
.L121:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L122:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L151
cmpb $0, 56(%rbx)
je .L125
movzbl 67(%rbx), %esi
.L126:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r14, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r13, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L152
cmpb $0, 56(%rbp)
je .L128
movzbl 67(%rbp), %esi
.L129:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $20, %edx
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r14, %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
divsd .LC14(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L153
cmpb $0, 56(%rbp)
je .L131
movzbl 67(%rbp), %esi
.L132:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $13, %edx
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L154
cmpb $0, 56(%rbx)
je .L134
movzbl 67(%rbx), %esi
.L135:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L150:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L120:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L121
.L151:
call _ZSt16__throw_bad_castv@PLT
.L125:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L126
.L152:
call _ZSt16__throw_bad_castv@PLT
.L128:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L129
.L153:
call _ZSt16__throw_bad_castv@PLT
.L131:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L132
.L154:
call _ZSt16__throw_bad_castv@PLT
.L134:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L135
.cfi_endproc
.LFE3669:
.size _Z8main4444v, .-_Z8main4444v
.section .rodata.str1.1
.LC19:
.string "_Z8addArrayPKdS0_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8addArrayPKdS0_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 1293080650
.long 1074340347
.align 8
.LC14:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <cmath>
#include <ctime>
using namespace std;
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
static const long long SIZE = 4096*4096*4;
cudaError_t calaAddArray(const double* a, const double* b, double* res, const long SIZE);
__global__ void addArray(const double* a,const double *b, double* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
while (i < SIZE)
{
c[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
i += gridDim.x*blockDim.x;;
}
}
int main4444()
{
cout<<"Begin : "<<endl;
srand(time(0));
double* a = new double[SIZE];
double* b = new double[SIZE];
for (long i = 0; i < SIZE; i++)
{
a[i] = (double)rand() * (double)rand();
b[i] = (double)rand() * (double)rand();
}
double* res = new double[SIZE];
int count=2;
clock_t start, finish;
start = clock();
for(int i=0;i<count;i++)
{
for (long long i = 0; i < SIZE; i++)
res[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << res[i] << ", ";
cout << endl << endl << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i] )
{
cout << "*********** Failed CPU" << endl;
break;
}
}
cout << start << " " << finish << endl;
cout << "By CPU Array Mult: " << (double)(finish - start) / CLOCKS_PER_SEC << endl;
start = clock();
for(int i=0;i<count;i++)
{
cudaError_t cudaErrorRes = calaAddArray(a, b, res, SIZE);
if (cudaErrorRes != cudaSuccess)
{
cout << "************* CUDA Return Result Failed " << endl;
}
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i])
{
cout << "************* Failed GPU" << endl;
break;
}
}
cout << endl;
cout << start << " " << finish << endl;
cout << "By CUDA Array Mult: " << (double)(finish - start)/CLOCKS_PER_SEC << endl;
cout<<"Game Over!!!!"<<endl;
return 1;
}
cudaError_t calaAddArray(const double* a, const double* b, double* c, const long SIZE)
{
double* dev_a=0;
double* dev_b=0;
double* dev_c=0;
cudaError_t cudaStatus=cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
cout << "CUDA ADD Failed In Function cudaError_t calaAddArray " << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvA failed!" << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvB failed!" << endl;
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_c, sizeof(double)*SIZE);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMalloc decvC failed!" << endl;
goto Error;
}
cudaStatus = cudaMemcpy(dev_a,a,SIZE * sizeof(double),cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvA failed!" << endl;
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, SIZE * sizeof(double), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvB failed!" << endl;
goto Error;
}
addArray <<<4096,1024>>>(dev_a, dev_b, dev_c);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
cout << "addKernel launch failed: " <<cudaGetErrorString(cudaStatus)<<endl;
goto Error;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
cout<<cudaStatus<<" cudaDeviceSynchronize returned error code %d after launching addKernel!"<<endl;
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, SIZE * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
cout << "cudaMemcpy decvC failed!" << endl;
goto Error;
}
Error:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return cudaStatus;
} | #include <iostream>
#include <cstdlib>
#include <cmath>
#include <ctime>
using namespace std;
#include "hip/hip_runtime.h"
static const long long SIZE = 4096*4096*4;
hipError_t calaAddArray(const double* a, const double* b, double* res, const long SIZE);
__global__ void addArray(const double* a,const double *b, double* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
while (i < SIZE)
{
c[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
i += gridDim.x*blockDim.x;;
}
}
int main4444()
{
cout<<"Begin : "<<endl;
srand(time(0));
double* a = new double[SIZE];
double* b = new double[SIZE];
for (long i = 0; i < SIZE; i++)
{
a[i] = (double)rand() * (double)rand();
b[i] = (double)rand() * (double)rand();
}
double* res = new double[SIZE];
int count=2;
clock_t start, finish;
start = clock();
for(int i=0;i<count;i++)
{
for (long long i = 0; i < SIZE; i++)
res[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << res[i] << ", ";
cout << endl << endl << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i] )
{
cout << "*********** Failed CPU" << endl;
break;
}
}
cout << start << " " << finish << endl;
cout << "By CPU Array Mult: " << (double)(finish - start) / CLOCKS_PER_SEC << endl;
start = clock();
for(int i=0;i<count;i++)
{
hipError_t cudaErrorRes = calaAddArray(a, b, res, SIZE);
if (cudaErrorRes != hipSuccess)
{
cout << "************* CUDA Return Result Failed " << endl;
}
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i])
{
cout << "************* Failed GPU" << endl;
break;
}
}
cout << endl;
cout << start << " " << finish << endl;
cout << "By CUDA Array Mult: " << (double)(finish - start)/CLOCKS_PER_SEC << endl;
cout<<"Game Over!!!!"<<endl;
return 1;
}
hipError_t calaAddArray(const double* a, const double* b, double* c, const long SIZE)
{
double* dev_a=0;
double* dev_b=0;
double* dev_c=0;
hipError_t cudaStatus=hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
cout << "CUDA ADD Failed In Function hipError_t calaAddArray " << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvA failed!" << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvB failed!" << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_c, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvC failed!" << endl;
goto Error;
}
cudaStatus = hipMemcpy(dev_a,a,SIZE * sizeof(double),hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvA failed!" << endl;
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, SIZE * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvB failed!" << endl;
goto Error;
}
addArray <<<4096,1024>>>(dev_a, dev_b, dev_c);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
cout << "addKernel launch failed: " <<hipGetErrorString(cudaStatus)<<endl;
goto Error;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess)
{
cout<<cudaStatus<<" hipDeviceSynchronize returned error code %d after launching addKernel!"<<endl;
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, SIZE * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvC failed!" << endl;
goto Error;
}
Error:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cstdlib>
#include <cmath>
#include <ctime>
using namespace std;
#include "hip/hip_runtime.h"
static const long long SIZE = 4096*4096*4;
hipError_t calaAddArray(const double* a, const double* b, double* res, const long SIZE);
__global__ void addArray(const double* a,const double *b, double* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
while (i < SIZE)
{
c[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
i += gridDim.x*blockDim.x;;
}
}
int main4444()
{
cout<<"Begin : "<<endl;
srand(time(0));
double* a = new double[SIZE];
double* b = new double[SIZE];
for (long i = 0; i < SIZE; i++)
{
a[i] = (double)rand() * (double)rand();
b[i] = (double)rand() * (double)rand();
}
double* res = new double[SIZE];
int count=2;
clock_t start, finish;
start = clock();
for(int i=0;i<count;i++)
{
for (long long i = 0; i < SIZE; i++)
res[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << res[i] << ", ";
cout << endl << endl << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i] )
{
cout << "*********** Failed CPU" << endl;
break;
}
}
cout << start << " " << finish << endl;
cout << "By CPU Array Mult: " << (double)(finish - start) / CLOCKS_PER_SEC << endl;
start = clock();
for(int i=0;i<count;i++)
{
hipError_t cudaErrorRes = calaAddArray(a, b, res, SIZE);
if (cudaErrorRes != hipSuccess)
{
cout << "************* CUDA Return Result Failed " << endl;
}
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i])
{
cout << "************* Failed GPU" << endl;
break;
}
}
cout << endl;
cout << start << " " << finish << endl;
cout << "By CUDA Array Mult: " << (double)(finish - start)/CLOCKS_PER_SEC << endl;
cout<<"Game Over!!!!"<<endl;
return 1;
}
hipError_t calaAddArray(const double* a, const double* b, double* c, const long SIZE)
{
double* dev_a=0;
double* dev_b=0;
double* dev_c=0;
hipError_t cudaStatus=hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
cout << "CUDA ADD Failed In Function hipError_t calaAddArray " << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvA failed!" << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvB failed!" << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_c, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvC failed!" << endl;
goto Error;
}
cudaStatus = hipMemcpy(dev_a,a,SIZE * sizeof(double),hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvA failed!" << endl;
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, SIZE * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvB failed!" << endl;
goto Error;
}
addArray <<<4096,1024>>>(dev_a, dev_b, dev_c);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
cout << "addKernel launch failed: " <<hipGetErrorString(cudaStatus)<<endl;
goto Error;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess)
{
cout<<cudaStatus<<" hipDeviceSynchronize returned error code %d after launching addKernel!"<<endl;
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, SIZE * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvC failed!" << endl;
goto Error;
}
Error:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8addArrayPKdS0_Pd
.globl _Z8addArrayPKdS0_Pd
.p2align 8
.type _Z8addArrayPKdS0_Pd,@function
_Z8addArrayPKdS0_Pd:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s1, 0
s_mov_b32 s9, 0xc00921fb
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s8
s_mov_b32 s8, 0x4d12d84a
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_mul_f64 v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[6:7], s[8:9], v[8:9]
v_div_scale_f64 v[12:13], null, v[4:5], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_div_scale_f64 v[16:17], vcc_lo, v[10:11], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[16:17], v[14:15]
v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19]
v_cmp_lt_i32_e32 vcc_lo, 0x3ffffff, v1
s_or_b32 s1, vcc_lo, s1
v_div_fixup_f64 v[4:5], v[12:13], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[6:7], v[4:5]
v_fma_f64 v[4:5], v[6:7], v[4:5], -v[8:9]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8addArrayPKdS0_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8addArrayPKdS0_Pd, .Lfunc_end0-_Z8addArrayPKdS0_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8addArrayPKdS0_Pd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8addArrayPKdS0_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cstdlib>
#include <cmath>
#include <ctime>
using namespace std;
#include "hip/hip_runtime.h"
static const long long SIZE = 4096*4096*4;
hipError_t calaAddArray(const double* a, const double* b, double* res, const long SIZE);
__global__ void addArray(const double* a,const double *b, double* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
while (i < SIZE)
{
c[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
i += gridDim.x*blockDim.x;;
}
}
int main4444()
{
cout<<"Begin : "<<endl;
srand(time(0));
double* a = new double[SIZE];
double* b = new double[SIZE];
for (long i = 0; i < SIZE; i++)
{
a[i] = (double)rand() * (double)rand();
b[i] = (double)rand() * (double)rand();
}
double* res = new double[SIZE];
int count=2;
clock_t start, finish;
start = clock();
for(int i=0;i<count;i++)
{
for (long long i = 0; i < SIZE; i++)
res[i] = (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i];
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << res[i] << ", ";
cout << endl << endl << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i] )
{
cout << "*********** Failed CPU" << endl;
break;
}
}
cout << start << " " << finish << endl;
cout << "By CPU Array Mult: " << (double)(finish - start) / CLOCKS_PER_SEC << endl;
start = clock();
for(int i=0;i<count;i++)
{
hipError_t cudaErrorRes = calaAddArray(a, b, res, SIZE);
if (cudaErrorRes != hipSuccess)
{
cout << "************* CUDA Return Result Failed " << endl;
}
}
finish = clock();
/*
for (int i = 0; i < SIZE; i++)
cout << a[i] << ", ";
cout << endl;
for (int i = 0; i < SIZE; i++)
cout << b[i] << ", ";
cout << endl;
*/
for (long long i = 0; i < SIZE; i++)
{
if (res[i] != (a[i] * b[i]-b[i]*3.1415926)/a[i] * b[i]*b[i]-a[i]*b[i])
{
cout << "************* Failed GPU" << endl;
break;
}
}
cout << endl;
cout << start << " " << finish << endl;
cout << "By CUDA Array Mult: " << (double)(finish - start)/CLOCKS_PER_SEC << endl;
cout<<"Game Over!!!!"<<endl;
return 1;
}
hipError_t calaAddArray(const double* a, const double* b, double* c, const long SIZE)
{
double* dev_a=0;
double* dev_b=0;
double* dev_c=0;
hipError_t cudaStatus=hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
cout << "CUDA ADD Failed In Function hipError_t calaAddArray " << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvA failed!" << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvB failed!" << endl;
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_c, sizeof(double)*SIZE);
if (cudaStatus != hipSuccess)
{
cout << "hipMalloc decvC failed!" << endl;
goto Error;
}
cudaStatus = hipMemcpy(dev_a,a,SIZE * sizeof(double),hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvA failed!" << endl;
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, SIZE * sizeof(double), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvB failed!" << endl;
goto Error;
}
addArray <<<4096,1024>>>(dev_a, dev_b, dev_c);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
cout << "addKernel launch failed: " <<hipGetErrorString(cudaStatus)<<endl;
goto Error;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess)
{
cout<<cudaStatus<<" hipDeviceSynchronize returned error code %d after launching addKernel!"<<endl;
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, SIZE * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
cout << "hipMemcpy decvC failed!" << endl;
goto Error;
}
Error:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return cudaStatus;
} | .text
.file "helloword.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__addArrayPKdS0_Pd # -- Begin function _Z23__device_stub__addArrayPKdS0_Pd
.p2align 4, 0x90
.type _Z23__device_stub__addArrayPKdS0_Pd,@function
_Z23__device_stub__addArrayPKdS0_Pd: # @_Z23__device_stub__addArrayPKdS0_Pd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8addArrayPKdS0_Pd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__addArrayPKdS0_Pd, .Lfunc_end0-_Z23__device_stub__addArrayPKdS0_Pd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8main4444v
.LCPI1_0:
.quad 0xc00921fb4d12d84a # double -3.1415926000000001
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z8main4444v
.p2align 4, 0x90
.type _Z8main4444v,@function
_Z8main4444v: # @_Z8main4444v
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_59
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $536870912, %edi # imm = 0x20000000
callq _Znam
movq %rax, %rbx
movl $536870912, %edi # imm = 0x20000000
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14,%r15,8)
incq %r15
cmpq $67108864, %r15 # imm = 0x4000000
jne .LBB1_5
# %bb.6:
movl $536870912, %edi # imm = 0x20000000
callq _Znam
movq %rax, %r15
xorl %r13d, %r13d
callq clock
movq %rax, %r12
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm0, %xmm2
mulsd %xmm1, %xmm2
movapd %xmm1, %xmm3
mulsd .LCPI1_0(%rip), %xmm3
addsd %xmm2, %xmm3
divsd %xmm0, %xmm3
mulsd %xmm1, %xmm3
mulsd %xmm1, %xmm3
subsd %xmm2, %xmm3
movsd %xmm3, (%r15,%rax,8)
incq %rax
cmpq $67108864, %rax # imm = 0x4000000
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
leal 1(%r13), %eax
testl %r13d, %r13d
movl %eax, %r13d
je .LBB1_7
# %bb.10:
xorl %ebp, %ebp
callq clock
movsd .LCPI1_0(%rip), %xmm5 # xmm5 = mem[0],zero
movq %rax, %r13
.p2align 4, 0x90
.LBB1_12: # =>This Inner Loop Header: Depth=1
movsd (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rbx,%rbp,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r14,%rbp,8), %xmm2 # xmm2 = mem[0],zero
movapd %xmm1, %xmm3
mulsd %xmm2, %xmm3
movapd %xmm2, %xmm4
mulsd %xmm5, %xmm4
addsd %xmm3, %xmm4
divsd %xmm1, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm2, %xmm4
subsd %xmm3, %xmm4
ucomisd %xmm4, %xmm0
jne .LBB1_13
jp .LBB1_13
# %bb.11: # in Loop: Header=BB1_12 Depth=1
incq %rbp
cmpq $67108864, %rbp # imm = 0x4000000
jne .LBB1_12
jmp .LBB1_18
.LBB1_13:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbp
testq %rbp, %rbp
je .LBB1_59
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%rbp)
je .LBB1_16
# %bb.15:
movzbl 67(%rbp), %eax
jmp .LBB1_17
.LBB1_16:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_18: # %.loopexit133
movl $_ZSt4cout, %edi
movq %r12, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbp
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB1_59
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%rbp)
je .LBB1_21
# %bb.20:
movzbl 67(%rbp), %ecx
jmp .LBB1_22
.LBB1_21:
movq %rbp, %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
movq (%rsp), %r12 # 8-byte Reload
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_59
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%r12)
je .LBB1_25
# %bb.24:
movzbl 67(%r12), %ecx
jmp .LBB1_26
.LBB1_25:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %ebp
callq clock
movq %rax, %r12
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_31: # in Loop: Header=BB1_27 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit107
# in Loop: Header=BB1_27 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_33: # in Loop: Header=BB1_27 Depth=1
decl %ebp
jne .LBB1_34
.LBB1_27: # =>This Inner Loop Header: Depth=1
movl $67108864, %ecx # imm = 0x4000000
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z12calaAddArrayPKdS0_Pdl
testl %eax, %eax
je .LBB1_33
# %bb.28: # in Loop: Header=BB1_27 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB1_59
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
# in Loop: Header=BB1_27 Depth=1
cmpb $0, 56(%r13)
je .LBB1_31
# %bb.30: # in Loop: Header=BB1_27 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_32
.LBB1_34:
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movsd .LCPI1_0(%rip), %xmm5 # xmm5 = mem[0],zero
.p2align 4, 0x90
.LBB1_36: # =>This Inner Loop Header: Depth=1
movsd (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rbx,%rbp,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r14,%rbp,8), %xmm2 # xmm2 = mem[0],zero
movapd %xmm1, %xmm3
mulsd %xmm2, %xmm3
movapd %xmm2, %xmm4
mulsd %xmm5, %xmm4
addsd %xmm3, %xmm4
divsd %xmm1, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm2, %xmm4
subsd %xmm3, %xmm4
ucomisd %xmm4, %xmm0
jne .LBB1_37
jp .LBB1_37
# %bb.35: # in Loop: Header=BB1_36 Depth=1
incq %rbp
cmpq $67108864, %rbp # imm = 0x4000000
jne .LBB1_36
jmp .LBB1_42
.LBB1_37:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_59
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i109
cmpb $0, 56(%rbx)
je .LBB1_40
# %bb.39:
movzbl 67(%rbx), %eax
jmp .LBB1_41
.LBB1_40:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_41: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit112
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_42: # %.loopexit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_59
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%rbx)
je .LBB1_45
# %bb.44:
movzbl 67(%rbx), %eax
jmp .LBB1_46
.LBB1_45:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movq %r12, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_59
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i119
cmpb $0, 56(%rbx)
je .LBB1_49
# %bb.48:
movzbl 67(%rbx), %ecx
jmp .LBB1_50
.LBB1_49:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit122
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_59
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
cmpb $0, 56(%rbx)
je .LBB1_53
# %bb.52:
movzbl 67(%rbx), %ecx
jmp .LBB1_54
.LBB1_53:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_59
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
cmpb $0, 56(%rbx)
je .LBB1_57
# %bb.56:
movzbl 67(%rbx), %eax
jmp .LBB1_58
.LBB1_57:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_59:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z8main4444v, .Lfunc_end1-_Z8main4444v
.cfi_endproc
# -- End function
.globl _Z12calaAddArrayPKdS0_Pdl # -- Begin function _Z12calaAddArrayPKdS0_Pdl
.p2align 4, 0x90
.type _Z12calaAddArrayPKdS0_Pdl,@function
_Z12calaAddArrayPKdS0_Pdl: # @_Z12calaAddArrayPKdS0_Pdl
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB2_5
# %bb.1:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $52, %edx
jmp .LBB2_2
.LBB2_5:
shlq $3, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_9
# %bb.6:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
jmp .LBB2_7
.LBB2_9:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
jmp .LBB2_7
.LBB2_11:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_16
# %bb.12:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
.LBB2_7:
movl $23, %edx
.LBB2_2:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_8
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_13
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB2_14
.LBB2_13:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB2_15:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_16:
.cfi_def_cfa_offset 80
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_18
# %bb.17:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
jmp .LBB2_20
.LBB2_18:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_22
# %bb.19:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
.LBB2_20:
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
.LBB2_21:
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB2_15
.LBB2_22:
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z23__device_stub__addArrayPKdS0_Pd
.LBB2_24:
callq hipGetLastError
testl %eax, %eax
je .LBB2_26
# %bb.25:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
jmp .LBB2_21
.LBB2_26:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_28
# %bb.27:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.15, %esi
movl $71, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
jmp .LBB2_21
.LBB2_28:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_30
# %bb.29:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
jmp .LBB2_20
.LBB2_30:
xorl %ebx, %ebx
jmp .LBB2_15
.LBB2_8:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z12calaAddArrayPKdS0_Pdl, .Lfunc_end2-_Z12calaAddArrayPKdS0_Pdl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8addArrayPKdS0_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8addArrayPKdS0_Pd,@object # @_Z8addArrayPKdS0_Pd
.section .rodata,"a",@progbits
.globl _Z8addArrayPKdS0_Pd
.p2align 3, 0x0
_Z8addArrayPKdS0_Pd:
.quad _Z23__device_stub__addArrayPKdS0_Pd
.size _Z8addArrayPKdS0_Pd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Begin : "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "*********** Failed CPU"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "By CPU Array Mult: "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "************* CUDA Return Result Failed "
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "************* Failed GPU"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "By CUDA Array Mult: "
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Game Over!!!!"
.size .L.str.7, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CUDA ADD Failed In Function hipError_t calaAddArray "
.size .L.str.8, 53
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc decvA failed!"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMalloc decvB failed!"
.size .L.str.10, 24
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipMalloc decvC failed!"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipMemcpy decvA failed!"
.size .L.str.12, 24
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy decvB failed!"
.size .L.str.13, 24
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "addKernel launch failed: "
.size .L.str.14, 26
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " hipDeviceSynchronize returned error code %d after launching addKernel!"
.size .L.str.15, 72
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "hipMemcpy decvC failed!"
.size .L.str.16, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8addArrayPKdS0_Pd"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__addArrayPKdS0_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8addArrayPKdS0_Pd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8addArrayPKdS0_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R20, SR_CTAID.X ; /* 0x0000000000147919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R20, R20, c[0x0][0x0], R3 ; /* 0x0000000014147a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R20, 0x3ffffff, PT ; /* 0x03ffffff1400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R2, R20, R7, c[0x0][0x160] ; /* 0x0000580014027625 */
/* 0x001fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R20, R7, c[0x0][0x168] ; /* 0x00005a0014067625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x240 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R21, RZ, RZ, R20 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0014 */
/*00f0*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x004e260000001800 */
/*0100*/ DFMA R8, -R2, R4, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000104 */
/*0110*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0120*/ DFMA R4, R4, R8, R4 ; /* 0x000000080404722b */
/* 0x001e080000000004 */
/*0130*/ DMUL R8, R6, R2 ; /* 0x0000000206087228 */
/* 0x00ae480000000000 */
/*0140*/ DFMA R10, -R2, R4, 1 ; /* 0x3ff00000020a742b */
/* 0x001e080000000104 */
/*0150*/ DFMA R14, R6, c[0x2][0x0], R8 ; /* 0x00800000060e7a2b */
/* 0x002fc80000000008 */
/*0160*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x001e0c0000000004 */
/*0170*/ DMUL R4, R14, R10 ; /* 0x0000000a0e047228 */
/* 0x001e220000000000 */
/*0180*/ FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x000fca0003f4e200 */
/*0190*/ DFMA R12, -R2, R4, R14 ; /* 0x00000004020c722b */
/* 0x001e0c000000010e */
/*01a0*/ DFMA R4, R10, R12, R4 ; /* 0x0000000c0a04722b */
/* 0x0010640000000004 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */
/* 0x001fc800078e00ff */
/*01c0*/ IMAD R20, R11, c[0x0][0x0], R20 ; /* 0x000000000b147a24 */
/* 0x000fc800078e0214 */
/*01d0*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x002fe20000000005 */
/*01e0*/ ISETP.GE.AND P1, PT, R20, 0x4000000, PT ; /* 0x040000001400780c */
/* 0x000fc80003f26270 */
/*01f0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0200*/ @P0 BRA P2, 0x230 ; /* 0x0000002000000947 */
/* 0x000fea0001000000 */
/*0210*/ MOV R0, 0x230 ; /* 0x0000023000007802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x2b0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ DMUL R4, R6, R4 ; /* 0x0000000406047228 */
/* 0x000e220000000000 */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE R2, R21, R2, c[0x0][0x170] ; /* 0x00005c0015027625 */
/* 0x000fe200078e0202 */
/*0270*/ DFMA R4, R6, R4, -R8 ; /* 0x000000040604722b */
/* 0x001e0e0000000808 */
/*0280*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011e2000c101b04 */
/*0290*/ @!P1 BRA 0x70 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*02d0*/ LOP3.LUT R10, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff030a7812 */
/* 0x000fe200078ec0ff */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0003 */
/*02f0*/ FSETP.GEU.AND P3, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f6e200 */
/*0300*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0330*/ LOP3.LUT R22, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f167812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0350*/ LOP3.LUT R25, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003197812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*0370*/ BSSY B1, 0x860 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*0380*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*0390*/ ISETP.GE.U32.AND P2, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f46070 */
/*03a0*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fc400078e0016 */
/*03b0*/ @!P3 LOP3.LUT R17, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d11b812 */
/* 0x000fe200078ec0ff */
/*03c0*/ @!P3 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12b224 */
/* 0x000fe200078e00ff */
/*03d0*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e220000001800 */
/*03e0*/ SEL R3, R23, 0x63400000, !P2 ; /* 0x6340000017037807 */
/* 0x000fe40005000000 */
/*03f0*/ @!P3 ISETP.GE.U32.AND P4, PT, R22, R17, PT ; /* 0x000000111600b20c */
/* 0x000fe40003f86070 */
/*0400*/ LOP3.LUT R3, R3, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80f */
/*0410*/ @!P3 SEL R19, R23, 0x63400000, !P4 ; /* 0x634000001713b807 */
/* 0x000fe40006000000 */
/*0420*/ @!P0 LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b198812 */
/* 0x000fc400078ec0ff */
/*0430*/ @!P3 LOP3.LUT R19, R19, 0x80000000, R15, 0xf8, !PT ; /* 0x800000001313b812 */
/* 0x000fe400078ef80f */
/*0440*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fe40007ffe0ff */
/*0450*/ @!P3 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313b812 */
/* 0x000fe200078efcff */
/*0460*/ DFMA R16, R4, -R10, 1 ; /* 0x3ff000000410742b */
/* 0x001e0a000000080a */
/*0470*/ @!P3 DFMA R2, R2, 2, -R18 ; /* 0x400000000202b82b */
/* 0x000fc80000000812 */
/*0480*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0490*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e220000000004 */
/*04a0*/ @!P3 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000318b812 */
/* 0x000fc800078ec0ff */
/*04b0*/ IADD3 R18, R24, -0x1, RZ ; /* 0xffffffff18127810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DFMA R4, R16, -R10, 1 ; /* 0x3ff000001004742b */
/* 0x001e06000000080a */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*04e0*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x001e220000000010 */
/*04f0*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0500*/ DMUL R4, R16, R2 ; /* 0x0000000210047228 */
/* 0x001e0c0000000000 */
/*0510*/ DFMA R18, R4, -R10, R2 ; /* 0x8000000a0412722b */
/* 0x001e0c0000000002 */
/*0520*/ DFMA R18, R16, R18, R4 ; /* 0x000000121012722b */
/* 0x0010620000000004 */
/*0530*/ @P0 BRA 0x700 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R5, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d057812 */
/* 0x001fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R22.reuse, R5, PT ; /* 0x000000051600720c */
/* 0x040fe20003f06070 */
/*0570*/ IMAD.IADD R4, R22, 0x1, -R5 ; /* 0x0000000116047824 */
/* 0x000fc600078e0a05 */
/*0580*/ SEL R23, R23, 0x63400000, !P0 ; /* 0x6340000017177807 */
/* 0x000fe40004000000 */
/*0590*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*05a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*05b0*/ IMAD.IADD R14, R4, 0x1, -R23 ; /* 0x00000001040e7824 */
/* 0x000fca00078e0a17 */
/*05c0*/ IADD3 R17, R14, 0x7fe00000, RZ ; /* 0x7fe000000e117810 */
/* 0x000fcc0007ffe0ff */
/*05d0*/ DMUL R4, R18, R16 ; /* 0x0000001012047228 */
/* 0x002e140000000000 */
/*05e0*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*05f0*/ @P0 BRA 0x850 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0600*/ DFMA R2, R18, -R10, R2 ; /* 0x8000000a1202722b */
/* 0x000e220000000002 */
/*0610*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*0620*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0630*/ LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fc800078e480d */
/*0640*/ LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ; /* 0x000000110d117212 */
/* 0x000fce00078efcff */
/*0650*/ @!P0 BRA 0x850 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*0670*/ DMUL.RP R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x000e220000008000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0690*/ DFMA R2, R4, -R2, R18 ; /* 0x800000020402722b */
/* 0x000e460000000012 */
/*06a0*/ LOP3.LUT R13, R17, R13, RZ, 0x3c, !PT ; /* 0x0000000d110d7212 */
/* 0x001fc600078e3cff */
/*06b0*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*06c0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*06d0*/ FSEL R4, R16, R4, !P0 ; /* 0x0000000410047208 */
/* 0x000fe40004000000 */
/*06e0*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*06f0*/ BRA 0x850 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0700*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0710*/ @P0 BRA 0x830 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0730*/ @P0 BRA 0x800 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0770*/ @!P0 BRA 0x850 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*0790*/ LOP3.LUT R5, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f057812 */
/* 0x000fe400078e480d */
/*07a0*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*07b0*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x001fe200078efcff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R5, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f057812 */
/* 0x001fe200078efcff */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff77002007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8addArrayPKdS0_Pd
.globl _Z8addArrayPKdS0_Pd
.p2align 8
.type _Z8addArrayPKdS0_Pd,@function
_Z8addArrayPKdS0_Pd:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s1, 0
s_mov_b32 s9, 0xc00921fb
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s8
s_mov_b32 s8, 0x4d12d84a
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_mul_f64 v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[6:7], s[8:9], v[8:9]
v_div_scale_f64 v[12:13], null, v[4:5], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_div_scale_f64 v[16:17], vcc_lo, v[10:11], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[16:17], v[14:15]
v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19]
v_cmp_lt_i32_e32 vcc_lo, 0x3ffffff, v1
s_or_b32 s1, vcc_lo, s1
v_div_fixup_f64 v[4:5], v[12:13], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[6:7], v[4:5]
v_fma_f64 v[4:5], v[6:7], v[4:5], -v[8:9]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8addArrayPKdS0_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8addArrayPKdS0_Pd, .Lfunc_end0-_Z8addArrayPKdS0_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8addArrayPKdS0_Pd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8addArrayPKdS0_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo) {
// Each thread process only one channel of one voxel.
int blk_idx = blockIdx.x;
int thd_idx = threadIdx.x;
int pt_idx = blk_idx * blockDim.x + thd_idx;
if (pt_idx >= batch_size * num_points) {
return;
} else {
int batch_idx = pt_idx / num_points;
int x = geom_xyz[pt_idx * 3];
int y = geom_xyz[pt_idx * 3 + 1];
int z = geom_xyz[pt_idx * 3 + 2];
// if coord of current voxel is out of boundary, return.
if (x < 0 || x >= num_voxel_x || y < 0 || y >= num_voxel_y || z < 0 || z >= num_voxel_z) {
return;
}
pos_memo[pt_idx * 3] = batch_idx;
pos_memo[pt_idx * 3 + 1] = y;
pos_memo[pt_idx * 3 + 2] = x;
for (int channel_idx = 0; channel_idx < num_channels; channel_idx++) {
atomicAdd(
&output_features[(batch_idx * num_voxel_y * num_voxel_x + y * num_voxel_x + x) * num_channels + channel_idx],
input_features[pt_idx * num_channels + channel_idx]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo,
cudaStream_t stream) {
cudaError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK)); // blockIdx.x(col), blockIdx.y(row)
dim3 threads(THREADS_PER_BLOCK);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x,
num_voxel_y, num_voxel_z, geom_xyz, input_features,
output_features, pos_memo);
// cudaDeviceSynchronize(); // for using printf in kernel function
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
} | code for sm_80
Function : _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD R5, R0, 0x3, RZ ; /* 0x0000000300057824 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD.WIDE R6, R5, R2, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fca00078e0202 */
/*00c0*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0000a8000c1e1900 */
/*00d0*/ LDG.E R4, [R6.64+0x4] ; /* 0x0000040406047981 */
/* 0x0000a8000c1e1900 */
/*00e0*/ LDG.E R11, [R6.64+0x8] ; /* 0x00000804060b7981 */
/* 0x0000e2000c1e1900 */
/*00f0*/ IABS R13, c[0x0][0x164] ; /* 0x00005900000d7a13 */
/* 0x000fc80000000000 */
/*0100*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */
/* 0x000e620000209400 */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x001fce0000000000 */
/*0120*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x002e240000001000 */
/*0130*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0170*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fcc00078e0008 */
/*0190*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R7, RZ, RZ, -R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a09 */
/*01b0*/ IMAD R6, R13, R7, R6 ; /* 0x000000070d067224 */
/* 0x000fca00078e0206 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R13, R6, PT ; /* 0x000000060d00720c */
/* 0x000fda0003f24070 */
/*01d0*/ @!P1 IMAD.IADD R6, R6, 0x1, -R13 ; /* 0x0000000106069824 */
/* 0x000fe200078e0a0d */
/*01e0*/ @!P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109099810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f25270 */
/*0200*/ ISETP.GE.U32.AND P2, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe40003f46070 */
/*0210*/ LOP3.LUT R6, R0, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590000067a12 */
/* 0x000fc800078e3cff */
/*0220*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fce0003f66270 */
/*0230*/ @P2 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109092810 */
/* 0x000fe40007ffe0ff */
/*0240*/ LOP3.LUT R7, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304077212 */
/* 0x004fc800078efcff */
/*0250*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f06270 */
/*0260*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x16c], !P0 ; /* 0x00005b0003007a0c */
/* 0x000fc80004706670 */
/*0270*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fc80000706670 */
/*0280*/ ISETP.LT.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x008fc80000701670 */
/*0290*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x174], P0 ; /* 0x00005d000b007a0c */
/* 0x000fda0000706670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*02c0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*02d0*/ LEA R6, P0, R5.reuse, c[0x0][0x190], 0x2 ; /* 0x0000640005067a11 */
/* 0x040fe400078010ff */
/*02e0*/ MOV R9, c[0x0][0x168] ; /* 0x00005a0000097a02 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P3 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0bb224 */
/* 0x000fe200078e0a0b */
/*0300*/ LEA.HI.X R7, R5, c[0x0][0x194], R8, 0x2, P0 ; /* 0x0000650005077a11 */
/* 0x000fe400000f1408 */
/*0310*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f06270 */
/*0320*/ @!P1 LOP3.LUT R11, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff0b9a12 */
/* 0x000fe200078e33ff */
/*0330*/ STG.E [R6.64+0x4], R4 ; /* 0x0000040406007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R6.64+0x8], R3 ; /* 0x0000080306007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e4000c101904 */
/*0360*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD R4, R11, c[0x0][0x170], R4 ; /* 0x00005c000b047a24 */
/* 0x001fc600078e0204 */
/*0390*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*03a0*/ LOP3.LUT R5, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309057812 */
/* 0x000fe200078ec0ff */
/*03b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd400078e00ff */
/*03c0*/ @!P0 BRA 0xc90 ; /* 0x000008c000008947 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD R6, R4, c[0x0][0x16c], R3 ; /* 0x00005b0004067a24 */
/* 0x000fe200078e0203 */
/*03e0*/ IADD3 R24, -R5, c[0x0][0x168], RZ ; /* 0x00005a0005187a10 */
/* 0x000fe20007ffe1ff */
/*03f0*/ ULDC.64 UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe40000000a00 */
/*0400*/ IMAD R7, R6, c[0x0][0x168], RZ ; /* 0x00005a0006077a24 */
/* 0x000fe200078e02ff */
/*0410*/ ISETP.GT.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fc60003f04270 */
/*0420*/ IMAD.WIDE R12, R7.reuse, R2.reuse, c[0x0][0x188] ; /* 0x00006200070c7625 */
/* 0x0c0fe200078e0202 */
/*0430*/ IADD3 R9, R7.reuse, 0x3, RZ ; /* 0x0000000307097810 */
/* 0x040fe40007ffe0ff */
/*0440*/ IADD3 R21, R7.reuse, 0x2, RZ ; /* 0x0000000207157810 */
/* 0x040fe40007ffe0ff */
/*0450*/ IADD3 R23, R7, 0x1, RZ ; /* 0x0000000107177810 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.WIDE R6, R9, R2, c[0x0][0x188] ; /* 0x0000620009067625 */
/* 0x000fc800078e0202 */
/*0470*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*0480*/ IMAD.WIDE R20, R21, R2, c[0x0][0x188] ; /* 0x0000620015147625 */
/* 0x000fc800078e0202 */
/*0490*/ IMAD.WIDE R22, R23, R2, c[0x0][0x188] ; /* 0x0000620017167625 */
/* 0x000fc800078e0202 */
/*04a0*/ IMAD R6, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a24 */
/* 0x000fe400078e02ff */
/*04b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*04c0*/ @!P0 BRA 0xae0 ; /* 0x0000061000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GT.AND P1, PT, R24, 0xc, PT ; /* 0x0000000c1800780c */
/* 0x000fe40003f24270 */
/*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*04f0*/ @!P1 BRA 0x840 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*0500*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0510*/ IMAD.U32 R10, RZ, RZ, UR6 ; /* 0x00000006ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0520*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc8000f8e00ff */
/*0530*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001ea8000c1e1900 */
/*0550*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; /* 0x0000000f0c00798e */
/* 0x0041e8000c10e784 */
/*0560*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea8000c1e1900 */
/*0570*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64], R17 ; /* 0x000000111600798e */
/* 0x0043e8000c10e784 */
/*0580*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000ea2000c1e1900 */
/*0590*/ MOV R14, R8 ; /* 0x00000008000e7202 */
/* 0x000fe20000000f00 */
/*05a0*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x001fc400078e0007 */
/*05b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64], R19 ; /* 0x000000131400798e */
/* 0x0041e8000c10e784 */
/*05c0*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R25 ; /* 0x000000190e00798e */
/* 0x0045e8000c10e784 */
/*05e0*/ LDG.E R7, [R10.64+0x10] ; /* 0x000010040a077981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x10], R7 ; /* 0x000010070c00798e */
/* 0x0087e8000c10e784 */
/*0600*/ LDG.E R27, [R10.64+0x14] ; /* 0x000014040a1b7981 */
/* 0x000f28000c1e1900 */
/*0610*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x10], R27 ; /* 0x0000101b1600798e */
/* 0x0109e8000c10e784 */
/*0620*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x002f68000c1e1900 */
/*0630*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x10], R17 ; /* 0x000010111400798e */
/* 0x0203e8000c10e784 */
/*0640*/ LDG.E R29, [R10.64+0x1c] ; /* 0x00001c040a1d7981 */
/* 0x000f68000c1e1900 */
/*0650*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x10], R29 ; /* 0x0000101d0e00798e */
/* 0x020be8000c10e784 */
/*0660*/ LDG.E R19, [R10.64+0x20] ; /* 0x000020040a137981 */
/* 0x001ea8000c1e1900 */
/*0670*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x20], R19 ; /* 0x000020130c00798e */
/* 0x0041e8000c10e784 */
/*0680*/ LDG.E R25, [R10.64+0x24] ; /* 0x000024040a197981 */
/* 0x000ea8000c1e1900 */
/*0690*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x20], R25 ; /* 0x000020191600798e */
/* 0x0045e8000c10e784 */
/*06a0*/ LDG.E R7, [R10.64+0x28] ; /* 0x000028040a077981 */
/* 0x008ee8000c1e1900 */
/*06b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x20], R7 ; /* 0x000020071400798e */
/* 0x008fe8000c10e784 */
/*06c0*/ LDG.E R27, [R10.64+0x2c] ; /* 0x00002c040a1b7981 */
/* 0x010ee8000c1e1900 */
/*06d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x20], R27 ; /* 0x0000201b0e00798e */
/* 0x008fe8000c10e784 */
/*06e0*/ LDG.E R17, [R10.64+0x30] ; /* 0x000030040a117981 */
/* 0x002ee8000c1e1900 */
/*06f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x30], R17 ; /* 0x000030110c00798e */
/* 0x008fe8000c10e784 */
/*0700*/ LDG.E R29, [R10.64+0x34] ; /* 0x000034040a1d7981 */
/* 0x020ee8000c1e1900 */
/*0710*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x30], R29 ; /* 0x0000301d1600798e */
/* 0x0083e8000c10e784 */
/*0720*/ LDG.E R19, [R10.64+0x38] ; /* 0x000038040a137981 */
/* 0x001ee2000c1e1900 */
/*0730*/ IADD3 R24, R24, -0x10, RZ ; /* 0xfffffff018187810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GT.AND P1, PT, R24, 0xc, PT ; /* 0x0000000c1800780c */
/* 0x000fe20003f24270 */
/*0750*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x30], R19 ; /* 0x000030131400798e */
/* 0x0081e8000c10e784 */
/*0760*/ LDG.E R25, [R10.64+0x3c] ; /* 0x00003c040a197981 */
/* 0x004ea2000c1e1900 */
/*0770*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0780*/ IADD3 R8, P2, R14, 0x40, RZ ; /* 0x000000400e087810 */
/* 0x000fe40007f5e0ff */
/*0790*/ IADD3 R22, P4, R22, 0x40, RZ ; /* 0x0000004016167810 */
/* 0x002fe40007f9e0ff */
/*07a0*/ IADD3 R12, P5, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc40007fbe0ff */
/*07b0*/ IADD3 R20, P3, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x001fe20007f7e0ff */
/*07c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07d0*/ IMAD.X R7, RZ, RZ, R15, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e060f */
/*07e0*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ IMAD.X R23, RZ, RZ, R23, P4 ; /* 0x000000ffff177224 */
/* 0x000fe400020e0617 */
/*0800*/ IMAD.X R21, RZ, RZ, R21, P3 ; /* 0x000000ffff157224 */
/* 0x000fe400018e0615 */
/*0810*/ IMAD.X R13, RZ, RZ, R13, P5 ; /* 0x000000ffff0d7224 */
/* 0x000fe200028e060d */
/*0820*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x30], R25 ; /* 0x000030190e00798e */
/* 0x0041e2000c10e784 */
/*0830*/ @P1 BRA 0x510 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R24, 0x4, PT ; /* 0x000000041800780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xac0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0860*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0870*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc8000f8e00ff */
/*0880*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fca00078e020a */
/*0890*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001ea2000c1e1900 */
/*08a0*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0016 */
/*08b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; /* 0x0000000f0c00798e */
/* 0x0041e8000c10e784 */
/*08c0*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ IMAD.MOV.U32 R15, RZ, RZ, R23 ; /* 0x000000ffff0f7224 */
/* 0x001fca00078e0017 */
/*08e0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R17 ; /* 0x000000110e00798e */
/* 0x0041e8000c10e784 */
/*08f0*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IMAD.MOV.U32 R16, RZ, RZ, R20 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0014 */
/*0910*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff117224 */
/* 0x001fca00078e0015 */
/*0920*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0041e8000c10e784 */
/*0930*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000ea2000c1e1900 */
/*0940*/ MOV R18, R8 ; /* 0x0000000800127202 */
/* 0x000fe20000000f00 */
/*0950*/ IMAD.MOV.U32 R19, RZ, RZ, R7 ; /* 0x000000ffff137224 */
/* 0x001fca00078e0007 */
/*0960*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R18.64], R25 ; /* 0x000000191200798e */
/* 0x004fe8000c10e784 */
/*0970*/ LDG.E R27, [R10.64+0x10] ; /* 0x000010040a1b7981 */
/* 0x000ea8000c1e1900 */
/*0980*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x10], R27 ; /* 0x0000101b0c00798e */
/* 0x0041e8000c10e784 */
/*0990*/ LDG.E R29, [R10.64+0x14] ; /* 0x000014040a1d7981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x10], R29 ; /* 0x0000101d0e00798e */
/* 0x0043e8000c10e784 */
/*09b0*/ LDG.E R26, [R10.64+0x18] ; /* 0x000018040a1a7981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64+0x10], R26 ; /* 0x0000101a1000798e */
/* 0x0043e8000c10e784 */
/*09d0*/ LDG.E R28, [R10.64+0x1c] ; /* 0x00001c040a1c7981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IADD3 R8, P1, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fc40007f3e0ff */
/*09f0*/ IADD3 R20, P2, R20, 0x20, RZ ; /* 0x0000002014147810 */
/* 0x000fe40007f5e0ff */
/*0a00*/ IADD3 R22, P3, R22, 0x20, RZ ; /* 0x0000002016167810 */
/* 0x000fe40007f7e0ff */
/*0a10*/ IADD3 R12, P4, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x001fe20007f9e0ff */
/*0a20*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R18.64+0x10], R28 ; /* 0x0000101c1200798e */
/* 0x0043e2000c10e784 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a50*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0a60*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ IMAD.X R21, RZ, RZ, R21, P2 ; /* 0x000000ffff157224 */
/* 0x000fe200010e0615 */
/*0a80*/ IADD3 R24, R24, -0x8, RZ ; /* 0xfffffff818187810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.X R23, RZ, RZ, R23, P3 ; /* 0x000000ffff177224 */
/* 0x000fe200018e0617 */
/*0aa0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ab0*/ IMAD.X R13, RZ, RZ, R13, P4 ; /* 0x000000ffff0d7224 */
/* 0x000fc400020e060d */
/*0ac0*/ ISETP.NE.OR P0, PT, R24, RZ, P0 ; /* 0x000000ff1800720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xc90 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0af0*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc8000f8e00ff */
/*0b00*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fca00078e020a */
/*0b10*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x003ea8000c1e1900 */
/*0b20*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; /* 0x0000000f0c00798e */
/* 0x0041e8000c10e784 */
/*0b30*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64], R17 ; /* 0x000000111600798e */
/* 0x0043e8000c10e784 */
/*0b50*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ IADD3 R24, R24, -0x4, RZ ; /* 0xfffffffc18187810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f05270 */
/*0b80*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64], R19 ; /* 0x000000131400798e */
/* 0x0045e8000c10e784 */
/*0b90*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000722000c1e1900 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0bb0*/ IADD3 R12, P4, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x001fe40007f9e0ff */
/*0bc0*/ IADD3 R22, P3, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x002fe20007f7e0ff */
/*0bd0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0be0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x008fc400078e0008 */
/*0bf0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*0c00*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0c10*/ IADD3 R20, P2, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x004fe20007f5e0ff */
/*0c20*/ IMAD.X R13, RZ, RZ, R13, P4 ; /* 0x000000ffff0d7224 */
/* 0x000fe200020e060d */
/*0c30*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0c50*/ IADD3.X R23, RZ, R23, RZ, P3, !PT ; /* 0x00000017ff177210 */
/* 0x000fe20001ffe4ff */
/*0c60*/ IMAD.X R21, RZ, RZ, R21, P2 ; /* 0x000000ffff157224 */
/* 0x000fe200010e0615 */
/*0c70*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R25 ; /* 0x000000190a00798e */
/* 0x0101e4000c10e784 */
/*0c80*/ @P0 BRA 0xae0 ; /* 0xfffffe5000000947 */
/* 0x001fea000383ffff */
/*0c90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ca0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cb0*/ IMAD R4, R4, c[0x0][0x16c], R3 ; /* 0x00005b0004047a24 */
/* 0x000fe400078e0203 */
/*0cc0*/ IMAD R7, R0, c[0x0][0x168], R9.reuse ; /* 0x00005a0000077a24 */
/* 0x100fe400078e0209 */
/*0cd0*/ IMAD R3, R4, c[0x0][0x168], R9 ; /* 0x00005a0004037a24 */
/* 0x000fe400078e0209 */
/*0ce0*/ IMAD.WIDE R6, R7, R2, c[0x0][0x180] ; /* 0x0000600007067625 */
/* 0x000fc800078e0202 */
/*0cf0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fc800078e0202 */
/*0d00*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0007 */
/*0d10*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0002 */
/*0d20*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0d30*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x004fe200078e0006 */
/*0d40*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fca0000000f00 */
/*0d50*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x0004e2000c1e1900 */
/*0d60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0d80*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007f3e0ff */
/*0d90*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x004fe400078e0000 */
/*0da0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0db0*/ IADD3 R0, P2, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007f5e0ff */
/*0dc0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fc800008e060b */
/*0dd0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0de0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x0085e2000c10e784 */
/*0df0*/ @P0 BRA 0xd30 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ BRA 0xe10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo) {
// Each thread process only one channel of one voxel.
int blk_idx = blockIdx.x;
int thd_idx = threadIdx.x;
int pt_idx = blk_idx * blockDim.x + thd_idx;
if (pt_idx >= batch_size * num_points) {
return;
} else {
int batch_idx = pt_idx / num_points;
int x = geom_xyz[pt_idx * 3];
int y = geom_xyz[pt_idx * 3 + 1];
int z = geom_xyz[pt_idx * 3 + 2];
// if coord of current voxel is out of boundary, return.
if (x < 0 || x >= num_voxel_x || y < 0 || y >= num_voxel_y || z < 0 || z >= num_voxel_z) {
return;
}
pos_memo[pt_idx * 3] = batch_idx;
pos_memo[pt_idx * 3 + 1] = y;
pos_memo[pt_idx * 3 + 2] = x;
for (int channel_idx = 0; channel_idx < num_channels; channel_idx++) {
atomicAdd(
&output_features[(batch_idx * num_voxel_y * num_voxel_x + y * num_voxel_x + x) * num_channels + channel_idx],
input_features[pt_idx * num_channels + channel_idx]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo,
cudaStream_t stream) {
cudaError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK)); // blockIdx.x(col), blockIdx.y(row)
dim3 threads(THREADS_PER_BLOCK);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x,
num_voxel_y, num_voxel_z, geom_xyz, input_features,
output_features, pos_memo);
// cudaDeviceSynchronize(); // for using printf in kernel function
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
} | .file "tmpxft_00005c97_00000000-6_voxel_pooling_forward_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.type _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, @function
_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi:
.LFB2082:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 240(%rsp), %rax
movq %rax, 32(%rsp)
movq 248(%rsp), %rax
movq %rax, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, .-_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, @function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA kernel failed : %s\n"
.text
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, @function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movl %edi, %edx
imull %esi, %edx
movl %edx, %ecx
sarl $31, %ecx
shrl $24, %ecx
leal (%rdx,%rcx), %eax
movzbl %al, %eax
subl %ecx, %eax
testl %eax, %eax
setg %cl
movzbl %cl, %ecx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
addl %ecx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movq 128(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, .-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) Megvii Inc. All rights reserved.
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo) {
// Each thread process only one channel of one voxel.
int blk_idx = blockIdx.x;
int thd_idx = threadIdx.x;
int pt_idx = blk_idx * blockDim.x + thd_idx;
if (pt_idx >= batch_size * num_points) {
return;
} else {
int batch_idx = pt_idx / num_points;
int x = geom_xyz[pt_idx * 3];
int y = geom_xyz[pt_idx * 3 + 1];
int z = geom_xyz[pt_idx * 3 + 2];
// if coord of current voxel is out of boundary, return.
if (x < 0 || x >= num_voxel_x || y < 0 || y >= num_voxel_y || z < 0 || z >= num_voxel_z) {
return;
}
pos_memo[pt_idx * 3] = batch_idx;
pos_memo[pt_idx * 3 + 1] = y;
pos_memo[pt_idx * 3 + 2] = x;
for (int channel_idx = 0; channel_idx < num_channels; channel_idx++) {
atomicAdd(
&output_features[(batch_idx * num_voxel_y * num_voxel_x + y * num_voxel_x + x) * num_channels + channel_idx],
input_features[pt_idx * num_channels + channel_idx]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo,
cudaStream_t stream) {
cudaError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK)); // blockIdx.x(col), blockIdx.y(row)
dim3 threads(THREADS_PER_BLOCK);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x,
num_voxel_y, num_voxel_z, geom_xyz, input_features,
output_features, pos_memo);
// cudaDeviceSynchronize(); // for using printf in kernel function
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
} | // Copyright (c) Megvii Inc. All rights reserved.
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo) {
// Each thread process only one channel of one voxel.
int blk_idx = blockIdx.x;
int thd_idx = threadIdx.x;
int pt_idx = blk_idx * blockDim.x + thd_idx;
if (pt_idx >= batch_size * num_points) {
return;
} else {
int batch_idx = pt_idx / num_points;
int x = geom_xyz[pt_idx * 3];
int y = geom_xyz[pt_idx * 3 + 1];
int z = geom_xyz[pt_idx * 3 + 2];
// if coord of current voxel is out of boundary, return.
if (x < 0 || x >= num_voxel_x || y < 0 || y >= num_voxel_y || z < 0 || z >= num_voxel_z) {
return;
}
pos_memo[pt_idx * 3] = batch_idx;
pos_memo[pt_idx * 3 + 1] = y;
pos_memo[pt_idx * 3 + 2] = x;
for (int channel_idx = 0; channel_idx < num_channels; channel_idx++) {
atomicAdd(
&output_features[(batch_idx * num_voxel_y * num_voxel_x + y * num_voxel_x + x) * num_channels + channel_idx],
input_features[pt_idx * num_channels + channel_idx]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo,
hipStream_t stream) {
hipError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK)); // blockIdx.x(col), blockIdx.y(row)
dim3 threads(THREADS_PER_BLOCK);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x,
num_voxel_y, num_voxel_z, geom_xyz, input_features,
output_features, pos_memo);
// cudaDeviceSynchronize(); // for using printf in kernel function
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo) {
// Each thread process only one channel of one voxel.
int blk_idx = blockIdx.x;
int thd_idx = threadIdx.x;
int pt_idx = blk_idx * blockDim.x + thd_idx;
if (pt_idx >= batch_size * num_points) {
return;
} else {
int batch_idx = pt_idx / num_points;
int x = geom_xyz[pt_idx * 3];
int y = geom_xyz[pt_idx * 3 + 1];
int z = geom_xyz[pt_idx * 3 + 2];
// if coord of current voxel is out of boundary, return.
if (x < 0 || x >= num_voxel_x || y < 0 || y >= num_voxel_y || z < 0 || z >= num_voxel_z) {
return;
}
pos_memo[pt_idx * 3] = batch_idx;
pos_memo[pt_idx * 3 + 1] = y;
pos_memo[pt_idx * 3 + 2] = x;
for (int channel_idx = 0; channel_idx < num_channels; channel_idx++) {
atomicAdd(
&output_features[(batch_idx * num_voxel_y * num_voxel_x + y * num_voxel_x + x) * num_channels + channel_idx],
input_features[pt_idx * num_channels + channel_idx]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo,
hipStream_t stream) {
hipError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK)); // blockIdx.x(col), blockIdx.y(row)
dim3 threads(THREADS_PER_BLOCK);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x,
num_voxel_y, num_voxel_z, geom_xyz, input_features,
output_features, pos_memo);
// cudaDeviceSynchronize(); // for using printf in kernel function
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 8
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[6:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b64 s[4:5], s[0:1], 0x18
v_lshl_add_u32 v3, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v5, 1, v3
s_load_b32 s6, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v7, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
s_load_b64 s[4:5], s[0:1], 0x10
global_load_b32 v9, v[9:10], off
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s2, s5, v9
v_cmp_lt_i32_e64 s3, -1, v9
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
s_ashr_i32 s8, s7, 31
v_ashrrev_i32_e32 v11, 31, v1
s_add_i32 s2, s7, s8
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_xor_b32 s7, s2, s8
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_cvt_f32_u32_e32 v9, s7
s_sub_i32 s2, 0, s7
v_add_nc_u32_e32 v12, v1, v11
s_load_b32 s5, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v9, v9
v_xor_b32_e32 v12, v12, v11
v_xor_b32_e32 v11, s8, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x4f7ffffe, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v9, v9
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
v_mul_lo_u32 v10, s2, v9
s_load_b64 s[2:3], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v9, v10
v_add_nc_u32_e32 v13, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v12, v13, 0
v_mul_lo_u32 v9, v10, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v12, v9
v_subrev_nc_u32_e32 v13, s7, v9
v_cmp_le_u32_e32 vcc_lo, s7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v9, v13 :: v_dual_add_nc_u32 v12, 1, v10
v_cndmask_b32_e32 v10, v10, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v9
v_add_nc_u32_e32 v12, 1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v12, v10, v12, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo
v_xor_b32_e32 v3, v12, v11
v_add_co_u32 v4, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v3, v11
v_add_co_u32 v6, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v8, vcc_lo
s_clause 0x2
global_store_b32 v[9:10], v3, off
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v0, off
s_cbranch_scc1 .LBB0_9
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
s_load_b128 s[0:3], s[0:1], 0x20
v_mul_lo_u32 v5, v1, s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s6, v[0:1]
v_mul_lo_u32 v4, v2, s5
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, s4, v5
v_add_nc_u32_e32 v2, s4, v4
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v3, v[0:1], off
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v6
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, s5
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) Megvii Inc. All rights reserved.
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m, n) ((m) / (n) + ((m) % (n) > 0))
__global__ void voxel_pooling_forward_kernel(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo) {
// Each thread process only one channel of one voxel.
int blk_idx = blockIdx.x;
int thd_idx = threadIdx.x;
int pt_idx = blk_idx * blockDim.x + thd_idx;
if (pt_idx >= batch_size * num_points) {
return;
} else {
int batch_idx = pt_idx / num_points;
int x = geom_xyz[pt_idx * 3];
int y = geom_xyz[pt_idx * 3 + 1];
int z = geom_xyz[pt_idx * 3 + 2];
// if coord of current voxel is out of boundary, return.
if (x < 0 || x >= num_voxel_x || y < 0 || y >= num_voxel_y || z < 0 || z >= num_voxel_z) {
return;
}
pos_memo[pt_idx * 3] = batch_idx;
pos_memo[pt_idx * 3 + 1] = y;
pos_memo[pt_idx * 3 + 2] = x;
for (int channel_idx = 0; channel_idx < num_channels; channel_idx++) {
atomicAdd(
&output_features[(batch_idx * num_voxel_y * num_voxel_x + y * num_voxel_x + x) * num_channels + channel_idx],
input_features[pt_idx * num_channels + channel_idx]);
}
}
}
void voxel_pooling_forward_kernel_launcher(int batch_size, int num_points, int num_channels, int num_voxel_x,
int num_voxel_y, int num_voxel_z, const int *geom_xyz,
const float *input_features, float *output_features, int *pos_memo,
hipStream_t stream) {
hipError_t err;
dim3 blocks(DIVUP(batch_size * num_points, THREADS_PER_BLOCK)); // blockIdx.x(col), blockIdx.y(row)
dim3 threads(THREADS_PER_BLOCK);
voxel_pooling_forward_kernel<<<blocks, threads, 0, stream>>>(batch_size, num_points, num_channels, num_voxel_x,
num_voxel_y, num_voxel_z, geom_xyz, input_features,
output_features, pos_memo);
// cudaDeviceSynchronize(); // for using printf in kernel function
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
} | .text
.file "voxel_pooling_forward_cuda.hip"
.globl _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi # -- Begin function _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 4, 0x90
.type _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: # @_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_endproc
# -- End function
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t # -- Begin function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.p2align 4, 0x90
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t,@function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t: # @_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movq 288(%rsp), %r9
movl %esi, %eax
imull %edi, %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
xorl %edi, %edi
testl $-2147483393, %eax # imm = 0x800000FF
setg %dil
addl %ecx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t, .Lfunc_end1-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@object # @_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata,"a",@progbits
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 3, 0x0
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.quad _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : %s\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD R5, R0, 0x3, RZ ; /* 0x0000000300057824 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD.WIDE R6, R5, R2, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fca00078e0202 */
/*00c0*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0000a8000c1e1900 */
/*00d0*/ LDG.E R4, [R6.64+0x4] ; /* 0x0000040406047981 */
/* 0x0000a8000c1e1900 */
/*00e0*/ LDG.E R11, [R6.64+0x8] ; /* 0x00000804060b7981 */
/* 0x0000e2000c1e1900 */
/*00f0*/ IABS R13, c[0x0][0x164] ; /* 0x00005900000d7a13 */
/* 0x000fc80000000000 */
/*0100*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */
/* 0x000e620000209400 */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x001fce0000000000 */
/*0120*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x002e240000001000 */
/*0130*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0170*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fcc00078e0008 */
/*0190*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R7, RZ, RZ, -R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a09 */
/*01b0*/ IMAD R6, R13, R7, R6 ; /* 0x000000070d067224 */
/* 0x000fca00078e0206 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R13, R6, PT ; /* 0x000000060d00720c */
/* 0x000fda0003f24070 */
/*01d0*/ @!P1 IMAD.IADD R6, R6, 0x1, -R13 ; /* 0x0000000106069824 */
/* 0x000fe200078e0a0d */
/*01e0*/ @!P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109099810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f25270 */
/*0200*/ ISETP.GE.U32.AND P2, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe40003f46070 */
/*0210*/ LOP3.LUT R6, R0, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590000067a12 */
/* 0x000fc800078e3cff */
/*0220*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fce0003f66270 */
/*0230*/ @P2 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109092810 */
/* 0x000fe40007ffe0ff */
/*0240*/ LOP3.LUT R7, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304077212 */
/* 0x004fc800078efcff */
/*0250*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f06270 */
/*0260*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x16c], !P0 ; /* 0x00005b0003007a0c */
/* 0x000fc80004706670 */
/*0270*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fc80000706670 */
/*0280*/ ISETP.LT.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x008fc80000701670 */
/*0290*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x174], P0 ; /* 0x00005d000b007a0c */
/* 0x000fda0000706670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*02c0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*02d0*/ LEA R6, P0, R5.reuse, c[0x0][0x190], 0x2 ; /* 0x0000640005067a11 */
/* 0x040fe400078010ff */
/*02e0*/ MOV R9, c[0x0][0x168] ; /* 0x00005a0000097a02 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P3 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0bb224 */
/* 0x000fe200078e0a0b */
/*0300*/ LEA.HI.X R7, R5, c[0x0][0x194], R8, 0x2, P0 ; /* 0x0000650005077a11 */
/* 0x000fe400000f1408 */
/*0310*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f06270 */
/*0320*/ @!P1 LOP3.LUT R11, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff0b9a12 */
/* 0x000fe200078e33ff */
/*0330*/ STG.E [R6.64+0x4], R4 ; /* 0x0000040406007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R6.64+0x8], R3 ; /* 0x0000080306007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e4000c101904 */
/*0360*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD R4, R11, c[0x0][0x170], R4 ; /* 0x00005c000b047a24 */
/* 0x001fc600078e0204 */
/*0390*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*03a0*/ LOP3.LUT R5, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309057812 */
/* 0x000fe200078ec0ff */
/*03b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd400078e00ff */
/*03c0*/ @!P0 BRA 0xc90 ; /* 0x000008c000008947 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD R6, R4, c[0x0][0x16c], R3 ; /* 0x00005b0004067a24 */
/* 0x000fe200078e0203 */
/*03e0*/ IADD3 R24, -R5, c[0x0][0x168], RZ ; /* 0x00005a0005187a10 */
/* 0x000fe20007ffe1ff */
/*03f0*/ ULDC.64 UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe40000000a00 */
/*0400*/ IMAD R7, R6, c[0x0][0x168], RZ ; /* 0x00005a0006077a24 */
/* 0x000fe200078e02ff */
/*0410*/ ISETP.GT.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fc60003f04270 */
/*0420*/ IMAD.WIDE R12, R7.reuse, R2.reuse, c[0x0][0x188] ; /* 0x00006200070c7625 */
/* 0x0c0fe200078e0202 */
/*0430*/ IADD3 R9, R7.reuse, 0x3, RZ ; /* 0x0000000307097810 */
/* 0x040fe40007ffe0ff */
/*0440*/ IADD3 R21, R7.reuse, 0x2, RZ ; /* 0x0000000207157810 */
/* 0x040fe40007ffe0ff */
/*0450*/ IADD3 R23, R7, 0x1, RZ ; /* 0x0000000107177810 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.WIDE R6, R9, R2, c[0x0][0x188] ; /* 0x0000620009067625 */
/* 0x000fc800078e0202 */
/*0470*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*0480*/ IMAD.WIDE R20, R21, R2, c[0x0][0x188] ; /* 0x0000620015147625 */
/* 0x000fc800078e0202 */
/*0490*/ IMAD.WIDE R22, R23, R2, c[0x0][0x188] ; /* 0x0000620017167625 */
/* 0x000fc800078e0202 */
/*04a0*/ IMAD R6, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a24 */
/* 0x000fe400078e02ff */
/*04b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*04c0*/ @!P0 BRA 0xae0 ; /* 0x0000061000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GT.AND P1, PT, R24, 0xc, PT ; /* 0x0000000c1800780c */
/* 0x000fe40003f24270 */
/*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*04f0*/ @!P1 BRA 0x840 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*0500*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0510*/ IMAD.U32 R10, RZ, RZ, UR6 ; /* 0x00000006ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0520*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc8000f8e00ff */
/*0530*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001ea8000c1e1900 */
/*0550*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; /* 0x0000000f0c00798e */
/* 0x0041e8000c10e784 */
/*0560*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea8000c1e1900 */
/*0570*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64], R17 ; /* 0x000000111600798e */
/* 0x0043e8000c10e784 */
/*0580*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000ea2000c1e1900 */
/*0590*/ MOV R14, R8 ; /* 0x00000008000e7202 */
/* 0x000fe20000000f00 */
/*05a0*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x001fc400078e0007 */
/*05b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64], R19 ; /* 0x000000131400798e */
/* 0x0041e8000c10e784 */
/*05c0*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R25 ; /* 0x000000190e00798e */
/* 0x0045e8000c10e784 */
/*05e0*/ LDG.E R7, [R10.64+0x10] ; /* 0x000010040a077981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x10], R7 ; /* 0x000010070c00798e */
/* 0x0087e8000c10e784 */
/*0600*/ LDG.E R27, [R10.64+0x14] ; /* 0x000014040a1b7981 */
/* 0x000f28000c1e1900 */
/*0610*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x10], R27 ; /* 0x0000101b1600798e */
/* 0x0109e8000c10e784 */
/*0620*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x002f68000c1e1900 */
/*0630*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x10], R17 ; /* 0x000010111400798e */
/* 0x0203e8000c10e784 */
/*0640*/ LDG.E R29, [R10.64+0x1c] ; /* 0x00001c040a1d7981 */
/* 0x000f68000c1e1900 */
/*0650*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x10], R29 ; /* 0x0000101d0e00798e */
/* 0x020be8000c10e784 */
/*0660*/ LDG.E R19, [R10.64+0x20] ; /* 0x000020040a137981 */
/* 0x001ea8000c1e1900 */
/*0670*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x20], R19 ; /* 0x000020130c00798e */
/* 0x0041e8000c10e784 */
/*0680*/ LDG.E R25, [R10.64+0x24] ; /* 0x000024040a197981 */
/* 0x000ea8000c1e1900 */
/*0690*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x20], R25 ; /* 0x000020191600798e */
/* 0x0045e8000c10e784 */
/*06a0*/ LDG.E R7, [R10.64+0x28] ; /* 0x000028040a077981 */
/* 0x008ee8000c1e1900 */
/*06b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x20], R7 ; /* 0x000020071400798e */
/* 0x008fe8000c10e784 */
/*06c0*/ LDG.E R27, [R10.64+0x2c] ; /* 0x00002c040a1b7981 */
/* 0x010ee8000c1e1900 */
/*06d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x20], R27 ; /* 0x0000201b0e00798e */
/* 0x008fe8000c10e784 */
/*06e0*/ LDG.E R17, [R10.64+0x30] ; /* 0x000030040a117981 */
/* 0x002ee8000c1e1900 */
/*06f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x30], R17 ; /* 0x000030110c00798e */
/* 0x008fe8000c10e784 */
/*0700*/ LDG.E R29, [R10.64+0x34] ; /* 0x000034040a1d7981 */
/* 0x020ee8000c1e1900 */
/*0710*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x30], R29 ; /* 0x0000301d1600798e */
/* 0x0083e8000c10e784 */
/*0720*/ LDG.E R19, [R10.64+0x38] ; /* 0x000038040a137981 */
/* 0x001ee2000c1e1900 */
/*0730*/ IADD3 R24, R24, -0x10, RZ ; /* 0xfffffff018187810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GT.AND P1, PT, R24, 0xc, PT ; /* 0x0000000c1800780c */
/* 0x000fe20003f24270 */
/*0750*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x30], R19 ; /* 0x000030131400798e */
/* 0x0081e8000c10e784 */
/*0760*/ LDG.E R25, [R10.64+0x3c] ; /* 0x00003c040a197981 */
/* 0x004ea2000c1e1900 */
/*0770*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0780*/ IADD3 R8, P2, R14, 0x40, RZ ; /* 0x000000400e087810 */
/* 0x000fe40007f5e0ff */
/*0790*/ IADD3 R22, P4, R22, 0x40, RZ ; /* 0x0000004016167810 */
/* 0x002fe40007f9e0ff */
/*07a0*/ IADD3 R12, P5, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc40007fbe0ff */
/*07b0*/ IADD3 R20, P3, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x001fe20007f7e0ff */
/*07c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07d0*/ IMAD.X R7, RZ, RZ, R15, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e060f */
/*07e0*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ IMAD.X R23, RZ, RZ, R23, P4 ; /* 0x000000ffff177224 */
/* 0x000fe400020e0617 */
/*0800*/ IMAD.X R21, RZ, RZ, R21, P3 ; /* 0x000000ffff157224 */
/* 0x000fe400018e0615 */
/*0810*/ IMAD.X R13, RZ, RZ, R13, P5 ; /* 0x000000ffff0d7224 */
/* 0x000fe200028e060d */
/*0820*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x30], R25 ; /* 0x000030190e00798e */
/* 0x0041e2000c10e784 */
/*0830*/ @P1 BRA 0x510 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R24, 0x4, PT ; /* 0x000000041800780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xac0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0860*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0870*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc8000f8e00ff */
/*0880*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fca00078e020a */
/*0890*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001ea2000c1e1900 */
/*08a0*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0016 */
/*08b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; /* 0x0000000f0c00798e */
/* 0x0041e8000c10e784 */
/*08c0*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ IMAD.MOV.U32 R15, RZ, RZ, R23 ; /* 0x000000ffff0f7224 */
/* 0x001fca00078e0017 */
/*08e0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R17 ; /* 0x000000110e00798e */
/* 0x0041e8000c10e784 */
/*08f0*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IMAD.MOV.U32 R16, RZ, RZ, R20 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0014 */
/*0910*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff117224 */
/* 0x001fca00078e0015 */
/*0920*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0041e8000c10e784 */
/*0930*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000ea2000c1e1900 */
/*0940*/ MOV R18, R8 ; /* 0x0000000800127202 */
/* 0x000fe20000000f00 */
/*0950*/ IMAD.MOV.U32 R19, RZ, RZ, R7 ; /* 0x000000ffff137224 */
/* 0x001fca00078e0007 */
/*0960*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R18.64], R25 ; /* 0x000000191200798e */
/* 0x004fe8000c10e784 */
/*0970*/ LDG.E R27, [R10.64+0x10] ; /* 0x000010040a1b7981 */
/* 0x000ea8000c1e1900 */
/*0980*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x10], R27 ; /* 0x0000101b0c00798e */
/* 0x0041e8000c10e784 */
/*0990*/ LDG.E R29, [R10.64+0x14] ; /* 0x000014040a1d7981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x10], R29 ; /* 0x0000101d0e00798e */
/* 0x0043e8000c10e784 */
/*09b0*/ LDG.E R26, [R10.64+0x18] ; /* 0x000018040a1a7981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64+0x10], R26 ; /* 0x0000101a1000798e */
/* 0x0043e8000c10e784 */
/*09d0*/ LDG.E R28, [R10.64+0x1c] ; /* 0x00001c040a1c7981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IADD3 R8, P1, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fc40007f3e0ff */
/*09f0*/ IADD3 R20, P2, R20, 0x20, RZ ; /* 0x0000002014147810 */
/* 0x000fe40007f5e0ff */
/*0a00*/ IADD3 R22, P3, R22, 0x20, RZ ; /* 0x0000002016167810 */
/* 0x000fe40007f7e0ff */
/*0a10*/ IADD3 R12, P4, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x001fe20007f9e0ff */
/*0a20*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R18.64+0x10], R28 ; /* 0x0000101c1200798e */
/* 0x0043e2000c10e784 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a50*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0a60*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ IMAD.X R21, RZ, RZ, R21, P2 ; /* 0x000000ffff157224 */
/* 0x000fe200010e0615 */
/*0a80*/ IADD3 R24, R24, -0x8, RZ ; /* 0xfffffff818187810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.X R23, RZ, RZ, R23, P3 ; /* 0x000000ffff177224 */
/* 0x000fe200018e0617 */
/*0aa0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ab0*/ IMAD.X R13, RZ, RZ, R13, P4 ; /* 0x000000ffff0d7224 */
/* 0x000fc400020e060d */
/*0ac0*/ ISETP.NE.OR P0, PT, R24, RZ, P0 ; /* 0x000000ff1800720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xc90 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0af0*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc8000f8e00ff */
/*0b00*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fca00078e020a */
/*0b10*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x003ea8000c1e1900 */
/*0b20*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; /* 0x0000000f0c00798e */
/* 0x0041e8000c10e784 */
/*0b30*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64], R17 ; /* 0x000000111600798e */
/* 0x0043e8000c10e784 */
/*0b50*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ IADD3 R24, R24, -0x4, RZ ; /* 0xfffffffc18187810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f05270 */
/*0b80*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64], R19 ; /* 0x000000131400798e */
/* 0x0045e8000c10e784 */
/*0b90*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000722000c1e1900 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0bb0*/ IADD3 R12, P4, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x001fe40007f9e0ff */
/*0bc0*/ IADD3 R22, P3, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x002fe20007f7e0ff */
/*0bd0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0be0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x008fc400078e0008 */
/*0bf0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*0c00*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0c10*/ IADD3 R20, P2, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x004fe20007f5e0ff */
/*0c20*/ IMAD.X R13, RZ, RZ, R13, P4 ; /* 0x000000ffff0d7224 */
/* 0x000fe200020e060d */
/*0c30*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0c50*/ IADD3.X R23, RZ, R23, RZ, P3, !PT ; /* 0x00000017ff177210 */
/* 0x000fe20001ffe4ff */
/*0c60*/ IMAD.X R21, RZ, RZ, R21, P2 ; /* 0x000000ffff157224 */
/* 0x000fe200010e0615 */
/*0c70*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R25 ; /* 0x000000190a00798e */
/* 0x0101e4000c10e784 */
/*0c80*/ @P0 BRA 0xae0 ; /* 0xfffffe5000000947 */
/* 0x001fea000383ffff */
/*0c90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ca0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cb0*/ IMAD R4, R4, c[0x0][0x16c], R3 ; /* 0x00005b0004047a24 */
/* 0x000fe400078e0203 */
/*0cc0*/ IMAD R7, R0, c[0x0][0x168], R9.reuse ; /* 0x00005a0000077a24 */
/* 0x100fe400078e0209 */
/*0cd0*/ IMAD R3, R4, c[0x0][0x168], R9 ; /* 0x00005a0004037a24 */
/* 0x000fe400078e0209 */
/*0ce0*/ IMAD.WIDE R6, R7, R2, c[0x0][0x180] ; /* 0x0000600007067625 */
/* 0x000fc800078e0202 */
/*0cf0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fc800078e0202 */
/*0d00*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0007 */
/*0d10*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0002 */
/*0d20*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0d30*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x004fe200078e0006 */
/*0d40*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fca0000000f00 */
/*0d50*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x0004e2000c1e1900 */
/*0d60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0d80*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007f3e0ff */
/*0d90*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x004fe400078e0000 */
/*0da0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0db0*/ IADD3 R0, P2, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007f5e0ff */
/*0dc0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fc800008e060b */
/*0dd0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0de0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x0085e2000c10e784 */
/*0df0*/ @P0 BRA 0xd30 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ BRA 0xe10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 8
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[6:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b64 s[4:5], s[0:1], 0x18
v_lshl_add_u32 v3, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v5, 1, v3
s_load_b32 s6, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v7, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
s_load_b64 s[4:5], s[0:1], 0x10
global_load_b32 v9, v[9:10], off
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s2, s5, v9
v_cmp_lt_i32_e64 s3, -1, v9
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
s_ashr_i32 s8, s7, 31
v_ashrrev_i32_e32 v11, 31, v1
s_add_i32 s2, s7, s8
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_xor_b32 s7, s2, s8
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_cvt_f32_u32_e32 v9, s7
s_sub_i32 s2, 0, s7
v_add_nc_u32_e32 v12, v1, v11
s_load_b32 s5, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v9, v9
v_xor_b32_e32 v12, v12, v11
v_xor_b32_e32 v11, s8, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x4f7ffffe, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v9, v9
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
v_mul_lo_u32 v10, s2, v9
s_load_b64 s[2:3], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v9, v10
v_add_nc_u32_e32 v13, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v12, v13, 0
v_mul_lo_u32 v9, v10, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v12, v9
v_subrev_nc_u32_e32 v13, s7, v9
v_cmp_le_u32_e32 vcc_lo, s7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v9, v13 :: v_dual_add_nc_u32 v12, 1, v10
v_cndmask_b32_e32 v10, v10, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v9
v_add_nc_u32_e32 v12, 1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v12, v10, v12, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo
v_xor_b32_e32 v3, v12, v11
v_add_co_u32 v4, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v3, v11
v_add_co_u32 v6, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v8, vcc_lo
s_clause 0x2
global_store_b32 v[9:10], v3, off
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v0, off
s_cbranch_scc1 .LBB0_9
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
s_load_b128 s[0:3], s[0:1], 0x20
v_mul_lo_u32 v5, v1, s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s6, v[0:1]
v_mul_lo_u32 v4, v2, s5
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, s4, v5
v_add_nc_u32_e32 v2, s4, v4
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v3, v[0:1], off
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v6
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, s5
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005c97_00000000-6_voxel_pooling_forward_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.type _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, @function
_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi:
.LFB2082:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 240(%rsp), %rax
movq %rax, 32(%rsp)
movq 248(%rsp), %rax
movq %rax, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, .-_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, @function
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA kernel failed : %s\n"
.text
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, @function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movl %edi, %edx
imull %esi, %edx
movl %edx, %ecx
sarl $31, %ecx
shrl $24, %ecx
leal (%rdx,%rcx), %eax
movzbl %al, %eax
subl %ecx, %eax
testl %eax, %eax
setg %cl
movzbl %cl, %ecx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
addl %ecx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movq 128(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, .-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "voxel_pooling_forward_cuda.hip"
.globl _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi # -- Begin function _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 4, 0x90
.type _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function
_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: # @_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.cfi_endproc
# -- End function
.globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t # -- Begin function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.p2align 4, 0x90
.type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t,@function
_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t: # @_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movq 288(%rsp), %r9
movl %esi, %eax
imull %edi, %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
xorl %edi, %edi
testl $-2147483393, %eax # imm = 0x800000FF
setg %dil
addl %ecx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t, .Lfunc_end1-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@object # @_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.section .rodata,"a",@progbits
.globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.p2align 3, 0x0
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
.quad _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : %s\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include <cuda.h>
# include <stdlib.h>
# include <stdio.h>
# include <time.h>
# include <curand_kernel.h>
# define N 10
# define CUDA_ERROR_CHECK(error) {\
e = error; \
if (e != cudaSuccess){ \
printf("%s\n", cudaGetErrorString(e)); \
exit(0); \
} \
}
__constant__ int a[2][2];
__global__ void setup_kernel ( curandState * state, unsigned long seed )
{
int id = threadIdx.x;
curand_init ( seed, id, 0, &state[id] );
}
__global__ void generate( curandState* globalState )
{
int ind = threadIdx.x;
curandState localState = globalState[ind];
int i = 0;
while (i<10){
float RANDOM = curand_uniform( &localState );
i++;
}
globalState[ind] = localState;
}
int main( int argc, char** argv)
{
cudaError_t e;
int ** c_a = (int **)malloc(sizeof(int*)*2);
c_a[0] = (int*)malloc(sizeof(int)*2);
c_a[1] = (int*)malloc(sizeof(int)*2);
c_a[0][0] = 1;
c_a[0][1] = 2;
c_a[1][0] = 4;
c_a[1][1] = 8;
printf("c_a: [%d][%d] [%d][%d]\n", c_a[0][0], c_a[0][1], c_a[1][0], c_a[1][1]);
CUDA_ERROR_CHECK(cudaMemcpyToSymbol(a, c_a, 2*2*sizeof(int)))
dim3 tpb(N,1,1);
curandState* devStates;
cudaMalloc ( &devStates, N*sizeof( curandState ) );
// setup seeds
setup_kernel <<< 1, tpb >>> ( devStates, time(NULL) );
// generate random numbers
generate <<< 1, tpb >>> ( devStates );
return 0;
} | .file "tmpxft_0011baa8_00000000-6_test1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.type _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, @function
_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, .-_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.globl _Z12setup_kernelP17curandStateXORWOWm
.type _Z12setup_kernelP17curandStateXORWOWm, @function
_Z12setup_kernelP17curandStateXORWOWm:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z12setup_kernelP17curandStateXORWOWm, .-_Z12setup_kernelP17curandStateXORWOWm
.globl _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
.type _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW, @function
_Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW:
.LFB2298:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8generateP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2298:
.size _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW, .-_Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
.globl _Z8generateP17curandStateXORWOW
.type _Z8generateP17curandStateXORWOW, @function
_Z8generateP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _Z8generateP17curandStateXORWOW, .-_Z8generateP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c_a: [%d][%d] [%d][%d]\n"
.LC1:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
movl $8, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, (%rbx)
movl $8, %edi
call malloc@PLT
movq %rax, 8(%rbx)
movl $1, 0(%rbp)
movl $2, 4(%rbp)
movl $4, (%rax)
movl $8, 4(%rax)
movl $8, %r9d
movl $4, %r8d
movl $2, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $0, %ecx
movl $16, %edx
movq %rbx, %rsi
leaq _ZL1a(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L20
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L20:
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
leaq 8(%rsp), %rdi
movl $480, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $0, %edi
call time@PLT
movq %rax, %rsi
movq 8(%rsp), %rdi
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
jmp .L21
.L26:
movq 8(%rsp), %rdi
call _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z8generateP17curandStateXORWOW"
.align 8
.LC3:
.string "_Z12setup_kernelP17curandStateXORWOWm"
.section .rodata.str1.1
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.LC13:
.string "a"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2301:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8generateP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1a(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2301:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1a
.comm _ZL1a,16,16
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include <cuda.h>
# include <stdlib.h>
# include <stdio.h>
# include <time.h>
# include <curand_kernel.h>
# define N 10
# define CUDA_ERROR_CHECK(error) {\
e = error; \
if (e != cudaSuccess){ \
printf("%s\n", cudaGetErrorString(e)); \
exit(0); \
} \
}
__constant__ int a[2][2];
__global__ void setup_kernel ( curandState * state, unsigned long seed )
{
int id = threadIdx.x;
curand_init ( seed, id, 0, &state[id] );
}
__global__ void generate( curandState* globalState )
{
int ind = threadIdx.x;
curandState localState = globalState[ind];
int i = 0;
while (i<10){
float RANDOM = curand_uniform( &localState );
i++;
}
globalState[ind] = localState;
}
int main( int argc, char** argv)
{
cudaError_t e;
int ** c_a = (int **)malloc(sizeof(int*)*2);
c_a[0] = (int*)malloc(sizeof(int)*2);
c_a[1] = (int*)malloc(sizeof(int)*2);
c_a[0][0] = 1;
c_a[0][1] = 2;
c_a[1][0] = 4;
c_a[1][1] = 8;
printf("c_a: [%d][%d] [%d][%d]\n", c_a[0][0], c_a[0][1], c_a[1][0], c_a[1][1]);
CUDA_ERROR_CHECK(cudaMemcpyToSymbol(a, c_a, 2*2*sizeof(int)))
dim3 tpb(N,1,1);
curandState* devStates;
cudaMalloc ( &devStates, N*sizeof( curandState ) );
// setup seeds
setup_kernel <<< 1, tpb >>> ( devStates, time(NULL) );
// generate random numbers
generate <<< 1, tpb >>> ( devStates );
return 0;
} | # include <hip/hip_runtime.h>
# include <stdlib.h>
# include <stdio.h>
# include <time.h>
# include <hiprand/hiprand_kernel.h>
# define N 10
# define CUDA_ERROR_CHECK(error) {\
e = error; \
if (e != hipSuccess){ \
printf("%s\n", hipGetErrorString(e)); \
exit(0); \
} \
}
__constant__ int a[2][2];
__global__ void setup_kernel ( hiprandState * state, unsigned long seed )
{
int id = threadIdx.x;
hiprand_init ( seed, id, 0, &state[id] );
}
__global__ void generate( hiprandState* globalState )
{
int ind = threadIdx.x;
hiprandState localState = globalState[ind];
int i = 0;
while (i<10){
float RANDOM = hiprand_uniform( &localState );
i++;
}
globalState[ind] = localState;
}
int main( int argc, char** argv)
{
hipError_t e;
int ** c_a = (int **)malloc(sizeof(int*)*2);
c_a[0] = (int*)malloc(sizeof(int)*2);
c_a[1] = (int*)malloc(sizeof(int)*2);
c_a[0][0] = 1;
c_a[0][1] = 2;
c_a[1][0] = 4;
c_a[1][1] = 8;
printf("c_a: [%d][%d] [%d][%d]\n", c_a[0][0], c_a[0][1], c_a[1][0], c_a[1][1]);
CUDA_ERROR_CHECK(hipMemcpyToSymbol(HIP_SYMBOL(a), c_a, 2*2*sizeof(int)))
dim3 tpb(N,1,1);
hiprandState* devStates;
hipMalloc ( &devStates, N*sizeof( hiprandState ) );
// setup seeds
setup_kernel <<< 1, tpb >>> ( devStates, time(NULL) );
// generate random numbers
generate <<< 1, tpb >>> ( devStates );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | # include <hip/hip_runtime.h>
# include <stdlib.h>
# include <stdio.h>
# include <time.h>
# include <hiprand/hiprand_kernel.h>
# define N 10
# define CUDA_ERROR_CHECK(error) {\
e = error; \
if (e != hipSuccess){ \
printf("%s\n", hipGetErrorString(e)); \
exit(0); \
} \
}
__constant__ int a[2][2];
__global__ void setup_kernel ( hiprandState * state, unsigned long seed )
{
int id = threadIdx.x;
hiprand_init ( seed, id, 0, &state[id] );
}
__global__ void generate( hiprandState* globalState )
{
int ind = threadIdx.x;
hiprandState localState = globalState[ind];
int i = 0;
while (i<10){
float RANDOM = hiprand_uniform( &localState );
i++;
}
globalState[ind] = localState;
}
int main( int argc, char** argv)
{
hipError_t e;
int ** c_a = (int **)malloc(sizeof(int*)*2);
c_a[0] = (int*)malloc(sizeof(int)*2);
c_a[1] = (int*)malloc(sizeof(int)*2);
c_a[0][0] = 1;
c_a[0][1] = 2;
c_a[1][0] = 4;
c_a[1][1] = 8;
printf("c_a: [%d][%d] [%d][%d]\n", c_a[0][0], c_a[0][1], c_a[1][0], c_a[1][1]);
CUDA_ERROR_CHECK(hipMemcpyToSymbol(HIP_SYMBOL(a), c_a, 2*2*sizeof(int)))
dim3 tpb(N,1,1);
hiprandState* devStates;
hipMalloc ( &devStates, N*sizeof( hiprandState ) );
// setup seeds
setup_kernel <<< 1, tpb >>> ( devStates, time(NULL) );
// generate random numbers
generate <<< 1, tpb >>> ( devStates );
return 0;
} | .text
.file "test1.hip"
.globl _Z27__device_stub__setup_kernelP12hiprandStatem # -- Begin function _Z27__device_stub__setup_kernelP12hiprandStatem
.p2align 4, 0x90
.type _Z27__device_stub__setup_kernelP12hiprandStatem,@function
_Z27__device_stub__setup_kernelP12hiprandStatem: # @_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__setup_kernelP12hiprandStatem, .Lfunc_end0-_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_endproc
# -- End function
.globl _Z23__device_stub__generateP12hiprandState # -- Begin function _Z23__device_stub__generateP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__generateP12hiprandState,@function
_Z23__device_stub__generateP12hiprandState: # @_Z23__device_stub__generateP12hiprandState
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8generateP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z23__device_stub__generateP12hiprandState, .Lfunc_end1-_Z23__device_stub__generateP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $8, %edi
callq malloc
movq %rax, %r14
movq %rax, (%rbx)
movl $8, %edi
callq malloc
movq %rax, 8(%rbx)
movabsq $8589934593, %rcx # imm = 0x200000001
movq %rcx, (%r14)
movabsq $34359738372, %rcx # imm = 0x800000004
movq %rcx, (%rax)
movl $.L.str, %edi
movl $1, %esi
movl $2, %edx
movl $4, %ecx
movl $8, %r8d
xorl %eax, %eax
callq printf
movl $a, %edi
movl $16, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB2_6
# %bb.1:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 80(%rsp), %rdi
movl $480, %esi # imm = 0x1E0
callq hipMalloc
leaq 9(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq 80(%rsp), %r15
xorl %edi, %edi
callq time
movq %r15, 24(%rsp)
movq %rax, 16(%rsp)
leaq 24(%rsp), %rax
movq %rax, 64(%rsp)
leaq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8generateP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_6:
.cfi_def_cfa_offset 128
movl %eax, %edi
callq hipGetErrorString
movq %rax, %rdi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12setup_kernelP12hiprandStatem, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8generateP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $a, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.local a
.comm a,16,16
.type _Z12setup_kernelP12hiprandStatem,@object # @_Z12setup_kernelP12hiprandStatem
.section .rodata,"a",@progbits
.globl _Z12setup_kernelP12hiprandStatem
.p2align 3, 0x0
_Z12setup_kernelP12hiprandStatem:
.quad _Z27__device_stub__setup_kernelP12hiprandStatem
.size _Z12setup_kernelP12hiprandStatem, 8
.type _Z8generateP12hiprandState,@object # @_Z8generateP12hiprandState
.globl _Z8generateP12hiprandState
.p2align 3, 0x0
_Z8generateP12hiprandState:
.quad _Z23__device_stub__generateP12hiprandState
.size _Z8generateP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c_a: [%d][%d] [%d][%d]\n"
.size .L.str, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12setup_kernelP12hiprandStatem"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8generateP12hiprandState"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "a"
.size .L__unnamed_3, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__setup_kernelP12hiprandStatem
.addrsig_sym _Z23__device_stub__generateP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a
.addrsig_sym _Z12setup_kernelP12hiprandStatem
.addrsig_sym _Z8generateP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011baa8_00000000-6_test1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.type _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, @function
_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, .-_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.globl _Z12setup_kernelP17curandStateXORWOWm
.type _Z12setup_kernelP17curandStateXORWOWm, @function
_Z12setup_kernelP17curandStateXORWOWm:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z12setup_kernelP17curandStateXORWOWm, .-_Z12setup_kernelP17curandStateXORWOWm
.globl _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
.type _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW, @function
_Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW:
.LFB2298:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8generateP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2298:
.size _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW, .-_Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
.globl _Z8generateP17curandStateXORWOW
.type _Z8generateP17curandStateXORWOW, @function
_Z8generateP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _Z8generateP17curandStateXORWOW, .-_Z8generateP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c_a: [%d][%d] [%d][%d]\n"
.LC1:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
movl $8, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, (%rbx)
movl $8, %edi
call malloc@PLT
movq %rax, 8(%rbx)
movl $1, 0(%rbp)
movl $2, 4(%rbp)
movl $4, (%rax)
movl $8, 4(%rax)
movl $8, %r9d
movl $4, %r8d
movl $2, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $0, %ecx
movl $16, %edx
movq %rbx, %rsi
leaq _ZL1a(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L20
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L20:
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
leaq 8(%rsp), %rdi
movl $480, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $0, %edi
call time@PLT
movq %rax, %rsi
movq 8(%rsp), %rdi
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
jmp .L21
.L26:
movq 8(%rsp), %rdi
call _Z45__device_stub__Z8generateP17curandStateXORWOWP17curandStateXORWOW
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z8generateP17curandStateXORWOW"
.align 8
.LC3:
.string "_Z12setup_kernelP17curandStateXORWOWm"
.section .rodata.str1.1
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.LC13:
.string "a"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2301:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8generateP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1a(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2301:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1a
.comm _ZL1a,16,16
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test1.hip"
.globl _Z27__device_stub__setup_kernelP12hiprandStatem # -- Begin function _Z27__device_stub__setup_kernelP12hiprandStatem
.p2align 4, 0x90
.type _Z27__device_stub__setup_kernelP12hiprandStatem,@function
_Z27__device_stub__setup_kernelP12hiprandStatem: # @_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__setup_kernelP12hiprandStatem, .Lfunc_end0-_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_endproc
# -- End function
.globl _Z23__device_stub__generateP12hiprandState # -- Begin function _Z23__device_stub__generateP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__generateP12hiprandState,@function
_Z23__device_stub__generateP12hiprandState: # @_Z23__device_stub__generateP12hiprandState
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8generateP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z23__device_stub__generateP12hiprandState, .Lfunc_end1-_Z23__device_stub__generateP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $8, %edi
callq malloc
movq %rax, %r14
movq %rax, (%rbx)
movl $8, %edi
callq malloc
movq %rax, 8(%rbx)
movabsq $8589934593, %rcx # imm = 0x200000001
movq %rcx, (%r14)
movabsq $34359738372, %rcx # imm = 0x800000004
movq %rcx, (%rax)
movl $.L.str, %edi
movl $1, %esi
movl $2, %edx
movl $4, %ecx
movl $8, %r8d
xorl %eax, %eax
callq printf
movl $a, %edi
movl $16, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB2_6
# %bb.1:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 80(%rsp), %rdi
movl $480, %esi # imm = 0x1E0
callq hipMalloc
leaq 9(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq 80(%rsp), %r15
xorl %edi, %edi
callq time
movq %r15, 24(%rsp)
movq %rax, 16(%rsp)
leaq 24(%rsp), %rax
movq %rax, 64(%rsp)
leaq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8generateP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_6:
.cfi_def_cfa_offset 128
movl %eax, %edi
callq hipGetErrorString
movq %rax, %rdi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12setup_kernelP12hiprandStatem, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8generateP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $a, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.local a
.comm a,16,16
.type _Z12setup_kernelP12hiprandStatem,@object # @_Z12setup_kernelP12hiprandStatem
.section .rodata,"a",@progbits
.globl _Z12setup_kernelP12hiprandStatem
.p2align 3, 0x0
_Z12setup_kernelP12hiprandStatem:
.quad _Z27__device_stub__setup_kernelP12hiprandStatem
.size _Z12setup_kernelP12hiprandStatem, 8
.type _Z8generateP12hiprandState,@object # @_Z8generateP12hiprandState
.globl _Z8generateP12hiprandState
.p2align 3, 0x0
_Z8generateP12hiprandState:
.quad _Z23__device_stub__generateP12hiprandState
.size _Z8generateP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c_a: [%d][%d] [%d][%d]\n"
.size .L.str, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12setup_kernelP12hiprandStatem"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8generateP12hiprandState"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "a"
.size .L__unnamed_3, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__setup_kernelP12hiprandStatem
.addrsig_sym _Z23__device_stub__generateP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a
.addrsig_sym _Z12setup_kernelP12hiprandStatem
.addrsig_sym _Z8generateP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define BLOCK_SIZE 32
__global__ void derivativeError(float *output, float *actual, float *deriv_err)
{
__shared__ float sdata[1024];
//ideally block is 1024x1 and grid is ??? x units
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y;
sdata[threadIdx.x] = output[row*gridDim.y + col];
__syncthreads();
for(int s= blockDim.x / 2; s>0; s>>=1)
{
if(threadIdx.x < s)
sdata[threadIdx.x] += sdata[threadIdx.x+s];
__syncthreads();
}
if(threadIdx.x == 0) //only tid0 can write
{
/*deriv_err[blockIdx.x] = sdata[0]*/deriv_err[blockDim.y*blockIdx.x+col] = sdata[blockIdx.x];
}
} | code for sm_80
Function : _Z15derivativeErrorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fc800078e0207 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R9 ; /* 0x0000040000007a24 */
/* 0x002fc800078e0209 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0150*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0170*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01e0*/ SHF.L.U32 R0, R6.reuse, 0x2, RZ ; /* 0x0000000206007819 */
/* 0x040fe200000006ff */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD R2, R6, c[0x0][0x4], R9 ; /* 0x0000010006027a24 */
/* 0x000fe400078e0209 */
/*0210*/ LDS R5, [R0] ; /* 0x0000000000057984 */
/* 0x000e240000000800 */
/*0220*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0003 */
/*0230*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define BLOCK_SIZE 32
__global__ void derivativeError(float *output, float *actual, float *deriv_err)
{
__shared__ float sdata[1024];
//ideally block is 1024x1 and grid is ??? x units
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y;
sdata[threadIdx.x] = output[row*gridDim.y + col];
__syncthreads();
for(int s= blockDim.x / 2; s>0; s>>=1)
{
if(threadIdx.x < s)
sdata[threadIdx.x] += sdata[threadIdx.x+s];
__syncthreads();
}
if(threadIdx.x == 0) //only tid0 can write
{
/*deriv_err[blockIdx.x] = sdata[0]*/deriv_err[blockDim.y*blockIdx.x+col] = sdata[blockIdx.x];
}
} | .file "tmpxft_000ec3b2_00000000-6_derivativeError.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_
.type _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_, @function
_Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15derivativeErrorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_, .-_Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_
.globl _Z15derivativeErrorPfS_S_
.type _Z15derivativeErrorPfS_S_, @function
_Z15derivativeErrorPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15derivativeErrorPfS_S_, .-_Z15derivativeErrorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15derivativeErrorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15derivativeErrorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define BLOCK_SIZE 32
__global__ void derivativeError(float *output, float *actual, float *deriv_err)
{
__shared__ float sdata[1024];
//ideally block is 1024x1 and grid is ??? x units
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y;
sdata[threadIdx.x] = output[row*gridDim.y + col];
__syncthreads();
for(int s= blockDim.x / 2; s>0; s>>=1)
{
if(threadIdx.x < s)
sdata[threadIdx.x] += sdata[threadIdx.x+s];
__syncthreads();
}
if(threadIdx.x == 0) //only tid0 can write
{
/*deriv_err[blockIdx.x] = sdata[0]*/deriv_err[blockDim.y*blockIdx.x+col] = sdata[blockIdx.x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 32
__global__ void derivativeError(float *output, float *actual, float *deriv_err)
{
__shared__ float sdata[1024];
//ideally block is 1024x1 and grid is ??? x units
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y;
sdata[threadIdx.x] = output[row*gridDim.y + col];
__syncthreads();
for(int s= blockDim.x / 2; s>0; s>>=1)
{
if(threadIdx.x < s)
sdata[threadIdx.x] += sdata[threadIdx.x+s];
__syncthreads();
}
if(threadIdx.x == 0) //only tid0 can write
{
/*deriv_err[blockIdx.x] = sdata[0]*/deriv_err[blockDim.y*blockIdx.x+col] = sdata[blockIdx.x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 32
__global__ void derivativeError(float *output, float *actual, float *deriv_err)
{
__shared__ float sdata[1024];
//ideally block is 1024x1 and grid is ??? x units
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y;
sdata[threadIdx.x] = output[row*gridDim.y + col];
__syncthreads();
for(int s= blockDim.x / 2; s>0; s>>=1)
{
if(threadIdx.x < s)
sdata[threadIdx.x] += sdata[threadIdx.x+s];
__syncthreads();
}
if(threadIdx.x == 0) //only tid0 can write
{
/*deriv_err[blockIdx.x] = sdata[0]*/deriv_err[blockDim.y*blockIdx.x+col] = sdata[blockIdx.x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15derivativeErrorPfS_S_
.globl _Z15derivativeErrorPfS_S_
.p2align 8
.type _Z15derivativeErrorPfS_S_,@function
_Z15derivativeErrorPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_mad_u64_u32 v[2:3], null, v1, s8, s[2:3]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s6
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s6, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_load_b32 s4, s[4:5], 0xc
s_lshl_b32 s5, s14, 2
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s14, s4
s_add_i32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15derivativeErrorPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15derivativeErrorPfS_S_, .Lfunc_end0-_Z15derivativeErrorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15derivativeErrorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15derivativeErrorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 32
__global__ void derivativeError(float *output, float *actual, float *deriv_err)
{
__shared__ float sdata[1024];
//ideally block is 1024x1 and grid is ??? x units
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y;
sdata[threadIdx.x] = output[row*gridDim.y + col];
__syncthreads();
for(int s= blockDim.x / 2; s>0; s>>=1)
{
if(threadIdx.x < s)
sdata[threadIdx.x] += sdata[threadIdx.x+s];
__syncthreads();
}
if(threadIdx.x == 0) //only tid0 can write
{
/*deriv_err[blockIdx.x] = sdata[0]*/deriv_err[blockDim.y*blockIdx.x+col] = sdata[blockIdx.x];
}
} | .text
.file "derivativeError.hip"
.globl _Z30__device_stub__derivativeErrorPfS_S_ # -- Begin function _Z30__device_stub__derivativeErrorPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__derivativeErrorPfS_S_,@function
_Z30__device_stub__derivativeErrorPfS_S_: # @_Z30__device_stub__derivativeErrorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15derivativeErrorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__derivativeErrorPfS_S_, .Lfunc_end0-_Z30__device_stub__derivativeErrorPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15derivativeErrorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15derivativeErrorPfS_S_,@object # @_Z15derivativeErrorPfS_S_
.section .rodata,"a",@progbits
.globl _Z15derivativeErrorPfS_S_
.p2align 3, 0x0
_Z15derivativeErrorPfS_S_:
.quad _Z30__device_stub__derivativeErrorPfS_S_
.size _Z15derivativeErrorPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15derivativeErrorPfS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__derivativeErrorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15derivativeErrorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15derivativeErrorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fc800078e0207 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R9 ; /* 0x0000040000007a24 */
/* 0x002fc800078e0209 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0150*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0170*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01e0*/ SHF.L.U32 R0, R6.reuse, 0x2, RZ ; /* 0x0000000206007819 */
/* 0x040fe200000006ff */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD R2, R6, c[0x0][0x4], R9 ; /* 0x0000010006027a24 */
/* 0x000fe400078e0209 */
/*0210*/ LDS R5, [R0] ; /* 0x0000000000057984 */
/* 0x000e240000000800 */
/*0220*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0003 */
/*0230*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15derivativeErrorPfS_S_
.globl _Z15derivativeErrorPfS_S_
.p2align 8
.type _Z15derivativeErrorPfS_S_,@function
_Z15derivativeErrorPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_mad_u64_u32 v[2:3], null, v1, s8, s[2:3]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s6
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s6, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_load_b32 s4, s[4:5], 0xc
s_lshl_b32 s5, s14, 2
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s14, s4
s_add_i32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15derivativeErrorPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15derivativeErrorPfS_S_, .Lfunc_end0-_Z15derivativeErrorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15derivativeErrorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15derivativeErrorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ec3b2_00000000-6_derivativeError.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_
.type _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_, @function
_Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15derivativeErrorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_, .-_Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_
.globl _Z15derivativeErrorPfS_S_
.type _Z15derivativeErrorPfS_S_, @function
_Z15derivativeErrorPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15derivativeErrorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15derivativeErrorPfS_S_, .-_Z15derivativeErrorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15derivativeErrorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15derivativeErrorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "derivativeError.hip"
.globl _Z30__device_stub__derivativeErrorPfS_S_ # -- Begin function _Z30__device_stub__derivativeErrorPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__derivativeErrorPfS_S_,@function
_Z30__device_stub__derivativeErrorPfS_S_: # @_Z30__device_stub__derivativeErrorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15derivativeErrorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__derivativeErrorPfS_S_, .Lfunc_end0-_Z30__device_stub__derivativeErrorPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15derivativeErrorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15derivativeErrorPfS_S_,@object # @_Z15derivativeErrorPfS_S_
.section .rodata,"a",@progbits
.globl _Z15derivativeErrorPfS_S_
.p2align 3, 0x0
_Z15derivativeErrorPfS_S_:
.quad _Z30__device_stub__derivativeErrorPfS_S_
.size _Z15derivativeErrorPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15derivativeErrorPfS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__derivativeErrorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15derivativeErrorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifdef USE_DOUBLE
#define real_t double
#define fftComplex_t cufftDoubleComplex
#define complex_t cuDoubleComplex
#else
#define real_t double
#define fftComplex_t cufftDoubleComplex
#define complex_t cuDoubleComplex
#endif
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include <cuComplex.h>
#define nThrdsX 16
#define nThrdsY 16
#define nThrds 256
#define clight 299792458
#define PI 3.14159265358979323846
#define cmtops (2*PI*clight*1.e-10)
__device__ __forceinline__ cuDoubleComplex my_cexpc (cuDoubleComplex z)
{
cuDoubleComplex res;
double t = exp(z.x);
res.x=cos(z.y);
res.y=sin(z.y);
res.x *= t;
res.y *= t;
return res;
}
__device__ __forceinline__ cuDoubleComplex my_cexpf (double z)
{
cuDoubleComplex res;
res.x=exp(z);
res.y=0.0;
return res;
}
__device__ __forceinline__ cuDoubleComplex my_cexpi (double z)
{
cuDoubleComplex res;
res.x=cos(z);
res.y=sin(z);
return res;
}
__device__ double g(double t, double *d_param)
{
double f1,f2,f3,f4;
f1=d_param[3]*exp(-t/d_param[6]);
f2=d_param[4]*exp(-t/d_param[7]);
f3=d_param[5]*exp(-t/d_param[8]);
f4=(d_param[0]+d_param[1]+d_param[2])*t-(d_param[3]+d_param[4]+d_param[5]);
return ( f1 + f2 + f3 + f4 );
}
__device__ cuDoubleComplex Rr(double t1 ,double t2, double t3, double *d_param)
{
cuDoubleComplex f1;
cuDoubleComplex f2;
f1 = my_cexpi( -( t3 - t1 ) * d_param[9] * cmtops );
f1 = cuCsub(f1 , cuCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 - ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = cuCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf(-g(t1,d_param) + g(t2,d_param) - g(t3,d_param) - g(t1+t2,d_param) - g(t2+t3,d_param) + g(t1+t2+t3,d_param) );
return cuCmul( f1 , f2 );
}
__device__ cuDoubleComplex Rnr(double t1 ,double t2, double t3, double *d_param)
{
cuDoubleComplex f1;
cuDoubleComplex f2;
f1 = my_cexpi( -( t3 + t1 ) * d_param[9] * cmtops );
f1 = cuCsub(f1 , cuCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 + ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = cuCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf( -g(t1,d_param) - g(t2,d_param) - g(t3,d_param) + g(t1+t2,d_param) + g(t2+t3,d_param) - g(t1+t2+t3,d_param) );
return cuCmul( f1 , f2 );
}
__global__ void kernelHalfFirstX(cufftDoubleComplex *d_r)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
cuDoubleComplex half;
half.x=0.5;
half.y=0.0;
d_r[i]=cuCmul(d_r[i],half);
}
__global__ void kernelHalfFirstY(cufftDoubleComplex *d_r, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = i*n;
cuDoubleComplex half;
half.x=0.5;
half.y=0.0;
if (j>0)
d_r[j]=cuCmul(d_r[j],half);
}
__global__ void kernelPermutation(cufftDoubleComplex *d_r,cufftDoubleComplex *d_ftr, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
int l = i * n + j + n/2 ;
int m = ( i + n/2 ) * n + j;
int p = ( i + n/2 ) * n + j + n/2;
d_r[m]=d_ftr[l];
d_r[p]=d_ftr[k];
d_r[l]=d_ftr[m];
d_r[k]=d_ftr[p];
}
__global__ void kernelRephasing(cufftDoubleComplex *d_r,double dt,double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rr(t1,t2,t3,d_param);
}
__global__ void kernelNonRephasing(cufftDoubleComplex *d_r, double dt, double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k= i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rnr(t1,t2,t3,d_param);
}
int main(int argc, char* argv[])
{
FILE* input=fopen(argv[1],"r");
FILE* out=fopen("spec.dat","w");
int i,ii,j,l,test;
int iw1,iw3,iFirst,iLast,jFirst,jLast;
int ndata,nw1,nw3,nave;
double t2,dt;
double w1min,w1max,w3min,w3max;
double w1,w3;
double **res;
double c1,tau1,c2,tau2,c3,tau3,wm,delta,tLife,alpha;
fscanf(input,"%lf %lf %lf %lf",&w1min,&w1max,&w3min,&w3max);
fscanf(input,"%lf %lf %lf",&delta,&tLife,&alpha);
fscanf(input,"%d %lf",&ndata,&dt);
fscanf(input,"%lf",&t2);
fscanf(input,"%d",&nave);
ndata=(int)(ndata/nThrds)+1;
ndata=nThrds*2*(int)(ndata/2);
printf("%d %d\n",ndata,nThrds);
nw1=0;
test=1;
for(i=ndata/2-1;i<ndata-1;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
if(w1>w1max)
{
iLast=i-1;
break;
}
if( w1>=w1min )
{
nw1++;
if(test)
{
test=0;
iFirst=i;
}
}
}
nw3=0;
test=1;
for(j=ndata/2-1;j<ndata-1;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
if(w3>w3max)
{
jLast=j-1;
break;
}
if( w3>=w3min )
{
nw3++;
if(test)
{
test=0;
jFirst=j;
}
}
}
printf("%d %d %d %d %d %d\n",iFirst,iLast,jFirst,jLast,nw1,nw3);
res=(double**)malloc(nw1*sizeof(double*));
for(i=0;i<nw1;i++)
{
res[i]=(double*)malloc(nw3*sizeof(double));
for(j=0;j<nw3;j++)
res[i][j]=0.0;
}
double *param,*d_param;
param=(double*)malloc(13*sizeof(double));
cudaMalloc((void**) &d_param,13*sizeof(double));
param[10]=delta;
param[11]=tLife;
param[12]=alpha;
cufftDoubleComplex *d_rlist,*d_ftrlist,*rlist;
cufftHandle d_pr;
rlist=(cufftDoubleComplex*)malloc(ndata*ndata*sizeof(cufftDoubleComplex));
cudaMalloc((void**) &d_rlist,ndata*ndata*sizeof(cufftDoubleComplex));
cudaMalloc((void**) &d_ftrlist,ndata*ndata*sizeof(cufftDoubleComplex));
cufftPlan2d(&d_pr,ndata,ndata,CUFFT_Z2Z);
dim3 threadsPerBlock(nThrdsX, nThrdsY);
dim3 numBlocks(ndata / threadsPerBlock.x, ndata / threadsPerBlock.y);
dim3 numHalfBlocks( (ndata/2) / threadsPerBlock.x, (ndata/2) / threadsPerBlock.y );
for(ii=0;ii<nave;ii++)
{
fscanf(input,"%lf",&wm);
fscanf(input,"%lf",&c1);
fscanf(input,"%lf",&c2);
fscanf(input,"%lf",&c3);
fscanf(input,"%lf",&tau1);
fscanf(input,"%lf",&tau2);
fscanf(input,"%lf",&tau3);
printf("%lf %lf %lf %lf %lf %lf %lf\n",wm,c1,c2,c3,tau1,tau2,tau3);
param[0]=c1*tau1;
param[1]=c2*tau2;
param[2]=c3*tau3;
param[3]=param[0]*tau1;
param[4]=param[1]*tau2;
param[5]=param[2]*tau3;
param[6]=tau1;
param[7]=tau2;
param[8]=tau3;
param[9]=wm;
cudaMemcpy(d_param,param,13*sizeof(double),cudaMemcpyHostToDevice);
// Rephasing component
kernelRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
cufftExecZ2Z(d_pr,d_rlist,d_ftrlist,CUFFT_INVERSE);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
cudaMemcpy(rlist,d_rlist,ndata*ndata*sizeof(cufftDoubleComplex),cudaMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(ndata-i-1)+j+1;
res[iw1][iw3]+=cuCreal(rlist[l]);
iw3++;
}
iw1++;
}
// Non-rephasing component
kernelNonRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
cufftExecZ2Z(d_pr,d_rlist,d_ftrlist,CUFFT_INVERSE);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
cudaMemcpy(rlist,d_rlist,ndata*ndata*sizeof(cufftDoubleComplex),cudaMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(i+1)+j+1;
res[iw1][iw3]+=cuCreal(rlist[l]);
iw3++;
}
iw1++;
}
}
cufftDestroy(d_pr);
cudaFree(d_rlist);
cudaFree(d_ftrlist);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
fprintf(out,"%lf\t%lf\t%le\n",w1,w3,res[iw1][iw3]/(double)ndata);
iw3++;
}
fprintf(out,"\n");
iw1++;
}
for(i=0;i<nw1;i++)
free(res[i]);
free(res);
fclose(out);
fclose(input);
return 0;
} | .file "tmpxft_00132e9e_00000000-6_irspec_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1gdPd
.type _Z1gdPd, @function
_Z1gdPd:
.LFB2083:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2083:
.size _Z1gdPd, .-_Z1gdPd
.globl _Z2RrdddPd
.type _Z2RrdddPd, @function
_Z2RrdddPd:
.LFB2084:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2084:
.size _Z2RrdddPd, .-_Z2RrdddPd
.globl _Z3RnrdddPd
.type _Z3RnrdddPd, @function
_Z3RnrdddPd:
.LFB2085:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2085:
.size _Z3RnrdddPd, .-_Z3RnrdddPd
.globl _Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2
.type _Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2, @function
_Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2:
.LFB2111:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16kernelHalfFirstXP7double2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2111:
.size _Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2, .-_Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2
.globl _Z16kernelHalfFirstXP7double2
.type _Z16kernelHalfFirstXP7double2, @function
_Z16kernelHalfFirstXP7double2:
.LFB2112:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2112:
.size _Z16kernelHalfFirstXP7double2, .-_Z16kernelHalfFirstXP7double2
.globl _Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i
.type _Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i, @function
_Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i:
.LFB2113:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16kernelHalfFirstYP7double2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2113:
.size _Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i, .-_Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i
.globl _Z16kernelHalfFirstYP7double2i
.type _Z16kernelHalfFirstYP7double2i, @function
_Z16kernelHalfFirstYP7double2i:
.LFB2114:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2114:
.size _Z16kernelHalfFirstYP7double2i, .-_Z16kernelHalfFirstYP7double2i
.globl _Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i
.type _Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i, @function
_Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i:
.LFB2115:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kernelPermutationP7double2S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2115:
.size _Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i, .-_Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i
.globl _Z17kernelPermutationP7double2S0_i
.type _Z17kernelPermutationP7double2S0_i, @function
_Z17kernelPermutationP7double2S0_i:
.LFB2116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2116:
.size _Z17kernelPermutationP7double2S0_i, .-_Z17kernelPermutationP7double2S0_i
.globl _Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd
.type _Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd, @function
_Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd:
.LFB2117:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kernelRephasingP7double2ddiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2117:
.size _Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd, .-_Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd
.globl _Z15kernelRephasingP7double2ddiPd
.type _Z15kernelRephasingP7double2ddiPd, @function
_Z15kernelRephasingP7double2ddiPd:
.LFB2118:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2118:
.size _Z15kernelRephasingP7double2ddiPd, .-_Z15kernelRephasingP7double2ddiPd
.globl _Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd
.type _Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd, @function
_Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd:
.LFB2119:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kernelNonRephasingP7double2ddiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2119:
.size _Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd, .-_Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd
.globl _Z18kernelNonRephasingP7double2ddiPd
.type _Z18kernelNonRephasingP7double2ddiPd, @function
_Z18kernelNonRephasingP7double2ddiPd:
.LFB2120:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2120:
.size _Z18kernelNonRephasingP7double2ddiPd, .-_Z18kernelNonRephasingP7double2ddiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "w"
.LC2:
.string "spec.dat"
.LC3:
.string "%lf %lf %lf %lf"
.LC4:
.string "%lf %lf %lf"
.LC5:
.string "%d %lf"
.LC6:
.string "%lf"
.LC7:
.string "%d"
.LC8:
.string "%d %d\n"
.LC11:
.string "%d %d %d %d %d %d\n"
.LC13:
.string "%lf %lf %lf %lf %lf %lf %lf\n"
.LC14:
.string "%lf\t%lf\t%le\n"
.LC15:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2086:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $296, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r15
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 120(%rsp), %r9
leaq 112(%rsp), %r8
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 192(%rsp), %rcx
leaq 184(%rsp), %rdx
leaq 200(%rsp), %r8
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 88(%rsp), %rcx
leaq 68(%rsp), %rdx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 80(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 72(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %edx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
sall $9, %edx
movl %edx, 68(%rsp)
movl $256, %ecx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 68(%rsp), %ecx
movl %ecx, %edi
shrl $31, %edi
addl %ecx, %edi
sarl %edi
cmpl %edi, %ecx
jle .L50
leal -1(%rdi), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd .LC9(%rip), %xmm0
mulsd 88(%rsp), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd 104(%rsp), %xmm3
movsd 96(%rsp), %xmm2
subl $1, %ecx
movl %eax, %edx
movl $0, %r10d
movl $1, %r8d
movl $1, %esi
subl %edi, %esi
movl $0, %r9d
jmp .L56
.L117:
movl %r10d, 52(%rsp)
leal -1(%rdx), %ebx
movl %ebx, 48(%rsp)
.L53:
movsd 120(%rsp), %xmm3
movsd 112(%rsp), %xmm2
movl $0, %r12d
movl $1, %edi
movl $0, %r8d
jmp .L62
.L54:
addl $1, %edx
cmpl %ecx, %edx
je .L116
.L56:
leal (%rdx,%rsi), %edi
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
mulsd %xmm1, %xmm0
comisd %xmm3, %xmm0
ja .L117
comisd %xmm2, %xmm0
jb .L54
addl $1, %r10d
testl %r8d, %r8d
je .L54
movl %edx, 28(%rsp)
movl %r9d, %r8d
jmp .L54
.L116:
movl %r10d, 52(%rsp)
jmp .L53
.L118:
leal -1(%rax), %ebp
.L59:
pushq %r12
.cfi_def_cfa_offset 360
movl 60(%rsp), %ebx
pushq %rbx
.cfi_def_cfa_offset 368
movl %ebp, %r9d
movl %r13d, %r8d
movl 64(%rsp), %ecx
movl 44(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
salq $3, %rax
movq %rax, 72(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rsi
movq %rax, 48(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 352
testl %ebx, %ebx
jle .L63
movslq %r12d, %r14
salq $3, %r14
movq %rax, %rbx
movq 56(%rsp), %rax
addq %rsi, %rax
movl %ebp, 8(%rsp)
movq %rax, %rbp
.L66:
movq %r14, %rdi
call malloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L64
movq %rax, %rdx
addq %r14, %rax
.L65:
movq $0x000000000, (%rdx)
addq $8, %rdx
cmpq %rax, %rdx
jne .L65
.L64:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L66
movl 8(%rsp), %ebp
.L63:
movl $104, %edi
call malloc@PLT
movq %rax, %r14
leaq 208(%rsp), %rdi
movl $104, %esi
call cudaMalloc@PLT
movsd 184(%rsp), %xmm0
movsd %xmm0, 80(%r14)
movsd 192(%rsp), %xmm0
movsd %xmm0, 88(%r14)
movsd 200(%rsp), %xmm0
movsd %xmm0, 96(%r14)
movl 68(%rsp), %eax
imull %eax, %eax
movslq %eax, %r12
salq $4, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 216(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl 68(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $4, %rsi
leaq 224(%rsp), %rdi
call cudaMalloc@PLT
movl 68(%rsp), %esi
leaq 76(%rsp), %rdi
movl $105, %ecx
movl %esi, %edx
call cufftPlan2d@PLT
movl $1, 240(%rsp)
movl 68(%rsp), %edx
movl %edx, %eax
shrl $4, %eax
movl %eax, 244(%rsp)
movl %eax, 248(%rsp)
movl $1, 252(%rsp)
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
shrl $4, %eax
movl %eax, 256(%rsp)
movl %eax, 260(%rsp)
movl $1, 264(%rsp)
cmpl $0, 72(%rsp)
jle .L67
movl $0, 8(%rsp)
movslq %r13d, %r12
addq $1, %r12
movq %r15, 40(%rsp)
movl 28(%rsp), %r15d
jmp .L86
.L60:
addl $1, %eax
cmpl %ecx, %eax
je .L59
.L62:
leal (%rax,%rsi), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd %xmm1, %xmm0
comisd %xmm3, %xmm0
ja .L118
comisd %xmm2, %xmm0
jb .L60
addl $1, %r12d
testl %edi, %edi
je .L60
movl %eax, %r13d
movl %r8d, %edi
jmp .L60
.L124:
movq 208(%rsp), %rdx
movl 68(%rsp), %esi
movsd 80(%rsp), %xmm1
movsd 88(%rsp), %xmm0
movq 216(%rsp), %rdi
call _Z47__device_stub__Z15kernelRephasingP7double2ddiPdP7double2ddiPd
jmp .L68
.L125:
movq 216(%rsp), %rdi
call _Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2
jmp .L69
.L126:
movl 68(%rsp), %esi
movq 216(%rsp), %rdi
call _Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i
jmp .L70
.L127:
movl 68(%rsp), %edx
movq 224(%rsp), %rsi
movq 216(%rsp), %rdi
call _Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i
jmp .L71
.L75:
movslq %esi, %rdx
addq %r12, %rdx
salq $4, %rdx
addq %rbx, %rdx
movq (%rcx), %rax
leaq (%r9,%rax), %r10
.L74:
movsd (%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rax)
addq $16, %rdx
addq $8, %rax
cmpq %r10, %rax
jne .L74
.L76:
subl %edi, %esi
addq $8, %rcx
cmpq %r8, %rcx
je .L72
.L73:
cmpl %r13d, %ebp
jge .L75
jmp .L76
.L72:
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 244(%rsp), %rdi
movl 252(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L119
.L77:
movl 68(%rsp), %eax
shrl $4, %eax
movl %eax, 268(%rsp)
movl $1, 272(%rsp)
movl $1, 276(%rsp)
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 268(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L120
.L78:
movl 68(%rsp), %eax
shrl $4, %eax
movl %eax, 268(%rsp)
movl $1, 272(%rsp)
movl $1, 276(%rsp)
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 268(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L121
.L79:
movl $1, %ecx
movq 224(%rsp), %rdx
movq 216(%rsp), %rsi
movl 76(%rsp), %edi
call cufftExecZ2Z@PLT
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 256(%rsp), %rdi
movl 264(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L122
.L80:
movl 68(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $4, %rdx
movl $2, %ecx
movq 216(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 48(%rsp), %edx
cmpl %r15d, %edx
jl .L81
movl 68(%rsp), %edi
leal 1(%r15), %esi
imull %edi, %esi
movq 32(%rsp), %r11
movq %r11, %rcx
movl %edx, %eax
subl %r15d, %eax
leaq 8(%r11,%rax,8), %r8
movl %ebp, %eax
subl %r13d, %eax
leaq 8(,%rax,8), %r9
jmp .L82
.L119:
movq 208(%rsp), %rdx
movl 68(%rsp), %esi
movsd 80(%rsp), %xmm1
movsd 88(%rsp), %xmm0
movq 216(%rsp), %rdi
call _Z50__device_stub__Z18kernelNonRephasingP7double2ddiPdP7double2ddiPd
jmp .L77
.L120:
movq 216(%rsp), %rdi
call _Z43__device_stub__Z16kernelHalfFirstXP7double2P7double2
jmp .L78
.L121:
movl 68(%rsp), %esi
movq 216(%rsp), %rdi
call _Z44__device_stub__Z16kernelHalfFirstYP7double2iP7double2i
jmp .L79
.L122:
movl 68(%rsp), %edx
movq 224(%rsp), %rsi
movq 216(%rsp), %rdi
call _Z48__device_stub__Z17kernelPermutationP7double2S0_iP7double2S0_i
jmp .L80
.L84:
movslq %esi, %rdx
addq %r12, %rdx
salq $4, %rdx
addq %rbx, %rdx
movq (%rcx), %rax
leaq (%r9,%rax), %r10
.L83:
movsd (%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rax)
addq $16, %rdx
addq $8, %rax
cmpq %r10, %rax
jne .L83
.L85:
addl %edi, %esi
addq $8, %rcx
cmpq %r8, %rcx
je .L81
.L82:
cmpl %r13d, %ebp
jge .L84
jmp .L85
.L81:
addl $1, 8(%rsp)
movl 8(%rsp), %eax
cmpl %eax, 72(%rsp)
jle .L123
.L86:
leaq 176(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 128(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 144(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 160(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 136(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 152(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 168(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq 16(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movsd 168(%rsp), %xmm6
movsd 152(%rsp), %xmm5
movsd 136(%rsp), %xmm4
movsd 160(%rsp), %xmm3
movsd 144(%rsp), %xmm2
movsd 128(%rsp), %xmm1
movsd 176(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $7, %eax
call __printf_chk@PLT
movsd 136(%rsp), %xmm5
movapd %xmm5, %xmm2
mulsd 128(%rsp), %xmm2
movsd %xmm2, (%r14)
movsd 152(%rsp), %xmm4
movapd %xmm4, %xmm1
mulsd 144(%rsp), %xmm1
movsd %xmm1, 8(%r14)
movsd 168(%rsp), %xmm3
movapd %xmm3, %xmm0
mulsd 160(%rsp), %xmm0
movsd %xmm0, 16(%r14)
mulsd %xmm5, %xmm2
movsd %xmm2, 24(%r14)
mulsd %xmm4, %xmm1
movsd %xmm1, 32(%r14)
mulsd %xmm3, %xmm0
movsd %xmm0, 40(%r14)
movsd %xmm5, 48(%r14)
movsd %xmm4, 56(%r14)
movsd %xmm3, 64(%r14)
movsd 176(%rsp), %xmm0
movsd %xmm0, 72(%r14)
movl $1, %ecx
movl $104, %edx
movq %r14, %rsi
movq 208(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 232(%rsp)
movl $16, 236(%rsp)
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 244(%rsp), %rdi
movl 252(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L124
.L68:
movl 68(%rsp), %eax
shrl $4, %eax
movl %eax, 268(%rsp)
movl $1, 272(%rsp)
movl $1, 276(%rsp)
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 268(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L125
.L69:
movl 68(%rsp), %eax
shrl $4, %eax
movl %eax, 268(%rsp)
movl $1, 272(%rsp)
movl $1, 276(%rsp)
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 268(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L126
.L70:
movl $1, %ecx
movq 224(%rsp), %rdx
movq 216(%rsp), %rsi
movl 76(%rsp), %edi
call cufftExecZ2Z@PLT
movl 240(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 232(%rsp), %rdx
movq 256(%rsp), %rdi
movl 264(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L127
.L71:
movl 68(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $4, %rdx
movl $2, %ecx
movq 216(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 48(%rsp), %edx
cmpl %r15d, %edx
jl .L72
movl 68(%rsp), %edi
leal -1(%rdi), %esi
subl %r15d, %esi
imull %edi, %esi
movq 32(%rsp), %r11
movq %r11, %rcx
movl %edx, %eax
subl %r15d, %eax
leaq 8(%r11,%rax,8), %r8
movl %ebp, %eax
subl %r13d, %eax
leaq 8(,%rax,8), %r9
jmp .L73
.L123:
movq 40(%rsp), %r15
.L67:
movl 76(%rsp), %edi
call cufftDestroy@PLT
movq 216(%rsp), %rdi
call cudaFree@PLT
movq 224(%rsp), %rdi
call cudaFree@PLT
movl 28(%rsp), %ebx
cmpl %ebx, 48(%rsp)
jl .L87
movq 32(%rsp), %r14
movl %r13d, 40(%rsp)
.L90:
movl 68(%rsp), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC9(%rip), %xmm0
mulsd 88(%rsp), %xmm0
movsd .LC10(%rip), %xmm4
divsd %xmm0, %xmm4
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
negl %eax
movl 28(%rsp), %ebx
leal 1(%rbx,%rax), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm0, %xmm4
movl 40(%rsp), %eax
cmpl %eax, %ebp
jl .L88
movl %eax, %ebx
movl $0, %r12d
leaq .LC14(%rip), %r13
movsd %xmm4, 8(%rsp)
.L89:
movl 68(%rsp), %edx
pxor %xmm3, %xmm3
cvtsi2sdl %edx, %xmm3
movq (%r14), %rax
movsd (%rax,%r12), %xmm2
movapd %xmm3, %xmm0
mulsd .LC9(%rip), %xmm0
mulsd 88(%rsp), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
negl %eax
leal 1(%rbx,%rax), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd %xmm3, %xmm2
mulsd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r15, %rdi
movl $3, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $8, %r12
cmpl %ebx, %ebp
jge .L89
.L88:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 28(%rsp)
movl 28(%rsp), %eax
addq $8, %r14
cmpl %eax, 48(%rsp)
jge .L90
.L87:
cmpl $0, 52(%rsp)
jle .L91
movq 32(%rsp), %rax
movq %rax, %rbx
movq 56(%rsp), %rbp
addq %rax, %rbp
.L92:
movq (%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L92
.L91:
movq 32(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call fclose@PLT
movq 16(%rsp), %rdi
call fclose@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L128
movl $0, %eax
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq $0
.cfi_def_cfa_offset 360
pushq $0
.cfi_def_cfa_offset 368
movl $0, %ebp
movl %ebp, %r9d
movl $0, %r13d
movl %r13d, %r8d
movl $0, %ecx
movl %ecx, 64(%rsp)
movl $0, %edx
movl %edx, 44(%rsp)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call malloc@PLT
movq %rax, 48(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 352
movl $0, 52(%rsp)
movq $0, 56(%rsp)
jmp .L63
.L128:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "_Z18kernelNonRephasingP7double2ddiPd"
.align 8
.LC17:
.string "_Z15kernelRephasingP7double2ddiPd"
.align 8
.LC18:
.string "_Z17kernelPermutationP7double2S0_i"
.align 8
.LC19:
.string "_Z16kernelHalfFirstYP7double2i"
.section .rodata.str1.1
.LC20:
.string "_Z16kernelHalfFirstXP7double2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2122:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernelNonRephasingP7double2ddiPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernelRephasingP7double2ddiPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernelPermutationP7double2S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernelHalfFirstYP7double2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernelHalfFirstXP7double2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2122:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 1241513984
.long 1102175864
.align 8
.LC10:
.long 536870912
.long 1107468383
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifdef USE_DOUBLE
#define real_t double
#define fftComplex_t cufftDoubleComplex
#define complex_t cuDoubleComplex
#else
#define real_t double
#define fftComplex_t cufftDoubleComplex
#define complex_t cuDoubleComplex
#endif
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include <cuComplex.h>
#define nThrdsX 16
#define nThrdsY 16
#define nThrds 256
#define clight 299792458
#define PI 3.14159265358979323846
#define cmtops (2*PI*clight*1.e-10)
__device__ __forceinline__ cuDoubleComplex my_cexpc (cuDoubleComplex z)
{
cuDoubleComplex res;
double t = exp(z.x);
res.x=cos(z.y);
res.y=sin(z.y);
res.x *= t;
res.y *= t;
return res;
}
__device__ __forceinline__ cuDoubleComplex my_cexpf (double z)
{
cuDoubleComplex res;
res.x=exp(z);
res.y=0.0;
return res;
}
__device__ __forceinline__ cuDoubleComplex my_cexpi (double z)
{
cuDoubleComplex res;
res.x=cos(z);
res.y=sin(z);
return res;
}
__device__ double g(double t, double *d_param)
{
double f1,f2,f3,f4;
f1=d_param[3]*exp(-t/d_param[6]);
f2=d_param[4]*exp(-t/d_param[7]);
f3=d_param[5]*exp(-t/d_param[8]);
f4=(d_param[0]+d_param[1]+d_param[2])*t-(d_param[3]+d_param[4]+d_param[5]);
return ( f1 + f2 + f3 + f4 );
}
__device__ cuDoubleComplex Rr(double t1 ,double t2, double t3, double *d_param)
{
cuDoubleComplex f1;
cuDoubleComplex f2;
f1 = my_cexpi( -( t3 - t1 ) * d_param[9] * cmtops );
f1 = cuCsub(f1 , cuCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 - ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = cuCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf(-g(t1,d_param) + g(t2,d_param) - g(t3,d_param) - g(t1+t2,d_param) - g(t2+t3,d_param) + g(t1+t2+t3,d_param) );
return cuCmul( f1 , f2 );
}
__device__ cuDoubleComplex Rnr(double t1 ,double t2, double t3, double *d_param)
{
cuDoubleComplex f1;
cuDoubleComplex f2;
f1 = my_cexpi( -( t3 + t1 ) * d_param[9] * cmtops );
f1 = cuCsub(f1 , cuCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 + ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = cuCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf( -g(t1,d_param) - g(t2,d_param) - g(t3,d_param) + g(t1+t2,d_param) + g(t2+t3,d_param) - g(t1+t2+t3,d_param) );
return cuCmul( f1 , f2 );
}
__global__ void kernelHalfFirstX(cufftDoubleComplex *d_r)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
cuDoubleComplex half;
half.x=0.5;
half.y=0.0;
d_r[i]=cuCmul(d_r[i],half);
}
__global__ void kernelHalfFirstY(cufftDoubleComplex *d_r, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = i*n;
cuDoubleComplex half;
half.x=0.5;
half.y=0.0;
if (j>0)
d_r[j]=cuCmul(d_r[j],half);
}
__global__ void kernelPermutation(cufftDoubleComplex *d_r,cufftDoubleComplex *d_ftr, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
int l = i * n + j + n/2 ;
int m = ( i + n/2 ) * n + j;
int p = ( i + n/2 ) * n + j + n/2;
d_r[m]=d_ftr[l];
d_r[p]=d_ftr[k];
d_r[l]=d_ftr[m];
d_r[k]=d_ftr[p];
}
__global__ void kernelRephasing(cufftDoubleComplex *d_r,double dt,double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rr(t1,t2,t3,d_param);
}
__global__ void kernelNonRephasing(cufftDoubleComplex *d_r, double dt, double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k= i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rnr(t1,t2,t3,d_param);
}
int main(int argc, char* argv[])
{
FILE* input=fopen(argv[1],"r");
FILE* out=fopen("spec.dat","w");
int i,ii,j,l,test;
int iw1,iw3,iFirst,iLast,jFirst,jLast;
int ndata,nw1,nw3,nave;
double t2,dt;
double w1min,w1max,w3min,w3max;
double w1,w3;
double **res;
double c1,tau1,c2,tau2,c3,tau3,wm,delta,tLife,alpha;
fscanf(input,"%lf %lf %lf %lf",&w1min,&w1max,&w3min,&w3max);
fscanf(input,"%lf %lf %lf",&delta,&tLife,&alpha);
fscanf(input,"%d %lf",&ndata,&dt);
fscanf(input,"%lf",&t2);
fscanf(input,"%d",&nave);
ndata=(int)(ndata/nThrds)+1;
ndata=nThrds*2*(int)(ndata/2);
printf("%d %d\n",ndata,nThrds);
nw1=0;
test=1;
for(i=ndata/2-1;i<ndata-1;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
if(w1>w1max)
{
iLast=i-1;
break;
}
if( w1>=w1min )
{
nw1++;
if(test)
{
test=0;
iFirst=i;
}
}
}
nw3=0;
test=1;
for(j=ndata/2-1;j<ndata-1;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
if(w3>w3max)
{
jLast=j-1;
break;
}
if( w3>=w3min )
{
nw3++;
if(test)
{
test=0;
jFirst=j;
}
}
}
printf("%d %d %d %d %d %d\n",iFirst,iLast,jFirst,jLast,nw1,nw3);
res=(double**)malloc(nw1*sizeof(double*));
for(i=0;i<nw1;i++)
{
res[i]=(double*)malloc(nw3*sizeof(double));
for(j=0;j<nw3;j++)
res[i][j]=0.0;
}
double *param,*d_param;
param=(double*)malloc(13*sizeof(double));
cudaMalloc((void**) &d_param,13*sizeof(double));
param[10]=delta;
param[11]=tLife;
param[12]=alpha;
cufftDoubleComplex *d_rlist,*d_ftrlist,*rlist;
cufftHandle d_pr;
rlist=(cufftDoubleComplex*)malloc(ndata*ndata*sizeof(cufftDoubleComplex));
cudaMalloc((void**) &d_rlist,ndata*ndata*sizeof(cufftDoubleComplex));
cudaMalloc((void**) &d_ftrlist,ndata*ndata*sizeof(cufftDoubleComplex));
cufftPlan2d(&d_pr,ndata,ndata,CUFFT_Z2Z);
dim3 threadsPerBlock(nThrdsX, nThrdsY);
dim3 numBlocks(ndata / threadsPerBlock.x, ndata / threadsPerBlock.y);
dim3 numHalfBlocks( (ndata/2) / threadsPerBlock.x, (ndata/2) / threadsPerBlock.y );
for(ii=0;ii<nave;ii++)
{
fscanf(input,"%lf",&wm);
fscanf(input,"%lf",&c1);
fscanf(input,"%lf",&c2);
fscanf(input,"%lf",&c3);
fscanf(input,"%lf",&tau1);
fscanf(input,"%lf",&tau2);
fscanf(input,"%lf",&tau3);
printf("%lf %lf %lf %lf %lf %lf %lf\n",wm,c1,c2,c3,tau1,tau2,tau3);
param[0]=c1*tau1;
param[1]=c2*tau2;
param[2]=c3*tau3;
param[3]=param[0]*tau1;
param[4]=param[1]*tau2;
param[5]=param[2]*tau3;
param[6]=tau1;
param[7]=tau2;
param[8]=tau3;
param[9]=wm;
cudaMemcpy(d_param,param,13*sizeof(double),cudaMemcpyHostToDevice);
// Rephasing component
kernelRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
cufftExecZ2Z(d_pr,d_rlist,d_ftrlist,CUFFT_INVERSE);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
cudaMemcpy(rlist,d_rlist,ndata*ndata*sizeof(cufftDoubleComplex),cudaMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(ndata-i-1)+j+1;
res[iw1][iw3]+=cuCreal(rlist[l]);
iw3++;
}
iw1++;
}
// Non-rephasing component
kernelNonRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
cufftExecZ2Z(d_pr,d_rlist,d_ftrlist,CUFFT_INVERSE);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
cudaMemcpy(rlist,d_rlist,ndata*ndata*sizeof(cufftDoubleComplex),cudaMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(i+1)+j+1;
res[iw1][iw3]+=cuCreal(rlist[l]);
iw3++;
}
iw1++;
}
}
cufftDestroy(d_pr);
cudaFree(d_rlist);
cudaFree(d_ftrlist);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
fprintf(out,"%lf\t%lf\t%le\n",w1,w3,res[iw1][iw3]/(double)ndata);
iw3++;
}
fprintf(out,"\n");
iw1++;
}
for(i=0;i<nw1;i++)
free(res[i]);
free(res);
fclose(out);
fclose(input);
return 0;
} | #ifdef USE_DOUBLE
#define real_t double
#define fftComplex_t hipfftDoubleComplex
#define complex_t hipDoubleComplex
#else
#define real_t double
#define fftComplex_t hipfftDoubleComplex
#define complex_t hipDoubleComplex
#endif
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_complex.h>
#define nThrdsX 16
#define nThrdsY 16
#define nThrds 256
#define clight 299792458
#define PI 3.14159265358979323846
#define cmtops (2*PI*clight*1.e-10)
__device__ __forceinline__ hipDoubleComplex my_cexpc (hipDoubleComplex z)
{
hipDoubleComplex res;
double t = exp(z.x);
res.x=cos(z.y);
res.y=sin(z.y);
res.x *= t;
res.y *= t;
return res;
}
__device__ __forceinline__ hipDoubleComplex my_cexpf (double z)
{
hipDoubleComplex res;
res.x=exp(z);
res.y=0.0;
return res;
}
__device__ __forceinline__ hipDoubleComplex my_cexpi (double z)
{
hipDoubleComplex res;
res.x=cos(z);
res.y=sin(z);
return res;
}
__device__ double g(double t, double *d_param)
{
double f1,f2,f3,f4;
f1=d_param[3]*exp(-t/d_param[6]);
f2=d_param[4]*exp(-t/d_param[7]);
f3=d_param[5]*exp(-t/d_param[8]);
f4=(d_param[0]+d_param[1]+d_param[2])*t-(d_param[3]+d_param[4]+d_param[5]);
return ( f1 + f2 + f3 + f4 );
}
__device__ hipDoubleComplex Rr(double t1 ,double t2, double t3, double *d_param)
{
hipDoubleComplex f1;
hipDoubleComplex f2;
f1 = my_cexpi( -( t3 - t1 ) * d_param[9] * cmtops );
f1 = hipCsub(f1 , hipCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 - ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = hipCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf(-g(t1,d_param) + g(t2,d_param) - g(t3,d_param) - g(t1+t2,d_param) - g(t2+t3,d_param) + g(t1+t2+t3,d_param) );
return hipCmul( f1 , f2 );
}
__device__ hipDoubleComplex Rnr(double t1 ,double t2, double t3, double *d_param)
{
hipDoubleComplex f1;
hipDoubleComplex f2;
f1 = my_cexpi( -( t3 + t1 ) * d_param[9] * cmtops );
f1 = hipCsub(f1 , hipCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 + ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = hipCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf( -g(t1,d_param) - g(t2,d_param) - g(t3,d_param) + g(t1+t2,d_param) + g(t2+t3,d_param) - g(t1+t2+t3,d_param) );
return hipCmul( f1 , f2 );
}
__global__ void kernelHalfFirstX(hipfftDoubleComplex *d_r)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
hipDoubleComplex half;
half.x=0.5;
half.y=0.0;
d_r[i]=hipCmul(d_r[i],half);
}
__global__ void kernelHalfFirstY(hipfftDoubleComplex *d_r, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = i*n;
hipDoubleComplex half;
half.x=0.5;
half.y=0.0;
if (j>0)
d_r[j]=hipCmul(d_r[j],half);
}
__global__ void kernelPermutation(hipfftDoubleComplex *d_r,hipfftDoubleComplex *d_ftr, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
int l = i * n + j + n/2 ;
int m = ( i + n/2 ) * n + j;
int p = ( i + n/2 ) * n + j + n/2;
d_r[m]=d_ftr[l];
d_r[p]=d_ftr[k];
d_r[l]=d_ftr[m];
d_r[k]=d_ftr[p];
}
__global__ void kernelRephasing(hipfftDoubleComplex *d_r,double dt,double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rr(t1,t2,t3,d_param);
}
__global__ void kernelNonRephasing(hipfftDoubleComplex *d_r, double dt, double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k= i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rnr(t1,t2,t3,d_param);
}
int main(int argc, char* argv[])
{
FILE* input=fopen(argv[1],"r");
FILE* out=fopen("spec.dat","w");
int i,ii,j,l,test;
int iw1,iw3,iFirst,iLast,jFirst,jLast;
int ndata,nw1,nw3,nave;
double t2,dt;
double w1min,w1max,w3min,w3max;
double w1,w3;
double **res;
double c1,tau1,c2,tau2,c3,tau3,wm,delta,tLife,alpha;
fscanf(input,"%lf %lf %lf %lf",&w1min,&w1max,&w3min,&w3max);
fscanf(input,"%lf %lf %lf",&delta,&tLife,&alpha);
fscanf(input,"%d %lf",&ndata,&dt);
fscanf(input,"%lf",&t2);
fscanf(input,"%d",&nave);
ndata=(int)(ndata/nThrds)+1;
ndata=nThrds*2*(int)(ndata/2);
printf("%d %d\n",ndata,nThrds);
nw1=0;
test=1;
for(i=ndata/2-1;i<ndata-1;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
if(w1>w1max)
{
iLast=i-1;
break;
}
if( w1>=w1min )
{
nw1++;
if(test)
{
test=0;
iFirst=i;
}
}
}
nw3=0;
test=1;
for(j=ndata/2-1;j<ndata-1;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
if(w3>w3max)
{
jLast=j-1;
break;
}
if( w3>=w3min )
{
nw3++;
if(test)
{
test=0;
jFirst=j;
}
}
}
printf("%d %d %d %d %d %d\n",iFirst,iLast,jFirst,jLast,nw1,nw3);
res=(double**)malloc(nw1*sizeof(double*));
for(i=0;i<nw1;i++)
{
res[i]=(double*)malloc(nw3*sizeof(double));
for(j=0;j<nw3;j++)
res[i][j]=0.0;
}
double *param,*d_param;
param=(double*)malloc(13*sizeof(double));
hipMalloc((void**) &d_param,13*sizeof(double));
param[10]=delta;
param[11]=tLife;
param[12]=alpha;
hipfftDoubleComplex *d_rlist,*d_ftrlist,*rlist;
hipfftHandle d_pr;
rlist=(hipfftDoubleComplex*)malloc(ndata*ndata*sizeof(hipfftDoubleComplex));
hipMalloc((void**) &d_rlist,ndata*ndata*sizeof(hipfftDoubleComplex));
hipMalloc((void**) &d_ftrlist,ndata*ndata*sizeof(hipfftDoubleComplex));
hipfftPlan2d(&d_pr,ndata,ndata,HIPFFT_Z2Z);
dim3 threadsPerBlock(nThrdsX, nThrdsY);
dim3 numBlocks(ndata / threadsPerBlock.x, ndata / threadsPerBlock.y);
dim3 numHalfBlocks( (ndata/2) / threadsPerBlock.x, (ndata/2) / threadsPerBlock.y );
for(ii=0;ii<nave;ii++)
{
fscanf(input,"%lf",&wm);
fscanf(input,"%lf",&c1);
fscanf(input,"%lf",&c2);
fscanf(input,"%lf",&c3);
fscanf(input,"%lf",&tau1);
fscanf(input,"%lf",&tau2);
fscanf(input,"%lf",&tau3);
printf("%lf %lf %lf %lf %lf %lf %lf\n",wm,c1,c2,c3,tau1,tau2,tau3);
param[0]=c1*tau1;
param[1]=c2*tau2;
param[2]=c3*tau3;
param[3]=param[0]*tau1;
param[4]=param[1]*tau2;
param[5]=param[2]*tau3;
param[6]=tau1;
param[7]=tau2;
param[8]=tau3;
param[9]=wm;
hipMemcpy(d_param,param,13*sizeof(double),hipMemcpyHostToDevice);
// Rephasing component
kernelRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
hipfftExecZ2Z(d_pr,d_rlist,d_ftrlist,HIPFFT_BACKWARD);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
hipMemcpy(rlist,d_rlist,ndata*ndata*sizeof(hipfftDoubleComplex),hipMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(ndata-i-1)+j+1;
res[iw1][iw3]+=hipCreal(rlist[l]);
iw3++;
}
iw1++;
}
// Non-rephasing component
kernelNonRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
hipfftExecZ2Z(d_pr,d_rlist,d_ftrlist,HIPFFT_BACKWARD);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
hipMemcpy(rlist,d_rlist,ndata*ndata*sizeof(hipfftDoubleComplex),hipMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(i+1)+j+1;
res[iw1][iw3]+=hipCreal(rlist[l]);
iw3++;
}
iw1++;
}
}
hipfftDestroy(d_pr);
hipFree(d_rlist);
hipFree(d_ftrlist);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
fprintf(out,"%lf\t%lf\t%le\n",w1,w3,res[iw1][iw3]/(double)ndata);
iw3++;
}
fprintf(out,"\n");
iw1++;
}
for(i=0;i<nw1;i++)
free(res[i]);
free(res);
fclose(out);
fclose(input);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifdef USE_DOUBLE
#define real_t double
#define fftComplex_t hipfftDoubleComplex
#define complex_t hipDoubleComplex
#else
#define real_t double
#define fftComplex_t hipfftDoubleComplex
#define complex_t hipDoubleComplex
#endif
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_complex.h>
#define nThrdsX 16
#define nThrdsY 16
#define nThrds 256
#define clight 299792458
#define PI 3.14159265358979323846
#define cmtops (2*PI*clight*1.e-10)
__device__ __forceinline__ hipDoubleComplex my_cexpc (hipDoubleComplex z)
{
hipDoubleComplex res;
double t = exp(z.x);
res.x=cos(z.y);
res.y=sin(z.y);
res.x *= t;
res.y *= t;
return res;
}
__device__ __forceinline__ hipDoubleComplex my_cexpf (double z)
{
hipDoubleComplex res;
res.x=exp(z);
res.y=0.0;
return res;
}
__device__ __forceinline__ hipDoubleComplex my_cexpi (double z)
{
hipDoubleComplex res;
res.x=cos(z);
res.y=sin(z);
return res;
}
__device__ double g(double t, double *d_param)
{
double f1,f2,f3,f4;
f1=d_param[3]*exp(-t/d_param[6]);
f2=d_param[4]*exp(-t/d_param[7]);
f3=d_param[5]*exp(-t/d_param[8]);
f4=(d_param[0]+d_param[1]+d_param[2])*t-(d_param[3]+d_param[4]+d_param[5]);
return ( f1 + f2 + f3 + f4 );
}
__device__ hipDoubleComplex Rr(double t1 ,double t2, double t3, double *d_param)
{
hipDoubleComplex f1;
hipDoubleComplex f2;
f1 = my_cexpi( -( t3 - t1 ) * d_param[9] * cmtops );
f1 = hipCsub(f1 , hipCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 - ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = hipCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf(-g(t1,d_param) + g(t2,d_param) - g(t3,d_param) - g(t1+t2,d_param) - g(t2+t3,d_param) + g(t1+t2+t3,d_param) );
return hipCmul( f1 , f2 );
}
__device__ hipDoubleComplex Rnr(double t1 ,double t2, double t3, double *d_param)
{
hipDoubleComplex f1;
hipDoubleComplex f2;
f1 = my_cexpi( -( t3 + t1 ) * d_param[9] * cmtops );
f1 = hipCsub(f1 , hipCmul( my_cexpi( -cmtops * ( ( d_param[9] - d_param[10] ) * t3 + ( d_param[9] * t1 ) ) ) , my_cexpf( -(d_param[12]*t3)/(2.*d_param[11]) ) ) );
f1 = hipCmul(f1 , my_cexpf( -( t1 + t3 + (2.*t2) ) / ( 2.*d_param[11] ) ) );
f2 = my_cexpf( -g(t1,d_param) - g(t2,d_param) - g(t3,d_param) + g(t1+t2,d_param) + g(t2+t3,d_param) - g(t1+t2+t3,d_param) );
return hipCmul( f1 , f2 );
}
__global__ void kernelHalfFirstX(hipfftDoubleComplex *d_r)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
hipDoubleComplex half;
half.x=0.5;
half.y=0.0;
d_r[i]=hipCmul(d_r[i],half);
}
__global__ void kernelHalfFirstY(hipfftDoubleComplex *d_r, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = i*n;
hipDoubleComplex half;
half.x=0.5;
half.y=0.0;
if (j>0)
d_r[j]=hipCmul(d_r[j],half);
}
__global__ void kernelPermutation(hipfftDoubleComplex *d_r,hipfftDoubleComplex *d_ftr, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
int l = i * n + j + n/2 ;
int m = ( i + n/2 ) * n + j;
int p = ( i + n/2 ) * n + j + n/2;
d_r[m]=d_ftr[l];
d_r[p]=d_ftr[k];
d_r[l]=d_ftr[m];
d_r[k]=d_ftr[p];
}
__global__ void kernelRephasing(hipfftDoubleComplex *d_r,double dt,double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rr(t1,t2,t3,d_param);
}
__global__ void kernelNonRephasing(hipfftDoubleComplex *d_r, double dt, double t2,int n,double *d_param)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k= i * n + j;
double t1 = i * dt;
double t3 = j * dt;
d_r[k]=Rnr(t1,t2,t3,d_param);
}
int main(int argc, char* argv[])
{
FILE* input=fopen(argv[1],"r");
FILE* out=fopen("spec.dat","w");
int i,ii,j,l,test;
int iw1,iw3,iFirst,iLast,jFirst,jLast;
int ndata,nw1,nw3,nave;
double t2,dt;
double w1min,w1max,w3min,w3max;
double w1,w3;
double **res;
double c1,tau1,c2,tau2,c3,tau3,wm,delta,tLife,alpha;
fscanf(input,"%lf %lf %lf %lf",&w1min,&w1max,&w3min,&w3max);
fscanf(input,"%lf %lf %lf",&delta,&tLife,&alpha);
fscanf(input,"%d %lf",&ndata,&dt);
fscanf(input,"%lf",&t2);
fscanf(input,"%d",&nave);
ndata=(int)(ndata/nThrds)+1;
ndata=nThrds*2*(int)(ndata/2);
printf("%d %d\n",ndata,nThrds);
nw1=0;
test=1;
for(i=ndata/2-1;i<ndata-1;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
if(w1>w1max)
{
iLast=i-1;
break;
}
if( w1>=w1min )
{
nw1++;
if(test)
{
test=0;
iFirst=i;
}
}
}
nw3=0;
test=1;
for(j=ndata/2-1;j<ndata-1;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
if(w3>w3max)
{
jLast=j-1;
break;
}
if( w3>=w3min )
{
nw3++;
if(test)
{
test=0;
jFirst=j;
}
}
}
printf("%d %d %d %d %d %d\n",iFirst,iLast,jFirst,jLast,nw1,nw3);
res=(double**)malloc(nw1*sizeof(double*));
for(i=0;i<nw1;i++)
{
res[i]=(double*)malloc(nw3*sizeof(double));
for(j=0;j<nw3;j++)
res[i][j]=0.0;
}
double *param,*d_param;
param=(double*)malloc(13*sizeof(double));
hipMalloc((void**) &d_param,13*sizeof(double));
param[10]=delta;
param[11]=tLife;
param[12]=alpha;
hipfftDoubleComplex *d_rlist,*d_ftrlist,*rlist;
hipfftHandle d_pr;
rlist=(hipfftDoubleComplex*)malloc(ndata*ndata*sizeof(hipfftDoubleComplex));
hipMalloc((void**) &d_rlist,ndata*ndata*sizeof(hipfftDoubleComplex));
hipMalloc((void**) &d_ftrlist,ndata*ndata*sizeof(hipfftDoubleComplex));
hipfftPlan2d(&d_pr,ndata,ndata,HIPFFT_Z2Z);
dim3 threadsPerBlock(nThrdsX, nThrdsY);
dim3 numBlocks(ndata / threadsPerBlock.x, ndata / threadsPerBlock.y);
dim3 numHalfBlocks( (ndata/2) / threadsPerBlock.x, (ndata/2) / threadsPerBlock.y );
for(ii=0;ii<nave;ii++)
{
fscanf(input,"%lf",&wm);
fscanf(input,"%lf",&c1);
fscanf(input,"%lf",&c2);
fscanf(input,"%lf",&c3);
fscanf(input,"%lf",&tau1);
fscanf(input,"%lf",&tau2);
fscanf(input,"%lf",&tau3);
printf("%lf %lf %lf %lf %lf %lf %lf\n",wm,c1,c2,c3,tau1,tau2,tau3);
param[0]=c1*tau1;
param[1]=c2*tau2;
param[2]=c3*tau3;
param[3]=param[0]*tau1;
param[4]=param[1]*tau2;
param[5]=param[2]*tau3;
param[6]=tau1;
param[7]=tau2;
param[8]=tau3;
param[9]=wm;
hipMemcpy(d_param,param,13*sizeof(double),hipMemcpyHostToDevice);
// Rephasing component
kernelRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
hipfftExecZ2Z(d_pr,d_rlist,d_ftrlist,HIPFFT_BACKWARD);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
hipMemcpy(rlist,d_rlist,ndata*ndata*sizeof(hipfftDoubleComplex),hipMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(ndata-i-1)+j+1;
res[iw1][iw3]+=hipCreal(rlist[l]);
iw3++;
}
iw1++;
}
// Non-rephasing component
kernelNonRephasing<<<numBlocks,threadsPerBlock>>>(d_rlist,dt,t2,ndata,d_param);
kernelHalfFirstX<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist);
kernelHalfFirstY<<<(ndata / threadsPerBlock.x),threadsPerBlock>>>(d_rlist,ndata);
hipfftExecZ2Z(d_pr,d_rlist,d_ftrlist,HIPFFT_BACKWARD);
kernelPermutation<<<numHalfBlocks,threadsPerBlock>>>(d_rlist,d_ftrlist,ndata);
hipMemcpy(rlist,d_rlist,ndata*ndata*sizeof(hipfftDoubleComplex),hipMemcpyDeviceToHost);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
l=ndata*(i+1)+j+1;
res[iw1][iw3]+=hipCreal(rlist[l]);
iw3++;
}
iw1++;
}
}
hipfftDestroy(d_pr);
hipFree(d_rlist);
hipFree(d_ftrlist);
iw1=0;
for(i=iFirst;i<=iLast;i++)
{
w1=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+i);
iw3=0;
for(j=jFirst;j<=jLast;j++)
{
w3=1.e10/((double)ndata*clight*dt)*(double)(1-ndata/2+j);
fprintf(out,"%lf\t%lf\t%le\n",w1,w3,res[iw1][iw3]/(double)ndata);
iw3++;
}
fprintf(out,"\n");
iw1++;
}
for(i=0;i<nw1;i++)
free(res[i]);
free(res);
fclose(out);
fclose(input);
return 0;
} | .text
.file "irspec_double.hip"
.globl _Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE # -- Begin function _Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.p2align 4, 0x90
.type _Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE,@function
_Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE: # @_Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE, .Lfunc_end0-_Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.cfi_endproc
# -- End function
.globl _Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi # -- Begin function _Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.p2align 4, 0x90
.type _Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi,@function
_Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi: # @_Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi, .Lfunc_end1-_Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i # -- Begin function _Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.p2align 4, 0x90
.type _Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i,@function
_Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i: # @_Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i, .Lfunc_end2-_Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd # -- Begin function _Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.p2align 4, 0x90
.type _Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd,@function
_Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd: # @_Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd, .Lfunc_end3-_Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.cfi_endproc
# -- End function
.globl _Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd # -- Begin function _Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.p2align 4, 0x90
.type _Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd,@function
_Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd: # @_Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end4:
.size _Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd, .Lfunc_end4-_Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x41b1de784a000000 # double 299792458
.LCPI5_1:
.quad 0x4202a05f20000000 # double 1.0E+10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, 360(%rsp) # 8-byte Spill
xorl %r14d, %r14d
leaq 432(%rsp), %rdx
leaq 424(%rsp), %rcx
leaq 416(%rsp), %r8
leaq 408(%rsp), %r9
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 400(%rsp), %rdx
leaq 392(%rsp), %rcx
leaq 384(%rsp), %r8
movl $.L.str.4, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 8(%rsp), %rdx
leaq 120(%rsp), %rcx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 352(%rsp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 212(%rsp), %rdx
movl $.L.str.7, %esi
movq %rbx, 264(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
movl %ecx, %eax
incl %eax
shrl $31, %eax
leal (%rcx,%rax), %esi
incl %esi
andl $-2, %esi
shll $8, %esi
movl %esi, 8(%rsp)
movl $.L.str.8, %edi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
movl %eax, %ebp
shrl $31, %ebp
addl %eax, %ebp
sarl %ebp
leal -1(%rbp), %edx
movl $0, %r15d
# implicit-def: $ecx
# kill: killed $ecx
# implicit-def: $esi
movq %rsi, 96(%rsp) # 8-byte Spill
cmpl %eax, %ebp
jge .LBB5_6
# %bb.1: # %.lr.ph
cvtsi2sd %eax, %xmm1
mulsd .LCPI5_0(%rip), %xmm1
mulsd 120(%rsp), %xmm1
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd 424(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 432(%rsp), %xmm2 # xmm2 = mem[0],zero
movl %ebp, %esi
negl %esi
movl %eax, %edi
negl %edi
movl %ebp, %r8d
subl %ebp, %r8d
xorl %r9d, %r9d
movl $1, %r11d
movl %edx, %r10d
# implicit-def: $ecx
# kill: killed $ecx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2sd %r8d, %xmm3
mulsd %xmm0, %xmm3
ucomisd %xmm1, %xmm3
ja .LBB5_5
# %bb.3: # in Loop: Header=BB5_2 Depth=1
ucomisd %xmm2, %xmm3
sbbl $-1, %r15d
ucomisd %xmm2, %xmm3
movl %r11d, %ebx
cmovael %r9d, %ebx
testl %r11d, %r11d
movl %r10d, %r11d
movl 12(%rsp), %ecx # 4-byte Reload
cmovel %ecx, %r11d
ucomisd %xmm2, %xmm3
cmovael %r11d, %ecx
movl %ecx, 12(%rsp) # 4-byte Spill
incl %r10d
decl %esi
incl %r8d
movl %ebx, %r11d
# implicit-def: $ebx
movq %rbx, 96(%rsp) # 8-byte Spill
cmpl %esi, %edi
jne .LBB5_2
.LBB5_6:
# implicit-def: $ecx
# implicit-def: $ebx
cmpl %eax, %ebp
jge .LBB5_11
.LBB5_7: # %.lr.ph347
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd .LCPI5_0(%rip), %xmm1
mulsd 120(%rsp), %xmm1
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd 408(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 416(%rsp), %xmm2 # xmm2 = mem[0],zero
movl %ebp, %esi
negl %esi
negl %eax
subl %ebp, %ebp
xorl %edi, %edi
movl $1, %r8d
# implicit-def: $ecx
xorl %r14d, %r14d
# implicit-def: $ebx
.p2align 4, 0x90
.LBB5_8: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2sd %ebp, %xmm3
mulsd %xmm0, %xmm3
ucomisd %xmm1, %xmm3
ja .LBB5_10
# %bb.9: # in Loop: Header=BB5_8 Depth=1
ucomisd %xmm2, %xmm3
sbbl $-1, %r14d
ucomisd %xmm2, %xmm3
movl %r8d, %r9d
cmovael %edi, %r9d
testl %r8d, %r8d
movl %edx, %r8d
cmovel %ecx, %r8d
ucomisd %xmm2, %xmm3
cmovael %r8d, %ecx
incl %edx
decl %esi
incl %ebp
movl %r9d, %r8d
cmpl %esi, %eax
jne .LBB5_8
jmp .LBB5_11
.LBB5_5:
movl $-2, %edi
subl %esi, %edi
movq %rdi, 96(%rsp) # 8-byte Spill
# implicit-def: $ecx
# implicit-def: $ebx
cmpl %eax, %ebp
jge .LBB5_11
jmp .LBB5_7
.LBB5_10:
movl $-2, %ebx
subl %esi, %ebx
.LBB5_11: # %.loopexit
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.9, %edi
movl 20(%rsp), %esi # 4-byte Reload
movq 104(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movq %rcx, 184(%rsp) # 8-byte Spill
# kill: def $ecx killed $ecx killed $rcx
movl %ebx, %r8d
movl %r15d, %r9d
xorl %eax, %eax
pushq %r14
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl %r15d, %eax
movq %rax, 256(%rsp) # 8-byte Spill
leaq (,%rax,8), %rdi
callq malloc
movq %rax, 184(%rsp) # 8-byte Spill
movl %r15d, 244(%rsp) # 4-byte Spill
testl %r15d, %r15d
movl %ebx, %ebp
je .LBB5_16
# %bb.12: # %.lr.ph354
movl %r14d, %ebx
shlq $3, %rbx
xorl %r15d, %r15d
jmp .LBB5_14
.p2align 4, 0x90
.LBB5_13: # %._crit_edge
# in Loop: Header=BB5_14 Depth=1
incq %r15
cmpq %r15, 256(%rsp) # 8-byte Folded Reload
je .LBB5_16
.LBB5_14: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq malloc
movq 184(%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx,%r15,8)
testl %r14d, %r14d
je .LBB5_13
# %bb.15: # %.lr.ph351.preheader
# in Loop: Header=BB5_14 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
jmp .LBB5_13
.LBB5_16: # %._crit_edge355
movl $104, %edi
callq malloc
movq %rax, %rbx
leaq 224(%rsp), %rdi
movl $104, %esi
callq hipMalloc
movsd 400(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 80(%rbx)
movsd 392(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 88(%rbx)
movsd 384(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 96(%rbx)
movl 8(%rsp), %r15d
imull %r15d, %r15d
shlq $4, %r15
movq %r15, %rdi
callq malloc
movq %rax, 192(%rsp) # 8-byte Spill
leaq 80(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl 8(%rsp), %esi
imull %esi, %esi
shlq $4, %rsi
leaq 200(%rsp), %rdi
callq hipMalloc
movl 8(%rsp), %edx
leaq 216(%rsp), %rdi
movl %edx, %esi
movl $105, %ecx
callq hipfftPlan2d
cmpl $0, 212(%rsp)
jle .LBB5_47
# %bb.17: # %.lr.ph378
movabsq $4294967296, %rsi # imm = 0x100000000
movl 8(%rsp), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
movl %eax, %edx
shrl $4, %edx
leaq 1(%rsi), %rax
imulq %rax, %rdx
movq %rdx, 280(%rsp) # 8-byte Spill
sarl %ecx
shrl $4, %ecx
imulq %rax, %rcx
movq %rcx, 288(%rsp) # 8-byte Spill
movq 176(%rsp), %rcx # 8-byte Reload
movslq %ecx, %rax
movl %ebp, %r15d
subl %ecx, %r15d
incl %r15d
movl 12(%rsp), %edx # 4-byte Reload
movslq %edx, %rsi
movq 96(%rsp), %r14 # 8-byte Reload
# kill: def $r14d killed $r14d killed $r14 def $r14
subl %edx, %r14d
incl %r14d
shlq $4, %rax
movq 192(%rsp), %rcx # 8-byte Reload
leaq (%rax,%rcx), %r11
addq $16, %r11
movl %edx, %eax
notl %eax
movq %rax, 368(%rsp) # 8-byte Spill
shlq $4, %rsi
addq $16, %rsi
movq %rsi, 376(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %r11, 272(%rsp) # 8-byte Spill
movabsq $68719476752, %r12 # imm = 0x1000000010
jmp .LBB5_19
.p2align 4, 0x90
.LBB5_18: # %._crit_edge375
# in Loop: Header=BB5_19 Depth=1
movl 252(%rsp), %eax # 4-byte Reload
incl %eax
cmpl 212(%rsp), %eax
jge .LBB5_47
.LBB5_19: # =>This Loop Header: Depth=1
# Child Loop BB5_44 Depth 2
# Child Loop BB5_46 Depth 3
# Child Loop BB5_39 Depth 2
# Child Loop BB5_41 Depth 3
movl %eax, 252(%rsp) # 4-byte Spill
movl $.L.str.6, %esi
movq 264(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
leaq 296(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 344(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 328(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 312(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 336(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 320(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 304(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movsd 296(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd 344(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 328(%rsp), %xmm2 # xmm2 = mem[0],zero
movsd 312(%rsp), %xmm3 # xmm3 = mem[0],zero
movsd 336(%rsp), %xmm4 # xmm4 = mem[0],zero
movsd 320(%rsp), %xmm5 # xmm5 = mem[0],zero
movsd 304(%rsp), %xmm6 # xmm6 = mem[0],zero
movl $.L.str.10, %edi
movb $7, %al
callq printf
movsd 336(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd 344(%rsp), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm1, (%rbx)
movsd 320(%rsp), %xmm2 # xmm2 = mem[0],zero
movsd 328(%rsp), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm2, %xmm3
movsd %xmm3, 8(%rbx)
movsd 304(%rsp), %xmm4 # xmm4 = mem[0],zero
movsd 312(%rsp), %xmm5 # xmm5 = mem[0],zero
mulsd %xmm4, %xmm5
movsd %xmm5, 16(%rbx)
mulsd %xmm0, %xmm1
movsd %xmm1, 24(%rbx)
mulsd %xmm2, %xmm3
movsd %xmm3, 32(%rbx)
mulsd %xmm4, %xmm5
movsd %xmm5, 40(%rbx)
movsd %xmm0, 48(%rbx)
movsd %xmm2, 56(%rbx)
movsd %xmm4, 64(%rbx)
movsd 296(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 72(%rbx)
movq 224(%rsp), %rdi
movl $104, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 280(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_21
# %bb.20: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movsd 120(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd 352(%rsp), %xmm1 # xmm1 = mem[0],zero
movl 8(%rsp), %ecx
movq 224(%rsp), %rdx
movq %rax, 56(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 16(%rsp)
movl %ecx, 116(%rsp)
movq %rdx, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 116(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 232(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd, %edi
leaq 128(%rsp), %r9
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_21: # in Loop: Header=BB5_19 Depth=1
movl 8(%rsp), %edi
shrl $4, %edi
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_23
# %bb.22: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 128(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE, %edi
leaq 16(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_23: # in Loop: Header=BB5_19 Depth=1
movl 8(%rsp), %edi
shrl $4, %edi
orq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_25
# %bb.24: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movl 8(%rsp), %ecx
movq %rax, 56(%rsp)
movl %ecx, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi, %edi
leaq 128(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_25: # in Loop: Header=BB5_19 Depth=1
movq 216(%rsp), %rdi
movq 80(%rsp), %rsi
movq 200(%rsp), %rdx
movl $1, %ecx
callq hipfftExecZ2Z
movq 288(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_27
# %bb.26: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movq 200(%rsp), %rcx
movl 8(%rsp), %edx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movl %edx, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i, %edi
leaq 128(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_27: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rsi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $4, %rdx
movq 192(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax # 4-byte Reload
cmpl 96(%rsp), %eax # 4-byte Folded Reload
movq 176(%rsp), %r9 # 8-byte Reload
movq 184(%rsp), %r10 # 8-byte Reload
movq 272(%rsp), %r11 # 8-byte Reload
jle .LBB5_42
.LBB5_28: # %._crit_edge364
# in Loop: Header=BB5_19 Depth=1
movq 280(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_30
# %bb.29: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movsd 120(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd 352(%rsp), %xmm1 # xmm1 = mem[0],zero
movl 8(%rsp), %ecx
movq 224(%rsp), %rdx
movq %rax, 56(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 16(%rsp)
movl %ecx, 116(%rsp)
movq %rdx, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 116(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 232(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd, %edi
leaq 128(%rsp), %r9
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_30: # in Loop: Header=BB5_19 Depth=1
movl 8(%rsp), %edi
shrl $4, %edi
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_32
# %bb.31: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 128(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE, %edi
leaq 16(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_32: # in Loop: Header=BB5_19 Depth=1
movl 8(%rsp), %edi
shrl $4, %edi
orq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_34
# %bb.33: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movl 8(%rsp), %ecx
movq %rax, 56(%rsp)
movl %ecx, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi, %edi
leaq 128(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_34: # in Loop: Header=BB5_19 Depth=1
movq 216(%rsp), %rdi
movq 80(%rsp), %rsi
movq 200(%rsp), %rdx
movl $1, %ecx
callq hipfftExecZ2Z
movq 288(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_36
# %bb.35: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rax
movq 200(%rsp), %rcx
movl 8(%rsp), %edx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movl %edx, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i, %edi
leaq 128(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_36: # in Loop: Header=BB5_19 Depth=1
movq 80(%rsp), %rsi
movl 8(%rsp), %edx
imull %edx, %edx
shlq $4, %rdx
movq 192(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax # 4-byte Reload
cmpl 96(%rsp), %eax # 4-byte Folded Reload
movq 176(%rsp), %r9 # 8-byte Reload
movq 184(%rsp), %r10 # 8-byte Reload
movq 272(%rsp), %r11 # 8-byte Reload
jg .LBB5_18
# %bb.37: # %.preheader323.lr.ph
# in Loop: Header=BB5_19 Depth=1
movslq 8(%rsp), %rax
movq 376(%rsp), %rcx # 8-byte Reload
imulq %rax, %rcx
addq %r11, %rcx
shlq $4, %rax
xorl %edx, %edx
jmp .LBB5_39
.p2align 4, 0x90
.LBB5_38: # %._crit_edge371
# in Loop: Header=BB5_39 Depth=2
incq %rdx
addq %rax, %rcx
cmpq %r14, %rdx
je .LBB5_18
.LBB5_39: # %.preheader323
# Parent Loop BB5_19 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_41 Depth 3
cmpl %ebp, %r9d
jg .LBB5_38
# %bb.40: # %.lr.ph370
# in Loop: Header=BB5_39 Depth=2
movq (%r10,%rdx,8), %rsi
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_41: # Parent Loop BB5_19 Depth=1
# Parent Loop BB5_39 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdi), %xmm0 # xmm0 = mem[0],zero
addsd (%rsi,%r8,8), %xmm0
movsd %xmm0, (%rsi,%r8,8)
incq %r8
addq $16, %rdi
cmpq %r8, %r15
jne .LBB5_41
jmp .LBB5_38
.p2align 4, 0x90
.LBB5_42: # %.preheader324.lr.ph
# in Loop: Header=BB5_19 Depth=1
movl 8(%rsp), %eax
movq 368(%rsp), %rcx # 8-byte Reload
addl %eax, %ecx
imull %eax, %ecx
xorl %edx, %edx
jmp .LBB5_44
.p2align 4, 0x90
.LBB5_43: # %._crit_edge360
# in Loop: Header=BB5_44 Depth=2
incq %rdx
subl %eax, %ecx
cmpq %r14, %rdx
je .LBB5_28
.LBB5_44: # %.preheader324
# Parent Loop BB5_19 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_46 Depth 3
cmpl %ebp, %r9d
jg .LBB5_43
# %bb.45: # %.lr.ph359
# in Loop: Header=BB5_44 Depth=2
movslq %ecx, %rsi
shlq $4, %rsi
addq %r11, %rsi
movq (%r10,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_46: # Parent Loop BB5_19 Depth=1
# Parent Loop BB5_44 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rsi), %xmm0 # xmm0 = mem[0],zero
addsd (%rdi,%r8,8), %xmm0
movsd %xmm0, (%rdi,%r8,8)
incq %r8
addq $16, %rsi
cmpq %r8, %r15
jne .LBB5_46
jmp .LBB5_43
.LBB5_47: # %._crit_edge379
movq 216(%rsp), %rdi
callq hipfftDestroy
movq 80(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movl 12(%rsp), %eax # 4-byte Reload
cmpl 96(%rsp), %eax # 4-byte Folded Reload
movq 360(%rsp), %r13 # 8-byte Reload
jle .LBB5_52
.LBB5_48: # %.preheader
cmpl $0, 244(%rsp) # 4-byte Folded Reload
movq 256(%rsp), %r14 # 8-byte Reload
movq 184(%rsp), %r15 # 8-byte Reload
je .LBB5_51
# %bb.49: # %.lr.ph392.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_50: # %.lr.ph392
# =>This Inner Loop Header: Depth=1
movq (%r15,%rbx,8), %rdi
callq free
incq %rbx
cmpq %rbx, %r14
jne .LBB5_50
.LBB5_51: # %._crit_edge393
movq %r15, %rdi
callq free
movq %r13, %rdi
callq fclose
movq 264(%rsp), %rdi # 8-byte Reload
callq fclose
xorl %eax, %eax
addq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_52: # %.lr.ph390
.cfi_def_cfa_offset 496
movl %ebp, %ebx
movq 176(%rsp), %rcx # 8-byte Reload
subl %ecx, %ebx
incl %ebx
movq 96(%rsp), %rax # 8-byte Reload
subl 12(%rsp), %eax # 4-byte Folded Reload
incl %eax
movq %rax, 96(%rsp) # 8-byte Spill
leal 1(%rcx), %r14d
xorl %r15d, %r15d
movsd .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero
movl %ebp, 248(%rsp) # 4-byte Spill
jmp .LBB5_54
.p2align 4, 0x90
.LBB5_53: # %._crit_edge385
# in Loop: Header=BB5_54 Depth=1
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
movsd .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero
incq %r15
incl 12(%rsp) # 4-byte Folded Spill
cmpq 96(%rsp), %r15 # 8-byte Folded Reload
movl 248(%rsp), %ebp # 4-byte Reload
movsd .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero
je .LBB5_48
.LBB5_54: # =>This Loop Header: Depth=1
# Child Loop BB5_56 Depth 2
movl 8(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd %xmm1, %xmm0
cmpl %ebp, 176(%rsp) # 4-byte Folded Reload
jg .LBB5_53
# %bb.55: # %.lr.ph384
# in Loop: Header=BB5_54 Depth=1
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl 12(%rsp), %eax # 4-byte Reload
subl %ecx, %eax
mulsd 120(%rsp), %xmm0
incl %eax
movapd %xmm3, %xmm1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
divsd %xmm0, %xmm1
mulsd %xmm1, %xmm2
movsd %xmm2, 192(%rsp) # 8-byte Spill
movq 184(%rsp), %rax # 8-byte Reload
movq (%rax,%r15,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_56: # Parent Loop BB5_54 Depth=1
# => This Inner Loop Header: Depth=2
movl 8(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movapd %xmm0, %xmm1
mulsd .LCPI5_0(%rip), %xmm1
mulsd 120(%rsp), %xmm1
movsd (%r12,%rbp,8), %xmm2 # xmm2 = mem[0],zero
divsd %xmm0, %xmm2
movapd %xmm3, %xmm0
divsd %xmm1, %xmm0
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
leal (%r14,%rbp), %eax
subl %ecx, %eax
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movl $.L.str.11, %esi
movq %r13, %rdi
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $3, %al
callq fprintf
movsd .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero
incq %rbp
cmpq %rbp, %rbx
jne .LBB5_56
jmp .LBB5_53
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE,@object # @_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.section .rodata,"a",@progbits
.globl _Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.p2align 3, 0x0
_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE:
.quad _Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.size _Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE, 8
.type _Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi,@object # @_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.globl _Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.p2align 3, 0x0
_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi:
.quad _Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.size _Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi, 8
.type _Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i,@object # @_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.globl _Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.p2align 3, 0x0
_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i:
.quad _Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.size _Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i, 8
.type _Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd,@object # @_Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.globl _Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.p2align 3, 0x0
_Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd:
.quad _Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.size _Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd, 8
.type _Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd,@object # @_Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.globl _Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.p2align 3, 0x0
_Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd:
.quad _Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.size _Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "spec.dat"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lf %lf %lf %lf"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lf %lf %lf"
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %lf"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%lf"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d %d %d %d %d %d\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%lf %lf %lf %lf %lf %lf %lf\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%lf\t%lf\t%le\n"
.size .L.str.11, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE"
.size .L__unnamed_1, 46
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi"
.size .L__unnamed_2, 47
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i"
.size .L__unnamed_3, 51
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd"
.size .L__unnamed_4, 50
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd"
.size .L__unnamed_5, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.addrsig_sym _Z31__device_stub__kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.addrsig_sym _Z32__device_stub__kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.addrsig_sym _Z30__device_stub__kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.addrsig_sym _Z33__device_stub__kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kernelHalfFirstXP15HIP_vector_typeIdLj2EE
.addrsig_sym _Z16kernelHalfFirstYP15HIP_vector_typeIdLj2EEi
.addrsig_sym _Z17kernelPermutationP15HIP_vector_typeIdLj2EES1_i
.addrsig_sym _Z15kernelRephasingP15HIP_vector_typeIdLj2EEddiPd
.addrsig_sym _Z18kernelNonRephasingP15HIP_vector_typeIdLj2EEddiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | typedef double BYTE; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | typedef double BYTE; | .file "tmpxft_00005d6f_00000000-6_typedef.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | typedef double BYTE; | #include <hip/hip_runtime.h>
typedef double BYTE; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
typedef double BYTE; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
typedef double BYTE; | .text
.file "typedef.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005d6f_00000000-6_typedef.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "typedef.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstring>
#include<iostream>
using namespace std;
class Myclass
{
public:
Myclass(int a=0,int b=0)
{_a=a;_b=b;}
virtual __host__ __device__ void printValues()
{
printf("a = %d, b = %d\n", _a, _b);
}
private:
int _a;
int _b;
};
__global__ void virtualFunctions(Myclass *vf)
{
Myclass vf_local = Myclass(*vf);
memcpy(vf, &vf_local, sizeof(Myclass));
vf->printValues();
}
__global__ void callVFunc(Myclass *vf)
{
vf->printValues();
}
int main() {
//CPU
Myclass vf_host(4,5);
//GPU
Myclass *vf;
cudaMalloc(&vf, sizeof(Myclass));
// CPU --> GPU
cudaMemcpy(vf, &vf_host, sizeof(Myclass), cudaMemcpyHostToDevice);
virtualFunctions<<<1, 1>>>(vf);
cudaDeviceSynchronize();
callVFunc<<<1, 1>>>(vf);
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z9callVFuncP7Myclass
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fcc00078e00ff */
/*0040*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ LD.E R0, [R2.64] ; /* 0x0000000402007980 */
/* 0x004ea2000c101900 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R6, c[0x2][R0] ; /* 0x0080000000067b82 */
/* 0x00406c0000000a00 */
/*0090*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; /* 0x00000000ff157424 */
/* 0x000fc800078e00ff */
/*00b0*/ CALL.REL.NOINC R6 0x0 ; /* 0xffffff4006007344 */
/* 0x003fea0003c3ffff */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0005 */
/*00f0*/ STL [R1+0x10], R21 ; /* 0x0000101501007387 */
/* 0x000fe80000100800 */
/*0100*/ STL [R1+0xc], R20 ; /* 0x00000c1401007387 */
/* 0x000fe80000100800 */
/*0110*/ STL [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e40000100800 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc800078e0004 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0140*/ LD.E.64 R2, [R2.64+0x8] ; /* 0x0000080402027980 */
/* 0x000ea2000c101b00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0190*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*01b0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100a00 */
/*01c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fc60000000000 */
/*01d0*/ MOV R11, 0x240 ; /* 0x00000240000b7802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R0, 0x1c0 ; /* 0x000001c000007802 */
/* 0x000fc40000000f00 */
/*01f0*/ MOV R13, 0x0 ; /* 0x00000000000d7802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fe40000000f00 */
/*0210*/ IADD3 R20, P0, P1, -R0, R11, R2 ; /* 0x0000000b00147210 */
/* 0x000fc8000791e102 */
/*0220*/ IADD3.X R21, ~R10, R13, R3, P0, P1 ; /* 0x0000000d0a157210 */
/* 0x000fc800007e2503 */
/*0230*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0240*/ LDL R20, [R1+0xc] ; /* 0x00000c0001147983 */
/* 0x0000a80000100800 */
/*0250*/ LDL R21, [R1+0x10] ; /* 0x0000100001157983 */
/* 0x0000a80000100800 */
/*0260*/ LDL R2, [R1+0x8] ; /* 0x0000080001027983 */
/* 0x0000a40000100800 */
/*0270*/ IADD3 R1, R1, 0x18, RZ ; /* 0x0000001801017810 */
/* 0x001fe20007ffe0ff */
/*0280*/ RET.REL.NODEC R20 0x0 ; /* 0xfffffd7014007950 */
/* 0x004fec0003c3ffff */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16virtualFunctionsP7Myclass
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff0b7624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fc600078e00ff */
/*0080*/ IADD3 R11, P0, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fca0007f1e0ff */
/*0090*/ IMAD.X R0, RZ, RZ, c[0x4][0xc], P0 ; /* 0x01000300ff007624 */
/* 0x000fe200000e06ff */
/*00a0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101104 */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f1e0ff */
/*00c0*/ STG.E.U8 [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x0001e2000c101104 */
/*00d0*/ SHF.R.U32.HI R5, RZ, 0x18, R0.reuse ; /* 0x00000018ff057819 */
/* 0x100fe40000011600 */
/*00e0*/ SHF.R.U32.HI R7, RZ, 0x10, R0.reuse ; /* 0x00000010ff077819 */
/* 0x100fe40000011600 */
/*00f0*/ SHF.R.U32.HI R19, RZ, 0x8, R0.reuse ; /* 0x00000008ff137819 */
/* 0x100fe20000011600 */
/*0100*/ STG.E.U8 [R2.64+0x7], R5 ; /* 0x0000070502007986 */
/* 0x0003e2000c101104 */
/*0110*/ SHF.R.U64 R17, R11.reuse, 0x18, R0.reuse ; /* 0x000000180b117819 */
/* 0x140fe40000001200 */
/*0120*/ SHF.R.U64 R15, R11.reuse, 0x10, R0.reuse ; /* 0x000000100b0f7819 */
/* 0x140fe20000001200 */
/*0130*/ STG.E.U8 [R2.64+0x5], R19 ; /* 0x0000051302007986 */
/* 0x000fe2000c101104 */
/*0140*/ SHF.R.U64 R13, R11, 0x8, R0 ; /* 0x000000080b0d7819 */
/* 0x000fc40000001200 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe20000000f00 */
/*0160*/ STG.E.U8 [R2.64+0x3], R17 ; /* 0x0000031102007986 */
/* 0x000fe6000c101104 */
/*0170*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0000e20000000a00 */
/*0180*/ STG.E.U8 [R2.64+0x2], R15 ; /* 0x0000020f02007986 */
/* 0x000fe2000c101104 */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x002fc600078e00ff */
/*01a0*/ STG.E.U8 [R2.64+0x1], R13 ; /* 0x0000010d02007986 */
/* 0x000fe8000c101104 */
/*01b0*/ STG.E.U8 [R2.64+0x6], R7 ; /* 0x0000060702007986 */
/* 0x0003e4000c101104 */
/*01c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x002fe400000e06ff */
/*01d0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0041e80000100a00 */
/*01e0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x008fe40000000000 */
/*01f0*/ MOV R9, 0x260 ; /* 0x0000026000097802 */
/* 0x001fe40000000f00 */
/*0200*/ MOV R20, 0x1e0 ; /* 0x000001e000147802 */
/* 0x000fc40000000f00 */
/*0210*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0230*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0240*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0250*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0005 */
/*0290*/ STL [R1+0x10], R21 ; /* 0x0000101501007387 */
/* 0x000fe80000100800 */
/*02a0*/ STL [R1+0xc], R20 ; /* 0x00000c1401007387 */
/* 0x000fe80000100800 */
/*02b0*/ STL [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e40000100800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc800078e0004 */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*02e0*/ LD.E.64 R2, [R2.64+0x8] ; /* 0x0000080402027980 */
/* 0x000ea2000c101b00 */
/*02f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0330*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*0340*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0350*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100a00 */
/*0360*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fc60000000000 */
/*0370*/ MOV R11, 0x3e0 ; /* 0x000003e0000b7802 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R0, 0x360 ; /* 0x0000036000007802 */
/* 0x000fc40000000f00 */
/*0390*/ MOV R13, 0x0 ; /* 0x00000000000d7802 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fe40000000f00 */
/*03b0*/ IADD3 R20, P0, P1, -R0, R11, R2 ; /* 0x0000000b00147210 */
/* 0x000fc8000791e102 */
/*03c0*/ IADD3.X R21, ~R10, R13, R3, P0, P1 ; /* 0x0000000d0a157210 */
/* 0x000fc800007e2503 */
/*03d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*03e0*/ LDL R20, [R1+0xc] ; /* 0x00000c0001147983 */
/* 0x0000a80000100800 */
/*03f0*/ LDL R21, [R1+0x10] ; /* 0x0000100001157983 */
/* 0x0000a80000100800 */
/*0400*/ LDL R2, [R1+0x8] ; /* 0x0000080001027983 */
/* 0x0000a40000100800 */
/*0410*/ IADD3 R1, R1, 0x18, RZ ; /* 0x0000001801017810 */
/* 0x001fe20007ffe0ff */
/*0420*/ RET.REL.NODEC R20 0x0 ; /* 0xfffffbd014007950 */
/* 0x004fec0003c3ffff */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstring>
#include<iostream>
using namespace std;
class Myclass
{
public:
Myclass(int a=0,int b=0)
{_a=a;_b=b;}
virtual __host__ __device__ void printValues()
{
printf("a = %d, b = %d\n", _a, _b);
}
private:
int _a;
int _b;
};
__global__ void virtualFunctions(Myclass *vf)
{
Myclass vf_local = Myclass(*vf);
memcpy(vf, &vf_local, sizeof(Myclass));
vf->printValues();
}
__global__ void callVFunc(Myclass *vf)
{
vf->printValues();
}
int main() {
//CPU
Myclass vf_host(4,5);
//GPU
Myclass *vf;
cudaMalloc(&vf, sizeof(Myclass));
// CPU --> GPU
cudaMemcpy(vf, &vf_host, sizeof(Myclass), cudaMemcpyHostToDevice);
virtualFunctions<<<1, 1>>>(vf);
cudaDeviceSynchronize();
callVFunc<<<1, 1>>>(vf);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000896a0_00000000-6_vfunc_ub.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata._ZN7Myclass11printValuesEv.str1.1,"aMS",@progbits,1
.LC0:
.string "a = %d, b = %d\n"
#NO_APP
.section .text._ZN7Myclass11printValuesEv,"axG",@progbits,_ZN7Myclass11printValuesEv,comdat
.align 2
.weak _ZN7Myclass11printValuesEv
.type _ZN7Myclass11printValuesEv, @function
_ZN7Myclass11printValuesEv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 12(%rdi), %ecx
movl 8(%rdi), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZN7Myclass11printValuesEv, .-_ZN7Myclass11printValuesEv
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
.type _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass, @function
_Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass:
.LFB3698:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16virtualFunctionsP7Myclass(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass, .-_Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
.globl _Z16virtualFunctionsP7Myclass
.type _Z16virtualFunctionsP7Myclass, @function
_Z16virtualFunctionsP7Myclass:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z16virtualFunctionsP7Myclass, .-_Z16virtualFunctionsP7Myclass
.globl _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
.type _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass, @function
_Z35__device_stub__Z9callVFuncP7MyclassP7Myclass:
.LFB3700:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9callVFuncP7Myclass(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass, .-_Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
.globl _Z9callVFuncP7Myclass
.type _Z9callVFuncP7Myclass, @function
_Z9callVFuncP7Myclass:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z9callVFuncP7Myclass, .-_Z9callVFuncP7Myclass
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16+_ZTV7Myclass(%rip), %rax
movq %rax, 32(%rsp)
movl $4, 40(%rsp)
movl $5, 44(%rsp)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
call cudaDeviceSynchronize@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq (%rsp), %rdi
call _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
jmp .L22
.L27:
movq (%rsp), %rdi
call _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9callVFuncP7Myclass"
.LC2:
.string "_Z16virtualFunctionsP7Myclass"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9callVFuncP7Myclass(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16virtualFunctionsP7Myclass(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS7Myclass
.section .rodata._ZTS7Myclass,"aG",@progbits,_ZTS7Myclass,comdat
.align 8
.type _ZTS7Myclass, @object
.size _ZTS7Myclass, 9
_ZTS7Myclass:
.string "7Myclass"
.weak _ZTI7Myclass
.section .data.rel.ro._ZTI7Myclass,"awG",@progbits,_ZTI7Myclass,comdat
.align 8
.type _ZTI7Myclass, @object
.size _ZTI7Myclass, 16
_ZTI7Myclass:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS7Myclass
.weak _ZTV7Myclass
.section .data.rel.ro.local._ZTV7Myclass,"awG",@progbits,_ZTV7Myclass,comdat
.align 8
.type _ZTV7Myclass, @object
.size _ZTV7Myclass, 24
_ZTV7Myclass:
.quad 0
.quad _ZTI7Myclass
.quad _ZN7Myclass11printValuesEv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstring>
#include<iostream>
using namespace std;
class Myclass
{
public:
Myclass(int a=0,int b=0)
{_a=a;_b=b;}
virtual __host__ __device__ void printValues()
{
printf("a = %d, b = %d\n", _a, _b);
}
private:
int _a;
int _b;
};
__global__ void virtualFunctions(Myclass *vf)
{
Myclass vf_local = Myclass(*vf);
memcpy(vf, &vf_local, sizeof(Myclass));
vf->printValues();
}
__global__ void callVFunc(Myclass *vf)
{
vf->printValues();
}
int main() {
//CPU
Myclass vf_host(4,5);
//GPU
Myclass *vf;
cudaMalloc(&vf, sizeof(Myclass));
// CPU --> GPU
cudaMemcpy(vf, &vf_host, sizeof(Myclass), cudaMemcpyHostToDevice);
virtualFunctions<<<1, 1>>>(vf);
cudaDeviceSynchronize();
callVFunc<<<1, 1>>>(vf);
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstring>
#include<iostream>
using namespace std;
class Myclass
{
public:
Myclass(int a=0,int b=0)
{_a=a;_b=b;}
virtual __host__ __device__ void printValues()
{
printf("a = %d, b = %d\n", _a, _b);
}
private:
int _a;
int _b;
};
__global__ void virtualFunctions(Myclass *vf)
{
Myclass vf_local = Myclass(*vf);
memcpy(vf, &vf_local, sizeof(Myclass));
vf->printValues();
}
__global__ void callVFunc(Myclass *vf)
{
vf->printValues();
}
int main() {
//CPU
Myclass vf_host(4,5);
//GPU
Myclass *vf;
hipMalloc(&vf, sizeof(Myclass));
// CPU --> GPU
hipMemcpy(vf, &vf_host, sizeof(Myclass), hipMemcpyHostToDevice);
virtualFunctions<<<1, 1>>>(vf);
hipDeviceSynchronize();
callVFunc<<<1, 1>>>(vf);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstring>
#include<iostream>
using namespace std;
class Myclass
{
public:
Myclass(int a=0,int b=0)
{_a=a;_b=b;}
virtual __host__ __device__ void printValues()
{
printf("a = %d, b = %d\n", _a, _b);
}
private:
int _a;
int _b;
};
__global__ void virtualFunctions(Myclass *vf)
{
Myclass vf_local = Myclass(*vf);
memcpy(vf, &vf_local, sizeof(Myclass));
vf->printValues();
}
__global__ void callVFunc(Myclass *vf)
{
vf->printValues();
}
int main() {
//CPU
Myclass vf_host(4,5);
//GPU
Myclass *vf;
hipMalloc(&vf, sizeof(Myclass));
// CPU --> GPU
hipMemcpy(vf, &vf_host, sizeof(Myclass), hipMemcpyHostToDevice);
virtualFunctions<<<1, 1>>>(vf);
hipDeviceSynchronize();
callVFunc<<<1, 1>>>(vf);
hipDeviceSynchronize();
return 0;
} | .text
.file "vfunc_ub.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__virtualFunctionsP7Myclass # -- Begin function _Z31__device_stub__virtualFunctionsP7Myclass
.p2align 4, 0x90
.type _Z31__device_stub__virtualFunctionsP7Myclass,@function
_Z31__device_stub__virtualFunctionsP7Myclass: # @_Z31__device_stub__virtualFunctionsP7Myclass
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16virtualFunctionsP7Myclass, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z31__device_stub__virtualFunctionsP7Myclass, .Lfunc_end0-_Z31__device_stub__virtualFunctionsP7Myclass
.cfi_endproc
# -- End function
.globl _Z24__device_stub__callVFuncP7Myclass # -- Begin function _Z24__device_stub__callVFuncP7Myclass
.p2align 4, 0x90
.type _Z24__device_stub__callVFuncP7Myclass,@function
_Z24__device_stub__callVFuncP7Myclass: # @_Z24__device_stub__callVFuncP7Myclass
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9callVFuncP7Myclass, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z24__device_stub__callVFuncP7Myclass, .Lfunc_end1-_Z24__device_stub__callVFuncP7Myclass
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq $_ZTV7Myclass+16, 80(%rsp)
movabsq $21474836484, %rax # imm = 0x500000004
movq %rax, 88(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z16virtualFunctionsP7Myclass, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z9callVFuncP7Myclass, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZN7Myclass11printValuesEv,"axG",@progbits,_ZN7Myclass11printValuesEv,comdat
.weak _ZN7Myclass11printValuesEv # -- Begin function _ZN7Myclass11printValuesEv
.p2align 4, 0x90
.type _ZN7Myclass11printValuesEv,@function
_ZN7Myclass11printValuesEv: # @_ZN7Myclass11printValuesEv
.cfi_startproc
# %bb.0:
movl 8(%rdi), %esi
movl 12(%rdi), %edx
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end3:
.size _ZN7Myclass11printValuesEv, .Lfunc_end3-_ZN7Myclass11printValuesEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16virtualFunctionsP7Myclass, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9callVFuncP7Myclass, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16virtualFunctionsP7Myclass,@object # @_Z16virtualFunctionsP7Myclass
.section .rodata,"a",@progbits
.globl _Z16virtualFunctionsP7Myclass
.p2align 3, 0x0
_Z16virtualFunctionsP7Myclass:
.quad _Z31__device_stub__virtualFunctionsP7Myclass
.size _Z16virtualFunctionsP7Myclass, 8
.type _Z9callVFuncP7Myclass,@object # @_Z9callVFuncP7Myclass
.globl _Z9callVFuncP7Myclass
.p2align 3, 0x0
_Z9callVFuncP7Myclass:
.quad _Z24__device_stub__callVFuncP7Myclass
.size _Z9callVFuncP7Myclass, 8
.type _ZTV7Myclass,@object # @_ZTV7Myclass
.section .rodata._ZTV7Myclass,"aG",@progbits,_ZTV7Myclass,comdat
.weak _ZTV7Myclass
.p2align 3, 0x0
_ZTV7Myclass:
.quad 0
.quad _ZTI7Myclass
.quad _ZN7Myclass11printValuesEv
.size _ZTV7Myclass, 24
.type _ZTS7Myclass,@object # @_ZTS7Myclass
.section .rodata._ZTS7Myclass,"aG",@progbits,_ZTS7Myclass,comdat
.weak _ZTS7Myclass
_ZTS7Myclass:
.asciz "7Myclass"
.size _ZTS7Myclass, 9
.type _ZTI7Myclass,@object # @_ZTI7Myclass
.section .rodata._ZTI7Myclass,"aG",@progbits,_ZTI7Myclass,comdat
.weak _ZTI7Myclass
.p2align 3, 0x0
_ZTI7Myclass:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS7Myclass
.size _ZTI7Myclass, 16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a = %d, b = %d\n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16virtualFunctionsP7Myclass"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9callVFuncP7Myclass"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__virtualFunctionsP7Myclass
.addrsig_sym _Z24__device_stub__callVFuncP7Myclass
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16virtualFunctionsP7Myclass
.addrsig_sym _Z9callVFuncP7Myclass
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTS7Myclass
.addrsig_sym _ZTI7Myclass
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000896a0_00000000-6_vfunc_ub.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata._ZN7Myclass11printValuesEv.str1.1,"aMS",@progbits,1
.LC0:
.string "a = %d, b = %d\n"
#NO_APP
.section .text._ZN7Myclass11printValuesEv,"axG",@progbits,_ZN7Myclass11printValuesEv,comdat
.align 2
.weak _ZN7Myclass11printValuesEv
.type _ZN7Myclass11printValuesEv, @function
_ZN7Myclass11printValuesEv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 12(%rdi), %ecx
movl 8(%rdi), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZN7Myclass11printValuesEv, .-_ZN7Myclass11printValuesEv
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
.type _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass, @function
_Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass:
.LFB3698:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16virtualFunctionsP7Myclass(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass, .-_Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
.globl _Z16virtualFunctionsP7Myclass
.type _Z16virtualFunctionsP7Myclass, @function
_Z16virtualFunctionsP7Myclass:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z16virtualFunctionsP7Myclass, .-_Z16virtualFunctionsP7Myclass
.globl _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
.type _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass, @function
_Z35__device_stub__Z9callVFuncP7MyclassP7Myclass:
.LFB3700:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9callVFuncP7Myclass(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass, .-_Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
.globl _Z9callVFuncP7Myclass
.type _Z9callVFuncP7Myclass, @function
_Z9callVFuncP7Myclass:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z9callVFuncP7Myclass, .-_Z9callVFuncP7Myclass
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16+_ZTV7Myclass(%rip), %rax
movq %rax, 32(%rsp)
movl $4, 40(%rsp)
movl $5, 44(%rsp)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
call cudaDeviceSynchronize@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq (%rsp), %rdi
call _Z43__device_stub__Z16virtualFunctionsP7MyclassP7Myclass
jmp .L22
.L27:
movq (%rsp), %rdi
call _Z35__device_stub__Z9callVFuncP7MyclassP7Myclass
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9callVFuncP7Myclass"
.LC2:
.string "_Z16virtualFunctionsP7Myclass"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9callVFuncP7Myclass(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16virtualFunctionsP7Myclass(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS7Myclass
.section .rodata._ZTS7Myclass,"aG",@progbits,_ZTS7Myclass,comdat
.align 8
.type _ZTS7Myclass, @object
.size _ZTS7Myclass, 9
_ZTS7Myclass:
.string "7Myclass"
.weak _ZTI7Myclass
.section .data.rel.ro._ZTI7Myclass,"awG",@progbits,_ZTI7Myclass,comdat
.align 8
.type _ZTI7Myclass, @object
.size _ZTI7Myclass, 16
_ZTI7Myclass:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS7Myclass
.weak _ZTV7Myclass
.section .data.rel.ro.local._ZTV7Myclass,"awG",@progbits,_ZTV7Myclass,comdat
.align 8
.type _ZTV7Myclass, @object
.size _ZTV7Myclass, 24
_ZTV7Myclass:
.quad 0
.quad _ZTI7Myclass
.quad _ZN7Myclass11printValuesEv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vfunc_ub.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__virtualFunctionsP7Myclass # -- Begin function _Z31__device_stub__virtualFunctionsP7Myclass
.p2align 4, 0x90
.type _Z31__device_stub__virtualFunctionsP7Myclass,@function
_Z31__device_stub__virtualFunctionsP7Myclass: # @_Z31__device_stub__virtualFunctionsP7Myclass
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16virtualFunctionsP7Myclass, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z31__device_stub__virtualFunctionsP7Myclass, .Lfunc_end0-_Z31__device_stub__virtualFunctionsP7Myclass
.cfi_endproc
# -- End function
.globl _Z24__device_stub__callVFuncP7Myclass # -- Begin function _Z24__device_stub__callVFuncP7Myclass
.p2align 4, 0x90
.type _Z24__device_stub__callVFuncP7Myclass,@function
_Z24__device_stub__callVFuncP7Myclass: # @_Z24__device_stub__callVFuncP7Myclass
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9callVFuncP7Myclass, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z24__device_stub__callVFuncP7Myclass, .Lfunc_end1-_Z24__device_stub__callVFuncP7Myclass
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq $_ZTV7Myclass+16, 80(%rsp)
movabsq $21474836484, %rax # imm = 0x500000004
movq %rax, 88(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z16virtualFunctionsP7Myclass, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z9callVFuncP7Myclass, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZN7Myclass11printValuesEv,"axG",@progbits,_ZN7Myclass11printValuesEv,comdat
.weak _ZN7Myclass11printValuesEv # -- Begin function _ZN7Myclass11printValuesEv
.p2align 4, 0x90
.type _ZN7Myclass11printValuesEv,@function
_ZN7Myclass11printValuesEv: # @_ZN7Myclass11printValuesEv
.cfi_startproc
# %bb.0:
movl 8(%rdi), %esi
movl 12(%rdi), %edx
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end3:
.size _ZN7Myclass11printValuesEv, .Lfunc_end3-_ZN7Myclass11printValuesEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16virtualFunctionsP7Myclass, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9callVFuncP7Myclass, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16virtualFunctionsP7Myclass,@object # @_Z16virtualFunctionsP7Myclass
.section .rodata,"a",@progbits
.globl _Z16virtualFunctionsP7Myclass
.p2align 3, 0x0
_Z16virtualFunctionsP7Myclass:
.quad _Z31__device_stub__virtualFunctionsP7Myclass
.size _Z16virtualFunctionsP7Myclass, 8
.type _Z9callVFuncP7Myclass,@object # @_Z9callVFuncP7Myclass
.globl _Z9callVFuncP7Myclass
.p2align 3, 0x0
_Z9callVFuncP7Myclass:
.quad _Z24__device_stub__callVFuncP7Myclass
.size _Z9callVFuncP7Myclass, 8
.type _ZTV7Myclass,@object # @_ZTV7Myclass
.section .rodata._ZTV7Myclass,"aG",@progbits,_ZTV7Myclass,comdat
.weak _ZTV7Myclass
.p2align 3, 0x0
_ZTV7Myclass:
.quad 0
.quad _ZTI7Myclass
.quad _ZN7Myclass11printValuesEv
.size _ZTV7Myclass, 24
.type _ZTS7Myclass,@object # @_ZTS7Myclass
.section .rodata._ZTS7Myclass,"aG",@progbits,_ZTS7Myclass,comdat
.weak _ZTS7Myclass
_ZTS7Myclass:
.asciz "7Myclass"
.size _ZTS7Myclass, 9
.type _ZTI7Myclass,@object # @_ZTI7Myclass
.section .rodata._ZTI7Myclass,"aG",@progbits,_ZTI7Myclass,comdat
.weak _ZTI7Myclass
.p2align 3, 0x0
_ZTI7Myclass:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS7Myclass
.size _ZTI7Myclass, 16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a = %d, b = %d\n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16virtualFunctionsP7Myclass"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9callVFuncP7Myclass"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__virtualFunctionsP7Myclass
.addrsig_sym _Z24__device_stub__callVFuncP7Myclass
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16virtualFunctionsP7Myclass
.addrsig_sym _Z9callVFuncP7Myclass
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTS7Myclass
.addrsig_sym _ZTI7Myclass
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
//size of array
#define N 4096
//vector addition kernel
__global__ void vectorAddKernel(int *a, int *b, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]+b[tdx];
}
}
int main()
{
//grid and block sizes
dim3 grid(16, 1, 1);
dim3 block(256, 1, 1);
//host arrays
int a_h[N];
int b_h[N];
int c_h[N];
//device memory pointers
int *a_d;
int *b_d;
int *c_d;
//load arrays with some numbers
for(int i=0; i<N; i++)
{
a_h[i] = i;
b_h[i] = i*1;
}
//allocate device memory
cudaMalloc((void**)&a_d, N*sizeof(int));
cudaMalloc((void**)&b_d, N*sizeof(int));
cudaMalloc((void**)&c_d, N*sizeof(int));
//copy the host arrays to device
cudaMemcpy(&a_d, &a_h, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(&b_d, &b_h, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(&c_d, &c_h, N*sizeof(int), cudaMemcpyHostToDevice);
//CUDA events to measure time
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
//start timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//launch kernel
vectorAddKernel<<<grid, block>>>(a_d, b_d, c_d);
//stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
//copy the results to host
cudaMemcpy(c_h, c_d, N*sizeof(int), cudaMemcpyDeviceToHost);
//print the results
for(int i=0; i<N; i++)
{
printf("%i+%i = %i\n",a_h[i], b_h[i], c_h[i]);
}
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
//clean up
cudaFree(a_h);
cudaFree(b_h);
cudaFree(c_h);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z15vectorAddKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xfff, PT ; /* 0x00000fff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
//size of array
#define N 4096
//vector addition kernel
__global__ void vectorAddKernel(int *a, int *b, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]+b[tdx];
}
}
int main()
{
//grid and block sizes
dim3 grid(16, 1, 1);
dim3 block(256, 1, 1);
//host arrays
int a_h[N];
int b_h[N];
int c_h[N];
//device memory pointers
int *a_d;
int *b_d;
int *c_d;
//load arrays with some numbers
for(int i=0; i<N; i++)
{
a_h[i] = i;
b_h[i] = i*1;
}
//allocate device memory
cudaMalloc((void**)&a_d, N*sizeof(int));
cudaMalloc((void**)&b_d, N*sizeof(int));
cudaMalloc((void**)&c_d, N*sizeof(int));
//copy the host arrays to device
cudaMemcpy(&a_d, &a_h, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(&b_d, &b_h, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(&c_d, &c_h, N*sizeof(int), cudaMemcpyHostToDevice);
//CUDA events to measure time
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
//start timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//launch kernel
vectorAddKernel<<<grid, block>>>(a_d, b_d, c_d);
//stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
//copy the results to host
cudaMemcpy(c_h, c_d, N*sizeof(int), cudaMemcpyDeviceToHost);
//print the results
for(int i=0; i<N; i++)
{
printf("%i+%i = %i\n",a_h[i], b_h[i], c_h[i]);
}
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
//clean up
cudaFree(a_h);
cudaFree(b_h);
cudaFree(c_h);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_000d3fb6_00000000-6_exc2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
.type _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_, @function
_Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15vectorAddKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_, .-_Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
.globl _Z15vectorAddKernelPiS_S_
.type _Z15vectorAddKernelPiS_S_, @function
_Z15vectorAddKernelPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15vectorAddKernelPiS_S_, .-_Z15vectorAddKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i+%i = %i\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time to calculate results: %f ms.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -49152(%rsp), %r11
.cfi_def_cfa 11, 49184
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $96, %rsp
.cfi_def_cfa_offset 49280
movq %fs:40, %rax
movq %rax, 49240(%rsp)
xorl %eax, %eax
movl $16, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
.L12:
movl %eax, 80(%rsp,%rax,4)
movl %eax, 16464(%rsp,%rax,4)
addq $1, %rax
cmpq $4096, %rax
jne .L12
leaq 16(%rsp), %r12
movl $16384, %esi
movq %r12, %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rbp
movl $16384, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rbx
movl $16384, %esi
movq %rbx, %rdi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $16384, %edx
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 16464(%rsp), %rsi
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 32848(%rsp), %rsi
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 32848(%rsp), %rdi
movl $2, %ecx
movl $16384, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 16464(%rsp,%rbx), %ecx
movl 80(%rsp,%rbx), %edx
movl 32848(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $16384, %rbx
jne .L14
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaFree@PLT
leaq 16464(%rsp), %rdi
call cudaFree@PLT
leaq 32848(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 49240(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $49248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z15vectorAddKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vectorAddKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
//size of array
#define N 4096
//vector addition kernel
__global__ void vectorAddKernel(int *a, int *b, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]+b[tdx];
}
}
int main()
{
//grid and block sizes
dim3 grid(16, 1, 1);
dim3 block(256, 1, 1);
//host arrays
int a_h[N];
int b_h[N];
int c_h[N];
//device memory pointers
int *a_d;
int *b_d;
int *c_d;
//load arrays with some numbers
for(int i=0; i<N; i++)
{
a_h[i] = i;
b_h[i] = i*1;
}
//allocate device memory
cudaMalloc((void**)&a_d, N*sizeof(int));
cudaMalloc((void**)&b_d, N*sizeof(int));
cudaMalloc((void**)&c_d, N*sizeof(int));
//copy the host arrays to device
cudaMemcpy(&a_d, &a_h, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(&b_d, &b_h, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(&c_d, &c_h, N*sizeof(int), cudaMemcpyHostToDevice);
//CUDA events to measure time
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
//start timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//launch kernel
vectorAddKernel<<<grid, block>>>(a_d, b_d, c_d);
//stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
//copy the results to host
cudaMemcpy(c_h, c_d, N*sizeof(int), cudaMemcpyDeviceToHost);
//print the results
for(int i=0; i<N; i++)
{
printf("%i+%i = %i\n",a_h[i], b_h[i], c_h[i]);
}
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
//clean up
cudaFree(a_h);
cudaFree(b_h);
cudaFree(c_h);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
//size of array
#define N 4096
//vector addition kernel
__global__ void vectorAddKernel(int *a, int *b, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]+b[tdx];
}
}
int main()
{
//grid and block sizes
dim3 grid(16, 1, 1);
dim3 block(256, 1, 1);
//host arrays
int a_h[N];
int b_h[N];
int c_h[N];
//device memory pointers
int *a_d;
int *b_d;
int *c_d;
//load arrays with some numbers
for(int i=0; i<N; i++)
{
a_h[i] = i;
b_h[i] = i*1;
}
//allocate device memory
hipMalloc((void**)&a_d, N*sizeof(int));
hipMalloc((void**)&b_d, N*sizeof(int));
hipMalloc((void**)&c_d, N*sizeof(int));
//copy the host arrays to device
hipMemcpy(&a_d, &a_h, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(&b_d, &b_h, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(&c_d, &c_h, N*sizeof(int), hipMemcpyHostToDevice);
//CUDA events to measure time
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
//start timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//launch kernel
vectorAddKernel<<<grid, block>>>(a_d, b_d, c_d);
//stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
//copy the results to host
hipMemcpy(c_h, c_d, N*sizeof(int), hipMemcpyDeviceToHost);
//print the results
for(int i=0; i<N; i++)
{
printf("%i+%i = %i\n",a_h[i], b_h[i], c_h[i]);
}
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
//clean up
hipFree(a_h);
hipFree(b_h);
hipFree(c_h);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
//size of array
#define N 4096
//vector addition kernel
__global__ void vectorAddKernel(int *a, int *b, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]+b[tdx];
}
}
int main()
{
//grid and block sizes
dim3 grid(16, 1, 1);
dim3 block(256, 1, 1);
//host arrays
int a_h[N];
int b_h[N];
int c_h[N];
//device memory pointers
int *a_d;
int *b_d;
int *c_d;
//load arrays with some numbers
for(int i=0; i<N; i++)
{
a_h[i] = i;
b_h[i] = i*1;
}
//allocate device memory
hipMalloc((void**)&a_d, N*sizeof(int));
hipMalloc((void**)&b_d, N*sizeof(int));
hipMalloc((void**)&c_d, N*sizeof(int));
//copy the host arrays to device
hipMemcpy(&a_d, &a_h, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(&b_d, &b_h, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(&c_d, &c_h, N*sizeof(int), hipMemcpyHostToDevice);
//CUDA events to measure time
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
//start timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//launch kernel
vectorAddKernel<<<grid, block>>>(a_d, b_d, c_d);
//stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
//copy the results to host
hipMemcpy(c_h, c_d, N*sizeof(int), hipMemcpyDeviceToHost);
//print the results
for(int i=0; i<N; i++)
{
printf("%i+%i = %i\n",a_h[i], b_h[i], c_h[i]);
}
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
//clean up
hipFree(a_h);
hipFree(b_h);
hipFree(c_h);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15vectorAddKernelPiS_S_
.globl _Z15vectorAddKernelPiS_S_
.p2align 8
.type _Z15vectorAddKernelPiS_S_,@function
_Z15vectorAddKernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15vectorAddKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15vectorAddKernelPiS_S_, .Lfunc_end0-_Z15vectorAddKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15vectorAddKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15vectorAddKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
//size of array
#define N 4096
//vector addition kernel
__global__ void vectorAddKernel(int *a, int *b, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]+b[tdx];
}
}
int main()
{
//grid and block sizes
dim3 grid(16, 1, 1);
dim3 block(256, 1, 1);
//host arrays
int a_h[N];
int b_h[N];
int c_h[N];
//device memory pointers
int *a_d;
int *b_d;
int *c_d;
//load arrays with some numbers
for(int i=0; i<N; i++)
{
a_h[i] = i;
b_h[i] = i*1;
}
//allocate device memory
hipMalloc((void**)&a_d, N*sizeof(int));
hipMalloc((void**)&b_d, N*sizeof(int));
hipMalloc((void**)&c_d, N*sizeof(int));
//copy the host arrays to device
hipMemcpy(&a_d, &a_h, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(&b_d, &b_h, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(&c_d, &c_h, N*sizeof(int), hipMemcpyHostToDevice);
//CUDA events to measure time
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
//start timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//launch kernel
vectorAddKernel<<<grid, block>>>(a_d, b_d, c_d);
//stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
//copy the results to host
hipMemcpy(c_h, c_d, N*sizeof(int), hipMemcpyDeviceToHost);
//print the results
for(int i=0; i<N; i++)
{
printf("%i+%i = %i\n",a_h[i], b_h[i], c_h[i]);
}
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
//clean up
hipFree(a_h);
hipFree(b_h);
hipFree(c_h);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "exc2a.hip"
.globl _Z30__device_stub__vectorAddKernelPiS_S_ # -- Begin function _Z30__device_stub__vectorAddKernelPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__vectorAddKernelPiS_S_,@function
_Z30__device_stub__vectorAddKernelPiS_S_: # @_Z30__device_stub__vectorAddKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15vectorAddKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__vectorAddKernelPiS_S_, .Lfunc_end0-_Z30__device_stub__vectorAddKernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $49296, %rsp # imm = 0xC090
.cfi_def_cfa_offset 49328
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 32912(%rsp,%rax,4)
movl %eax, 16528(%rsp,%rax,4)
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB1_1
# %bb.2:
leaq 64(%rsp), %r14
movl $16384, %esi # imm = 0x4000
movq %r14, %rdi
callq hipMalloc
leaq 56(%rsp), %r15
movl $16384, %esi # imm = 0x4000
movq %r15, %rdi
callq hipMalloc
leaq 24(%rsp), %rbx
movl $16384, %esi # imm = 0x4000
movq %rbx, %rdi
callq hipMalloc
leaq 32912(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $1, %ecx
callq hipMemcpy
leaq 16528(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $1, %ecx
callq hipMemcpy
leaq 144(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rdi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 32(%rsp)
leaq 128(%rsp), %rax
movq %rax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15vectorAddKernelPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32912(%rsp,%rbx,4), %esi
movl 16528(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4096, %rbx # imm = 0x1000
jne .LBB1_5
# %bb.6:
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 32912(%rsp), %rdi
callq hipFree
leaq 16528(%rsp), %rdi
callq hipFree
leaq 144(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $49296, %rsp # imm = 0xC090
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15vectorAddKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15vectorAddKernelPiS_S_,@object # @_Z15vectorAddKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z15vectorAddKernelPiS_S_
.p2align 3, 0x0
_Z15vectorAddKernelPiS_S_:
.quad _Z30__device_stub__vectorAddKernelPiS_S_
.size _Z15vectorAddKernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i+%i = %i\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to calculate results: %f ms.\n"
.size .L.str.1, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15vectorAddKernelPiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__vectorAddKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15vectorAddKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15vectorAddKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xfff, PT ; /* 0x00000fff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15vectorAddKernelPiS_S_
.globl _Z15vectorAddKernelPiS_S_
.p2align 8
.type _Z15vectorAddKernelPiS_S_,@function
_Z15vectorAddKernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15vectorAddKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15vectorAddKernelPiS_S_, .Lfunc_end0-_Z15vectorAddKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15vectorAddKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15vectorAddKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d3fb6_00000000-6_exc2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
.type _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_, @function
_Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15vectorAddKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_, .-_Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
.globl _Z15vectorAddKernelPiS_S_
.type _Z15vectorAddKernelPiS_S_, @function
_Z15vectorAddKernelPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15vectorAddKernelPiS_S_, .-_Z15vectorAddKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i+%i = %i\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time to calculate results: %f ms.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -49152(%rsp), %r11
.cfi_def_cfa 11, 49184
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $96, %rsp
.cfi_def_cfa_offset 49280
movq %fs:40, %rax
movq %rax, 49240(%rsp)
xorl %eax, %eax
movl $16, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
.L12:
movl %eax, 80(%rsp,%rax,4)
movl %eax, 16464(%rsp,%rax,4)
addq $1, %rax
cmpq $4096, %rax
jne .L12
leaq 16(%rsp), %r12
movl $16384, %esi
movq %r12, %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rbp
movl $16384, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rbx
movl $16384, %esi
movq %rbx, %rdi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $16384, %edx
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 16464(%rsp), %rsi
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 32848(%rsp), %rsi
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 32848(%rsp), %rdi
movl $2, %ecx
movl $16384, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 16464(%rsp,%rbx), %ecx
movl 80(%rsp,%rbx), %edx
movl 32848(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $16384, %rbx
jne .L14
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaFree@PLT
leaq 16464(%rsp), %rdi
call cudaFree@PLT
leaq 32848(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 49240(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $49248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z39__device_stub__Z15vectorAddKernelPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z15vectorAddKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vectorAddKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exc2a.hip"
.globl _Z30__device_stub__vectorAddKernelPiS_S_ # -- Begin function _Z30__device_stub__vectorAddKernelPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__vectorAddKernelPiS_S_,@function
_Z30__device_stub__vectorAddKernelPiS_S_: # @_Z30__device_stub__vectorAddKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15vectorAddKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__vectorAddKernelPiS_S_, .Lfunc_end0-_Z30__device_stub__vectorAddKernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $49296, %rsp # imm = 0xC090
.cfi_def_cfa_offset 49328
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 32912(%rsp,%rax,4)
movl %eax, 16528(%rsp,%rax,4)
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB1_1
# %bb.2:
leaq 64(%rsp), %r14
movl $16384, %esi # imm = 0x4000
movq %r14, %rdi
callq hipMalloc
leaq 56(%rsp), %r15
movl $16384, %esi # imm = 0x4000
movq %r15, %rdi
callq hipMalloc
leaq 24(%rsp), %rbx
movl $16384, %esi # imm = 0x4000
movq %rbx, %rdi
callq hipMalloc
leaq 32912(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $1, %ecx
callq hipMemcpy
leaq 16528(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $1, %ecx
callq hipMemcpy
leaq 144(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rdi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 32(%rsp)
leaq 128(%rsp), %rax
movq %rax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15vectorAddKernelPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32912(%rsp,%rbx,4), %esi
movl 16528(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4096, %rbx # imm = 0x1000
jne .LBB1_5
# %bb.6:
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 32912(%rsp), %rdi
callq hipFree
leaq 16528(%rsp), %rdi
callq hipFree
leaq 144(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $49296, %rsp # imm = 0xC090
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15vectorAddKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15vectorAddKernelPiS_S_,@object # @_Z15vectorAddKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z15vectorAddKernelPiS_S_
.p2align 3, 0x0
_Z15vectorAddKernelPiS_S_:
.quad _Z30__device_stub__vectorAddKernelPiS_S_
.size _Z15vectorAddKernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i+%i = %i\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to calculate results: %f ms.\n"
.size .L.str.1, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15vectorAddKernelPiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__vectorAddKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15vectorAddKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void KerCalcRidp(unsigned n,unsigned ini,unsigned idini,unsigned idfin,const unsigned *idp,unsigned *ridp)
{
unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Number of particle.
if(p<n){
p+=ini;
const unsigned id=idp[p];
if(idini<=id && id<idfin)ridp[id-idini]=p;
}
} | code for sm_80
Function : _Z11KerCalcRidpjjjjPKjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R5, R0, c[0x0][0x164], RZ ; /* 0x0000590000057a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R5, R0, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fcc00078e0000 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x004fc80003f06070 */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x16c], !P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0004706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R2, R2, -c[0x0][0x168], RZ ; /* 0x80005a0002027a10 */
/* 0x000fca0007ffe0ff */
/*00f0*/ IMAD.WIDE.U32 R2, R2, R0, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void KerCalcRidp(unsigned n,unsigned ini,unsigned idini,unsigned idfin,const unsigned *idp,unsigned *ridp)
{
unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Number of particle.
if(p<n){
p+=ini;
const unsigned id=idp[p];
if(idini<=id && id<idfin)ridp[id-idini]=p;
}
} | .file "tmpxft_001b4975_00000000-6_KerCalcRidp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj
.type _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj, @function
_Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11KerCalcRidpjjjjPKjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj, .-_Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj
.globl _Z11KerCalcRidpjjjjPKjPj
.type _Z11KerCalcRidpjjjjPKjPj, @function
_Z11KerCalcRidpjjjjPKjPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11KerCalcRidpjjjjPKjPj, .-_Z11KerCalcRidpjjjjPKjPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11KerCalcRidpjjjjPKjPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11KerCalcRidpjjjjPKjPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void KerCalcRidp(unsigned n,unsigned ini,unsigned idini,unsigned idfin,const unsigned *idp,unsigned *ridp)
{
unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Number of particle.
if(p<n){
p+=ini;
const unsigned id=idp[p];
if(idini<=id && id<idfin)ridp[id-idini]=p;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KerCalcRidp(unsigned n,unsigned ini,unsigned idini,unsigned idfin,const unsigned *idp,unsigned *ridp)
{
unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Number of particle.
if(p<n){
p+=ini;
const unsigned id=idp[p];
if(idini<=id && id<idfin)ridp[id-idini]=p;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KerCalcRidp(unsigned n,unsigned ini,unsigned idini,unsigned idfin,const unsigned *idp,unsigned *ridp)
{
unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Number of particle.
if(p<n){
p+=ini;
const unsigned id=idp[p];
if(idini<=id && id<idfin)ridp[id-idini]=p;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11KerCalcRidpjjjjPKjPj
.globl _Z11KerCalcRidpjjjjPKjPj
.p2align 8
.type _Z11KerCalcRidpjjjjPKjPj,@function
_Z11KerCalcRidpjjjjPKjPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v2
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cmp_gt_u32_e64 s2, s6, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x18
v_subrev_nc_u32_e32 v2, s3, v2
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11KerCalcRidpjjjjPKjPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11KerCalcRidpjjjjPKjPj, .Lfunc_end0-_Z11KerCalcRidpjjjjPKjPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11KerCalcRidpjjjjPKjPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11KerCalcRidpjjjjPKjPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KerCalcRidp(unsigned n,unsigned ini,unsigned idini,unsigned idfin,const unsigned *idp,unsigned *ridp)
{
unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Number of particle.
if(p<n){
p+=ini;
const unsigned id=idp[p];
if(idini<=id && id<idfin)ridp[id-idini]=p;
}
} | .text
.file "KerCalcRidp.hip"
.globl _Z26__device_stub__KerCalcRidpjjjjPKjPj # -- Begin function _Z26__device_stub__KerCalcRidpjjjjPKjPj
.p2align 4, 0x90
.type _Z26__device_stub__KerCalcRidpjjjjPKjPj,@function
_Z26__device_stub__KerCalcRidpjjjjPKjPj: # @_Z26__device_stub__KerCalcRidpjjjjPKjPj
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11KerCalcRidpjjjjPKjPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__KerCalcRidpjjjjPKjPj, .Lfunc_end0-_Z26__device_stub__KerCalcRidpjjjjPKjPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11KerCalcRidpjjjjPKjPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11KerCalcRidpjjjjPKjPj,@object # @_Z11KerCalcRidpjjjjPKjPj
.section .rodata,"a",@progbits
.globl _Z11KerCalcRidpjjjjPKjPj
.p2align 3, 0x0
_Z11KerCalcRidpjjjjPKjPj:
.quad _Z26__device_stub__KerCalcRidpjjjjPKjPj
.size _Z11KerCalcRidpjjjjPKjPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11KerCalcRidpjjjjPKjPj"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__KerCalcRidpjjjjPKjPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11KerCalcRidpjjjjPKjPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11KerCalcRidpjjjjPKjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R5, R0, c[0x0][0x164], RZ ; /* 0x0000590000057a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R5, R0, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fcc00078e0000 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x004fc80003f06070 */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x16c], !P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0004706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R2, R2, -c[0x0][0x168], RZ ; /* 0x80005a0002027a10 */
/* 0x000fca0007ffe0ff */
/*00f0*/ IMAD.WIDE.U32 R2, R2, R0, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11KerCalcRidpjjjjPKjPj
.globl _Z11KerCalcRidpjjjjPKjPj
.p2align 8
.type _Z11KerCalcRidpjjjjPKjPj,@function
_Z11KerCalcRidpjjjjPKjPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v2
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cmp_gt_u32_e64 s2, s6, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x18
v_subrev_nc_u32_e32 v2, s3, v2
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11KerCalcRidpjjjjPKjPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11KerCalcRidpjjjjPKjPj, .Lfunc_end0-_Z11KerCalcRidpjjjjPKjPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11KerCalcRidpjjjjPKjPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11KerCalcRidpjjjjPKjPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b4975_00000000-6_KerCalcRidp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj
.type _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj, @function
_Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11KerCalcRidpjjjjPKjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj, .-_Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj
.globl _Z11KerCalcRidpjjjjPKjPj
.type _Z11KerCalcRidpjjjjPKjPj, @function
_Z11KerCalcRidpjjjjPKjPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11KerCalcRidpjjjjPKjPjjjjjPKjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11KerCalcRidpjjjjPKjPj, .-_Z11KerCalcRidpjjjjPKjPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11KerCalcRidpjjjjPKjPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11KerCalcRidpjjjjPKjPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KerCalcRidp.hip"
.globl _Z26__device_stub__KerCalcRidpjjjjPKjPj # -- Begin function _Z26__device_stub__KerCalcRidpjjjjPKjPj
.p2align 4, 0x90
.type _Z26__device_stub__KerCalcRidpjjjjPKjPj,@function
_Z26__device_stub__KerCalcRidpjjjjPKjPj: # @_Z26__device_stub__KerCalcRidpjjjjPKjPj
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11KerCalcRidpjjjjPKjPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__KerCalcRidpjjjjPKjPj, .Lfunc_end0-_Z26__device_stub__KerCalcRidpjjjjPKjPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11KerCalcRidpjjjjPKjPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11KerCalcRidpjjjjPKjPj,@object # @_Z11KerCalcRidpjjjjPKjPj
.section .rodata,"a",@progbits
.globl _Z11KerCalcRidpjjjjPKjPj
.p2align 3, 0x0
_Z11KerCalcRidpjjjjPKjPj:
.quad _Z26__device_stub__KerCalcRidpjjjjPKjPj
.size _Z11KerCalcRidpjjjjPKjPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11KerCalcRidpjjjjPKjPj"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__KerCalcRidpjjjjPKjPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11KerCalcRidpjjjjPKjPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
xor_train.cu
Implementation of a XOR neural network in CUDA, including
network training using backpropagation.
Andrei de A. Formiga, 2012-03-31
*/
#include <stdio.h>
#include <stdlib.h>
#include <curand.h>
// constant for the RNG seed
#define SEED 419217ULL
//#define SEED 419229ULL
// maximum absolute value for random initialization of weights
#define MAX_ABS 1.5f
// learning rate
#define LRATE 0.75f
// total number of weights
#define NWEIGHTS 9
// number of active neurons
#define NEURONS 3
#define NEURONS_HIDDEN 2
#define NEURONS_OUT 1
// number of deltas (= number of neurons)
#define NDELTAS NEURONS
#define DELTAS_HIDDEN NEURONS_HIDDEN
#define DELTAS_OUT NEURONS_OUT
#define NCASES 4
#define INPUT_SIZE 2
#define HIDDEN_SIZE 2
#define OUTPUT_SIZE 1
// the network weights on the device
float *dev_weights;
const int l1w_off = 0; // offset into the weight array for layer 1 weights
const int l2w_off = 6; // offset into the weight array for layer 2 weights
// the random number generator
curandGenerator_t gen;
// device input
float *dev_in;
// hidden outputs and activations (on device)
float *dev_hidden;
// outputs and activations for final layer (on device)
float *dev_out;
// inputs
float inputs[] = { 0.0f, 0.0f, 0.0f, 1.0f,
1.0f, 0.0f, 1.0f, 1.0f };
const int ncases = 4;
const int input_size = 2;
const int hidden_size = 2;
const int out_size = 1;
// desired outputs
float outputs[] = { 0.1f, 0.9f, 0.9f, 0.1f };
float *dev_dout; // for the device
// deltas and derivatives (on the device)
float *dev_delta_h;
float *dev_delta_o;
float *dev_deriv;
// errors (device)
float *dev_err;
// sigmoid activation function
__device__ float asigmoid(float t)
{
return 1.0f / (1.0f + expf(-t));
}
__device__ float dsigmoid(float output)
{
return output * (1.0f - output);
}
// --- initialization kernels ---------------------------------------------
// make randomly generated weights in (0.0, 1.0] be in the
// interval from -max_abs to +max_abs
__global__ void normalize_weights(float *w, float max_abs)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
w[tid] = ((w[tid] - 0.5f) / 0.5f) * max_abs;
}
// random initialization for weights
// w must be an array of floats on the device
void random_initialize_weights(float *w, float max_abs, int nweights)
{
curandGenerator_t gen;
// create and initialize generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_XORWOW);
curandSetPseudoRandomGeneratorSeed(gen, SEED);
curandSetGeneratorOrdering(gen, CURAND_ORDERING_PSEUDO_SEEDED);
curandGenerateUniform(gen, w, nweights);
normalize_weights<<<1, nweights>>>(w, max_abs);
curandDestroyGenerator(gen);
}
// --- forward propagation kernels ----------------------------------------
// kernel for hidden layer
__global__ void forward_hidden(float *w, float *input, float *hidden)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int input_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l1w_off + threadIdx.x * 3; // 3 weights per neuron in hidden layer
float h;
h = w[toff] * 1.0f +
w[toff + 1] * input[input_ix] +
w[toff + 2] * input[input_ix+1];
hidden[tid] = asigmoid(h);
}
// kernel for output layer
__global__ void forward_output(float *w, float *hidden, float *output)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int hidden_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l2w_off + threadIdx.x; // 3 weights per neuron, but only 1 neuron
float o;
o = w[toff] * 1.0f +
w[toff+1] * hidden[hidden_ix] +
w[toff+2] * hidden[hidden_ix+1];
output[tid] = asigmoid(o);
}
// --- kernels for backpropagation ----------------------------------------
// launch grid: <<<N, 1>>> for N = number of cases, 1 output neuron
__global__ void deltas_output(float *output, float *expected_out, float *deltao, float *err)
{
// there's one delta for each output node
int tid = blockIdx.x * blockDim.x + threadIdx.x;
err[tid] = expected_out[tid] - output[tid];
deltao[tid] = -err[tid] * dsigmoid(output[tid]);
}
// launch grid: <<<N, 2>>> for N = number of cases, 2 hidden neurons
__global__ void deltas_hidden(float *hidden, float *w, float *deltah, float *deltao)
{
// tid is the index for deltah and hidden
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// oid is the corresponding index in the output layer
// there's only one node in output so 1 per block
int oid = blockIdx.x;
// wid is the index into the weights, taking into account the bias weight
int wid = l2w_off + threadIdx.x + 1;
deltah[tid] = w[wid] * deltao[oid] * dsigmoid(hidden[tid]);
}
// launch grid: <<<N, 6>>> for N cases, 6 weights for hidden layer
__global__ void derivs_hidden(float *input, float *deltah, float *deriv)
{
// weights per node (2 inputs + bias)
const int wpn = INPUT_SIZE + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l1w_off + threadIdx.x;
// delta index (3 weights per node: 2 inputs + bias)
int did = blockIdx.x * DELTAS_HIDDEN + (threadIdx.x / wpn);
// input index (3 weights per node)
int iid = blockIdx.x * INPUT_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float in = (threadIdx.x % wpn == 0? 1.0f : input[iid]);
deriv[wid] = deltah[did] * in;
}
// launch grid: <<<N, 3>>> for N cases, 3 weights for output layer
__global__ void derivs_output(float *hidden, float *deltao, float *deriv)
{
// weights per node (2 hidden neurons + bias)
const int wpn = NEURONS_HIDDEN + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l2w_off + threadIdx.x;
// delta index (3 weights per node)
int did = blockIdx.x * DELTAS_OUT + (threadIdx.x / wpn);
// hidden index (3 weights per node)
int hid = blockIdx.x * HIDDEN_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float h = (threadIdx.x % wpn == 0? 1.0f : hidden[hid]);
deriv[wid] = deltao[did] * h;
}
// <<<N, 9>>> for N cases, 9 derivs per case?
__global__ void sum_derivs(float *deriv)
{
}
// launch grid: <<<1, NWEIGHTS>>> for number of weights
__global__ void update_weights_nreduc(float *ws, float *deriv, float lrate)
{
float dE = 0.0f;
int wid = blockIdx.x * blockDim.x + threadIdx.x;
// sum all derivs for the same weight
for (int i = 0; i < NCASES; ++i)
dE += deriv[i * NWEIGHTS + wid];
// update weight
ws[wid] -= (lrate * dE);
}
// --- memory allocations and initialization ------------------------------
inline float* allocateFloatsDev(int n)
{
float *res;
if (cudaMalloc((void**) &res, n * sizeof(float)) != cudaSuccess) {
fprintf(stderr, "Could not allocate memory on the device\n");
exit(1);
}
return res;
}
void allocateDev(void)
{
// weights
dev_weights = allocateFloatsDev(NWEIGHTS);
// node values
dev_in = allocateFloatsDev(ncases * input_size);
dev_hidden = allocateFloatsDev(ncases * hidden_size);
dev_out = allocateFloatsDev(ncases * out_size);
// desired outputs and errors on device
dev_dout = allocateFloatsDev(ncases * out_size);
dev_err = allocateFloatsDev(ncases * out_size);
// deltas and derivatives
dev_delta_h = allocateFloatsDev(NEURONS_HIDDEN);
dev_delta_o = allocateFloatsDev(NEURONS_OUT);
dev_deriv = allocateFloatsDev(NWEIGHTS);
}
void freeDev(void)
{
// weights
cudaFree(dev_weights);
// node values
cudaFree(dev_in);
cudaFree(dev_hidden);
cudaFree(dev_out);
// desired outputs and errors
cudaFree(dev_dout);
cudaFree(dev_err);
// deltas and derivatives
cudaFree(dev_delta_h);
cudaFree(dev_deriv);
cudaFree(dev_delta_o);
}
// initialize memory on the device to run kernels
void memorySetup(void)
{
allocateDev();
// initialize weights
random_initialize_weights(dev_weights, MAX_ABS, NWEIGHTS);
// copy inputs and desired outputs
cudaMemcpy(dev_in, inputs, ncases * input_size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dout, outputs, ncases * out_size * sizeof(float), cudaMemcpyHostToDevice);
}
void printDevArray(float *devA, int length)
{
float *hostA;
hostA = (float*) malloc(length * sizeof(float));
cudaMemcpy(hostA, devA, length * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < length; ++i)
printf("%6.3f ", hostA[i]);
printf("\n");
}
// --- training -----------------------------------------------------------
float batch_train(int epochs, int calc_sse, int print_sse)
{
float err[NCASES * OUTPUT_SIZE];
float sse = 0.0f;
for (int e = 0; e < epochs; ++e) {
// forward propagation for all input cases
forward_hidden<<<4, 2>>>(dev_weights, dev_in, dev_hidden);
forward_output<<<4, 1>>>(dev_weights, dev_hidden, dev_out);
// printf("Outputs: ");
// printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// backprop
deltas_output<<<4, 1>>>(dev_out, dev_dout, dev_delta_o, dev_err);
deltas_hidden<<<4, 2>>>(dev_hidden, dev_weights, dev_delta_h, dev_delta_o);
// printf("Deltas (hidden): ");
// printDevArray(dev_delta_h, DELTAS_HIDDEN);
// printf("Deltas (output): ");
// printDevArray(dev_delta_o, DELTAS_OUT);
// calculate SSE for this trial
if (calc_sse) {
sse = 0.0f;
cudaMemcpy(err, dev_err, NCASES * OUTPUT_SIZE * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < NCASES * OUTPUT_SIZE; ++i) {
//printf("%6.3f ", err[i]);
sse += (err[i] * err[i]);
}
if (print_sse)
printf("SSE = %5.3f\n", sse);
}
// calculate derivatives
derivs_hidden<<<4, 6>>>(dev_in, dev_delta_h, dev_deriv);
derivs_output<<<4, 3>>>(dev_hidden, dev_delta_o, dev_deriv);
// update weights
update_weights_nreduc<<<1, NWEIGHTS>>>(dev_weights, dev_deriv, LRATE);
}
return sse;
}
void print_weights(void)
{
float weights[NWEIGHTS];
cudaMemcpy(weights, dev_weights, NWEIGHTS * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < NWEIGHTS; ++i)
printf("%6.4f ", weights[i]);
printf("\n");
}
// --- main ---------------------------------------------------------------
int main(int argc, char **argv)
{
float sse;
memorySetup();
// print the generated weights
printf("Randomly generated weights on the device:\n");
print_weights();
// do training
printf("Batch training with 5000 epochs...\n");
sse = batch_train(8000, 1, 0);
printf("Final SSE: %6.3f\n", sse);
printf("Outputs: ");
printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// weights after training
printf("Weights after training:\n");
print_weights();
freeDev();
return 0;
} | .file "tmpxft_001a1a4f_00000000-6_xor_train.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8asigmoidf
.type _Z8asigmoidf, @function
_Z8asigmoidf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8asigmoidf, .-_Z8asigmoidf
.globl _Z8dsigmoidf
.type _Z8dsigmoidf, @function
_Z8dsigmoidf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8dsigmoidf, .-_Z8dsigmoidf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Could not allocate memory on the device\n"
.text
.globl _Z11allocateDevv
.type _Z11allocateDevv, @function
_Z11allocateDevv:
.LFB2061:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $36, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movq (%rsp), %rax
movq %rax, dev_weights(%rip)
movq %rsp, %rdi
movl $32, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L20
movq (%rsp), %rax
movq %rax, dev_in(%rip)
movq %rsp, %rdi
movl $32, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L21
movq (%rsp), %rax
movq %rax, dev_hidden(%rip)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L22
movq (%rsp), %rax
movq %rax, dev_out(%rip)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L23
movq (%rsp), %rax
movq %rax, dev_dout(%rip)
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L24
movq (%rsp), %rax
movq %rax, dev_err(%rip)
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
movq (%rsp), %rax
movq %rax, dev_delta_h(%rip)
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
movq (%rsp), %rax
movq %rax, dev_delta_o(%rip)
movq %rsp, %rdi
movl $36, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movq (%rsp), %rax
movq %rax, dev_deriv(%rip)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z11allocateDevv, .-_Z11allocateDevv
.globl _Z7freeDevv
.type _Z7freeDevv, @function
_Z7freeDevv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq dev_weights(%rip), %rdi
call cudaFree@PLT
movq dev_in(%rip), %rdi
call cudaFree@PLT
movq dev_hidden(%rip), %rdi
call cudaFree@PLT
movq dev_out(%rip), %rdi
call cudaFree@PLT
movq dev_dout(%rip), %rdi
call cudaFree@PLT
movq dev_err(%rip), %rdi
call cudaFree@PLT
movq dev_delta_h(%rip), %rdi
call cudaFree@PLT
movq dev_deriv(%rip), %rdi
call cudaFree@PLT
movq dev_delta_o(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z7freeDevv, .-_Z7freeDevv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%6.3f "
.LC2:
.string "\n"
.text
.globl _Z13printDevArrayPfi
.type _Z13printDevArrayPfi, @function
_Z13printDevArrayPfi:
.LFB2064:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %ebx
movslq %esi, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L32
movq %rbp, %rbx
addq %r12, %rbp
leaq .LC1(%rip), %r12
.L33:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L33
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z13printDevArrayPfi, .-_Z13printDevArrayPfi
.section .rodata.str1.1
.LC3:
.string "%6.4f "
.text
.globl _Z13print_weightsv
.type _Z13print_weightsv, @function
_Z13print_weightsv:
.LFB2066:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $2, %ecx
movl $36, %edx
movq dev_weights(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %r12
leaq .LC3(%rip), %rbp
.L37:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L37
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z13print_weightsv, .-_Z13print_weightsv
.globl _Z38__device_stub__Z17normalize_weightsPffPff
.type _Z38__device_stub__Z17normalize_weightsPffPff, @function
_Z38__device_stub__Z17normalize_weightsPffPff:
.LFB2092:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17normalize_weightsPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z38__device_stub__Z17normalize_weightsPffPff, .-_Z38__device_stub__Z17normalize_weightsPffPff
.globl _Z17normalize_weightsPff
.type _Z17normalize_weightsPff, @function
_Z17normalize_weightsPff:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17normalize_weightsPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z17normalize_weightsPff, .-_Z17normalize_weightsPff
.globl _Z25random_initialize_weightsPffi
.type _Z25random_initialize_weightsPffi, @function
_Z25random_initialize_weightsPffi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movss %xmm0, 12(%rsp)
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $101, %esi
call curandCreateGenerator@PLT
movl $419217, %esi
movq 24(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movl $102, %esi
movq 24(%rsp), %rdi
call curandSetGeneratorOrdering@PLT
movslq %ebx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call curandGenerateUniform@PLT
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L51:
movq 24(%rsp), %rdi
call curandDestroyGenerator@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movss 12(%rsp), %xmm0
movq %rbp, %rdi
call _Z38__device_stub__Z17normalize_weightsPffPff
jmp .L51
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z25random_initialize_weightsPffi, .-_Z25random_initialize_weightsPffi
.globl _Z11memorySetupv
.type _Z11memorySetupv, @function
_Z11memorySetupv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z11allocateDevv
movl $9, %esi
movss .LC4(%rip), %xmm0
movq dev_weights(%rip), %rdi
call _Z25random_initialize_weightsPffi
movl $1, %ecx
movl $32, %edx
leaq inputs(%rip), %rsi
movq dev_in(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
leaq outputs(%rip), %rsi
movq dev_dout(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z11memorySetupv, .-_Z11memorySetupv
.globl _Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_
.type _Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_, @function
_Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14forward_hiddenPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_, .-_Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_
.globl _Z14forward_hiddenPfS_S_
.type _Z14forward_hiddenPfS_S_, @function
_Z14forward_hiddenPfS_S_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z14forward_hiddenPfS_S_, .-_Z14forward_hiddenPfS_S_
.globl _Z38__device_stub__Z14forward_outputPfS_S_PfS_S_
.type _Z38__device_stub__Z14forward_outputPfS_S_PfS_S_, @function
_Z38__device_stub__Z14forward_outputPfS_S_PfS_S_:
.LFB2096:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14forward_outputPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z38__device_stub__Z14forward_outputPfS_S_PfS_S_, .-_Z38__device_stub__Z14forward_outputPfS_S_PfS_S_
.globl _Z14forward_outputPfS_S_
.type _Z14forward_outputPfS_S_, @function
_Z14forward_outputPfS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14forward_outputPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z14forward_outputPfS_S_, .-_Z14forward_outputPfS_S_
.globl _Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_
.type _Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_, @function
_Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L78
.L74:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L79
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13deltas_outputPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L74
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_, .-_Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_
.globl _Z13deltas_outputPfS_S_S_
.type _Z13deltas_outputPfS_S_S_, @function
_Z13deltas_outputPfS_S_S_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z13deltas_outputPfS_S_S_, .-_Z13deltas_outputPfS_S_S_
.globl _Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_
.type _Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_, @function
_Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13deltas_hiddenPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L82
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_, .-_Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_
.globl _Z13deltas_hiddenPfS_S_S_
.type _Z13deltas_hiddenPfS_S_S_, @function
_Z13deltas_hiddenPfS_S_S_:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z13deltas_hiddenPfS_S_S_, .-_Z13deltas_hiddenPfS_S_S_
.globl _Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_
.type _Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_, @function
_Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_:
.LFB2102:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13derivs_hiddenPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_, .-_Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_
.globl _Z13derivs_hiddenPfS_S_
.type _Z13derivs_hiddenPfS_S_, @function
_Z13derivs_hiddenPfS_S_:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z13derivs_hiddenPfS_S_, .-_Z13derivs_hiddenPfS_S_
.globl _Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_
.type _Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_, @function
_Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_:
.LFB2104:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L102
.L98:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13derivs_outputPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L98
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_, .-_Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_
.globl _Z13derivs_outputPfS_S_
.type _Z13derivs_outputPfS_S_, @function
_Z13derivs_outputPfS_S_:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z13derivs_outputPfS_S_, .-_Z13derivs_outputPfS_S_
.globl _Z30__device_stub__Z10sum_derivsPfPf
.type _Z30__device_stub__Z10sum_derivsPfPf, @function
_Z30__device_stub__Z10sum_derivsPfPf:
.LFB2106:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L110
.L106:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L111
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10sum_derivsPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L106
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z30__device_stub__Z10sum_derivsPfPf, .-_Z30__device_stub__Z10sum_derivsPfPf
.globl _Z10sum_derivsPf
.type _Z10sum_derivsPf, @function
_Z10sum_derivsPf:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10sum_derivsPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z10sum_derivsPf, .-_Z10sum_derivsPf
.globl _Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f
.type _Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f, @function
_Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f:
.LFB2108:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L118
.L114:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L119
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L118:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21update_weights_nreducPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L114
.L119:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f, .-_Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f
.globl _Z21update_weights_nreducPfS_f
.type _Z21update_weights_nreducPfS_f, @function
_Z21update_weights_nreducPfS_f:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _Z21update_weights_nreducPfS_f, .-_Z21update_weights_nreducPfS_f
.section .rodata.str1.1
.LC6:
.string "SSE = %5.3f\n"
.text
.globl _Z11batch_trainiii
.type _Z11batch_trainiii, @function
_Z11batch_trainiii:
.LFB2065:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
testl %edi, %edi
jle .L135
movl %edi, %r12d
movl %esi, %r13d
movl %edx, %r14d
movl $0, %ebx
movl $0x00000000, 12(%rsp)
jmp .L133
.L139:
movq dev_hidden(%rip), %rdx
movq dev_in(%rip), %rsi
movq dev_weights(%rip), %rdi
call _Z38__device_stub__Z14forward_hiddenPfS_S_PfS_S_
jmp .L124
.L140:
movq dev_out(%rip), %rdx
movq dev_hidden(%rip), %rsi
movq dev_weights(%rip), %rdi
call _Z38__device_stub__Z14forward_outputPfS_S_PfS_S_
jmp .L125
.L141:
movq dev_err(%rip), %rcx
movq dev_delta_o(%rip), %rdx
movq dev_dout(%rip), %rsi
movq dev_out(%rip), %rdi
call _Z39__device_stub__Z13deltas_outputPfS_S_S_PfS_S_S_
jmp .L126
.L142:
movq dev_delta_o(%rip), %rcx
movq dev_delta_h(%rip), %rdx
movq dev_weights(%rip), %rsi
movq dev_hidden(%rip), %rdi
call _Z39__device_stub__Z13deltas_hiddenPfS_S_S_PfS_S_S_
jmp .L127
.L143:
leaq 48(%rsp), %rbp
movl $2, %ecx
movl $16, %edx
movq dev_err(%rip), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rax
leaq 64(%rsp), %rdx
movl $0x00000000, 12(%rsp)
.L129:
movss (%rax), %xmm0
mulss %xmm0, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L129
testl %r14d, %r14d
je .L128
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L128
.L144:
movq dev_deriv(%rip), %rdx
movq dev_delta_h(%rip), %rsi
movq dev_in(%rip), %rdi
call _Z37__device_stub__Z13derivs_hiddenPfS_S_PfS_S_
jmp .L130
.L145:
movq dev_deriv(%rip), %rdx
movq dev_delta_o(%rip), %rsi
movq dev_hidden(%rip), %rdi
call _Z37__device_stub__Z13derivs_outputPfS_S_PfS_S_
jmp .L131
.L132:
addl $1, %ebx
cmpl %ebx, %r12d
je .L122
.L133:
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L139
.L124:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L140
.L125:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L141
.L126:
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L142
.L127:
testl %r13d, %r13d
jne .L143
.L128:
movl $6, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L144
.L130:
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L145
.L131:
movl $9, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L132
movss .LC7(%rip), %xmm0
movq dev_deriv(%rip), %rsi
movq dev_weights(%rip), %rdi
call _Z44__device_stub__Z21update_weights_nreducPfS_fPfS_f
jmp .L132
.L135:
movl $0x00000000, 12(%rsp)
.L122:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L146
movss 12(%rsp), %xmm0
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L146:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z11batch_trainiii, .-_Z11batch_trainiii
.section .rodata.str1.8
.align 8
.LC8:
.string "Randomly generated weights on the device:\n"
.align 8
.LC9:
.string "Batch training with 5000 epochs...\n"
.section .rodata.str1.1
.LC10:
.string "Final SSE: %6.3f\n"
.LC11:
.string "Outputs: "
.LC12:
.string "Weights after training:\n"
.text
.globl main
.type main, @function
main:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z11memorySetupv
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z13print_weightsv
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edx
movl $1, %esi
movl $8000, %edi
call _Z11batch_trainiii
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %esi
movq dev_out(%rip), %rdi
call _Z13printDevArrayPfi
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z13print_weightsv
call _Z7freeDevv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC13:
.string "_Z21update_weights_nreducPfS_f"
.section .rodata.str1.1
.LC14:
.string "_Z10sum_derivsPf"
.LC15:
.string "_Z13derivs_outputPfS_S_"
.LC16:
.string "_Z13derivs_hiddenPfS_S_"
.LC17:
.string "_Z13deltas_hiddenPfS_S_S_"
.LC18:
.string "_Z13deltas_outputPfS_S_S_"
.LC19:
.string "_Z14forward_outputPfS_S_"
.LC20:
.string "_Z14forward_hiddenPfS_S_"
.LC21:
.string "_Z17normalize_weightsPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2111:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z21update_weights_nreducPfS_f(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_derivsPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z13derivs_outputPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z13derivs_hiddenPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z13deltas_hiddenPfS_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z13deltas_outputPfS_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z14forward_outputPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z14forward_hiddenPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z17normalize_weightsPff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_err
.bss
.align 8
.type dev_err, @object
.size dev_err, 8
dev_err:
.zero 8
.globl dev_deriv
.align 8
.type dev_deriv, @object
.size dev_deriv, 8
dev_deriv:
.zero 8
.globl dev_delta_o
.align 8
.type dev_delta_o, @object
.size dev_delta_o, 8
dev_delta_o:
.zero 8
.globl dev_delta_h
.align 8
.type dev_delta_h, @object
.size dev_delta_h, 8
dev_delta_h:
.zero 8
.globl dev_dout
.align 8
.type dev_dout, @object
.size dev_dout, 8
dev_dout:
.zero 8
.globl outputs
.data
.align 16
.type outputs, @object
.size outputs, 16
outputs:
.long 1036831949
.long 1063675494
.long 1063675494
.long 1036831949
.globl inputs
.align 32
.type inputs, @object
.size inputs, 32
inputs:
.long 0
.long 0
.long 0
.long 1065353216
.long 1065353216
.long 0
.long 1065353216
.long 1065353216
.globl dev_out
.bss
.align 8
.type dev_out, @object
.size dev_out, 8
dev_out:
.zero 8
.globl dev_hidden
.align 8
.type dev_hidden, @object
.size dev_hidden, 8
dev_hidden:
.zero 8
.globl dev_in
.align 8
.type dev_in, @object
.size dev_in, 8
dev_in:
.zero 8
.globl gen
.align 8
.type gen, @object
.size gen, 8
gen:
.zero 8
.globl dev_weights
.align 8
.type dev_weights, @object
.size dev_weights, 8
dev_weights:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1069547520
.align 4
.LC7:
.long 1061158912
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
xor_train.cu
Implementation of a XOR neural network in CUDA, including
network training using backpropagation.
Andrei de A. Formiga, 2012-03-31
*/
#include <stdio.h>
#include <stdlib.h>
#include <curand.h>
// constant for the RNG seed
#define SEED 419217ULL
//#define SEED 419229ULL
// maximum absolute value for random initialization of weights
#define MAX_ABS 1.5f
// learning rate
#define LRATE 0.75f
// total number of weights
#define NWEIGHTS 9
// number of active neurons
#define NEURONS 3
#define NEURONS_HIDDEN 2
#define NEURONS_OUT 1
// number of deltas (= number of neurons)
#define NDELTAS NEURONS
#define DELTAS_HIDDEN NEURONS_HIDDEN
#define DELTAS_OUT NEURONS_OUT
#define NCASES 4
#define INPUT_SIZE 2
#define HIDDEN_SIZE 2
#define OUTPUT_SIZE 1
// the network weights on the device
float *dev_weights;
const int l1w_off = 0; // offset into the weight array for layer 1 weights
const int l2w_off = 6; // offset into the weight array for layer 2 weights
// the random number generator
curandGenerator_t gen;
// device input
float *dev_in;
// hidden outputs and activations (on device)
float *dev_hidden;
// outputs and activations for final layer (on device)
float *dev_out;
// inputs
float inputs[] = { 0.0f, 0.0f, 0.0f, 1.0f,
1.0f, 0.0f, 1.0f, 1.0f };
const int ncases = 4;
const int input_size = 2;
const int hidden_size = 2;
const int out_size = 1;
// desired outputs
float outputs[] = { 0.1f, 0.9f, 0.9f, 0.1f };
float *dev_dout; // for the device
// deltas and derivatives (on the device)
float *dev_delta_h;
float *dev_delta_o;
float *dev_deriv;
// errors (device)
float *dev_err;
// sigmoid activation function
__device__ float asigmoid(float t)
{
return 1.0f / (1.0f + expf(-t));
}
__device__ float dsigmoid(float output)
{
return output * (1.0f - output);
}
// --- initialization kernels ---------------------------------------------
// make randomly generated weights in (0.0, 1.0] be in the
// interval from -max_abs to +max_abs
__global__ void normalize_weights(float *w, float max_abs)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
w[tid] = ((w[tid] - 0.5f) / 0.5f) * max_abs;
}
// random initialization for weights
// w must be an array of floats on the device
void random_initialize_weights(float *w, float max_abs, int nweights)
{
curandGenerator_t gen;
// create and initialize generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_XORWOW);
curandSetPseudoRandomGeneratorSeed(gen, SEED);
curandSetGeneratorOrdering(gen, CURAND_ORDERING_PSEUDO_SEEDED);
curandGenerateUniform(gen, w, nweights);
normalize_weights<<<1, nweights>>>(w, max_abs);
curandDestroyGenerator(gen);
}
// --- forward propagation kernels ----------------------------------------
// kernel for hidden layer
__global__ void forward_hidden(float *w, float *input, float *hidden)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int input_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l1w_off + threadIdx.x * 3; // 3 weights per neuron in hidden layer
float h;
h = w[toff] * 1.0f +
w[toff + 1] * input[input_ix] +
w[toff + 2] * input[input_ix+1];
hidden[tid] = asigmoid(h);
}
// kernel for output layer
__global__ void forward_output(float *w, float *hidden, float *output)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int hidden_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l2w_off + threadIdx.x; // 3 weights per neuron, but only 1 neuron
float o;
o = w[toff] * 1.0f +
w[toff+1] * hidden[hidden_ix] +
w[toff+2] * hidden[hidden_ix+1];
output[tid] = asigmoid(o);
}
// --- kernels for backpropagation ----------------------------------------
// launch grid: <<<N, 1>>> for N = number of cases, 1 output neuron
__global__ void deltas_output(float *output, float *expected_out, float *deltao, float *err)
{
// there's one delta for each output node
int tid = blockIdx.x * blockDim.x + threadIdx.x;
err[tid] = expected_out[tid] - output[tid];
deltao[tid] = -err[tid] * dsigmoid(output[tid]);
}
// launch grid: <<<N, 2>>> for N = number of cases, 2 hidden neurons
__global__ void deltas_hidden(float *hidden, float *w, float *deltah, float *deltao)
{
// tid is the index for deltah and hidden
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// oid is the corresponding index in the output layer
// there's only one node in output so 1 per block
int oid = blockIdx.x;
// wid is the index into the weights, taking into account the bias weight
int wid = l2w_off + threadIdx.x + 1;
deltah[tid] = w[wid] * deltao[oid] * dsigmoid(hidden[tid]);
}
// launch grid: <<<N, 6>>> for N cases, 6 weights for hidden layer
__global__ void derivs_hidden(float *input, float *deltah, float *deriv)
{
// weights per node (2 inputs + bias)
const int wpn = INPUT_SIZE + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l1w_off + threadIdx.x;
// delta index (3 weights per node: 2 inputs + bias)
int did = blockIdx.x * DELTAS_HIDDEN + (threadIdx.x / wpn);
// input index (3 weights per node)
int iid = blockIdx.x * INPUT_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float in = (threadIdx.x % wpn == 0? 1.0f : input[iid]);
deriv[wid] = deltah[did] * in;
}
// launch grid: <<<N, 3>>> for N cases, 3 weights for output layer
__global__ void derivs_output(float *hidden, float *deltao, float *deriv)
{
// weights per node (2 hidden neurons + bias)
const int wpn = NEURONS_HIDDEN + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l2w_off + threadIdx.x;
// delta index (3 weights per node)
int did = blockIdx.x * DELTAS_OUT + (threadIdx.x / wpn);
// hidden index (3 weights per node)
int hid = blockIdx.x * HIDDEN_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float h = (threadIdx.x % wpn == 0? 1.0f : hidden[hid]);
deriv[wid] = deltao[did] * h;
}
// <<<N, 9>>> for N cases, 9 derivs per case?
__global__ void sum_derivs(float *deriv)
{
}
// launch grid: <<<1, NWEIGHTS>>> for number of weights
__global__ void update_weights_nreduc(float *ws, float *deriv, float lrate)
{
float dE = 0.0f;
int wid = blockIdx.x * blockDim.x + threadIdx.x;
// sum all derivs for the same weight
for (int i = 0; i < NCASES; ++i)
dE += deriv[i * NWEIGHTS + wid];
// update weight
ws[wid] -= (lrate * dE);
}
// --- memory allocations and initialization ------------------------------
inline float* allocateFloatsDev(int n)
{
float *res;
if (cudaMalloc((void**) &res, n * sizeof(float)) != cudaSuccess) {
fprintf(stderr, "Could not allocate memory on the device\n");
exit(1);
}
return res;
}
void allocateDev(void)
{
// weights
dev_weights = allocateFloatsDev(NWEIGHTS);
// node values
dev_in = allocateFloatsDev(ncases * input_size);
dev_hidden = allocateFloatsDev(ncases * hidden_size);
dev_out = allocateFloatsDev(ncases * out_size);
// desired outputs and errors on device
dev_dout = allocateFloatsDev(ncases * out_size);
dev_err = allocateFloatsDev(ncases * out_size);
// deltas and derivatives
dev_delta_h = allocateFloatsDev(NEURONS_HIDDEN);
dev_delta_o = allocateFloatsDev(NEURONS_OUT);
dev_deriv = allocateFloatsDev(NWEIGHTS);
}
void freeDev(void)
{
// weights
cudaFree(dev_weights);
// node values
cudaFree(dev_in);
cudaFree(dev_hidden);
cudaFree(dev_out);
// desired outputs and errors
cudaFree(dev_dout);
cudaFree(dev_err);
// deltas and derivatives
cudaFree(dev_delta_h);
cudaFree(dev_deriv);
cudaFree(dev_delta_o);
}
// initialize memory on the device to run kernels
void memorySetup(void)
{
allocateDev();
// initialize weights
random_initialize_weights(dev_weights, MAX_ABS, NWEIGHTS);
// copy inputs and desired outputs
cudaMemcpy(dev_in, inputs, ncases * input_size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_dout, outputs, ncases * out_size * sizeof(float), cudaMemcpyHostToDevice);
}
void printDevArray(float *devA, int length)
{
float *hostA;
hostA = (float*) malloc(length * sizeof(float));
cudaMemcpy(hostA, devA, length * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < length; ++i)
printf("%6.3f ", hostA[i]);
printf("\n");
}
// --- training -----------------------------------------------------------
float batch_train(int epochs, int calc_sse, int print_sse)
{
float err[NCASES * OUTPUT_SIZE];
float sse = 0.0f;
for (int e = 0; e < epochs; ++e) {
// forward propagation for all input cases
forward_hidden<<<4, 2>>>(dev_weights, dev_in, dev_hidden);
forward_output<<<4, 1>>>(dev_weights, dev_hidden, dev_out);
// printf("Outputs: ");
// printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// backprop
deltas_output<<<4, 1>>>(dev_out, dev_dout, dev_delta_o, dev_err);
deltas_hidden<<<4, 2>>>(dev_hidden, dev_weights, dev_delta_h, dev_delta_o);
// printf("Deltas (hidden): ");
// printDevArray(dev_delta_h, DELTAS_HIDDEN);
// printf("Deltas (output): ");
// printDevArray(dev_delta_o, DELTAS_OUT);
// calculate SSE for this trial
if (calc_sse) {
sse = 0.0f;
cudaMemcpy(err, dev_err, NCASES * OUTPUT_SIZE * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < NCASES * OUTPUT_SIZE; ++i) {
//printf("%6.3f ", err[i]);
sse += (err[i] * err[i]);
}
if (print_sse)
printf("SSE = %5.3f\n", sse);
}
// calculate derivatives
derivs_hidden<<<4, 6>>>(dev_in, dev_delta_h, dev_deriv);
derivs_output<<<4, 3>>>(dev_hidden, dev_delta_o, dev_deriv);
// update weights
update_weights_nreduc<<<1, NWEIGHTS>>>(dev_weights, dev_deriv, LRATE);
}
return sse;
}
void print_weights(void)
{
float weights[NWEIGHTS];
cudaMemcpy(weights, dev_weights, NWEIGHTS * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < NWEIGHTS; ++i)
printf("%6.4f ", weights[i]);
printf("\n");
}
// --- main ---------------------------------------------------------------
int main(int argc, char **argv)
{
float sse;
memorySetup();
// print the generated weights
printf("Randomly generated weights on the device:\n");
print_weights();
// do training
printf("Batch training with 5000 epochs...\n");
sse = batch_train(8000, 1, 0);
printf("Final SSE: %6.3f\n", sse);
printf("Outputs: ");
printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// weights after training
printf("Weights after training:\n");
print_weights();
freeDev();
return 0;
} | /*
xor_train.cu
Implementation of a XOR neural network in CUDA, including
network training using backpropagation.
Andrei de A. Formiga, 2012-03-31
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
// constant for the RNG seed
#define SEED 419217ULL
//#define SEED 419229ULL
// maximum absolute value for random initialization of weights
#define MAX_ABS 1.5f
// learning rate
#define LRATE 0.75f
// total number of weights
#define NWEIGHTS 9
// number of active neurons
#define NEURONS 3
#define NEURONS_HIDDEN 2
#define NEURONS_OUT 1
// number of deltas (= number of neurons)
#define NDELTAS NEURONS
#define DELTAS_HIDDEN NEURONS_HIDDEN
#define DELTAS_OUT NEURONS_OUT
#define NCASES 4
#define INPUT_SIZE 2
#define HIDDEN_SIZE 2
#define OUTPUT_SIZE 1
// the network weights on the device
float *dev_weights;
const int l1w_off = 0; // offset into the weight array for layer 1 weights
const int l2w_off = 6; // offset into the weight array for layer 2 weights
// the random number generator
hiprandGenerator_t gen;
// device input
float *dev_in;
// hidden outputs and activations (on device)
float *dev_hidden;
// outputs and activations for final layer (on device)
float *dev_out;
// inputs
float inputs[] = { 0.0f, 0.0f, 0.0f, 1.0f,
1.0f, 0.0f, 1.0f, 1.0f };
const int ncases = 4;
const int input_size = 2;
const int hidden_size = 2;
const int out_size = 1;
// desired outputs
float outputs[] = { 0.1f, 0.9f, 0.9f, 0.1f };
float *dev_dout; // for the device
// deltas and derivatives (on the device)
float *dev_delta_h;
float *dev_delta_o;
float *dev_deriv;
// errors (device)
float *dev_err;
// sigmoid activation function
__device__ float asigmoid(float t)
{
return 1.0f / (1.0f + expf(-t));
}
__device__ float dsigmoid(float output)
{
return output * (1.0f - output);
}
// --- initialization kernels ---------------------------------------------
// make randomly generated weights in (0.0, 1.0] be in the
// interval from -max_abs to +max_abs
__global__ void normalize_weights(float *w, float max_abs)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
w[tid] = ((w[tid] - 0.5f) / 0.5f) * max_abs;
}
// random initialization for weights
// w must be an array of floats on the device
void random_initialize_weights(float *w, float max_abs, int nweights)
{
hiprandGenerator_t gen;
// create and initialize generator
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_XORWOW);
hiprandSetPseudoRandomGeneratorSeed(gen, SEED);
hiprandSetGeneratorOrdering(gen, HIPRAND_ORDERING_PSEUDO_SEEDED);
hiprandGenerateUniform(gen, w, nweights);
normalize_weights<<<1, nweights>>>(w, max_abs);
hiprandDestroyGenerator(gen);
}
// --- forward propagation kernels ----------------------------------------
// kernel for hidden layer
__global__ void forward_hidden(float *w, float *input, float *hidden)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int input_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l1w_off + threadIdx.x * 3; // 3 weights per neuron in hidden layer
float h;
h = w[toff] * 1.0f +
w[toff + 1] * input[input_ix] +
w[toff + 2] * input[input_ix+1];
hidden[tid] = asigmoid(h);
}
// kernel for output layer
__global__ void forward_output(float *w, float *hidden, float *output)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int hidden_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l2w_off + threadIdx.x; // 3 weights per neuron, but only 1 neuron
float o;
o = w[toff] * 1.0f +
w[toff+1] * hidden[hidden_ix] +
w[toff+2] * hidden[hidden_ix+1];
output[tid] = asigmoid(o);
}
// --- kernels for backpropagation ----------------------------------------
// launch grid: <<<N, 1>>> for N = number of cases, 1 output neuron
__global__ void deltas_output(float *output, float *expected_out, float *deltao, float *err)
{
// there's one delta for each output node
int tid = blockIdx.x * blockDim.x + threadIdx.x;
err[tid] = expected_out[tid] - output[tid];
deltao[tid] = -err[tid] * dsigmoid(output[tid]);
}
// launch grid: <<<N, 2>>> for N = number of cases, 2 hidden neurons
__global__ void deltas_hidden(float *hidden, float *w, float *deltah, float *deltao)
{
// tid is the index for deltah and hidden
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// oid is the corresponding index in the output layer
// there's only one node in output so 1 per block
int oid = blockIdx.x;
// wid is the index into the weights, taking into account the bias weight
int wid = l2w_off + threadIdx.x + 1;
deltah[tid] = w[wid] * deltao[oid] * dsigmoid(hidden[tid]);
}
// launch grid: <<<N, 6>>> for N cases, 6 weights for hidden layer
__global__ void derivs_hidden(float *input, float *deltah, float *deriv)
{
// weights per node (2 inputs + bias)
const int wpn = INPUT_SIZE + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l1w_off + threadIdx.x;
// delta index (3 weights per node: 2 inputs + bias)
int did = blockIdx.x * DELTAS_HIDDEN + (threadIdx.x / wpn);
// input index (3 weights per node)
int iid = blockIdx.x * INPUT_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float in = (threadIdx.x % wpn == 0? 1.0f : input[iid]);
deriv[wid] = deltah[did] * in;
}
// launch grid: <<<N, 3>>> for N cases, 3 weights for output layer
__global__ void derivs_output(float *hidden, float *deltao, float *deriv)
{
// weights per node (2 hidden neurons + bias)
const int wpn = NEURONS_HIDDEN + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l2w_off + threadIdx.x;
// delta index (3 weights per node)
int did = blockIdx.x * DELTAS_OUT + (threadIdx.x / wpn);
// hidden index (3 weights per node)
int hid = blockIdx.x * HIDDEN_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float h = (threadIdx.x % wpn == 0? 1.0f : hidden[hid]);
deriv[wid] = deltao[did] * h;
}
// <<<N, 9>>> for N cases, 9 derivs per case?
__global__ void sum_derivs(float *deriv)
{
}
// launch grid: <<<1, NWEIGHTS>>> for number of weights
__global__ void update_weights_nreduc(float *ws, float *deriv, float lrate)
{
float dE = 0.0f;
int wid = blockIdx.x * blockDim.x + threadIdx.x;
// sum all derivs for the same weight
for (int i = 0; i < NCASES; ++i)
dE += deriv[i * NWEIGHTS + wid];
// update weight
ws[wid] -= (lrate * dE);
}
// --- memory allocations and initialization ------------------------------
inline float* allocateFloatsDev(int n)
{
float *res;
if (hipMalloc((void**) &res, n * sizeof(float)) != hipSuccess) {
fprintf(stderr, "Could not allocate memory on the device\n");
exit(1);
}
return res;
}
void allocateDev(void)
{
// weights
dev_weights = allocateFloatsDev(NWEIGHTS);
// node values
dev_in = allocateFloatsDev(ncases * input_size);
dev_hidden = allocateFloatsDev(ncases * hidden_size);
dev_out = allocateFloatsDev(ncases * out_size);
// desired outputs and errors on device
dev_dout = allocateFloatsDev(ncases * out_size);
dev_err = allocateFloatsDev(ncases * out_size);
// deltas and derivatives
dev_delta_h = allocateFloatsDev(NEURONS_HIDDEN);
dev_delta_o = allocateFloatsDev(NEURONS_OUT);
dev_deriv = allocateFloatsDev(NWEIGHTS);
}
void freeDev(void)
{
// weights
hipFree(dev_weights);
// node values
hipFree(dev_in);
hipFree(dev_hidden);
hipFree(dev_out);
// desired outputs and errors
hipFree(dev_dout);
hipFree(dev_err);
// deltas and derivatives
hipFree(dev_delta_h);
hipFree(dev_deriv);
hipFree(dev_delta_o);
}
// initialize memory on the device to run kernels
void memorySetup(void)
{
allocateDev();
// initialize weights
random_initialize_weights(dev_weights, MAX_ABS, NWEIGHTS);
// copy inputs and desired outputs
hipMemcpy(dev_in, inputs, ncases * input_size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_dout, outputs, ncases * out_size * sizeof(float), hipMemcpyHostToDevice);
}
void printDevArray(float *devA, int length)
{
float *hostA;
hostA = (float*) malloc(length * sizeof(float));
hipMemcpy(hostA, devA, length * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < length; ++i)
printf("%6.3f ", hostA[i]);
printf("\n");
}
// --- training -----------------------------------------------------------
float batch_train(int epochs, int calc_sse, int print_sse)
{
float err[NCASES * OUTPUT_SIZE];
float sse = 0.0f;
for (int e = 0; e < epochs; ++e) {
// forward propagation for all input cases
forward_hidden<<<4, 2>>>(dev_weights, dev_in, dev_hidden);
forward_output<<<4, 1>>>(dev_weights, dev_hidden, dev_out);
// printf("Outputs: ");
// printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// backprop
deltas_output<<<4, 1>>>(dev_out, dev_dout, dev_delta_o, dev_err);
deltas_hidden<<<4, 2>>>(dev_hidden, dev_weights, dev_delta_h, dev_delta_o);
// printf("Deltas (hidden): ");
// printDevArray(dev_delta_h, DELTAS_HIDDEN);
// printf("Deltas (output): ");
// printDevArray(dev_delta_o, DELTAS_OUT);
// calculate SSE for this trial
if (calc_sse) {
sse = 0.0f;
hipMemcpy(err, dev_err, NCASES * OUTPUT_SIZE * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < NCASES * OUTPUT_SIZE; ++i) {
//printf("%6.3f ", err[i]);
sse += (err[i] * err[i]);
}
if (print_sse)
printf("SSE = %5.3f\n", sse);
}
// calculate derivatives
derivs_hidden<<<4, 6>>>(dev_in, dev_delta_h, dev_deriv);
derivs_output<<<4, 3>>>(dev_hidden, dev_delta_o, dev_deriv);
// update weights
update_weights_nreduc<<<1, NWEIGHTS>>>(dev_weights, dev_deriv, LRATE);
}
return sse;
}
void print_weights(void)
{
float weights[NWEIGHTS];
hipMemcpy(weights, dev_weights, NWEIGHTS * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < NWEIGHTS; ++i)
printf("%6.4f ", weights[i]);
printf("\n");
}
// --- main ---------------------------------------------------------------
int main(int argc, char **argv)
{
float sse;
memorySetup();
// print the generated weights
printf("Randomly generated weights on the device:\n");
print_weights();
// do training
printf("Batch training with 5000 epochs...\n");
sse = batch_train(8000, 1, 0);
printf("Final SSE: %6.3f\n", sse);
printf("Outputs: ");
printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// weights after training
printf("Weights after training:\n");
print_weights();
freeDev();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
xor_train.cu
Implementation of a XOR neural network in CUDA, including
network training using backpropagation.
Andrei de A. Formiga, 2012-03-31
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
// constant for the RNG seed
#define SEED 419217ULL
//#define SEED 419229ULL
// maximum absolute value for random initialization of weights
#define MAX_ABS 1.5f
// learning rate
#define LRATE 0.75f
// total number of weights
#define NWEIGHTS 9
// number of active neurons
#define NEURONS 3
#define NEURONS_HIDDEN 2
#define NEURONS_OUT 1
// number of deltas (= number of neurons)
#define NDELTAS NEURONS
#define DELTAS_HIDDEN NEURONS_HIDDEN
#define DELTAS_OUT NEURONS_OUT
#define NCASES 4
#define INPUT_SIZE 2
#define HIDDEN_SIZE 2
#define OUTPUT_SIZE 1
// the network weights on the device
float *dev_weights;
const int l1w_off = 0; // offset into the weight array for layer 1 weights
const int l2w_off = 6; // offset into the weight array for layer 2 weights
// the random number generator
hiprandGenerator_t gen;
// device input
float *dev_in;
// hidden outputs and activations (on device)
float *dev_hidden;
// outputs and activations for final layer (on device)
float *dev_out;
// inputs
float inputs[] = { 0.0f, 0.0f, 0.0f, 1.0f,
1.0f, 0.0f, 1.0f, 1.0f };
const int ncases = 4;
const int input_size = 2;
const int hidden_size = 2;
const int out_size = 1;
// desired outputs
float outputs[] = { 0.1f, 0.9f, 0.9f, 0.1f };
float *dev_dout; // for the device
// deltas and derivatives (on the device)
float *dev_delta_h;
float *dev_delta_o;
float *dev_deriv;
// errors (device)
float *dev_err;
// sigmoid activation function
__device__ float asigmoid(float t)
{
return 1.0f / (1.0f + expf(-t));
}
__device__ float dsigmoid(float output)
{
return output * (1.0f - output);
}
// --- initialization kernels ---------------------------------------------
// make randomly generated weights in (0.0, 1.0] be in the
// interval from -max_abs to +max_abs
__global__ void normalize_weights(float *w, float max_abs)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
w[tid] = ((w[tid] - 0.5f) / 0.5f) * max_abs;
}
// random initialization for weights
// w must be an array of floats on the device
void random_initialize_weights(float *w, float max_abs, int nweights)
{
hiprandGenerator_t gen;
// create and initialize generator
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_XORWOW);
hiprandSetPseudoRandomGeneratorSeed(gen, SEED);
hiprandSetGeneratorOrdering(gen, HIPRAND_ORDERING_PSEUDO_SEEDED);
hiprandGenerateUniform(gen, w, nweights);
normalize_weights<<<1, nweights>>>(w, max_abs);
hiprandDestroyGenerator(gen);
}
// --- forward propagation kernels ----------------------------------------
// kernel for hidden layer
__global__ void forward_hidden(float *w, float *input, float *hidden)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int input_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l1w_off + threadIdx.x * 3; // 3 weights per neuron in hidden layer
float h;
h = w[toff] * 1.0f +
w[toff + 1] * input[input_ix] +
w[toff + 2] * input[input_ix+1];
hidden[tid] = asigmoid(h);
}
// kernel for output layer
__global__ void forward_output(float *w, float *hidden, float *output)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int hidden_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l2w_off + threadIdx.x; // 3 weights per neuron, but only 1 neuron
float o;
o = w[toff] * 1.0f +
w[toff+1] * hidden[hidden_ix] +
w[toff+2] * hidden[hidden_ix+1];
output[tid] = asigmoid(o);
}
// --- kernels for backpropagation ----------------------------------------
// launch grid: <<<N, 1>>> for N = number of cases, 1 output neuron
__global__ void deltas_output(float *output, float *expected_out, float *deltao, float *err)
{
// there's one delta for each output node
int tid = blockIdx.x * blockDim.x + threadIdx.x;
err[tid] = expected_out[tid] - output[tid];
deltao[tid] = -err[tid] * dsigmoid(output[tid]);
}
// launch grid: <<<N, 2>>> for N = number of cases, 2 hidden neurons
__global__ void deltas_hidden(float *hidden, float *w, float *deltah, float *deltao)
{
// tid is the index for deltah and hidden
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// oid is the corresponding index in the output layer
// there's only one node in output so 1 per block
int oid = blockIdx.x;
// wid is the index into the weights, taking into account the bias weight
int wid = l2w_off + threadIdx.x + 1;
deltah[tid] = w[wid] * deltao[oid] * dsigmoid(hidden[tid]);
}
// launch grid: <<<N, 6>>> for N cases, 6 weights for hidden layer
__global__ void derivs_hidden(float *input, float *deltah, float *deriv)
{
// weights per node (2 inputs + bias)
const int wpn = INPUT_SIZE + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l1w_off + threadIdx.x;
// delta index (3 weights per node: 2 inputs + bias)
int did = blockIdx.x * DELTAS_HIDDEN + (threadIdx.x / wpn);
// input index (3 weights per node)
int iid = blockIdx.x * INPUT_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float in = (threadIdx.x % wpn == 0? 1.0f : input[iid]);
deriv[wid] = deltah[did] * in;
}
// launch grid: <<<N, 3>>> for N cases, 3 weights for output layer
__global__ void derivs_output(float *hidden, float *deltao, float *deriv)
{
// weights per node (2 hidden neurons + bias)
const int wpn = NEURONS_HIDDEN + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l2w_off + threadIdx.x;
// delta index (3 weights per node)
int did = blockIdx.x * DELTAS_OUT + (threadIdx.x / wpn);
// hidden index (3 weights per node)
int hid = blockIdx.x * HIDDEN_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float h = (threadIdx.x % wpn == 0? 1.0f : hidden[hid]);
deriv[wid] = deltao[did] * h;
}
// <<<N, 9>>> for N cases, 9 derivs per case?
__global__ void sum_derivs(float *deriv)
{
}
// launch grid: <<<1, NWEIGHTS>>> for number of weights
__global__ void update_weights_nreduc(float *ws, float *deriv, float lrate)
{
float dE = 0.0f;
int wid = blockIdx.x * blockDim.x + threadIdx.x;
// sum all derivs for the same weight
for (int i = 0; i < NCASES; ++i)
dE += deriv[i * NWEIGHTS + wid];
// update weight
ws[wid] -= (lrate * dE);
}
// --- memory allocations and initialization ------------------------------
inline float* allocateFloatsDev(int n)
{
float *res;
if (hipMalloc((void**) &res, n * sizeof(float)) != hipSuccess) {
fprintf(stderr, "Could not allocate memory on the device\n");
exit(1);
}
return res;
}
void allocateDev(void)
{
// weights
dev_weights = allocateFloatsDev(NWEIGHTS);
// node values
dev_in = allocateFloatsDev(ncases * input_size);
dev_hidden = allocateFloatsDev(ncases * hidden_size);
dev_out = allocateFloatsDev(ncases * out_size);
// desired outputs and errors on device
dev_dout = allocateFloatsDev(ncases * out_size);
dev_err = allocateFloatsDev(ncases * out_size);
// deltas and derivatives
dev_delta_h = allocateFloatsDev(NEURONS_HIDDEN);
dev_delta_o = allocateFloatsDev(NEURONS_OUT);
dev_deriv = allocateFloatsDev(NWEIGHTS);
}
void freeDev(void)
{
// weights
hipFree(dev_weights);
// node values
hipFree(dev_in);
hipFree(dev_hidden);
hipFree(dev_out);
// desired outputs and errors
hipFree(dev_dout);
hipFree(dev_err);
// deltas and derivatives
hipFree(dev_delta_h);
hipFree(dev_deriv);
hipFree(dev_delta_o);
}
// initialize memory on the device to run kernels
void memorySetup(void)
{
allocateDev();
// initialize weights
random_initialize_weights(dev_weights, MAX_ABS, NWEIGHTS);
// copy inputs and desired outputs
hipMemcpy(dev_in, inputs, ncases * input_size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_dout, outputs, ncases * out_size * sizeof(float), hipMemcpyHostToDevice);
}
void printDevArray(float *devA, int length)
{
float *hostA;
hostA = (float*) malloc(length * sizeof(float));
hipMemcpy(hostA, devA, length * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < length; ++i)
printf("%6.3f ", hostA[i]);
printf("\n");
}
// --- training -----------------------------------------------------------
float batch_train(int epochs, int calc_sse, int print_sse)
{
float err[NCASES * OUTPUT_SIZE];
float sse = 0.0f;
for (int e = 0; e < epochs; ++e) {
// forward propagation for all input cases
forward_hidden<<<4, 2>>>(dev_weights, dev_in, dev_hidden);
forward_output<<<4, 1>>>(dev_weights, dev_hidden, dev_out);
// printf("Outputs: ");
// printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// backprop
deltas_output<<<4, 1>>>(dev_out, dev_dout, dev_delta_o, dev_err);
deltas_hidden<<<4, 2>>>(dev_hidden, dev_weights, dev_delta_h, dev_delta_o);
// printf("Deltas (hidden): ");
// printDevArray(dev_delta_h, DELTAS_HIDDEN);
// printf("Deltas (output): ");
// printDevArray(dev_delta_o, DELTAS_OUT);
// calculate SSE for this trial
if (calc_sse) {
sse = 0.0f;
hipMemcpy(err, dev_err, NCASES * OUTPUT_SIZE * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < NCASES * OUTPUT_SIZE; ++i) {
//printf("%6.3f ", err[i]);
sse += (err[i] * err[i]);
}
if (print_sse)
printf("SSE = %5.3f\n", sse);
}
// calculate derivatives
derivs_hidden<<<4, 6>>>(dev_in, dev_delta_h, dev_deriv);
derivs_output<<<4, 3>>>(dev_hidden, dev_delta_o, dev_deriv);
// update weights
update_weights_nreduc<<<1, NWEIGHTS>>>(dev_weights, dev_deriv, LRATE);
}
return sse;
}
void print_weights(void)
{
float weights[NWEIGHTS];
hipMemcpy(weights, dev_weights, NWEIGHTS * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < NWEIGHTS; ++i)
printf("%6.4f ", weights[i]);
printf("\n");
}
// --- main ---------------------------------------------------------------
int main(int argc, char **argv)
{
float sse;
memorySetup();
// print the generated weights
printf("Randomly generated weights on the device:\n");
print_weights();
// do training
printf("Batch training with 5000 epochs...\n");
sse = batch_train(8000, 1, 0);
printf("Final SSE: %6.3f\n", sse);
printf("Outputs: ");
printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// weights after training
printf("Weights after training:\n");
print_weights();
freeDev();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17normalize_weightsPff
.globl _Z17normalize_weightsPff
.p2align 8
.type _Z17normalize_weightsPff,@function
_Z17normalize_weightsPff:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, -0.5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v2
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17normalize_weightsPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17normalize_weightsPff, .Lfunc_end0-_Z17normalize_weightsPff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14forward_hiddenPfS_S_
.globl _Z14forward_hiddenPfS_S_
.p2align 8
.type _Z14forward_hiddenPfS_S_,@function
_Z14forward_hiddenPfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mul_u32_u24_e32 v1, 3, v0
s_load_b32 s8, s[0:1], 0x24
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(0)
global_load_b96 v[1:3], v1, s[4:5]
s_lshl_b64 s[4:5], s[0:1], 2
s_and_b32 s8, s8, 0xffff
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
s_or_b32 s0, s0, 1
s_load_b32 s4, s[4:5], 0x0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v1, s4, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, s0, v3
v_mul_f32_e32 v2, 0xbfb8aa3b, v1
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v3, v1, 0xbfb8aa3b, -v2
v_rndne_f32_e32 v4, v2
v_dual_fmamk_f32 v3, v1, 0xb2a5705f, v3 :: v_dual_sub_f32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v2, v3
v_cvt_i32_f32_e32 v3, v4
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v1
v_cndmask_b32_e32 v1, 0x7f800000, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v1
v_div_scale_f32 v4, null, v3, v3, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v4, v5, 1.0
v_fmac_f32_e32 v5, v1, v5
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, v6, v5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v4, v7, v6
v_div_fmas_f32 v4, v0, v5, v7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, v3, 1.0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14forward_hiddenPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14forward_hiddenPfS_S_, .Lfunc_end1-_Z14forward_hiddenPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14forward_outputPfS_S_
.globl _Z14forward_outputPfS_S_
.p2align 8
.type _Z14forward_outputPfS_S_,@function
_Z14forward_outputPfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s8, s[0:1], 0x24
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_waitcnt lgkmcnt(0)
global_load_b96 v[1:3], v1, s[4:5] offset:24
s_lshl_b64 s[4:5], s[0:1], 2
s_and_b32 s8, s8, 0xffff
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
s_or_b32 s0, s0, 1
s_load_b32 s4, s[4:5], 0x0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v1, s4, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, s0, v3
v_mul_f32_e32 v2, 0xbfb8aa3b, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v3, v1, 0xbfb8aa3b, -v2
v_rndne_f32_e32 v4, v2
v_sub_f32_e32 v2, v2, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v1, 0xb2a5705f, v3
v_add_f32_e32 v2, v2, v3
v_cvt_i32_f32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v2, v3
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x7f800000, v2, vcc_lo
v_add_f32_e32 v3, 1.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v5, v1, v5
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v0, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v0, v5, v7
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_div_fixup_f32 v2, v4, v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14forward_outputPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14forward_outputPfS_S_, .Lfunc_end2-_Z14forward_outputPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13deltas_outputPfS_S_S_
.globl _Z13deltas_outputPfS_S_S_
.p2align 8
.type _Z13deltas_outputPfS_S_S_,@function
_Z13deltas_outputPfS_S_S_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v7
global_store_b32 v[2:3], v6, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
v_mul_f32_e64 v2, v2, -v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13deltas_outputPfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z13deltas_outputPfS_S_S_, .Lfunc_end3-_Z13deltas_outputPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13deltas_hiddenPfS_S_S_
.globl _Z13deltas_hiddenPfS_S_S_
.p2align 8
.type _Z13deltas_hiddenPfS_S_S_,@function
_Z13deltas_hiddenPfS_S_S_:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_mov_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s9, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s8, s9, v[0:1]
v_lshlrev_b32_e32 v0, 2, v0
s_ashr_i32 s9, s15, 31
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_lshl_b64 s[0:1], s[8:9], 2
global_load_b32 v3, v[3:4], off
global_load_b32 v0, v0, s[2:3] offset:28
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(1)
v_sub_f32_e32 v4, 1.0, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v4
v_mul_f32_e32 v3, v0, v3
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13deltas_hiddenPfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z13deltas_hiddenPfS_S_S_, .Lfunc_end4-_Z13deltas_hiddenPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13derivs_hiddenPfS_S_
.globl _Z13derivs_hiddenPfS_S_
.p2align 8
.type _Z13derivs_hiddenPfS_S_,@function
_Z13derivs_hiddenPfS_S_:
v_mul_hi_u32 v2, v0, 0x55555556
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, 3, v2
v_sub_nc_u32_e32 v3, v0, v1
v_mov_b32_e32 v1, 1.0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ne_u32_e32 0, v3
s_cbranch_execz .LBB5_2
s_load_b64 s[4:5], s[0:1], 0x0
s_lshl_b32 s3, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, s3, -1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v1, v[3:4], off
.LBB5_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshl_add_u32 v2, s15, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[2:3], null, s15, 9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v1, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13derivs_hiddenPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z13derivs_hiddenPfS_S_, .Lfunc_end5-_Z13derivs_hiddenPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13derivs_outputPfS_S_
.globl _Z13derivs_outputPfS_S_
.p2align 8
.type _Z13derivs_outputPfS_S_,@function
_Z13derivs_outputPfS_S_:
v_mul_hi_u32 v2, v0, 0x55555556
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, 3, v2
v_sub_nc_u32_e32 v3, v0, v1
v_mov_b32_e32 v1, 1.0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ne_u32_e32 0, v3
s_cbranch_execz .LBB6_2
s_load_b64 s[4:5], s[0:1], 0x0
s_lshl_b32 s3, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, s3, -1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v1, v[3:4], off
.LBB6_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x8
v_add_nc_u32_e32 v2, s15, v2
s_mul_i32 s15, s15, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_add3_u32 v2, v0, s15, 6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v1, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13derivs_outputPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z13derivs_outputPfS_S_, .Lfunc_end6-_Z13derivs_outputPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10sum_derivsPf
.globl _Z10sum_derivsPf
.p2align 8
.type _Z10sum_derivsPf,@function
_Z10sum_derivsPf:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_derivsPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end7:
.size _Z10sum_derivsPf, .Lfunc_end7-_Z10sum_derivsPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21update_weights_nreducPfS_f
.globl _Z21update_weights_nreducPfS_f
.p2align 8
.type _Z21update_weights_nreducPfS_f,@function
_Z21update_weights_nreducPfS_f:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
.LBB8_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s4, v1
s_add_i32 s4, s4, 9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 36
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
s_cbranch_scc0 .LBB8_1
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_fma_f32 v0, -v0, s0, v3
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21update_weights_nreducPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end8:
.size _Z21update_weights_nreducPfS_f, .Lfunc_end8-_Z21update_weights_nreducPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17normalize_weightsPff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17normalize_weightsPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14forward_hiddenPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14forward_hiddenPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14forward_outputPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14forward_outputPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13deltas_outputPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13deltas_outputPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13deltas_hiddenPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13deltas_hiddenPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13derivs_hiddenPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13derivs_hiddenPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13derivs_outputPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13derivs_outputPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_derivsPf
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10sum_derivsPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21update_weights_nreducPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21update_weights_nreducPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
xor_train.cu
Implementation of a XOR neural network in CUDA, including
network training using backpropagation.
Andrei de A. Formiga, 2012-03-31
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
// constant for the RNG seed
#define SEED 419217ULL
//#define SEED 419229ULL
// maximum absolute value for random initialization of weights
#define MAX_ABS 1.5f
// learning rate
#define LRATE 0.75f
// total number of weights
#define NWEIGHTS 9
// number of active neurons
#define NEURONS 3
#define NEURONS_HIDDEN 2
#define NEURONS_OUT 1
// number of deltas (= number of neurons)
#define NDELTAS NEURONS
#define DELTAS_HIDDEN NEURONS_HIDDEN
#define DELTAS_OUT NEURONS_OUT
#define NCASES 4
#define INPUT_SIZE 2
#define HIDDEN_SIZE 2
#define OUTPUT_SIZE 1
// the network weights on the device
float *dev_weights;
const int l1w_off = 0; // offset into the weight array for layer 1 weights
const int l2w_off = 6; // offset into the weight array for layer 2 weights
// the random number generator
hiprandGenerator_t gen;
// device input
float *dev_in;
// hidden outputs and activations (on device)
float *dev_hidden;
// outputs and activations for final layer (on device)
float *dev_out;
// inputs
float inputs[] = { 0.0f, 0.0f, 0.0f, 1.0f,
1.0f, 0.0f, 1.0f, 1.0f };
const int ncases = 4;
const int input_size = 2;
const int hidden_size = 2;
const int out_size = 1;
// desired outputs
float outputs[] = { 0.1f, 0.9f, 0.9f, 0.1f };
float *dev_dout; // for the device
// deltas and derivatives (on the device)
float *dev_delta_h;
float *dev_delta_o;
float *dev_deriv;
// errors (device)
float *dev_err;
// sigmoid activation function
__device__ float asigmoid(float t)
{
return 1.0f / (1.0f + expf(-t));
}
__device__ float dsigmoid(float output)
{
return output * (1.0f - output);
}
// --- initialization kernels ---------------------------------------------
// make randomly generated weights in (0.0, 1.0] be in the
// interval from -max_abs to +max_abs
__global__ void normalize_weights(float *w, float max_abs)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
w[tid] = ((w[tid] - 0.5f) / 0.5f) * max_abs;
}
// random initialization for weights
// w must be an array of floats on the device
void random_initialize_weights(float *w, float max_abs, int nweights)
{
hiprandGenerator_t gen;
// create and initialize generator
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_XORWOW);
hiprandSetPseudoRandomGeneratorSeed(gen, SEED);
hiprandSetGeneratorOrdering(gen, HIPRAND_ORDERING_PSEUDO_SEEDED);
hiprandGenerateUniform(gen, w, nweights);
normalize_weights<<<1, nweights>>>(w, max_abs);
hiprandDestroyGenerator(gen);
}
// --- forward propagation kernels ----------------------------------------
// kernel for hidden layer
__global__ void forward_hidden(float *w, float *input, float *hidden)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int input_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l1w_off + threadIdx.x * 3; // 3 weights per neuron in hidden layer
float h;
h = w[toff] * 1.0f +
w[toff + 1] * input[input_ix] +
w[toff + 2] * input[input_ix+1];
hidden[tid] = asigmoid(h);
}
// kernel for output layer
__global__ void forward_output(float *w, float *hidden, float *output)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int hidden_ix = blockIdx.x * 2; // 2 neurons in the previous layer
int toff = l2w_off + threadIdx.x; // 3 weights per neuron, but only 1 neuron
float o;
o = w[toff] * 1.0f +
w[toff+1] * hidden[hidden_ix] +
w[toff+2] * hidden[hidden_ix+1];
output[tid] = asigmoid(o);
}
// --- kernels for backpropagation ----------------------------------------
// launch grid: <<<N, 1>>> for N = number of cases, 1 output neuron
__global__ void deltas_output(float *output, float *expected_out, float *deltao, float *err)
{
// there's one delta for each output node
int tid = blockIdx.x * blockDim.x + threadIdx.x;
err[tid] = expected_out[tid] - output[tid];
deltao[tid] = -err[tid] * dsigmoid(output[tid]);
}
// launch grid: <<<N, 2>>> for N = number of cases, 2 hidden neurons
__global__ void deltas_hidden(float *hidden, float *w, float *deltah, float *deltao)
{
// tid is the index for deltah and hidden
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// oid is the corresponding index in the output layer
// there's only one node in output so 1 per block
int oid = blockIdx.x;
// wid is the index into the weights, taking into account the bias weight
int wid = l2w_off + threadIdx.x + 1;
deltah[tid] = w[wid] * deltao[oid] * dsigmoid(hidden[tid]);
}
// launch grid: <<<N, 6>>> for N cases, 6 weights for hidden layer
__global__ void derivs_hidden(float *input, float *deltah, float *deriv)
{
// weights per node (2 inputs + bias)
const int wpn = INPUT_SIZE + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l1w_off + threadIdx.x;
// delta index (3 weights per node: 2 inputs + bias)
int did = blockIdx.x * DELTAS_HIDDEN + (threadIdx.x / wpn);
// input index (3 weights per node)
int iid = blockIdx.x * INPUT_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float in = (threadIdx.x % wpn == 0? 1.0f : input[iid]);
deriv[wid] = deltah[did] * in;
}
// launch grid: <<<N, 3>>> for N cases, 3 weights for output layer
__global__ void derivs_output(float *hidden, float *deltao, float *deriv)
{
// weights per node (2 hidden neurons + bias)
const int wpn = NEURONS_HIDDEN + 1;
// weight index
int wid = blockIdx.x * NWEIGHTS + l2w_off + threadIdx.x;
// delta index (3 weights per node)
int did = blockIdx.x * DELTAS_OUT + (threadIdx.x / wpn);
// hidden index (3 weights per node)
int hid = blockIdx.x * HIDDEN_SIZE + (threadIdx.x % wpn) - 1;
// divergence due to bias weight
float h = (threadIdx.x % wpn == 0? 1.0f : hidden[hid]);
deriv[wid] = deltao[did] * h;
}
// <<<N, 9>>> for N cases, 9 derivs per case?
__global__ void sum_derivs(float *deriv)
{
}
// launch grid: <<<1, NWEIGHTS>>> for number of weights
__global__ void update_weights_nreduc(float *ws, float *deriv, float lrate)
{
float dE = 0.0f;
int wid = blockIdx.x * blockDim.x + threadIdx.x;
// sum all derivs for the same weight
for (int i = 0; i < NCASES; ++i)
dE += deriv[i * NWEIGHTS + wid];
// update weight
ws[wid] -= (lrate * dE);
}
// --- memory allocations and initialization ------------------------------
inline float* allocateFloatsDev(int n)
{
float *res;
if (hipMalloc((void**) &res, n * sizeof(float)) != hipSuccess) {
fprintf(stderr, "Could not allocate memory on the device\n");
exit(1);
}
return res;
}
void allocateDev(void)
{
// weights
dev_weights = allocateFloatsDev(NWEIGHTS);
// node values
dev_in = allocateFloatsDev(ncases * input_size);
dev_hidden = allocateFloatsDev(ncases * hidden_size);
dev_out = allocateFloatsDev(ncases * out_size);
// desired outputs and errors on device
dev_dout = allocateFloatsDev(ncases * out_size);
dev_err = allocateFloatsDev(ncases * out_size);
// deltas and derivatives
dev_delta_h = allocateFloatsDev(NEURONS_HIDDEN);
dev_delta_o = allocateFloatsDev(NEURONS_OUT);
dev_deriv = allocateFloatsDev(NWEIGHTS);
}
void freeDev(void)
{
// weights
hipFree(dev_weights);
// node values
hipFree(dev_in);
hipFree(dev_hidden);
hipFree(dev_out);
// desired outputs and errors
hipFree(dev_dout);
hipFree(dev_err);
// deltas and derivatives
hipFree(dev_delta_h);
hipFree(dev_deriv);
hipFree(dev_delta_o);
}
// initialize memory on the device to run kernels
void memorySetup(void)
{
allocateDev();
// initialize weights
random_initialize_weights(dev_weights, MAX_ABS, NWEIGHTS);
// copy inputs and desired outputs
hipMemcpy(dev_in, inputs, ncases * input_size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_dout, outputs, ncases * out_size * sizeof(float), hipMemcpyHostToDevice);
}
void printDevArray(float *devA, int length)
{
float *hostA;
hostA = (float*) malloc(length * sizeof(float));
hipMemcpy(hostA, devA, length * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < length; ++i)
printf("%6.3f ", hostA[i]);
printf("\n");
}
// --- training -----------------------------------------------------------
float batch_train(int epochs, int calc_sse, int print_sse)
{
float err[NCASES * OUTPUT_SIZE];
float sse = 0.0f;
for (int e = 0; e < epochs; ++e) {
// forward propagation for all input cases
forward_hidden<<<4, 2>>>(dev_weights, dev_in, dev_hidden);
forward_output<<<4, 1>>>(dev_weights, dev_hidden, dev_out);
// printf("Outputs: ");
// printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// backprop
deltas_output<<<4, 1>>>(dev_out, dev_dout, dev_delta_o, dev_err);
deltas_hidden<<<4, 2>>>(dev_hidden, dev_weights, dev_delta_h, dev_delta_o);
// printf("Deltas (hidden): ");
// printDevArray(dev_delta_h, DELTAS_HIDDEN);
// printf("Deltas (output): ");
// printDevArray(dev_delta_o, DELTAS_OUT);
// calculate SSE for this trial
if (calc_sse) {
sse = 0.0f;
hipMemcpy(err, dev_err, NCASES * OUTPUT_SIZE * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < NCASES * OUTPUT_SIZE; ++i) {
//printf("%6.3f ", err[i]);
sse += (err[i] * err[i]);
}
if (print_sse)
printf("SSE = %5.3f\n", sse);
}
// calculate derivatives
derivs_hidden<<<4, 6>>>(dev_in, dev_delta_h, dev_deriv);
derivs_output<<<4, 3>>>(dev_hidden, dev_delta_o, dev_deriv);
// update weights
update_weights_nreduc<<<1, NWEIGHTS>>>(dev_weights, dev_deriv, LRATE);
}
return sse;
}
void print_weights(void)
{
float weights[NWEIGHTS];
hipMemcpy(weights, dev_weights, NWEIGHTS * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < NWEIGHTS; ++i)
printf("%6.4f ", weights[i]);
printf("\n");
}
// --- main ---------------------------------------------------------------
int main(int argc, char **argv)
{
float sse;
memorySetup();
// print the generated weights
printf("Randomly generated weights on the device:\n");
print_weights();
// do training
printf("Batch training with 5000 epochs...\n");
sse = batch_train(8000, 1, 0);
printf("Final SSE: %6.3f\n", sse);
printf("Outputs: ");
printDevArray(dev_out, NCASES * OUTPUT_SIZE);
// weights after training
printf("Weights after training:\n");
print_weights();
freeDev();
return 0;
} | .text
.file "xor_train.hip"
.globl _Z32__device_stub__normalize_weightsPff # -- Begin function _Z32__device_stub__normalize_weightsPff
.p2align 4, 0x90
.type _Z32__device_stub__normalize_weightsPff,@function
_Z32__device_stub__normalize_weightsPff: # @_Z32__device_stub__normalize_weightsPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17normalize_weightsPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__normalize_weightsPff, .Lfunc_end0-_Z32__device_stub__normalize_weightsPff
.cfi_endproc
# -- End function
.globl _Z25random_initialize_weightsPffi # -- Begin function _Z25random_initialize_weightsPffi
.p2align 4, 0x90
.type _Z25random_initialize_weightsPffi,@function
_Z25random_initialize_weightsPffi: # @_Z25random_initialize_weightsPffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movss %xmm0, 16(%rsp) # 4-byte Spill
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movl $401, %esi # imm = 0x191
callq hiprandCreateGenerator
movq 8(%rsp), %rdi
movl $419217, %esi # imm = 0x66591
callq hiprandSetPseudoRandomGeneratorSeed
movq 8(%rsp), %rdi
movl $102, %esi
callq hiprandSetGeneratorOrdering
movq 8(%rsp), %rdi
movslq %ebp, %r14
movq %rbx, %rsi
movq %r14, %rdx
callq hiprandGenerateUniform
movl %r14d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 72(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17normalize_weightsPff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hiprandDestroyGenerator
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25random_initialize_weightsPffi, .Lfunc_end1-_Z25random_initialize_weightsPffi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__forward_hiddenPfS_S_ # -- Begin function _Z29__device_stub__forward_hiddenPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__forward_hiddenPfS_S_,@function
_Z29__device_stub__forward_hiddenPfS_S_: # @_Z29__device_stub__forward_hiddenPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14forward_hiddenPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z29__device_stub__forward_hiddenPfS_S_, .Lfunc_end2-_Z29__device_stub__forward_hiddenPfS_S_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__forward_outputPfS_S_ # -- Begin function _Z29__device_stub__forward_outputPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__forward_outputPfS_S_,@function
_Z29__device_stub__forward_outputPfS_S_: # @_Z29__device_stub__forward_outputPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14forward_outputPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__forward_outputPfS_S_, .Lfunc_end3-_Z29__device_stub__forward_outputPfS_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__deltas_outputPfS_S_S_ # -- Begin function _Z28__device_stub__deltas_outputPfS_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__deltas_outputPfS_S_S_,@function
_Z28__device_stub__deltas_outputPfS_S_S_: # @_Z28__device_stub__deltas_outputPfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13deltas_outputPfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z28__device_stub__deltas_outputPfS_S_S_, .Lfunc_end4-_Z28__device_stub__deltas_outputPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__deltas_hiddenPfS_S_S_ # -- Begin function _Z28__device_stub__deltas_hiddenPfS_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__deltas_hiddenPfS_S_S_,@function
_Z28__device_stub__deltas_hiddenPfS_S_S_: # @_Z28__device_stub__deltas_hiddenPfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13deltas_hiddenPfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z28__device_stub__deltas_hiddenPfS_S_S_, .Lfunc_end5-_Z28__device_stub__deltas_hiddenPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__derivs_hiddenPfS_S_ # -- Begin function _Z28__device_stub__derivs_hiddenPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__derivs_hiddenPfS_S_,@function
_Z28__device_stub__derivs_hiddenPfS_S_: # @_Z28__device_stub__derivs_hiddenPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13derivs_hiddenPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z28__device_stub__derivs_hiddenPfS_S_, .Lfunc_end6-_Z28__device_stub__derivs_hiddenPfS_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__derivs_outputPfS_S_ # -- Begin function _Z28__device_stub__derivs_outputPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__derivs_outputPfS_S_,@function
_Z28__device_stub__derivs_outputPfS_S_: # @_Z28__device_stub__derivs_outputPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13derivs_outputPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end7:
.size _Z28__device_stub__derivs_outputPfS_S_, .Lfunc_end7-_Z28__device_stub__derivs_outputPfS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__sum_derivsPf # -- Begin function _Z25__device_stub__sum_derivsPf
.p2align 4, 0x90
.type _Z25__device_stub__sum_derivsPf,@function
_Z25__device_stub__sum_derivsPf: # @_Z25__device_stub__sum_derivsPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10sum_derivsPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end8:
.size _Z25__device_stub__sum_derivsPf, .Lfunc_end8-_Z25__device_stub__sum_derivsPf
.cfi_endproc
# -- End function
.globl _Z36__device_stub__update_weights_nreducPfS_f # -- Begin function _Z36__device_stub__update_weights_nreducPfS_f
.p2align 4, 0x90
.type _Z36__device_stub__update_weights_nreducPfS_f,@function
_Z36__device_stub__update_weights_nreducPfS_f: # @_Z36__device_stub__update_weights_nreducPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21update_weights_nreducPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end9:
.size _Z36__device_stub__update_weights_nreducPfS_f, .Lfunc_end9-_Z36__device_stub__update_weights_nreducPfS_f
.cfi_endproc
# -- End function
.globl _Z11allocateDevv # -- Begin function _Z11allocateDevv
.p2align 4, 0x90
.type _Z11allocateDevv,@function
_Z11allocateDevv: # @_Z11allocateDevv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $36, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.1: # %_Z17allocateFloatsDevi.exit
movq (%rsp), %rax
movq %rax, dev_weights(%rip)
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.2: # %_Z17allocateFloatsDevi.exit2
movq (%rsp), %rax
movq %rax, dev_in(%rip)
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.3: # %_Z17allocateFloatsDevi.exit4
movq (%rsp), %rax
movq %rax, dev_hidden(%rip)
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.4: # %_Z17allocateFloatsDevi.exit6
movq (%rsp), %rax
movq %rax, dev_out(%rip)
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.5: # %_Z17allocateFloatsDevi.exit8
movq (%rsp), %rax
movq %rax, dev_dout(%rip)
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.6: # %_Z17allocateFloatsDevi.exit10
movq (%rsp), %rax
movq %rax, dev_err(%rip)
movq %rsp, %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.7: # %_Z17allocateFloatsDevi.exit12
movq (%rsp), %rax
movq %rax, dev_delta_h(%rip)
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.8: # %_Z17allocateFloatsDevi.exit14
movq (%rsp), %rax
movq %rax, dev_delta_o(%rip)
movq %rsp, %rdi
movl $36, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB10_10
# %bb.9: # %_Z17allocateFloatsDevi.exit16
movq (%rsp), %rax
movq %rax, dev_deriv(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB10_10:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $40, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end10:
.size _Z11allocateDevv, .Lfunc_end10-_Z11allocateDevv
.cfi_endproc
# -- End function
.globl _Z7freeDevv # -- Begin function _Z7freeDevv
.p2align 4, 0x90
.type _Z7freeDevv,@function
_Z7freeDevv: # @_Z7freeDevv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq dev_weights(%rip), %rdi
callq hipFree
movq dev_in(%rip), %rdi
callq hipFree
movq dev_hidden(%rip), %rdi
callq hipFree
movq dev_out(%rip), %rdi
callq hipFree
movq dev_dout(%rip), %rdi
callq hipFree
movq dev_err(%rip), %rdi
callq hipFree
movq dev_delta_h(%rip), %rdi
callq hipFree
movq dev_deriv(%rip), %rdi
callq hipFree
movq dev_delta_o(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end11:
.size _Z7freeDevv, .Lfunc_end11-_Z7freeDevv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11memorySetupv
.LCPI12_0:
.long 0x3fc00000 # float 1.5
.text
.globl _Z11memorySetupv
.p2align 4, 0x90
.type _Z11memorySetupv,@function
_Z11memorySetupv: # @_Z11memorySetupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z11allocateDevv
movq dev_weights(%rip), %rdi
movss .LCPI12_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $9, %esi
callq _Z25random_initialize_weightsPffi
movq dev_in(%rip), %rdi
movl $inputs, %esi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_dout(%rip), %rdi
movl $outputs, %esi
movl $16, %edx
movl $1, %ecx
popq %rax
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end12:
.size _Z11memorySetupv, .Lfunc_end12-_Z11memorySetupv
.cfi_endproc
# -- End function
.globl _Z13printDevArrayPfi # -- Begin function _Z13printDevArrayPfi
.p2align 4, 0x90
.type _Z13printDevArrayPfi,@function
_Z13printDevArrayPfi: # @_Z13printDevArrayPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r12
leaq (,%r12,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB13_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB13_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB13_2
.LBB13_3: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end13:
.size _Z13printDevArrayPfi, .Lfunc_end13-_Z13printDevArrayPfi
.cfi_endproc
# -- End function
.globl _Z11batch_trainiii # -- Begin function _Z11batch_trainiii
.p2align 4, 0x90
.type _Z11batch_trainiii,@function
_Z11batch_trainiii: # @_Z11batch_trainiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 124(%rsp) # 4-byte Spill
movl %esi, 132(%rsp) # 4-byte Spill
movl %edi, 128(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB14_1
# %bb.3: # %.lr.ph
xorl %r14d, %r14d
xorps %xmm0, %xmm0
movss %xmm0, 68(%rsp) # 4-byte Spill
movabsq $4294967300, %r15 # imm = 0x100000004
leaq -2(%r15), %r12
leaq 72(%rsp), %r13
leaq 80(%rsp), %rbx
leaq -3(%r15), %rbp
leaq 2(%r15), %rax
movq %rax, 152(%rsp) # 8-byte Spill
leaq -1(%r15), %rax
movq %rax, 144(%rsp) # 8-byte Spill
leaq 5(%r15), %rax
movq %rax, 136(%rsp) # 8-byte Spill
jmp .LBB14_4
.p2align 4, 0x90
.LBB14_24: # in Loop: Header=BB14_4 Depth=1
incl %r14d
cmpl 128(%rsp), %r14d # 4-byte Folded Reload
je .LBB14_2
.LBB14_4: # =>This Loop Header: Depth=1
# Child Loop BB14_14 Depth 2
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB14_6
# %bb.5: # in Loop: Header=BB14_4 Depth=1
movq dev_weights(%rip), %rax
movq dev_in(%rip), %rcx
movq dev_hidden(%rip), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %rsp, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z14forward_hiddenPfS_S_, %edi
movq %rbx, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB14_6: # in Loop: Header=BB14_4 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB14_8
# %bb.7: # in Loop: Header=BB14_4 Depth=1
movq dev_weights(%rip), %rax
movq dev_hidden(%rip), %rcx
movq dev_out(%rip), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %rsp, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z14forward_outputPfS_S_, %edi
movq %rbx, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB14_8: # in Loop: Header=BB14_4 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB14_10
# %bb.9: # in Loop: Header=BB14_4 Depth=1
movq dev_out(%rip), %rax
movq dev_dout(%rip), %rcx
movq dev_delta_o(%rip), %rdx
movq dev_err(%rip), %rsi
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 8(%rsp)
movq %rsi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r13, %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z13deltas_outputPfS_S_S_, %edi
movq %rbx, %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB14_10: # in Loop: Header=BB14_4 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB14_11
# %bb.12: # in Loop: Header=BB14_4 Depth=1
cmpl $0, 132(%rsp) # 4-byte Folded Reload
jne .LBB14_13
jmp .LBB14_18
.p2align 4, 0x90
.LBB14_11: # in Loop: Header=BB14_4 Depth=1
movq dev_hidden(%rip), %rax
movq dev_weights(%rip), %rcx
movq dev_delta_h(%rip), %rdx
movq dev_delta_o(%rip), %rsi
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 8(%rsp)
movq %rsi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r13, %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z13deltas_hiddenPfS_S_S_, %edi
movq %rbx, %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $0, 132(%rsp) # 4-byte Folded Reload
je .LBB14_18
.LBB14_13: # in Loop: Header=BB14_4 Depth=1
movq dev_err(%rip), %rsi
movl $16, %edx
leaq 160(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB14_14: # Parent Loop BB14_4 Depth=1
# => This Inner Loop Header: Depth=2
movss 160(%rsp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $4, %rax
jne .LBB14_14
# %bb.15: # in Loop: Header=BB14_4 Depth=1
cmpl $0, 124(%rsp) # 4-byte Folded Reload
je .LBB14_16
# %bb.17: # in Loop: Header=BB14_4 Depth=1
movss %xmm1, 68(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
jmp .LBB14_18
.p2align 4, 0x90
.LBB14_16: # in Loop: Header=BB14_4 Depth=1
movss %xmm1, 68(%rsp) # 4-byte Spill
.LBB14_18: # in Loop: Header=BB14_4 Depth=1
movq %r15, %rdi
movl $1, %esi
movq 152(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB14_20
# %bb.19: # in Loop: Header=BB14_4 Depth=1
movq dev_in(%rip), %rax
movq dev_delta_h(%rip), %rcx
movq dev_deriv(%rip), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %rsp, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z13derivs_hiddenPfS_S_, %edi
movq %rbx, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB14_20: # in Loop: Header=BB14_4 Depth=1
movq %r15, %rdi
movl $1, %esi
movq 144(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB14_22
# %bb.21: # in Loop: Header=BB14_4 Depth=1
movq dev_hidden(%rip), %rax
movq dev_delta_o(%rip), %rcx
movq dev_deriv(%rip), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %rsp, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z13derivs_outputPfS_S_, %edi
movq %rbx, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB14_22: # in Loop: Header=BB14_4 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq 136(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB14_24
# %bb.23: # in Loop: Header=BB14_4 Depth=1
movq dev_weights(%rip), %rax
movq dev_deriv(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movl $1061158912, 72(%rsp) # imm = 0x3F400000
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
movq %r13, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z21update_weights_nreducPfS_f, %edi
movq %rbx, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB14_24
.LBB14_1:
xorps %xmm0, %xmm0
movss %xmm0, 68(%rsp) # 4-byte Spill
.LBB14_2: # %._crit_edge
movss 68(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end14:
.size _Z11batch_trainiii, .Lfunc_end14-_Z11batch_trainiii
.cfi_endproc
# -- End function
.globl _Z13print_weightsv # -- Begin function _Z13print_weightsv
.p2align 4, 0x90
.type _Z13print_weightsv,@function
_Z13print_weightsv: # @_Z13print_weightsv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $48, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -16
movq dev_weights(%rip), %rsi
movq %rsp, %rdi
movl $36, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB15_1: # =>This Inner Loop Header: Depth=1
movss (%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $9, %rbx
jne .LBB15_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
addq $48, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end15:
.size _Z13print_weightsv, .Lfunc_end15-_Z13print_weightsv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI16_0:
.long 0x3fc00000 # float 1.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $48, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z11allocateDevv
movq dev_weights(%rip), %rdi
movss .LCPI16_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $9, %esi
callq _Z25random_initialize_weightsPffi
movq dev_in(%rip), %rdi
movl $inputs, %esi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_dout(%rip), %rdi
movl $outputs, %esi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq dev_weights(%rip), %rsi
movq %rsp, %rdi
movl $36, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB16_1: # =>This Inner Loop Header: Depth=1
movss (%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $9, %rbx
jne .LBB16_1
# %bb.2: # %_Z13print_weightsv.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
movl $8000, %edi # imm = 0x1F40
movl $1, %esi
xorl %edx, %edx
callq _Z11batch_trainiii
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq dev_out(%rip), %r14
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edx
movq %rax, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB16_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB16_3
# %bb.4: # %_Z13printDevArrayPfi.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movq dev_weights(%rip), %rsi
movq %rsp, %rdi
movl $36, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB16_5: # =>This Inner Loop Header: Depth=1
movss (%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $9, %rbx
jne .LBB16_5
# %bb.6: # %_Z13print_weightsv.exit11
movl $10, %edi
callq putchar@PLT
movq dev_weights(%rip), %rdi
callq hipFree
movq dev_in(%rip), %rdi
callq hipFree
movq dev_hidden(%rip), %rdi
callq hipFree
movq dev_out(%rip), %rdi
callq hipFree
movq dev_dout(%rip), %rdi
callq hipFree
movq dev_err(%rip), %rdi
callq hipFree
movq dev_delta_h(%rip), %rdi
callq hipFree
movq dev_deriv(%rip), %rdi
callq hipFree
movq dev_delta_o(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end16:
.size main, .Lfunc_end16-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB17_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB17_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17normalize_weightsPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14forward_hiddenPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14forward_outputPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13deltas_outputPfS_S_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13deltas_hiddenPfS_S_S_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13derivs_hiddenPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13derivs_outputPfS_S_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_derivsPf, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21update_weights_nreducPfS_f, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end17:
.size __hip_module_ctor, .Lfunc_end17-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB18_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB18_2:
retq
.Lfunc_end18:
.size __hip_module_dtor, .Lfunc_end18-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_weights,@object # @dev_weights
.bss
.globl dev_weights
.p2align 3, 0x0
dev_weights:
.quad 0
.size dev_weights, 8
.type gen,@object # @gen
.globl gen
.p2align 3, 0x0
gen:
.quad 0
.size gen, 8
.type dev_in,@object # @dev_in
.globl dev_in
.p2align 3, 0x0
dev_in:
.quad 0
.size dev_in, 8
.type dev_hidden,@object # @dev_hidden
.globl dev_hidden
.p2align 3, 0x0
dev_hidden:
.quad 0
.size dev_hidden, 8
.type dev_out,@object # @dev_out
.globl dev_out
.p2align 3, 0x0
dev_out:
.quad 0
.size dev_out, 8
.type inputs,@object # @inputs
.data
.globl inputs
.p2align 4, 0x0
inputs:
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.size inputs, 32
.type outputs,@object # @outputs
.globl outputs
.p2align 4, 0x0
outputs:
.long 0x3dcccccd # float 0.100000001
.long 0x3f666666 # float 0.899999976
.long 0x3f666666 # float 0.899999976
.long 0x3dcccccd # float 0.100000001
.size outputs, 16
.type dev_dout,@object # @dev_dout
.bss
.globl dev_dout
.p2align 3, 0x0
dev_dout:
.quad 0
.size dev_dout, 8
.type dev_delta_h,@object # @dev_delta_h
.globl dev_delta_h
.p2align 3, 0x0
dev_delta_h:
.quad 0
.size dev_delta_h, 8
.type dev_delta_o,@object # @dev_delta_o
.globl dev_delta_o
.p2align 3, 0x0
dev_delta_o:
.quad 0
.size dev_delta_o, 8
.type dev_deriv,@object # @dev_deriv
.globl dev_deriv
.p2align 3, 0x0
dev_deriv:
.quad 0
.size dev_deriv, 8
.type dev_err,@object # @dev_err
.globl dev_err
.p2align 3, 0x0
dev_err:
.quad 0
.size dev_err, 8
.type _Z17normalize_weightsPff,@object # @_Z17normalize_weightsPff
.section .rodata,"a",@progbits
.globl _Z17normalize_weightsPff
.p2align 3, 0x0
_Z17normalize_weightsPff:
.quad _Z32__device_stub__normalize_weightsPff
.size _Z17normalize_weightsPff, 8
.type _Z14forward_hiddenPfS_S_,@object # @_Z14forward_hiddenPfS_S_
.globl _Z14forward_hiddenPfS_S_
.p2align 3, 0x0
_Z14forward_hiddenPfS_S_:
.quad _Z29__device_stub__forward_hiddenPfS_S_
.size _Z14forward_hiddenPfS_S_, 8
.type _Z14forward_outputPfS_S_,@object # @_Z14forward_outputPfS_S_
.globl _Z14forward_outputPfS_S_
.p2align 3, 0x0
_Z14forward_outputPfS_S_:
.quad _Z29__device_stub__forward_outputPfS_S_
.size _Z14forward_outputPfS_S_, 8
.type _Z13deltas_outputPfS_S_S_,@object # @_Z13deltas_outputPfS_S_S_
.globl _Z13deltas_outputPfS_S_S_
.p2align 3, 0x0
_Z13deltas_outputPfS_S_S_:
.quad _Z28__device_stub__deltas_outputPfS_S_S_
.size _Z13deltas_outputPfS_S_S_, 8
.type _Z13deltas_hiddenPfS_S_S_,@object # @_Z13deltas_hiddenPfS_S_S_
.globl _Z13deltas_hiddenPfS_S_S_
.p2align 3, 0x0
_Z13deltas_hiddenPfS_S_S_:
.quad _Z28__device_stub__deltas_hiddenPfS_S_S_
.size _Z13deltas_hiddenPfS_S_S_, 8
.type _Z13derivs_hiddenPfS_S_,@object # @_Z13derivs_hiddenPfS_S_
.globl _Z13derivs_hiddenPfS_S_
.p2align 3, 0x0
_Z13derivs_hiddenPfS_S_:
.quad _Z28__device_stub__derivs_hiddenPfS_S_
.size _Z13derivs_hiddenPfS_S_, 8
.type _Z13derivs_outputPfS_S_,@object # @_Z13derivs_outputPfS_S_
.globl _Z13derivs_outputPfS_S_
.p2align 3, 0x0
_Z13derivs_outputPfS_S_:
.quad _Z28__device_stub__derivs_outputPfS_S_
.size _Z13derivs_outputPfS_S_, 8
.type _Z10sum_derivsPf,@object # @_Z10sum_derivsPf
.globl _Z10sum_derivsPf
.p2align 3, 0x0
_Z10sum_derivsPf:
.quad _Z25__device_stub__sum_derivsPf
.size _Z10sum_derivsPf, 8
.type _Z21update_weights_nreducPfS_f,@object # @_Z21update_weights_nreducPfS_f
.globl _Z21update_weights_nreducPfS_f
.p2align 3, 0x0
_Z21update_weights_nreducPfS_f:
.quad _Z36__device_stub__update_weights_nreducPfS_f
.size _Z21update_weights_nreducPfS_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%6.3f "
.size .L.str, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "SSE = %5.3f\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%6.4f "
.size .L.str.3, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Final SSE: %6.3f\n"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Outputs: "
.size .L.str.7, 10
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Could not allocate memory on the device\n"
.size .L.str.9, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17normalize_weightsPff"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14forward_hiddenPfS_S_"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14forward_outputPfS_S_"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z13deltas_outputPfS_S_S_"
.size .L__unnamed_4, 26
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z13deltas_hiddenPfS_S_S_"
.size .L__unnamed_5, 26
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z13derivs_hiddenPfS_S_"
.size .L__unnamed_6, 24
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z13derivs_outputPfS_S_"
.size .L__unnamed_7, 24
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z10sum_derivsPf"
.size .L__unnamed_8, 17
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z21update_weights_nreducPfS_f"
.size .L__unnamed_9, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Randomly generated weights on the device:"
.size .Lstr, 42
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Batch training with 5000 epochs..."
.size .Lstr.1, 35
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Weights after training:"
.size .Lstr.2, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__normalize_weightsPff
.addrsig_sym _Z29__device_stub__forward_hiddenPfS_S_
.addrsig_sym _Z29__device_stub__forward_outputPfS_S_
.addrsig_sym _Z28__device_stub__deltas_outputPfS_S_S_
.addrsig_sym _Z28__device_stub__deltas_hiddenPfS_S_S_
.addrsig_sym _Z28__device_stub__derivs_hiddenPfS_S_
.addrsig_sym _Z28__device_stub__derivs_outputPfS_S_
.addrsig_sym _Z25__device_stub__sum_derivsPf
.addrsig_sym _Z36__device_stub__update_weights_nreducPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym inputs
.addrsig_sym outputs
.addrsig_sym _Z17normalize_weightsPff
.addrsig_sym _Z14forward_hiddenPfS_S_
.addrsig_sym _Z14forward_outputPfS_S_
.addrsig_sym _Z13deltas_outputPfS_S_S_
.addrsig_sym _Z13deltas_hiddenPfS_S_S_
.addrsig_sym _Z13derivs_hiddenPfS_S_
.addrsig_sym _Z13derivs_outputPfS_S_
.addrsig_sym _Z10sum_derivsPf
.addrsig_sym _Z21update_weights_nreducPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define SIZE 16
__global__
void VectorAdd(int *a,int *b,int *c,int n)
{
int i = threadIdx.x;
if(i < n)c[i] = a[i] + b[i];
else printf("-----%d-----\n",i);
int j = threadIdx.x;
int k = threadIdx.y;
int e = blockIdx.x;
int f = blockIdx.y;
int g = blockDim.x;
int h = blockDim.y;
printf("thread:%d,%d,block:%d,%d,blockdim:%d,%d\n",j,k,e,f,g,h);
}
int main() {
int *a,*b,*c;
cudaMallocManaged(&a, SIZE * sizeof(int));
cudaMallocManaged(&b, SIZE * sizeof(int));
cudaMallocManaged(&c, SIZE * sizeof(int));
for (int i = 0;i < SIZE;i++)
{
a[i] = b[i] = i;
c[i] = 0;
}
VectorAdd <<<1,SIZE>>> (a,b,c,SIZE);
cudaDeviceSynchronize();
for (int i = 0; i < 10; i++)printf("c[%d] = %d\n",i,c[i]);
cudaFree(a);
cudaFree(b);
cudaFree(c);
return 0;
} | code for sm_80
Function : _Z9VectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B6, 0x220 ; /* 0x000001d000067945 */
/* 0x000fe40003800000 */
/*0050*/ IADD3 R17, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001117a10 */
/* 0x000fca0007f3e0ff */
/*0060*/ IMAD.X R16, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff107624 */
/* 0x000fe200008e06ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x001fda0003f06270 */
/*0080*/ @!P0 BRA 0x190 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*00a0*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100800 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00d0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0011 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0010 */
/*0100*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fe40000000000 */
/*0110*/ MOV R3, 0x180 ; /* 0x0000018000037802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0160*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0170*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0180*/ BRA 0x210 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R6, R2, R9, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0209 */
/*01b0*/ IMAD.WIDE R4, R2.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x0c0fe400078e0209 */
/*01c0*/ LDG.E R6, [R6.64] ; /* 0x0000002406067981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R5, [R4.64] ; /* 0x0000002404057981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R8, R2, R9, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fc800078e0209 */
/*01f0*/ IMAD.IADD R3, R6, 0x1, R5 ; /* 0x0000000106037824 */
/* 0x004fca00078e0205 */
/*0200*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0001e4000c101924 */
/*0210*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0220*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x001e220000002200 */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0240*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0b7624 */
/* 0x000fe200078e00ff */
/*0260*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0011 */
/*0280*/ LDC.64 R12, c[0x4][R0] ; /* 0x01000000000c7b82 */
/* 0x0004e20000000a00 */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0010 */
/*02a0*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e620000002500 */
/*02b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*02d0*/ STL.64 [R1+0x10], R10 ; /* 0x0000100a01007387 */
/* 0x0005e80000100a00 */
/*02e0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0015e80000100a00 */
/*02f0*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0025e40000100a00 */
/*0300*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x00cfe40000000000 */
/*0310*/ MOV R9, 0x380 ; /* 0x0000038000097802 */
/* 0x000fe40000000f00 */
/*0320*/ MOV R20, 0x300 ; /* 0x0000030000147802 */
/* 0x000fc40000000f00 */
/*0330*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0340*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0350*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0360*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0370*/ CALL.ABS.NOINC R12 ; /* 0x000000000c007343 */
/* 0x000fea0003c00000 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define SIZE 16
__global__
void VectorAdd(int *a,int *b,int *c,int n)
{
int i = threadIdx.x;
if(i < n)c[i] = a[i] + b[i];
else printf("-----%d-----\n",i);
int j = threadIdx.x;
int k = threadIdx.y;
int e = blockIdx.x;
int f = blockIdx.y;
int g = blockDim.x;
int h = blockDim.y;
printf("thread:%d,%d,block:%d,%d,blockdim:%d,%d\n",j,k,e,f,g,h);
}
int main() {
int *a,*b,*c;
cudaMallocManaged(&a, SIZE * sizeof(int));
cudaMallocManaged(&b, SIZE * sizeof(int));
cudaMallocManaged(&c, SIZE * sizeof(int));
for (int i = 0;i < SIZE;i++)
{
a[i] = b[i] = i;
c[i] = 0;
}
VectorAdd <<<1,SIZE>>> (a,b,c,SIZE);
cudaDeviceSynchronize();
for (int i = 0; i < 10; i++)printf("c[%d] = %d\n",i,c[i]);
cudaFree(a);
cudaFree(b);
cudaFree(c);
return 0;
} | .file "tmpxft_00071f1d_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.globl _Z9VectorAddPiS_S_i
.type _Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 24(%rsp), %rdx
movl $0, (%rdx,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movq 24(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $16, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9VectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define SIZE 16
__global__
void VectorAdd(int *a,int *b,int *c,int n)
{
int i = threadIdx.x;
if(i < n)c[i] = a[i] + b[i];
else printf("-----%d-----\n",i);
int j = threadIdx.x;
int k = threadIdx.y;
int e = blockIdx.x;
int f = blockIdx.y;
int g = blockDim.x;
int h = blockDim.y;
printf("thread:%d,%d,block:%d,%d,blockdim:%d,%d\n",j,k,e,f,g,h);
}
int main() {
int *a,*b,*c;
cudaMallocManaged(&a, SIZE * sizeof(int));
cudaMallocManaged(&b, SIZE * sizeof(int));
cudaMallocManaged(&c, SIZE * sizeof(int));
for (int i = 0;i < SIZE;i++)
{
a[i] = b[i] = i;
c[i] = 0;
}
VectorAdd <<<1,SIZE>>> (a,b,c,SIZE);
cudaDeviceSynchronize();
for (int i = 0; i < 10; i++)printf("c[%d] = %d\n",i,c[i]);
cudaFree(a);
cudaFree(b);
cudaFree(c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 16
__global__
void VectorAdd(int *a,int *b,int *c,int n)
{
int i = threadIdx.x;
if(i < n)c[i] = a[i] + b[i];
else printf("-----%d-----\n",i);
int j = threadIdx.x;
int k = threadIdx.y;
int e = blockIdx.x;
int f = blockIdx.y;
int g = blockDim.x;
int h = blockDim.y;
printf("thread:%d,%d,block:%d,%d,blockdim:%d,%d\n",j,k,e,f,g,h);
}
int main() {
int *a,*b,*c;
hipMallocManaged(&a, SIZE * sizeof(int));
hipMallocManaged(&b, SIZE * sizeof(int));
hipMallocManaged(&c, SIZE * sizeof(int));
for (int i = 0;i < SIZE;i++)
{
a[i] = b[i] = i;
c[i] = 0;
}
VectorAdd <<<1,SIZE>>> (a,b,c,SIZE);
hipDeviceSynchronize();
for (int i = 0; i < 10; i++)printf("c[%d] = %d\n",i,c[i]);
hipFree(a);
hipFree(b);
hipFree(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 16
__global__
void VectorAdd(int *a,int *b,int *c,int n)
{
int i = threadIdx.x;
if(i < n)c[i] = a[i] + b[i];
else printf("-----%d-----\n",i);
int j = threadIdx.x;
int k = threadIdx.y;
int e = blockIdx.x;
int f = blockIdx.y;
int g = blockDim.x;
int h = blockDim.y;
printf("thread:%d,%d,block:%d,%d,blockdim:%d,%d\n",j,k,e,f,g,h);
}
int main() {
int *a,*b,*c;
hipMallocManaged(&a, SIZE * sizeof(int));
hipMallocManaged(&b, SIZE * sizeof(int));
hipMallocManaged(&c, SIZE * sizeof(int));
for (int i = 0;i < SIZE;i++)
{
a[i] = b[i] = i;
c[i] = 0;
}
VectorAdd <<<1,SIZE>>> (a,b,c,SIZE);
hipDeviceSynchronize();
for (int i = 0; i < 10; i++)printf("c[%d] = %d\n",i,c[i]);
hipFree(a);
hipFree(b);
hipFree(c);
return 0;
} | .text
.file "main.hip"
.globl _Z24__device_stub__VectorAddPiS_S_i # -- Begin function _Z24__device_stub__VectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPiS_S_i,@function
_Z24__device_stub__VectorAddPiS_S_i: # @_Z24__device_stub__VectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
xorl %edx, %edx
movq 8(%rsp), %rsi
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %edx, (%rax,%rdx,4)
movl %edx, (%rcx,%rdx,4)
movl $0, (%rsi,%rdx,4)
incq %rdx
cmpq $16, %rdx
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPiS_S_i,@object # @_Z9VectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPiS_S_i
.p2align 3, 0x0
_Z9VectorAddPiS_S_i:
.quad _Z24__device_stub__VectorAddPiS_S_i
.size _Z9VectorAddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9VectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00071f1d_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.globl _Z9VectorAddPiS_S_i
.type _Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 24(%rsp), %rdx
movl $0, (%rdx,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movq 24(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $16, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9VectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z24__device_stub__VectorAddPiS_S_i # -- Begin function _Z24__device_stub__VectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPiS_S_i,@function
_Z24__device_stub__VectorAddPiS_S_i: # @_Z24__device_stub__VectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
xorl %edx, %edx
movq 8(%rsp), %rsi
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %edx, (%rax,%rdx,4)
movl %edx, (%rcx,%rdx,4)
movl $0, (%rsi,%rdx,4)
incq %rdx
cmpq $16, %rdx
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPiS_S_i,@object # @_Z9VectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPiS_S_i
.p2align 3, 0x0
_Z9VectorAddPiS_S_i:
.quad _Z24__device_stub__VectorAddPiS_S_i
.size _Z9VectorAddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9VectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
#define MAIN "_MAIN_:"
#define F1LO "_ODD_:"
#define CTRL "_CRTL_:"
#define ARRAY_SIZE 100000
#define TILE_WIDTH 128
#define DEVICE 1 //device 0 o 1
__device__
inline void SWAP(int32_t *_a,int32_t *_b){int32_t __aux; __aux = *_a; *_a = *_b; *_b = __aux;}
/*###################################
########### KERNELS ###########
###################################*/
__global__
void odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t t_position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
int32_t i_limit = blockDim.x*2;
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && t_position< n-1 && tid < blockDim.x*2-1 ) { // impar
if (*(arr_d+t_position + 1) < *(arr_d+t_position)) {
SWAP(arr_d + t_position, arr_d + t_position + 1);
}
}
if(!(i&1) && t_position < n && tid < blockDim.x*2){ //par
if (*(arr_d+t_position) < *(arr_d+t_position-1)) {
SWAP(arr_d + t_position, arr_d + t_position - 1);
}
}
__syncthreads();
}
}
__global__
void fast_odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
__shared__ int32_t sh_arr[2*TILE_WIDTH];
int32_t bound = blockDim.x*2;
int32_t i_limit = blockDim.x*2;
if(position < n){
*(sh_arr+tid)=*(arr_d+position);
*(sh_arr+tid-1)=*(arr_d+position-1);
__syncthreads();
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && position< n-1 && tid < bound-1 ) { // impar
if (*(sh_arr+tid + 1) < *(sh_arr+tid)) {
SWAP(sh_arr + tid, sh_arr + tid + 1);
}
}
if(!(i&1) && position < n && tid < bound){ //par
if (*(sh_arr+tid) < *(sh_arr+tid-1)) {
SWAP(sh_arr + tid, sh_arr + tid - 1);
}
}
__syncthreads();
}
*(arr_d+position) = *(sh_arr+tid);
*(arr_d+position-1) = *(sh_arr+tid-1);
}
}
/*##########################################
########### HOST FUNCTIONS ###########
##########################################*/
__host__
void odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
cudaError_t err;
cudaEvent_t start, stop;
float mili;
err = cudaMalloc((void**)&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
cudaEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
cudaEventRecord(stop);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
cudaEventElapsedTime(&mili, start, stop);
cudaMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
cudaFree(cuda_d);
}
__host__
void fast_odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
//float tile = TILE_WIDTH , size_t = ARRAY_SIZE;
//dim3 dimGrid ((uint)ceil(size_t/tile), 1, 1);
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
cudaError_t err;
cudaEvent_t start, stop;
float mili;
err = cudaMalloc(&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
cudaEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
fast_odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
cudaEventRecord(stop);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
cudaEventElapsedTime(&mili, start, stop);
cudaMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
cudaFree(cuda_d);
}
__host__
int control(int32_t *arr, int32_t n){
for(int32_t i=1; i<n; i++){
if(arr[i-1] > arr[i]){
printf("%s I = %d\n", CTRL, i);
return 1;
}
}
return 0;
}
/*###################################
########### MAIN ###########
###################################*/
int main( int argc, char *argv[] ){
int32_t *arr;
cudaError_t err;
arr = (int32_t*)malloc(sizeof(int32_t)*ARRAY_SIZE);
printf("array size: %d tile: %d\n",ARRAY_SIZE, TILE_WIDTH);
printf("#### SORT WHIT GLOBAL MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000+1;
// printf("%d ", arr[i]);
}
arr[0]=1001;
arr[ARRAY_SIZE-1]=0;
printf("\n");
err = cudaSetDevice(DEVICE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
printf("#### SORT WHIT SHARED MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000;
// printf("%d ", arr[i]);
}
printf("\n");
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
fast_odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
free(arr);
printf("\n");
return 0;
} | code for sm_80
Function : _Z25fast_odd_even_sort_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0207 */
/*0040*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x000fca00078e00ff */
/*0050*/ IADD3 R0, R4, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00c0*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ LEA R6, R7, 0x1, 0x1 ; /* 0x0000000107067811 */
/* 0x000fe200078e08ff */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fca00078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f06270 */
/*0120*/ STS [R6.X4], R9 ; /* 0x0000000906007388 */
/* 0x0041e80000004800 */
/*0130*/ STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b06007388 */
/* 0x0081e80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P0 BRA 0x670 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R9, R7.reuse, -0x1, RZ ; /* 0xffffffff07097810 */
/* 0x041fe20007ffe0ff */
/*0170*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0180*/ LOP3.LUT R8, R7, 0x2, RZ, 0xc0, !PT ; /* 0x0000000207087812 */
/* 0x000fe200078ec0ff */
/*0190*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe20003f06070 */
/*01b0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe2000fffe13f */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd600078e00ff */
/*01d0*/ @!P0 BRA 0x4b0 ; /* 0x000002d000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*01f0*/ IMAD.IADD R13, R7, 0x1, -R8 ; /* 0x00000001070d7824 */
/* 0x000fe200078e0a08 */
/*0200*/ ISETP.GE.AND P1, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */
/* 0x040fe20003f26270 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.LT.AND P0, PT, R6, R9, !P0 ; /* 0x000000090600720c */
/* 0x000fd40004701270 */
/*0230*/ BSSY B0, 0x2b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0240*/ @P1 BRA 0x2a0 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*0250*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x000fe80000004800 */
/*0260*/ LDS R10, [R6.X4+-0x4] ; /* 0xfffffc00060a7984 */
/* 0x000e240000004800 */
/*0270*/ ISETP.GE.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x001fda0003f46270 */
/*0280*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*0290*/ @!P2 STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b0600a388 */
/* 0x0001e40000004800 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ BSSY B0, 0x340 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*02d0*/ @!P0 BRA 0x330 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02e0*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*02f0*/ LDS R10, [R6.X4+0x4] ; /* 0x00000400060a7984 */
/* 0x000e240000004800 */
/*0300*/ ISETP.GE.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x001fda0003f46270 */
/*0310*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*0320*/ @!P2 STS [R6.X4+0x4], R11 ; /* 0x0000040b0600a388 */
/* 0x0001e40000004800 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ BSSY B0, 0x3d0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0360*/ @P1 BRA 0x3c0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0370*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*0380*/ LDS R10, [R6.X4+-0x4] ; /* 0xfffffc00060a7984 */
/* 0x000e240000004800 */
/*0390*/ ISETP.GE.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x001fda0003f46270 */
/*03a0*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*03b0*/ @!P2 STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b0600a388 */
/* 0x0001e40000004800 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*03f0*/ ISETP.NE.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f65270 */
/*0400*/ BSSY B0, 0x480 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0410*/ @!P0 BRA 0x470 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0420*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*0430*/ LDS R10, [R6.X4+0x4] ; /* 0x00000400060a7984 */
/* 0x000e240000004800 */
/*0440*/ ISETP.GE.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x001fda0003f46270 */
/*0450*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*0460*/ @!P2 STS [R6.X4+0x4], R11 ; /* 0x0000040b0600a388 */
/* 0x0001e40000004800 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0490*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fca0007ffe0ff */
/*04a0*/ @P3 BRA 0x230 ; /* 0xfffffd8000003947 */
/* 0x000fea000383ffff */
/*04b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*04c0*/ @!P0 BRA 0x670 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*04d0*/ LOP3.LUT P0, R10, R12, 0x1, RZ, 0xc0, !PT ; /* 0x000000010c0a7812 */
/* 0x001fe2000780c0ff */
/*04e0*/ BSSY B0, 0x5a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*04f0*/ ISETP.GE.OR P0, PT, R0, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x000fe4000c706670 */
/*0500*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*0510*/ ISETP.GE.OR P0, PT, R6.reuse, R9, P0 ; /* 0x000000090600720c */
/* 0x040fe40000706670 */
/*0520*/ ISETP.GE.OR P1, PT, R6, R7, P1 ; /* 0x000000070600720c */
/* 0x000fd60000f26670 */
/*0530*/ @P0 BRA 0x590 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0540*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x000fe80000004800 */
/*0550*/ LDS R10, [R6.X4+0x4] ; /* 0x00000400060a7984 */
/* 0x000e240000004800 */
/*0560*/ ISETP.GE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x001fda0003f06270 */
/*0570*/ @!P0 STS [R6.X4], R10 ; /* 0x0000000a06008388 */
/* 0x0001e80000004800 */
/*0580*/ @!P0 STS [R6.X4+0x4], R11 ; /* 0x0000040b06008388 */
/* 0x0001e40000004800 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ BSSY B0, 0x620 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*05b0*/ @P1 BRA 0x610 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*05c0*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*05d0*/ LDS R10, [R6.X4+-0x4] ; /* 0xfffffc00060a7984 */
/* 0x000e240000004800 */
/*05e0*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x001fda0003f06270 */
/*05f0*/ @!P0 STS [R6.X4], R10 ; /* 0x0000000a06008388 */
/* 0x0001e80000004800 */
/*0600*/ @!P0 STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b06008388 */
/* 0x0001e40000004800 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0640*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0660*/ @P0 BRA 0x4d0 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0670*/ LDS R7, [R6.X4] ; /* 0x0000000006077984 */
/* 0x001e280000004800 */
/*0680*/ LDS R9, [R6.X4+-0x4] ; /* 0xfffffc0006097984 */
/* 0x000e680000004800 */
/*0690*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101906 */
/*06a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20odd_even_sort_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0040*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fca00078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fd800078e0207 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R10, R8, -0x1, RZ ; /* 0xffffffff080a7810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*00a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fe20003f06070 */
/*00d0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe20007ffe0ff */
/*00f0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe2000fffe13f */
/*0100*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0205 */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ LEA R7, R7, 0x1, 0x1 ; /* 0x0000000107077811 */
/* 0x000fc400078e08ff */
/*0130*/ LOP3.LUT R9, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208097812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe400078e0205 */
/*0160*/ @!P0 BRA 0x450 ; /* 0x000002e000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f06270 */
/*0180*/ IMAD.IADD R13, R8, 0x1, -R9 ; /* 0x00000001080d7824 */
/* 0x000fe200078e0a09 */
/*0190*/ ISETP.GE.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf26270 */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.LT.U32.AND P0, PT, R7.reuse, R8, !P0 ; /* 0x000000080700720c */
/* 0x040fe40004701070 */
/*01c0*/ ISETP.LT.U32.AND P1, PT, R7, R10, !P1 ; /* 0x0000000a0700720c */
/* 0x000fd40004f21070 */
/*01d0*/ BSSY B0, 0x250 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @!P0 BRA 0x240 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*0210*/ ISETP.GE.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x004fda0003f46270 */
/*0220*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*0230*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e4000c101906 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ BSSY B0, 0x2e0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0270*/ @!P1 BRA 0x2d0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*0290*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ ISETP.GE.AND P2, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f46270 */
/*02b0*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*02c0*/ @!P2 STG.E [R4.64+0x4], R11 ; /* 0x0000040b0400a986 */
/* 0x0001e4000c101906 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ BSSY B0, 0x370 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0300*/ @!P0 BRA 0x360 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*0320*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*0330*/ ISETP.GE.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x004fda0003f46270 */
/*0340*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*0350*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e4000c101906 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe20007ffe0ff */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0390*/ ISETP.NE.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f65270 */
/*03a0*/ BSSY B0, 0x420 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*03b0*/ @!P1 BRA 0x410 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*03d0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ ISETP.GE.AND P2, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f46270 */
/*03f0*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*0400*/ @!P2 STG.E [R4.64+0x4], R11 ; /* 0x0000040b0400a986 */
/* 0x0001e4000c101906 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fca0007ffe0ff */
/*0440*/ @P3 BRA 0x1d0 ; /* 0xfffffd8000003947 */
/* 0x000fea000383ffff */
/*0450*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0460*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0470*/ LOP3.LUT P0, R0, R12, 0x1, RZ, 0xc0, !PT ; /* 0x000000010c007812 */
/* 0x001fe2000780c0ff */
/*0480*/ BSSY B0, 0x550 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*0490*/ ISETP.GE.OR P0, PT, R6, UR4, !P0 ; /* 0x0000000406007c0c */
/* 0x000fe4000c706670 */
/*04a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*04b0*/ ISETP.GE.U32.OR P0, PT, R7, R10, P0 ; /* 0x0000000a0700720c */
/* 0x000fe40000706470 */
/*04c0*/ ISETP.GE.OR P1, PT, R6, c[0x0][0x168], P1 ; /* 0x00005a0006007a0c */
/* 0x000fc80000f26670 */
/*04d0*/ ISETP.GE.U32.OR P1, PT, R7, R8, P1 ; /* 0x000000080700720c */
/* 0x000fce0000f26470 */
/*04e0*/ @P0 BRA 0x540 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*04f0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea4000c1e1900 */
/*0510*/ ISETP.GE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f06270 */
/*0520*/ @!P0 STG.E [R4.64], R0 ; /* 0x0000000004008986 */
/* 0x0001e8000c101906 */
/*0530*/ @!P0 STG.E [R4.64+0x4], R11 ; /* 0x0000040b04008986 */
/* 0x0001e4000c101906 */
/*0540*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0550*/ BSSY B0, 0x5d0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0560*/ @P1 BRA 0x5c0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*0580*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*0590*/ ISETP.GE.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x004fda0003f06270 */
/*05a0*/ @!P0 STG.E [R4.64], R0 ; /* 0x0000000004008986 */
/* 0x0001e8000c101906 */
/*05b0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e4000c101906 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0610*/ @P0 BRA 0x470 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
#define MAIN "_MAIN_:"
#define F1LO "_ODD_:"
#define CTRL "_CRTL_:"
#define ARRAY_SIZE 100000
#define TILE_WIDTH 128
#define DEVICE 1 //device 0 o 1
__device__
inline void SWAP(int32_t *_a,int32_t *_b){int32_t __aux; __aux = *_a; *_a = *_b; *_b = __aux;}
/*###################################
########### KERNELS ###########
###################################*/
__global__
void odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t t_position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
int32_t i_limit = blockDim.x*2;
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && t_position< n-1 && tid < blockDim.x*2-1 ) { // impar
if (*(arr_d+t_position + 1) < *(arr_d+t_position)) {
SWAP(arr_d + t_position, arr_d + t_position + 1);
}
}
if(!(i&1) && t_position < n && tid < blockDim.x*2){ //par
if (*(arr_d+t_position) < *(arr_d+t_position-1)) {
SWAP(arr_d + t_position, arr_d + t_position - 1);
}
}
__syncthreads();
}
}
__global__
void fast_odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
__shared__ int32_t sh_arr[2*TILE_WIDTH];
int32_t bound = blockDim.x*2;
int32_t i_limit = blockDim.x*2;
if(position < n){
*(sh_arr+tid)=*(arr_d+position);
*(sh_arr+tid-1)=*(arr_d+position-1);
__syncthreads();
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && position< n-1 && tid < bound-1 ) { // impar
if (*(sh_arr+tid + 1) < *(sh_arr+tid)) {
SWAP(sh_arr + tid, sh_arr + tid + 1);
}
}
if(!(i&1) && position < n && tid < bound){ //par
if (*(sh_arr+tid) < *(sh_arr+tid-1)) {
SWAP(sh_arr + tid, sh_arr + tid - 1);
}
}
__syncthreads();
}
*(arr_d+position) = *(sh_arr+tid);
*(arr_d+position-1) = *(sh_arr+tid-1);
}
}
/*##########################################
########### HOST FUNCTIONS ###########
##########################################*/
__host__
void odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
cudaError_t err;
cudaEvent_t start, stop;
float mili;
err = cudaMalloc((void**)&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
cudaEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
cudaEventRecord(stop);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
cudaEventElapsedTime(&mili, start, stop);
cudaMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
cudaFree(cuda_d);
}
__host__
void fast_odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
//float tile = TILE_WIDTH , size_t = ARRAY_SIZE;
//dim3 dimGrid ((uint)ceil(size_t/tile), 1, 1);
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
cudaError_t err;
cudaEvent_t start, stop;
float mili;
err = cudaMalloc(&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
cudaEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
fast_odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
cudaEventRecord(stop);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
cudaEventElapsedTime(&mili, start, stop);
cudaMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
cudaFree(cuda_d);
}
__host__
int control(int32_t *arr, int32_t n){
for(int32_t i=1; i<n; i++){
if(arr[i-1] > arr[i]){
printf("%s I = %d\n", CTRL, i);
return 1;
}
}
return 0;
}
/*###################################
########### MAIN ###########
###################################*/
int main( int argc, char *argv[] ){
int32_t *arr;
cudaError_t err;
arr = (int32_t*)malloc(sizeof(int32_t)*ARRAY_SIZE);
printf("array size: %d tile: %d\n",ARRAY_SIZE, TILE_WIDTH);
printf("#### SORT WHIT GLOBAL MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000+1;
// printf("%d ", arr[i]);
}
arr[0]=1001;
arr[ARRAY_SIZE-1]=0;
printf("\n");
err = cudaSetDevice(DEVICE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
printf("#### SORT WHIT SHARED MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000;
// printf("%d ", arr[i]);
}
printf("\n");
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
fast_odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
free(arr);
printf("\n");
return 0;
} | .file "tmpxft_001b59cc_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_CRTL_:"
.LC1:
.string "%s I = %d\n"
.text
.globl _Z7controlPii
.type _Z7controlPii, @function
_Z7controlPii:
.LFB2060:
.cfi_startproc
endbr64
cmpl $1, %esi
jle .L7
movl %esi, %esi
movl $1, %ecx
.L6:
movl (%rdi,%rcx,4), %eax
cmpl %eax, -4(%rdi,%rcx,4)
jg .L13
addq $1, %rcx
cmpq %rsi, %rcx
jne .L6
movl $0, %eax
ret
.L13:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L7:
movl $0, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z7controlPii, .-_Z7controlPii
.globl _Z41__device_stub__Z20odd_even_sort_kernelPiiPii
.type _Z41__device_stub__Z20odd_even_sort_kernelPiiPii, @function
_Z41__device_stub__Z20odd_even_sort_kernelPiiPii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20odd_even_sort_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z41__device_stub__Z20odd_even_sort_kernelPiiPii, .-_Z41__device_stub__Z20odd_even_sort_kernelPiiPii
.globl _Z20odd_even_sort_kernelPii
.type _Z20odd_even_sort_kernelPii, @function
_Z20odd_even_sort_kernelPii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z20odd_even_sort_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z20odd_even_sort_kernelPii, .-_Z20odd_even_sort_kernelPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/iotincho/TP_cuda/master/main.cu"
.section .rodata.str1.1
.LC3:
.string "%s in %s at line %d\n"
.LC4:
.string "_ODD_:"
.LC5:
.string "%s ordenando..\n"
.LC7:
.string "%s terminanding.. time: %f s\n"
.text
.globl _Z13odd_even_sortPii
.type _Z13odd_even_sortPii, @function
_Z13odd_even_sortPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $782, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $400000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 127(%r13), %ebp
testl %r13d, %r13d
cmovns %r13d, %ebp
sarl $7, %ebp
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $-127, %r13d
jl .L24
addl $1, %ebp
movl $0, %ebx
jmp .L26
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $99, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
addl $1, %ebx
cmpl %ebx, %ebp
je .L24
.L26:
movq 8(%rsp), %r12
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl %ebx, %eax
andl $1, %eax
sall $7, %eax
movl %r13d, %esi
subl %eax, %esi
cltq
leaq (%r12,%rax,4), %rdi
call _Z41__device_stub__Z20odd_even_sort_kernelPiiPii
jmp .L25
.L24:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $400000, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movss 4(%rsp), %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13odd_even_sortPii, .-_Z13odd_even_sortPii
.globl _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
.type _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii, @function
_Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25fast_odd_even_sort_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii, .-_Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
.globl _Z25fast_odd_even_sort_kernelPii
.type _Z25fast_odd_even_sort_kernelPii, @function
_Z25fast_odd_even_sort_kernelPii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z25fast_odd_even_sort_kernelPii, .-_Z25fast_odd_even_sort_kernelPii
.globl _Z18fast_odd_even_sortPii
.type _Z18fast_odd_even_sortPii, @function
_Z18fast_odd_even_sortPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $782, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L48
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $400000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 127(%r13), %ebp
testl %r13d, %r13d
cmovns %r13d, %ebp
sarl $7, %ebp
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $-127, %r13d
jl .L42
addl $1, %ebp
movl $0, %ebx
jmp .L44
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $142, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
addl $1, %ebx
cmpl %ebx, %ebp
je .L42
.L44:
movq 8(%rsp), %r12
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl %ebx, %eax
andl $1, %eax
sall $7, %eax
movl %r13d, %esi
subl %eax, %esi
cltq
leaq (%r12,%rax,4), %rdi
call _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
jmp .L43
.L42:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $400000, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movss 4(%rsp), %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z18fast_odd_even_sortPii, .-_Z18fast_odd_even_sortPii
.section .rodata.str1.1
.LC8:
.string "array size: %d tile: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "#### SORT WHIT GLOBAL MEMORY ####\n"
.section .rodata.str1.1
.LC10:
.string "\n"
.LC11:
.string "_MAIN_:"
.LC12:
.string "%s desordenado!! \n"
.LC13:
.string "%s ok!! \n"
.section .rodata.str1.8
.align 8
.LC14:
.string "#### SORT WHIT SHARED MEMORY ####\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $400000, %edi
call malloc@PLT
movq %rax, %r13
movl $128, %ecx
movl $100000, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbp
leaq 400000(%r13), %r12
movq %r13, %rbx
.L51:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L51
movl $1001, 0(%r13)
movl $0, 399996(%r13)
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L65
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L53
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L54:
movl $100000, %esi
movq %r13, %rdi
call _Z13odd_even_sortPii
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L55
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L56:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L57:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L57
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L58
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L59:
movl $100000, %esi
movq %r13, %rdi
call _Z18fast_odd_even_sortPii
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L60
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L61:
movq %r13, %rdi
call free@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $209, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L55:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L58:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.L60:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L61
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z25fast_odd_even_sort_kernelPii"
.section .rodata.str1.1
.LC16:
.string "_Z20odd_even_sort_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z25fast_odd_even_sort_kernelPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z20odd_even_sort_kernelPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
#define MAIN "_MAIN_:"
#define F1LO "_ODD_:"
#define CTRL "_CRTL_:"
#define ARRAY_SIZE 100000
#define TILE_WIDTH 128
#define DEVICE 1 //device 0 o 1
__device__
inline void SWAP(int32_t *_a,int32_t *_b){int32_t __aux; __aux = *_a; *_a = *_b; *_b = __aux;}
/*###################################
########### KERNELS ###########
###################################*/
__global__
void odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t t_position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
int32_t i_limit = blockDim.x*2;
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && t_position< n-1 && tid < blockDim.x*2-1 ) { // impar
if (*(arr_d+t_position + 1) < *(arr_d+t_position)) {
SWAP(arr_d + t_position, arr_d + t_position + 1);
}
}
if(!(i&1) && t_position < n && tid < blockDim.x*2){ //par
if (*(arr_d+t_position) < *(arr_d+t_position-1)) {
SWAP(arr_d + t_position, arr_d + t_position - 1);
}
}
__syncthreads();
}
}
__global__
void fast_odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
__shared__ int32_t sh_arr[2*TILE_WIDTH];
int32_t bound = blockDim.x*2;
int32_t i_limit = blockDim.x*2;
if(position < n){
*(sh_arr+tid)=*(arr_d+position);
*(sh_arr+tid-1)=*(arr_d+position-1);
__syncthreads();
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && position< n-1 && tid < bound-1 ) { // impar
if (*(sh_arr+tid + 1) < *(sh_arr+tid)) {
SWAP(sh_arr + tid, sh_arr + tid + 1);
}
}
if(!(i&1) && position < n && tid < bound){ //par
if (*(sh_arr+tid) < *(sh_arr+tid-1)) {
SWAP(sh_arr + tid, sh_arr + tid - 1);
}
}
__syncthreads();
}
*(arr_d+position) = *(sh_arr+tid);
*(arr_d+position-1) = *(sh_arr+tid-1);
}
}
/*##########################################
########### HOST FUNCTIONS ###########
##########################################*/
__host__
void odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
cudaError_t err;
cudaEvent_t start, stop;
float mili;
err = cudaMalloc((void**)&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
cudaEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
cudaEventRecord(stop);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
cudaEventElapsedTime(&mili, start, stop);
cudaMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
cudaFree(cuda_d);
}
__host__
void fast_odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
//float tile = TILE_WIDTH , size_t = ARRAY_SIZE;
//dim3 dimGrid ((uint)ceil(size_t/tile), 1, 1);
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
cudaError_t err;
cudaEvent_t start, stop;
float mili;
err = cudaMalloc(&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
cudaEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
fast_odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
cudaEventRecord(stop);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
cudaEventElapsedTime(&mili, start, stop);
cudaMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
cudaFree(cuda_d);
}
__host__
int control(int32_t *arr, int32_t n){
for(int32_t i=1; i<n; i++){
if(arr[i-1] > arr[i]){
printf("%s I = %d\n", CTRL, i);
return 1;
}
}
return 0;
}
/*###################################
########### MAIN ###########
###################################*/
int main( int argc, char *argv[] ){
int32_t *arr;
cudaError_t err;
arr = (int32_t*)malloc(sizeof(int32_t)*ARRAY_SIZE);
printf("array size: %d tile: %d\n",ARRAY_SIZE, TILE_WIDTH);
printf("#### SORT WHIT GLOBAL MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000+1;
// printf("%d ", arr[i]);
}
arr[0]=1001;
arr[ARRAY_SIZE-1]=0;
printf("\n");
err = cudaSetDevice(DEVICE);
if( err != cudaSuccess){
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
printf("#### SORT WHIT SHARED MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000;
// printf("%d ", arr[i]);
}
printf("\n");
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
fast_odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
free(arr);
printf("\n");
return 0;
} | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#define MAIN "_MAIN_:"
#define F1LO "_ODD_:"
#define CTRL "_CRTL_:"
#define ARRAY_SIZE 100000
#define TILE_WIDTH 128
#define DEVICE 1 //device 0 o 1
__device__
inline void SWAP(int32_t *_a,int32_t *_b){int32_t __aux; __aux = *_a; *_a = *_b; *_b = __aux;}
/*###################################
########### KERNELS ###########
###################################*/
__global__
void odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t t_position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
int32_t i_limit = blockDim.x*2;
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && t_position< n-1 && tid < blockDim.x*2-1 ) { // impar
if (*(arr_d+t_position + 1) < *(arr_d+t_position)) {
SWAP(arr_d + t_position, arr_d + t_position + 1);
}
}
if(!(i&1) && t_position < n && tid < blockDim.x*2){ //par
if (*(arr_d+t_position) < *(arr_d+t_position-1)) {
SWAP(arr_d + t_position, arr_d + t_position - 1);
}
}
__syncthreads();
}
}
__global__
void fast_odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
__shared__ int32_t sh_arr[2*TILE_WIDTH];
int32_t bound = blockDim.x*2;
int32_t i_limit = blockDim.x*2;
if(position < n){
*(sh_arr+tid)=*(arr_d+position);
*(sh_arr+tid-1)=*(arr_d+position-1);
__syncthreads();
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && position< n-1 && tid < bound-1 ) { // impar
if (*(sh_arr+tid + 1) < *(sh_arr+tid)) {
SWAP(sh_arr + tid, sh_arr + tid + 1);
}
}
if(!(i&1) && position < n && tid < bound){ //par
if (*(sh_arr+tid) < *(sh_arr+tid-1)) {
SWAP(sh_arr + tid, sh_arr + tid - 1);
}
}
__syncthreads();
}
*(arr_d+position) = *(sh_arr+tid);
*(arr_d+position-1) = *(sh_arr+tid-1);
}
}
/*##########################################
########### HOST FUNCTIONS ###########
##########################################*/
__host__
void odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
hipError_t err;
hipEvent_t start, stop;
float mili;
err = hipMalloc((void**)&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
hipEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
hipEventRecord(stop);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
hipEventElapsedTime(&mili, start, stop);
hipMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
hipFree(cuda_d);
}
__host__
void fast_odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
//float tile = TILE_WIDTH , size_t = ARRAY_SIZE;
//dim3 dimGrid ((uint)ceil(size_t/tile), 1, 1);
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
hipError_t err;
hipEvent_t start, stop;
float mili;
err = hipMalloc(&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
hipEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
fast_odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
hipEventRecord(stop);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
hipEventElapsedTime(&mili, start, stop);
hipMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
hipFree(cuda_d);
}
__host__
int control(int32_t *arr, int32_t n){
for(int32_t i=1; i<n; i++){
if(arr[i-1] > arr[i]){
printf("%s I = %d\n", CTRL, i);
return 1;
}
}
return 0;
}
/*###################################
########### MAIN ###########
###################################*/
int main( int argc, char *argv[] ){
int32_t *arr;
hipError_t err;
arr = (int32_t*)malloc(sizeof(int32_t)*ARRAY_SIZE);
printf("array size: %d tile: %d\n",ARRAY_SIZE, TILE_WIDTH);
printf("#### SORT WHIT GLOBAL MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000+1;
// printf("%d ", arr[i]);
}
arr[0]=1001;
arr[ARRAY_SIZE-1]=0;
printf("\n");
err = hipSetDevice(DEVICE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
printf("#### SORT WHIT SHARED MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000;
// printf("%d ", arr[i]);
}
printf("\n");
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
fast_odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
free(arr);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#define MAIN "_MAIN_:"
#define F1LO "_ODD_:"
#define CTRL "_CRTL_:"
#define ARRAY_SIZE 100000
#define TILE_WIDTH 128
#define DEVICE 1 //device 0 o 1
__device__
inline void SWAP(int32_t *_a,int32_t *_b){int32_t __aux; __aux = *_a; *_a = *_b; *_b = __aux;}
/*###################################
########### KERNELS ###########
###################################*/
__global__
void odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t t_position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
int32_t i_limit = blockDim.x*2;
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && t_position< n-1 && tid < blockDim.x*2-1 ) { // impar
if (*(arr_d+t_position + 1) < *(arr_d+t_position)) {
SWAP(arr_d + t_position, arr_d + t_position + 1);
}
}
if(!(i&1) && t_position < n && tid < blockDim.x*2){ //par
if (*(arr_d+t_position) < *(arr_d+t_position-1)) {
SWAP(arr_d + t_position, arr_d + t_position - 1);
}
}
__syncthreads();
}
}
__global__
void fast_odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
__shared__ int32_t sh_arr[2*TILE_WIDTH];
int32_t bound = blockDim.x*2;
int32_t i_limit = blockDim.x*2;
if(position < n){
*(sh_arr+tid)=*(arr_d+position);
*(sh_arr+tid-1)=*(arr_d+position-1);
__syncthreads();
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && position< n-1 && tid < bound-1 ) { // impar
if (*(sh_arr+tid + 1) < *(sh_arr+tid)) {
SWAP(sh_arr + tid, sh_arr + tid + 1);
}
}
if(!(i&1) && position < n && tid < bound){ //par
if (*(sh_arr+tid) < *(sh_arr+tid-1)) {
SWAP(sh_arr + tid, sh_arr + tid - 1);
}
}
__syncthreads();
}
*(arr_d+position) = *(sh_arr+tid);
*(arr_d+position-1) = *(sh_arr+tid-1);
}
}
/*##########################################
########### HOST FUNCTIONS ###########
##########################################*/
__host__
void odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
hipError_t err;
hipEvent_t start, stop;
float mili;
err = hipMalloc((void**)&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
hipEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
hipEventRecord(stop);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
hipEventElapsedTime(&mili, start, stop);
hipMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
hipFree(cuda_d);
}
__host__
void fast_odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
//float tile = TILE_WIDTH , size_t = ARRAY_SIZE;
//dim3 dimGrid ((uint)ceil(size_t/tile), 1, 1);
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
hipError_t err;
hipEvent_t start, stop;
float mili;
err = hipMalloc(&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
hipEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
fast_odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
hipEventRecord(stop);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
hipEventElapsedTime(&mili, start, stop);
hipMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
hipFree(cuda_d);
}
__host__
int control(int32_t *arr, int32_t n){
for(int32_t i=1; i<n; i++){
if(arr[i-1] > arr[i]){
printf("%s I = %d\n", CTRL, i);
return 1;
}
}
return 0;
}
/*###################################
########### MAIN ###########
###################################*/
int main( int argc, char *argv[] ){
int32_t *arr;
hipError_t err;
arr = (int32_t*)malloc(sizeof(int32_t)*ARRAY_SIZE);
printf("array size: %d tile: %d\n",ARRAY_SIZE, TILE_WIDTH);
printf("#### SORT WHIT GLOBAL MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000+1;
// printf("%d ", arr[i]);
}
arr[0]=1001;
arr[ARRAY_SIZE-1]=0;
printf("\n");
err = hipSetDevice(DEVICE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
printf("#### SORT WHIT SHARED MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000;
// printf("%d ", arr[i]);
}
printf("\n");
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
fast_odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
free(arr);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20odd_even_sort_kernelPii
.globl _Z20odd_even_sort_kernelPii
.p2align 8
.type _Z20odd_even_sort_kernelPii,@function
_Z20odd_even_sort_kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_9
s_and_b32 s5, 0xffff, s2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_lshl_or_b32 v4, v0, 1, 1
s_lshl_b32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s0, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v1, v1, 1, 1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s6, -1
v_cmp_gt_i32_e64 s0, s6, v1
v_cmp_gt_i32_e64 s1, s1, v1
v_add_co_u32 v0, s2, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, s3, v3, s2
v_cmp_gt_u32_e64 s2, s5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s4, s4, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s5, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_and_b32 s3, s4, 1
s_and_b32 s7, 1, s4
s_cmp_eq_u32 s3, 0
s_cselect_b32 s6, -1, 0
s_cmp_eq_u32 s7, 1
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s3
s_cbranch_execz .LBB0_6
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s3, v3, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v4, v2
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_and_b32 s3, s6, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_and_saveexec_b32 s6, s3
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v2, v[0:1], off
global_load_b32 v3, v[0:1], off offset:-4
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s3, v2, v3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_2
s_clause 0x1
global_store_b32 v[0:1], v3, off
global_store_b32 v[0:1], v2, off offset:-4
s_branch .LBB0_2
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20odd_even_sort_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20odd_even_sort_kernelPii, .Lfunc_end0-_Z20odd_even_sort_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25fast_odd_even_sort_kernelPii
.globl _Z25fast_odd_even_sort_kernelPii
.p2align 8
.type _Z25fast_odd_even_sort_kernelPii,@function
_Z25fast_odd_even_sort_kernelPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_lshl_or_b32 v3, v1, 1, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_lshl_or_b32 v4, v0, 1, 1
v_lshlrev_b32_e32 v0, 2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v5, -4, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_eq_u16_e64 s0, s3, 0
s_mov_b32 s3, 0
global_load_b64 v[6:7], v[1:2], off offset:-4
s_and_b32 vcc_lo, exec_lo, s0
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[6:7]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_10
s_lshl_b32 s4, s4, 1
s_add_i32 s2, s2, -1
s_add_i32 s0, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v3
v_cmp_gt_i32_e64 s0, s0, v4
v_cmp_gt_u32_e64 s1, s4, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_10
.LBB1_4:
s_and_b32 s2, s3, 1
s_and_b32 s6, 1, s3
s_cmp_eq_u32 s2, 0
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s6, 1
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB1_7
ds_load_2addr_b32 v[3:4], v0 offset1:1
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s2, v4, v3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_7
ds_store_2addr_b32 v0, v4, v3 offset1:1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s6
s_and_b32 s2, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_3
ds_load_b32 v3, v0
ds_load_b32 v4, v5
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_3
ds_store_b32 v0, v4
ds_store_b32 v5, v3
s_branch .LBB1_3
.LBB1_10:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v0
ds_load_b32 v3, v5
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v0, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v3, off offset:-4
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fast_odd_even_sort_kernelPii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25fast_odd_even_sort_kernelPii, .Lfunc_end1-_Z25fast_odd_even_sort_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20odd_even_sort_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20odd_even_sort_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fast_odd_even_sort_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fast_odd_even_sort_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#define MAIN "_MAIN_:"
#define F1LO "_ODD_:"
#define CTRL "_CRTL_:"
#define ARRAY_SIZE 100000
#define TILE_WIDTH 128
#define DEVICE 1 //device 0 o 1
__device__
inline void SWAP(int32_t *_a,int32_t *_b){int32_t __aux; __aux = *_a; *_a = *_b; *_b = __aux;}
/*###################################
########### KERNELS ###########
###################################*/
__global__
void odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t t_position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
int32_t i_limit = blockDim.x*2;
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && t_position< n-1 && tid < blockDim.x*2-1 ) { // impar
if (*(arr_d+t_position + 1) < *(arr_d+t_position)) {
SWAP(arr_d + t_position, arr_d + t_position + 1);
}
}
if(!(i&1) && t_position < n && tid < blockDim.x*2){ //par
if (*(arr_d+t_position) < *(arr_d+t_position-1)) {
SWAP(arr_d + t_position, arr_d + t_position - 1);
}
}
__syncthreads();
}
}
__global__
void fast_odd_even_sort_kernel(int32_t * arr_d, int32_t n){
int32_t position = (blockDim.x * blockIdx.x + threadIdx.x)*2 + 1;// +1 corresponde para evitar el overflow en el 0
int32_t tid = threadIdx.x*2+1;
__shared__ int32_t sh_arr[2*TILE_WIDTH];
int32_t bound = blockDim.x*2;
int32_t i_limit = blockDim.x*2;
if(position < n){
*(sh_arr+tid)=*(arr_d+position);
*(sh_arr+tid-1)=*(arr_d+position-1);
__syncthreads();
for(int32_t i=0; i<i_limit;i++){
if ((i&1) && position< n-1 && tid < bound-1 ) { // impar
if (*(sh_arr+tid + 1) < *(sh_arr+tid)) {
SWAP(sh_arr + tid, sh_arr + tid + 1);
}
}
if(!(i&1) && position < n && tid < bound){ //par
if (*(sh_arr+tid) < *(sh_arr+tid-1)) {
SWAP(sh_arr + tid, sh_arr + tid - 1);
}
}
__syncthreads();
}
*(arr_d+position) = *(sh_arr+tid);
*(arr_d+position-1) = *(sh_arr+tid-1);
}
}
/*##########################################
########### HOST FUNCTIONS ###########
##########################################*/
__host__
void odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
hipError_t err;
hipEvent_t start, stop;
float mili;
err = hipMalloc((void**)&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
hipEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
hipEventRecord(stop);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
hipEventElapsedTime(&mili, start, stop);
hipMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
hipFree(cuda_d);
}
__host__
void fast_odd_even_sort(int32_t * arr, int32_t n){
int32_t *cuda_d;
//float tile = TILE_WIDTH , size_t = ARRAY_SIZE;
//dim3 dimGrid ((uint)ceil(size_t/tile), 1, 1);
dim3 dimGrid ((uint)((ARRAY_SIZE / TILE_WIDTH)+1), 1, 1);
dim3 dimBlock (TILE_WIDTH, 1, 1);
hipError_t err;
hipEvent_t start, stop;
float mili;
err = hipMalloc(&cuda_d, sizeof(int32_t)*ARRAY_SIZE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(cuda_d, arr, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyHostToDevice);
int32_t j_limit = n/TILE_WIDTH+1;
int32_t *p_cuda;
int32_t size;
printf("%s ordenando..\n",F1LO);
hipEventRecord(start);
for(int32_t j=0;j<j_limit;j++){
p_cuda = cuda_d + (j&1) * TILE_WIDTH;
size = n - (j&1) * TILE_WIDTH;
fast_odd_even_sort_kernel<<<dimGrid, dimBlock>>>(p_cuda, size);
}
hipEventRecord(stop);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
hipEventElapsedTime(&mili, start, stop);
hipMemcpy(arr, cuda_d, sizeof(int32_t)*ARRAY_SIZE, hipMemcpyDeviceToHost);
printf("%s terminanding.. time: %f s\n", F1LO, mili/1000);
hipFree(cuda_d);
}
__host__
int control(int32_t *arr, int32_t n){
for(int32_t i=1; i<n; i++){
if(arr[i-1] > arr[i]){
printf("%s I = %d\n", CTRL, i);
return 1;
}
}
return 0;
}
/*###################################
########### MAIN ###########
###################################*/
int main( int argc, char *argv[] ){
int32_t *arr;
hipError_t err;
arr = (int32_t*)malloc(sizeof(int32_t)*ARRAY_SIZE);
printf("array size: %d tile: %d\n",ARRAY_SIZE, TILE_WIDTH);
printf("#### SORT WHIT GLOBAL MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000+1;
// printf("%d ", arr[i]);
}
arr[0]=1001;
arr[ARRAY_SIZE-1]=0;
printf("\n");
err = hipSetDevice(DEVICE);
if( err != hipSuccess){
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__); // best definition
exit(EXIT_FAILURE);
}
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
printf("#### SORT WHIT SHARED MEMORY ####\n" );
for (int i = 0; i < ARRAY_SIZE; i++) {
arr[i] = rand()%1000;
// printf("%d ", arr[i]);
}
printf("\n");
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n",MAIN);
fast_odd_even_sort(arr,ARRAY_SIZE);
if(control(arr, ARRAY_SIZE)) printf("%s desordenado!! \n",MAIN);
else printf("%s ok!! \n" ,MAIN);
free(arr);
printf("\n");
return 0;
} | .text
.file "main.hip"
.globl _Z35__device_stub__odd_even_sort_kernelPii # -- Begin function _Z35__device_stub__odd_even_sort_kernelPii
.p2align 4, 0x90
.type _Z35__device_stub__odd_even_sort_kernelPii,@function
_Z35__device_stub__odd_even_sort_kernelPii: # @_Z35__device_stub__odd_even_sort_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20odd_even_sort_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__odd_even_sort_kernelPii, .Lfunc_end0-_Z35__device_stub__odd_even_sort_kernelPii
.cfi_endproc
# -- End function
.globl _Z40__device_stub__fast_odd_even_sort_kernelPii # -- Begin function _Z40__device_stub__fast_odd_even_sort_kernelPii
.p2align 4, 0x90
.type _Z40__device_stub__fast_odd_even_sort_kernelPii,@function
_Z40__device_stub__fast_odd_even_sort_kernelPii: # @_Z40__device_stub__fast_odd_even_sort_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25fast_odd_even_sort_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z40__device_stub__fast_odd_even_sort_kernelPii, .Lfunc_end1-_Z40__device_stub__fast_odd_even_sort_kernelPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13odd_even_sortPii
.LCPI2_0:
.long 0x447a0000 # float 1000
.text
.globl _Z13odd_even_sortPii
.p2align 4, 0x90
.type _Z13odd_even_sortPii,@function
_Z13odd_even_sortPii: # @_Z13odd_even_sortPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movq %rdi, %rbx
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB2_7
# %bb.1:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq (%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movl $.L.str.2, %edi
movl $.L.str.3, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $-127, %r14d
jge .LBB2_2
.LBB2_6: # %._crit_edge
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq (%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movl $.L.str.3, %esi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_2: # %.lr.ph
.cfi_def_cfa_offset 176
movabsq $4294967424, %r15 # imm = 0x100000080
leal 127(%r14), %r13d
testl %r14d, %r14d
cmovnsl %r14d, %r13d
sarl $7, %r13d
incl %r13d
leaq 654(%r15), %r12
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
subl $-128, %ebx
decl %r13d
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rbp
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl %ebx, %eax
andl $128, %eax
movl %r14d, %ecx
subl %eax, %ecx
leaq (,%rax,4), %rax
addq %rbp, %rax
movq %rax, 112(%rsp)
movl %ecx, 20(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 20(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z20odd_even_sort_kernelPii, %edi
leaq 32(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.LBB2_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $99, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z13odd_even_sortPii, .Lfunc_end2-_Z13odd_even_sortPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z18fast_odd_even_sortPii
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl _Z18fast_odd_even_sortPii
.p2align 4, 0x90
.type _Z18fast_odd_even_sortPii,@function
_Z18fast_odd_even_sortPii: # @_Z18fast_odd_even_sortPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movq %rdi, %rbx
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB3_7
# %bb.1:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq (%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movl $.L.str.2, %edi
movl $.L.str.3, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $-127, %r14d
jge .LBB3_2
.LBB3_6: # %._crit_edge
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq (%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movl $.L.str.3, %esi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_2: # %.lr.ph
.cfi_def_cfa_offset 176
movabsq $4294967424, %r15 # imm = 0x100000080
leal 127(%r14), %r13d
testl %r14d, %r14d
cmovnsl %r14d, %r13d
sarl $7, %r13d
incl %r13d
leaq 654(%r15), %r12
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
subl $-128, %ebx
decl %r13d
je .LBB3_6
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rbp
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl %ebx, %eax
andl $128, %eax
movl %r14d, %ecx
subl %eax, %ecx
leaq (,%rax,4), %rax
addq %rbp, %rax
movq %rax, 112(%rsp)
movl %ecx, 20(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 20(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z25fast_odd_even_sort_kernelPii, %edi
leaq 32(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_5
.LBB3_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $142, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z18fast_odd_even_sortPii, .Lfunc_end3-_Z18fast_odd_even_sortPii
.cfi_endproc
# -- End function
.globl _Z7controlPii # -- Begin function _Z7controlPii
.p2align 4, 0x90
.type _Z7controlPii,@function
_Z7controlPii: # @_Z7controlPii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpl $2, %esi
setge %bl
jl .LBB4_8
# %bb.1: # %.lr.ph.preheader
movl (%rdi), %eax
movl $1, %edx
cmpl 4(%rdi), %eax
jg .LBB4_6
# %bb.2: # %.lr.ph22.preheader
movl %esi, %eax
movl $2, %ecx
subq %rax, %rcx
movl $1, %esi
.p2align 4, 0x90
.LBB4_3: # %.lr.ph22
# =>This Inner Loop Header: Depth=1
leaq (%rcx,%rsi), %rdx
cmpq $1, %rdx
je .LBB4_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB4_3 Depth=1
movl (%rdi,%rsi,4), %r8d
leaq 1(%rsi), %rdx
cmpl 4(%rdi,%rsi,4), %r8d
movq %rdx, %rsi
jle .LBB4_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %rax, %rdx
setb %bl
.LBB4_6:
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB4_8
.LBB4_7: # %.loopexit.loopexit
incq %rsi
cmpq %rax, %rsi
setb %bl
.LBB4_8: # %.loopexit
movzbl %bl, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z7controlPii, .Lfunc_end4-_Z7controlPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
movl $.L.str.7, %edi
movl $100000, %esi # imm = 0x186A0
movl $128, %edx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB5_1
# %bb.2:
movl $1001, (%rbx) # imm = 0x3E9
movl $0, 399996(%rbx)
movl $10, %edi
callq putchar@PLT
movl $1, %r14d
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_7
# %bb.3: # %.lr.ph.i.preheader
movl (%rbx), %eax
movb $1, %bpl
cmpl 4(%rbx), %eax
jg .LBB5_10
# %bb.4: # %.lr.ph.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_6
# %bb.8: # %.lr.ph.i
# in Loop: Header=BB5_5 Depth=1
movl (%rbx,%rcx,4), %edx
decq %rax
leaq 1(%rcx), %r14
cmpl 4(%rbx,%rcx,4), %edx
movq %r14, %rcx
jle .LBB5_5
# %bb.9: # %.lr.ph.i._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_10: # %.lr.ph.i._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
jmp .LBB5_11
.LBB5_6: # %_Z7controlPii.exit.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_11: # %_Z7controlPii.exit
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl $100000, %esi # imm = 0x186A0
callq _Z13odd_even_sortPii
movl (%rbx), %eax
cmpl 4(%rbx), %eax
jle .LBB5_16
# %bb.12:
movb $1, %bpl
movl $1, %edx
jmp .LBB5_15
.LBB5_16: # %.lr.ph66.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_17: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_18
# %bb.13: # %.lr.ph.i27
# in Loop: Header=BB5_17 Depth=1
movl (%rbx,%rcx,4), %esi
decq %rax
leaq 1(%rcx), %rdx
cmpl 4(%rbx,%rcx,4), %esi
movq %rdx, %rcx
jle .LBB5_17
# %bb.14: # %.lr.ph.i27._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_15: # %.lr.ph.i27._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB5_19
.LBB5_18: # %_Z7controlPii.exit35.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_19: # %_Z7controlPii.exit35
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
xorl %r14d, %r14d
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB5_20: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB5_20
# %bb.21:
movl $10, %edi
callq putchar@PLT
movl (%rbx), %eax
cmpl 4(%rbx), %eax
jle .LBB5_26
# %bb.22:
movb $1, %bpl
movl $1, %edx
jmp .LBB5_25
.LBB5_26: # %.lr.ph71.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_27: # %.lr.ph71
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_28
# %bb.23: # %.lr.ph.i36
# in Loop: Header=BB5_27 Depth=1
movl (%rbx,%rcx,4), %esi
decq %rax
leaq 1(%rcx), %rdx
cmpl 4(%rbx,%rcx,4), %esi
movq %rdx, %rcx
jle .LBB5_27
# %bb.24: # %.lr.ph.i36._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_25: # %.lr.ph.i36._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB5_29
.LBB5_28: # %_Z7controlPii.exit44.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_29: # %_Z7controlPii.exit44
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl $100000, %esi # imm = 0x186A0
callq _Z18fast_odd_even_sortPii
movl (%rbx), %eax
cmpl 4(%rbx), %eax
jle .LBB5_34
# %bb.30:
movb $1, %bpl
movl $1, %edx
jmp .LBB5_33
.LBB5_34: # %.lr.ph75.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_35: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_36
# %bb.31: # %.lr.ph.i45
# in Loop: Header=BB5_35 Depth=1
movl (%rbx,%rcx,4), %esi
decq %rax
leaq 1(%rcx), %rdx
cmpl 4(%rbx,%rcx,4), %esi
movq %rdx, %rcx
jle .LBB5_35
# %bb.32: # %.lr.ph.i45._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_33: # %.lr.ph.i45._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB5_37
.LBB5_36: # %_Z7controlPii.exit53.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_37: # %_Z7controlPii.exit53
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_7:
.cfi_def_cfa_offset 32
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $209, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20odd_even_sort_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fast_odd_even_sort_kernelPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20odd_even_sort_kernelPii,@object # @_Z20odd_even_sort_kernelPii
.section .rodata,"a",@progbits
.globl _Z20odd_even_sort_kernelPii
.p2align 3, 0x0
_Z20odd_even_sort_kernelPii:
.quad _Z35__device_stub__odd_even_sort_kernelPii
.size _Z20odd_even_sort_kernelPii, 8
.type _Z25fast_odd_even_sort_kernelPii,@object # @_Z25fast_odd_even_sort_kernelPii
.globl _Z25fast_odd_even_sort_kernelPii
.p2align 3, 0x0
_Z25fast_odd_even_sort_kernelPii:
.quad _Z40__device_stub__fast_odd_even_sort_kernelPii
.size _Z25fast_odd_even_sort_kernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/iotincho/TP_cuda/master/main.hip"
.size .L.str.1, 90
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s ordenando..\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "_ODD_:"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s terminanding.. time: %f s\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s I = %d\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "_CRTL_:"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "array size: %d tile: %d\n"
.size .L.str.7, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%s desordenado!! \n"
.size .L.str.10, 19
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "_MAIN_:"
.size .L.str.11, 8
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%s ok!! \n"
.size .L.str.12, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20odd_even_sort_kernelPii"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25fast_odd_even_sort_kernelPii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "#### SORT WHIT GLOBAL MEMORY ####"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "#### SORT WHIT SHARED MEMORY ####"
.size .Lstr.1, 38
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__odd_even_sort_kernelPii
.addrsig_sym _Z40__device_stub__fast_odd_even_sort_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20odd_even_sort_kernelPii
.addrsig_sym _Z25fast_odd_even_sort_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25fast_odd_even_sort_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0207 */
/*0040*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x000fca00078e00ff */
/*0050*/ IADD3 R0, R4, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00c0*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ LEA R6, R7, 0x1, 0x1 ; /* 0x0000000107067811 */
/* 0x000fe200078e08ff */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fca00078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f06270 */
/*0120*/ STS [R6.X4], R9 ; /* 0x0000000906007388 */
/* 0x0041e80000004800 */
/*0130*/ STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b06007388 */
/* 0x0081e80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P0 BRA 0x670 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R9, R7.reuse, -0x1, RZ ; /* 0xffffffff07097810 */
/* 0x041fe20007ffe0ff */
/*0170*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0180*/ LOP3.LUT R8, R7, 0x2, RZ, 0xc0, !PT ; /* 0x0000000207087812 */
/* 0x000fe200078ec0ff */
/*0190*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe20003f06070 */
/*01b0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe2000fffe13f */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd600078e00ff */
/*01d0*/ @!P0 BRA 0x4b0 ; /* 0x000002d000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*01f0*/ IMAD.IADD R13, R7, 0x1, -R8 ; /* 0x00000001070d7824 */
/* 0x000fe200078e0a08 */
/*0200*/ ISETP.GE.AND P1, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */
/* 0x040fe20003f26270 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.LT.AND P0, PT, R6, R9, !P0 ; /* 0x000000090600720c */
/* 0x000fd40004701270 */
/*0230*/ BSSY B0, 0x2b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0240*/ @P1 BRA 0x2a0 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*0250*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x000fe80000004800 */
/*0260*/ LDS R10, [R6.X4+-0x4] ; /* 0xfffffc00060a7984 */
/* 0x000e240000004800 */
/*0270*/ ISETP.GE.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x001fda0003f46270 */
/*0280*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*0290*/ @!P2 STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b0600a388 */
/* 0x0001e40000004800 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ BSSY B0, 0x340 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*02d0*/ @!P0 BRA 0x330 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02e0*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*02f0*/ LDS R10, [R6.X4+0x4] ; /* 0x00000400060a7984 */
/* 0x000e240000004800 */
/*0300*/ ISETP.GE.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x001fda0003f46270 */
/*0310*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*0320*/ @!P2 STS [R6.X4+0x4], R11 ; /* 0x0000040b0600a388 */
/* 0x0001e40000004800 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ BSSY B0, 0x3d0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0360*/ @P1 BRA 0x3c0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0370*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*0380*/ LDS R10, [R6.X4+-0x4] ; /* 0xfffffc00060a7984 */
/* 0x000e240000004800 */
/*0390*/ ISETP.GE.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x001fda0003f46270 */
/*03a0*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*03b0*/ @!P2 STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b0600a388 */
/* 0x0001e40000004800 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*03f0*/ ISETP.NE.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f65270 */
/*0400*/ BSSY B0, 0x480 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0410*/ @!P0 BRA 0x470 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0420*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*0430*/ LDS R10, [R6.X4+0x4] ; /* 0x00000400060a7984 */
/* 0x000e240000004800 */
/*0440*/ ISETP.GE.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x001fda0003f46270 */
/*0450*/ @!P2 STS [R6.X4], R10 ; /* 0x0000000a0600a388 */
/* 0x0001e80000004800 */
/*0460*/ @!P2 STS [R6.X4+0x4], R11 ; /* 0x0000040b0600a388 */
/* 0x0001e40000004800 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0490*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fca0007ffe0ff */
/*04a0*/ @P3 BRA 0x230 ; /* 0xfffffd8000003947 */
/* 0x000fea000383ffff */
/*04b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*04c0*/ @!P0 BRA 0x670 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*04d0*/ LOP3.LUT P0, R10, R12, 0x1, RZ, 0xc0, !PT ; /* 0x000000010c0a7812 */
/* 0x001fe2000780c0ff */
/*04e0*/ BSSY B0, 0x5a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*04f0*/ ISETP.GE.OR P0, PT, R0, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x000fe4000c706670 */
/*0500*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*0510*/ ISETP.GE.OR P0, PT, R6.reuse, R9, P0 ; /* 0x000000090600720c */
/* 0x040fe40000706670 */
/*0520*/ ISETP.GE.OR P1, PT, R6, R7, P1 ; /* 0x000000070600720c */
/* 0x000fd60000f26670 */
/*0530*/ @P0 BRA 0x590 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0540*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x000fe80000004800 */
/*0550*/ LDS R10, [R6.X4+0x4] ; /* 0x00000400060a7984 */
/* 0x000e240000004800 */
/*0560*/ ISETP.GE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x001fda0003f06270 */
/*0570*/ @!P0 STS [R6.X4], R10 ; /* 0x0000000a06008388 */
/* 0x0001e80000004800 */
/*0580*/ @!P0 STS [R6.X4+0x4], R11 ; /* 0x0000040b06008388 */
/* 0x0001e40000004800 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ BSSY B0, 0x620 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*05b0*/ @P1 BRA 0x610 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*05c0*/ LDS R11, [R6.X4] ; /* 0x00000000060b7984 */
/* 0x001fe80000004800 */
/*05d0*/ LDS R10, [R6.X4+-0x4] ; /* 0xfffffc00060a7984 */
/* 0x000e240000004800 */
/*05e0*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x001fda0003f06270 */
/*05f0*/ @!P0 STS [R6.X4], R10 ; /* 0x0000000a06008388 */
/* 0x0001e80000004800 */
/*0600*/ @!P0 STS [R6.X4+-0x4], R11 ; /* 0xfffffc0b06008388 */
/* 0x0001e40000004800 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0640*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0660*/ @P0 BRA 0x4d0 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0670*/ LDS R7, [R6.X4] ; /* 0x0000000006077984 */
/* 0x001e280000004800 */
/*0680*/ LDS R9, [R6.X4+-0x4] ; /* 0xfffffc0006097984 */
/* 0x000e680000004800 */
/*0690*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101906 */
/*06a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20odd_even_sort_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0040*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fca00078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fd800078e0207 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R10, R8, -0x1, RZ ; /* 0xffffffff080a7810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*00a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fe20003f06070 */
/*00d0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe20007ffe0ff */
/*00f0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe2000fffe13f */
/*0100*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0205 */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ LEA R7, R7, 0x1, 0x1 ; /* 0x0000000107077811 */
/* 0x000fc400078e08ff */
/*0130*/ LOP3.LUT R9, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208097812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe400078e0205 */
/*0160*/ @!P0 BRA 0x450 ; /* 0x000002e000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f06270 */
/*0180*/ IMAD.IADD R13, R8, 0x1, -R9 ; /* 0x00000001080d7824 */
/* 0x000fe200078e0a09 */
/*0190*/ ISETP.GE.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf26270 */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.LT.U32.AND P0, PT, R7.reuse, R8, !P0 ; /* 0x000000080700720c */
/* 0x040fe40004701070 */
/*01c0*/ ISETP.LT.U32.AND P1, PT, R7, R10, !P1 ; /* 0x0000000a0700720c */
/* 0x000fd40004f21070 */
/*01d0*/ BSSY B0, 0x250 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @!P0 BRA 0x240 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*0210*/ ISETP.GE.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x004fda0003f46270 */
/*0220*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*0230*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e4000c101906 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ BSSY B0, 0x2e0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0270*/ @!P1 BRA 0x2d0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*0290*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ ISETP.GE.AND P2, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f46270 */
/*02b0*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*02c0*/ @!P2 STG.E [R4.64+0x4], R11 ; /* 0x0000040b0400a986 */
/* 0x0001e4000c101906 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ BSSY B0, 0x370 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0300*/ @!P0 BRA 0x360 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*0320*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*0330*/ ISETP.GE.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x004fda0003f46270 */
/*0340*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*0350*/ @!P2 STG.E [R2.64], R11 ; /* 0x0000000b0200a986 */
/* 0x0001e4000c101906 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe20007ffe0ff */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0390*/ ISETP.NE.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f65270 */
/*03a0*/ BSSY B0, 0x420 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*03b0*/ @!P1 BRA 0x410 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*03d0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ ISETP.GE.AND P2, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f46270 */
/*03f0*/ @!P2 STG.E [R4.64], R0 ; /* 0x000000000400a986 */
/* 0x0001e8000c101906 */
/*0400*/ @!P2 STG.E [R4.64+0x4], R11 ; /* 0x0000040b0400a986 */
/* 0x0001e4000c101906 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fca0007ffe0ff */
/*0440*/ @P3 BRA 0x1d0 ; /* 0xfffffd8000003947 */
/* 0x000fea000383ffff */
/*0450*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0460*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0470*/ LOP3.LUT P0, R0, R12, 0x1, RZ, 0xc0, !PT ; /* 0x000000010c007812 */
/* 0x001fe2000780c0ff */
/*0480*/ BSSY B0, 0x550 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*0490*/ ISETP.GE.OR P0, PT, R6, UR4, !P0 ; /* 0x0000000406007c0c */
/* 0x000fe4000c706670 */
/*04a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*04b0*/ ISETP.GE.U32.OR P0, PT, R7, R10, P0 ; /* 0x0000000a0700720c */
/* 0x000fe40000706470 */
/*04c0*/ ISETP.GE.OR P1, PT, R6, c[0x0][0x168], P1 ; /* 0x00005a0006007a0c */
/* 0x000fc80000f26670 */
/*04d0*/ ISETP.GE.U32.OR P1, PT, R7, R8, P1 ; /* 0x000000080700720c */
/* 0x000fce0000f26470 */
/*04e0*/ @P0 BRA 0x540 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*04f0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea4000c1e1900 */
/*0510*/ ISETP.GE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f06270 */
/*0520*/ @!P0 STG.E [R4.64], R0 ; /* 0x0000000004008986 */
/* 0x0001e8000c101906 */
/*0530*/ @!P0 STG.E [R4.64+0x4], R11 ; /* 0x0000040b04008986 */
/* 0x0001e4000c101906 */
/*0540*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0550*/ BSSY B0, 0x5d0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0560*/ @P1 BRA 0x5c0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x001ea8000c1e1900 */
/*0580*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*0590*/ ISETP.GE.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x004fda0003f06270 */
/*05a0*/ @!P0 STG.E [R4.64], R0 ; /* 0x0000000004008986 */
/* 0x0001e8000c101906 */
/*05b0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e4000c101906 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0610*/ @P0 BRA 0x470 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20odd_even_sort_kernelPii
.globl _Z20odd_even_sort_kernelPii
.p2align 8
.type _Z20odd_even_sort_kernelPii,@function
_Z20odd_even_sort_kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_9
s_and_b32 s5, 0xffff, s2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_lshl_or_b32 v4, v0, 1, 1
s_lshl_b32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s0, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v1, v1, 1, 1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s6, -1
v_cmp_gt_i32_e64 s0, s6, v1
v_cmp_gt_i32_e64 s1, s1, v1
v_add_co_u32 v0, s2, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, s3, v3, s2
v_cmp_gt_u32_e64 s2, s5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s4, s4, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s5, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_and_b32 s3, s4, 1
s_and_b32 s7, 1, s4
s_cmp_eq_u32 s3, 0
s_cselect_b32 s6, -1, 0
s_cmp_eq_u32 s7, 1
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s3
s_cbranch_execz .LBB0_6
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s3, v3, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v4, v2
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_and_b32 s3, s6, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_and_saveexec_b32 s6, s3
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v2, v[0:1], off
global_load_b32 v3, v[0:1], off offset:-4
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s3, v2, v3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_2
s_clause 0x1
global_store_b32 v[0:1], v3, off
global_store_b32 v[0:1], v2, off offset:-4
s_branch .LBB0_2
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20odd_even_sort_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20odd_even_sort_kernelPii, .Lfunc_end0-_Z20odd_even_sort_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25fast_odd_even_sort_kernelPii
.globl _Z25fast_odd_even_sort_kernelPii
.p2align 8
.type _Z25fast_odd_even_sort_kernelPii,@function
_Z25fast_odd_even_sort_kernelPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_lshl_or_b32 v3, v1, 1, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_lshl_or_b32 v4, v0, 1, 1
v_lshlrev_b32_e32 v0, 2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v5, -4, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_eq_u16_e64 s0, s3, 0
s_mov_b32 s3, 0
global_load_b64 v[6:7], v[1:2], off offset:-4
s_and_b32 vcc_lo, exec_lo, s0
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[6:7]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_10
s_lshl_b32 s4, s4, 1
s_add_i32 s2, s2, -1
s_add_i32 s0, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v3
v_cmp_gt_i32_e64 s0, s0, v4
v_cmp_gt_u32_e64 s1, s4, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_10
.LBB1_4:
s_and_b32 s2, s3, 1
s_and_b32 s6, 1, s3
s_cmp_eq_u32 s2, 0
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s6, 1
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB1_7
ds_load_2addr_b32 v[3:4], v0 offset1:1
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s2, v4, v3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_7
ds_store_2addr_b32 v0, v4, v3 offset1:1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s6
s_and_b32 s2, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_3
ds_load_b32 v3, v0
ds_load_b32 v4, v5
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_3
ds_store_b32 v0, v4
ds_store_b32 v5, v3
s_branch .LBB1_3
.LBB1_10:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v0
ds_load_b32 v3, v5
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v0, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v3, off offset:-4
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fast_odd_even_sort_kernelPii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25fast_odd_even_sort_kernelPii, .Lfunc_end1-_Z25fast_odd_even_sort_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20odd_even_sort_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20odd_even_sort_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fast_odd_even_sort_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fast_odd_even_sort_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b59cc_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_CRTL_:"
.LC1:
.string "%s I = %d\n"
.text
.globl _Z7controlPii
.type _Z7controlPii, @function
_Z7controlPii:
.LFB2060:
.cfi_startproc
endbr64
cmpl $1, %esi
jle .L7
movl %esi, %esi
movl $1, %ecx
.L6:
movl (%rdi,%rcx,4), %eax
cmpl %eax, -4(%rdi,%rcx,4)
jg .L13
addq $1, %rcx
cmpq %rsi, %rcx
jne .L6
movl $0, %eax
ret
.L13:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L7:
movl $0, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z7controlPii, .-_Z7controlPii
.globl _Z41__device_stub__Z20odd_even_sort_kernelPiiPii
.type _Z41__device_stub__Z20odd_even_sort_kernelPiiPii, @function
_Z41__device_stub__Z20odd_even_sort_kernelPiiPii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20odd_even_sort_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z41__device_stub__Z20odd_even_sort_kernelPiiPii, .-_Z41__device_stub__Z20odd_even_sort_kernelPiiPii
.globl _Z20odd_even_sort_kernelPii
.type _Z20odd_even_sort_kernelPii, @function
_Z20odd_even_sort_kernelPii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z20odd_even_sort_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z20odd_even_sort_kernelPii, .-_Z20odd_even_sort_kernelPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/iotincho/TP_cuda/master/main.cu"
.section .rodata.str1.1
.LC3:
.string "%s in %s at line %d\n"
.LC4:
.string "_ODD_:"
.LC5:
.string "%s ordenando..\n"
.LC7:
.string "%s terminanding.. time: %f s\n"
.text
.globl _Z13odd_even_sortPii
.type _Z13odd_even_sortPii, @function
_Z13odd_even_sortPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $782, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $400000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 127(%r13), %ebp
testl %r13d, %r13d
cmovns %r13d, %ebp
sarl $7, %ebp
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $-127, %r13d
jl .L24
addl $1, %ebp
movl $0, %ebx
jmp .L26
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $99, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
addl $1, %ebx
cmpl %ebx, %ebp
je .L24
.L26:
movq 8(%rsp), %r12
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl %ebx, %eax
andl $1, %eax
sall $7, %eax
movl %r13d, %esi
subl %eax, %esi
cltq
leaq (%r12,%rax,4), %rdi
call _Z41__device_stub__Z20odd_even_sort_kernelPiiPii
jmp .L25
.L24:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $400000, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movss 4(%rsp), %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13odd_even_sortPii, .-_Z13odd_even_sortPii
.globl _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
.type _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii, @function
_Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25fast_odd_even_sort_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii, .-_Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
.globl _Z25fast_odd_even_sort_kernelPii
.type _Z25fast_odd_even_sort_kernelPii, @function
_Z25fast_odd_even_sort_kernelPii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z25fast_odd_even_sort_kernelPii, .-_Z25fast_odd_even_sort_kernelPii
.globl _Z18fast_odd_even_sortPii
.type _Z18fast_odd_even_sortPii, @function
_Z18fast_odd_even_sortPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $782, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L48
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $400000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 127(%r13), %ebp
testl %r13d, %r13d
cmovns %r13d, %ebp
sarl $7, %ebp
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $-127, %r13d
jl .L42
addl $1, %ebp
movl $0, %ebx
jmp .L44
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $142, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
addl $1, %ebx
cmpl %ebx, %ebp
je .L42
.L44:
movq 8(%rsp), %r12
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl %ebx, %eax
andl $1, %eax
sall $7, %eax
movl %r13d, %esi
subl %eax, %esi
cltq
leaq (%r12,%rax,4), %rdi
call _Z46__device_stub__Z25fast_odd_even_sort_kernelPiiPii
jmp .L43
.L42:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $400000, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movss 4(%rsp), %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z18fast_odd_even_sortPii, .-_Z18fast_odd_even_sortPii
.section .rodata.str1.1
.LC8:
.string "array size: %d tile: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "#### SORT WHIT GLOBAL MEMORY ####\n"
.section .rodata.str1.1
.LC10:
.string "\n"
.LC11:
.string "_MAIN_:"
.LC12:
.string "%s desordenado!! \n"
.LC13:
.string "%s ok!! \n"
.section .rodata.str1.8
.align 8
.LC14:
.string "#### SORT WHIT SHARED MEMORY ####\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $400000, %edi
call malloc@PLT
movq %rax, %r13
movl $128, %ecx
movl $100000, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbp
leaq 400000(%r13), %r12
movq %r13, %rbx
.L51:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L51
movl $1001, 0(%r13)
movl $0, 399996(%r13)
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L65
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L53
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L54:
movl $100000, %esi
movq %r13, %rdi
call _Z13odd_even_sortPii
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L55
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L56:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L57:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L57
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L58
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L59:
movl $100000, %esi
movq %r13, %rdi
call _Z18fast_odd_even_sortPii
movl $100000, %esi
movq %r13, %rdi
call _Z7controlPii
testl %eax, %eax
je .L60
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L61:
movq %r13, %rdi
call free@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $209, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L55:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L58:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.L60:
leaq .LC11(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L61
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z25fast_odd_even_sort_kernelPii"
.section .rodata.str1.1
.LC16:
.string "_Z20odd_even_sort_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z25fast_odd_even_sort_kernelPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z20odd_even_sort_kernelPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z35__device_stub__odd_even_sort_kernelPii # -- Begin function _Z35__device_stub__odd_even_sort_kernelPii
.p2align 4, 0x90
.type _Z35__device_stub__odd_even_sort_kernelPii,@function
_Z35__device_stub__odd_even_sort_kernelPii: # @_Z35__device_stub__odd_even_sort_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20odd_even_sort_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__odd_even_sort_kernelPii, .Lfunc_end0-_Z35__device_stub__odd_even_sort_kernelPii
.cfi_endproc
# -- End function
.globl _Z40__device_stub__fast_odd_even_sort_kernelPii # -- Begin function _Z40__device_stub__fast_odd_even_sort_kernelPii
.p2align 4, 0x90
.type _Z40__device_stub__fast_odd_even_sort_kernelPii,@function
_Z40__device_stub__fast_odd_even_sort_kernelPii: # @_Z40__device_stub__fast_odd_even_sort_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25fast_odd_even_sort_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z40__device_stub__fast_odd_even_sort_kernelPii, .Lfunc_end1-_Z40__device_stub__fast_odd_even_sort_kernelPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13odd_even_sortPii
.LCPI2_0:
.long 0x447a0000 # float 1000
.text
.globl _Z13odd_even_sortPii
.p2align 4, 0x90
.type _Z13odd_even_sortPii,@function
_Z13odd_even_sortPii: # @_Z13odd_even_sortPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movq %rdi, %rbx
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB2_7
# %bb.1:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq (%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movl $.L.str.2, %edi
movl $.L.str.3, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $-127, %r14d
jge .LBB2_2
.LBB2_6: # %._crit_edge
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq (%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movl $.L.str.3, %esi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_2: # %.lr.ph
.cfi_def_cfa_offset 176
movabsq $4294967424, %r15 # imm = 0x100000080
leal 127(%r14), %r13d
testl %r14d, %r14d
cmovnsl %r14d, %r13d
sarl $7, %r13d
incl %r13d
leaq 654(%r15), %r12
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
subl $-128, %ebx
decl %r13d
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rbp
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl %ebx, %eax
andl $128, %eax
movl %r14d, %ecx
subl %eax, %ecx
leaq (,%rax,4), %rax
addq %rbp, %rax
movq %rax, 112(%rsp)
movl %ecx, 20(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 20(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z20odd_even_sort_kernelPii, %edi
leaq 32(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.LBB2_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $99, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z13odd_even_sortPii, .Lfunc_end2-_Z13odd_even_sortPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z18fast_odd_even_sortPii
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl _Z18fast_odd_even_sortPii
.p2align 4, 0x90
.type _Z18fast_odd_even_sortPii,@function
_Z18fast_odd_even_sortPii: # @_Z18fast_odd_even_sortPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movq %rdi, %rbx
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
testl %eax, %eax
jne .LBB3_7
# %bb.1:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq (%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movl $.L.str.2, %edi
movl $.L.str.3, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $-127, %r14d
jge .LBB3_2
.LBB3_6: # %._crit_edge
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq (%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movl $.L.str.3, %esi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_2: # %.lr.ph
.cfi_def_cfa_offset 176
movabsq $4294967424, %r15 # imm = 0x100000080
leal 127(%r14), %r13d
testl %r14d, %r14d
cmovnsl %r14d, %r13d
sarl $7, %r13d
incl %r13d
leaq 654(%r15), %r12
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
subl $-128, %ebx
decl %r13d
je .LBB3_6
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rbp
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl %ebx, %eax
andl $128, %eax
movl %r14d, %ecx
subl %eax, %ecx
leaq (,%rax,4), %rax
addq %rbp, %rax
movq %rax, 112(%rsp)
movl %ecx, 20(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 20(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z25fast_odd_even_sort_kernelPii, %edi
leaq 32(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_5
.LBB3_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $142, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z18fast_odd_even_sortPii, .Lfunc_end3-_Z18fast_odd_even_sortPii
.cfi_endproc
# -- End function
.globl _Z7controlPii # -- Begin function _Z7controlPii
.p2align 4, 0x90
.type _Z7controlPii,@function
_Z7controlPii: # @_Z7controlPii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpl $2, %esi
setge %bl
jl .LBB4_8
# %bb.1: # %.lr.ph.preheader
movl (%rdi), %eax
movl $1, %edx
cmpl 4(%rdi), %eax
jg .LBB4_6
# %bb.2: # %.lr.ph22.preheader
movl %esi, %eax
movl $2, %ecx
subq %rax, %rcx
movl $1, %esi
.p2align 4, 0x90
.LBB4_3: # %.lr.ph22
# =>This Inner Loop Header: Depth=1
leaq (%rcx,%rsi), %rdx
cmpq $1, %rdx
je .LBB4_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB4_3 Depth=1
movl (%rdi,%rsi,4), %r8d
leaq 1(%rsi), %rdx
cmpl 4(%rdi,%rsi,4), %r8d
movq %rdx, %rsi
jle .LBB4_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %rax, %rdx
setb %bl
.LBB4_6:
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB4_8
.LBB4_7: # %.loopexit.loopexit
incq %rsi
cmpq %rax, %rsi
setb %bl
.LBB4_8: # %.loopexit
movzbl %bl, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z7controlPii, .Lfunc_end4-_Z7controlPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
movl $.L.str.7, %edi
movl $100000, %esi # imm = 0x186A0
movl $128, %edx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB5_1
# %bb.2:
movl $1001, (%rbx) # imm = 0x3E9
movl $0, 399996(%rbx)
movl $10, %edi
callq putchar@PLT
movl $1, %r14d
movl $1, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_7
# %bb.3: # %.lr.ph.i.preheader
movl (%rbx), %eax
movb $1, %bpl
cmpl 4(%rbx), %eax
jg .LBB5_10
# %bb.4: # %.lr.ph.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_6
# %bb.8: # %.lr.ph.i
# in Loop: Header=BB5_5 Depth=1
movl (%rbx,%rcx,4), %edx
decq %rax
leaq 1(%rcx), %r14
cmpl 4(%rbx,%rcx,4), %edx
movq %r14, %rcx
jle .LBB5_5
# %bb.9: # %.lr.ph.i._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_10: # %.lr.ph.i._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
jmp .LBB5_11
.LBB5_6: # %_Z7controlPii.exit.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_11: # %_Z7controlPii.exit
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl $100000, %esi # imm = 0x186A0
callq _Z13odd_even_sortPii
movl (%rbx), %eax
cmpl 4(%rbx), %eax
jle .LBB5_16
# %bb.12:
movb $1, %bpl
movl $1, %edx
jmp .LBB5_15
.LBB5_16: # %.lr.ph66.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_17: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_18
# %bb.13: # %.lr.ph.i27
# in Loop: Header=BB5_17 Depth=1
movl (%rbx,%rcx,4), %esi
decq %rax
leaq 1(%rcx), %rdx
cmpl 4(%rbx,%rcx,4), %esi
movq %rdx, %rcx
jle .LBB5_17
# %bb.14: # %.lr.ph.i27._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_15: # %.lr.ph.i27._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB5_19
.LBB5_18: # %_Z7controlPii.exit35.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_19: # %_Z7controlPii.exit35
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
xorl %r14d, %r14d
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB5_20: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB5_20
# %bb.21:
movl $10, %edi
callq putchar@PLT
movl (%rbx), %eax
cmpl 4(%rbx), %eax
jle .LBB5_26
# %bb.22:
movb $1, %bpl
movl $1, %edx
jmp .LBB5_25
.LBB5_26: # %.lr.ph71.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_27: # %.lr.ph71
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_28
# %bb.23: # %.lr.ph.i36
# in Loop: Header=BB5_27 Depth=1
movl (%rbx,%rcx,4), %esi
decq %rax
leaq 1(%rcx), %rdx
cmpl 4(%rbx,%rcx,4), %esi
movq %rdx, %rcx
jle .LBB5_27
# %bb.24: # %.lr.ph.i36._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_25: # %.lr.ph.i36._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB5_29
.LBB5_28: # %_Z7controlPii.exit44.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_29: # %_Z7controlPii.exit44
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl $100000, %esi # imm = 0x186A0
callq _Z18fast_odd_even_sortPii
movl (%rbx), %eax
cmpl 4(%rbx), %eax
jle .LBB5_34
# %bb.30:
movb $1, %bpl
movl $1, %edx
jmp .LBB5_33
.LBB5_34: # %.lr.ph75.preheader
movl $1, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_35: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
cmpq $-99998, %rax # imm = 0xFFFE7962
je .LBB5_36
# %bb.31: # %.lr.ph.i45
# in Loop: Header=BB5_35 Depth=1
movl (%rbx,%rcx,4), %esi
decq %rax
leaq 1(%rcx), %rdx
cmpl 4(%rbx,%rcx,4), %esi
movq %rdx, %rcx
jle .LBB5_35
# %bb.32: # %.lr.ph.i45._crit_edge.loopexit
negq %rax
cmpq $99999, %rax # imm = 0x1869F
setb %bpl
.LBB5_33: # %.lr.ph.i45._crit_edge
movl $.L.str.5, %edi
movl $.L.str.6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB5_37
.LBB5_36: # %_Z7controlPii.exit53.loopexit
cmpq $99999, %rcx # imm = 0x1869F
setb %bpl
.LBB5_37: # %_Z7controlPii.exit53
movl $.L.str.10, %eax
movl $.L.str.12, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_7:
.cfi_def_cfa_offset 32
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $209, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20odd_even_sort_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fast_odd_even_sort_kernelPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20odd_even_sort_kernelPii,@object # @_Z20odd_even_sort_kernelPii
.section .rodata,"a",@progbits
.globl _Z20odd_even_sort_kernelPii
.p2align 3, 0x0
_Z20odd_even_sort_kernelPii:
.quad _Z35__device_stub__odd_even_sort_kernelPii
.size _Z20odd_even_sort_kernelPii, 8
.type _Z25fast_odd_even_sort_kernelPii,@object # @_Z25fast_odd_even_sort_kernelPii
.globl _Z25fast_odd_even_sort_kernelPii
.p2align 3, 0x0
_Z25fast_odd_even_sort_kernelPii:
.quad _Z40__device_stub__fast_odd_even_sort_kernelPii
.size _Z25fast_odd_even_sort_kernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/iotincho/TP_cuda/master/main.hip"
.size .L.str.1, 90
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s ordenando..\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "_ODD_:"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s terminanding.. time: %f s\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s I = %d\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "_CRTL_:"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "array size: %d tile: %d\n"
.size .L.str.7, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%s desordenado!! \n"
.size .L.str.10, 19
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "_MAIN_:"
.size .L.str.11, 8
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%s ok!! \n"
.size .L.str.12, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20odd_even_sort_kernelPii"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25fast_odd_even_sort_kernelPii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "#### SORT WHIT GLOBAL MEMORY ####"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "#### SORT WHIT SHARED MEMORY ####"
.size .Lstr.1, 38
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__odd_even_sort_kernelPii
.addrsig_sym _Z40__device_stub__fast_odd_even_sort_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20odd_even_sort_kernelPii
.addrsig_sym _Z25fast_odd_even_sort_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
#include <errno.h>
#include <vector>
#include <time.h>
#include <sys/time.h>
using std::cout;
using std::cerr;
using std::endl;
using std::cin;
using std::vector;
constexpr size_t IM_X = 1300;
constexpr size_t IM_Y = 600;
constexpr size_t IM_V = sizeof(float2);
constexpr size_t IM_SIZE = IM_X * IM_Y * IM_V;
constexpr size_t XSR = 10;
constexpr size_t YSR = 5;
__device__
inline float2 mul(float s, float2 v) {
v.x *= s;
v.y *= s;
return v;
}
__device__
inline float2 add(float2 v1, float2 v2) {
v1.x += v2.x;
v1.y += v2.y;
return v1;
}
__global__
void integrate(float2* out, cudaTextureObject_t vecs, float dt, size_t steps) {
float2 k1, k2, k3, k4, p, q;
// Initial position
p.x = blockIdx.x * blockDim.x + threadIdx.x;
p.y = blockIdx.y * blockDim.y + threadIdx.y;
// Output location
size_t idx = (blockDim.x * gridDim.x * (int)p.y + (int)p.x) * steps;
// Apply sample rate
p.x *= XSR;
p.y *= YSR;
// Initial output
out[idx++] = p;
// Integrate forward
for (size_t i = 1; i < steps; i++) {
k1 = mul(dt, tex2D<float2>(vecs, p.x, p.y));
q = add(p, mul(0.5, k1));
k2 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, mul(0.5, k2));
k3 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, k3);
k4 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
p.x += (1.0/6.0)*(k1.x + 2*k2.x + 2*k3.x + k4.x);
p.y += (1.0/6.0)*(k1.y + 2*k2.y + 2*k3.y + k4.y);
out[idx++] = p;
}
}
__host__
cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
cerr << "CUDA Runtime Error: " << cudaGetErrorString(result) << endl;
abort();
}
return result;
}
__host__
int checkLinux(int result) {
if (result == -1) {
cerr << "Linux Runtime Error: (" << errno << ") " << strerror(errno) << endl;
abort();
}
return result;
}
__host__
void writeCSV(char* file, float2* output, size_t num_particles, size_t steps) {
const size_t file_size = num_particles * steps * (20 + 9 + 9 + 3);
umask(0111);
int fd = checkLinux(open(file, O_RDWR | O_CREAT | O_TRUNC, 06666));
checkLinux(ftruncate(fd, file_size));
char* map = (char*) mmap(NULL, file_size, PROT_WRITE, MAP_SHARED, fd, 0);
checkLinux((int)(size_t)map);
char* cur = map;
const char* header = "line_id, coordinate_x, coordinate_y\n";
checkLinux(write(fd, header, strlen(header)));
for (size_t i = 0; i < num_particles; i++)
for (size_t s = 0; s < steps; s++) {
float2 p = output[i * steps + s];
cur += sprintf(cur, "%llu,%.7f,%.7f\n", i, p.x, p.y);
}
msync(map, file_size, MS_SYNC);
munmap(map, file_size);
checkLinux(ftruncate(fd, cur - map));
checkLinux(close(fd));
}
vector<const char*> names;
vector<timespec> wall;
vector<timespec> proc;
vector<size_t> levels;
size_t cur_level = 0;
__host__
static inline void stime(const char* name) {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
names.push_back(name);
levels.push_back(cur_level++);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
__host__
static inline void ftime() {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
levels.push_back(--cur_level);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
// from https://gist.github.com/diabloneo/9619917
__host__
static inline void timespecDiff(timespec& a, timespec& b, timespec& result) {
result.tv_sec = a.tv_sec - b.tv_sec;
result.tv_nsec = a.tv_nsec - b.tv_nsec;
if (result.tv_nsec < 0) {
--result.tv_sec;
result.tv_nsec += 1000000000L;
}
}
__host__
static inline double timespecToMs(const timespec& t) {
return (double)t.tv_sec * 1000.0 + (double)t.tv_nsec / 1000000.0;
}
__host__
static size_t ptime(const char* name, size_t n = 0, size_t i = 0, size_t l = 0) {
while (n < names.size() and levels[i] == l) {
size_t j = i + 1;
auto& sw = wall[i];
auto& sp = proc[i];
int jumped = j;
while (l < levels[j]) j++;
auto& fw = wall[j];
auto& fp = proc[j];
timespec w, p;
timespecDiff(fw, sw, w);
timespecDiff(fp, sp, p);
for (size_t k = 0; k < l; k++)
printf("\t");
printf("\"%s\", \"%s\", %.3f, %.3f\n",
name,
names[n++],
timespecToMs(w),
timespecToMs(p));
if (jumped < j)
n = ptime(name, n, jumped, l + 1);
i = j + 1;
}
return n;
}
__host__
int main(int argc, char **argv) {
stime("Program");
stime("Setup");
if (argc != 3) {
ftime();
ftime();
printf("Usage: ./main image output\n");
return 0;
}
float dt = 1;
//cout << "Enter delta time: ";
//cin >> dt;
size_t steps = 100;
//cout << "Enter number of steps: ";
//cin >> steps;
// Opening file
stime("Read input");
int fd = checkLinux(open(argv[1], O_RDONLY));
// Allocating + Mapping host memory
float2 *im;
cudaArray* im_d;
float2 *output_d;
float2 *output;
// Memory mapping does not provide a performance boost.
// It trades off between copy time to GPU or copy to RAM.
checkCuda(cudaMallocHost(&im, IM_SIZE));
checkLinux(read(fd, im, IM_SIZE));
close(fd);
ftime();
// Modified basic cuda texture manipulation obtained from
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
// Allocate CUDA array in device memory
stime("Copy to GPU");
cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc(32, 32, 0, 0,
cudaChannelFormatKindFloat);
checkCuda(cudaMallocArray(&im_d, &channelDesc, IM_X, IM_Y));
checkCuda(cudaMemcpyToArray(im_d, 0, 0, im, IM_SIZE, cudaMemcpyHostToDevice));
ftime();
// Specify texture
stime("Initialize Texture");
struct cudaResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = cudaResourceTypeArray;
resDesc.res.array.array = im_d;
// Specify texture object parameters
struct cudaTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.addressMode[0] = cudaAddressModeBorder;
texDesc.addressMode[1] = cudaAddressModeBorder;
texDesc.filterMode = cudaFilterModeLinear;
texDesc.readMode = cudaReadModeElementType;
texDesc.maxAnisotropy = 2;
texDesc.normalizedCoords = false;
// Create texture object
cudaTextureObject_t imTex = 0;
checkCuda(cudaCreateTextureObject(&imTex, &resDesc, &texDesc, NULL));
ftime();
dim3 block(26, 24, 1);
dim3 grid(5, 5, 1);
// dim3 block(1, 24, 1);
// dim3 grid(1, 25, 1);
const size_t num_particles = block.x * grid.x * block.y * grid.y;
const size_t out_size = num_particles * sizeof(float2) * steps;
stime("Allocate Output");
checkCuda(cudaMalloc(&output_d, out_size));
ftime();
ftime();
stime("Computation");
integrate<<<grid, block>>>(output_d, imTex, dt, steps);
ftime();
// Copying from device to host
stime("Copy to host");
checkCuda(cudaMallocHost(&output, out_size));
checkCuda(cudaMemcpy(output, output_d, out_size, cudaMemcpyDeviceToHost));
ftime();
stime("Free device memory");
checkCuda(cudaFree(output_d));
checkCuda(cudaDestroyTextureObject(imTex));
checkCuda(cudaFreeArray(im_d));
ftime();
//stime("Write");
//writeCSV(argv[2], output, num_particles, steps);
//ftime();
stime("Free host memory");
checkCuda(cudaFreeHost(im));
checkCuda(cudaFreeHost(output));
ftime();
ftime();
ptime("GPU");
return 0;
} | code for sm_80
Function : _Z9integrateP6float2yfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0070*/ MOV R12, c[0x0][0x17c] ; /* 0x00005f00000c7a02 */
/* 0x000fe40000000f00 */
/*0080*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002600 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f06070 */
/*00a0*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*00b0*/ ISETP.GE.U32.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe20003f06100 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fcc00078e0203 */
/*00d0*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000e220000201000 */
/*00e0*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x002fce00078e0205 */
/*00f0*/ I2F.U32 R6, R4 ; /* 0x0000000400067306 */
/* 0x000e700000201000 */
/*0100*/ F2I.TRUNC.NTZ R3, R0 ; /* 0x0000000000037305 */
/* 0x001fe2000020f100 */
/*0110*/ FMUL R10, R0, 10 ; /* 0x41200000000a7820 */
/* 0x000fce0000400000 */
/*0120*/ F2I.TRUNC.NTZ R2, R6 ; /* 0x0000000600027305 */
/* 0x002e22000020f100 */
/*0130*/ FMUL R11, R6, 5 ; /* 0x40a00000060b7820 */
/* 0x000fe40000400000 */
/*0140*/ IMAD R5, R2, UR4, R3 ; /* 0x0000000402057c24 */
/* 0x001fe2000f8e0203 */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0160*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x178], RZ ; /* 0x00005e0005027a25 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD R7, R5, c[0x0][0x17c], R3 ; /* 0x00005f0005077a24 */
/* 0x000fe200078e0203 */
/*0180*/ LEA R4, P1, R2, c[0x0][0x160], 0x3 ; /* 0x0000580002047a11 */
/* 0x000fc800078218ff */
/*0190*/ LEA.HI.X R5, R2, c[0x0][0x164], R7, 0x3, P1 ; /* 0x0000590002057a11 */
/* 0x000fca00008f1c07 */
/*01a0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e2000c101b04 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R0, P1, R8.reuse, -0x2, RZ ; /* 0xfffffffe08007810 */
/* 0x040fe40007f3e0ff */
/*01d0*/ IADD3 R5, P2, R8, -0x1, RZ ; /* 0xffffffff08057810 */
/* 0x001fe40007f5e0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*01f0*/ IADD3.X R0, R12, -0x1, RZ, P1, !PT ; /* 0xffffffff0c007810 */
/* 0x000fe40000ffe4ff */
/*0200*/ MOV R9, R2 ; /* 0x0000000200097202 */
/* 0x000fe40000000f00 */
/*0210*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc40003f06100 */
/*0220*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe40000000f00 */
/*0230*/ LOP3.LUT P1, RZ, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305ff7812 */
/* 0x040fe4000782c0ff */
/*0240*/ MOV R0, R7 ; /* 0x0000000700007202 */
/* 0x000fe40000000f00 */
/*0250*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0260*/ IADD3.X R10, R12, -0x1, RZ, P2, !PT ; /* 0xffffffff0c0a7810 */
/* 0x000fe400017fe4ff */
/*0270*/ LOP3.LUT R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe200078ec0ff */
/*0280*/ @!P0 BRA 0xb10 ; /* 0x0000088000008947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R11, P0, -R8, R5, RZ ; /* 0x00000005080b7210 */
/* 0x000fc80007f1e1ff */
/*02a0*/ IADD3.X R10, R10, -0x1, RZ, P0, !PT ; /* 0xffffffff0a0a7810 */
/* 0x000fe400007fe4ff */
/*02b0*/ HFMA2.MMA R14, -RZ, RZ, -3, 0 ; /* 0xc2000000ff0e7435 */
/* 0x000fcc00000001ff */
/*02c0*/ TEX.SCR.LL RZ, R4, R2, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e02047b60 */
/* 0x000f4400019e03ff */
/*02d0*/ FMUL R15, R4, c[0x0][0x170] ; /* 0x00005c00040f7a20 */
/* 0x020fe40000400000 */
/*02e0*/ FMUL R6, R5, c[0x0][0x170] ; /* 0x00005c0005067a20 */
/* 0x004fe40000400000 */
/*02f0*/ FFMA R4, R15, 0.5, R2 ; /* 0x3f0000000f047823 */
/* 0x000fe40000000002 */
/*0300*/ FFMA R5, R6, 0.5, R3 ; /* 0x3f00000006057823 */
/* 0x000fcc0000000003 */
/*0310*/ TEX.SCR.LL RZ, R4, R4, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e04047b60 */
/* 0x000f4400019e03ff */
/*0320*/ FMUL R16, R4, c[0x0][0x170] ; /* 0x00005c0004107a20 */
/* 0x020fe40000400000 */
/*0330*/ FMUL R7, R5, c[0x0][0x170] ; /* 0x00005c0005077a20 */
/* 0x000fe40000400000 */
/*0340*/ FFMA R18, R16, 0.5, R2 ; /* 0x3f00000010127823 */
/* 0x000fe40000000002 */
/*0350*/ FFMA R19, R7, 0.5, R3 ; /* 0x3f00000007137823 */
/* 0x000fcc0000000003 */
/*0360*/ TEX.SCR.LL RZ, R18, R18, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e12127b60 */
/* 0x000f4400019e03ff */
/*0370*/ FMUL R17, R18, c[0x0][0x170] ; /* 0x00005c0012117a20 */
/* 0x020fe40000400000 */
/*0380*/ FMUL R20, R19, c[0x0][0x170] ; /* 0x00005c0013147a20 */
/* 0x000fe40000400000 */
/*0390*/ FADD R22, R17, R2 ; /* 0x0000000211167221 */
/* 0x000fe40000000000 */
/*03a0*/ FADD R23, R20, R3 ; /* 0x0000000314177221 */
/* 0x000fc80000000000 */
/*03b0*/ TEX.SCR.LL RZ, R12, R22, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e160c7b60 */
/* 0x000f4200019e03ff */
/*03c0*/ FFMA R16, R16, 2, R15 ; /* 0x4000000010107823 */
/* 0x000fe2000000000f */
/*03d0*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x000fe20000201800 */
/*03e0*/ FFMA R21, R7, 2, R6 ; /* 0x4000000007157823 */
/* 0x000fe40000000006 */
/*03f0*/ FFMA R15, R17, 2, R16 ; /* 0x40000000110f7823 */
/* 0x000fe40000000010 */
/*0400*/ FFMA R20, R20, 2, R21 ; /* 0x4000000014147823 */
/* 0x000fc60000000015 */
/*0410*/ F2F.F64.F32 R6, R2 ; /* 0x0000000200067310 */
/* 0x000fe20000201800 */
/*0420*/ FFMA R12, R12, c[0x0][0x170], R15 ; /* 0x00005c000c0c7a23 */
/* 0x020fe4000000000f */
/*0430*/ FFMA R20, R13, c[0x0][0x170], R20 ; /* 0x00005c000d147a23 */
/* 0x000fca0000000014 */
/*0440*/ F2F.F64.F32 R16, R20 ; /* 0x0000001400107310 */
/* 0x000e300000201800 */
/*0450*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000e620000201800 */
/*0460*/ DFMA R16, R16, c[0x2][0x0], R4 ; /* 0x0080000010107a2b */
/* 0x001e0e0000000004 */
/*0470*/ F2F.F32.F64 R5, R16 ; /* 0x0000001000057310 */
/* 0x001fe20000301000 */
/*0480*/ DFMA R6, R12, c[0x2][0x0], R6 ; /* 0x008000000c067a2b */
/* 0x002e0e0000000006 */
/*0490*/ F2F.F32.F64 R4, R6 ; /* 0x0000000600047310 */
/* 0x001e240000301000 */
/*04a0*/ TEX.SCR.LL RZ, R2, R4, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e04027b60 */
/* 0x001f4400019e03ff */
/*04b0*/ FMUL R13, R2, c[0x0][0x170] ; /* 0x00005c00020d7a20 */
/* 0x020fe40000400000 */
/*04c0*/ FMUL R18, R3, c[0x0][0x170] ; /* 0x00005c0003127a20 */
/* 0x000fe40000400000 */
/*04d0*/ FFMA R2, R13, 0.5, R4 ; /* 0x3f0000000d027823 */
/* 0x000fe40000000004 */
/*04e0*/ FFMA R3, R18, 0.5, R5 ; /* 0x3f00000012037823 */
/* 0x000fcc0000000005 */
/*04f0*/ TEX.SCR.LL RZ, R2, R2, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e02027b60 */
/* 0x000f4400019e03ff */
/*0500*/ FMUL R12, R2, c[0x0][0x170] ; /* 0x00005c00020c7a20 */
/* 0x020fe40000400000 */
/*0510*/ FMUL R15, R3, c[0x0][0x170] ; /* 0x00005c00030f7a20 */
/* 0x000fe40000400000 */
/*0520*/ FFMA R16, R12, 0.5, R4 ; /* 0x3f0000000c107823 */
/* 0x000fe40000000004 */
/*0530*/ FFMA R17, R15, 0.5, R5 ; /* 0x3f0000000f117823 */
/* 0x000fcc0000000005 */
/*0540*/ TEX.SCR.LL RZ, R16, R16, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e10107b60 */
/* 0x000f4400019e03ff */
/*0550*/ FMUL R19, R16, c[0x0][0x170] ; /* 0x00005c0010137a20 */
/* 0x020fe40000400000 */
/*0560*/ FMUL R20, R17, c[0x0][0x170] ; /* 0x00005c0011147a20 */
/* 0x000fe40000400000 */
/*0570*/ FADD R6, R4, R19 ; /* 0x0000001304067221 */
/* 0x000fe40000000000 */
/*0580*/ FADD R7, R5, R20 ; /* 0x0000001405077221 */
/* 0x000fcc0000000000 */
/*0590*/ TEX.SCR.LL RZ, R6, R6, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e06067b60 */
/* 0x000f4200019e03ff */
/*05a0*/ FFMA R12, R12, 2, R13 ; /* 0x400000000c0c7823 */
/* 0x000fe2000000000d */
/*05b0*/ F2F.F64.F32 R2, R4 ; /* 0x0000000400027310 */
/* 0x000fe20000201800 */
/*05c0*/ FFMA R15, R15, 2, R18 ; /* 0x400000000f0f7823 */
/* 0x000fe40000000012 */
/*05d0*/ FFMA R19, R19, 2, R12 ; /* 0x4000000013137823 */
/* 0x000fe4000000000c */
/*05e0*/ FFMA R20, R20, 2, R15 ; /* 0x4000000014147823 */
/* 0x000fc6000000000f */
/*05f0*/ F2F.F64.F32 R12, R5 ; /* 0x00000005000c7310 */
/* 0x000fe20000201800 */
/*0600*/ FFMA R16, R6, c[0x0][0x170], R19 ; /* 0x00005c0006107a23 */
/* 0x020fe40000000013 */
/*0610*/ FFMA R20, R7, c[0x0][0x170], R20 ; /* 0x00005c0007147a23 */
/* 0x000fca0000000014 */
/*0620*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x000e300000201800 */
/*0630*/ F2F.F64.F32 R18, R20 ; /* 0x0000001400127310 */
/* 0x000e620000201800 */
/*0640*/ DFMA R2, R16, c[0x2][0x0], R2 ; /* 0x0080000010027a2b */
/* 0x001e0e0000000002 */
/*0650*/ F2F.F32.F64 R6, R2 ; /* 0x0000000200067310 */
/* 0x001fe20000301000 */
/*0660*/ DFMA R18, R18, c[0x2][0x0], R12 ; /* 0x0080000012127a2b */
/* 0x002e0e000000000c */
/*0670*/ F2F.F32.F64 R7, R18 ; /* 0x0000001200077310 */
/* 0x001e240000301000 */
/*0680*/ TEX.SCR.LL RZ, R22, R6, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e06167b60 */
/* 0x001f4400019e03ff */
/*0690*/ FMUL R13, R22, c[0x0][0x170] ; /* 0x00005c00160d7a20 */
/* 0x020fe40000400000 */
/*06a0*/ FMUL R12, R23, c[0x0][0x170] ; /* 0x00005c00170c7a20 */
/* 0x000fe40000400000 */
/*06b0*/ FFMA R22, R13, 0.5, R6 ; /* 0x3f0000000d167823 */
/* 0x000fe40000000006 */
/*06c0*/ FFMA R23, R12, 0.5, R7 ; /* 0x3f0000000c177823 */
/* 0x000fcc0000000007 */
/*06d0*/ TEX.SCR.LL RZ, R22, R22, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e16167b60 */
/* 0x000f4400019e03ff */
/*06e0*/ FMUL R15, R22, c[0x0][0x170] ; /* 0x00005c00160f7a20 */
/* 0x020fe40000400000 */
/*06f0*/ FMUL R20, R23, c[0x0][0x170] ; /* 0x00005c0017147a20 */
/* 0x000fe40000400000 */
/*0700*/ FFMA R24, R15, 0.5, R6 ; /* 0x3f0000000f187823 */
/* 0x000fe40000000006 */
/*0710*/ FFMA R25, R20, 0.5, R7 ; /* 0x3f00000014197823 */
/* 0x000fcc0000000007 */
/*0720*/ TEX.SCR.LL RZ, R24, R24, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e18187b60 */
/* 0x000f4400019e03ff */
/*0730*/ FMUL R19, R24, c[0x0][0x170] ; /* 0x00005c0018137a20 */
/* 0x020fe40000400000 */
/*0740*/ FMUL R18, R25, c[0x0][0x170] ; /* 0x00005c0019127a20 */
/* 0x000fe40000400000 */
/*0750*/ FADD R16, R6, R19 ; /* 0x0000001306107221 */
/* 0x000fe40000000000 */
/*0760*/ FADD R17, R7, R18 ; /* 0x0000001207117221 */
/* 0x000fcc0000000000 */
/*0770*/ TEX.SCR.LL RZ, R16, R16, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e10107b60 */
/* 0x000f4200019e03ff */
/*0780*/ FFMA R22, R15, 2, R13 ; /* 0x400000000f167823 */
/* 0x000fe2000000000d */
/*0790*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x000fe20000201800 */
/*07a0*/ FFMA R15, R20, 2, R12 ; /* 0x40000000140f7823 */
/* 0x000fe4000000000c */
/*07b0*/ FFMA R19, R19, 2, R22 ; /* 0x4000000013137823 */
/* 0x000fe40000000016 */
/*07c0*/ FFMA R20, R18, 2, R15 ; /* 0x4000000012147823 */
/* 0x000fc6000000000f */
/*07d0*/ F2F.F64.F32 R12, R7 ; /* 0x00000007000c7310 */
/* 0x000fe20000201800 */
/*07e0*/ FFMA R15, R16, c[0x0][0x170], R19 ; /* 0x00005c00100f7a23 */
/* 0x020fe40000000013 */
/*07f0*/ FFMA R22, R17, c[0x0][0x170], R20 ; /* 0x00005c0011167a23 */
/* 0x000fca0000000014 */
/*0800*/ F2F.F64.F32 R18, R15 ; /* 0x0000000f00127310 */
/* 0x000e300000201800 */
/*0810*/ F2F.F64.F32 R20, R22 ; /* 0x0000001600147310 */
/* 0x000e620000201800 */
/*0820*/ DFMA R18, R18, c[0x2][0x0], R2 ; /* 0x0080000012127a2b */
/* 0x001e0e0000000002 */
/*0830*/ F2F.F32.F64 R2, R18 ; /* 0x0000001200027310 */
/* 0x001fe20000301000 */
/*0840*/ DFMA R12, R20, c[0x2][0x0], R12 ; /* 0x00800000140c7a2b */
/* 0x002e0e000000000c */
/*0850*/ F2F.F32.F64 R3, R12 ; /* 0x0000000c00037310 */
/* 0x001e240000301000 */
/*0860*/ TEX.SCR.LL RZ, R16, R2, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e02107b60 */
/* 0x001f4400019e03ff */
/*0870*/ FMUL R21, R16, c[0x0][0x170] ; /* 0x00005c0010157a20 */
/* 0x020fe40000400000 */
/*0880*/ FMUL R20, R17, c[0x0][0x170] ; /* 0x00005c0011147a20 */
/* 0x000fe40000400000 */
/*0890*/ FFMA R26, R21, 0.5, R2 ; /* 0x3f000000151a7823 */
/* 0x000fe40000000002 */
/*08a0*/ FFMA R27, R20, 0.5, R3 ; /* 0x3f000000141b7823 */
/* 0x000fcc0000000003 */
/*08b0*/ TEX.SCR.LL RZ, R26, R26, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e1a1a7b60 */
/* 0x000f4400019e03ff */
/*08c0*/ FMUL R22, R26, c[0x0][0x170] ; /* 0x00005c001a167a20 */
/* 0x020fe40000400000 */
/*08d0*/ FMUL R15, R27, c[0x0][0x170] ; /* 0x00005c001b0f7a20 */
/* 0x000fe40000400000 */
/*08e0*/ FFMA R28, R22, 0.5, R2 ; /* 0x3f000000161c7823 */
/* 0x000fe40000000002 */
/*08f0*/ FFMA R29, R15, 0.5, R3 ; /* 0x3f0000000f1d7823 */
/* 0x000fc80000000003 */
/*0900*/ TEX.SCR.LL RZ, R12, R28, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e1c0c7b60 */
/* 0x000f4400019e03ff */
/*0910*/ FMUL R25, R12, c[0x0][0x170] ; /* 0x00005c000c197a20 */
/* 0x020fe40000400000 */
/*0920*/ FMUL R24, R13, c[0x0][0x170] ; /* 0x00005c000d187a20 */
/* 0x000fe40000400000 */
/*0930*/ FADD R16, R2, R25 ; /* 0x0000001902107221 */
/* 0x000fe40000000000 */
/*0940*/ FADD R17, R3, R24 ; /* 0x0000001803117221 */
/* 0x000fcc0000000000 */
/*0950*/ TEX.SCR.LL RZ, R16, R16, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e10107b60 */
/* 0x000f4200019e03ff */
/*0960*/ FFMA R26, R22, 2, R21 ; /* 0x40000000161a7823 */
/* 0x000fe20000000015 */
/*0970*/ LEA R12, P0, R9, c[0x0][0x160], 0x3 ; /* 0x00005800090c7a11 */
/* 0x000fe200078018ff */
/*0980*/ FFMA R15, R15, 2, R20 ; /* 0x400000000f0f7823 */
/* 0x000fe20000000014 */
/*0990*/ F2F.F64.F32 R18, R2 ; /* 0x0000000200127310 */
/* 0x000fe20000201800 */
/*09a0*/ FFMA R25, R25, 2, R26 ; /* 0x4000000019197823 */
/* 0x000fe2000000001a */
/*09b0*/ LEA.HI.X R13, R9, c[0x0][0x164], R0, 0x3, P0 ; /* 0x00005900090d7a11 */
/* 0x000fe200000f1c00 */
/*09c0*/ FFMA R24, R24, 2, R15 ; /* 0x4000000018187823 */
/* 0x000fe2000000000f */
/*09d0*/ IADD3 R11, P0, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe40007f1e0ff */
/*09e0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f5e0ff */
/*09f0*/ STG.E.64 [R12.64+0x8], R4 ; /* 0x000008040c007986 */
/* 0x0001e2000c101b04 */
/*0a00*/ F2F.F64.F32 R22, R3 ; /* 0x0000000300167310 */
/* 0x000fe20000201800 */
/*0a10*/ IADD3.X R10, R10, -0x1, RZ, P0, !PT ; /* 0xffffffff0a0a7810 */
/* 0x000fc400007fe4ff */
/*0a20*/ STG.E.64 [R12.64+0x18], R2 ; /* 0x000018020c007986 */
/* 0x0003e2000c101b04 */
/*0a30*/ ISETP.NE.U32.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05070 */
/*0a40*/ IADD3.X R0, RZ, R0, RZ, P2, !PT ; /* 0x00000000ff007210 */
/* 0x000fe200017fe4ff */
/*0a50*/ STG.E.64 [R12.64+0x10], R6 ; /* 0x000010060c007986 */
/* 0x0005e2000c101b04 */
/*0a60*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05300 */
/*0a70*/ FFMA R16, R16, c[0x0][0x170], R25 ; /* 0x00005c0010107a23 */
/* 0x020fe40000000019 */
/*0a80*/ FFMA R17, R17, c[0x0][0x170], R24 ; /* 0x00005c0011117a23 */
/* 0x000fe40000000018 */
/*0a90*/ F2F.F64.F32 R14, R16 ; /* 0x00000010000e7310 */
/* 0x000ef00000201800 */
/*0aa0*/ F2F.F64.F32 R4, R17 ; /* 0x0000001100047310 */
/* 0x001e220000201800 */
/*0ab0*/ DFMA R14, R14, c[0x2][0x0], R18 ; /* 0x008000000e0e7a2b */
/* 0x008e4e0000000012 */
/*0ac0*/ F2F.F32.F64 R2, R14 ; /* 0x0000000e00027310 */
/* 0x002fe20000301000 */
/*0ad0*/ DFMA R4, R4, c[0x2][0x0], R22 ; /* 0x0080000004047a2b */
/* 0x001e0e0000000016 */
/*0ae0*/ F2F.F32.F64 R3, R4 ; /* 0x0000000400037310 */
/* 0x001e240000301000 */
/*0af0*/ STG.E.64 [R12.64+0x20], R2 ; /* 0x000020020c007986 */
/* 0x0015e2000c101b04 */
/*0b00*/ @P0 BRA 0x2b0 ; /* 0xfffff7a000000947 */
/* 0x000fea000383ffff */
/*0b10*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0b20*/ LEA R4, P0, R9.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580009047a11 */
/* 0x040fe400078018ff */
/*0b30*/ IADD3 R8, P2, RZ, -R8, RZ ; /* 0x80000008ff087210 */
/* 0x000fe40007f5e0ff */
/*0b40*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0b50*/ LEA.HI.X R5, R9, c[0x0][0x164], R0, 0x3, P0 ; /* 0x0000590009057a11 */
/* 0x000fe400000f1c00 */
/*0b60*/ IADD3.X R0, RZ, -0x1, RZ, P2, !PT ; /* 0xffffffffff007810 */
/* 0x000fc400017fe4ff */
/*0b70*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0b80*/ MOV R9, 0xc2000000 ; /* 0xc200000000097802 */
/* 0x000fc80000000f00 */
/*0b90*/ TEX.SCR.LL RZ, R6, R2, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0902067b60 */
/* 0x005f4400019e03ff */
/*0ba0*/ FMUL R13, R6, c[0x0][0x170] ; /* 0x00005c00060d7a20 */
/* 0x020fe40000400000 */
/*0bb0*/ FMUL R14, R7, c[0x0][0x170] ; /* 0x00005c00070e7a20 */
/* 0x000fe40000400000 */
/*0bc0*/ FFMA R6, R13, 0.5, R2 ; /* 0x3f0000000d067823 */
/* 0x000fe40000000002 */
/*0bd0*/ FFMA R7, R14, 0.5, R3 ; /* 0x3f0000000e077823 */
/* 0x000fcc0000000003 */
/*0be0*/ TEX.SCR.LL RZ, R6, R6, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0906067b60 */
/* 0x000f4400019e03ff */
/*0bf0*/ FMUL R12, R6, c[0x0][0x170] ; /* 0x00005c00060c7a20 */
/* 0x020fe40000400000 */
/*0c00*/ FMUL R15, R7, c[0x0][0x170] ; /* 0x00005c00070f7a20 */
/* 0x000fe40000400000 */
/*0c10*/ FFMA R16, R12, 0.5, R2 ; /* 0x3f0000000c107823 */
/* 0x000fe40000000002 */
/*0c20*/ FFMA R17, R15, 0.5, R3 ; /* 0x3f0000000f117823 */
/* 0x000fcc0000000003 */
/*0c30*/ TEX.SCR.LL RZ, R16, R16, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0910107b60 */
/* 0x000f4400019e03ff */
/*0c40*/ FMUL R19, R16, c[0x0][0x170] ; /* 0x00005c0010137a20 */
/* 0x020fe40000400000 */
/*0c50*/ FMUL R18, R17, c[0x0][0x170] ; /* 0x00005c0011127a20 */
/* 0x000fe40000400000 */
/*0c60*/ FADD R20, R19, R2 ; /* 0x0000000213147221 */
/* 0x000fe40000000000 */
/*0c70*/ FADD R21, R18, R3 ; /* 0x0000000312157221 */
/* 0x000fc80000000000 */
/*0c80*/ TEX.SCR.LL RZ, R10, R20, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a09140a7b60 */
/* 0x000f4200019e03ff */
/*0c90*/ FFMA R22, R12, 2, R13 ; /* 0x400000000c167823 */
/* 0x000fe2000000000d */
/*0ca0*/ F2F.F64.F32 R6, R2 ; /* 0x0000000200067310 */
/* 0x000fe20000201800 */
/*0cb0*/ FFMA R15, R15, 2, R14 ; /* 0x400000000f0f7823 */
/* 0x000fe2000000000e */
/*0cc0*/ IADD3 R8, P0, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007f1e0ff */
/*0cd0*/ FFMA R19, R19, 2, R22 ; /* 0x4000000013137823 */
/* 0x000fe40000000016 */
/*0ce0*/ FFMA R18, R18, 2, R15 ; /* 0x4000000012127823 */
/* 0x000fe2000000000f */
/*0cf0*/ IADD3.X R0, RZ, R0, RZ, P0, !PT ; /* 0x00000000ff007210 */
/* 0x000fe400007fe4ff */
/*0d00*/ F2F.F64.F32 R12, R3 ; /* 0x00000003000c7310 */
/* 0x000fe20000201800 */
/*0d10*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0d20*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0d30*/ FFMA R14, R10, c[0x0][0x170], R19 ; /* 0x00005c000a0e7a23 */
/* 0x020fe40000000013 */
/*0d40*/ FFMA R18, R11, c[0x0][0x170], R18 ; /* 0x00005c000b127a23 */
/* 0x000fc80000000012 */
/*0d50*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000e300000201800 */
/*0d60*/ F2F.F64.F32 R10, R18 ; /* 0x00000012000a7310 */
/* 0x000e620000201800 */
/*0d70*/ DFMA R6, R14, c[0x2][0x0], R6 ; /* 0x008000000e067a2b */
/* 0x001e0e0000000006 */
/*0d80*/ F2F.F32.F64 R2, R6 ; /* 0x0000000600027310 */
/* 0x0011e20000301000 */
/*0d90*/ DFMA R10, R10, c[0x2][0x0], R12 ; /* 0x008000000a0a7a2b */
/* 0x002e4e000000000c */
/*0da0*/ F2F.F32.F64 R3, R10 ; /* 0x0000000a00037310 */
/* 0x002e620000301000 */
/*0db0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe40000000f00 */
/*0dc0*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0dd0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc80007f3e0ff */
/*0de0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0df0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0021e2000c101b04 */
/*0e00*/ @P0 BRA 0xb80 ; /* 0xfffffd7000000947 */
/* 0x000fea000383ffff */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
#include <errno.h>
#include <vector>
#include <time.h>
#include <sys/time.h>
using std::cout;
using std::cerr;
using std::endl;
using std::cin;
using std::vector;
constexpr size_t IM_X = 1300;
constexpr size_t IM_Y = 600;
constexpr size_t IM_V = sizeof(float2);
constexpr size_t IM_SIZE = IM_X * IM_Y * IM_V;
constexpr size_t XSR = 10;
constexpr size_t YSR = 5;
__device__
inline float2 mul(float s, float2 v) {
v.x *= s;
v.y *= s;
return v;
}
__device__
inline float2 add(float2 v1, float2 v2) {
v1.x += v2.x;
v1.y += v2.y;
return v1;
}
__global__
void integrate(float2* out, cudaTextureObject_t vecs, float dt, size_t steps) {
float2 k1, k2, k3, k4, p, q;
// Initial position
p.x = blockIdx.x * blockDim.x + threadIdx.x;
p.y = blockIdx.y * blockDim.y + threadIdx.y;
// Output location
size_t idx = (blockDim.x * gridDim.x * (int)p.y + (int)p.x) * steps;
// Apply sample rate
p.x *= XSR;
p.y *= YSR;
// Initial output
out[idx++] = p;
// Integrate forward
for (size_t i = 1; i < steps; i++) {
k1 = mul(dt, tex2D<float2>(vecs, p.x, p.y));
q = add(p, mul(0.5, k1));
k2 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, mul(0.5, k2));
k3 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, k3);
k4 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
p.x += (1.0/6.0)*(k1.x + 2*k2.x + 2*k3.x + k4.x);
p.y += (1.0/6.0)*(k1.y + 2*k2.y + 2*k3.y + k4.y);
out[idx++] = p;
}
}
__host__
cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
cerr << "CUDA Runtime Error: " << cudaGetErrorString(result) << endl;
abort();
}
return result;
}
__host__
int checkLinux(int result) {
if (result == -1) {
cerr << "Linux Runtime Error: (" << errno << ") " << strerror(errno) << endl;
abort();
}
return result;
}
__host__
void writeCSV(char* file, float2* output, size_t num_particles, size_t steps) {
const size_t file_size = num_particles * steps * (20 + 9 + 9 + 3);
umask(0111);
int fd = checkLinux(open(file, O_RDWR | O_CREAT | O_TRUNC, 06666));
checkLinux(ftruncate(fd, file_size));
char* map = (char*) mmap(NULL, file_size, PROT_WRITE, MAP_SHARED, fd, 0);
checkLinux((int)(size_t)map);
char* cur = map;
const char* header = "line_id, coordinate_x, coordinate_y\n";
checkLinux(write(fd, header, strlen(header)));
for (size_t i = 0; i < num_particles; i++)
for (size_t s = 0; s < steps; s++) {
float2 p = output[i * steps + s];
cur += sprintf(cur, "%llu,%.7f,%.7f\n", i, p.x, p.y);
}
msync(map, file_size, MS_SYNC);
munmap(map, file_size);
checkLinux(ftruncate(fd, cur - map));
checkLinux(close(fd));
}
vector<const char*> names;
vector<timespec> wall;
vector<timespec> proc;
vector<size_t> levels;
size_t cur_level = 0;
__host__
static inline void stime(const char* name) {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
names.push_back(name);
levels.push_back(cur_level++);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
__host__
static inline void ftime() {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
levels.push_back(--cur_level);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
// from https://gist.github.com/diabloneo/9619917
__host__
static inline void timespecDiff(timespec& a, timespec& b, timespec& result) {
result.tv_sec = a.tv_sec - b.tv_sec;
result.tv_nsec = a.tv_nsec - b.tv_nsec;
if (result.tv_nsec < 0) {
--result.tv_sec;
result.tv_nsec += 1000000000L;
}
}
__host__
static inline double timespecToMs(const timespec& t) {
return (double)t.tv_sec * 1000.0 + (double)t.tv_nsec / 1000000.0;
}
__host__
static size_t ptime(const char* name, size_t n = 0, size_t i = 0, size_t l = 0) {
while (n < names.size() and levels[i] == l) {
size_t j = i + 1;
auto& sw = wall[i];
auto& sp = proc[i];
int jumped = j;
while (l < levels[j]) j++;
auto& fw = wall[j];
auto& fp = proc[j];
timespec w, p;
timespecDiff(fw, sw, w);
timespecDiff(fp, sp, p);
for (size_t k = 0; k < l; k++)
printf("\t");
printf("\"%s\", \"%s\", %.3f, %.3f\n",
name,
names[n++],
timespecToMs(w),
timespecToMs(p));
if (jumped < j)
n = ptime(name, n, jumped, l + 1);
i = j + 1;
}
return n;
}
__host__
int main(int argc, char **argv) {
stime("Program");
stime("Setup");
if (argc != 3) {
ftime();
ftime();
printf("Usage: ./main image output\n");
return 0;
}
float dt = 1;
//cout << "Enter delta time: ";
//cin >> dt;
size_t steps = 100;
//cout << "Enter number of steps: ";
//cin >> steps;
// Opening file
stime("Read input");
int fd = checkLinux(open(argv[1], O_RDONLY));
// Allocating + Mapping host memory
float2 *im;
cudaArray* im_d;
float2 *output_d;
float2 *output;
// Memory mapping does not provide a performance boost.
// It trades off between copy time to GPU or copy to RAM.
checkCuda(cudaMallocHost(&im, IM_SIZE));
checkLinux(read(fd, im, IM_SIZE));
close(fd);
ftime();
// Modified basic cuda texture manipulation obtained from
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
// Allocate CUDA array in device memory
stime("Copy to GPU");
cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc(32, 32, 0, 0,
cudaChannelFormatKindFloat);
checkCuda(cudaMallocArray(&im_d, &channelDesc, IM_X, IM_Y));
checkCuda(cudaMemcpyToArray(im_d, 0, 0, im, IM_SIZE, cudaMemcpyHostToDevice));
ftime();
// Specify texture
stime("Initialize Texture");
struct cudaResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = cudaResourceTypeArray;
resDesc.res.array.array = im_d;
// Specify texture object parameters
struct cudaTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.addressMode[0] = cudaAddressModeBorder;
texDesc.addressMode[1] = cudaAddressModeBorder;
texDesc.filterMode = cudaFilterModeLinear;
texDesc.readMode = cudaReadModeElementType;
texDesc.maxAnisotropy = 2;
texDesc.normalizedCoords = false;
// Create texture object
cudaTextureObject_t imTex = 0;
checkCuda(cudaCreateTextureObject(&imTex, &resDesc, &texDesc, NULL));
ftime();
dim3 block(26, 24, 1);
dim3 grid(5, 5, 1);
// dim3 block(1, 24, 1);
// dim3 grid(1, 25, 1);
const size_t num_particles = block.x * grid.x * block.y * grid.y;
const size_t out_size = num_particles * sizeof(float2) * steps;
stime("Allocate Output");
checkCuda(cudaMalloc(&output_d, out_size));
ftime();
ftime();
stime("Computation");
integrate<<<grid, block>>>(output_d, imTex, dt, steps);
ftime();
// Copying from device to host
stime("Copy to host");
checkCuda(cudaMallocHost(&output, out_size));
checkCuda(cudaMemcpy(output, output_d, out_size, cudaMemcpyDeviceToHost));
ftime();
stime("Free device memory");
checkCuda(cudaFree(output_d));
checkCuda(cudaDestroyTextureObject(imTex));
checkCuda(cudaFreeArray(im_d));
ftime();
//stime("Write");
//writeCSV(argv[2], output, num_particles, steps);
//ftime();
stime("Free host memory");
checkCuda(cudaFreeHost(im));
checkCuda(cudaFreeHost(output));
ftime();
ftime();
ptime("GPU");
return 0;
} | .file "tmpxft_000a7733_00000000-6_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC3:
.string "\"%s\", \"%s\", %.3f, %.3f\n"
#NO_APP
.text
.type _ZL5ptimePKcmmm, @function
_ZL5ptimePKcmmm:
.LFB4088:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 40(%rsp)
movq %rsi, %r14
movq 8+names(%rip), %rax
subq names(%rip), %rax
sarq $3, %rax
cmpq %rax, %rsi
jnb .L18
movq %rcx, %r12
leaq .LC0(%rip), %r13
jmp .L2
.L18:
movq %rsi, %rax
jmp .L1
.L21:
subq $1, %r9
movq %r9, 8(%rsp)
addq $1000000000, %rax
movq %rax, 24(%rsp)
jmp .L5
.L6:
testq %r12, %r12
je .L7
movl $0, %ebp
.L8:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq %rbp, %r12
jne .L8
.L7:
leaq 1(%r14), %rbp
pxor %xmm2, %xmm2
cvtsi2sdq %r15, %xmm2
mulsd .LC1(%rip), %xmm2
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LC2(%rip), %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm3, %xmm3
cvtsi2sdq 24(%rsp), %xmm3
divsd .LC2(%rip), %xmm3
addsd %xmm3, %xmm0
movq names(%rip), %rax
movq (%rax,%r14,8), %rcx
addsd %xmm2, %xmm1
movq 40(%rsp), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movslq 36(%rsp), %rdx
movq %rbp, %r14
cmpq %rbx, %rdx
jb .L20
.L9:
leaq 1(%rbx), %rdx
movq 8+names(%rip), %rax
subq names(%rip), %rax
sarq $3, %rax
cmpq %rax, %r14
jnb .L12
.L2:
movq levels(%rip), %rax
leaq 0(,%rdx,8), %r8
cmpq %r12, (%rax,%rdx,8)
jne .L13
leaq 1(%rdx), %rbx
movq wall(%rip), %rcx
salq $4, %rdx
leaq (%rcx,%rdx), %rdi
movq proc(%rip), %rsi
addq %rsi, %rdx
movl %ebx, 36(%rsp)
cmpq 8(%rax,%r8), %r12
jnb .L10
.L4:
addq $1, %rbx
cmpq (%rax,%rbx,8), %r12
jb .L4
.L10:
movq %rbx, %rax
salq $4, %rax
addq %rax, %rcx
addq %rax, %rsi
movq (%rcx), %rax
subq (%rdi), %rax
movq %rax, %r9
movq %rax, 8(%rsp)
movq 8(%rcx), %rax
subq 8(%rdi), %rax
movq %rax, 24(%rsp)
js .L21
.L5:
movq (%rsi), %r15
subq (%rdx), %r15
movq 8(%rsi), %rax
subq 8(%rdx), %rax
movq %rax, 16(%rsp)
jns .L6
subq $1, %r15
addq $1000000000, %rax
movq %rax, 16(%rsp)
jmp .L6
.L20:
leaq 1(%r12), %rcx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call _ZL5ptimePKcmmm
movq %rax, %r14
jmp .L9
.L12:
movq %r14, %rax
jmp .L1
.L13:
movq %r14, %rax
.L1:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4088:
.size _ZL5ptimePKcmmm, .-_ZL5ptimePKcmmm
.section .text._ZNSt6vectorImSaImEED2Ev,"axG",@progbits,_ZNSt6vectorImSaImEED5Ev,comdat
.align 2
.weak _ZNSt6vectorImSaImEED2Ev
.type _ZNSt6vectorImSaImEED2Ev, @function
_ZNSt6vectorImSaImEED2Ev:
.LFB4952:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L25
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L25:
ret
.cfi_endproc
.LFE4952:
.size _ZNSt6vectorImSaImEED2Ev, .-_ZNSt6vectorImSaImEED2Ev
.weak _ZNSt6vectorImSaImEED1Ev
.set _ZNSt6vectorImSaImEED1Ev,_ZNSt6vectorImSaImEED2Ev
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4092:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZNSt6vectorIPKcSaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorIPKcSaIS1_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPKcSaIS1_EED2Ev
.type _ZNSt6vectorIPKcSaIS1_EED2Ev, @function
_ZNSt6vectorIPKcSaIS1_EED2Ev:
.LFB4946:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L33
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L33:
ret
.cfi_endproc
.LFE4946:
.size _ZNSt6vectorIPKcSaIS1_EED2Ev, .-_ZNSt6vectorIPKcSaIS1_EED2Ev
.weak _ZNSt6vectorIPKcSaIS1_EED1Ev
.set _ZNSt6vectorIPKcSaIS1_EED1Ev,_ZNSt6vectorIPKcSaIS1_EED2Ev
.section .text._ZNSt6vectorI8timespecSaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorI8timespecSaIS0_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorI8timespecSaIS0_EED2Ev
.type _ZNSt6vectorI8timespecSaIS0_EED2Ev, @function
_ZNSt6vectorI8timespecSaIS0_EED2Ev:
.LFB4949:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L39
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L39:
ret
.cfi_endproc
.LFE4949:
.size _ZNSt6vectorI8timespecSaIS0_EED2Ev, .-_ZNSt6vectorI8timespecSaIS0_EED2Ev
.weak _ZNSt6vectorI8timespecSaIS0_EED1Ev
.set _ZNSt6vectorI8timespecSaIS0_EED1Ev,_ZNSt6vectorI8timespecSaIS0_EED2Ev
.section .rodata.str1.1
.LC4:
.string "CUDA Runtime Error: "
.text
.globl _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB4051:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L47
movl $0, %eax
ret
.L47:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC4(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call abort@PLT
.cfi_endproc
.LFE4051:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.section .rodata.str1.1
.LC5:
.string "Linux Runtime Error: ("
.LC6:
.string ") "
.text
.globl _Z10checkLinuxi
.type _Z10checkLinuxi, @function
_Z10checkLinuxi:
.LFB4052:
.cfi_startproc
endbr64
cmpl $-1, %edi
je .L53
movl %edi, %eax
ret
.L53:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl (%rbx), %edi
call strerror@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call abort@PLT
.cfi_endproc
.LFE4052:
.size _Z10checkLinuxi, .-_Z10checkLinuxi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "line_id, coordinate_x, coordinate_y\n"
.section .rodata.str1.1
.LC8:
.string "%llu,%.7f,%.7f\n"
.text
.globl _Z8writeCSVPcP6float2mm
.type _Z8writeCSVPcP6float2mm, @function
_Z8writeCSVPcP6float2mm:
.LFB4053:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %r13
movq %rsi, 16(%rsp)
movq %rdx, %r14
movq %rdx, 24(%rsp)
movq %rcx, %r12
movq %rdx, %rax
imulq %rcx, %rax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,8), %rbx
movl $73, %edi
call umask@PLT
movl $3510, %edx
movl $578, %esi
movq %rbp, %rdi
movl $0, %eax
call open@PLT
movl %eax, %edi
call _Z10checkLinuxi
movl %eax, %r15d
movl %eax, 52(%rsp)
movq %rbx, %rsi
movl %eax, %edi
call ftruncate@PLT
movl %eax, %edi
call _Z10checkLinuxi
movl $0, %r9d
movl %r15d, %r8d
movl $1, %ecx
movl $2, %edx
movq %rbx, %rsi
movl $0, %edi
call mmap@PLT
movq %rax, %rbp
movq %rax, 40(%rsp)
movl %eax, %edi
call _Z10checkLinuxi
movl $36, %edx
leaq .LC7(%rip), %rsi
movl %r15d, %edi
call write@PLT
movl %eax, %edi
call _Z10checkLinuxi
testq %r14, %r14
je .L60
movq %r12, %rax
leaq 0(,%r12,8), %rdi
addq %rdi, %r13
movl $0, %r15d
movl $0, %r14d
leaq .LC8(%rip), %r12
movq %rdi, 32(%rsp)
movq %rax, %rdi
movq %rbx, 56(%rsp)
jmp .L56
.L64:
movq %r14, 8(%rsp)
movq %rdi, %r14
.L57:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rbx), %xmm1
movq %r15, %r8
movq %r12, %rcx
movq $-1, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $2, %eax
call __sprintf_chk@PLT
cltq
addq %rax, %rbp
addq $8, %rbx
cmpq %r13, %rbx
jne .L57
movq %r14, %rdi
movq 8(%rsp), %r14
.L59:
addq $1, %r15
addq %rdi, %r14
movq 32(%rsp), %rax
addq %rax, %r13
cmpq %r15, 24(%rsp)
je .L63
.L56:
movq 16(%rsp), %rax
leaq (%rax,%r14,8), %rbx
testq %rdi, %rdi
jne .L64
jmp .L59
.L60:
movq 40(%rsp), %rbp
jmp .L55
.L63:
movq 56(%rsp), %rbx
.L55:
movl $4, %edx
movq %rbx, %rsi
movq 40(%rsp), %r14
movq %r14, %rdi
call msync@PLT
movq %rbx, %rsi
movq %r14, %rdi
call munmap@PLT
movq %rbp, %rsi
subq %r14, %rsi
movl 52(%rsp), %ebx
movl %ebx, %edi
call ftruncate@PLT
movl %eax, %edi
call _Z10checkLinuxi
movl %ebx, %edi
call close@PLT
movl %eax, %edi
call _Z10checkLinuxi
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4053:
.size _Z8writeCSVPcP6float2mm, .-_Z8writeCSVPcP6float2mm
.globl _Z37__device_stub__Z9integrateP6float2yfmP6float2yfm
.type _Z37__device_stub__Z9integrateP6float2yfmP6float2yfm, @function
_Z37__device_stub__Z9integrateP6float2yfmP6float2yfm:
.LFB4114:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9integrateP6float2yfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4114:
.size _Z37__device_stub__Z9integrateP6float2yfmP6float2yfm, .-_Z37__device_stub__Z9integrateP6float2yfmP6float2yfm
.globl _Z9integrateP6float2yfm
.type _Z9integrateP6float2yfm, @function
_Z9integrateP6float2yfm:
.LFB4115:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9integrateP6float2yfmP6float2yfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4115:
.size _Z9integrateP6float2yfm, .-_Z9integrateP6float2yfm
.section .rodata.str1.1
.LC9:
.string "_Z9integrateP6float2yfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4117:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9integrateP6float2yfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4117:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.str1.1,"aMS",@progbits,1
.LC10:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,"axG",@progbits,_ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.type _ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, @function
_ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_:
.LFB4635:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L93
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L79
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L80
jmp .L87
.L93:
leaq .LC10(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L94:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L82
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L86
.L79:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L87:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L80:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L94
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L84
.L82:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L84:
addq %rbp, %r15
testq %r13, %r13
je .L85
movq 16(%rbx), %rsi
subq %r13, %rsi
.L86:
movq %r13, %rdi
call _ZdlPvm@PLT
.L85:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4635:
.size _ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, .-_ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.section .text._ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,"axG",@progbits,_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.type _ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, @function
_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_:
.LFB4643:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $4, %rax
movabsq $576460752303423487, %rdx
cmpq %rdx, %rax
je .L112
movq %rdi, %rbx
movq %rsi, %r14
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L98
movabsq $576460752303423487, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, (%rsp)
movq %rsi, %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L99
jmp .L106
.L112:
leaq .LC10(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L113:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 16(%r12,%r15), %r15
subq %r14, %rbp
testq %rbp, %rbp
jg .L101
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L105
.L98:
movq %rsi, %r15
subq %r13, %r15
movabsq $576460752303423487, %rax
movq %rax, (%rsp)
.L106:
movq (%rsp), %rdi
salq $4, %rdi
call _Znwm@PLT
movq %rax, %r12
.L99:
movq 8(%rsp), %rax
movdqu (%rax), %xmm0
movups %xmm0, (%r12,%r15)
testq %r15, %r15
jg .L113
leaq 16(%r12,%r15), %r15
subq %r14, %rbp
testq %rbp, %rbp
jle .L103
.L101:
movq %rbp, %rdx
movq %r14, %rsi
movq %r15, %rdi
call memcpy@PLT
.L103:
addq %rbp, %r15
testq %r13, %r13
je .L104
movq 16(%rbx), %rsi
subq %r13, %rsi
.L105:
movq %r13, %rdi
call _ZdlPvm@PLT
.L104:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
movq (%rsp), %rax
salq $4, %rax
addq %r12, %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, .-_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.section .text._ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_,"axG",@progbits,_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_,comdat
.align 2
.weak _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_
.type _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_, @function
_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_:
.LFB4450:
.cfi_startproc
endbr64
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
je .L115
movdqu (%rsi), %xmm0
movups %xmm0, (%rax)
addq $16, 8(%rdi)
ret
.L115:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movq %rax, %rsi
call _ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4450:
.size _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_, .-_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_
.section .text._ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.type _ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, @function
_ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_:
.LFB4649:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L137
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L123
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L124
jmp .L131
.L137:
leaq .LC10(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L138:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L126
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L130
.L123:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L131:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L124:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L138
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L128
.L126:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L128:
addq %rbp, %r15
testq %r13, %r13
je .L129
movq 16(%rbx), %rsi
subq %r13, %rsi
.L130:
movq %r13, %rdi
call _ZdlPvm@PLT
.L129:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4649:
.size _ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, .-_ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.text
.type _ZL5ftimev, @function
_ZL5ftimev:
.LFB4085:
.cfi_startproc
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 16(%rsp), %rsi
movl $2, %edi
call clock_gettime@PLT
movq cur_level(%rip), %rax
subq $1, %rax
movq %rax, cur_level(%rip)
movq 8+levels(%rip), %rsi
cmpq 16+levels(%rip), %rsi
je .L140
movq %rax, (%rsi)
addq $8, 8+levels(%rip)
.L141:
movq %rsp, %rsi
leaq wall(%rip), %rdi
call _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_
leaq 16(%rsp), %rsi
leaq proc(%rip), %rdi
call _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L144
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L140:
.cfi_restore_state
leaq cur_level(%rip), %rdx
leaq levels(%rip), %rdi
call _ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
jmp .L141
.L144:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4085:
.size _ZL5ftimev, .-_ZL5ftimev
.section .text._ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.type _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, @function
_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_:
.LFB4771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L162
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L148
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L149
jmp .L156
.L162:
leaq .LC10(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L163:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L151
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L155
.L148:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L156:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L149:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L163
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L153
.L151:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L153:
addq %rbp, %r15
testq %r13, %r13
je .L154
movq 16(%rbx), %rsi
subq %r13, %rsi
.L155:
movq %r13, %rdi
call _ZdlPvm@PLT
.L154:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4771:
.size _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, .-_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.text
.type _ZL5stimePKc, @function
_ZL5stimePKc:
.LFB4084:
.cfi_startproc
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 48(%rsp), %rsi
movl $2, %edi
call clock_gettime@PLT
movq 8+names(%rip), %rsi
cmpq 16+names(%rip), %rsi
je .L165
movq 8(%rsp), %rax
movq %rax, (%rsi)
addq $8, 8+names(%rip)
.L166:
movq cur_level(%rip), %rax
leaq 1(%rax), %rdx
movq %rdx, cur_level(%rip)
movq %rax, 24(%rsp)
movq 8+levels(%rip), %rsi
cmpq 16+levels(%rip), %rsi
je .L167
movq %rax, (%rsi)
addq $8, 8+levels(%rip)
.L168:
leaq 32(%rsp), %rsi
leaq wall(%rip), %rdi
call _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_
leaq 48(%rsp), %rsi
leaq proc(%rip), %rdi
call _ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L171
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L165:
.cfi_restore_state
leaq 8(%rsp), %rdx
leaq names(%rip), %rdi
call _ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
jmp .L166
.L167:
leaq 24(%rsp), %rdx
leaq levels(%rip), %rdi
call _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
jmp .L168
.L171:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4084:
.size _ZL5stimePKc, .-_ZL5stimePKc
.section .rodata.str1.1
.LC11:
.string "Program"
.LC12:
.string "Setup"
.LC13:
.string "Usage: ./main image output\n"
.LC14:
.string "Read input"
.LC15:
.string "Copy to GPU"
.LC16:
.string "Initialize Texture"
.LC17:
.string "Allocate Output"
.LC18:
.string "Computation"
.LC20:
.string "Copy to host"
.LC21:
.string "Free device memory"
.LC22:
.string "Free host memory"
.LC23:
.string "GPU"
.text
.globl main
.type main, @function
main:
.LFB4089:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $248, %rsp
.cfi_def_cfa_offset 272
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq .LC11(%rip), %rdi
call _ZL5stimePKc
leaq .LC12(%rip), %rdi
call _ZL5stimePKc
cmpl $3, %ebx
je .L173
call _ZL5ftimev
call _ZL5ftimev
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L174:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L178
movl $0, %eax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L173:
.cfi_restore_state
leaq .LC14(%rip), %rdi
call _ZL5stimePKc
movq 8(%rbp), %rdi
movl $0, %esi
call __open_2@PLT
movl %eax, %edi
call _Z10checkLinuxi
movl %eax, %ebx
movq %rsp, %rdi
movl $0, %edx
movl $6240000, %esi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq $-1, %rcx
movl $6240000, %edx
movq (%rsp), %rsi
movl %ebx, %edi
call __read_chk@PLT
movl %eax, %edi
call _Z10checkLinuxi
movl %ebx, %edi
call close@PLT
call _ZL5ftimev
leaq .LC15(%rip), %rdi
call _ZL5stimePKc
leaq 64(%rsp), %rbx
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $32, %edx
movl $32, %esi
movq %rbx, %rdi
call cudaCreateChannelDesc@PLT
leaq 8(%rsp), %rdi
movl $0, %r8d
movl $600, %ecx
movl $1300, %edx
movq %rbx, %rsi
call cudaMallocArray@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $1, %r9d
movl $6240000, %r8d
movq (%rsp), %rcx
movl $0, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemcpyToArray@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call _ZL5ftimev
leaq .LC16(%rip), %rdi
call _ZL5stimePKc
leaq 96(%rsp), %rsi
movl $0, %eax
movl $16, %ecx
movq %rsi, %rdi
rep stosl
movq 8(%rsp), %rdx
movq %rdx, 104(%rsp)
leaq 160(%rsp), %r8
leaq 168(%rsp), %rdx
movl $16, %ecx
movq %rdx, %rdi
rep stosl
movl $3, 160(%rsp)
movl $3, 164(%rsp)
movl $1, 172(%rsp)
movl $2, 204(%rsp)
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq %r8, %rdx
call cudaCreateTextureObject@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call _ZL5ftimev
movl $1, 48(%rsp)
movl $1, 60(%rsp)
leaq .LC17(%rip), %rdi
call _ZL5stimePKc
leaq 16(%rsp), %rdi
movl $12480000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call _ZL5ftimev
call _ZL5ftimev
leaq .LC18(%rip), %rdi
call _ZL5stimePKc
movl $5, 52(%rsp)
movl $5, 56(%rsp)
movl $26, 40(%rsp)
movl $24, 44(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L179
.L175:
call _ZL5ftimev
leaq .LC20(%rip), %rdi
call _ZL5stimePKc
leaq 24(%rsp), %rdi
movl $0, %edx
movl $12480000, %esi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $2, %ecx
movl $12480000, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call _ZL5ftimev
leaq .LC21(%rip), %rdi
call _ZL5stimePKc
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 32(%rsp), %rdi
call cudaDestroyTextureObject@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 8(%rsp), %rdi
call cudaFreeArray@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call _ZL5ftimev
leaq .LC22(%rip), %rdi
call _ZL5stimePKc
movq (%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call _ZL5ftimev
call _ZL5ftimev
movl $0, %ecx
movl $0, %edx
movl $0, %esi
leaq .LC23(%rip), %rdi
call _ZL5ptimePKcmmm
jmp .L174
.L179:
movl $100, %edx
movss .LC19(%rip), %xmm0
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z9integrateP6float2yfmP6float2yfm
jmp .L175
.L178:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4089:
.size main, .-main
.type _GLOBAL__sub_I__Z9checkCuda9cudaError, @function
_GLOBAL__sub_I__Z9checkCuda9cudaError:
.LFB4954:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq $0, names(%rip)
movq $0, 8+names(%rip)
movq $0, 16+names(%rip)
leaq __dso_handle(%rip), %rbx
movq %rbx, %rdx
leaq names(%rip), %rsi
leaq _ZNSt6vectorIPKcSaIS1_EED1Ev(%rip), %rdi
call __cxa_atexit@PLT
movq $0, wall(%rip)
movq $0, 8+wall(%rip)
movq $0, 16+wall(%rip)
movq %rbx, %rdx
leaq wall(%rip), %rsi
leaq _ZNSt6vectorI8timespecSaIS0_EED1Ev(%rip), %rbp
movq %rbp, %rdi
call __cxa_atexit@PLT
movq $0, proc(%rip)
movq $0, 8+proc(%rip)
movq $0, 16+proc(%rip)
movq %rbx, %rdx
leaq proc(%rip), %rsi
movq %rbp, %rdi
call __cxa_atexit@PLT
movq $0, levels(%rip)
movq $0, 8+levels(%rip)
movq $0, 16+levels(%rip)
movq %rbx, %rdx
leaq levels(%rip), %rsi
leaq _ZNSt6vectorImSaImEED1Ev(%rip), %rdi
call __cxa_atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4954:
.size _GLOBAL__sub_I__Z9checkCuda9cudaError, .-_GLOBAL__sub_I__Z9checkCuda9cudaError
.section .init_array
.align 8
.quad _GLOBAL__sub_I__Z9checkCuda9cudaError
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cur_level
.bss
.align 8
.type cur_level, @object
.size cur_level, 8
cur_level:
.zero 8
.globl levels
.align 16
.type levels, @object
.size levels, 24
levels:
.zero 24
.globl proc
.align 16
.type proc, @object
.size proc, 24
proc:
.zero 24
.globl wall
.align 16
.type wall, @object
.size wall, 24
wall:
.zero 24
.globl names
.align 16
.type names, @object
.size names, 24
names:
.zero 24
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC19:
.long 1065353216
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
#include <errno.h>
#include <vector>
#include <time.h>
#include <sys/time.h>
using std::cout;
using std::cerr;
using std::endl;
using std::cin;
using std::vector;
constexpr size_t IM_X = 1300;
constexpr size_t IM_Y = 600;
constexpr size_t IM_V = sizeof(float2);
constexpr size_t IM_SIZE = IM_X * IM_Y * IM_V;
constexpr size_t XSR = 10;
constexpr size_t YSR = 5;
__device__
inline float2 mul(float s, float2 v) {
v.x *= s;
v.y *= s;
return v;
}
__device__
inline float2 add(float2 v1, float2 v2) {
v1.x += v2.x;
v1.y += v2.y;
return v1;
}
__global__
void integrate(float2* out, cudaTextureObject_t vecs, float dt, size_t steps) {
float2 k1, k2, k3, k4, p, q;
// Initial position
p.x = blockIdx.x * blockDim.x + threadIdx.x;
p.y = blockIdx.y * blockDim.y + threadIdx.y;
// Output location
size_t idx = (blockDim.x * gridDim.x * (int)p.y + (int)p.x) * steps;
// Apply sample rate
p.x *= XSR;
p.y *= YSR;
// Initial output
out[idx++] = p;
// Integrate forward
for (size_t i = 1; i < steps; i++) {
k1 = mul(dt, tex2D<float2>(vecs, p.x, p.y));
q = add(p, mul(0.5, k1));
k2 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, mul(0.5, k2));
k3 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, k3);
k4 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
p.x += (1.0/6.0)*(k1.x + 2*k2.x + 2*k3.x + k4.x);
p.y += (1.0/6.0)*(k1.y + 2*k2.y + 2*k3.y + k4.y);
out[idx++] = p;
}
}
__host__
cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
cerr << "CUDA Runtime Error: " << cudaGetErrorString(result) << endl;
abort();
}
return result;
}
__host__
int checkLinux(int result) {
if (result == -1) {
cerr << "Linux Runtime Error: (" << errno << ") " << strerror(errno) << endl;
abort();
}
return result;
}
__host__
void writeCSV(char* file, float2* output, size_t num_particles, size_t steps) {
const size_t file_size = num_particles * steps * (20 + 9 + 9 + 3);
umask(0111);
int fd = checkLinux(open(file, O_RDWR | O_CREAT | O_TRUNC, 06666));
checkLinux(ftruncate(fd, file_size));
char* map = (char*) mmap(NULL, file_size, PROT_WRITE, MAP_SHARED, fd, 0);
checkLinux((int)(size_t)map);
char* cur = map;
const char* header = "line_id, coordinate_x, coordinate_y\n";
checkLinux(write(fd, header, strlen(header)));
for (size_t i = 0; i < num_particles; i++)
for (size_t s = 0; s < steps; s++) {
float2 p = output[i * steps + s];
cur += sprintf(cur, "%llu,%.7f,%.7f\n", i, p.x, p.y);
}
msync(map, file_size, MS_SYNC);
munmap(map, file_size);
checkLinux(ftruncate(fd, cur - map));
checkLinux(close(fd));
}
vector<const char*> names;
vector<timespec> wall;
vector<timespec> proc;
vector<size_t> levels;
size_t cur_level = 0;
__host__
static inline void stime(const char* name) {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
names.push_back(name);
levels.push_back(cur_level++);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
__host__
static inline void ftime() {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
levels.push_back(--cur_level);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
// from https://gist.github.com/diabloneo/9619917
__host__
static inline void timespecDiff(timespec& a, timespec& b, timespec& result) {
result.tv_sec = a.tv_sec - b.tv_sec;
result.tv_nsec = a.tv_nsec - b.tv_nsec;
if (result.tv_nsec < 0) {
--result.tv_sec;
result.tv_nsec += 1000000000L;
}
}
__host__
static inline double timespecToMs(const timespec& t) {
return (double)t.tv_sec * 1000.0 + (double)t.tv_nsec / 1000000.0;
}
__host__
static size_t ptime(const char* name, size_t n = 0, size_t i = 0, size_t l = 0) {
while (n < names.size() and levels[i] == l) {
size_t j = i + 1;
auto& sw = wall[i];
auto& sp = proc[i];
int jumped = j;
while (l < levels[j]) j++;
auto& fw = wall[j];
auto& fp = proc[j];
timespec w, p;
timespecDiff(fw, sw, w);
timespecDiff(fp, sp, p);
for (size_t k = 0; k < l; k++)
printf("\t");
printf("\"%s\", \"%s\", %.3f, %.3f\n",
name,
names[n++],
timespecToMs(w),
timespecToMs(p));
if (jumped < j)
n = ptime(name, n, jumped, l + 1);
i = j + 1;
}
return n;
}
__host__
int main(int argc, char **argv) {
stime("Program");
stime("Setup");
if (argc != 3) {
ftime();
ftime();
printf("Usage: ./main image output\n");
return 0;
}
float dt = 1;
//cout << "Enter delta time: ";
//cin >> dt;
size_t steps = 100;
//cout << "Enter number of steps: ";
//cin >> steps;
// Opening file
stime("Read input");
int fd = checkLinux(open(argv[1], O_RDONLY));
// Allocating + Mapping host memory
float2 *im;
cudaArray* im_d;
float2 *output_d;
float2 *output;
// Memory mapping does not provide a performance boost.
// It trades off between copy time to GPU or copy to RAM.
checkCuda(cudaMallocHost(&im, IM_SIZE));
checkLinux(read(fd, im, IM_SIZE));
close(fd);
ftime();
// Modified basic cuda texture manipulation obtained from
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
// Allocate CUDA array in device memory
stime("Copy to GPU");
cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc(32, 32, 0, 0,
cudaChannelFormatKindFloat);
checkCuda(cudaMallocArray(&im_d, &channelDesc, IM_X, IM_Y));
checkCuda(cudaMemcpyToArray(im_d, 0, 0, im, IM_SIZE, cudaMemcpyHostToDevice));
ftime();
// Specify texture
stime("Initialize Texture");
struct cudaResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = cudaResourceTypeArray;
resDesc.res.array.array = im_d;
// Specify texture object parameters
struct cudaTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.addressMode[0] = cudaAddressModeBorder;
texDesc.addressMode[1] = cudaAddressModeBorder;
texDesc.filterMode = cudaFilterModeLinear;
texDesc.readMode = cudaReadModeElementType;
texDesc.maxAnisotropy = 2;
texDesc.normalizedCoords = false;
// Create texture object
cudaTextureObject_t imTex = 0;
checkCuda(cudaCreateTextureObject(&imTex, &resDesc, &texDesc, NULL));
ftime();
dim3 block(26, 24, 1);
dim3 grid(5, 5, 1);
// dim3 block(1, 24, 1);
// dim3 grid(1, 25, 1);
const size_t num_particles = block.x * grid.x * block.y * grid.y;
const size_t out_size = num_particles * sizeof(float2) * steps;
stime("Allocate Output");
checkCuda(cudaMalloc(&output_d, out_size));
ftime();
ftime();
stime("Computation");
integrate<<<grid, block>>>(output_d, imTex, dt, steps);
ftime();
// Copying from device to host
stime("Copy to host");
checkCuda(cudaMallocHost(&output, out_size));
checkCuda(cudaMemcpy(output, output_d, out_size, cudaMemcpyDeviceToHost));
ftime();
stime("Free device memory");
checkCuda(cudaFree(output_d));
checkCuda(cudaDestroyTextureObject(imTex));
checkCuda(cudaFreeArray(im_d));
ftime();
//stime("Write");
//writeCSV(argv[2], output, num_particles, steps);
//ftime();
stime("Free host memory");
checkCuda(cudaFreeHost(im));
checkCuda(cudaFreeHost(output));
ftime();
ftime();
ptime("GPU");
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
#include <errno.h>
#include <vector>
#include <time.h>
#include <sys/time.h>
using std::cout;
using std::cerr;
using std::endl;
using std::cin;
using std::vector;
constexpr size_t IM_X = 1300;
constexpr size_t IM_Y = 600;
constexpr size_t IM_V = sizeof(float2);
constexpr size_t IM_SIZE = IM_X * IM_Y * IM_V;
constexpr size_t XSR = 10;
constexpr size_t YSR = 5;
__device__
inline float2 mul(float s, float2 v) {
v.x *= s;
v.y *= s;
return v;
}
__device__
inline float2 add(float2 v1, float2 v2) {
v1.x += v2.x;
v1.y += v2.y;
return v1;
}
__global__
void integrate(float2* out, hipTextureObject_t vecs, float dt, size_t steps) {
float2 k1, k2, k3, k4, p, q;
// Initial position
p.x = blockIdx.x * blockDim.x + threadIdx.x;
p.y = blockIdx.y * blockDim.y + threadIdx.y;
// Output location
size_t idx = (blockDim.x * gridDim.x * (int)p.y + (int)p.x) * steps;
// Apply sample rate
p.x *= XSR;
p.y *= YSR;
// Initial output
out[idx++] = p;
// Integrate forward
for (size_t i = 1; i < steps; i++) {
k1 = mul(dt, tex2D<float2>(vecs, p.x, p.y));
q = add(p, mul(0.5, k1));
k2 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, mul(0.5, k2));
k3 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, k3);
k4 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
p.x += (1.0/6.0)*(k1.x + 2*k2.x + 2*k3.x + k4.x);
p.y += (1.0/6.0)*(k1.y + 2*k2.y + 2*k3.y + k4.y);
out[idx++] = p;
}
}
__host__
hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
cerr << "CUDA Runtime Error: " << hipGetErrorString(result) << endl;
abort();
}
return result;
}
__host__
int checkLinux(int result) {
if (result == -1) {
cerr << "Linux Runtime Error: (" << errno << ") " << strerror(errno) << endl;
abort();
}
return result;
}
__host__
void writeCSV(char* file, float2* output, size_t num_particles, size_t steps) {
const size_t file_size = num_particles * steps * (20 + 9 + 9 + 3);
umask(0111);
int fd = checkLinux(open(file, O_RDWR | O_CREAT | O_TRUNC, 06666));
checkLinux(ftruncate(fd, file_size));
char* map = (char*) mmap(NULL, file_size, PROT_WRITE, MAP_SHARED, fd, 0);
checkLinux((int)(size_t)map);
char* cur = map;
const char* header = "line_id, coordinate_x, coordinate_y\n";
checkLinux(write(fd, header, strlen(header)));
for (size_t i = 0; i < num_particles; i++)
for (size_t s = 0; s < steps; s++) {
float2 p = output[i * steps + s];
cur += sprintf(cur, "%llu,%.7f,%.7f\n", i, p.x, p.y);
}
msync(map, file_size, MS_SYNC);
munmap(map, file_size);
checkLinux(ftruncate(fd, cur - map));
checkLinux(close(fd));
}
vector<const char*> names;
vector<timespec> wall;
vector<timespec> proc;
vector<size_t> levels;
size_t cur_level = 0;
__host__
static inline void stime(const char* name) {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
names.push_back(name);
levels.push_back(cur_level++);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
__host__
static inline void ftime() {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
levels.push_back(--cur_level);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
// from https://gist.github.com/diabloneo/9619917
__host__
static inline void timespecDiff(timespec& a, timespec& b, timespec& result) {
result.tv_sec = a.tv_sec - b.tv_sec;
result.tv_nsec = a.tv_nsec - b.tv_nsec;
if (result.tv_nsec < 0) {
--result.tv_sec;
result.tv_nsec += 1000000000L;
}
}
__host__
static inline double timespecToMs(const timespec& t) {
return (double)t.tv_sec * 1000.0 + (double)t.tv_nsec / 1000000.0;
}
__host__
static size_t ptime(const char* name, size_t n = 0, size_t i = 0, size_t l = 0) {
while (n < names.size() and levels[i] == l) {
size_t j = i + 1;
auto& sw = wall[i];
auto& sp = proc[i];
int jumped = j;
while (l < levels[j]) j++;
auto& fw = wall[j];
auto& fp = proc[j];
timespec w, p;
timespecDiff(fw, sw, w);
timespecDiff(fp, sp, p);
for (size_t k = 0; k < l; k++)
printf("\t");
printf("\"%s\", \"%s\", %.3f, %.3f\n",
name,
names[n++],
timespecToMs(w),
timespecToMs(p));
if (jumped < j)
n = ptime(name, n, jumped, l + 1);
i = j + 1;
}
return n;
}
__host__
int main(int argc, char **argv) {
stime("Program");
stime("Setup");
if (argc != 3) {
ftime();
ftime();
printf("Usage: ./main image output\n");
return 0;
}
float dt = 1;
//cout << "Enter delta time: ";
//cin >> dt;
size_t steps = 100;
//cout << "Enter number of steps: ";
//cin >> steps;
// Opening file
stime("Read input");
int fd = checkLinux(open(argv[1], O_RDONLY));
// Allocating + Mapping host memory
float2 *im;
hipArray* im_d;
float2 *output_d;
float2 *output;
// Memory mapping does not provide a performance boost.
// It trades off between copy time to GPU or copy to RAM.
checkCuda(hipHostMalloc(&im, IM_SIZE, hipHostMallocDefault));
checkLinux(read(fd, im, IM_SIZE));
close(fd);
ftime();
// Modified basic cuda texture manipulation obtained from
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
// Allocate CUDA array in device memory
stime("Copy to GPU");
hipChannelFormatDesc channelDesc = hipCreateChannelDesc(32, 32, 0, 0,
hipChannelFormatKindFloat);
checkCuda(hipMallocArray(&im_d, &channelDesc, IM_X, IM_Y));
checkCuda(hipMemcpyToArray(im_d, 0, 0, im, IM_SIZE, hipMemcpyHostToDevice));
ftime();
// Specify texture
stime("Initialize Texture");
struct hipResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = hipResourceTypeArray;
resDesc.res.array.array = im_d;
// Specify texture object parameters
struct hipTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.addressMode[0] = hipAddressModeBorder;
texDesc.addressMode[1] = hipAddressModeBorder;
texDesc.filterMode = hipFilterModeLinear;
texDesc.readMode = hipReadModeElementType;
texDesc.maxAnisotropy = 2;
texDesc.normalizedCoords = false;
// Create texture object
hipTextureObject_t imTex = 0;
checkCuda(hipCreateTextureObject(&imTex, &resDesc, &texDesc, NULL));
ftime();
dim3 block(26, 24, 1);
dim3 grid(5, 5, 1);
// dim3 block(1, 24, 1);
// dim3 grid(1, 25, 1);
const size_t num_particles = block.x * grid.x * block.y * grid.y;
const size_t out_size = num_particles * sizeof(float2) * steps;
stime("Allocate Output");
checkCuda(hipMalloc(&output_d, out_size));
ftime();
ftime();
stime("Computation");
integrate<<<grid, block>>>(output_d, imTex, dt, steps);
ftime();
// Copying from device to host
stime("Copy to host");
checkCuda(hipHostMalloc(&output, out_size, hipHostMallocDefault));
checkCuda(hipMemcpy(output, output_d, out_size, hipMemcpyDeviceToHost));
ftime();
stime("Free device memory");
checkCuda(hipFree(output_d));
checkCuda(hipDestroyTextureObject(imTex));
checkCuda(hipFreeArray(im_d));
ftime();
//stime("Write");
//writeCSV(argv[2], output, num_particles, steps);
//ftime();
stime("Free host memory");
checkCuda(hipHostFree(im));
checkCuda(hipHostFree(output));
ftime();
ftime();
ptime("GPU");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
#include <errno.h>
#include <vector>
#include <time.h>
#include <sys/time.h>
using std::cout;
using std::cerr;
using std::endl;
using std::cin;
using std::vector;
constexpr size_t IM_X = 1300;
constexpr size_t IM_Y = 600;
constexpr size_t IM_V = sizeof(float2);
constexpr size_t IM_SIZE = IM_X * IM_Y * IM_V;
constexpr size_t XSR = 10;
constexpr size_t YSR = 5;
__device__
inline float2 mul(float s, float2 v) {
v.x *= s;
v.y *= s;
return v;
}
__device__
inline float2 add(float2 v1, float2 v2) {
v1.x += v2.x;
v1.y += v2.y;
return v1;
}
__global__
void integrate(float2* out, hipTextureObject_t vecs, float dt, size_t steps) {
float2 k1, k2, k3, k4, p, q;
// Initial position
p.x = blockIdx.x * blockDim.x + threadIdx.x;
p.y = blockIdx.y * blockDim.y + threadIdx.y;
// Output location
size_t idx = (blockDim.x * gridDim.x * (int)p.y + (int)p.x) * steps;
// Apply sample rate
p.x *= XSR;
p.y *= YSR;
// Initial output
out[idx++] = p;
// Integrate forward
for (size_t i = 1; i < steps; i++) {
k1 = mul(dt, tex2D<float2>(vecs, p.x, p.y));
q = add(p, mul(0.5, k1));
k2 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, mul(0.5, k2));
k3 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, k3);
k4 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
p.x += (1.0/6.0)*(k1.x + 2*k2.x + 2*k3.x + k4.x);
p.y += (1.0/6.0)*(k1.y + 2*k2.y + 2*k3.y + k4.y);
out[idx++] = p;
}
}
__host__
hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
cerr << "CUDA Runtime Error: " << hipGetErrorString(result) << endl;
abort();
}
return result;
}
__host__
int checkLinux(int result) {
if (result == -1) {
cerr << "Linux Runtime Error: (" << errno << ") " << strerror(errno) << endl;
abort();
}
return result;
}
__host__
void writeCSV(char* file, float2* output, size_t num_particles, size_t steps) {
const size_t file_size = num_particles * steps * (20 + 9 + 9 + 3);
umask(0111);
int fd = checkLinux(open(file, O_RDWR | O_CREAT | O_TRUNC, 06666));
checkLinux(ftruncate(fd, file_size));
char* map = (char*) mmap(NULL, file_size, PROT_WRITE, MAP_SHARED, fd, 0);
checkLinux((int)(size_t)map);
char* cur = map;
const char* header = "line_id, coordinate_x, coordinate_y\n";
checkLinux(write(fd, header, strlen(header)));
for (size_t i = 0; i < num_particles; i++)
for (size_t s = 0; s < steps; s++) {
float2 p = output[i * steps + s];
cur += sprintf(cur, "%llu,%.7f,%.7f\n", i, p.x, p.y);
}
msync(map, file_size, MS_SYNC);
munmap(map, file_size);
checkLinux(ftruncate(fd, cur - map));
checkLinux(close(fd));
}
vector<const char*> names;
vector<timespec> wall;
vector<timespec> proc;
vector<size_t> levels;
size_t cur_level = 0;
__host__
static inline void stime(const char* name) {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
names.push_back(name);
levels.push_back(cur_level++);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
__host__
static inline void ftime() {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
levels.push_back(--cur_level);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
// from https://gist.github.com/diabloneo/9619917
__host__
static inline void timespecDiff(timespec& a, timespec& b, timespec& result) {
result.tv_sec = a.tv_sec - b.tv_sec;
result.tv_nsec = a.tv_nsec - b.tv_nsec;
if (result.tv_nsec < 0) {
--result.tv_sec;
result.tv_nsec += 1000000000L;
}
}
__host__
static inline double timespecToMs(const timespec& t) {
return (double)t.tv_sec * 1000.0 + (double)t.tv_nsec / 1000000.0;
}
__host__
static size_t ptime(const char* name, size_t n = 0, size_t i = 0, size_t l = 0) {
while (n < names.size() and levels[i] == l) {
size_t j = i + 1;
auto& sw = wall[i];
auto& sp = proc[i];
int jumped = j;
while (l < levels[j]) j++;
auto& fw = wall[j];
auto& fp = proc[j];
timespec w, p;
timespecDiff(fw, sw, w);
timespecDiff(fp, sp, p);
for (size_t k = 0; k < l; k++)
printf("\t");
printf("\"%s\", \"%s\", %.3f, %.3f\n",
name,
names[n++],
timespecToMs(w),
timespecToMs(p));
if (jumped < j)
n = ptime(name, n, jumped, l + 1);
i = j + 1;
}
return n;
}
__host__
int main(int argc, char **argv) {
stime("Program");
stime("Setup");
if (argc != 3) {
ftime();
ftime();
printf("Usage: ./main image output\n");
return 0;
}
float dt = 1;
//cout << "Enter delta time: ";
//cin >> dt;
size_t steps = 100;
//cout << "Enter number of steps: ";
//cin >> steps;
// Opening file
stime("Read input");
int fd = checkLinux(open(argv[1], O_RDONLY));
// Allocating + Mapping host memory
float2 *im;
hipArray* im_d;
float2 *output_d;
float2 *output;
// Memory mapping does not provide a performance boost.
// It trades off between copy time to GPU or copy to RAM.
checkCuda(hipHostMalloc(&im, IM_SIZE, hipHostMallocDefault));
checkLinux(read(fd, im, IM_SIZE));
close(fd);
ftime();
// Modified basic cuda texture manipulation obtained from
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
// Allocate CUDA array in device memory
stime("Copy to GPU");
hipChannelFormatDesc channelDesc = hipCreateChannelDesc(32, 32, 0, 0,
hipChannelFormatKindFloat);
checkCuda(hipMallocArray(&im_d, &channelDesc, IM_X, IM_Y));
checkCuda(hipMemcpyToArray(im_d, 0, 0, im, IM_SIZE, hipMemcpyHostToDevice));
ftime();
// Specify texture
stime("Initialize Texture");
struct hipResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = hipResourceTypeArray;
resDesc.res.array.array = im_d;
// Specify texture object parameters
struct hipTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.addressMode[0] = hipAddressModeBorder;
texDesc.addressMode[1] = hipAddressModeBorder;
texDesc.filterMode = hipFilterModeLinear;
texDesc.readMode = hipReadModeElementType;
texDesc.maxAnisotropy = 2;
texDesc.normalizedCoords = false;
// Create texture object
hipTextureObject_t imTex = 0;
checkCuda(hipCreateTextureObject(&imTex, &resDesc, &texDesc, NULL));
ftime();
dim3 block(26, 24, 1);
dim3 grid(5, 5, 1);
// dim3 block(1, 24, 1);
// dim3 grid(1, 25, 1);
const size_t num_particles = block.x * grid.x * block.y * grid.y;
const size_t out_size = num_particles * sizeof(float2) * steps;
stime("Allocate Output");
checkCuda(hipMalloc(&output_d, out_size));
ftime();
ftime();
stime("Computation");
integrate<<<grid, block>>>(output_d, imTex, dt, steps);
ftime();
// Copying from device to host
stime("Copy to host");
checkCuda(hipHostMalloc(&output, out_size, hipHostMallocDefault));
checkCuda(hipMemcpy(output, output_d, out_size, hipMemcpyDeviceToHost));
ftime();
stime("Free device memory");
checkCuda(hipFree(output_d));
checkCuda(hipDestroyTextureObject(imTex));
checkCuda(hipFreeArray(im_d));
ftime();
//stime("Write");
//writeCSV(argv[2], output, num_particles, steps);
//ftime();
stime("Free host memory");
checkCuda(hipHostFree(im));
checkCuda(hipHostFree(output));
ftime();
ftime();
ptime("GPU");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.globl _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.p2align 8
.type _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm,@function
_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[16:17], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s4, s4, s5
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s5, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v5, v2
v_cvt_f32_u32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v1, v5
v_cvt_i32_f32_e32 v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s4, v1, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e64 s4, s[2:3], 2
v_mad_u64_u32 v[0:1], null, v2, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_mul_f32_e32 v0, 0x41200000, v6
v_mul_f32_e32 v1, 0x40a00000, v5
v_add_co_u32 v3, vcc_lo, s16, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
s_and_b32 vcc_lo, exec_lo, s4
global_store_b64 v[3:4], v[0:1], off
s_cbranch_vccnz .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s1, s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, s2, v2, 0
s_waitcnt lgkmcnt(0)
s_clause 0x3
s_load_b32 s0, s[4:5], 0x38
s_load_b32 s6, s[4:5], 0x30
s_load_b32 s7, s[4:5], 0x8
s_load_b32 s18, s[4:5], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, s3, v2, v[4:5]
s_load_b128 s[12:15], s[4:5], 0x30
v_mov_b32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[3:4]
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
v_cvt_f32_u32_e32 v6, s18
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s6, 15
s_cselect_b32 s0, -1, 0
s_bfe_u32 s6, s7, 0xe000e
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_i32 s19, s6, 1
s_load_b256 s[4:11], s[4:5], 0x0
v_cvt_f32_u32_e32 v5, s19
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
v_cndmask_b32_e64 v4, 1.0, v5, s0
v_cndmask_b32_e64 v5, 1.0, v6, s0
v_add_co_u32 v2, s0, v2, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v3, s0, s17, v3, s0
v_rcp_f32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v5
v_add_co_u32 v2, s0, v2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_mov_b32 s17, 0x3fc55555
s_mov_b32 s16, 0x55555555
.LBB0_2:
v_dual_mul_f32 v8, v1, v4 :: v_dual_mul_f32 v9, v0, v5
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u64 s[2:3], 0
v_floor_f32_e32 v8, v8
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v6, v8
v_dual_mul_f32 v10, v7, v9 :: v_dual_cndmask_b32 v9, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v0, v10, vcc_lo
s_waitcnt lgkmcnt(0)
image_sample_lz v[8:9], v[8:9], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_dual_mul_f32 v14, s1, v9 :: v_dual_mul_f32 v15, s1, v8
v_fma_f32 v8, 0.5, v14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, 0.5, v15, v0
v_mul_f32_e32 v11, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v11, v11
v_mul_f32_e32 v11, v7, v11
v_mul_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v9, v9
v_mul_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v8, v9 :: v_dual_cndmask_b32 v8, v10, v11
image_sample_lz v[8:9], v[8:9], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_dual_mul_f32 v16, s1, v9 :: v_dual_mul_f32 v17, s1, v8
v_fma_f32 v8, 0.5, v16, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v10, 0.5, v17, v0
v_dual_fmac_f32 v14, 2.0, v16 :: v_dual_fmac_f32 v15, 2.0, v17
v_mul_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v10, v5
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v11, v11
v_mul_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v7, v11
v_dual_cndmask_b32 v9, v8, v9 :: v_dual_cndmask_b32 v8, v10, v11
image_sample_lz v[8:9], v[8:9], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_fma_f32 v10, s1, v9, v1
v_fma_f32 v12, s1, v8, v0
v_dual_mul_f32 v9, s1, v9 :: v_dual_mul_f32 v8, s1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v10, v4
v_mul_f32_e32 v13, v12, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v14, 2.0, v9 :: v_dual_fmac_f32 v15, 2.0, v8
v_floor_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v13, v13
v_mul_f32_e32 v11, v6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, v7, v13
v_dual_cndmask_b32 v11, v10, v11 :: v_dual_cndmask_b32 v10, v12, v13
v_cvt_f64_f32_e32 v[12:13], v0
v_cvt_f64_f32_e32 v[0:1], v1
image_sample_lz v[10:11], v[10:11], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v15, s1, v10 :: v_dual_fmac_f32 v14, s1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[8:9], v15
v_cvt_f64_f32_e32 v[10:11], v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], s[16:17], v[12:13]
v_fma_f64 v[10:11], v[10:11], s[16:17], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v0, v[8:9]
v_cvt_f32_f64_e32 v1, v[10:11]
global_store_b64 v[2:3], v[0:1], off
v_add_co_u32 v2, s0, v2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, .Lfunc_end0-_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <assert.h>
#include <fcntl.h>
#include <errno.h>
#include <vector>
#include <time.h>
#include <sys/time.h>
using std::cout;
using std::cerr;
using std::endl;
using std::cin;
using std::vector;
constexpr size_t IM_X = 1300;
constexpr size_t IM_Y = 600;
constexpr size_t IM_V = sizeof(float2);
constexpr size_t IM_SIZE = IM_X * IM_Y * IM_V;
constexpr size_t XSR = 10;
constexpr size_t YSR = 5;
__device__
inline float2 mul(float s, float2 v) {
v.x *= s;
v.y *= s;
return v;
}
__device__
inline float2 add(float2 v1, float2 v2) {
v1.x += v2.x;
v1.y += v2.y;
return v1;
}
__global__
void integrate(float2* out, hipTextureObject_t vecs, float dt, size_t steps) {
float2 k1, k2, k3, k4, p, q;
// Initial position
p.x = blockIdx.x * blockDim.x + threadIdx.x;
p.y = blockIdx.y * blockDim.y + threadIdx.y;
// Output location
size_t idx = (blockDim.x * gridDim.x * (int)p.y + (int)p.x) * steps;
// Apply sample rate
p.x *= XSR;
p.y *= YSR;
// Initial output
out[idx++] = p;
// Integrate forward
for (size_t i = 1; i < steps; i++) {
k1 = mul(dt, tex2D<float2>(vecs, p.x, p.y));
q = add(p, mul(0.5, k1));
k2 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, mul(0.5, k2));
k3 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
q = add(p, k3);
k4 = mul(dt, tex2D<float2>(vecs, q.x, q.y));
p.x += (1.0/6.0)*(k1.x + 2*k2.x + 2*k3.x + k4.x);
p.y += (1.0/6.0)*(k1.y + 2*k2.y + 2*k3.y + k4.y);
out[idx++] = p;
}
}
__host__
hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
cerr << "CUDA Runtime Error: " << hipGetErrorString(result) << endl;
abort();
}
return result;
}
__host__
int checkLinux(int result) {
if (result == -1) {
cerr << "Linux Runtime Error: (" << errno << ") " << strerror(errno) << endl;
abort();
}
return result;
}
__host__
void writeCSV(char* file, float2* output, size_t num_particles, size_t steps) {
const size_t file_size = num_particles * steps * (20 + 9 + 9 + 3);
umask(0111);
int fd = checkLinux(open(file, O_RDWR | O_CREAT | O_TRUNC, 06666));
checkLinux(ftruncate(fd, file_size));
char* map = (char*) mmap(NULL, file_size, PROT_WRITE, MAP_SHARED, fd, 0);
checkLinux((int)(size_t)map);
char* cur = map;
const char* header = "line_id, coordinate_x, coordinate_y\n";
checkLinux(write(fd, header, strlen(header)));
for (size_t i = 0; i < num_particles; i++)
for (size_t s = 0; s < steps; s++) {
float2 p = output[i * steps + s];
cur += sprintf(cur, "%llu,%.7f,%.7f\n", i, p.x, p.y);
}
msync(map, file_size, MS_SYNC);
munmap(map, file_size);
checkLinux(ftruncate(fd, cur - map));
checkLinux(close(fd));
}
vector<const char*> names;
vector<timespec> wall;
vector<timespec> proc;
vector<size_t> levels;
size_t cur_level = 0;
__host__
static inline void stime(const char* name) {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
names.push_back(name);
levels.push_back(cur_level++);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
__host__
static inline void ftime() {
timespec cur_wall, cur_proc;
clock_gettime(CLOCK_REALTIME, &cur_wall);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &cur_proc);
levels.push_back(--cur_level);
wall.push_back(cur_wall);
proc.push_back(cur_proc);
}
// from https://gist.github.com/diabloneo/9619917
__host__
static inline void timespecDiff(timespec& a, timespec& b, timespec& result) {
result.tv_sec = a.tv_sec - b.tv_sec;
result.tv_nsec = a.tv_nsec - b.tv_nsec;
if (result.tv_nsec < 0) {
--result.tv_sec;
result.tv_nsec += 1000000000L;
}
}
__host__
static inline double timespecToMs(const timespec& t) {
return (double)t.tv_sec * 1000.0 + (double)t.tv_nsec / 1000000.0;
}
__host__
static size_t ptime(const char* name, size_t n = 0, size_t i = 0, size_t l = 0) {
while (n < names.size() and levels[i] == l) {
size_t j = i + 1;
auto& sw = wall[i];
auto& sp = proc[i];
int jumped = j;
while (l < levels[j]) j++;
auto& fw = wall[j];
auto& fp = proc[j];
timespec w, p;
timespecDiff(fw, sw, w);
timespecDiff(fp, sp, p);
for (size_t k = 0; k < l; k++)
printf("\t");
printf("\"%s\", \"%s\", %.3f, %.3f\n",
name,
names[n++],
timespecToMs(w),
timespecToMs(p));
if (jumped < j)
n = ptime(name, n, jumped, l + 1);
i = j + 1;
}
return n;
}
__host__
int main(int argc, char **argv) {
stime("Program");
stime("Setup");
if (argc != 3) {
ftime();
ftime();
printf("Usage: ./main image output\n");
return 0;
}
float dt = 1;
//cout << "Enter delta time: ";
//cin >> dt;
size_t steps = 100;
//cout << "Enter number of steps: ";
//cin >> steps;
// Opening file
stime("Read input");
int fd = checkLinux(open(argv[1], O_RDONLY));
// Allocating + Mapping host memory
float2 *im;
hipArray* im_d;
float2 *output_d;
float2 *output;
// Memory mapping does not provide a performance boost.
// It trades off between copy time to GPU or copy to RAM.
checkCuda(hipHostMalloc(&im, IM_SIZE, hipHostMallocDefault));
checkLinux(read(fd, im, IM_SIZE));
close(fd);
ftime();
// Modified basic cuda texture manipulation obtained from
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
// Allocate CUDA array in device memory
stime("Copy to GPU");
hipChannelFormatDesc channelDesc = hipCreateChannelDesc(32, 32, 0, 0,
hipChannelFormatKindFloat);
checkCuda(hipMallocArray(&im_d, &channelDesc, IM_X, IM_Y));
checkCuda(hipMemcpyToArray(im_d, 0, 0, im, IM_SIZE, hipMemcpyHostToDevice));
ftime();
// Specify texture
stime("Initialize Texture");
struct hipResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = hipResourceTypeArray;
resDesc.res.array.array = im_d;
// Specify texture object parameters
struct hipTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.addressMode[0] = hipAddressModeBorder;
texDesc.addressMode[1] = hipAddressModeBorder;
texDesc.filterMode = hipFilterModeLinear;
texDesc.readMode = hipReadModeElementType;
texDesc.maxAnisotropy = 2;
texDesc.normalizedCoords = false;
// Create texture object
hipTextureObject_t imTex = 0;
checkCuda(hipCreateTextureObject(&imTex, &resDesc, &texDesc, NULL));
ftime();
dim3 block(26, 24, 1);
dim3 grid(5, 5, 1);
// dim3 block(1, 24, 1);
// dim3 grid(1, 25, 1);
const size_t num_particles = block.x * grid.x * block.y * grid.y;
const size_t out_size = num_particles * sizeof(float2) * steps;
stime("Allocate Output");
checkCuda(hipMalloc(&output_d, out_size));
ftime();
ftime();
stime("Computation");
integrate<<<grid, block>>>(output_d, imTex, dt, steps);
ftime();
// Copying from device to host
stime("Copy to host");
checkCuda(hipHostMalloc(&output, out_size, hipHostMallocDefault));
checkCuda(hipMemcpy(output, output_d, out_size, hipMemcpyDeviceToHost));
ftime();
stime("Free device memory");
checkCuda(hipFree(output_d));
checkCuda(hipDestroyTextureObject(imTex));
checkCuda(hipFreeArray(im_d));
ftime();
//stime("Write");
//writeCSV(argv[2], output, num_particles, steps);
//ftime();
stime("Free host memory");
checkCuda(hipHostFree(im));
checkCuda(hipHostFree(output));
ftime();
ftime();
ptime("GPU");
return 0;
} | .text
.file "gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm # -- Begin function _Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.p2align 4, 0x90
.type _Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm,@function
_Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm: # @_Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, .Lfunc_end0-_Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.cfi_endproc
# -- End function
.globl _Z9checkCuda10hipError_t # -- Begin function _Z9checkCuda10hipError_t
.p2align 4, 0x90
.type _Z9checkCuda10hipError_t,@function
_Z9checkCuda10hipError_t: # @_Z9checkCuda10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
xorl %eax, %eax
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
callq abort
.Lfunc_end1:
.size _Z9checkCuda10hipError_t, .Lfunc_end1-_Z9checkCuda10hipError_t
.cfi_endproc
# -- End function
.globl _Z10checkLinuxi # -- Begin function _Z10checkLinuxi
.p2align 4, 0x90
.type _Z10checkLinuxi,@function
_Z10checkLinuxi: # @_Z10checkLinuxi
.cfi_startproc
# %bb.0:
cmpl $-1, %edi
je .LBB2_2
# %bb.1:
movl %edi, %eax
retq
.LBB2_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
callq __errno_location
movq %rax, %r14
movl (%rax), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
movl (%r14), %edi
callq strerror
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
callq abort
.Lfunc_end2:
.size _Z10checkLinuxi, .Lfunc_end2-_Z10checkLinuxi
.cfi_endproc
# -- End function
.globl _Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm # -- Begin function _Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm
.p2align 4, 0x90
.type _Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm,@function
_Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm: # @_Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rdx, %rax
imulq %rcx, %rax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,8), %r14
movl $73, %edi
callq umask
movq %rbx, %rdi
movl $578, %esi # imm = 0x242
movl $3510, %edx # imm = 0xDB6
xorl %eax, %eax
callq open
movl %eax, %ebx
movl %eax, %edi
callq _Z10checkLinuxi
movl %ebx, %edi
movq %r14, %rsi
callq ftruncate
movl %eax, %edi
callq _Z10checkLinuxi
xorl %edi, %edi
movq %r14, 16(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $2, %edx
movl $1, %ecx
movl %ebx, %r8d
xorl %r9d, %r9d
callq mmap
movq %rax, %rbp
movl %ebp, %edi
callq _Z10checkLinuxi
movl $.L.str.3, %esi
movl $36, %edx
movl %ebx, 4(%rsp) # 4-byte Spill
movl %ebx, %edi
callq write
movl %eax, %edi
callq _Z10checkLinuxi
movq %rbp, 8(%rsp) # 8-byte Spill
movq %r12, 32(%rsp) # 8-byte Spill
testq %r12, %r12
je .LBB3_5
# %bb.1: # %.preheader.lr.ph
addq $4, %r13
leaq (,%r15,8), %rax
movq %rax, 24(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movq 8(%rsp), %rbx # 8-byte Reload
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_2 Depth=1
movq %rbx, %rbp
.LBB3_4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r14
addq 24(%rsp), %r13 # 8-byte Folded Reload
movq %rbp, %rbx
cmpq 32(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_5
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
testq %r15, %r15
je .LBB3_3
# %bb.6: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%r13,%r12,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13,%r12,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %esi
movq %rbx, %rdi
movq %r14, %rdx
movb $2, %al
callq sprintf
movslq %eax, %rbp
addq %rbx, %rbp
incq %r12
movq %rbp, %rbx
cmpq %r12, %r15
jne .LBB3_7
jmp .LBB3_4
.LBB3_5: # %._crit_edge39
movq 8(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq 16(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $4, %edx
callq msync
movq %r14, %rdi
movq %rbx, %rsi
callq munmap
subq %r14, %rbp
movl 4(%rsp), %ebx # 4-byte Reload
movl %ebx, %edi
movq %rbp, %rsi
callq ftruncate
movl %eax, %edi
callq _Z10checkLinuxi
movl %ebx, %edi
callq close
movl %eax, %edi
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z10checkLinuxi # TAILCALL
.Lfunc_end3:
.size _Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm, .Lfunc_end3-_Z8writeCSVPcP15HIP_vector_typeIfLj2EEmm
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorIPKcSaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorIPKcSaIS1_EED2Ev,comdat
.weak _ZNSt6vectorIPKcSaIS1_EED2Ev # -- Begin function _ZNSt6vectorIPKcSaIS1_EED2Ev
.p2align 4, 0x90
.type _ZNSt6vectorIPKcSaIS1_EED2Ev,@function
_ZNSt6vectorIPKcSaIS1_EED2Ev: # @_ZNSt6vectorIPKcSaIS1_EED2Ev
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
testq %rdi, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt12_Vector_baseIPKcSaIS1_EED2Ev.exit
retq
.Lfunc_end4:
.size _ZNSt6vectorIPKcSaIS1_EED2Ev, .Lfunc_end4-_ZNSt6vectorIPKcSaIS1_EED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorI8timespecSaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorI8timespecSaIS0_EED2Ev,comdat
.weak _ZNSt6vectorI8timespecSaIS0_EED2Ev # -- Begin function _ZNSt6vectorI8timespecSaIS0_EED2Ev
.p2align 4, 0x90
.type _ZNSt6vectorI8timespecSaIS0_EED2Ev,@function
_ZNSt6vectorI8timespecSaIS0_EED2Ev: # @_ZNSt6vectorI8timespecSaIS0_EED2Ev
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
testq %rdi, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt12_Vector_baseI8timespecSaIS0_EED2Ev.exit
retq
.Lfunc_end5:
.size _ZNSt6vectorI8timespecSaIS0_EED2Ev, .Lfunc_end5-_ZNSt6vectorI8timespecSaIS0_EED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorImSaImEED2Ev,"axG",@progbits,_ZNSt6vectorImSaImEED2Ev,comdat
.weak _ZNSt6vectorImSaImEED2Ev # -- Begin function _ZNSt6vectorImSaImEED2Ev
.p2align 4, 0x90
.type _ZNSt6vectorImSaImEED2Ev,@function
_ZNSt6vectorImSaImEED2Ev: # @_ZNSt6vectorImSaImEED2Ev
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
testq %rdi, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt12_Vector_baseImSaImEED2Ev.exit
retq
.Lfunc_end6:
.size _ZNSt6vectorImSaImEED2Ev, .Lfunc_end6-_ZNSt6vectorImSaImEED2Ev
.cfi_endproc
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.L.str.8, %edi
callq _ZL5stimePKc
movl $.L.str.9, %edi
callq _ZL5stimePKc
cmpl $3, %ebp
jne .LBB7_1
# %bb.2:
movl $.L.str.11, %edi
callq _ZL5stimePKc
movq 8(%rbx), %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
movl %eax, %ebx
movl %eax, %edi
callq _Z10checkLinuxi
leaq 32(%rsp), %rdi
movl $6240000, %esi # imm = 0x5F3700
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB7_18
# %bb.3: # %_Z9checkCuda10hipError_t.exit
movq 32(%rsp), %rsi
movl $6240000, %edx # imm = 0x5F3700
movl %ebx, %edi
callq read
movl %eax, %edi
callq _Z10checkLinuxi
movl %ebx, %edi
callq close
callq _ZL5ftimev
movl $.L.str.12, %edi
callq _ZL5stimePKc
leaq 300(%rsp), %rbx
movq %rbx, %rdi
movl $32, %esi
movl $32, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
leaq 24(%rsp), %rdi
movl $1300, %edx # imm = 0x514
movl $600, %ecx # imm = 0x258
movq %rbx, %rsi
xorl %r8d, %r8d
callq hipMallocArray
testl %eax, %eax
jne .LBB7_18
# %bb.4: # %_Z9checkCuda10hipError_t.exit19
movq 24(%rsp), %rdi
movq 32(%rsp), %rcx
movl $6240000, %r8d # imm = 0x5F3700
xorl %esi, %esi
xorl %edx, %edx
movl $1, %r9d
callq hipMemcpyToArray
testl %eax, %eax
jne .LBB7_18
# %bb.5: # %_Z9checkCuda10hipError_t.exit21
callq _ZL5ftimev
movl $.L.str.13, %edi
callq _ZL5stimePKc
xorps %xmm0, %xmm0
movaps %xmm0, 224(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movq 24(%rsp), %rax
movq %rax, 232(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 208(%rsp)
movabsq $12884901891, %rax # imm = 0x300000003
movq %rax, 160(%rsp)
movl $1, 172(%rsp)
movl $0, 176(%rsp)
movabsq $8589934592, %rax # imm = 0x200000000
movq %rax, 200(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
leaq 160(%rsp), %rdx
xorl %ecx, %ecx
callq hipCreateTextureObject
testl %eax, %eax
jne .LBB7_18
# %bb.6: # %_Z9checkCuda10hipError_t.exit23
callq _ZL5ftimev
movl $.L.str.14, %edi
callq _ZL5stimePKc
leaq 16(%rsp), %rdi
movl $12480000, %esi # imm = 0xBE6E00
callq hipMalloc
testl %eax, %eax
jne .LBB7_18
# %bb.7: # %_Z9checkCuda10hipError_t.exit25
callq _ZL5ftimev
callq _ZL5ftimev
movl $.L.str.15, %edi
callq _ZL5stimePKc
movabsq $21474836485, %rdi # imm = 0x500000005
movabsq $103079215130, %rdx # imm = 0x180000001A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movl $1065353216, 44(%rsp) # imm = 0x3F800000
movq $100, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 48(%rsp)
leaq 144(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_9:
callq _ZL5ftimev
movl $.L.str.16, %edi
callq _ZL5stimePKc
leaq 48(%rsp), %rdi
movl $12480000, %esi # imm = 0xBE6E00
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB7_18
# %bb.10: # %_Z9checkCuda10hipError_t.exit27
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi
movl $12480000, %edx # imm = 0xBE6E00
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_18
# %bb.11: # %_Z9checkCuda10hipError_t.exit29
callq _ZL5ftimev
movl $.L.str.17, %edi
callq _ZL5stimePKc
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_18
# %bb.12: # %_Z9checkCuda10hipError_t.exit31
movq 8(%rsp), %rdi
callq hipDestroyTextureObject
testl %eax, %eax
jne .LBB7_18
# %bb.13: # %_Z9checkCuda10hipError_t.exit33
movq 24(%rsp), %rdi
callq hipFreeArray
testl %eax, %eax
jne .LBB7_18
# %bb.14: # %_Z9checkCuda10hipError_t.exit35
callq _ZL5ftimev
movl $.L.str.18, %edi
callq _ZL5stimePKc
movq 32(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB7_18
# %bb.15: # %_Z9checkCuda10hipError_t.exit37
movq 48(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB7_18
# %bb.16: # %_Z9checkCuda10hipError_t.exit39
callq _ZL5ftimev
callq _ZL5ftimev
xorl %edi, %edi
xorl %esi, %esi
xorl %edx, %edx
callq _ZL5ptimePKcmmm
jmp .LBB7_17
.LBB7_1:
callq _ZL5ftimev
callq _ZL5ftimev
movl $.Lstr, %edi
callq puts@PLT
.LBB7_17:
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_18:
.cfi_def_cfa_offset 352
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
callq abort
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL5stimePKc
.type _ZL5stimePKc,@function
_ZL5stimePKc: # @_ZL5stimePKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movabsq $9223372036854775792, %r13 # imm = 0x7FFFFFFFFFFFFFF0
leaq 24(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leaq 8(%rsp), %rsi
movl $2, %edi
callq clock_gettime
movq names+8(%rip), %r14
cmpq names+16(%rip), %r14
je .LBB8_2
# %bb.1:
movq %rbx, (%r14)
addq $8, names+8(%rip)
jmp .LBB8_11
.LBB8_2:
movq names(%rip), %r15
subq %r15, %r14
leaq 8(%r13), %rax
cmpq %rax, %r14
je .LBB8_45
# %bb.3: # %_ZNKSt6vectorIPKcSaIS1_EE12_M_check_lenEmS1_.exit.i.i
movq %r14, %r13
sarq $3, %r13
cmpq $1, %r13
movq %r13, %rax
adcq $0, %rax
leaq (%rax,%r13), %rbp
movabsq $1152921504606846975, %rcx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rcx, %rbp
cmovaeq %rcx, %rbp
addq %r13, %rax
cmovbq %rcx, %rbp
testq %rbp, %rbp
je .LBB8_4
# %bb.5:
leaq (,%rbp,8), %rdi
callq _Znwm
movq %rax, %r12
jmp .LBB8_6
.LBB8_4:
xorl %r12d, %r12d
.LBB8_6: # %_ZNSt12_Vector_baseIPKcSaIS1_EE11_M_allocateEm.exit.i.i
movq %rbx, (%r12,%r13,8)
testq %r14, %r14
jle .LBB8_8
# %bb.7:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB8_8: # %_ZNSt6vectorIPKcSaIS1_EE11_S_relocateEPS1_S4_S4_RS2_.exit.i.i
leaq (%r12,%r14), %rbx
addq $8, %rbx
testq %r15, %r15
movabsq $9223372036854775792, %r13 # imm = 0x7FFFFFFFFFFFFFF0
je .LBB8_10
# %bb.9:
movq %r15, %rdi
callq _ZdlPv
.LBB8_10: # %_ZNSt6vectorIPKcSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.exit.i
movq %r12, names(%rip)
movq %rbx, names+8(%rip)
leaq (%r12,%rbp,8), %rax
movq %rax, names+16(%rip)
.LBB8_11: # %_ZNSt6vectorIPKcSaIS1_EE9push_backERKS1_.exit
movq cur_level(%rip), %rbp
leaq 1(%rbp), %rax
movq %rax, cur_level(%rip)
movq levels+8(%rip), %rbx
cmpq levels+16(%rip), %rbx
je .LBB8_13
# %bb.12:
movq %rbp, (%rbx)
addq $8, %rbx
movq %rbx, levels+8(%rip)
jmp .LBB8_22
.LBB8_13:
movq levels(%rip), %r14
subq %r14, %rbx
leaq 8(%r13), %rax
cmpq %rax, %rbx
je .LBB8_45
# %bb.14: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
movq %rbx, %r13
sarq $3, %r13
cmpq $1, %r13
movq %r13, %rax
adcq $0, %rax
leaq (%rax,%r13), %r12
movabsq $1152921504606846975, %rcx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rcx, %r12
cmovaeq %rcx, %r12
addq %r13, %rax
cmovbq %rcx, %r12
testq %r12, %r12
je .LBB8_15
# %bb.16:
leaq (,%r12,8), %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB8_17
.LBB8_15:
xorl %r15d, %r15d
.LBB8_17: # %_ZNSt12_Vector_baseImSaImEE11_M_allocateEm.exit.i.i.i
movq %rbp, (%r15,%r13,8)
testq %rbx, %rbx
jle .LBB8_19
# %bb.18:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB8_19: # %_ZNSt6vectorImSaImEE11_S_relocateEPmS2_S2_RS0_.exit.i.i.i
addq %r15, %rbx
addq $8, %rbx
testq %r14, %r14
movabsq $9223372036854775792, %r13 # imm = 0x7FFFFFFFFFFFFFF0
je .LBB8_21
# %bb.20:
movq %r14, %rdi
callq _ZdlPv
.LBB8_21: # %_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_.exit.i.i
movq %r15, levels(%rip)
movq %rbx, levels+8(%rip)
leaq (%r15,%r12,8), %rax
movq %rax, levels+16(%rip)
.LBB8_22: # %_ZNSt6vectorImSaImEE9push_backEOm.exit
movq wall+8(%rip), %rbx
cmpq wall+16(%rip), %rbx
je .LBB8_24
# %bb.23:
movups 24(%rsp), %xmm0
movups %xmm0, (%rbx)
addq $16, wall+8(%rip)
jmp .LBB8_33
.LBB8_24:
movq wall(%rip), %r14
subq %r14, %rbx
cmpq %r13, %rbx
je .LBB8_45
# %bb.25: # %_ZNKSt6vectorI8timespecSaIS0_EE12_M_check_lenEmPKc.exit.i.i
movq %rbx, %rbp
sarq $4, %rbp
cmpq $1, %rbp
movq %rbp, %rax
adcq $0, %rax
leaq (%rax,%rbp), %r12
movabsq $576460752303423487, %rcx # imm = 0x7FFFFFFFFFFFFFF
cmpq %rcx, %r12
cmovaeq %rcx, %r12
addq %rbp, %rax
cmovbq %rcx, %r12
testq %r12, %r12
je .LBB8_26
# %bb.27:
movq %r12, %rdi
shlq $4, %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB8_28
.LBB8_26:
xorl %r15d, %r15d
.LBB8_28: # %_ZNSt12_Vector_baseI8timespecSaIS0_EE11_M_allocateEm.exit.i.i
shlq $4, %rbp
movups 24(%rsp), %xmm0
movups %xmm0, (%r15,%rbp)
testq %rbx, %rbx
jle .LBB8_30
# %bb.29:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB8_30: # %_ZNSt6vectorI8timespecSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit.i.i
addq %r15, %rbx
addq $16, %rbx
testq %r14, %r14
je .LBB8_32
# %bb.31:
movq %r14, %rdi
callq _ZdlPv
.LBB8_32: # %_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_.exit.i
movq %r15, wall(%rip)
movq %rbx, wall+8(%rip)
shlq $4, %r12
addq %r15, %r12
movq %r12, wall+16(%rip)
.LBB8_33: # %_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_.exit
movq proc+8(%rip), %rbx
cmpq proc+16(%rip), %rbx
je .LBB8_35
# %bb.34:
movups 8(%rsp), %xmm0
movups %xmm0, (%rbx)
addq $16, proc+8(%rip)
jmp .LBB8_44
.LBB8_35:
movq proc(%rip), %r14
subq %r14, %rbx
cmpq %r13, %rbx
je .LBB8_45
# %bb.36: # %_ZNKSt6vectorI8timespecSaIS0_EE12_M_check_lenEmPKc.exit.i.i6
movq %rbx, %r13
sarq $4, %r13
cmpq $1, %r13
movq %r13, %rax
adcq $0, %rax
leaq (%rax,%r13), %r12
movabsq $576460752303423487, %rcx # imm = 0x7FFFFFFFFFFFFFF
cmpq %rcx, %r12
cmovaeq %rcx, %r12
addq %r13, %rax
cmovbq %rcx, %r12
testq %r12, %r12
je .LBB8_37
# %bb.38:
movq %r12, %rdi
shlq $4, %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB8_39
.LBB8_37:
xorl %r15d, %r15d
.LBB8_39: # %_ZNSt12_Vector_baseI8timespecSaIS0_EE11_M_allocateEm.exit.i.i9
shlq $4, %r13
movups 8(%rsp), %xmm0
movups %xmm0, (%r15,%r13)
testq %rbx, %rbx
jle .LBB8_41
# %bb.40:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB8_41: # %_ZNSt6vectorI8timespecSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit.i.i10
addq %r15, %rbx
addq $16, %rbx
testq %r14, %r14
je .LBB8_43
# %bb.42:
movq %r14, %rdi
callq _ZdlPv
.LBB8_43: # %_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_.exit.i12
movq %r15, proc(%rip)
movq %rbx, proc+8(%rip)
shlq $4, %r12
addq %r15, %r12
movq %r12, proc+16(%rip)
.LBB8_44: # %_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_.exit13
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_45:
.cfi_def_cfa_offset 96
movl $.L.str.20, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end8:
.size _ZL5stimePKc, .Lfunc_end8-_ZL5stimePKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL5ftimev
.type _ZL5ftimev,@function
_ZL5ftimev: # @_ZL5ftimev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $9223372036854775792, %r12 # imm = 0x7FFFFFFFFFFFFFF0
leaq 24(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leaq 8(%rsp), %rsi
movl $2, %edi
callq clock_gettime
movq cur_level(%rip), %rbp
decq %rbp
movq %rbp, cur_level(%rip)
movq levels+8(%rip), %rbx
cmpq levels+16(%rip), %rbx
je .LBB9_2
# %bb.1:
movq %rbp, (%rbx)
addq $8, %rbx
movq %rbx, levels+8(%rip)
jmp .LBB9_11
.LBB9_2:
movq levels(%rip), %r14
subq %r14, %rbx
leaq 8(%r12), %rax
cmpq %rax, %rbx
je .LBB9_34
# %bb.3: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i
movq %rbx, %r12
sarq $3, %r12
cmpq $1, %r12
movq %r12, %rax
adcq $0, %rax
leaq (%rax,%r12), %r13
movabsq $1152921504606846975, %rcx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rcx, %r13
cmovaeq %rcx, %r13
addq %r12, %rax
cmovbq %rcx, %r13
testq %r13, %r13
je .LBB9_4
# %bb.5:
leaq (,%r13,8), %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB9_6
.LBB9_4:
xorl %r15d, %r15d
.LBB9_6: # %_ZNSt12_Vector_baseImSaImEE11_M_allocateEm.exit.i.i
movq %rbp, (%r15,%r12,8)
testq %rbx, %rbx
jle .LBB9_8
# %bb.7:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB9_8: # %_ZNSt6vectorImSaImEE11_S_relocateEPmS2_S2_RS0_.exit.i.i
addq %r15, %rbx
addq $8, %rbx
testq %r14, %r14
movabsq $9223372036854775792, %r12 # imm = 0x7FFFFFFFFFFFFFF0
je .LBB9_10
# %bb.9:
movq %r14, %rdi
callq _ZdlPv
.LBB9_10: # %_ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_.exit.i
movq %r15, levels(%rip)
movq %rbx, levels+8(%rip)
leaq (%r15,%r13,8), %rax
movq %rax, levels+16(%rip)
.LBB9_11: # %_ZNSt6vectorImSaImEE9push_backERKm.exit
movq wall+8(%rip), %rbx
cmpq wall+16(%rip), %rbx
je .LBB9_13
# %bb.12:
movups 24(%rsp), %xmm0
movups %xmm0, (%rbx)
addq $16, wall+8(%rip)
jmp .LBB9_22
.LBB9_13:
movq wall(%rip), %r14
subq %r14, %rbx
cmpq %r12, %rbx
je .LBB9_34
# %bb.14: # %_ZNKSt6vectorI8timespecSaIS0_EE12_M_check_lenEmPKc.exit.i.i
movq %rbx, %rbp
sarq $4, %rbp
cmpq $1, %rbp
movq %rbp, %rax
adcq $0, %rax
leaq (%rax,%rbp), %r13
movabsq $576460752303423487, %rcx # imm = 0x7FFFFFFFFFFFFFF
cmpq %rcx, %r13
cmovaeq %rcx, %r13
addq %rbp, %rax
cmovbq %rcx, %r13
testq %r13, %r13
je .LBB9_15
# %bb.16:
movq %r13, %rdi
shlq $4, %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB9_17
.LBB9_15:
xorl %r15d, %r15d
.LBB9_17: # %_ZNSt12_Vector_baseI8timespecSaIS0_EE11_M_allocateEm.exit.i.i
shlq $4, %rbp
movups 24(%rsp), %xmm0
movups %xmm0, (%r15,%rbp)
testq %rbx, %rbx
jle .LBB9_19
# %bb.18:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB9_19: # %_ZNSt6vectorI8timespecSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit.i.i
addq %r15, %rbx
addq $16, %rbx
testq %r14, %r14
je .LBB9_21
# %bb.20:
movq %r14, %rdi
callq _ZdlPv
.LBB9_21: # %_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_.exit.i
movq %r15, wall(%rip)
movq %rbx, wall+8(%rip)
shlq $4, %r13
addq %r15, %r13
movq %r13, wall+16(%rip)
.LBB9_22: # %_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_.exit
movq proc+8(%rip), %rbx
cmpq proc+16(%rip), %rbx
je .LBB9_24
# %bb.23:
movups 8(%rsp), %xmm0
movups %xmm0, (%rbx)
addq $16, proc+8(%rip)
jmp .LBB9_33
.LBB9_24:
movq proc(%rip), %r14
subq %r14, %rbx
cmpq %r12, %rbx
je .LBB9_34
# %bb.25: # %_ZNKSt6vectorI8timespecSaIS0_EE12_M_check_lenEmPKc.exit.i.i6
movq %rbx, %r13
sarq $4, %r13
cmpq $1, %r13
movq %r13, %rax
adcq $0, %rax
leaq (%rax,%r13), %r12
movabsq $576460752303423487, %rcx # imm = 0x7FFFFFFFFFFFFFF
cmpq %rcx, %r12
cmovaeq %rcx, %r12
addq %r13, %rax
cmovbq %rcx, %r12
testq %r12, %r12
je .LBB9_26
# %bb.27:
movq %r12, %rdi
shlq $4, %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB9_28
.LBB9_26:
xorl %r15d, %r15d
.LBB9_28: # %_ZNSt12_Vector_baseI8timespecSaIS0_EE11_M_allocateEm.exit.i.i9
shlq $4, %r13
movups 8(%rsp), %xmm0
movups %xmm0, (%r15,%r13)
testq %rbx, %rbx
jle .LBB9_30
# %bb.29:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB9_30: # %_ZNSt6vectorI8timespecSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit.i.i10
addq %r15, %rbx
addq $16, %rbx
testq %r14, %r14
je .LBB9_32
# %bb.31:
movq %r14, %rdi
callq _ZdlPv
.LBB9_32: # %_ZNSt6vectorI8timespecSaIS0_EE17_M_realloc_insertIJRKS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_.exit.i12
movq %r15, proc(%rip)
movq %rbx, proc+8(%rip)
shlq $4, %r12
addq %r15, %r12
movq %r12, proc+16(%rip)
.LBB9_33: # %_ZNSt6vectorI8timespecSaIS0_EE9push_backERKS0_.exit13
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB9_34:
.cfi_def_cfa_offset 96
movl $.L.str.20, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end9:
.size _ZL5ftimev, .Lfunc_end9-_ZL5ftimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZL5ptimePKcmmm
.LCPI10_0:
.quad 0x408f400000000000 # double 1000
.LCPI10_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.p2align 4, 0x90
.type _ZL5ptimePKcmmm,@function
_ZL5ptimePKcmmm: # @_ZL5ptimePKcmmm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movq names+8(%rip), %rax
subq names(%rip), %rax
sarq $3, %rax
cmpq %rdi, %rax
jbe .LBB10_9
# %bb.1: # %.lr.ph42
movq %rdx, %rbp
leaq 1(%rdx), %rax
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB10_2
.p2align 4, 0x90
.LBB10_8: # in Loop: Header=BB10_2 Depth=1
movq names+8(%rip), %rax
subq names(%rip), %rax
sarq $3, %rax
movq %r12, %rsi
cmpq %rax, %r14
jae .LBB10_9
.LBB10_2: # =>This Loop Header: Depth=1
# Child Loop BB10_4 Depth 2
# Child Loop BB10_10 Depth 2
movq levels(%rip), %rdi
cmpq %rbp, (%rdi,%rsi,8)
jne .LBB10_9
# %bb.3: # in Loop: Header=BB10_2 Depth=1
movq %r14, 48(%rsp) # 8-byte Spill
leaq 1(%rsi), %r12
movq wall(%rip), %rdx
movq proc(%rip), %rax
leaq 4(,%rsi,8), %rcx
movq %r12, %r8
movq %r12, 40(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB10_4: # Parent Loop BB10_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %r8
incq %r12
addq $8, %rcx
cmpq %rbp, (%rdi,%r8,8)
ja .LBB10_4
# %bb.5: # %_ZL12timespecDiffR8timespecS0_S0_.exit
# in Loop: Header=BB10_2 Depth=1
shlq $4, %rsi
movq -8(%rdx,%rcx,2), %rdi
movq (%rdx,%rcx,2), %r13
subq (%rdx,%rsi), %rdi
movq %rdi, 32(%rsp) # 8-byte Spill
subq 8(%rdx,%rsi), %r13
leaq 1000000000(%r13), %rdx
testq %r13, %r13
cmovnsq %r13, %rdx
movq %rdx, 24(%rsp) # 8-byte Spill
movq -8(%rax,%rcx,2), %r15
movq (%rax,%rcx,2), %rbx
subq (%rax,%rsi), %r15
subq 8(%rax,%rsi), %rbx
leaq 1000000000(%rbx), %rax
testq %rbx, %rbx
cmovnsq %rbx, %rax
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbp, %r14
testq %rbp, %rbp
je .LBB10_6
.p2align 4, 0x90
.LBB10_10: # %.lr.ph
# Parent Loop BB10_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $9, %edi
callq putchar@PLT
decq %r14
jne .LBB10_10
.LBB10_6: # %._crit_edge
# in Loop: Header=BB10_2 Depth=1
sarq $63, %r13
movq 32(%rsp), %rcx # 8-byte Reload
addq %r13, %rcx
sarq $63, %rbx
addq %rbx, %r15
leaq -1(%r12), %rbx
movq names(%rip), %rax
movq 48(%rsp), %r14 # 8-byte Reload
movq (%rax,%r14,8), %rdx
incq %r14
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
movsd .LCPI10_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
cvtsi2sdq 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd .LCPI10_1(%rip), %xmm4 # xmm4 = mem[0],zero
divsd %xmm4, %xmm0
addsd %xmm1, %xmm0
cvtsi2sd %r15, %xmm2
mulsd %xmm3, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1 # 8-byte Folded Reload
divsd %xmm4, %xmm1
addsd %xmm2, %xmm1
movl $.L.str.22, %edi
movl $.L.str.19, %esi
movb $2, %al
callq printf
movslq 40(%rsp), %rsi # 4-byte Folded Reload
cmpq %rbx, %rsi
jae .LBB10_8
# %bb.7: # in Loop: Header=BB10_2 Depth=1
movq %r14, %rdi
movq 8(%rsp), %rdx # 8-byte Reload
callq _ZL5ptimePKcmmm
movq %rax, %r14
jmp .LBB10_8
.LBB10_9: # %.critedge
movq %r14, %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _ZL5ptimePKcmmm, .Lfunc_end10-_ZL5ptimePKcmmm
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_gpu.hip
.type _GLOBAL__sub_I_gpu.hip,@function
_GLOBAL__sub_I_gpu.hip: # @_GLOBAL__sub_I_gpu.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZNSt6vectorIPKcSaIS1_EED2Ev, %edi
movl $names, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt6vectorI8timespecSaIS0_EED2Ev, %edi
movl $wall, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt6vectorI8timespecSaIS0_EED2Ev, %edi
movl $proc, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt6vectorImSaImEED2Ev, %edi
movl $levels, %esi
movl $__dso_handle, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end11:
.size _GLOBAL__sub_I_gpu.hip, .Lfunc_end11-_GLOBAL__sub_I_gpu.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB12_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB12_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end12:
.size __hip_module_ctor, .Lfunc_end12-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB13_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB13_2:
retq
.Lfunc_end13:
.size __hip_module_dtor, .Lfunc_end13-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm,@object # @_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.section .rodata,"a",@progbits
.globl _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.p2align 3, 0x0
_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm:
.quad _Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.size _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Runtime Error: "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Linux Runtime Error: ("
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ") "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "line_id, coordinate_x, coordinate_y\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%llu,%.7f,%.7f\n"
.size .L.str.4, 16
.type names,@object # @names
.bss
.globl names
.p2align 3, 0x0
names:
.zero 24
.size names, 24
.hidden __dso_handle
.type wall,@object # @wall
.globl wall
.p2align 3, 0x0
wall:
.zero 24
.size wall, 24
.type proc,@object # @proc
.globl proc
.p2align 3, 0x0
proc:
.zero 24
.size proc, 24
.type levels,@object # @levels
.globl levels
.p2align 3, 0x0
levels:
.zero 24
.size levels, 24
.type cur_level,@object # @cur_level
.globl cur_level
.p2align 3, 0x0
cur_level:
.quad 0 # 0x0
.size cur_level, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "Program"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Setup"
.size .L.str.9, 6
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Read input"
.size .L.str.11, 11
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Copy to GPU"
.size .L.str.12, 12
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Initialize Texture"
.size .L.str.13, 19
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Allocate Output"
.size .L.str.14, 16
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Computation"
.size .L.str.15, 12
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Copy to host"
.size .L.str.16, 13
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Free device memory"
.size .L.str.17, 19
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Free host memory"
.size .L.str.18, 17
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "GPU"
.size .L.str.19, 4
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "vector::_M_realloc_insert"
.size .L.str.20, 26
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "\"%s\", \"%s\", %.3f, %.3f\n"
.size .L.str.22, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_gpu.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./main image output"
.size .Lstr, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.addrsig_sym __gxx_personality_v0
.addrsig_sym _GLOBAL__sub_I_gpu.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.addrsig_sym _ZSt4cerr
.addrsig_sym names
.addrsig_sym __dso_handle
.addrsig_sym wall
.addrsig_sym proc
.addrsig_sym levels
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9integrateP6float2yfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0070*/ MOV R12, c[0x0][0x17c] ; /* 0x00005f00000c7a02 */
/* 0x000fe40000000f00 */
/*0080*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002600 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f06070 */
/*00a0*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*00b0*/ ISETP.GE.U32.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe20003f06100 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fcc00078e0203 */
/*00d0*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000e220000201000 */
/*00e0*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x002fce00078e0205 */
/*00f0*/ I2F.U32 R6, R4 ; /* 0x0000000400067306 */
/* 0x000e700000201000 */
/*0100*/ F2I.TRUNC.NTZ R3, R0 ; /* 0x0000000000037305 */
/* 0x001fe2000020f100 */
/*0110*/ FMUL R10, R0, 10 ; /* 0x41200000000a7820 */
/* 0x000fce0000400000 */
/*0120*/ F2I.TRUNC.NTZ R2, R6 ; /* 0x0000000600027305 */
/* 0x002e22000020f100 */
/*0130*/ FMUL R11, R6, 5 ; /* 0x40a00000060b7820 */
/* 0x000fe40000400000 */
/*0140*/ IMAD R5, R2, UR4, R3 ; /* 0x0000000402057c24 */
/* 0x001fe2000f8e0203 */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0160*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x178], RZ ; /* 0x00005e0005027a25 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD R7, R5, c[0x0][0x17c], R3 ; /* 0x00005f0005077a24 */
/* 0x000fe200078e0203 */
/*0180*/ LEA R4, P1, R2, c[0x0][0x160], 0x3 ; /* 0x0000580002047a11 */
/* 0x000fc800078218ff */
/*0190*/ LEA.HI.X R5, R2, c[0x0][0x164], R7, 0x3, P1 ; /* 0x0000590002057a11 */
/* 0x000fca00008f1c07 */
/*01a0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e2000c101b04 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R0, P1, R8.reuse, -0x2, RZ ; /* 0xfffffffe08007810 */
/* 0x040fe40007f3e0ff */
/*01d0*/ IADD3 R5, P2, R8, -0x1, RZ ; /* 0xffffffff08057810 */
/* 0x001fe40007f5e0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*01f0*/ IADD3.X R0, R12, -0x1, RZ, P1, !PT ; /* 0xffffffff0c007810 */
/* 0x000fe40000ffe4ff */
/*0200*/ MOV R9, R2 ; /* 0x0000000200097202 */
/* 0x000fe40000000f00 */
/*0210*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc40003f06100 */
/*0220*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe40000000f00 */
/*0230*/ LOP3.LUT P1, RZ, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305ff7812 */
/* 0x040fe4000782c0ff */
/*0240*/ MOV R0, R7 ; /* 0x0000000700007202 */
/* 0x000fe40000000f00 */
/*0250*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0260*/ IADD3.X R10, R12, -0x1, RZ, P2, !PT ; /* 0xffffffff0c0a7810 */
/* 0x000fe400017fe4ff */
/*0270*/ LOP3.LUT R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe200078ec0ff */
/*0280*/ @!P0 BRA 0xb10 ; /* 0x0000088000008947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R11, P0, -R8, R5, RZ ; /* 0x00000005080b7210 */
/* 0x000fc80007f1e1ff */
/*02a0*/ IADD3.X R10, R10, -0x1, RZ, P0, !PT ; /* 0xffffffff0a0a7810 */
/* 0x000fe400007fe4ff */
/*02b0*/ HFMA2.MMA R14, -RZ, RZ, -3, 0 ; /* 0xc2000000ff0e7435 */
/* 0x000fcc00000001ff */
/*02c0*/ TEX.SCR.LL RZ, R4, R2, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e02047b60 */
/* 0x000f4400019e03ff */
/*02d0*/ FMUL R15, R4, c[0x0][0x170] ; /* 0x00005c00040f7a20 */
/* 0x020fe40000400000 */
/*02e0*/ FMUL R6, R5, c[0x0][0x170] ; /* 0x00005c0005067a20 */
/* 0x004fe40000400000 */
/*02f0*/ FFMA R4, R15, 0.5, R2 ; /* 0x3f0000000f047823 */
/* 0x000fe40000000002 */
/*0300*/ FFMA R5, R6, 0.5, R3 ; /* 0x3f00000006057823 */
/* 0x000fcc0000000003 */
/*0310*/ TEX.SCR.LL RZ, R4, R4, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e04047b60 */
/* 0x000f4400019e03ff */
/*0320*/ FMUL R16, R4, c[0x0][0x170] ; /* 0x00005c0004107a20 */
/* 0x020fe40000400000 */
/*0330*/ FMUL R7, R5, c[0x0][0x170] ; /* 0x00005c0005077a20 */
/* 0x000fe40000400000 */
/*0340*/ FFMA R18, R16, 0.5, R2 ; /* 0x3f00000010127823 */
/* 0x000fe40000000002 */
/*0350*/ FFMA R19, R7, 0.5, R3 ; /* 0x3f00000007137823 */
/* 0x000fcc0000000003 */
/*0360*/ TEX.SCR.LL RZ, R18, R18, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e12127b60 */
/* 0x000f4400019e03ff */
/*0370*/ FMUL R17, R18, c[0x0][0x170] ; /* 0x00005c0012117a20 */
/* 0x020fe40000400000 */
/*0380*/ FMUL R20, R19, c[0x0][0x170] ; /* 0x00005c0013147a20 */
/* 0x000fe40000400000 */
/*0390*/ FADD R22, R17, R2 ; /* 0x0000000211167221 */
/* 0x000fe40000000000 */
/*03a0*/ FADD R23, R20, R3 ; /* 0x0000000314177221 */
/* 0x000fc80000000000 */
/*03b0*/ TEX.SCR.LL RZ, R12, R22, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e160c7b60 */
/* 0x000f4200019e03ff */
/*03c0*/ FFMA R16, R16, 2, R15 ; /* 0x4000000010107823 */
/* 0x000fe2000000000f */
/*03d0*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x000fe20000201800 */
/*03e0*/ FFMA R21, R7, 2, R6 ; /* 0x4000000007157823 */
/* 0x000fe40000000006 */
/*03f0*/ FFMA R15, R17, 2, R16 ; /* 0x40000000110f7823 */
/* 0x000fe40000000010 */
/*0400*/ FFMA R20, R20, 2, R21 ; /* 0x4000000014147823 */
/* 0x000fc60000000015 */
/*0410*/ F2F.F64.F32 R6, R2 ; /* 0x0000000200067310 */
/* 0x000fe20000201800 */
/*0420*/ FFMA R12, R12, c[0x0][0x170], R15 ; /* 0x00005c000c0c7a23 */
/* 0x020fe4000000000f */
/*0430*/ FFMA R20, R13, c[0x0][0x170], R20 ; /* 0x00005c000d147a23 */
/* 0x000fca0000000014 */
/*0440*/ F2F.F64.F32 R16, R20 ; /* 0x0000001400107310 */
/* 0x000e300000201800 */
/*0450*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000e620000201800 */
/*0460*/ DFMA R16, R16, c[0x2][0x0], R4 ; /* 0x0080000010107a2b */
/* 0x001e0e0000000004 */
/*0470*/ F2F.F32.F64 R5, R16 ; /* 0x0000001000057310 */
/* 0x001fe20000301000 */
/*0480*/ DFMA R6, R12, c[0x2][0x0], R6 ; /* 0x008000000c067a2b */
/* 0x002e0e0000000006 */
/*0490*/ F2F.F32.F64 R4, R6 ; /* 0x0000000600047310 */
/* 0x001e240000301000 */
/*04a0*/ TEX.SCR.LL RZ, R2, R4, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e04027b60 */
/* 0x001f4400019e03ff */
/*04b0*/ FMUL R13, R2, c[0x0][0x170] ; /* 0x00005c00020d7a20 */
/* 0x020fe40000400000 */
/*04c0*/ FMUL R18, R3, c[0x0][0x170] ; /* 0x00005c0003127a20 */
/* 0x000fe40000400000 */
/*04d0*/ FFMA R2, R13, 0.5, R4 ; /* 0x3f0000000d027823 */
/* 0x000fe40000000004 */
/*04e0*/ FFMA R3, R18, 0.5, R5 ; /* 0x3f00000012037823 */
/* 0x000fcc0000000005 */
/*04f0*/ TEX.SCR.LL RZ, R2, R2, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e02027b60 */
/* 0x000f4400019e03ff */
/*0500*/ FMUL R12, R2, c[0x0][0x170] ; /* 0x00005c00020c7a20 */
/* 0x020fe40000400000 */
/*0510*/ FMUL R15, R3, c[0x0][0x170] ; /* 0x00005c00030f7a20 */
/* 0x000fe40000400000 */
/*0520*/ FFMA R16, R12, 0.5, R4 ; /* 0x3f0000000c107823 */
/* 0x000fe40000000004 */
/*0530*/ FFMA R17, R15, 0.5, R5 ; /* 0x3f0000000f117823 */
/* 0x000fcc0000000005 */
/*0540*/ TEX.SCR.LL RZ, R16, R16, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e10107b60 */
/* 0x000f4400019e03ff */
/*0550*/ FMUL R19, R16, c[0x0][0x170] ; /* 0x00005c0010137a20 */
/* 0x020fe40000400000 */
/*0560*/ FMUL R20, R17, c[0x0][0x170] ; /* 0x00005c0011147a20 */
/* 0x000fe40000400000 */
/*0570*/ FADD R6, R4, R19 ; /* 0x0000001304067221 */
/* 0x000fe40000000000 */
/*0580*/ FADD R7, R5, R20 ; /* 0x0000001405077221 */
/* 0x000fcc0000000000 */
/*0590*/ TEX.SCR.LL RZ, R6, R6, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e06067b60 */
/* 0x000f4200019e03ff */
/*05a0*/ FFMA R12, R12, 2, R13 ; /* 0x400000000c0c7823 */
/* 0x000fe2000000000d */
/*05b0*/ F2F.F64.F32 R2, R4 ; /* 0x0000000400027310 */
/* 0x000fe20000201800 */
/*05c0*/ FFMA R15, R15, 2, R18 ; /* 0x400000000f0f7823 */
/* 0x000fe40000000012 */
/*05d0*/ FFMA R19, R19, 2, R12 ; /* 0x4000000013137823 */
/* 0x000fe4000000000c */
/*05e0*/ FFMA R20, R20, 2, R15 ; /* 0x4000000014147823 */
/* 0x000fc6000000000f */
/*05f0*/ F2F.F64.F32 R12, R5 ; /* 0x00000005000c7310 */
/* 0x000fe20000201800 */
/*0600*/ FFMA R16, R6, c[0x0][0x170], R19 ; /* 0x00005c0006107a23 */
/* 0x020fe40000000013 */
/*0610*/ FFMA R20, R7, c[0x0][0x170], R20 ; /* 0x00005c0007147a23 */
/* 0x000fca0000000014 */
/*0620*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x000e300000201800 */
/*0630*/ F2F.F64.F32 R18, R20 ; /* 0x0000001400127310 */
/* 0x000e620000201800 */
/*0640*/ DFMA R2, R16, c[0x2][0x0], R2 ; /* 0x0080000010027a2b */
/* 0x001e0e0000000002 */
/*0650*/ F2F.F32.F64 R6, R2 ; /* 0x0000000200067310 */
/* 0x001fe20000301000 */
/*0660*/ DFMA R18, R18, c[0x2][0x0], R12 ; /* 0x0080000012127a2b */
/* 0x002e0e000000000c */
/*0670*/ F2F.F32.F64 R7, R18 ; /* 0x0000001200077310 */
/* 0x001e240000301000 */
/*0680*/ TEX.SCR.LL RZ, R22, R6, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e06167b60 */
/* 0x001f4400019e03ff */
/*0690*/ FMUL R13, R22, c[0x0][0x170] ; /* 0x00005c00160d7a20 */
/* 0x020fe40000400000 */
/*06a0*/ FMUL R12, R23, c[0x0][0x170] ; /* 0x00005c00170c7a20 */
/* 0x000fe40000400000 */
/*06b0*/ FFMA R22, R13, 0.5, R6 ; /* 0x3f0000000d167823 */
/* 0x000fe40000000006 */
/*06c0*/ FFMA R23, R12, 0.5, R7 ; /* 0x3f0000000c177823 */
/* 0x000fcc0000000007 */
/*06d0*/ TEX.SCR.LL RZ, R22, R22, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e16167b60 */
/* 0x000f4400019e03ff */
/*06e0*/ FMUL R15, R22, c[0x0][0x170] ; /* 0x00005c00160f7a20 */
/* 0x020fe40000400000 */
/*06f0*/ FMUL R20, R23, c[0x0][0x170] ; /* 0x00005c0017147a20 */
/* 0x000fe40000400000 */
/*0700*/ FFMA R24, R15, 0.5, R6 ; /* 0x3f0000000f187823 */
/* 0x000fe40000000006 */
/*0710*/ FFMA R25, R20, 0.5, R7 ; /* 0x3f00000014197823 */
/* 0x000fcc0000000007 */
/*0720*/ TEX.SCR.LL RZ, R24, R24, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e18187b60 */
/* 0x000f4400019e03ff */
/*0730*/ FMUL R19, R24, c[0x0][0x170] ; /* 0x00005c0018137a20 */
/* 0x020fe40000400000 */
/*0740*/ FMUL R18, R25, c[0x0][0x170] ; /* 0x00005c0019127a20 */
/* 0x000fe40000400000 */
/*0750*/ FADD R16, R6, R19 ; /* 0x0000001306107221 */
/* 0x000fe40000000000 */
/*0760*/ FADD R17, R7, R18 ; /* 0x0000001207117221 */
/* 0x000fcc0000000000 */
/*0770*/ TEX.SCR.LL RZ, R16, R16, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e10107b60 */
/* 0x000f4200019e03ff */
/*0780*/ FFMA R22, R15, 2, R13 ; /* 0x400000000f167823 */
/* 0x000fe2000000000d */
/*0790*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x000fe20000201800 */
/*07a0*/ FFMA R15, R20, 2, R12 ; /* 0x40000000140f7823 */
/* 0x000fe4000000000c */
/*07b0*/ FFMA R19, R19, 2, R22 ; /* 0x4000000013137823 */
/* 0x000fe40000000016 */
/*07c0*/ FFMA R20, R18, 2, R15 ; /* 0x4000000012147823 */
/* 0x000fc6000000000f */
/*07d0*/ F2F.F64.F32 R12, R7 ; /* 0x00000007000c7310 */
/* 0x000fe20000201800 */
/*07e0*/ FFMA R15, R16, c[0x0][0x170], R19 ; /* 0x00005c00100f7a23 */
/* 0x020fe40000000013 */
/*07f0*/ FFMA R22, R17, c[0x0][0x170], R20 ; /* 0x00005c0011167a23 */
/* 0x000fca0000000014 */
/*0800*/ F2F.F64.F32 R18, R15 ; /* 0x0000000f00127310 */
/* 0x000e300000201800 */
/*0810*/ F2F.F64.F32 R20, R22 ; /* 0x0000001600147310 */
/* 0x000e620000201800 */
/*0820*/ DFMA R18, R18, c[0x2][0x0], R2 ; /* 0x0080000012127a2b */
/* 0x001e0e0000000002 */
/*0830*/ F2F.F32.F64 R2, R18 ; /* 0x0000001200027310 */
/* 0x001fe20000301000 */
/*0840*/ DFMA R12, R20, c[0x2][0x0], R12 ; /* 0x00800000140c7a2b */
/* 0x002e0e000000000c */
/*0850*/ F2F.F32.F64 R3, R12 ; /* 0x0000000c00037310 */
/* 0x001e240000301000 */
/*0860*/ TEX.SCR.LL RZ, R16, R2, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e02107b60 */
/* 0x001f4400019e03ff */
/*0870*/ FMUL R21, R16, c[0x0][0x170] ; /* 0x00005c0010157a20 */
/* 0x020fe40000400000 */
/*0880*/ FMUL R20, R17, c[0x0][0x170] ; /* 0x00005c0011147a20 */
/* 0x000fe40000400000 */
/*0890*/ FFMA R26, R21, 0.5, R2 ; /* 0x3f000000151a7823 */
/* 0x000fe40000000002 */
/*08a0*/ FFMA R27, R20, 0.5, R3 ; /* 0x3f000000141b7823 */
/* 0x000fcc0000000003 */
/*08b0*/ TEX.SCR.LL RZ, R26, R26, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e1a1a7b60 */
/* 0x000f4400019e03ff */
/*08c0*/ FMUL R22, R26, c[0x0][0x170] ; /* 0x00005c001a167a20 */
/* 0x020fe40000400000 */
/*08d0*/ FMUL R15, R27, c[0x0][0x170] ; /* 0x00005c001b0f7a20 */
/* 0x000fe40000400000 */
/*08e0*/ FFMA R28, R22, 0.5, R2 ; /* 0x3f000000161c7823 */
/* 0x000fe40000000002 */
/*08f0*/ FFMA R29, R15, 0.5, R3 ; /* 0x3f0000000f1d7823 */
/* 0x000fc80000000003 */
/*0900*/ TEX.SCR.LL RZ, R12, R28, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e1c0c7b60 */
/* 0x000f4400019e03ff */
/*0910*/ FMUL R25, R12, c[0x0][0x170] ; /* 0x00005c000c197a20 */
/* 0x020fe40000400000 */
/*0920*/ FMUL R24, R13, c[0x0][0x170] ; /* 0x00005c000d187a20 */
/* 0x000fe40000400000 */
/*0930*/ FADD R16, R2, R25 ; /* 0x0000001902107221 */
/* 0x000fe40000000000 */
/*0940*/ FADD R17, R3, R24 ; /* 0x0000001803117221 */
/* 0x000fcc0000000000 */
/*0950*/ TEX.SCR.LL RZ, R16, R16, R14, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0e10107b60 */
/* 0x000f4200019e03ff */
/*0960*/ FFMA R26, R22, 2, R21 ; /* 0x40000000161a7823 */
/* 0x000fe20000000015 */
/*0970*/ LEA R12, P0, R9, c[0x0][0x160], 0x3 ; /* 0x00005800090c7a11 */
/* 0x000fe200078018ff */
/*0980*/ FFMA R15, R15, 2, R20 ; /* 0x400000000f0f7823 */
/* 0x000fe20000000014 */
/*0990*/ F2F.F64.F32 R18, R2 ; /* 0x0000000200127310 */
/* 0x000fe20000201800 */
/*09a0*/ FFMA R25, R25, 2, R26 ; /* 0x4000000019197823 */
/* 0x000fe2000000001a */
/*09b0*/ LEA.HI.X R13, R9, c[0x0][0x164], R0, 0x3, P0 ; /* 0x00005900090d7a11 */
/* 0x000fe200000f1c00 */
/*09c0*/ FFMA R24, R24, 2, R15 ; /* 0x4000000018187823 */
/* 0x000fe2000000000f */
/*09d0*/ IADD3 R11, P0, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe40007f1e0ff */
/*09e0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f5e0ff */
/*09f0*/ STG.E.64 [R12.64+0x8], R4 ; /* 0x000008040c007986 */
/* 0x0001e2000c101b04 */
/*0a00*/ F2F.F64.F32 R22, R3 ; /* 0x0000000300167310 */
/* 0x000fe20000201800 */
/*0a10*/ IADD3.X R10, R10, -0x1, RZ, P0, !PT ; /* 0xffffffff0a0a7810 */
/* 0x000fc400007fe4ff */
/*0a20*/ STG.E.64 [R12.64+0x18], R2 ; /* 0x000018020c007986 */
/* 0x0003e2000c101b04 */
/*0a30*/ ISETP.NE.U32.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05070 */
/*0a40*/ IADD3.X R0, RZ, R0, RZ, P2, !PT ; /* 0x00000000ff007210 */
/* 0x000fe200017fe4ff */
/*0a50*/ STG.E.64 [R12.64+0x10], R6 ; /* 0x000010060c007986 */
/* 0x0005e2000c101b04 */
/*0a60*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05300 */
/*0a70*/ FFMA R16, R16, c[0x0][0x170], R25 ; /* 0x00005c0010107a23 */
/* 0x020fe40000000019 */
/*0a80*/ FFMA R17, R17, c[0x0][0x170], R24 ; /* 0x00005c0011117a23 */
/* 0x000fe40000000018 */
/*0a90*/ F2F.F64.F32 R14, R16 ; /* 0x00000010000e7310 */
/* 0x000ef00000201800 */
/*0aa0*/ F2F.F64.F32 R4, R17 ; /* 0x0000001100047310 */
/* 0x001e220000201800 */
/*0ab0*/ DFMA R14, R14, c[0x2][0x0], R18 ; /* 0x008000000e0e7a2b */
/* 0x008e4e0000000012 */
/*0ac0*/ F2F.F32.F64 R2, R14 ; /* 0x0000000e00027310 */
/* 0x002fe20000301000 */
/*0ad0*/ DFMA R4, R4, c[0x2][0x0], R22 ; /* 0x0080000004047a2b */
/* 0x001e0e0000000016 */
/*0ae0*/ F2F.F32.F64 R3, R4 ; /* 0x0000000400037310 */
/* 0x001e240000301000 */
/*0af0*/ STG.E.64 [R12.64+0x20], R2 ; /* 0x000020020c007986 */
/* 0x0015e2000c101b04 */
/*0b00*/ @P0 BRA 0x2b0 ; /* 0xfffff7a000000947 */
/* 0x000fea000383ffff */
/*0b10*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0b20*/ LEA R4, P0, R9.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580009047a11 */
/* 0x040fe400078018ff */
/*0b30*/ IADD3 R8, P2, RZ, -R8, RZ ; /* 0x80000008ff087210 */
/* 0x000fe40007f5e0ff */
/*0b40*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0b50*/ LEA.HI.X R5, R9, c[0x0][0x164], R0, 0x3, P0 ; /* 0x0000590009057a11 */
/* 0x000fe400000f1c00 */
/*0b60*/ IADD3.X R0, RZ, -0x1, RZ, P2, !PT ; /* 0xffffffffff007810 */
/* 0x000fc400017fe4ff */
/*0b70*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0b80*/ MOV R9, 0xc2000000 ; /* 0xc200000000097802 */
/* 0x000fc80000000f00 */
/*0b90*/ TEX.SCR.LL RZ, R6, R2, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0902067b60 */
/* 0x005f4400019e03ff */
/*0ba0*/ FMUL R13, R6, c[0x0][0x170] ; /* 0x00005c00060d7a20 */
/* 0x020fe40000400000 */
/*0bb0*/ FMUL R14, R7, c[0x0][0x170] ; /* 0x00005c00070e7a20 */
/* 0x000fe40000400000 */
/*0bc0*/ FFMA R6, R13, 0.5, R2 ; /* 0x3f0000000d067823 */
/* 0x000fe40000000002 */
/*0bd0*/ FFMA R7, R14, 0.5, R3 ; /* 0x3f0000000e077823 */
/* 0x000fcc0000000003 */
/*0be0*/ TEX.SCR.LL RZ, R6, R6, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0906067b60 */
/* 0x000f4400019e03ff */
/*0bf0*/ FMUL R12, R6, c[0x0][0x170] ; /* 0x00005c00060c7a20 */
/* 0x020fe40000400000 */
/*0c00*/ FMUL R15, R7, c[0x0][0x170] ; /* 0x00005c00070f7a20 */
/* 0x000fe40000400000 */
/*0c10*/ FFMA R16, R12, 0.5, R2 ; /* 0x3f0000000c107823 */
/* 0x000fe40000000002 */
/*0c20*/ FFMA R17, R15, 0.5, R3 ; /* 0x3f0000000f117823 */
/* 0x000fcc0000000003 */
/*0c30*/ TEX.SCR.LL RZ, R16, R16, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a0910107b60 */
/* 0x000f4400019e03ff */
/*0c40*/ FMUL R19, R16, c[0x0][0x170] ; /* 0x00005c0010137a20 */
/* 0x020fe40000400000 */
/*0c50*/ FMUL R18, R17, c[0x0][0x170] ; /* 0x00005c0011127a20 */
/* 0x000fe40000400000 */
/*0c60*/ FADD R20, R19, R2 ; /* 0x0000000213147221 */
/* 0x000fe40000000000 */
/*0c70*/ FADD R21, R18, R3 ; /* 0x0000000312157221 */
/* 0x000fc80000000000 */
/*0c80*/ TEX.SCR.LL RZ, R10, R20, R9, 0x0, 0x5a, 2D, 0x3 ; /* 0x30005a09140a7b60 */
/* 0x000f4200019e03ff */
/*0c90*/ FFMA R22, R12, 2, R13 ; /* 0x400000000c167823 */
/* 0x000fe2000000000d */
/*0ca0*/ F2F.F64.F32 R6, R2 ; /* 0x0000000200067310 */
/* 0x000fe20000201800 */
/*0cb0*/ FFMA R15, R15, 2, R14 ; /* 0x400000000f0f7823 */
/* 0x000fe2000000000e */
/*0cc0*/ IADD3 R8, P0, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007f1e0ff */
/*0cd0*/ FFMA R19, R19, 2, R22 ; /* 0x4000000013137823 */
/* 0x000fe40000000016 */
/*0ce0*/ FFMA R18, R18, 2, R15 ; /* 0x4000000012127823 */
/* 0x000fe2000000000f */
/*0cf0*/ IADD3.X R0, RZ, R0, RZ, P0, !PT ; /* 0x00000000ff007210 */
/* 0x000fe400007fe4ff */
/*0d00*/ F2F.F64.F32 R12, R3 ; /* 0x00000003000c7310 */
/* 0x000fe20000201800 */
/*0d10*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0d20*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0d30*/ FFMA R14, R10, c[0x0][0x170], R19 ; /* 0x00005c000a0e7a23 */
/* 0x020fe40000000013 */
/*0d40*/ FFMA R18, R11, c[0x0][0x170], R18 ; /* 0x00005c000b127a23 */
/* 0x000fc80000000012 */
/*0d50*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000e300000201800 */
/*0d60*/ F2F.F64.F32 R10, R18 ; /* 0x00000012000a7310 */
/* 0x000e620000201800 */
/*0d70*/ DFMA R6, R14, c[0x2][0x0], R6 ; /* 0x008000000e067a2b */
/* 0x001e0e0000000006 */
/*0d80*/ F2F.F32.F64 R2, R6 ; /* 0x0000000600027310 */
/* 0x0011e20000301000 */
/*0d90*/ DFMA R10, R10, c[0x2][0x0], R12 ; /* 0x008000000a0a7a2b */
/* 0x002e4e000000000c */
/*0da0*/ F2F.F32.F64 R3, R10 ; /* 0x0000000a00037310 */
/* 0x002e620000301000 */
/*0db0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe40000000f00 */
/*0dc0*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0dd0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc80007f3e0ff */
/*0de0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0df0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0021e2000c101b04 */
/*0e00*/ @P0 BRA 0xb80 ; /* 0xfffffd7000000947 */
/* 0x000fea000383ffff */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.globl _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.p2align 8
.type _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm,@function
_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[16:17], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s4, s4, s5
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s5, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v5, v2
v_cvt_f32_u32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v1, v5
v_cvt_i32_f32_e32 v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s4, v1, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e64 s4, s[2:3], 2
v_mad_u64_u32 v[0:1], null, v2, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_mul_f32_e32 v0, 0x41200000, v6
v_mul_f32_e32 v1, 0x40a00000, v5
v_add_co_u32 v3, vcc_lo, s16, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
s_and_b32 vcc_lo, exec_lo, s4
global_store_b64 v[3:4], v[0:1], off
s_cbranch_vccnz .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s1, s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, s2, v2, 0
s_waitcnt lgkmcnt(0)
s_clause 0x3
s_load_b32 s0, s[4:5], 0x38
s_load_b32 s6, s[4:5], 0x30
s_load_b32 s7, s[4:5], 0x8
s_load_b32 s18, s[4:5], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, s3, v2, v[4:5]
s_load_b128 s[12:15], s[4:5], 0x30
v_mov_b32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[3:4]
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
v_cvt_f32_u32_e32 v6, s18
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s6, 15
s_cselect_b32 s0, -1, 0
s_bfe_u32 s6, s7, 0xe000e
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_i32 s19, s6, 1
s_load_b256 s[4:11], s[4:5], 0x0
v_cvt_f32_u32_e32 v5, s19
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
v_cndmask_b32_e64 v4, 1.0, v5, s0
v_cndmask_b32_e64 v5, 1.0, v6, s0
v_add_co_u32 v2, s0, v2, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v3, s0, s17, v3, s0
v_rcp_f32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v5
v_add_co_u32 v2, s0, v2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_mov_b32 s17, 0x3fc55555
s_mov_b32 s16, 0x55555555
.LBB0_2:
v_dual_mul_f32 v8, v1, v4 :: v_dual_mul_f32 v9, v0, v5
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u64 s[2:3], 0
v_floor_f32_e32 v8, v8
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v6, v8
v_dual_mul_f32 v10, v7, v9 :: v_dual_cndmask_b32 v9, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v0, v10, vcc_lo
s_waitcnt lgkmcnt(0)
image_sample_lz v[8:9], v[8:9], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_dual_mul_f32 v14, s1, v9 :: v_dual_mul_f32 v15, s1, v8
v_fma_f32 v8, 0.5, v14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, 0.5, v15, v0
v_mul_f32_e32 v11, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v11, v11
v_mul_f32_e32 v11, v7, v11
v_mul_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v9, v9
v_mul_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v8, v9 :: v_dual_cndmask_b32 v8, v10, v11
image_sample_lz v[8:9], v[8:9], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_dual_mul_f32 v16, s1, v9 :: v_dual_mul_f32 v17, s1, v8
v_fma_f32 v8, 0.5, v16, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v10, 0.5, v17, v0
v_dual_fmac_f32 v14, 2.0, v16 :: v_dual_fmac_f32 v15, 2.0, v17
v_mul_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v10, v5
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v11, v11
v_mul_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v7, v11
v_dual_cndmask_b32 v9, v8, v9 :: v_dual_cndmask_b32 v8, v10, v11
image_sample_lz v[8:9], v[8:9], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_fma_f32 v10, s1, v9, v1
v_fma_f32 v12, s1, v8, v0
v_dual_mul_f32 v9, s1, v9 :: v_dual_mul_f32 v8, s1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v10, v4
v_mul_f32_e32 v13, v12, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v14, 2.0, v9 :: v_dual_fmac_f32 v15, 2.0, v8
v_floor_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v13, v13
v_mul_f32_e32 v11, v6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, v7, v13
v_dual_cndmask_b32 v11, v10, v11 :: v_dual_cndmask_b32 v10, v12, v13
v_cvt_f64_f32_e32 v[12:13], v0
v_cvt_f64_f32_e32 v[0:1], v1
image_sample_lz v[10:11], v[10:11], s[4:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v15, s1, v10 :: v_dual_fmac_f32 v14, s1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[8:9], v15
v_cvt_f64_f32_e32 v[10:11], v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], s[16:17], v[12:13]
v_fma_f64 v[10:11], v[10:11], s[16:17], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v0, v[8:9]
v_cvt_f32_f64_e32 v1, v[10:11]
global_store_b64 v[2:3], v[0:1], off
v_add_co_u32 v2, s0, v2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm, .Lfunc_end0-_Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z9integrateP15HIP_vector_typeIfLj2EEP13__hip_texturefm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
int main()
{
const unsigned int N = 1048576;
const unsigned int bytes = N * sizeof(int);
int *h_a = (int*)malloc(bytes);
int *d_a;
cudaMalloc((int**)&d_a, bytes);
memset(h_a, 0, bytes);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(h_a, d_a, bytes, cudaMemcpyDeviceToHost);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
int main()
{
const unsigned int N = 1048576;
const unsigned int bytes = N * sizeof(int);
int *h_a = (int*)malloc(bytes);
int *d_a;
cudaMalloc((int**)&d_a, bytes);
memset(h_a, 0, bytes);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(h_a, d_a, bytes, cudaMemcpyDeviceToHost);
return 0;
} | .file "tmpxft_00117233_00000000-6_profile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $4194304, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4194304, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
int main()
{
const unsigned int N = 1048576;
const unsigned int bytes = N * sizeof(int);
int *h_a = (int*)malloc(bytes);
int *d_a;
cudaMalloc((int**)&d_a, bytes);
memset(h_a, 0, bytes);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(h_a, d_a, bytes, cudaMemcpyDeviceToHost);
return 0;
} | #include <hip/hip_runtime.h>
/* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
int main()
{
const unsigned int N = 1048576;
const unsigned int bytes = N * sizeof(int);
int *h_a = (int*)malloc(bytes);
int *d_a;
hipMalloc((int**)&d_a, bytes);
memset(h_a, 0, bytes);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(h_a, d_a, bytes, hipMemcpyDeviceToHost);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
int main()
{
const unsigned int N = 1048576;
const unsigned int bytes = N * sizeof(int);
int *h_a = (int*)malloc(bytes);
int *d_a;
hipMalloc((int**)&d_a, bytes);
memset(h_a, 0, bytes);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(h_a, d_a, bytes, hipMemcpyDeviceToHost);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
int main()
{
const unsigned int N = 1048576;
const unsigned int bytes = N * sizeof(int);
int *h_a = (int*)malloc(bytes);
int *d_a;
hipMalloc((int**)&d_a, bytes);
memset(h_a, 0, bytes);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(h_a, d_a, bytes, hipMemcpyDeviceToHost);
return 0;
} | .text
.file "profile.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00117233_00000000-6_profile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $4194304, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4194304, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "profile.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //-nvcc -arch=sm_11 -m64 -O3 main.cu -o atomic.bin
#include<iostream>
#include<cstdlib>
#include <cuda_runtime.h>
#include <cassert>
#include <vector>
#define CHECK_ERROR(call) do { \
if( cudaSuccess != call) { \
std::cerr << std::endl << "CUDA ERRO: " << \
cudaGetErrorString(call) << " in file: " << __FILE__ \
<< " in line: " << __LINE__ << std::endl; \
exit(0); \
} } while (0)
__global__
void kernel (int *vet, int *flag){
unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
vet[index] = index + 1;
if (threadIdx.x == 0)
atomicAdd(&flag[0], 1);
}
using namespace std;
int main(int argc, char *argv[]){
int dominio = 32,
threads = 4;
vector <int> h_vet;
int *d_Vet = NULL,
*d_Flag = NULL;
cout << "\nOperacao atomica\n";
//Reset no device
CHECK_ERROR(cudaDeviceReset());
//Alocando memória
h_vet.resize(dominio);
cudaMalloc(reinterpret_cast<void**> (&d_Vet), dominio * sizeof(int));
cudaMalloc(reinterpret_cast<void**> (&d_Flag), 1 * sizeof(int));
//Inicializando variáveis
bzero(&(h_vet[0]), dominio * sizeof(float));
CHECK_ERROR(cudaMemset(d_Vet, 0, dominio * sizeof(int)));
CHECK_ERROR(cudaMemset(d_Flag, 0, 1 * sizeof(int)));
int blocos = dominio / threads;
cout << "Blocos: " << blocos << endl;
cout << "Threads: " << threads << endl;
kernel<<<blocos, threads>>> (d_Vet, d_Flag);
CHECK_ERROR(cudaDeviceSynchronize());
cudaMemcpy(&(h_vet[0]), d_Vet, dominio * sizeof(int), cudaMemcpyDeviceToHost);
for (int k = 0; k < dominio; k++)
cout << h_vet[k] << endl;
cout << endl;
cudaMemcpy(&(h_vet[0]), d_Flag, 1 * sizeof(int), cudaMemcpyDeviceToHost);
cout << "cada thread[0] soma 1: " << h_vet[0] << endl;
cudaFree(d_Vet);
cudaFree(d_Flag);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fe20003f05270 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0203 */
/*0070*/ IADD3 R5, R2.reuse, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x040fe20007ffe0ff */
/*0080*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0007 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x001fe200078e00ff */
/*00c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*00e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //-nvcc -arch=sm_11 -m64 -O3 main.cu -o atomic.bin
#include<iostream>
#include<cstdlib>
#include <cuda_runtime.h>
#include <cassert>
#include <vector>
#define CHECK_ERROR(call) do { \
if( cudaSuccess != call) { \
std::cerr << std::endl << "CUDA ERRO: " << \
cudaGetErrorString(call) << " in file: " << __FILE__ \
<< " in line: " << __LINE__ << std::endl; \
exit(0); \
} } while (0)
__global__
void kernel (int *vet, int *flag){
unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
vet[index] = index + 1;
if (threadIdx.x == 0)
atomicAdd(&flag[0], 1);
}
using namespace std;
int main(int argc, char *argv[]){
int dominio = 32,
threads = 4;
vector <int> h_vet;
int *d_Vet = NULL,
*d_Flag = NULL;
cout << "\nOperacao atomica\n";
//Reset no device
CHECK_ERROR(cudaDeviceReset());
//Alocando memória
h_vet.resize(dominio);
cudaMalloc(reinterpret_cast<void**> (&d_Vet), dominio * sizeof(int));
cudaMalloc(reinterpret_cast<void**> (&d_Flag), 1 * sizeof(int));
//Inicializando variáveis
bzero(&(h_vet[0]), dominio * sizeof(float));
CHECK_ERROR(cudaMemset(d_Vet, 0, dominio * sizeof(int)));
CHECK_ERROR(cudaMemset(d_Flag, 0, 1 * sizeof(int)));
int blocos = dominio / threads;
cout << "Blocos: " << blocos << endl;
cout << "Threads: " << threads << endl;
kernel<<<blocos, threads>>> (d_Vet, d_Flag);
CHECK_ERROR(cudaDeviceSynchronize());
cudaMemcpy(&(h_vet[0]), d_Vet, dominio * sizeof(int), cudaMemcpyDeviceToHost);
for (int k = 0; k < dominio; k++)
cout << h_vet[k] << endl;
cout << endl;
cudaMemcpy(&(h_vet[0]), d_Flag, 1 * sizeof(int), cudaMemcpyDeviceToHost);
cout << "cada thread[0] soma 1: " << h_vet[0] << endl;
cudaFree(d_Vet);
cudaFree(d_Flag);
return EXIT_SUCCESS;
} | .file "tmpxft_00194945_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4045:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB4067:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4380:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4380:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_default_appendEm.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::_M_default_append"
.section .text._ZNSt6vectorIiSaIiEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_default_appendEm,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_default_appendEm
.type _ZNSt6vectorIiSaIiEE17_M_default_appendEm, @function
_ZNSt6vectorIiSaIiEE17_M_default_appendEm:
.LFB4543:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L33
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq 8(%rdi), %rdx
movq (%rdi), %r15
movq %rdx, %r14
subq %r15, %r14
movq %r14, %r13
sarq $2, %r13
movabsq $2305843009213693951, %rax
subq %r13, %rax
movq %rax, %rcx
movq 16(%rdi), %rax
subq %rdx, %rax
sarq $2, %rax
cmpq %rsi, %rax
jb .L21
movl $0, (%rdx)
leaq 4(%rdx), %rsi
subq $1, %rbx
je .L22
leaq (%rsi,%rbx,4), %rcx
movq %rsi, %rax
.L23:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L23
subq %rdx, %rcx
leaq -4(%rsi,%rcx), %rsi
.L22:
movq %rsi, 8(%rbp)
.L19:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
cmpq %rsi, %rcx
jb .L36
cmpq %r13, %rsi
movq %r13, %rax
cmovnb %rsi, %rax
addq %r13, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
cmova %rdx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call _Znwm@PLT
movq %rax, %r12
leaq (%rax,%r14), %rax
movl $0, (%rax)
movq %rbx, %rdx
subq $1, %rdx
je .L25
addq $4, %rax
leaq (%rax,%rdx,4), %rdx
.L26:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L26
.L25:
testq %r14, %r14
jg .L37
testq %r15, %r15
je .L29
movq 16(%rbp), %rsi
subq %r15, %rsi
jmp .L28
.L36:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L37:
movq %r14, %rdx
movq %r15, %rsi
movq %r12, %rdi
call memmove@PLT
movq 16(%rbp), %rsi
subq %r15, %rsi
.L28:
movq %r15, %rdi
call _ZdlPvm@PLT
.L29:
movq %r12, 0(%rbp)
addq %r13, %rbx
leaq (%r12,%rbx,4), %rax
movq %rax, 8(%rbp)
movq 8(%rsp), %rax
addq %rax, %r12
movq %r12, 16(%rbp)
jmp .L19
.L33:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE4543:
.size _ZNSt6vectorIiSaIiEE17_M_default_appendEm, .-_ZNSt6vectorIiSaIiEE17_M_default_appendEm
.section .rodata.str1.1
.LC2:
.string "\nOperacao atomica\n"
.LC3:
.string "CUDA ERRO: "
.LC4:
.string " in file: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/marzam/HPC-Aula/main/exemplos/cuda/05-Atomic/atomic.cu"
.section .rodata.str1.1
.LC6:
.string " in line: "
.LC7:
.string "Blocos: "
.LC8:
.string "Threads: "
.LC9:
.string "cada thread[0] soma 1: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
je .L39
leaq _ZSt4cerr(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call cudaDeviceReset@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $56, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L39:
leaq 48(%rsp), %rdi
movl $32, %esi
call _ZNSt6vectorIiSaIiEE17_M_default_appendEm
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq 48(%rsp), %r14
movl $32, %ecx
movl $0, %eax
movq %r14, %rdi
rep stosl
movl $128, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
je .L40
leaq _ZSt4cerr(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $128, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $66, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L40:
movl $4, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
je .L41
leaq _ZSt4cerr(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $4, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $67, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L41:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $4, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
.L42:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L43
leaq _ZSt4cerr(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $78, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L43:
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbp
leaq 128(%r14), %r12
leaq _ZSt4cout(%rip), %r13
jmp .L48
.L60:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
je .L46
movzbl 67(%r15), %esi
.L47:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L57
.L56:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L52:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L58:
call __stack_chk_fail@PLT
.L46:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L47
.L57:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq %rbp, %r12
je .L59
.L48:
movl 0(%rbp), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
jmp .L60
.L59:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r14), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE0:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 .L52-.LFB4032
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //-nvcc -arch=sm_11 -m64 -O3 main.cu -o atomic.bin
#include<iostream>
#include<cstdlib>
#include <cuda_runtime.h>
#include <cassert>
#include <vector>
#define CHECK_ERROR(call) do { \
if( cudaSuccess != call) { \
std::cerr << std::endl << "CUDA ERRO: " << \
cudaGetErrorString(call) << " in file: " << __FILE__ \
<< " in line: " << __LINE__ << std::endl; \
exit(0); \
} } while (0)
__global__
void kernel (int *vet, int *flag){
unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
vet[index] = index + 1;
if (threadIdx.x == 0)
atomicAdd(&flag[0], 1);
}
using namespace std;
int main(int argc, char *argv[]){
int dominio = 32,
threads = 4;
vector <int> h_vet;
int *d_Vet = NULL,
*d_Flag = NULL;
cout << "\nOperacao atomica\n";
//Reset no device
CHECK_ERROR(cudaDeviceReset());
//Alocando memória
h_vet.resize(dominio);
cudaMalloc(reinterpret_cast<void**> (&d_Vet), dominio * sizeof(int));
cudaMalloc(reinterpret_cast<void**> (&d_Flag), 1 * sizeof(int));
//Inicializando variáveis
bzero(&(h_vet[0]), dominio * sizeof(float));
CHECK_ERROR(cudaMemset(d_Vet, 0, dominio * sizeof(int)));
CHECK_ERROR(cudaMemset(d_Flag, 0, 1 * sizeof(int)));
int blocos = dominio / threads;
cout << "Blocos: " << blocos << endl;
cout << "Threads: " << threads << endl;
kernel<<<blocos, threads>>> (d_Vet, d_Flag);
CHECK_ERROR(cudaDeviceSynchronize());
cudaMemcpy(&(h_vet[0]), d_Vet, dominio * sizeof(int), cudaMemcpyDeviceToHost);
for (int k = 0; k < dominio; k++)
cout << h_vet[k] << endl;
cout << endl;
cudaMemcpy(&(h_vet[0]), d_Flag, 1 * sizeof(int), cudaMemcpyDeviceToHost);
cout << "cada thread[0] soma 1: " << h_vet[0] << endl;
cudaFree(d_Vet);
cudaFree(d_Flag);
return EXIT_SUCCESS;
} | //-nvcc -arch=sm_11 -m64 -O3 main.cu -o atomic.bin
#include<iostream>
#include<cstdlib>
#include <hip/hip_runtime.h>
#include <cassert>
#include <vector>
#define CHECK_ERROR(call) do { \
if( hipSuccess != call) { \
std::cerr << std::endl << "CUDA ERRO: " << \
hipGetErrorString(call) << " in file: " << __FILE__ \
<< " in line: " << __LINE__ << std::endl; \
exit(0); \
} } while (0)
__global__
void kernel (int *vet, int *flag){
unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
vet[index] = index + 1;
if (threadIdx.x == 0)
atomicAdd(&flag[0], 1);
}
using namespace std;
int main(int argc, char *argv[]){
int dominio = 32,
threads = 4;
vector <int> h_vet;
int *d_Vet = NULL,
*d_Flag = NULL;
cout << "\nOperacao atomica\n";
//Reset no device
CHECK_ERROR(hipDeviceReset());
//Alocando memória
h_vet.resize(dominio);
hipMalloc(reinterpret_cast<void**> (&d_Vet), dominio * sizeof(int));
hipMalloc(reinterpret_cast<void**> (&d_Flag), 1 * sizeof(int));
//Inicializando variáveis
bzero(&(h_vet[0]), dominio * sizeof(float));
CHECK_ERROR(hipMemset(d_Vet, 0, dominio * sizeof(int)));
CHECK_ERROR(hipMemset(d_Flag, 0, 1 * sizeof(int)));
int blocos = dominio / threads;
cout << "Blocos: " << blocos << endl;
cout << "Threads: " << threads << endl;
kernel<<<blocos, threads>>> (d_Vet, d_Flag);
CHECK_ERROR(hipDeviceSynchronize());
hipMemcpy(&(h_vet[0]), d_Vet, dominio * sizeof(int), hipMemcpyDeviceToHost);
for (int k = 0; k < dominio; k++)
cout << h_vet[k] << endl;
cout << endl;
hipMemcpy(&(h_vet[0]), d_Flag, 1 * sizeof(int), hipMemcpyDeviceToHost);
cout << "cada thread[0] soma 1: " << h_vet[0] << endl;
hipFree(d_Vet);
hipFree(d_Flag);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //-nvcc -arch=sm_11 -m64 -O3 main.cu -o atomic.bin
#include<iostream>
#include<cstdlib>
#include <hip/hip_runtime.h>
#include <cassert>
#include <vector>
#define CHECK_ERROR(call) do { \
if( hipSuccess != call) { \
std::cerr << std::endl << "CUDA ERRO: " << \
hipGetErrorString(call) << " in file: " << __FILE__ \
<< " in line: " << __LINE__ << std::endl; \
exit(0); \
} } while (0)
__global__
void kernel (int *vet, int *flag){
unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
vet[index] = index + 1;
if (threadIdx.x == 0)
atomicAdd(&flag[0], 1);
}
using namespace std;
int main(int argc, char *argv[]){
int dominio = 32,
threads = 4;
vector <int> h_vet;
int *d_Vet = NULL,
*d_Flag = NULL;
cout << "\nOperacao atomica\n";
//Reset no device
CHECK_ERROR(hipDeviceReset());
//Alocando memória
h_vet.resize(dominio);
hipMalloc(reinterpret_cast<void**> (&d_Vet), dominio * sizeof(int));
hipMalloc(reinterpret_cast<void**> (&d_Flag), 1 * sizeof(int));
//Inicializando variáveis
bzero(&(h_vet[0]), dominio * sizeof(float));
CHECK_ERROR(hipMemset(d_Vet, 0, dominio * sizeof(int)));
CHECK_ERROR(hipMemset(d_Flag, 0, 1 * sizeof(int)));
int blocos = dominio / threads;
cout << "Blocos: " << blocos << endl;
cout << "Threads: " << threads << endl;
kernel<<<blocos, threads>>> (d_Vet, d_Flag);
CHECK_ERROR(hipDeviceSynchronize());
hipMemcpy(&(h_vet[0]), d_Vet, dominio * sizeof(int), hipMemcpyDeviceToHost);
for (int k = 0; k < dominio; k++)
cout << h_vet[k] << endl;
cout << endl;
hipMemcpy(&(h_vet[0]), d_Flag, 1 * sizeof(int), hipMemcpyDeviceToHost);
cout << "cada thread[0] soma 1: " << h_vet[0] << endl;
hipFree(d_Vet);
hipFree(d_Flag);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[1:2], v4, off
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //-nvcc -arch=sm_11 -m64 -O3 main.cu -o atomic.bin
#include<iostream>
#include<cstdlib>
#include <hip/hip_runtime.h>
#include <cassert>
#include <vector>
#define CHECK_ERROR(call) do { \
if( hipSuccess != call) { \
std::cerr << std::endl << "CUDA ERRO: " << \
hipGetErrorString(call) << " in file: " << __FILE__ \
<< " in line: " << __LINE__ << std::endl; \
exit(0); \
} } while (0)
__global__
void kernel (int *vet, int *flag){
unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
vet[index] = index + 1;
if (threadIdx.x == 0)
atomicAdd(&flag[0], 1);
}
using namespace std;
int main(int argc, char *argv[]){
int dominio = 32,
threads = 4;
vector <int> h_vet;
int *d_Vet = NULL,
*d_Flag = NULL;
cout << "\nOperacao atomica\n";
//Reset no device
CHECK_ERROR(hipDeviceReset());
//Alocando memória
h_vet.resize(dominio);
hipMalloc(reinterpret_cast<void**> (&d_Vet), dominio * sizeof(int));
hipMalloc(reinterpret_cast<void**> (&d_Flag), 1 * sizeof(int));
//Inicializando variáveis
bzero(&(h_vet[0]), dominio * sizeof(float));
CHECK_ERROR(hipMemset(d_Vet, 0, dominio * sizeof(int)));
CHECK_ERROR(hipMemset(d_Flag, 0, 1 * sizeof(int)));
int blocos = dominio / threads;
cout << "Blocos: " << blocos << endl;
cout << "Threads: " << threads << endl;
kernel<<<blocos, threads>>> (d_Vet, d_Flag);
CHECK_ERROR(hipDeviceSynchronize());
hipMemcpy(&(h_vet[0]), d_Vet, dominio * sizeof(int), hipMemcpyDeviceToHost);
for (int k = 0; k < dominio; k++)
cout << h_vet[k] << endl;
cout << endl;
hipMemcpy(&(h_vet[0]), d_Flag, 1 * sizeof(int), hipMemcpyDeviceToHost);
cout << "cada thread[0] soma 1: " << h_vet[0] << endl;
hipFree(d_Vet);
hipFree(d_Flag);
return EXIT_SUCCESS;
} | .text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp2:
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
.Ltmp3:
# %bb.2:
testl %eax, %eax
jne .LBB1_3
# %bb.14:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $31, %rdi
ja .LBB1_16
# %bb.15:
movl $32, %esi
subq %rdi, %rsi
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZNSt6vectorIiSaIiEE17_M_default_appendEm
.Ltmp25:
jmp .LBB1_19
.LBB1_16:
cmpq $128, %rdx
je .LBB1_19
# %bb.17:
subq $-128, %rax
cmpq %rax, %rcx
je .LBB1_19
# %bb.18:
movq %rax, 24(%rsp)
.LBB1_19: # %_ZNSt6vectorIiSaIiEE6resizeEm.exit
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
.Ltmp27:
# %bb.20:
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
.Ltmp29:
# %bb.21:
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $128, %esi
callq bzero
movq 8(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $128, %edx
xorl %esi, %esi
callq hipMemset
.Ltmp31:
# %bb.22:
testl %eax, %eax
jne .LBB1_23
# %bb.34:
movq (%rsp), %rdi
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $4, %edx
xorl %esi, %esi
callq hipMemset
.Ltmp53:
# %bb.35:
testl %eax, %eax
jne .LBB1_36
# %bb.47:
.Ltmp75:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp76:
# %bb.48: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60
.Ltmp77:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $8, %esi
callq _ZNSolsEi
.Ltmp78:
# %bb.49:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_98
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_52
# %bb.51:
movzbl 67(%r14), %eax
jmp .LBB1_54
.LBB1_52:
.Ltmp79:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp80:
# %bb.53: # %.noexc93
movq (%r14), %rax
.Ltmp81:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp82:
.LBB1_54: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp83:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp84:
# %bb.55: # %.noexc95
.Ltmp85:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp86:
# %bb.56: # %_ZNSolsEPFRSoS_E.exit62
.Ltmp87:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp88:
# %bb.57: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
.Ltmp89:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $4, %esi
callq _ZNSolsEi
.Ltmp90:
# %bb.58:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_98
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
cmpb $0, 56(%r14)
je .LBB1_61
# %bb.60:
movzbl 67(%r14), %eax
jmp .LBB1_63
.LBB1_61:
.Ltmp91:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp92:
# %bb.62: # %.noexc103
movq (%r14), %rax
.Ltmp93:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp94:
.LBB1_63: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i100
.Ltmp95:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp96:
# %bb.64: # %.noexc105
.Ltmp97:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp98:
# %bb.65: # %_ZNSolsEPFRSoS_E.exit66
.Ltmp99:
.cfi_escape 0x2e, 0x00
movabsq $4294967304, %rdi # imm = 0x100000008
movabsq $4294967300, %rdx # imm = 0x100000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp100:
# %bb.66:
testl %eax, %eax
jne .LBB1_69
# %bb.67:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
.Ltmp101:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp102:
# %bb.68: # %.noexc67
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
.Ltmp103:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp104:
.LBB1_69:
.Ltmp105:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp106:
# %bb.70:
testl %eax, %eax
jne .LBB1_71
# %bb.82:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
.Ltmp127:
.cfi_escape 0x2e, 0x00
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp128:
# %bb.83: # %.preheader.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_84: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%r15,4), %esi
.Ltmp129:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp130:
# %bb.85: # in Loop: Header=BB1_84 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_86
# %bb.100: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i120
# in Loop: Header=BB1_84 Depth=1
cmpb $0, 56(%r14)
je .LBB1_102
# %bb.101: # in Loop: Header=BB1_84 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_104
.p2align 4, 0x90
.LBB1_102: # in Loop: Header=BB1_84 Depth=1
.Ltmp131:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp132:
# %bb.103: # %.noexc125
# in Loop: Header=BB1_84 Depth=1
movq (%r14), %rax
.Ltmp133:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp134:
.LBB1_104: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i122
# in Loop: Header=BB1_84 Depth=1
.Ltmp135:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp136:
# %bb.105: # %.noexc127
# in Loop: Header=BB1_84 Depth=1
.Ltmp137:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp138:
# %bb.106: # %_ZNSolsEPFRSoS_E.exit84
# in Loop: Header=BB1_84 Depth=1
incq %r15
cmpq $32, %r15
jne .LBB1_84
# %bb.87:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_98
# %bb.88: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i109
cmpb $0, 56(%rbx)
je .LBB1_90
# %bb.89:
movzbl 67(%rbx), %eax
jmp .LBB1_92
.LBB1_90:
.Ltmp140:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp141:
# %bb.91: # %.noexc114
movq (%rbx), %rax
.Ltmp142:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp143:
.LBB1_92: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i111
.Ltmp144:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp145:
# %bb.93: # %.noexc116
.Ltmp146:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp147:
# %bb.94: # %_ZNSolsEPFRSoS_E.exit82
movq 16(%rsp), %rdi
movq (%rsp), %rsi
.Ltmp148:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp149:
# %bb.95:
.Ltmp150:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp151:
# %bb.96: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit86
movq 16(%rsp), %rax
movl (%rax), %esi
.Ltmp152:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp153:
# %bb.97:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_98
# %bb.110: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i131
cmpb $0, 56(%r14)
je .LBB1_112
# %bb.111:
movzbl 67(%r14), %eax
jmp .LBB1_114
.LBB1_112:
.Ltmp154:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp155:
# %bb.113: # %.noexc136
movq (%r14), %rax
.Ltmp156:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp157:
.LBB1_114: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i133
.Ltmp158:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp159:
# %bb.115: # %.noexc138
.Ltmp160:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp161:
# %bb.116: # %_ZNSolsEPFRSoS_E.exit88
movq 8(%rsp), %rdi
.Ltmp162:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp163:
# %bb.117:
movq (%rsp), %rdi
.Ltmp164:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp165:
# %bb.118:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_120
# %bb.119:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_120: # %_ZNSt6vectorIiSaIiEED2Ev.exit
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_86:
.cfi_def_cfa_offset 160
.Ltmp166:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp167:
# %bb.99: # %.noexc124
.LBB1_98: # %.invoke
.Ltmp169:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp170:
# %bb.109: # %.cont
.LBB1_3:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp5:
# %bb.4: # %_ZNSolsEPFRSoS_E.exit
.Ltmp6:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30
.Ltmp8:
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
.Ltmp9:
# %bb.6:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp11:
# %bb.7:
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.Ltmp13:
# %bb.8:
.Ltmp14:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit31
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $112, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit32
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $10, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp19:
# %bb.11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit33
.Ltmp20:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $56, %esi
callq _ZNSolsEi
.Ltmp21:
# %bb.12:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp23:
# %bb.13: # %_ZNSolsEPFRSoS_E.exit34
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq exit
.LBB1_23:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp33:
# %bb.24: # %_ZNSolsEPFRSoS_E.exit36
.Ltmp34:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp35:
# %bb.25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit38
movq 8(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl $128, %edx
xorl %esi, %esi
callq hipMemset
.Ltmp37:
# %bb.26:
.Ltmp38:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp39:
# %bb.27:
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.Ltmp41:
# %bb.28:
.Ltmp42:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit40
.Ltmp44:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $112, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp45:
# %bb.30: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit42
.Ltmp46:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $10, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp47:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
.Ltmp48:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $66, %esi
callq _ZNSolsEi
.Ltmp49:
# %bb.32:
.Ltmp50:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp51:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit46
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq exit
.LBB1_36:
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp55:
# %bb.37: # %_ZNSolsEPFRSoS_E.exit48
.Ltmp56:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit50
movq (%rsp), %rdi
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $4, %edx
xorl %esi, %esi
callq hipMemset
.Ltmp59:
# %bb.39:
.Ltmp60:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp61:
# %bb.40:
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.Ltmp63:
# %bb.41:
.Ltmp64:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp65:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit52
.Ltmp66:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $112, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp67:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit54
.Ltmp68:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $10, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp69:
# %bb.44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56
.Ltmp70:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $67, %esi
callq _ZNSolsEi
.Ltmp71:
# %bb.45:
.Ltmp72:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp73:
# %bb.46: # %_ZNSolsEPFRSoS_E.exit58
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq exit
.LBB1_71:
.Ltmp107:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp108:
# %bb.72: # %_ZNSolsEPFRSoS_E.exit70
.Ltmp109:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp110:
# %bb.73: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit72
.Ltmp111:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp112:
# %bb.74:
.Ltmp113:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp114:
# %bb.75:
.Ltmp115:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.Ltmp116:
# %bb.76:
.Ltmp117:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp118:
# %bb.77: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit74
.Ltmp119:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $112, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp120:
# %bb.78: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit76
.Ltmp121:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $10, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp122:
# %bb.79: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit78
.Ltmp123:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $78, %esi
callq _ZNSolsEi
.Ltmp124:
# %bb.80:
.Ltmp125:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp126:
# %bb.81: # %_ZNSolsEPFRSoS_E.exit80
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq exit
.LBB1_121:
.Ltmp74:
jmp .LBB1_122
.LBB1_125:
.Ltmp171:
jmp .LBB1_122
.LBB1_108: # %.loopexit.split-lp
.Ltmp168:
jmp .LBB1_122
.LBB1_107: # %.loopexit
.Ltmp139:
.LBB1_122:
movq %rax, %rbx
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_124
# %bb.123:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_124: # %_ZNSt6vectorIiSaIiEED2Ev.exit90
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp53-.Ltmp0 # Call between .Ltmp0 and .Ltmp53
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp128-.Ltmp75 # Call between .Ltmp75 and .Ltmp128
.uleb128 .Ltmp171-.Lfunc_begin0 # jumps to .Ltmp171
.byte 0 # On action: cleanup
.uleb128 .Ltmp129-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp138-.Ltmp129 # Call between .Ltmp129 and .Ltmp138
.uleb128 .Ltmp139-.Lfunc_begin0 # jumps to .Ltmp139
.byte 0 # On action: cleanup
.uleb128 .Ltmp140-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp165-.Ltmp140 # Call between .Ltmp140 and .Ltmp165
.uleb128 .Ltmp171-.Lfunc_begin0 # jumps to .Ltmp171
.byte 0 # On action: cleanup
.uleb128 .Ltmp166-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp167-.Ltmp166 # Call between .Ltmp166 and .Ltmp167
.uleb128 .Ltmp168-.Lfunc_begin0 # jumps to .Ltmp168
.byte 0 # On action: cleanup
.uleb128 .Ltmp169-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp170-.Ltmp169 # Call between .Ltmp169 and .Ltmp170
.uleb128 .Ltmp171-.Lfunc_begin0 # jumps to .Ltmp171
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp73-.Ltmp4 # Call between .Ltmp4 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp107-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp126-.Ltmp107 # Call between .Ltmp107 and .Ltmp126
.uleb128 .Ltmp171-.Lfunc_begin0 # jumps to .Ltmp171
.byte 0 # On action: cleanup
.uleb128 .Ltmp126-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp126 # Call between .Ltmp126 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorIiSaIiEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_default_appendEm,comdat
.weak _ZNSt6vectorIiSaIiEE17_M_default_appendEm # -- Begin function _ZNSt6vectorIiSaIiEE17_M_default_appendEm
.p2align 4, 0x90
.type _ZNSt6vectorIiSaIiEE17_M_default_appendEm,@function
_ZNSt6vectorIiSaIiEE17_M_default_appendEm: # @_ZNSt6vectorIiSaIiEE17_M_default_appendEm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testq %rsi, %rsi
je .LBB2_16
# %bb.1:
movq %rsi, %r14
movq %rdi, %rbx
movq 8(%rdi), %r12
movq 16(%rdi), %rax
subq %r12, %rax
sarq $2, %rax
cmpq %rsi, %rax
jae .LBB2_2
# %bb.5:
movabsq $2305843009213693951, %rax # imm = 0x1FFFFFFFFFFFFFFF
movq (%rbx), %rcx
movq %rcx, 16(%rsp) # 8-byte Spill
subq %rcx, %r12
movq %r12, %r15
sarq $2, %r15
movq %r15, %rcx
xorq %rax, %rcx
cmpq %r14, %rcx
jb .LBB2_17
# %bb.6: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit
cmpq %r14, %r15
movq %r14, %rcx
cmovaq %r15, %rcx
leaq (%rcx,%r15), %rbp
cmpq %rax, %rbp
cmovaeq %rax, %rbp
addq %r15, %rcx
cmovbq %rax, %rbp
testq %rbp, %rbp
je .LBB2_7
# %bb.8:
leaq (,%rbp,4), %rdi
callq _Znwm
movq %rax, %r13
jmp .LBB2_9
.LBB2_2:
movl $0, (%r12)
leaq 4(%r12), %rdi
cmpq $1, %r14
je .LBB2_4
# %bb.3: # %_ZSt6fill_nIPimiET_S1_T0_RKT1_.exit.loopexit.i.i.i
leaq -4(,%r14,4), %rdx
xorl %esi, %esi
callq memset@PLT
leaq (%r12,%r14,4), %rdi
.LBB2_4: # %_ZSt27__uninitialized_default_n_aIPimiET_S1_T0_RSaIT1_E.exit
movq %rdi, 8(%rbx)
jmp .LBB2_16
.LBB2_7:
xorl %r13d, %r13d
.LBB2_9: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit
leaq (,%r15,4), %rax
addq %r13, %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl $0, (%r13,%r15,4)
cmpq $1, %r14
je .LBB2_11
# %bb.10: # %_ZSt6fill_nIPimiET_S1_T0_RKT1_.exit.loopexit.i.i.i30
movq 8(%rsp), %rax # 8-byte Reload
leaq 4(%rax), %rdi
leaq -4(,%r14,4), %rdx
xorl %esi, %esi
callq memset@PLT
.LBB2_11: # %_ZSt27__uninitialized_default_n_aIPimiET_S1_T0_RSaIT1_E.exit32
testq %r12, %r12
movq 16(%rsp), %r15 # 8-byte Reload
jle .LBB2_13
# %bb.12:
movq %r13, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB2_13: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit
testq %r15, %r15
je .LBB2_15
# %bb.14:
movq %r15, %rdi
callq _ZdlPv
.LBB2_15: # %_ZNSt12_Vector_baseIiSaIiEE13_M_deallocateEPim.exit35
movq %r13, (%rbx)
movq 8(%rsp), %rax # 8-byte Reload
leaq (%rax,%r14,4), %rax
movq %rax, 8(%rbx)
leaq (,%rbp,4), %rax
addq %r13, %rax
movq %rax, 16(%rbx)
.LBB2_16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 80
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _ZNSt6vectorIiSaIiEE17_M_default_appendEm, .Lfunc_end2-_ZNSt6vectorIiSaIiEE17_M_default_appendEm
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nOperacao atomica\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA ERRO: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " in file: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/marzam/HPC-Aula/main/exemplos/cuda/05-Atomic/atomic.hip"
.size .L.str.3, 113
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " in line: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Blocos: "
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Threads: "
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "cada thread[0] soma 1: "
.size .L.str.7, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "vector::_M_default_append"
.size .L.str.8, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fe20003f05270 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0203 */
/*0070*/ IADD3 R5, R2.reuse, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x040fe20007ffe0ff */
/*0080*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0007 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x001fe200078e00ff */
/*00c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*00e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[1:2], v4, off
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
// Gklee does not detect BC, Gkleep does detect.
// Gkleep detects oob access, Gklee does not.
#define N 128
__device__ int p(int n)
{
if(n < 0)
n = -1 * n;
if(n == 0 || n == 1)
return 0;
for(int i = 2; i*i<=n;i++)
if(n%i == 0)
return 0;
return 1;
}
__global__ void compact(int* g_in, int* g_out)
{
volatile __shared__ int data[N];
volatile __shared__ int out[N];
volatile __shared__ int idx[N];
volatile __shared__ int flag[N];
unsigned int offset, d, left, right, temp;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Copy input data to shared data
data[tid] = g_in[tid];
out[tid] = 0;
idx[tid] = 0;
__syncthreads();
flag[tid] = p(data[tid]);
__syncthreads();
if(tid < N/2){
idx[2*tid] = flag[2*tid];
idx[2*tid+1] = flag[2*tid+1];
}
// upsweep
offset = 1;
for(d = N/2; d > 0; d /= 2) {
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
idx[right] += idx[left];
}
offset *= 2;
}
// Downsweep
if(tid == 0)
idx[N-1] = 0;
for( d = 1; d < N; d *= 2) {
offset /= 2;
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
temp = idx[left];
idx[left] = idx[right];
idx[right] += temp;
}
}
__syncthreads();
if(tid < N && flag[tid] == 1)
out[idx[tid]] = data[tid];
__syncthreads();
if(tid < N)
g_out[tid] = out[tid];
}
int main()
{
int* in = (int*) malloc(N*sizeof(int));
for(int i = 0; i < N; i++)
in[i] = i;
int* din, *dout;
cudaMalloc((void**) &din, N*sizeof(int));
cudaMalloc((void**) &dout, N*sizeof(int));
cudaMemcpy(din, in, N*sizeof(int), cudaMemcpyHostToDevice);
compact<<<1,N>>>(din, dout);
cudaMemcpy(in, dout, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); cudaFree(din); cudaFree(dout);
} | code for sm_80
Function : _Z7compactPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00b0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x004fe80000004800 */
/*00c0*/ STS [R0.X4+0x200], RZ ; /* 0x000200ff00007388 */
/* 0x000fe80000004800 */
/*00d0*/ STS [R0.X4+0x400], RZ ; /* 0x000400ff00007388 */
/* 0x000fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e240000004800 */
/*0100*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x001fc80000000000 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fda0003f06070 */
/*0120*/ @!P0 BRA 0x310 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.AND P0, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f06270 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fd800078e00ff */
/*0150*/ @!P0 BRA 0x310 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0160*/ IABS R9, R2 ; /* 0x0000000200097213 */
/* 0x000fe20000000000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fc800078e00ff */
/*0180*/ I2F.U32.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209000 */
/*0190*/ ISETP.NE.U32.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25070 */
/*01a0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01b0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*01f0*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0200*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0240*/ IMAD R5, R2, R5, R9 ; /* 0x0000000502057224 */
/* 0x000fca00078e0209 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06070 */
/*0260*/ @P0 IADD3 R5, R5, -R2, RZ ; /* 0x8000000205050210 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06070 */
/*0280*/ @P0 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a02 */
/*0290*/ @!P1 LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff059212 */
/* 0x000fc800078e33ff */
/*02a0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02b0*/ @!P0 BRA 0x310 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fca0007ffe0ff */
/*02d0*/ IMAD R4, R2, R2, RZ ; /* 0x0000000202047224 */
/* 0x000fca00078e02ff */
/*02e0*/ ISETP.GT.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fda0003f04270 */
/*02f0*/ @!P0 BRA 0x180 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ STS [R0.X4+0x600], R7 ; /* 0x0006000700007388 */
/* 0x000fe20000004800 */
/*0330*/ ISETP.GE.AND P1, PT, R0.reuse, 0x40, PT ; /* 0x000000400000780c */
/* 0x040fe20003f26270 */
/*0340*/ BSSY B0, 0xa40 ; /* 0x000006f000007945 */
/* 0x000fe40003800000 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x040fe40003f04070 */
/*0370*/ ISETP.GT.U32.AND P6, PT, R0.reuse, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x040fe40003fc4070 */
/*0380*/ ISETP.GT.U32.AND P5, PT, R0.reuse, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x040fe40003fa4070 */
/*0390*/ ISETP.GT.U32.AND P4, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fc40003f84070 */
/*03a0*/ ISETP.GT.U32.AND P3, PT, R0.reuse, 0x3, PT ; /* 0x000000030000780c */
/* 0x040fe40003f64070 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f44070 */
/*03c0*/ @!P1 LDS R5, [R0.X8+0x600] ; /* 0x0006000000059984 */
/* 0x000e280000008800 */
/*03d0*/ @!P1 STS [R0.X8+0x400], R5 ; /* 0x0004000500009388 */
/* 0x001fe80000008800 */
/*03e0*/ @!P1 LDS R9, [R0.X8+0x604] ; /* 0x0006040000099984 */
/* 0x000e280000008800 */
/*03f0*/ @!P1 STS [R0.X8+0x404], R9 ; /* 0x0004040900009388 */
/* 0x001fe80000008800 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0410*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f25270 */
/*0420*/ @!P0 LDS R2, [R0.X8+0x400] ; /* 0x0004000000028984 */
/* 0x000fe80000008800 */
/*0430*/ @!P0 LDS R11, [R0.X8+0x404] ; /* 0x00040400000b8984 */
/* 0x000e240000008800 */
/*0440*/ @!P0 IMAD.IADD R11, R2, 0x1, R11 ; /* 0x00000001020b8824 */
/* 0x001fca00078e020b */
/*0450*/ @!P0 STS [R0.X8+0x404], R11 ; /* 0x0004040b00008388 */
/* 0x000fe80000008800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ @!P6 LDS R2, [R0.X16+0x404] ; /* 0x000404000002e984 */
/* 0x000fe8000000c800 */
/*0480*/ @!P6 LDS R5, [R0.X16+0x40c] ; /* 0x00040c000005e984 */
/* 0x000e24000000c800 */
/*0490*/ @!P6 IMAD.IADD R5, R2, 0x1, R5 ; /* 0x000000010205e824 */
/* 0x001fe200078e0205 */
/*04a0*/ LEA R2, R0, 0x10, 0x5 ; /* 0x0000001000027811 */
/* 0x000fc800078e28ff */
/*04b0*/ @!P6 STS [R0.X16+0x40c], R5 ; /* 0x00040c050000e388 */
/* 0x0001e8000000c800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ LEA R5, R0, 0x40, 0x7 ; /* 0x0000004000057811 */
/* 0x001fca00078e38ff */
/*04e0*/ @!P5 LDS R4, [R2+0x3fc] ; /* 0x0003fc000204d984 */
/* 0x000fe80000000800 */
/*04f0*/ @!P5 LDS R7, [R2+0x40c] ; /* 0x00040c000207d984 */
/* 0x000e240000000800 */
/*0500*/ @!P5 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407d824 */
/* 0x001fe200078e0207 */
/*0510*/ LEA R4, R0, 0x20, 0x6 ; /* 0x0000002000047811 */
/* 0x000fc800078e30ff */
/*0520*/ @!P5 STS [R2+0x40c], R7 ; /* 0x00040c070200d388 */
/* 0x0001e80000000800 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ LEA R7, R0, 0x80, 0x8 ; /* 0x0000008000077811 */
/* 0x001fca00078e40ff */
/*0550*/ @!P4 LDS R6, [R4+0x3fc] ; /* 0x0003fc000406c984 */
/* 0x000fe80000000800 */
/*0560*/ @!P4 LDS R9, [R4+0x41c] ; /* 0x00041c000409c984 */
/* 0x000e240000000800 */
/*0570*/ @!P4 IADD3 R9, R6, R9, RZ ; /* 0x000000090609c210 */
/* 0x001fca0007ffe0ff */
/*0580*/ @!P4 STS [R4+0x41c], R9 ; /* 0x00041c090400c388 */
/* 0x0001e80000000800 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05a0*/ LEA R9, R0, 0x100, 0x9 ; /* 0x0000010000097811 */
/* 0x001fca00078e48ff */
/*05b0*/ @!P3 LDS R6, [R5+0x3fc] ; /* 0x0003fc000506b984 */
/* 0x000fe80000000800 */
/*05c0*/ @!P3 LDS R11, [R5+0x43c] ; /* 0x00043c00050bb984 */
/* 0x000e240000000800 */
/*05d0*/ @!P3 IMAD.IADD R6, R6, 0x1, R11 ; /* 0x000000010606b824 */
/* 0x001fca00078e020b */
/*05e0*/ @!P3 STS [R5+0x43c], R6 ; /* 0x00043c060500b388 */
/* 0x000fe80000000800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0600*/ @!P2 LDS R8, [R7+0x3fc] ; /* 0x0003fc000708a984 */
/* 0x000fe80000000800 */
/*0610*/ @!P2 LDS R11, [R7+0x47c] ; /* 0x00047c00070ba984 */
/* 0x000e240000000800 */
/*0620*/ @!P2 IMAD.IADD R8, R8, 0x1, R11 ; /* 0x000000010808a824 */
/* 0x001fca00078e020b */
/*0630*/ @!P2 STS [R7+0x47c], R8 ; /* 0x00047c080700a388 */
/* 0x000fe80000000800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ @!P1 LDS R10, [R9+0x3fc] ; /* 0x0003fc00090a9984 */
/* 0x000fe80000000800 */
/*0660*/ @!P1 LDS R11, [R9+0x4fc] ; /* 0x0004fc00090b9984 */
/* 0x000e240000000800 */
/*0670*/ @!P1 IMAD.IADD R10, R10, 0x1, R11 ; /* 0x000000010a0a9824 */
/* 0x001fca00078e020b */
/*0680*/ @!P1 STS [R9+0x4fc], R10 ; /* 0x0004fc0a09009388 */
/* 0x000fe80000000800 */
/*0690*/ @!P1 STS [0x5fc], RZ ; /* 0x0005fcffff009388 */
/* 0x000fe80000000800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @!P1 LDS R6, [R9+0x3fc] ; /* 0x0003fc0009069984 */
/* 0x000fe80000000800 */
/*06c0*/ @!P1 LDS R12, [R9+0x4fc] ; /* 0x0004fc00090c9984 */
/* 0x000e280000000800 */
/*06d0*/ @!P1 STS [R9+0x3fc], R12 ; /* 0x0003fc0c09009388 */
/* 0x001fe80000000800 */
/*06e0*/ @!P1 LDS R11, [R9+0x4fc] ; /* 0x0004fc00090b9984 */
/* 0x000e240000000800 */
/*06f0*/ @!P1 IMAD.IADD R6, R6, 0x1, R11 ; /* 0x0000000106069824 */
/* 0x001fca00078e020b */
/*0700*/ @!P1 STS [R9+0x4fc], R6 ; /* 0x0004fc0609009388 */
/* 0x000fe80000000800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ ISETP.GT.AND P1, PT, R0, 0x7f, PT ; /* 0x0000007f0000780c */
/* 0x000fca0003f24270 */
/*0730*/ @!P2 LDS R8, [R7+0x3fc] ; /* 0x0003fc000708a984 */
/* 0x000fe80000000800 */
/*0740*/ @!P2 LDS R10, [R7+0x47c] ; /* 0x00047c00070aa984 */
/* 0x000e280000000800 */
/*0750*/ @!P2 STS [R7+0x3fc], R10 ; /* 0x0003fc0a0700a388 */
/* 0x001fe80000000800 */
/*0760*/ @!P2 LDS R11, [R7+0x47c] ; /* 0x00047c00070ba984 */
/* 0x000e240000000800 */
/*0770*/ @!P2 IMAD.IADD R8, R8, 0x1, R11 ; /* 0x000000010808a824 */
/* 0x001fca00078e020b */
/*0780*/ @!P2 STS [R7+0x47c], R8 ; /* 0x00047c080700a388 */
/* 0x000fe80000000800 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07a0*/ @!P3 LDS R11, [R5+0x3fc] ; /* 0x0003fc00050bb984 */
/* 0x000fe80000000800 */
/*07b0*/ @!P3 LDS R12, [R5+0x43c] ; /* 0x00043c00050cb984 */
/* 0x000e280000000800 */
/*07c0*/ @!P3 STS [R5+0x3fc], R12 ; /* 0x0003fc0c0500b388 */
/* 0x001fe80000000800 */
/*07d0*/ @!P3 LDS R6, [R5+0x43c] ; /* 0x00043c000506b984 */
/* 0x000e240000000800 */
/*07e0*/ @!P3 IADD3 R6, R11, R6, RZ ; /* 0x000000060b06b210 */
/* 0x001fca0007ffe0ff */
/*07f0*/ @!P3 STS [R5+0x43c], R6 ; /* 0x00043c060500b388 */
/* 0x000fe80000000800 */
/*0800*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0810*/ @!P4 LDS R9, [R4+0x3fc] ; /* 0x0003fc000409c984 */
/* 0x000fe80000000800 */
/*0820*/ @!P4 LDS R11, [R4+0x41c] ; /* 0x00041c00040bc984 */
/* 0x000e280000000800 */
/*0830*/ @!P4 STS [R4+0x3fc], R11 ; /* 0x0003fc0b0400c388 */
/* 0x001fe80000000800 */
/*0840*/ @!P4 LDS R8, [R4+0x41c] ; /* 0x00041c000408c984 */
/* 0x000e240000000800 */
/*0850*/ @!P4 IMAD.IADD R9, R9, 0x1, R8 ; /* 0x000000010909c824 */
/* 0x001fca00078e0208 */
/*0860*/ @!P4 STS [R4+0x41c], R9 ; /* 0x00041c090400c388 */
/* 0x000fe80000000800 */
/*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0880*/ @!P5 LDS R7, [R2+0x3fc] ; /* 0x0003fc000207d984 */
/* 0x000fe80000000800 */
/*0890*/ @!P5 LDS R13, [R2+0x40c] ; /* 0x00040c00020dd984 */
/* 0x000e280000000800 */
/*08a0*/ @!P5 STS [R2+0x3fc], R13 ; /* 0x0003fc0d0200d388 */
/* 0x001fe80000000800 */
/*08b0*/ @!P5 LDS R6, [R2+0x40c] ; /* 0x00040c000206d984 */
/* 0x000e240000000800 */
/*08c0*/ @!P5 IMAD.IADD R7, R7, 0x1, R6 ; /* 0x000000010707d824 */
/* 0x001fca00078e0206 */
/*08d0*/ @!P5 STS [R2+0x40c], R7 ; /* 0x00040c070200d388 */
/* 0x000fe80000000800 */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ @!P6 LDS R5, [R0.X16+0x404] ; /* 0x000404000005e984 */
/* 0x000fe8000000c800 */
/*0900*/ @!P6 LDS R11, [R0.X16+0x40c] ; /* 0x00040c00000be984 */
/* 0x000e28000000c800 */
/*0910*/ @!P6 STS [R0.X16+0x404], R11 ; /* 0x0004040b0000e388 */
/* 0x001fe8000000c800 */
/*0920*/ @!P6 LDS R4, [R0.X16+0x40c] ; /* 0x00040c000004e984 */
/* 0x000e24000000c800 */
/*0930*/ @!P6 IMAD.IADD R5, R5, 0x1, R4 ; /* 0x000000010505e824 */
/* 0x001fca00078e0204 */
/*0940*/ @!P6 STS [R0.X16+0x40c], R5 ; /* 0x00040c050000e388 */
/* 0x000fe8000000c800 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0960*/ @!P0 LDS R4, [R0.X8+0x400] ; /* 0x0004000000048984 */
/* 0x000fe80000008800 */
/*0970*/ @!P0 LDS R9, [R0.X8+0x404] ; /* 0x0004040000098984 */
/* 0x000e280000008800 */
/*0980*/ @!P0 STS [R0.X8+0x400], R9 ; /* 0x0004000900008388 */
/* 0x001fe80000008800 */
/*0990*/ @!P0 LDS R7, [R0.X8+0x404] ; /* 0x0004040000078984 */
/* 0x000e240000008800 */
/*09a0*/ @!P0 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104078824 */
/* 0x001fca00078e0207 */
/*09b0*/ @!P0 STS [R0.X8+0x404], R7 ; /* 0x0004040700008388 */
/* 0x0001e80000008800 */
/*09c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09d0*/ @P1 BRA 0xa30 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LDS R2, [R0.X4+0x600] ; /* 0x0006000000027984 */
/* 0x001e240000004800 */
/*09f0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x001fda0003f05270 */
/*0a00*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0a10*/ @!P0 LDS R5, [R0.X4+0x400] ; /* 0x0004000000058984 */
/* 0x000e280000004800 */
/*0a20*/ @!P0 STS [R5.X4+0x200], R2 ; /* 0x0002000205008388 */
/* 0x0011e40000004800 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a50*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0a60*/ LDS R5, [R0.X4+0x200] ; /* 0x0002000000057984 */
/* 0x000e220000004800 */
/*0a70*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0a80*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*0a90*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0aa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
// Gklee does not detect BC, Gkleep does detect.
// Gkleep detects oob access, Gklee does not.
#define N 128
__device__ int p(int n)
{
if(n < 0)
n = -1 * n;
if(n == 0 || n == 1)
return 0;
for(int i = 2; i*i<=n;i++)
if(n%i == 0)
return 0;
return 1;
}
__global__ void compact(int* g_in, int* g_out)
{
volatile __shared__ int data[N];
volatile __shared__ int out[N];
volatile __shared__ int idx[N];
volatile __shared__ int flag[N];
unsigned int offset, d, left, right, temp;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Copy input data to shared data
data[tid] = g_in[tid];
out[tid] = 0;
idx[tid] = 0;
__syncthreads();
flag[tid] = p(data[tid]);
__syncthreads();
if(tid < N/2){
idx[2*tid] = flag[2*tid];
idx[2*tid+1] = flag[2*tid+1];
}
// upsweep
offset = 1;
for(d = N/2; d > 0; d /= 2) {
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
idx[right] += idx[left];
}
offset *= 2;
}
// Downsweep
if(tid == 0)
idx[N-1] = 0;
for( d = 1; d < N; d *= 2) {
offset /= 2;
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
temp = idx[left];
idx[left] = idx[right];
idx[right] += temp;
}
}
__syncthreads();
if(tid < N && flag[tid] == 1)
out[idx[tid]] = data[tid];
__syncthreads();
if(tid < N)
g_out[tid] = out[tid];
}
int main()
{
int* in = (int*) malloc(N*sizeof(int));
for(int i = 0; i < N; i++)
in[i] = i;
int* din, *dout;
cudaMalloc((void**) &din, N*sizeof(int));
cudaMalloc((void**) &dout, N*sizeof(int));
cudaMemcpy(din, in, N*sizeof(int), cudaMemcpyHostToDevice);
compact<<<1,N>>>(din, dout);
cudaMemcpy(in, dout, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); cudaFree(din); cudaFree(dout);
} | .file "tmpxft_0011c5e9_00000000-6_prescan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1pi
.type _Z1pi, @function
_Z1pi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1pi, .-_Z1pi
.globl _Z28__device_stub__Z7compactPiS_PiS_
.type _Z28__device_stub__Z7compactPiS_PiS_, @function
_Z28__device_stub__Z7compactPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7compactPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z28__device_stub__Z7compactPiS_PiS_, .-_Z28__device_stub__Z7compactPiS_PiS_
.globl _Z7compactPiS_
.type _Z7compactPiS_, @function
_Z7compactPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7compactPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7compactPiS_, .-_Z7compactPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L14:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $128, %rax
jne .L14
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 512(%rbp), %r13
leaq .LC0(%rip), %r12
.L16:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7compactPiS_PiS_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7compactPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7compactPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
// Gklee does not detect BC, Gkleep does detect.
// Gkleep detects oob access, Gklee does not.
#define N 128
__device__ int p(int n)
{
if(n < 0)
n = -1 * n;
if(n == 0 || n == 1)
return 0;
for(int i = 2; i*i<=n;i++)
if(n%i == 0)
return 0;
return 1;
}
__global__ void compact(int* g_in, int* g_out)
{
volatile __shared__ int data[N];
volatile __shared__ int out[N];
volatile __shared__ int idx[N];
volatile __shared__ int flag[N];
unsigned int offset, d, left, right, temp;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Copy input data to shared data
data[tid] = g_in[tid];
out[tid] = 0;
idx[tid] = 0;
__syncthreads();
flag[tid] = p(data[tid]);
__syncthreads();
if(tid < N/2){
idx[2*tid] = flag[2*tid];
idx[2*tid+1] = flag[2*tid+1];
}
// upsweep
offset = 1;
for(d = N/2; d > 0; d /= 2) {
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
idx[right] += idx[left];
}
offset *= 2;
}
// Downsweep
if(tid == 0)
idx[N-1] = 0;
for( d = 1; d < N; d *= 2) {
offset /= 2;
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
temp = idx[left];
idx[left] = idx[right];
idx[right] += temp;
}
}
__syncthreads();
if(tid < N && flag[tid] == 1)
out[idx[tid]] = data[tid];
__syncthreads();
if(tid < N)
g_out[tid] = out[tid];
}
int main()
{
int* in = (int*) malloc(N*sizeof(int));
for(int i = 0; i < N; i++)
in[i] = i;
int* din, *dout;
cudaMalloc((void**) &din, N*sizeof(int));
cudaMalloc((void**) &dout, N*sizeof(int));
cudaMemcpy(din, in, N*sizeof(int), cudaMemcpyHostToDevice);
compact<<<1,N>>>(din, dout);
cudaMemcpy(in, dout, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); cudaFree(din); cudaFree(dout);
} | #include <hip/hip_runtime.h>
#include <cstdio>
// Gklee does not detect BC, Gkleep does detect.
// Gkleep detects oob access, Gklee does not.
#define N 128
__device__ int p(int n)
{
if(n < 0)
n = -1 * n;
if(n == 0 || n == 1)
return 0;
for(int i = 2; i*i<=n;i++)
if(n%i == 0)
return 0;
return 1;
}
__global__ void compact(int* g_in, int* g_out)
{
volatile __shared__ int data[N];
volatile __shared__ int out[N];
volatile __shared__ int idx[N];
volatile __shared__ int flag[N];
unsigned int offset, d, left, right, temp;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Copy input data to shared data
data[tid] = g_in[tid];
out[tid] = 0;
idx[tid] = 0;
__syncthreads();
flag[tid] = p(data[tid]);
__syncthreads();
if(tid < N/2){
idx[2*tid] = flag[2*tid];
idx[2*tid+1] = flag[2*tid+1];
}
// upsweep
offset = 1;
for(d = N/2; d > 0; d /= 2) {
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
idx[right] += idx[left];
}
offset *= 2;
}
// Downsweep
if(tid == 0)
idx[N-1] = 0;
for( d = 1; d < N; d *= 2) {
offset /= 2;
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
temp = idx[left];
idx[left] = idx[right];
idx[right] += temp;
}
}
__syncthreads();
if(tid < N && flag[tid] == 1)
out[idx[tid]] = data[tid];
__syncthreads();
if(tid < N)
g_out[tid] = out[tid];
}
int main()
{
int* in = (int*) malloc(N*sizeof(int));
for(int i = 0; i < N; i++)
in[i] = i;
int* din, *dout;
hipMalloc((void**) &din, N*sizeof(int));
hipMalloc((void**) &dout, N*sizeof(int));
hipMemcpy(din, in, N*sizeof(int), hipMemcpyHostToDevice);
compact<<<1,N>>>(din, dout);
hipMemcpy(in, dout, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); hipFree(din); hipFree(dout);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
// Gklee does not detect BC, Gkleep does detect.
// Gkleep detects oob access, Gklee does not.
#define N 128
__device__ int p(int n)
{
if(n < 0)
n = -1 * n;
if(n == 0 || n == 1)
return 0;
for(int i = 2; i*i<=n;i++)
if(n%i == 0)
return 0;
return 1;
}
__global__ void compact(int* g_in, int* g_out)
{
volatile __shared__ int data[N];
volatile __shared__ int out[N];
volatile __shared__ int idx[N];
volatile __shared__ int flag[N];
unsigned int offset, d, left, right, temp;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Copy input data to shared data
data[tid] = g_in[tid];
out[tid] = 0;
idx[tid] = 0;
__syncthreads();
flag[tid] = p(data[tid]);
__syncthreads();
if(tid < N/2){
idx[2*tid] = flag[2*tid];
idx[2*tid+1] = flag[2*tid+1];
}
// upsweep
offset = 1;
for(d = N/2; d > 0; d /= 2) {
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
idx[right] += idx[left];
}
offset *= 2;
}
// Downsweep
if(tid == 0)
idx[N-1] = 0;
for( d = 1; d < N; d *= 2) {
offset /= 2;
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
temp = idx[left];
idx[left] = idx[right];
idx[right] += temp;
}
}
__syncthreads();
if(tid < N && flag[tid] == 1)
out[idx[tid]] = data[tid];
__syncthreads();
if(tid < N)
g_out[tid] = out[tid];
}
int main()
{
int* in = (int*) malloc(N*sizeof(int));
for(int i = 0; i < N; i++)
in[i] = i;
int* din, *dout;
hipMalloc((void**) &din, N*sizeof(int));
hipMalloc((void**) &dout, N*sizeof(int));
hipMemcpy(din, in, N*sizeof(int), hipMemcpyHostToDevice);
compact<<<1,N>>>(din, dout);
hipMemcpy(in, dout, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); hipFree(din); hipFree(dout);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7compactPiS_
.globl _Z7compactPiS_
.p2align 8
.type _Z7compactPiS_,@function
_Z7compactPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v11, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b64 s[4:5], src_shared_base
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_lshlrev_b32_e32 v3, 2, v1
v_add_nc_u32_e32 v4, 0x400, v3
v_cmp_ne_u32_e64 s3, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_add_nc_u32_e32 v6, 0x200, v3
v_cndmask_b32_e64 v5, 0, v3, s3
v_cndmask_b32_e32 v7, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, -1, v6
v_cndmask_b32_e64 v8, 0, s5, vcc_lo
v_cndmask_b32_e64 v3, 0, v6, s2
v_cndmask_b32_e64 v4, 0, s5, s2
v_cndmask_b32_e64 v6, 0, s5, s3
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[7:8], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[3:4], v11 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[5:6], v11 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
flat_load_b32 v0, v[7:8] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v9, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v0, v9
v_cmpx_lt_u32_e32 1, v0
s_cbranch_execz .LBB0_8
v_and_b32_e32 v9, 1, v0
v_cmp_lt_u32_e32 vcc_lo, 3, v0
v_cmp_gt_u32_e64 s4, 4, v0
s_mov_b32 s6, 3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 1, v9
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_7
s_mov_b32 s8, -3
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s10
s_or_b32 s7, s2, s7
s_and_not1_b32 s2, s9, exec_lo
s_and_b32 s9, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s2, s9
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_6
.LBB0_4:
s_mul_i32 s2, s6, s6
s_or_b32 s10, s10, exec_lo
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_mov_b32 s11, exec_lo
v_cmpx_le_u32_e64 s2, v0
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v9, s6
s_and_not1_b32 s10, s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x4f7ffffe, v9
v_cvt_u32_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, s8, v9
v_mul_hi_u32 v10, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v9, v10
v_mul_hi_u32 v9, v0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v9, s6
v_sub_nc_u32_e32 v9, v0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v10, s6, v9
v_cmp_le_u32_e64 s2, s6, v9
v_cndmask_b32_e64 v9, v9, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, s8, v9
v_cmp_le_u32_e64 s2, s6, v9
s_add_i32 s8, s8, -1
s_add_i32 s6, s6, 1
v_cndmask_b32_e64 v9, v9, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v9
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s10, s2
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s4, exec_lo
s_and_b32 s4, s9, exec_lo
s_or_b32 s4, s2, s4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
v_cndmask_b32_e64 v11, 0, 1, s4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
v_lshl_add_u32 v0, v1, 2, 0x600
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s4, 64
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v9, 0, v0, vcc_lo
v_cndmask_b32_e64 v10, 0, s3, vcc_lo
s_mov_b32 s3, exec_lo
flat_store_b32 v[9:10], v11 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 64, v1
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v0, 3, v1
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, 0x600, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v11
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
v_add_nc_u32_e32 v13, 0x604, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v0
flat_load_b32 v15, v[11:12] glc dlc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s2, -1, v13
v_cndmask_b32_e32 v11, 0, v0, vcc_lo
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
v_or_b32_e32 v0, 4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, 0, v13, s2
v_cndmask_b32_e64 v14, 0, s7, s2
v_cmp_ne_u32_e32 vcc_lo, -1, v0
s_waitcnt lgkmcnt(0)
flat_store_b32 v[11:12], v15 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v13, v[13:14] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v11, 0, v0, vcc_lo
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[11:12], v13 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v11, 1, v1
s_mov_b32 s5, 1
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v0, 1, v11
v_add_nc_u32_e32 v11, 2, v11
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s2, s4, 1
s_lshl_b32 s5, s5, 1
s_cmp_gt_u32 s4, 1
s_mov_b32 s4, s2
s_cbranch_scc0 .LBB0_14
.LBB0_12:
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v12, s5, v0
v_mul_lo_u32 v13, s5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v12, v12, 2, -4
v_lshl_add_u32 v13, v13, 2, -4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v12
v_cmp_ne_u32_e64 s2, -1, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v14, 0, v13, s2
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
v_cndmask_b32_e64 v15, 0, s3, s2
flat_load_b32 v12, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[14:15] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v12, v13, v12
flat_store_b32 v[14:15], v12 dlc
s_waitcnt_vscnt null, 0x0
s_branch .LBB0_11
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_16
s_mov_b64 s[4:5], src_shared_base
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v11, 0x1fc :: v_dual_mov_b32 v12, s5
v_mov_b32_e32 v0, 0
flat_store_b32 v[11:12], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v11, 1, v1
s_mov_b32 s5, 1
s_movk_i32 s4, 0x80
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v0, 1, v11
v_add_nc_u32_e32 v11, 2, v11
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_18
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s2, s5, 1
s_cmp_lt_u32 s5, 64
s_mov_b32 s5, s2
s_cbranch_scc0 .LBB0_20
.LBB0_18:
s_lshr_b32 s4, s4, 1
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_17
v_mul_lo_u32 v12, s4, v0
v_mul_lo_u32 v13, s4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v12, v12, 2, -4
v_lshl_add_u32 v13, v13, 2, -4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v12
v_cmp_ne_u32_e64 s2, -1, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v14, 0, v13, s2
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
v_cndmask_b32_e64 v15, 0, s3, s2
flat_load_b32 v16, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[14:15] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[12:13], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v12, v[14:15] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v12, v12, v16
flat_store_b32 v[14:15], v12 dlc
s_waitcnt_vscnt null, 0x0
s_branch .LBB0_17
.LBB0_20:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_i32_e32 vcc_lo, 0x80, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_23
flat_load_b32 v0, v[9:10] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e64 s2, 1, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_23
flat_load_b32 v0, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0)
s_mov_b64 s[4:5], src_shared_base
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v5, v5, 2, 0x200
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, -1, v5
v_cndmask_b32_e64 v5, 0, v5, s2
v_cndmask_b32_e64 v6, 0, s5, s2
flat_store_b32 v[5:6], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_25
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_25:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7compactPiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7compactPiS_, .Lfunc_end0-_Z7compactPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7compactPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7compactPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
// Gklee does not detect BC, Gkleep does detect.
// Gkleep detects oob access, Gklee does not.
#define N 128
__device__ int p(int n)
{
if(n < 0)
n = -1 * n;
if(n == 0 || n == 1)
return 0;
for(int i = 2; i*i<=n;i++)
if(n%i == 0)
return 0;
return 1;
}
__global__ void compact(int* g_in, int* g_out)
{
volatile __shared__ int data[N];
volatile __shared__ int out[N];
volatile __shared__ int idx[N];
volatile __shared__ int flag[N];
unsigned int offset, d, left, right, temp;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Copy input data to shared data
data[tid] = g_in[tid];
out[tid] = 0;
idx[tid] = 0;
__syncthreads();
flag[tid] = p(data[tid]);
__syncthreads();
if(tid < N/2){
idx[2*tid] = flag[2*tid];
idx[2*tid+1] = flag[2*tid+1];
}
// upsweep
offset = 1;
for(d = N/2; d > 0; d /= 2) {
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
idx[right] += idx[left];
}
offset *= 2;
}
// Downsweep
if(tid == 0)
idx[N-1] = 0;
for( d = 1; d < N; d *= 2) {
offset /= 2;
__syncthreads();
if(tid < d) {
left = offset * (2 * tid + 1) - 1;
right = offset * (2 * tid + 2) - 1;
temp = idx[left];
idx[left] = idx[right];
idx[right] += temp;
}
}
__syncthreads();
if(tid < N && flag[tid] == 1)
out[idx[tid]] = data[tid];
__syncthreads();
if(tid < N)
g_out[tid] = out[tid];
}
int main()
{
int* in = (int*) malloc(N*sizeof(int));
for(int i = 0; i < N; i++)
in[i] = i;
int* din, *dout;
hipMalloc((void**) &din, N*sizeof(int));
hipMalloc((void**) &dout, N*sizeof(int));
hipMemcpy(din, in, N*sizeof(int), hipMemcpyHostToDevice);
compact<<<1,N>>>(din, dout);
hipMemcpy(in, dout, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); hipFree(din); hipFree(dout);
} | .text
.file "prescan.hip"
.globl _Z22__device_stub__compactPiS_ # -- Begin function _Z22__device_stub__compactPiS_
.p2align 4, 0x90
.type _Z22__device_stub__compactPiS_,@function
_Z22__device_stub__compactPiS_: # @_Z22__device_stub__compactPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7compactPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__compactPiS_, .Lfunc_end0-_Z22__device_stub__compactPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $128, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7compactPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $128, %r14
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7compactPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7compactPiS_,@object # @_Z7compactPiS_
.section .rodata,"a",@progbits
.globl _Z7compactPiS_
.p2align 3, 0x0
_Z7compactPiS_:
.quad _Z22__device_stub__compactPiS_
.size _Z7compactPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7compactPiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__compactPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7compactPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7compactPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00b0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x004fe80000004800 */
/*00c0*/ STS [R0.X4+0x200], RZ ; /* 0x000200ff00007388 */
/* 0x000fe80000004800 */
/*00d0*/ STS [R0.X4+0x400], RZ ; /* 0x000400ff00007388 */
/* 0x000fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e240000004800 */
/*0100*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x001fc80000000000 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fda0003f06070 */
/*0120*/ @!P0 BRA 0x310 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.AND P0, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f06270 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fd800078e00ff */
/*0150*/ @!P0 BRA 0x310 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0160*/ IABS R9, R2 ; /* 0x0000000200097213 */
/* 0x000fe20000000000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fc800078e00ff */
/*0180*/ I2F.U32.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209000 */
/*0190*/ ISETP.NE.U32.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25070 */
/*01a0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01b0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*01f0*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0200*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0240*/ IMAD R5, R2, R5, R9 ; /* 0x0000000502057224 */
/* 0x000fca00078e0209 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06070 */
/*0260*/ @P0 IADD3 R5, R5, -R2, RZ ; /* 0x8000000205050210 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06070 */
/*0280*/ @P0 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a02 */
/*0290*/ @!P1 LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff059212 */
/* 0x000fc800078e33ff */
/*02a0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02b0*/ @!P0 BRA 0x310 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fca0007ffe0ff */
/*02d0*/ IMAD R4, R2, R2, RZ ; /* 0x0000000202047224 */
/* 0x000fca00078e02ff */
/*02e0*/ ISETP.GT.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fda0003f04270 */
/*02f0*/ @!P0 BRA 0x180 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ STS [R0.X4+0x600], R7 ; /* 0x0006000700007388 */
/* 0x000fe20000004800 */
/*0330*/ ISETP.GE.AND P1, PT, R0.reuse, 0x40, PT ; /* 0x000000400000780c */
/* 0x040fe20003f26270 */
/*0340*/ BSSY B0, 0xa40 ; /* 0x000006f000007945 */
/* 0x000fe40003800000 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x040fe40003f04070 */
/*0370*/ ISETP.GT.U32.AND P6, PT, R0.reuse, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x040fe40003fc4070 */
/*0380*/ ISETP.GT.U32.AND P5, PT, R0.reuse, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x040fe40003fa4070 */
/*0390*/ ISETP.GT.U32.AND P4, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fc40003f84070 */
/*03a0*/ ISETP.GT.U32.AND P3, PT, R0.reuse, 0x3, PT ; /* 0x000000030000780c */
/* 0x040fe40003f64070 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f44070 */
/*03c0*/ @!P1 LDS R5, [R0.X8+0x600] ; /* 0x0006000000059984 */
/* 0x000e280000008800 */
/*03d0*/ @!P1 STS [R0.X8+0x400], R5 ; /* 0x0004000500009388 */
/* 0x001fe80000008800 */
/*03e0*/ @!P1 LDS R9, [R0.X8+0x604] ; /* 0x0006040000099984 */
/* 0x000e280000008800 */
/*03f0*/ @!P1 STS [R0.X8+0x404], R9 ; /* 0x0004040900009388 */
/* 0x001fe80000008800 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0410*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f25270 */
/*0420*/ @!P0 LDS R2, [R0.X8+0x400] ; /* 0x0004000000028984 */
/* 0x000fe80000008800 */
/*0430*/ @!P0 LDS R11, [R0.X8+0x404] ; /* 0x00040400000b8984 */
/* 0x000e240000008800 */
/*0440*/ @!P0 IMAD.IADD R11, R2, 0x1, R11 ; /* 0x00000001020b8824 */
/* 0x001fca00078e020b */
/*0450*/ @!P0 STS [R0.X8+0x404], R11 ; /* 0x0004040b00008388 */
/* 0x000fe80000008800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ @!P6 LDS R2, [R0.X16+0x404] ; /* 0x000404000002e984 */
/* 0x000fe8000000c800 */
/*0480*/ @!P6 LDS R5, [R0.X16+0x40c] ; /* 0x00040c000005e984 */
/* 0x000e24000000c800 */
/*0490*/ @!P6 IMAD.IADD R5, R2, 0x1, R5 ; /* 0x000000010205e824 */
/* 0x001fe200078e0205 */
/*04a0*/ LEA R2, R0, 0x10, 0x5 ; /* 0x0000001000027811 */
/* 0x000fc800078e28ff */
/*04b0*/ @!P6 STS [R0.X16+0x40c], R5 ; /* 0x00040c050000e388 */
/* 0x0001e8000000c800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ LEA R5, R0, 0x40, 0x7 ; /* 0x0000004000057811 */
/* 0x001fca00078e38ff */
/*04e0*/ @!P5 LDS R4, [R2+0x3fc] ; /* 0x0003fc000204d984 */
/* 0x000fe80000000800 */
/*04f0*/ @!P5 LDS R7, [R2+0x40c] ; /* 0x00040c000207d984 */
/* 0x000e240000000800 */
/*0500*/ @!P5 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407d824 */
/* 0x001fe200078e0207 */
/*0510*/ LEA R4, R0, 0x20, 0x6 ; /* 0x0000002000047811 */
/* 0x000fc800078e30ff */
/*0520*/ @!P5 STS [R2+0x40c], R7 ; /* 0x00040c070200d388 */
/* 0x0001e80000000800 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ LEA R7, R0, 0x80, 0x8 ; /* 0x0000008000077811 */
/* 0x001fca00078e40ff */
/*0550*/ @!P4 LDS R6, [R4+0x3fc] ; /* 0x0003fc000406c984 */
/* 0x000fe80000000800 */
/*0560*/ @!P4 LDS R9, [R4+0x41c] ; /* 0x00041c000409c984 */
/* 0x000e240000000800 */
/*0570*/ @!P4 IADD3 R9, R6, R9, RZ ; /* 0x000000090609c210 */
/* 0x001fca0007ffe0ff */
/*0580*/ @!P4 STS [R4+0x41c], R9 ; /* 0x00041c090400c388 */
/* 0x0001e80000000800 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05a0*/ LEA R9, R0, 0x100, 0x9 ; /* 0x0000010000097811 */
/* 0x001fca00078e48ff */
/*05b0*/ @!P3 LDS R6, [R5+0x3fc] ; /* 0x0003fc000506b984 */
/* 0x000fe80000000800 */
/*05c0*/ @!P3 LDS R11, [R5+0x43c] ; /* 0x00043c00050bb984 */
/* 0x000e240000000800 */
/*05d0*/ @!P3 IMAD.IADD R6, R6, 0x1, R11 ; /* 0x000000010606b824 */
/* 0x001fca00078e020b */
/*05e0*/ @!P3 STS [R5+0x43c], R6 ; /* 0x00043c060500b388 */
/* 0x000fe80000000800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0600*/ @!P2 LDS R8, [R7+0x3fc] ; /* 0x0003fc000708a984 */
/* 0x000fe80000000800 */
/*0610*/ @!P2 LDS R11, [R7+0x47c] ; /* 0x00047c00070ba984 */
/* 0x000e240000000800 */
/*0620*/ @!P2 IMAD.IADD R8, R8, 0x1, R11 ; /* 0x000000010808a824 */
/* 0x001fca00078e020b */
/*0630*/ @!P2 STS [R7+0x47c], R8 ; /* 0x00047c080700a388 */
/* 0x000fe80000000800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ @!P1 LDS R10, [R9+0x3fc] ; /* 0x0003fc00090a9984 */
/* 0x000fe80000000800 */
/*0660*/ @!P1 LDS R11, [R9+0x4fc] ; /* 0x0004fc00090b9984 */
/* 0x000e240000000800 */
/*0670*/ @!P1 IMAD.IADD R10, R10, 0x1, R11 ; /* 0x000000010a0a9824 */
/* 0x001fca00078e020b */
/*0680*/ @!P1 STS [R9+0x4fc], R10 ; /* 0x0004fc0a09009388 */
/* 0x000fe80000000800 */
/*0690*/ @!P1 STS [0x5fc], RZ ; /* 0x0005fcffff009388 */
/* 0x000fe80000000800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @!P1 LDS R6, [R9+0x3fc] ; /* 0x0003fc0009069984 */
/* 0x000fe80000000800 */
/*06c0*/ @!P1 LDS R12, [R9+0x4fc] ; /* 0x0004fc00090c9984 */
/* 0x000e280000000800 */
/*06d0*/ @!P1 STS [R9+0x3fc], R12 ; /* 0x0003fc0c09009388 */
/* 0x001fe80000000800 */
/*06e0*/ @!P1 LDS R11, [R9+0x4fc] ; /* 0x0004fc00090b9984 */
/* 0x000e240000000800 */
/*06f0*/ @!P1 IMAD.IADD R6, R6, 0x1, R11 ; /* 0x0000000106069824 */
/* 0x001fca00078e020b */
/*0700*/ @!P1 STS [R9+0x4fc], R6 ; /* 0x0004fc0609009388 */
/* 0x000fe80000000800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ ISETP.GT.AND P1, PT, R0, 0x7f, PT ; /* 0x0000007f0000780c */
/* 0x000fca0003f24270 */
/*0730*/ @!P2 LDS R8, [R7+0x3fc] ; /* 0x0003fc000708a984 */
/* 0x000fe80000000800 */
/*0740*/ @!P2 LDS R10, [R7+0x47c] ; /* 0x00047c00070aa984 */
/* 0x000e280000000800 */
/*0750*/ @!P2 STS [R7+0x3fc], R10 ; /* 0x0003fc0a0700a388 */
/* 0x001fe80000000800 */
/*0760*/ @!P2 LDS R11, [R7+0x47c] ; /* 0x00047c00070ba984 */
/* 0x000e240000000800 */
/*0770*/ @!P2 IMAD.IADD R8, R8, 0x1, R11 ; /* 0x000000010808a824 */
/* 0x001fca00078e020b */
/*0780*/ @!P2 STS [R7+0x47c], R8 ; /* 0x00047c080700a388 */
/* 0x000fe80000000800 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07a0*/ @!P3 LDS R11, [R5+0x3fc] ; /* 0x0003fc00050bb984 */
/* 0x000fe80000000800 */
/*07b0*/ @!P3 LDS R12, [R5+0x43c] ; /* 0x00043c00050cb984 */
/* 0x000e280000000800 */
/*07c0*/ @!P3 STS [R5+0x3fc], R12 ; /* 0x0003fc0c0500b388 */
/* 0x001fe80000000800 */
/*07d0*/ @!P3 LDS R6, [R5+0x43c] ; /* 0x00043c000506b984 */
/* 0x000e240000000800 */
/*07e0*/ @!P3 IADD3 R6, R11, R6, RZ ; /* 0x000000060b06b210 */
/* 0x001fca0007ffe0ff */
/*07f0*/ @!P3 STS [R5+0x43c], R6 ; /* 0x00043c060500b388 */
/* 0x000fe80000000800 */
/*0800*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0810*/ @!P4 LDS R9, [R4+0x3fc] ; /* 0x0003fc000409c984 */
/* 0x000fe80000000800 */
/*0820*/ @!P4 LDS R11, [R4+0x41c] ; /* 0x00041c00040bc984 */
/* 0x000e280000000800 */
/*0830*/ @!P4 STS [R4+0x3fc], R11 ; /* 0x0003fc0b0400c388 */
/* 0x001fe80000000800 */
/*0840*/ @!P4 LDS R8, [R4+0x41c] ; /* 0x00041c000408c984 */
/* 0x000e240000000800 */
/*0850*/ @!P4 IMAD.IADD R9, R9, 0x1, R8 ; /* 0x000000010909c824 */
/* 0x001fca00078e0208 */
/*0860*/ @!P4 STS [R4+0x41c], R9 ; /* 0x00041c090400c388 */
/* 0x000fe80000000800 */
/*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0880*/ @!P5 LDS R7, [R2+0x3fc] ; /* 0x0003fc000207d984 */
/* 0x000fe80000000800 */
/*0890*/ @!P5 LDS R13, [R2+0x40c] ; /* 0x00040c00020dd984 */
/* 0x000e280000000800 */
/*08a0*/ @!P5 STS [R2+0x3fc], R13 ; /* 0x0003fc0d0200d388 */
/* 0x001fe80000000800 */
/*08b0*/ @!P5 LDS R6, [R2+0x40c] ; /* 0x00040c000206d984 */
/* 0x000e240000000800 */
/*08c0*/ @!P5 IMAD.IADD R7, R7, 0x1, R6 ; /* 0x000000010707d824 */
/* 0x001fca00078e0206 */
/*08d0*/ @!P5 STS [R2+0x40c], R7 ; /* 0x00040c070200d388 */
/* 0x000fe80000000800 */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ @!P6 LDS R5, [R0.X16+0x404] ; /* 0x000404000005e984 */
/* 0x000fe8000000c800 */
/*0900*/ @!P6 LDS R11, [R0.X16+0x40c] ; /* 0x00040c00000be984 */
/* 0x000e28000000c800 */
/*0910*/ @!P6 STS [R0.X16+0x404], R11 ; /* 0x0004040b0000e388 */
/* 0x001fe8000000c800 */
/*0920*/ @!P6 LDS R4, [R0.X16+0x40c] ; /* 0x00040c000004e984 */
/* 0x000e24000000c800 */
/*0930*/ @!P6 IMAD.IADD R5, R5, 0x1, R4 ; /* 0x000000010505e824 */
/* 0x001fca00078e0204 */
/*0940*/ @!P6 STS [R0.X16+0x40c], R5 ; /* 0x00040c050000e388 */
/* 0x000fe8000000c800 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0960*/ @!P0 LDS R4, [R0.X8+0x400] ; /* 0x0004000000048984 */
/* 0x000fe80000008800 */
/*0970*/ @!P0 LDS R9, [R0.X8+0x404] ; /* 0x0004040000098984 */
/* 0x000e280000008800 */
/*0980*/ @!P0 STS [R0.X8+0x400], R9 ; /* 0x0004000900008388 */
/* 0x001fe80000008800 */
/*0990*/ @!P0 LDS R7, [R0.X8+0x404] ; /* 0x0004040000078984 */
/* 0x000e240000008800 */
/*09a0*/ @!P0 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104078824 */
/* 0x001fca00078e0207 */
/*09b0*/ @!P0 STS [R0.X8+0x404], R7 ; /* 0x0004040700008388 */
/* 0x0001e80000008800 */
/*09c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09d0*/ @P1 BRA 0xa30 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LDS R2, [R0.X4+0x600] ; /* 0x0006000000027984 */
/* 0x001e240000004800 */
/*09f0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x001fda0003f05270 */
/*0a00*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0a10*/ @!P0 LDS R5, [R0.X4+0x400] ; /* 0x0004000000058984 */
/* 0x000e280000004800 */
/*0a20*/ @!P0 STS [R5.X4+0x200], R2 ; /* 0x0002000205008388 */
/* 0x0011e40000004800 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a50*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0a60*/ LDS R5, [R0.X4+0x200] ; /* 0x0002000000057984 */
/* 0x000e220000004800 */
/*0a70*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0a80*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*0a90*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0aa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7compactPiS_
.globl _Z7compactPiS_
.p2align 8
.type _Z7compactPiS_,@function
_Z7compactPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v11, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b64 s[4:5], src_shared_base
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_lshlrev_b32_e32 v3, 2, v1
v_add_nc_u32_e32 v4, 0x400, v3
v_cmp_ne_u32_e64 s3, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_add_nc_u32_e32 v6, 0x200, v3
v_cndmask_b32_e64 v5, 0, v3, s3
v_cndmask_b32_e32 v7, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, -1, v6
v_cndmask_b32_e64 v8, 0, s5, vcc_lo
v_cndmask_b32_e64 v3, 0, v6, s2
v_cndmask_b32_e64 v4, 0, s5, s2
v_cndmask_b32_e64 v6, 0, s5, s3
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[7:8], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[3:4], v11 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[5:6], v11 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
flat_load_b32 v0, v[7:8] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v9, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v0, v9
v_cmpx_lt_u32_e32 1, v0
s_cbranch_execz .LBB0_8
v_and_b32_e32 v9, 1, v0
v_cmp_lt_u32_e32 vcc_lo, 3, v0
v_cmp_gt_u32_e64 s4, 4, v0
s_mov_b32 s6, 3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 1, v9
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_7
s_mov_b32 s8, -3
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s10
s_or_b32 s7, s2, s7
s_and_not1_b32 s2, s9, exec_lo
s_and_b32 s9, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s2, s9
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_6
.LBB0_4:
s_mul_i32 s2, s6, s6
s_or_b32 s10, s10, exec_lo
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_mov_b32 s11, exec_lo
v_cmpx_le_u32_e64 s2, v0
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v9, s6
s_and_not1_b32 s10, s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x4f7ffffe, v9
v_cvt_u32_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, s8, v9
v_mul_hi_u32 v10, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v9, v10
v_mul_hi_u32 v9, v0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v9, s6
v_sub_nc_u32_e32 v9, v0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v10, s6, v9
v_cmp_le_u32_e64 s2, s6, v9
v_cndmask_b32_e64 v9, v9, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, s8, v9
v_cmp_le_u32_e64 s2, s6, v9
s_add_i32 s8, s8, -1
s_add_i32 s6, s6, 1
v_cndmask_b32_e64 v9, v9, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v9
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s10, s2
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s4, exec_lo
s_and_b32 s4, s9, exec_lo
s_or_b32 s4, s2, s4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
v_cndmask_b32_e64 v11, 0, 1, s4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
v_lshl_add_u32 v0, v1, 2, 0x600
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s4, 64
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v9, 0, v0, vcc_lo
v_cndmask_b32_e64 v10, 0, s3, vcc_lo
s_mov_b32 s3, exec_lo
flat_store_b32 v[9:10], v11 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 64, v1
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v0, 3, v1
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, 0x600, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v11
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
v_add_nc_u32_e32 v13, 0x604, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v0
flat_load_b32 v15, v[11:12] glc dlc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s2, -1, v13
v_cndmask_b32_e32 v11, 0, v0, vcc_lo
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
v_or_b32_e32 v0, 4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, 0, v13, s2
v_cndmask_b32_e64 v14, 0, s7, s2
v_cmp_ne_u32_e32 vcc_lo, -1, v0
s_waitcnt lgkmcnt(0)
flat_store_b32 v[11:12], v15 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v13, v[13:14] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v11, 0, v0, vcc_lo
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[11:12], v13 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v11, 1, v1
s_mov_b32 s5, 1
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v0, 1, v11
v_add_nc_u32_e32 v11, 2, v11
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s2, s4, 1
s_lshl_b32 s5, s5, 1
s_cmp_gt_u32 s4, 1
s_mov_b32 s4, s2
s_cbranch_scc0 .LBB0_14
.LBB0_12:
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v12, s5, v0
v_mul_lo_u32 v13, s5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v12, v12, 2, -4
v_lshl_add_u32 v13, v13, 2, -4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v12
v_cmp_ne_u32_e64 s2, -1, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v14, 0, v13, s2
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
v_cndmask_b32_e64 v15, 0, s3, s2
flat_load_b32 v12, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[14:15] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v12, v13, v12
flat_store_b32 v[14:15], v12 dlc
s_waitcnt_vscnt null, 0x0
s_branch .LBB0_11
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_16
s_mov_b64 s[4:5], src_shared_base
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v11, 0x1fc :: v_dual_mov_b32 v12, s5
v_mov_b32_e32 v0, 0
flat_store_b32 v[11:12], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v11, 1, v1
s_mov_b32 s5, 1
s_movk_i32 s4, 0x80
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v0, 1, v11
v_add_nc_u32_e32 v11, 2, v11
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_18
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s2, s5, 1
s_cmp_lt_u32 s5, 64
s_mov_b32 s5, s2
s_cbranch_scc0 .LBB0_20
.LBB0_18:
s_lshr_b32 s4, s4, 1
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_17
v_mul_lo_u32 v12, s4, v0
v_mul_lo_u32 v13, s4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v12, v12, 2, -4
v_lshl_add_u32 v13, v13, 2, -4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v12
v_cmp_ne_u32_e64 s2, -1, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v14, 0, v13, s2
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
v_cndmask_b32_e64 v15, 0, s3, s2
flat_load_b32 v16, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[14:15] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[12:13], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v12, v[14:15] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v12, v12, v16
flat_store_b32 v[14:15], v12 dlc
s_waitcnt_vscnt null, 0x0
s_branch .LBB0_17
.LBB0_20:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_i32_e32 vcc_lo, 0x80, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_23
flat_load_b32 v0, v[9:10] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e64 s2, 1, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_23
flat_load_b32 v0, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0)
s_mov_b64 s[4:5], src_shared_base
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v5, v5, 2, 0x200
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, -1, v5
v_cndmask_b32_e64 v5, 0, v5, s2
v_cndmask_b32_e64 v6, 0, s5, s2
flat_store_b32 v[5:6], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_25
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_25:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7compactPiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7compactPiS_, .Lfunc_end0-_Z7compactPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7compactPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7compactPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011c5e9_00000000-6_prescan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1pi
.type _Z1pi, @function
_Z1pi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1pi, .-_Z1pi
.globl _Z28__device_stub__Z7compactPiS_PiS_
.type _Z28__device_stub__Z7compactPiS_PiS_, @function
_Z28__device_stub__Z7compactPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7compactPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z28__device_stub__Z7compactPiS_PiS_, .-_Z28__device_stub__Z7compactPiS_PiS_
.globl _Z7compactPiS_
.type _Z7compactPiS_, @function
_Z7compactPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7compactPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7compactPiS_, .-_Z7compactPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L14:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $128, %rax
jne .L14
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 512(%rbp), %r13
leaq .LC0(%rip), %r12
.L16:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7compactPiS_PiS_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7compactPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7compactPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prescan.hip"
.globl _Z22__device_stub__compactPiS_ # -- Begin function _Z22__device_stub__compactPiS_
.p2align 4, 0x90
.type _Z22__device_stub__compactPiS_,@function
_Z22__device_stub__compactPiS_: # @_Z22__device_stub__compactPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7compactPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__compactPiS_, .Lfunc_end0-_Z22__device_stub__compactPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $128, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7compactPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $128, %r14
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7compactPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7compactPiS_,@object # @_Z7compactPiS_
.section .rodata,"a",@progbits
.globl _Z7compactPiS_
.p2align 3, 0x0
_Z7compactPiS_:
.quad _Z22__device_stub__compactPiS_
.size _Z7compactPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7compactPiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__compactPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7compactPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdint.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &width, int &height, uchar3 * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P3") != 0) // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
for (int i = 0; i < width * height; i++)
fscanf(f, "%hhu%hhu%hhu", &pixels[i].x, &pixels[i].y, &pixels[i].z);
fclose(f);
}
void writePnm(uchar3 * pixels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "P3\n%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height; i++)
fprintf(f, "%hhu\n%hhu\n%hhu\n", pixels[i].x, pixels[i].y, pixels[i].z);
fclose(f);
}
__global__ void blurImgKernel(uchar3 * inPixels, int width, int height,
float * filter, int filterWidth,
uchar3 * outPixels)
{
// TODO
int row = threadIdx.x + blockIdx.x * blockDim.x;
int col = threadIdx.y + blockIdx.y * blockDim.y;
int half = filterWidth / 2;
if(row < height && col < width){
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
void blurImg(uchar3 * inPixels, int width, int height, float * filter, int filterWidth,
uchar3 * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1, 1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
// TODO
int half = filterWidth / 2;
for(int row = 0; row < height; row += 1) {
for(int col = 0; col < width; col += 1) {
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
}
else // Use device
{
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO
// Allocate device memories
uchar3 *d_inPixels, *d_outPixels;
float *d_filter;
CHECK(cudaMalloc(&d_inPixels, width * height * sizeof(uchar3)));
CHECK(cudaMalloc(&d_outPixels, width * height * sizeof(uchar3)));
CHECK(cudaMalloc(&d_filter, filterWidth * filterWidth * sizeof(float)));
// Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, width * height * sizeof(uchar3), cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_filter, filter, filterWidth * filterWidth * sizeof(float), cudaMemcpyHostToDevice));
// Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((height - 1) / blockSize.x + 1, (width - 1) / blockSize.y + 1);
blurImgKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_filter, filterWidth, d_outPixels);
// Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, width * height * sizeof(uchar3), cudaMemcpyDeviceToHost));
// Free device memories
CHECK(cudaFree(d_inPixels));
CHECK(cudaFree(d_outPixels));
CHECK(cudaFree(d_filter));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uchar3 * a1, uchar3 * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
{
err += abs((int)a1[i].x - (int)a2[i].x);
err += abs((int)a1[i].y - (int)a2[i].y);
err += abs((int)a1[i].z - (int)a2[i].z);
}
err /= (n * 3);
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 4 && argc != 6)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input image file
int width, height;
uchar3 * inPixels;
readPnm(argv[1], width, height, inPixels);
printf("Image size (width x height): %i x %i\n\n", width, height);
// Read correct output image file
int correctWidth, correctHeight;
uchar3 * correctOutPixels;
readPnm(argv[3], correctWidth, correctHeight, correctOutPixels);
if (correctWidth != width || correctHeight != height)
{
printf("The shape of the correct output image is invalid\n");
return EXIT_FAILURE;
}
// Set up a simple filter with blurring effect
int filterWidth = 9;
float * filter = (float *)malloc(filterWidth * filterWidth * sizeof(float));
for (int filterR = 0; filterR < filterWidth; filterR++)
{
for (int filterC = 0; filterC < filterWidth; filterC++)
{
filter[filterR * filterWidth + filterC] = 1. / (filterWidth * filterWidth);
}
}
// Blur input image using host
uchar3 * hostOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
blurImg(inPixels, width, height, filter, filterWidth, hostOutPixels);
// Compute mean absolute error between host result and correct result
float hostErr = computeError(hostOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", hostErr);
// Blur input image using device
uchar3 * deviceOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
dim3 blockSize(32, 32); // Default
if (argc == 6)
{
blockSize.x = atoi(argv[4]);
blockSize.y = atoi(argv[5]);
}
blurImg(inPixels, width, height, filter, filterWidth, deviceOutPixels, true, blockSize);
// Compute mean absolute error between device result and correct result
float deviceErr = computeError(deviceOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", deviceErr);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(hostOutPixels, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(deviceOutPixels, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(correctOutPixels);
free(hostOutPixels);
free(deviceOutPixels);
free(filter);
} | code for sm_80
Function : _Z13blurImgKernelP6uchar3iiPfiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe400078e0205 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fe40000706670 */
/*00a0*/ LEA.HI R2, R2, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0002027a11 */
/* 0x000fd600078f08ff */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*00d0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*00f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R5, -R2, RZ, RZ ; /* 0x000000ff02057210 */
/* 0x000fc80007ffe1ff */
/*0110*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 BRA 0xaf0 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, -R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe20007ffe1ff */
/*0140*/ IMAD.IADD R9, R3.reuse, 0x1, -R2 ; /* 0x0000000103097824 */
/* 0x040fe200078e0a02 */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.SHL.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067824 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R11, R3, R4, RZ ; /* 0x00000004030b7210 */
/* 0x000fe20007ffe0ff */
/*0180*/ UIADD3 UR5, UR6, -0x1, URZ ; /* 0xffffffff06057890 */
/* 0x000fe2000fffe03f */
/*0190*/ IMNMX R10, RZ, R9, !PT ; /* 0x00000009ff0a7217 */
/* 0x000fe20007800200 */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R12, R11, 0x1, RZ ; /* 0x000000010b0c7810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*01d0*/ IMNMX R11, RZ, R11, !PT ; /* 0x0000000bff0b7217 */
/* 0x000fe20007800200 */
/*01e0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ IMNMX R12, RZ, R12, !PT ; /* 0x0000000cff0c7217 */
/* 0x000fc40007800200 */
/*0200*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x000fe40003f06270 */
/*0220*/ ISETP.GE.AND P1, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fe40003f26270 */
/*0230*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x168], PT ; /* 0x00005a000c007a0c */
/* 0x000fe40003f46270 */
/*0240*/ IADD3 R7, -R2, 0x3, RZ ; /* 0x0000000302077810 */
/* 0x000fe40007ffe1ff */
/*0250*/ IADD3 R8, R3, 0x3, RZ ; /* 0x0000000303087810 */
/* 0x000fc40007ffe0ff */
/*0260*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*0270*/ SEL R10, R10, UR5, !P0 ; /* 0x000000050a0a7c07 */
/* 0x000fe4000c000000 */
/*0280*/ SEL R11, R11, UR5, !P1 ; /* 0x000000050b0b7c07 */
/* 0x000fe4000c800000 */
/*0290*/ SEL R12, R12, UR5, !P2 ; /* 0x000000050c0c7c07 */
/* 0x000fe4000d000000 */
/*02a0*/ IADD3 R13, R0, R5, RZ ; /* 0x00000005000d7210 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x3 ; /* 0x00000003ff127424 */
/* 0x000fc600078e00ff */
/*02c0*/ IMNMX R13, RZ, R13, !PT ; /* 0x0000000dff0d7217 */
/* 0x000fc80007800200 */
/*02d0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x16c], PT ; /* 0x00005b000d007a0c */
/* 0x000fc80003f06270 */
/*02e0*/ SEL R13, R13, UR4, !P0 ; /* 0x000000040d0d7c07 */
/* 0x000fca000c000000 */
/*02f0*/ IMAD R17, R13, c[0x0][0x168], R10 ; /* 0x00005a000d117a24 */
/* 0x000fc800078e020a */
/*0300*/ IMAD.WIDE R16, R17, R18, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fe200078e0212 */
/*0310*/ IADD3 R25, R2, R5, RZ ; /* 0x0000000502197210 */
/* 0x000fc80007ffe0ff */
/*0320*/ LDG.E.U8 R22, [R16.64] ; /* 0x0000000810167981 */
/* 0x0000a8000c1e1100 */
/*0330*/ LDG.E.U8 R24, [R16.64+0x1] ; /* 0x0000010810187981 */
/* 0x0000e8000c1e1100 */
/*0340*/ LDG.E.U8 R27, [R16.64+0x2] ; /* 0x00000208101b7981 */
/* 0x000122000c1e1100 */
/*0350*/ IMAD.MOV.U32 R26, RZ, RZ, 0x4 ; /* 0x00000004ff1a7424 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD R25, R25, c[0x0][0x178], RZ ; /* 0x00005e0019197a24 */
/* 0x000fc800078e02ff */
/*0370*/ IMAD.WIDE R14, R25, R26, c[0x0][0x170] ; /* 0x00005c00190e7625 */
/* 0x000fca00078e021a */
/*0380*/ LDG.E R23, [R14.64] ; /* 0x000000080e177981 */
/* 0x000f62000c1e1900 */
/*0390*/ ISETP.NE.AND P1, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f25270 */
/*03a0*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe40003f06270 */
/*03b0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f46070 */
/*03c0*/ MOV R16, R4 ; /* 0x0000000400107202 */
/* 0x001fe20000000f00 */
/*03d0*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x004f700000101000 */
/*03e0*/ I2F.U16 R24, R24 ; /* 0x0000001800187306 */
/* 0x008e300000101000 */
/*03f0*/ I2F.U16 R28, R27 ; /* 0x0000001b001c7306 */
/* 0x010e620000101000 */
/*0400*/ FFMA R21, R22, R23, R21 ; /* 0x0000001716157223 */
/* 0x020fc40000000015 */
/*0410*/ FFMA R20, R23.reuse, R24, R20 ; /* 0x0000001817147223 */
/* 0x041fe40000000014 */
/*0420*/ FFMA R19, R23, R28, R19 ; /* 0x0000001c17137223 */
/* 0x002fe20000000013 */
/*0430*/ @!P1 BRA 0x5d0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD R17, R13, c[0x0][0x168], R11 ; /* 0x00005a000d117a24 */
/* 0x000fe200078e020b */
/*0450*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004080e187981 */
/* 0x000ea6000c1e1900 */
/*0460*/ IMAD.WIDE R16, R17, R18, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fe200078e0212 */
/*0470*/ LDG.E R28, [R14.64+0x8] ; /* 0x000008080e1c7981 */
/* 0x0000e8000c1e1900 */
/*0480*/ LDG.E.U8 R22, [R16.64] ; /* 0x0000000810167981 */
/* 0x000f28000c1e1100 */
/*0490*/ LDG.E.U8 R27, [R16.64+0x1] ; /* 0x00000108101b7981 */
/* 0x000f62000c1e1100 */
/*04a0*/ IMAD R23, R13, c[0x0][0x168], R12 ; /* 0x00005a000d177a24 */
/* 0x000fc600078e020c */
/*04b0*/ LDG.E.U8 R29, [R16.64+0x2] ; /* 0x00000208101d7981 */
/* 0x0002a2000c1e1100 */
/*04c0*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x010eb00000101000 */
/*04d0*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x020f220000101000 */
/*04e0*/ FFMA R21, R22, R24, R21 ; /* 0x0000001816157223 */
/* 0x004fc40000000015 */
/*04f0*/ IMAD.WIDE R22, R23, R18, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fca00078e0212 */
/*0500*/ LDG.E.U8 R17, [R22.64+0x1] ; /* 0x0000010816117981 */
/* 0x002ea2000c1e1100 */
/*0510*/ FFMA R27, R24, R27, R20 ; /* 0x0000001b181b7223 */
/* 0x010fc60000000014 */
/*0520*/ LDG.E.U8 R20, [R22.64] ; /* 0x0000000816147981 */
/* 0x000f28000c1e1100 */
/*0530*/ LDG.E.U8 R15, [R22.64+0x2] ; /* 0x00000208160f7981 */
/* 0x001f62000c1e1100 */
/*0540*/ I2F.U16 R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e220000101000 */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, R7 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0007 */
/*0560*/ FFMA R19, R24, R29, R19 ; /* 0x0000001d18137223 */
/* 0x001fca0000000013 */
/*0570*/ I2F.U16 R14, R17 ; /* 0x00000011000e7306 */
/* 0x004ff00000101000 */
/*0580*/ I2F.U16 R20, R20 ; /* 0x0000001400147306 */
/* 0x010ef00000101000 */
/*0590*/ I2F.U16 R15, R15 ; /* 0x0000000f000f7306 */
/* 0x020e220000101000 */
/*05a0*/ FFMA R21, R20, R28, R21 ; /* 0x0000001c14157223 */
/* 0x008fc40000000015 */
/*05b0*/ FFMA R20, R28.reuse, R14, R27 ; /* 0x0000000e1c147223 */
/* 0x040fe4000000001b */
/*05c0*/ FFMA R19, R28, R15, R19 ; /* 0x0000000f1c137223 */
/* 0x001fc60000000013 */
/*05d0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ @!P2 BRA 0xae0 ; /* 0x000004f00000a947 */
/* 0x000fea0003800000 */
/*05f0*/ IADD3 R15, R25, R2, R16 ; /* 0x00000002190f7210 */
/* 0x000fe40007ffe010 */
/*0600*/ IADD3 R23, R16, -0x1, RZ ; /* 0xffffffff10177810 */
/* 0x000fe40007ffe0ff */
/*0610*/ IADD3 R22, R8, R16, RZ ; /* 0x0000001008167210 */
/* 0x000fe20007ffe0ff */
/*0620*/ IMAD.WIDE R14, R15, R26, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x000fc800078e021a */
/*0630*/ IMAD.MOV.U32 R25, RZ, RZ, R15 ; /* 0x000000ffff197224 */
/* 0x000fe200078e000f */
/*0640*/ MOV R24, R14 ; /* 0x0000000e00187202 */
/* 0x000fe20000000f00 */
/*0650*/ IMAD.IADD R14, R3, 0x1, R16 ; /* 0x00000001030e7824 */
/* 0x000fca00078e0210 */
/*0660*/ IMNMX R14, RZ, R14, !PT ; /* 0x0000000eff0e7217 */
/* 0x000fc80007800200 */
/*0670*/ ISETP.GE.AND P1, PT, R14, c[0x0][0x168], PT ; /* 0x00005a000e007a0c */
/* 0x000fc80003f26270 */
/*0680*/ SEL R14, R14, UR5, !P1 ; /* 0x000000050e0e7c07 */
/* 0x000fca000c800000 */
/*0690*/ IMAD R15, R13, c[0x0][0x168], R14 ; /* 0x00005a000d0f7a24 */
/* 0x000fc800078e020e */
/*06a0*/ IMAD.WIDE R14, R15, R18, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fca00078e0212 */
/*06b0*/ LDG.E.U8 R28, [R14.64] ; /* 0x000000080e1c7981 */
/* 0x0000a8000c1e1100 */
/*06c0*/ LDG.E.U8 R26, [R14.64+0x1] ; /* 0x000001080e1a7981 */
/* 0x0000e8000c1e1100 */
/*06d0*/ LDG.E.U8 R27, [R14.64+0x2] ; /* 0x000002080e1b7981 */
/* 0x000124000c1e1100 */
/*06e0*/ MOV R14, R24 ; /* 0x00000018000e7202 */
/* 0x001fe20000000f00 */
/*06f0*/ IMAD.MOV.U32 R15, RZ, RZ, R25 ; /* 0x000000ffff0f7224 */
/* 0x000fca00078e0019 */
/*0700*/ LDG.E R24, [R14.64] ; /* 0x000000080e187981 */
/* 0x000f62000c1e1900 */
/*0710*/ IADD3 R25, R22, -0x2, RZ ; /* 0xfffffffe16197810 */
/* 0x000fc80007ffe0ff */
/*0720*/ IMNMX R25, RZ, R25, !PT ; /* 0x00000019ff197217 */
/* 0x000fc80007800200 */
/*0730*/ ISETP.GE.AND P1, PT, R25, c[0x0][0x168], PT ; /* 0x00005a0019007a0c */
/* 0x000fc80003f26270 */
/*0740*/ SEL R25, R25, UR5, !P1 ; /* 0x0000000519197c07 */
/* 0x000fca000c800000 */
/*0750*/ IMAD R25, R13, c[0x0][0x168], R25 ; /* 0x00005a000d197a24 */
/* 0x000fe200078e0219 */
/*0760*/ I2F.U16 R16, R28 ; /* 0x0000001c00107306 */
/* 0x004f700000101000 */
/*0770*/ I2F.U16 R17, R26 ; /* 0x0000001a00117306 */
/* 0x008e300000101000 */
/*0780*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x010e620000101000 */
/*0790*/ FFMA R21, R16, R24, R21 ; /* 0x0000001810157223 */
/* 0x020fc40000000015 */
/*07a0*/ FFMA R20, R24, R17, R20 ; /* 0x0000001118147223 */
/* 0x001fe40000000014 */
/*07b0*/ IMAD.WIDE R16, R25, R18, c[0x0][0x160] ; /* 0x0000580019107625 */
/* 0x000fc800078e0212 */
/*07c0*/ FFMA R19, R24, R27, R19 ; /* 0x0000001b18137223 */
/* 0x002fe20000000013 */
/*07d0*/ LDG.E.U8 R26, [R16.64] ; /* 0x00000008101a7981 */
/* 0x0000a8000c1e1100 */
/*07e0*/ LDG.E.U8 R28, [R16.64+0x1] ; /* 0x00000108101c7981 */
/* 0x0000e8000c1e1100 */
/*07f0*/ LDG.E.U8 R25, [R16.64+0x2] ; /* 0x0000020810197981 */
/* 0x000128000c1e1100 */
/*0800*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004080e187981 */
/* 0x000f62000c1e1900 */
/*0810*/ IADD3 R29, R22, -0x1, RZ ; /* 0xffffffff161d7810 */
/* 0x000fc80007ffe0ff */
/*0820*/ IMNMX R29, RZ, R29, !PT ; /* 0x0000001dff1d7217 */
/* 0x000fc80007800200 */
/*0830*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x168], PT ; /* 0x00005a001d007a0c */
/* 0x000fc80003f26270 */
/*0840*/ SEL R29, R29, UR5, !P1 ; /* 0x000000051d1d7c07 */
/* 0x000fca000c800000 */
/*0850*/ IMAD R29, R13, c[0x0][0x168], R29 ; /* 0x00005a000d1d7a24 */
/* 0x000fc800078e021d */
/*0860*/ IMAD.WIDE R16, R29, R18, c[0x0][0x160] ; /* 0x000058001d107625 */
/* 0x001fe200078e0212 */
/*0870*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x004f700000101000 */
/*0880*/ I2F.U16 R27, R28 ; /* 0x0000001c001b7306 */
/* 0x0080700000101000 */
/*0890*/ I2F.U16 R25, R25 ; /* 0x0000001900197306 */
/* 0x010ea20000101000 */
/*08a0*/ FFMA R21, R26, R24, R21 ; /* 0x000000181a157223 */
/* 0x020fe20000000015 */
/*08b0*/ LDG.E.U8 R28, [R16.64+0x2] ; /* 0x00000208101c7981 */
/* 0x0010e8000c1e1100 */
/*08c0*/ LDG.E.U8 R26, [R16.64] ; /* 0x00000008101a7981 */
/* 0x000122000c1e1100 */
/*08d0*/ FFMA R20, R24, R27, R20 ; /* 0x0000001b18147223 */
/* 0x002fc60000000014 */
/*08e0*/ LDG.E.U8 R27, [R16.64+0x1] ; /* 0x00000108101b7981 */
/* 0x000162000c1e1100 */
/*08f0*/ FFMA R19, R24, R25, R19 ; /* 0x0000001918137223 */
/* 0x004fc60000000013 */
/*0900*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008080e187981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMNMX R29, RZ, R22, !PT ; /* 0x00000016ff1d7217 */
/* 0x000fc80007800200 */
/*0920*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x168], PT ; /* 0x00005a001d007a0c */
/* 0x000fc80003f26270 */
/*0930*/ SEL R29, R29, UR5, !P1 ; /* 0x000000051d1d7c07 */
/* 0x000fca000c800000 */
/*0940*/ IMAD R29, R13, c[0x0][0x168], R29 ; /* 0x00005a000d1d7a24 */
/* 0x000fc800078e021d */
/*0950*/ IMAD.WIDE R16, R29, R18, c[0x0][0x160] ; /* 0x000058001d107625 */
/* 0x001fca00078e0212 */
/*0960*/ LDG.E.U8 R29, [R16.64] ; /* 0x00000008101d7981 */
/* 0x000ea2000c1e1100 */
/*0970*/ I2F.U16 R25, R28 ; /* 0x0000001c00197306 */
/* 0x008eb00000101000 */
/*0980*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x010e300000101000 */
/*0990*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x020e620000101000 */
/*09a0*/ FFMA R19, R24, R25, R19 ; /* 0x0000001918137223 */
/* 0x004fc40000000013 */
/*09b0*/ FFMA R21, R26, R24, R21 ; /* 0x000000181a157223 */
/* 0x001fe40000000015 */
/*09c0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ FFMA R20, R24, R27, R20 ; /* 0x0000001b18147223 */
/* 0x002fc60000000014 */
/*09e0*/ LDG.E.U8 R24, [R16.64+0x1] ; /* 0x0000010810187981 */
/* 0x000ee8000c1e1100 */
/*09f0*/ LDG.E.U8 R27, [R16.64+0x2] ; /* 0x00000208101b7981 */
/* 0x000f22000c1e1100 */
/*0a00*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007ffe0ff */
/*0a10*/ I2F.U16 R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000ea60000101000 */
/*0a20*/ ISETP.GE.AND P1, PT, R23, R2, PT ; /* 0x000000021700720c */
/* 0x000fe40003f26270 */
/*0a30*/ IADD3 R28, R22, 0x4, RZ ; /* 0x00000004161c7810 */
/* 0x000fc60007ffe0ff */
/*0a40*/ I2F.U16 R25, R24 ; /* 0x0000001800197306 */
/* 0x0080700000101000 */
/*0a50*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x010ee20000101000 */
/*0a60*/ IADD3 R24, P2, R14, 0x10, RZ ; /* 0x000000100e187810 */
/* 0x001fe20007f5e0ff */
/*0a70*/ FFMA R21, R29, R26, R21 ; /* 0x0000001a1d157223 */
/* 0x004fe20000000015 */
/*0a80*/ IADD3 R14, R22, 0x1, RZ ; /* 0x00000001160e7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.MOV.U32 R22, RZ, RZ, R28 ; /* 0x000000ffff167224 */
/* 0x000fc400078e001c */
/*0aa0*/ FFMA R20, R26.reuse, R25, R20 ; /* 0x000000191a147223 */
/* 0x042fe20000000014 */
/*0ab0*/ IADD3.X R25, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff197210 */
/* 0x000fe200017fe4ff */
/*0ac0*/ FFMA R19, R26, R27, R19 ; /* 0x0000001b1a137223 */
/* 0x008fe20000000013 */
/*0ad0*/ @!P1 BRA 0x660 ; /* 0xfffffb8000009947 */
/* 0x000fea000383ffff */
/*0ae0*/ @!P0 BRA 0x2a0 ; /* 0xfffff7b000008947 */
/* 0x000fea000383ffff */
/*0af0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e22000020f100 */
/*0b00*/ HFMA2.MMA R2, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff027435 */
/* 0x000fe200000001ff */
/*0b10*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fcc00078e0203 */
/*0b20*/ F2I.TRUNC.NTZ R5, R20 ; /* 0x0000001400057305 */
/* 0x000e66000020f100 */
/*0b30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0b40*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000ea2000020f100 */
/*0b50*/ STG.E.U8 [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x001fe8000c101108 */
/*0b60*/ STG.E.U8 [R2.64+0x1], R5 ; /* 0x0000010502007986 */
/* 0x002fe8000c101108 */
/*0b70*/ STG.E.U8 [R2.64+0x2], R19 ; /* 0x0000021302007986 */
/* 0x004fe2000c101108 */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdint.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &width, int &height, uchar3 * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P3") != 0) // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
for (int i = 0; i < width * height; i++)
fscanf(f, "%hhu%hhu%hhu", &pixels[i].x, &pixels[i].y, &pixels[i].z);
fclose(f);
}
void writePnm(uchar3 * pixels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "P3\n%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height; i++)
fprintf(f, "%hhu\n%hhu\n%hhu\n", pixels[i].x, pixels[i].y, pixels[i].z);
fclose(f);
}
__global__ void blurImgKernel(uchar3 * inPixels, int width, int height,
float * filter, int filterWidth,
uchar3 * outPixels)
{
// TODO
int row = threadIdx.x + blockIdx.x * blockDim.x;
int col = threadIdx.y + blockIdx.y * blockDim.y;
int half = filterWidth / 2;
if(row < height && col < width){
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
void blurImg(uchar3 * inPixels, int width, int height, float * filter, int filterWidth,
uchar3 * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1, 1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
// TODO
int half = filterWidth / 2;
for(int row = 0; row < height; row += 1) {
for(int col = 0; col < width; col += 1) {
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
}
else // Use device
{
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO
// Allocate device memories
uchar3 *d_inPixels, *d_outPixels;
float *d_filter;
CHECK(cudaMalloc(&d_inPixels, width * height * sizeof(uchar3)));
CHECK(cudaMalloc(&d_outPixels, width * height * sizeof(uchar3)));
CHECK(cudaMalloc(&d_filter, filterWidth * filterWidth * sizeof(float)));
// Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, width * height * sizeof(uchar3), cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_filter, filter, filterWidth * filterWidth * sizeof(float), cudaMemcpyHostToDevice));
// Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((height - 1) / blockSize.x + 1, (width - 1) / blockSize.y + 1);
blurImgKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_filter, filterWidth, d_outPixels);
// Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, width * height * sizeof(uchar3), cudaMemcpyDeviceToHost));
// Free device memories
CHECK(cudaFree(d_inPixels));
CHECK(cudaFree(d_outPixels));
CHECK(cudaFree(d_filter));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uchar3 * a1, uchar3 * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
{
err += abs((int)a1[i].x - (int)a2[i].x);
err += abs((int)a1[i].y - (int)a2[i].y);
err += abs((int)a1[i].z - (int)a2[i].z);
}
err /= (n * 3);
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 4 && argc != 6)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input image file
int width, height;
uchar3 * inPixels;
readPnm(argv[1], width, height, inPixels);
printf("Image size (width x height): %i x %i\n\n", width, height);
// Read correct output image file
int correctWidth, correctHeight;
uchar3 * correctOutPixels;
readPnm(argv[3], correctWidth, correctHeight, correctOutPixels);
if (correctWidth != width || correctHeight != height)
{
printf("The shape of the correct output image is invalid\n");
return EXIT_FAILURE;
}
// Set up a simple filter with blurring effect
int filterWidth = 9;
float * filter = (float *)malloc(filterWidth * filterWidth * sizeof(float));
for (int filterR = 0; filterR < filterWidth; filterR++)
{
for (int filterC = 0; filterC < filterWidth; filterC++)
{
filter[filterR * filterWidth + filterC] = 1. / (filterWidth * filterWidth);
}
}
// Blur input image using host
uchar3 * hostOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
blurImg(inPixels, width, height, filter, filterWidth, hostOutPixels);
// Compute mean absolute error between host result and correct result
float hostErr = computeError(hostOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", hostErr);
// Blur input image using device
uchar3 * deviceOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
dim3 blockSize(32, 32); // Default
if (argc == 6)
{
blockSize.x = atoi(argv[4]);
blockSize.y = atoi(argv[5]);
}
blurImg(inPixels, width, height, filter, filterWidth, deviceOutPixels, true, blockSize);
// Compute mean absolute error between device result and correct result
float deviceErr = computeError(deviceOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", deviceErr);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(hostOutPixels, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(deviceOutPixels, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(correctOutPixels);
free(hostOutPixels);
free(deviceOutPixels);
free(filter);
} | .file "tmpxft_000f66bb_00000000-6_bt01_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "Cannot read %s\n"
.LC2:
.string "%s"
.LC3:
.string "P3"
.LC4:
.string "%i"
.LC5:
.string "%hhu%hhu%hhu"
.text
.globl _Z7readPnmPcRiS0_RP6uchar3
.type _Z7readPnmPcRiS0_RP6uchar3, @function
_Z7readPnmPcRiS0_RP6uchar3:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L12
movq %rax, %rbp
leaq 5(%rsp), %r15
movq %r15, %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC3(%rip), %rsi
movq %r15, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L13
movq %r12, %rdx
leaq .LC4(%rip), %r15
movq %r15, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r13, %rdx
movq %r15, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rsp, %rdx
movq %r15, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $255, (%rsp)
jg .L14
movl (%r12), %eax
imull 0(%r13), %eax
cltq
leaq (%rax,%rax,2), %rdi
call malloc@PLT
movq %rax, (%r14)
movl (%r12), %eax
imull 0(%r13), %eax
testl %eax, %eax
jle .L7
movl $0, %ebx
leaq .LC5(%rip), %r15
.L8:
leaq (%rbx,%rbx,2), %rdx
addq (%r14), %rdx
leaq 1(%rdx), %rcx
leaq 2(%rdx), %r8
movq %r15, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
movl (%r12), %eax
imull 0(%r13), %eax
cmpl %ebx, %eax
jg .L8
.L7:
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z7readPnmPcRiS0_RP6uchar3, .-_Z7readPnmPcRiS0_RP6uchar3
.section .rodata.str1.1
.LC6:
.string "w"
.LC7:
.string "Cannot write %s\n"
.LC8:
.string "P3\n%i\n%i\n255\n"
.LC9:
.string "%hhu\n%hhu\n%hhu\n"
.text
.globl _Z8writePnmP6uchar3iiPc
.type _Z8writePnmP6uchar3iiPc, @function
_Z8writePnmP6uchar3iiPc:
.LFB2067:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %r13d
movq %rcx, %r14
leaq .LC6(%rip), %rsi
movq %rcx, %rdi
call fopen@PLT
testq %rax, %rax
je .L22
movq %rax, %rbp
movl %r13d, %r8d
movl %ebx, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %r13d, %ebx
movl %ebx, %r8d
testl %ebx, %ebx
jle .L18
movq %r12, %rbx
movslq %r8d, %r8
leaq (%r8,%r8,2), %rax
addq %rax, %r12
leaq .LC9(%rip), %r13
.L19:
movzbl (%rbx), %ecx
movzbl 2(%rbx), %r9d
movzbl 1(%rbx), %r8d
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $3, %rbx
cmpq %r12, %rbx
jne .L19
.L18:
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq %r14, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z8writePnmP6uchar3iiPc, .-_Z8writePnmP6uchar3iiPc
.globl _Z12computeErrorP6uchar3S0_i
.type _Z12computeErrorP6uchar3S0_i, @function
_Z12computeErrorP6uchar3S0_i:
.LFB2069:
.cfi_startproc
endbr64
movl %edx, %r8d
testl %edx, %edx
jle .L26
movq %rdi, %rax
movslq %edx, %rdx
leaq (%rdx,%rdx,2), %rdx
addq %rdx, %rdi
pxor %xmm0, %xmm0
.L25:
movzbl (%rax), %edx
movzbl (%rsi), %ecx
subl %ecx, %edx
movl %edx, %ecx
negl %ecx
cmovns %ecx, %edx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
addss %xmm1, %xmm0
movzbl 1(%rax), %edx
movzbl 1(%rsi), %ecx
subl %ecx, %edx
movl %edx, %ecx
negl %ecx
cmovns %ecx, %edx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
addss %xmm0, %xmm1
movzbl 2(%rax), %edx
movzbl 2(%rsi), %ecx
subl %ecx, %edx
movl %edx, %ecx
negl %ecx
cmovns %ecx, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
addss %xmm1, %xmm0
addq $3, %rax
addq $3, %rsi
cmpq %rdi, %rax
jne .L25
.L24:
leal (%r8,%r8,2), %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
ret
.L26:
pxor %xmm0, %xmm0
jmp .L24
.cfi_endproc
.LFE2069:
.size _Z12computeErrorP6uchar3S0_i, .-_Z12computeErrorP6uchar3S0_i
.globl _Z9concatStrPKcS0_
.type _Z9concatStrPKcS0_, @function
_Z9concatStrPKcS0_:
.LFB2070:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbp
call strlen@PLT
movq %rax, %rbx
movq %rbp, %rdi
call strlen@PLT
leaq 1(%rbx,%rax), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdx
movq %r12, %rsi
movq %rax, %rdi
call __strcpy_chk@PLT
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z9concatStrPKcS0_, .-_Z9concatStrPKcS0_
.globl _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_
.type _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_, @function
_Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_:
.LFB2096:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13blurImgKernelP6uchar3iiPfiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_, .-_Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_
.globl _Z13blurImgKernelP6uchar3iiPfiS0_
.type _Z13blurImgKernelP6uchar3iiPfiS0_, @function
_Z13blurImgKernelP6uchar3iiPfiS0_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z13blurImgKernelP6uchar3iiPfiS0_, .-_Z13blurImgKernelP6uchar3iiPfiS0_
.section .rodata.str1.1
.LC11:
.string "use device"
.LC12:
.string "use host"
.LC13:
.string "GPU name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC14:
.string "GPU compute capability: %d.%d\n"
.align 8
.LC15:
.string "/home/ubuntu/Datasets/stackv2/train-structured/haunt98/learn-cuda/master/bt01_p2.cu"
.section .rodata.str1.1
.LC16:
.string "Error: %s:%d, "
.LC17:
.string "code: %d, reason: %s\n"
.LC18:
.string "Processing time (%s): %f ms\n"
.text
.globl _Z7blurImgP6uchar3iiPfiS0_b4dim3
.type _Z7blurImgP6uchar3iiPfiS0_b4dim3, @function
_Z7blurImgP6uchar3iiPfiS0_b4dim3:
.LFB2068:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2068
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1192, %rsp
.cfi_def_cfa_offset 1248
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r13d
movq %rcx, 8(%rsp)
movl %r8d, %r12d
movq %r9, 48(%rsp)
movl 1248(%rsp), %r15d
movl %r15d, 60(%rsp)
movq %fs:40, %rax
movq %rax, 1176(%rsp)
xorl %eax, %eax
leaq 128(%rsp), %rdi
.LEHB0:
call cudaEventCreate@PLT
leaq 136(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 128(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
testb %r15b, %r15b
jne .L39
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
testl %r13d, %r13d
jle .L40
leal 1(%rax), %esi
leal (%rax,%r13), %r10d
movl %eax, %edi
negl %edi
movslq %r12d, %r12
leaq 0(,%r12,4), %r14
movslq %edi, %rdx
movslq %eax, %rcx
addq %rcx, %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rcx
movq %rcx, 40(%rsp)
movl %esi, %r12d
movl $0, %edx
movl %ebx, %ecx
subl %eax, %ecx
movl %ecx, 32(%rsp)
leal -1(%rdi,%rdi), %ecx
movl %ecx, 64(%rsp)
leal -1(%r13), %r15d
leal -1(%rbx), %r9d
movl %edi, 36(%rsp)
movl %eax, 28(%rsp)
jmp .L41
.L47:
movslq %edx, %rax
leaq (%rax,%rax,2), %rax
movq 48(%rsp), %rdi
addq %rdi, %rax
movl 28(%rsp), %r11d
negl %r11d
movl 64(%rsp), %edi
addl %r12d, %edi
movl %edi, 56(%rsp)
movl %esi, %r8d
movl %edx, 68(%rsp)
movl %esi, 72(%rsp)
movl %r10d, 76(%rsp)
.L46:
movl 36(%rsp), %ecx
pxor %xmm2, %xmm2
movaps %xmm2, %xmm3
movaps %xmm2, %xmm4
cmpl %ecx, 28(%rsp)
jl .L43
movq 40(%rsp), %r10
movl 56(%rsp), %esi
pxor %xmm2, %xmm2
movaps %xmm2, %xmm3
movaps %xmm2, %xmm4
movq %rax, 16(%rsp)
movl %r11d, %edi
.L42:
testl %esi, %esi
movl $0, %r11d
cmovns %esi, %r11d
cmpl %r11d, %r13d
cmovle %r15d, %r11d
imull %ebx, %r11d
movq %r10, %rcx
movl %edi, %edx
movl %esi, 8(%rsp)
.L45:
testl %edx, %edx
movl $0, %eax
cmovns %edx, %eax
cmpl %eax, %ebx
cmovle %r9d, %eax
addl %r11d, %eax
cltq
leaq (%rax,%rax,2), %rax
addq %rbp, %rax
movss (%rcx), %xmm1
movzbl (%rax), %esi
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
mulss %xmm1, %xmm0
addss %xmm0, %xmm4
movzbl 1(%rax), %esi
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
mulss %xmm1, %xmm0
addss %xmm0, %xmm3
movzbl 2(%rax), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
addss %xmm0, %xmm2
addl $1, %edx
addq $4, %rcx
cmpl %r8d, %edx
jne .L45
movl 8(%rsp), %esi
addl $1, %esi
addq %r14, %r10
cmpl %r12d, %esi
jne .L42
movq 16(%rsp), %rax
movl %edi, %r11d
.L43:
cvttss2sil %xmm4, %edx
movb %dl, (%rax)
cvttss2sil %xmm3, %edx
movb %dl, 1(%rax)
cvttss2sil %xmm2, %edx
movb %dl, 2(%rax)
addq $3, %rax
addl $1, %r8d
addl $1, %r11d
movl 32(%rsp), %edi
cmpl %edi, %r11d
jne .L46
movl 68(%rsp), %edx
movl 72(%rsp), %esi
movl 76(%rsp), %r10d
.L48:
addl %ebx, %edx
leal 1(%r12), %eax
cmpl %r10d, %r12d
je .L40
movl %eax, %r12d
.L41:
testl %ebx, %ebx
jg .L47
jmp .L48
.L39:
leaq 144(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 144(%rsp), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 508(%rsp), %ecx
movl 504(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
leaq 88(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L70
leaq 96(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
jmp .L71
.L70:
movl $223, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r14d, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
movl %eax, %r14d
testl %eax, %eax
jne .L72
movl %r12d, %eax
imull %r12d, %eax
cltq
salq $2, %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
jmp .L73
.L72:
movl $224, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r14d, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl %eax, %r14d
testl %eax, %eax
jne .L74
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L75
.L74:
movl $225, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r14d, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl %eax, %ebp
testl %eax, %eax
jne .L76
movl $1, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L77
.L76:
movl $228, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
movl %eax, %ebp
testl %eax, %eax
jne .L78
leal -1(%rbx), %eax
movl $0, %edx
divl 1260(%rsp)
leal 1(%rax), %ecx
leal -1(%r13), %eax
movl $0, %edx
divl 1256(%rsp)
addl $1, %eax
movl %eax, 116(%rsp)
movl %ecx, 120(%rsp)
movl $1, 124(%rsp)
movl 1264(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 1256(%rsp), %rdx
movq 116(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L79
.L78:
movl $229, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L79:
testl %eax, %eax
jne .L54
movq 96(%rsp), %r9
movl %r12d, %r8d
movq 104(%rsp), %rcx
movl %r13d, %edx
movl %ebx, %esi
movq 88(%rsp), %rdi
call _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_
.L54:
movl $2, %ecx
movq %r15, %rdx
movq 96(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L80
movq 88(%rsp), %rdi
call cudaFree@PLT
jmp .L81
.L80:
movl $236, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
movl %eax, %ebx
testl %eax, %eax
jne .L82
movq 96(%rsp), %rdi
call cudaFree@PLT
jmp .L83
.L82:
movl $239, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L83:
movl %eax, %ebx
testl %eax, %eax
jne .L84
movq 104(%rsp), %rdi
call cudaFree@PLT
jmp .L85
.L84:
movl $240, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
movl %eax, %ebx
testl %eax, %eax
jne .L86
.L40:
movl $0, %esi
movq 136(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L87
.L86:
movl $241, %r8d
leaq .LC15(%rip), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movq 136(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 116(%rsp), %rdi
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 116(%rsp), %xmm0
cmpb $0, 60(%rsp)
leaq .LC12(%rip), %rdx
leaq .LC11(%rip), %rax
cmovne %rax, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.LEHE1:
movq 128(%rsp), %rdi
call cudaEventDestroy@PLT
movq 136(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1176(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $1192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq 128(%rsp), %rdi
call cudaEventDestroy@PLT
movq 136(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1176(%rsp), %rax
subq %fs:40, %rax
je .L61
call __stack_chk_fail@PLT
.L61:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2068:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2068-.LLSDACSB2068
.LLSDACSB2068:
.uleb128 .LEHB0-.LFB2068
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2068
.uleb128 .LEHE1-.LEHB1
.uleb128 .L65-.LFB2068
.uleb128 0
.uleb128 .LEHB2-.LFB2068
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE2068:
.text
.size _Z7blurImgP6uchar3iiPfiS0_b4dim3, .-_Z7blurImgP6uchar3iiPfiS0_b4dim3
.section .rodata.str1.8
.align 8
.LC19:
.string "The number of arguments is invalid\n"
.align 8
.LC20:
.string "Image size (width x height): %i x %i\n\n"
.align 8
.LC21:
.string "The shape of the correct output image is invalid\n"
.section .rodata.str1.1
.LC23:
.string "Error: %f\n\n"
.LC24:
.string "."
.LC25:
.string "_host.pnm"
.LC26:
.string "_device.pnm"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edi, %eax
andl $-3, %eax
cmpl $4, %eax
jne .L101
movl %edi, %ebp
movq %rsi, %rbx
leaq 40(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
movq 8(%rbx), %rdi
call _Z7readPnmPcRiS0_RP6uchar3
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rcx
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
movq 24(%rbx), %rdi
call _Z7readPnmPcRiS0_RP6uchar3
movl 24(%rsp), %r12d
cmpl %r12d, 32(%rsp)
jne .L92
movl 28(%rsp), %r14d
cmpl %r14d, 36(%rsp)
je .L93
.L92:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L89:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L102
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L89
.L93:
movl $324, %edi
call malloc@PLT
movq %rax, %r13
leaq 36(%rax), %rdx
leaq 360(%rax), %rcx
movss .LC22(%rip), %xmm0
.L94:
leaq -36(%rdx), %rax
.L95:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L95
addq $36, %rdx
cmpq %rcx, %rdx
jne .L94
movl %r12d, %edi
imull %r14d, %edi
movslq %edi, %rdi
imulq $3, %rdi, %rdi
call malloc@PLT
movq %rax, %rcx
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movq 40(%rsp), %r15
subq $24, %rsp
.cfi_def_cfa_offset 168
movq 84(%rsp), %rax
movq %rax, (%rsp)
movl $1, 8(%rsp)
pushq $0
.cfi_def_cfa_offset 176
movq %rcx, 40(%rsp)
movq %rcx, %r9
movl $9, %r8d
movq %r13, %rcx
movl %r14d, %edx
movl %r12d, %esi
movq %r15, %rdi
call _Z7blurImgP6uchar3iiPfiS0_b4dim3
movq 80(%rsp), %r12
addq $32, %rsp
.cfi_def_cfa_offset 144
movl 24(%rsp), %edx
imull 28(%rsp), %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call _Z12computeErrorP6uchar3S0_i
cvtss2sd %xmm0, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 24(%rsp), %edi
imull 28(%rsp), %edi
movslq %edi, %rdi
imulq $3, %rdi, %rdi
call malloc@PLT
movq %rax, %r14
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
cmpl $6, %ebp
je .L103
.L97:
subq $24, %rsp
.cfi_def_cfa_offset 168
movq 84(%rsp), %rax
movq %rax, (%rsp)
movl 92(%rsp), %eax
movl %eax, 8(%rsp)
pushq $1
.cfi_def_cfa_offset 176
movq %r14, %r9
movl $9, %r8d
movq %r13, %rcx
movl 60(%rsp), %edx
movl 56(%rsp), %esi
movq %r15, %rdi
call _Z7blurImgP6uchar3iiPfiS0_b4dim3
addq $32, %rsp
.cfi_def_cfa_offset 144
movl 24(%rsp), %edx
imull 28(%rsp), %edx
movq %r12, %rsi
movq %r14, %rdi
call _Z12computeErrorP6uchar3S0_i
cvtss2sd %xmm0, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rbx), %rdi
leaq .LC24(%rip), %rsi
call strtok@PLT
movq %rax, %rbx
leaq .LC25(%rip), %rsi
movq %rax, %rdi
call _Z9concatStrPKcS0_
movq %rax, %rcx
movl 28(%rsp), %edx
movl 24(%rsp), %esi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call _Z8writePnmP6uchar3iiPc
leaq .LC26(%rip), %rsi
movq %rbx, %rdi
call _Z9concatStrPKcS0_
movq %rax, %rcx
movl 28(%rsp), %edx
movl 24(%rsp), %esi
movq %r14, %rdi
call _Z8writePnmP6uchar3iiPc
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
jmp .L89
.L103:
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 60(%rsp)
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 64(%rsp)
jmp .L97
.L102:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC27:
.string "_Z13blurImgKernelP6uchar3iiPfiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z13blurImgKernelP6uchar3iiPfiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC22:
.long 1011500424
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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