system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdint.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &width, int &height, uchar3 * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P3") != 0) // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
for (int i = 0; i < width * height; i++)
fscanf(f, "%hhu%hhu%hhu", &pixels[i].x, &pixels[i].y, &pixels[i].z);
fclose(f);
}
void writePnm(uchar3 * pixels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "P3\n%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height; i++)
fprintf(f, "%hhu\n%hhu\n%hhu\n", pixels[i].x, pixels[i].y, pixels[i].z);
fclose(f);
}
__global__ void blurImgKernel(uchar3 * inPixels, int width, int height,
float * filter, int filterWidth,
uchar3 * outPixels)
{
// TODO
int row = threadIdx.x + blockIdx.x * blockDim.x;
int col = threadIdx.y + blockIdx.y * blockDim.y;
int half = filterWidth / 2;
if(row < height && col < width){
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
void blurImg(uchar3 * inPixels, int width, int height, float * filter, int filterWidth,
uchar3 * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1, 1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
// TODO
int half = filterWidth / 2;
for(int row = 0; row < height; row += 1) {
for(int col = 0; col < width; col += 1) {
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
}
else // Use device
{
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO
// Allocate device memories
uchar3 *d_inPixels, *d_outPixels;
float *d_filter;
CHECK(cudaMalloc(&d_inPixels, width * height * sizeof(uchar3)));
CHECK(cudaMalloc(&d_outPixels, width * height * sizeof(uchar3)));
CHECK(cudaMalloc(&d_filter, filterWidth * filterWidth * sizeof(float)));
// Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, width * height * sizeof(uchar3), cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_filter, filter, filterWidth * filterWidth * sizeof(float), cudaMemcpyHostToDevice));
// Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((height - 1) / blockSize.x + 1, (width - 1) / blockSize.y + 1);
blurImgKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_filter, filterWidth, d_outPixels);
// Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, width * height * sizeof(uchar3), cudaMemcpyDeviceToHost));
// Free device memories
CHECK(cudaFree(d_inPixels));
CHECK(cudaFree(d_outPixels));
CHECK(cudaFree(d_filter));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uchar3 * a1, uchar3 * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
{
err += abs((int)a1[i].x - (int)a2[i].x);
err += abs((int)a1[i].y - (int)a2[i].y);
err += abs((int)a1[i].z - (int)a2[i].z);
}
err /= (n * 3);
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 4 && argc != 6)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input image file
int width, height;
uchar3 * inPixels;
readPnm(argv[1], width, height, inPixels);
printf("Image size (width x height): %i x %i\n\n", width, height);
// Read correct output image file
int correctWidth, correctHeight;
uchar3 * correctOutPixels;
readPnm(argv[3], correctWidth, correctHeight, correctOutPixels);
if (correctWidth != width || correctHeight != height)
{
printf("The shape of the correct output image is invalid\n");
return EXIT_FAILURE;
}
// Set up a simple filter with blurring effect
int filterWidth = 9;
float * filter = (float *)malloc(filterWidth * filterWidth * sizeof(float));
for (int filterR = 0; filterR < filterWidth; filterR++)
{
for (int filterC = 0; filterC < filterWidth; filterC++)
{
filter[filterR * filterWidth + filterC] = 1. / (filterWidth * filterWidth);
}
}
// Blur input image using host
uchar3 * hostOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
blurImg(inPixels, width, height, filter, filterWidth, hostOutPixels);
// Compute mean absolute error between host result and correct result
float hostErr = computeError(hostOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", hostErr);
// Blur input image using device
uchar3 * deviceOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
dim3 blockSize(32, 32); // Default
if (argc == 6)
{
blockSize.x = atoi(argv[4]);
blockSize.y = atoi(argv[5]);
}
blurImg(inPixels, width, height, filter, filterWidth, deviceOutPixels, true, blockSize);
// Compute mean absolute error between device result and correct result
float deviceErr = computeError(deviceOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", deviceErr);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(hostOutPixels, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(deviceOutPixels, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(correctOutPixels);
free(hostOutPixels);
free(deviceOutPixels);
free(filter);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &width, int &height, uchar3 * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P3") != 0) // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
for (int i = 0; i < width * height; i++)
fscanf(f, "%hhu%hhu%hhu", &pixels[i].x, &pixels[i].y, &pixels[i].z);
fclose(f);
}
void writePnm(uchar3 * pixels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "P3\n%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height; i++)
fprintf(f, "%hhu\n%hhu\n%hhu\n", pixels[i].x, pixels[i].y, pixels[i].z);
fclose(f);
}
__global__ void blurImgKernel(uchar3 * inPixels, int width, int height,
float * filter, int filterWidth,
uchar3 * outPixels)
{
// TODO
int row = threadIdx.x + blockIdx.x * blockDim.x;
int col = threadIdx.y + blockIdx.y * blockDim.y;
int half = filterWidth / 2;
if(row < height && col < width){
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
void blurImg(uchar3 * inPixels, int width, int height, float * filter, int filterWidth,
uchar3 * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1, 1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
// TODO
int half = filterWidth / 2;
for(int row = 0; row < height; row += 1) {
for(int col = 0; col < width; col += 1) {
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
}
else // Use device
{
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO
// Allocate device memories
uchar3 *d_inPixels, *d_outPixels;
float *d_filter;
CHECK(hipMalloc(&d_inPixels, width * height * sizeof(uchar3)));
CHECK(hipMalloc(&d_outPixels, width * height * sizeof(uchar3)));
CHECK(hipMalloc(&d_filter, filterWidth * filterWidth * sizeof(float)));
// Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, width * height * sizeof(uchar3), hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_filter, filter, filterWidth * filterWidth * sizeof(float), hipMemcpyHostToDevice));
// Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((height - 1) / blockSize.x + 1, (width - 1) / blockSize.y + 1);
blurImgKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_filter, filterWidth, d_outPixels);
// Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, width * height * sizeof(uchar3), hipMemcpyDeviceToHost));
// Free device memories
CHECK(hipFree(d_inPixels));
CHECK(hipFree(d_outPixels));
CHECK(hipFree(d_filter));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uchar3 * a1, uchar3 * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
{
err += abs((int)a1[i].x - (int)a2[i].x);
err += abs((int)a1[i].y - (int)a2[i].y);
err += abs((int)a1[i].z - (int)a2[i].z);
}
err /= (n * 3);
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 4 && argc != 6)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input image file
int width, height;
uchar3 * inPixels;
readPnm(argv[1], width, height, inPixels);
printf("Image size (width x height): %i x %i\n\n", width, height);
// Read correct output image file
int correctWidth, correctHeight;
uchar3 * correctOutPixels;
readPnm(argv[3], correctWidth, correctHeight, correctOutPixels);
if (correctWidth != width || correctHeight != height)
{
printf("The shape of the correct output image is invalid\n");
return EXIT_FAILURE;
}
// Set up a simple filter with blurring effect
int filterWidth = 9;
float * filter = (float *)malloc(filterWidth * filterWidth * sizeof(float));
for (int filterR = 0; filterR < filterWidth; filterR++)
{
for (int filterC = 0; filterC < filterWidth; filterC++)
{
filter[filterR * filterWidth + filterC] = 1. / (filterWidth * filterWidth);
}
}
// Blur input image using host
uchar3 * hostOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
blurImg(inPixels, width, height, filter, filterWidth, hostOutPixels);
// Compute mean absolute error between host result and correct result
float hostErr = computeError(hostOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", hostErr);
// Blur input image using device
uchar3 * deviceOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
dim3 blockSize(32, 32); // Default
if (argc == 6)
{
blockSize.x = atoi(argv[4]);
blockSize.y = atoi(argv[5]);
}
blurImg(inPixels, width, height, filter, filterWidth, deviceOutPixels, true, blockSize);
// Compute mean absolute error between device result and correct result
float deviceErr = computeError(deviceOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", deviceErr);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(hostOutPixels, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(deviceOutPixels, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(correctOutPixels);
free(hostOutPixels);
free(deviceOutPixels);
free(filter);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName,
int &width, int &height, uchar3 * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P3") != 0) // In this exercise, we don't touch other types
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
int max_val;
fscanf(f, "%i", &max_val);
if (max_val > 255) // In this exercise, we assume 1 byte per value
{
fclose(f);
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
pixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
for (int i = 0; i < width * height; i++)
fscanf(f, "%hhu%hhu%hhu", &pixels[i].x, &pixels[i].y, &pixels[i].z);
fclose(f);
}
void writePnm(uchar3 * pixels, int width, int height,
char * fileName)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "P3\n%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height; i++)
fprintf(f, "%hhu\n%hhu\n%hhu\n", pixels[i].x, pixels[i].y, pixels[i].z);
fclose(f);
}
__global__ void blurImgKernel(uchar3 * inPixels, int width, int height,
float * filter, int filterWidth,
uchar3 * outPixels)
{
// TODO
int row = threadIdx.x + blockIdx.x * blockDim.x;
int col = threadIdx.y + blockIdx.y * blockDim.y;
int half = filterWidth / 2;
if(row < height && col < width){
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
void blurImg(uchar3 * inPixels, int width, int height, float * filter, int filterWidth,
uchar3 * outPixels,
bool useDevice=false, dim3 blockSize=dim3(1, 1))
{
GpuTimer timer;
timer.Start();
if (useDevice == false)
{
// TODO
int half = filterWidth / 2;
for(int row = 0; row < height; row += 1) {
for(int col = 0; col < width; col += 1) {
float x = 0;
float y = 0;
float z = 0;
for (int rowF = -half ; rowF <= half; rowF += 1) {
for (int colF = -half; colF <= half; colF += 1){
int newRow = row + rowF;
int newCol = col + colF;
if (newRow < 0) {
newRow = 0;
}
if (newRow >= height) {
newRow = height - 1;
}
if (newCol < 0) {
newCol = 0;
}
if (newCol >= width) {
newCol = width - 1;
}
int cord = newRow * width + newCol;
int cordF = (rowF + half) * filterWidth + (colF + half);
x += inPixels[cord].x * filter[cordF];
y += inPixels[cord].y * filter[cordF];
z += inPixels[cord].z * filter[cordF];
}
}
outPixels[row * width + col].x = int(x);
outPixels[row * width + col].y = int(y);
outPixels[row * width + col].z = int(z);
}
}
}
else // Use device
{
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
printf("GPU name: %s\n", devProp.name);
printf("GPU compute capability: %d.%d\n", devProp.major, devProp.minor);
// TODO
// Allocate device memories
uchar3 *d_inPixels, *d_outPixels;
float *d_filter;
CHECK(hipMalloc(&d_inPixels, width * height * sizeof(uchar3)));
CHECK(hipMalloc(&d_outPixels, width * height * sizeof(uchar3)));
CHECK(hipMalloc(&d_filter, filterWidth * filterWidth * sizeof(float)));
// Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, width * height * sizeof(uchar3), hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_filter, filter, filterWidth * filterWidth * sizeof(float), hipMemcpyHostToDevice));
// Set grid size and call kernel (remember to check kernel error)
dim3 gridSize((height - 1) / blockSize.x + 1, (width - 1) / blockSize.y + 1);
blurImgKernel<<<gridSize, blockSize>>>(d_inPixels, width, height, d_filter, filterWidth, d_outPixels);
// Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, width * height * sizeof(uchar3), hipMemcpyDeviceToHost));
// Free device memories
CHECK(hipFree(d_inPixels));
CHECK(hipFree(d_outPixels));
CHECK(hipFree(d_filter));
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time (%s): %f ms\n",
useDevice == true? "use device" : "use host", time);
}
float computeError(uchar3 * a1, uchar3 * a2, int n)
{
float err = 0;
for (int i = 0; i < n; i++)
{
err += abs((int)a1[i].x - (int)a2[i].x);
err += abs((int)a1[i].y - (int)a2[i].y);
err += abs((int)a1[i].z - (int)a2[i].z);
}
err /= (n * 3);
return err;
}
char * concatStr(const char * s1, const char * s2)
{
char * result = (char *)malloc(strlen(s1) + strlen(s2) + 1);
strcpy(result, s1);
strcat(result, s2);
return result;
}
int main(int argc, char ** argv)
{
if (argc != 4 && argc != 6)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
// Read input image file
int width, height;
uchar3 * inPixels;
readPnm(argv[1], width, height, inPixels);
printf("Image size (width x height): %i x %i\n\n", width, height);
// Read correct output image file
int correctWidth, correctHeight;
uchar3 * correctOutPixels;
readPnm(argv[3], correctWidth, correctHeight, correctOutPixels);
if (correctWidth != width || correctHeight != height)
{
printf("The shape of the correct output image is invalid\n");
return EXIT_FAILURE;
}
// Set up a simple filter with blurring effect
int filterWidth = 9;
float * filter = (float *)malloc(filterWidth * filterWidth * sizeof(float));
for (int filterR = 0; filterR < filterWidth; filterR++)
{
for (int filterC = 0; filterC < filterWidth; filterC++)
{
filter[filterR * filterWidth + filterC] = 1. / (filterWidth * filterWidth);
}
}
// Blur input image using host
uchar3 * hostOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
blurImg(inPixels, width, height, filter, filterWidth, hostOutPixels);
// Compute mean absolute error between host result and correct result
float hostErr = computeError(hostOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", hostErr);
// Blur input image using device
uchar3 * deviceOutPixels = (uchar3 *)malloc(width * height * sizeof(uchar3));
dim3 blockSize(32, 32); // Default
if (argc == 6)
{
blockSize.x = atoi(argv[4]);
blockSize.y = atoi(argv[5]);
}
blurImg(inPixels, width, height, filter, filterWidth, deviceOutPixels, true, blockSize);
// Compute mean absolute error between device result and correct result
float deviceErr = computeError(deviceOutPixels, correctOutPixels, width * height);
printf("Error: %f\n\n", deviceErr);
// Write results to files
char * outFileNameBase = strtok(argv[2], "."); // Get rid of extension
writePnm(hostOutPixels, width, height, concatStr(outFileNameBase, "_host.pnm"));
writePnm(deviceOutPixels, width, height, concatStr(outFileNameBase, "_device.pnm"));
// Free memories
free(inPixels);
free(correctOutPixels);
free(hostOutPixels);
free(deviceOutPixels);
free(filter);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.globl _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.p2align 8
.type _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_,@function
_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v1, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s10, s[0:1], 0x18
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, -1
s_cbranch_scc1 .LBB0_8
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_lshr_b32 s8, s10, 31
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_add_i32 s8, s10, s8
v_mov_b32_e32 v4, 0
s_ashr_i32 s8, s8, 1
s_add_i32 s12, s5, -1
s_abs_i32 s13, s8
v_subrev_nc_u32_e32 v3, s8, v1
s_add_i32 s16, s8, s13
s_sub_i32 s14, 0, s8
s_add_i32 s15, s4, -1
s_add_i32 s16, s16, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v6, s14, v0
s_mov_b32 s8, s11
s_mov_b32 s17, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v6, 0, v6
v_cmp_gt_i32_e32 vcc_lo, s5, v6
v_cndmask_b32_e32 v6, s12, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v6, v6, s4
.p2align 6
.LBB0_4:
v_max_i32_e32 v8, 0, v7
s_ashr_i32 s9, s8, 31
v_add_nc_u32_e32 v7, 1, v7
s_lshl_b64 s[18:19], s[8:9], 2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v8
s_waitcnt lgkmcnt(0)
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_add_i32 s17, s17, -1
s_add_i32 s8, s8, 1
v_cndmask_b32_e32 v8, s15, v8, vcc_lo
s_cmp_eq_u32 s17, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, v8, v6
v_mad_i64_i32 v[8:9], null, v10, 3, s[2:3]
s_clause 0x2
global_load_u8 v10, v[8:9], off
global_load_u8 v11, v[8:9], off offset:1
global_load_u8 v8, v[8:9], off offset:2
s_load_b32 s9, s[18:19], 0x0
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v9, v10
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v10, v11
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v8, v8
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, s9, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_fmac_f32 v4, s9, v10 :: v_dual_fmac_f32 v5, s9, v8
s_cbranch_scc0 .LBB0_4
s_add_i32 s8, s14, 1
s_add_i32 s11, s11, s10
s_cmp_eq_u32 s14, s13
s_cbranch_scc1 .LBB0_7
s_mov_b32 s14, s8
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
v_cvt_i32_f32_e32 v2, v2
v_cvt_i32_f32_e32 v3, v4
v_cvt_i32_f32_e32 v4, v5
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v5, 3, s[0:1]
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v3, off offset:1
global_store_b8 v[0:1], v4, off offset:2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, .Lfunc_end0-_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13blurImgKernelP6uchar3iiPfiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe400078e0205 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fe40000706670 */
/*00a0*/ LEA.HI R2, R2, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0002027a11 */
/* 0x000fd600078f08ff */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*00d0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*00f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R5, -R2, RZ, RZ ; /* 0x000000ff02057210 */
/* 0x000fc80007ffe1ff */
/*0110*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 BRA 0xaf0 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, -R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe20007ffe1ff */
/*0140*/ IMAD.IADD R9, R3.reuse, 0x1, -R2 ; /* 0x0000000103097824 */
/* 0x040fe200078e0a02 */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.SHL.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067824 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R11, R3, R4, RZ ; /* 0x00000004030b7210 */
/* 0x000fe20007ffe0ff */
/*0180*/ UIADD3 UR5, UR6, -0x1, URZ ; /* 0xffffffff06057890 */
/* 0x000fe2000fffe03f */
/*0190*/ IMNMX R10, RZ, R9, !PT ; /* 0x00000009ff0a7217 */
/* 0x000fe20007800200 */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R12, R11, 0x1, RZ ; /* 0x000000010b0c7810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*01d0*/ IMNMX R11, RZ, R11, !PT ; /* 0x0000000bff0b7217 */
/* 0x000fe20007800200 */
/*01e0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ IMNMX R12, RZ, R12, !PT ; /* 0x0000000cff0c7217 */
/* 0x000fc40007800200 */
/*0200*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x000fe40003f06270 */
/*0220*/ ISETP.GE.AND P1, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fe40003f26270 */
/*0230*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x168], PT ; /* 0x00005a000c007a0c */
/* 0x000fe40003f46270 */
/*0240*/ IADD3 R7, -R2, 0x3, RZ ; /* 0x0000000302077810 */
/* 0x000fe40007ffe1ff */
/*0250*/ IADD3 R8, R3, 0x3, RZ ; /* 0x0000000303087810 */
/* 0x000fc40007ffe0ff */
/*0260*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*0270*/ SEL R10, R10, UR5, !P0 ; /* 0x000000050a0a7c07 */
/* 0x000fe4000c000000 */
/*0280*/ SEL R11, R11, UR5, !P1 ; /* 0x000000050b0b7c07 */
/* 0x000fe4000c800000 */
/*0290*/ SEL R12, R12, UR5, !P2 ; /* 0x000000050c0c7c07 */
/* 0x000fe4000d000000 */
/*02a0*/ IADD3 R13, R0, R5, RZ ; /* 0x00000005000d7210 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x3 ; /* 0x00000003ff127424 */
/* 0x000fc600078e00ff */
/*02c0*/ IMNMX R13, RZ, R13, !PT ; /* 0x0000000dff0d7217 */
/* 0x000fc80007800200 */
/*02d0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x16c], PT ; /* 0x00005b000d007a0c */
/* 0x000fc80003f06270 */
/*02e0*/ SEL R13, R13, UR4, !P0 ; /* 0x000000040d0d7c07 */
/* 0x000fca000c000000 */
/*02f0*/ IMAD R17, R13, c[0x0][0x168], R10 ; /* 0x00005a000d117a24 */
/* 0x000fc800078e020a */
/*0300*/ IMAD.WIDE R16, R17, R18, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fe200078e0212 */
/*0310*/ IADD3 R25, R2, R5, RZ ; /* 0x0000000502197210 */
/* 0x000fc80007ffe0ff */
/*0320*/ LDG.E.U8 R22, [R16.64] ; /* 0x0000000810167981 */
/* 0x0000a8000c1e1100 */
/*0330*/ LDG.E.U8 R24, [R16.64+0x1] ; /* 0x0000010810187981 */
/* 0x0000e8000c1e1100 */
/*0340*/ LDG.E.U8 R27, [R16.64+0x2] ; /* 0x00000208101b7981 */
/* 0x000122000c1e1100 */
/*0350*/ IMAD.MOV.U32 R26, RZ, RZ, 0x4 ; /* 0x00000004ff1a7424 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD R25, R25, c[0x0][0x178], RZ ; /* 0x00005e0019197a24 */
/* 0x000fc800078e02ff */
/*0370*/ IMAD.WIDE R14, R25, R26, c[0x0][0x170] ; /* 0x00005c00190e7625 */
/* 0x000fca00078e021a */
/*0380*/ LDG.E R23, [R14.64] ; /* 0x000000080e177981 */
/* 0x000f62000c1e1900 */
/*0390*/ ISETP.NE.AND P1, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f25270 */
/*03a0*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe40003f06270 */
/*03b0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f46070 */
/*03c0*/ MOV R16, R4 ; /* 0x0000000400107202 */
/* 0x001fe20000000f00 */
/*03d0*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x004f700000101000 */
/*03e0*/ I2F.U16 R24, R24 ; /* 0x0000001800187306 */
/* 0x008e300000101000 */
/*03f0*/ I2F.U16 R28, R27 ; /* 0x0000001b001c7306 */
/* 0x010e620000101000 */
/*0400*/ FFMA R21, R22, R23, R21 ; /* 0x0000001716157223 */
/* 0x020fc40000000015 */
/*0410*/ FFMA R20, R23.reuse, R24, R20 ; /* 0x0000001817147223 */
/* 0x041fe40000000014 */
/*0420*/ FFMA R19, R23, R28, R19 ; /* 0x0000001c17137223 */
/* 0x002fe20000000013 */
/*0430*/ @!P1 BRA 0x5d0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD R17, R13, c[0x0][0x168], R11 ; /* 0x00005a000d117a24 */
/* 0x000fe200078e020b */
/*0450*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004080e187981 */
/* 0x000ea6000c1e1900 */
/*0460*/ IMAD.WIDE R16, R17, R18, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fe200078e0212 */
/*0470*/ LDG.E R28, [R14.64+0x8] ; /* 0x000008080e1c7981 */
/* 0x0000e8000c1e1900 */
/*0480*/ LDG.E.U8 R22, [R16.64] ; /* 0x0000000810167981 */
/* 0x000f28000c1e1100 */
/*0490*/ LDG.E.U8 R27, [R16.64+0x1] ; /* 0x00000108101b7981 */
/* 0x000f62000c1e1100 */
/*04a0*/ IMAD R23, R13, c[0x0][0x168], R12 ; /* 0x00005a000d177a24 */
/* 0x000fc600078e020c */
/*04b0*/ LDG.E.U8 R29, [R16.64+0x2] ; /* 0x00000208101d7981 */
/* 0x0002a2000c1e1100 */
/*04c0*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x010eb00000101000 */
/*04d0*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x020f220000101000 */
/*04e0*/ FFMA R21, R22, R24, R21 ; /* 0x0000001816157223 */
/* 0x004fc40000000015 */
/*04f0*/ IMAD.WIDE R22, R23, R18, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fca00078e0212 */
/*0500*/ LDG.E.U8 R17, [R22.64+0x1] ; /* 0x0000010816117981 */
/* 0x002ea2000c1e1100 */
/*0510*/ FFMA R27, R24, R27, R20 ; /* 0x0000001b181b7223 */
/* 0x010fc60000000014 */
/*0520*/ LDG.E.U8 R20, [R22.64] ; /* 0x0000000816147981 */
/* 0x000f28000c1e1100 */
/*0530*/ LDG.E.U8 R15, [R22.64+0x2] ; /* 0x00000208160f7981 */
/* 0x001f62000c1e1100 */
/*0540*/ I2F.U16 R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e220000101000 */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, R7 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0007 */
/*0560*/ FFMA R19, R24, R29, R19 ; /* 0x0000001d18137223 */
/* 0x001fca0000000013 */
/*0570*/ I2F.U16 R14, R17 ; /* 0x00000011000e7306 */
/* 0x004ff00000101000 */
/*0580*/ I2F.U16 R20, R20 ; /* 0x0000001400147306 */
/* 0x010ef00000101000 */
/*0590*/ I2F.U16 R15, R15 ; /* 0x0000000f000f7306 */
/* 0x020e220000101000 */
/*05a0*/ FFMA R21, R20, R28, R21 ; /* 0x0000001c14157223 */
/* 0x008fc40000000015 */
/*05b0*/ FFMA R20, R28.reuse, R14, R27 ; /* 0x0000000e1c147223 */
/* 0x040fe4000000001b */
/*05c0*/ FFMA R19, R28, R15, R19 ; /* 0x0000000f1c137223 */
/* 0x001fc60000000013 */
/*05d0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ @!P2 BRA 0xae0 ; /* 0x000004f00000a947 */
/* 0x000fea0003800000 */
/*05f0*/ IADD3 R15, R25, R2, R16 ; /* 0x00000002190f7210 */
/* 0x000fe40007ffe010 */
/*0600*/ IADD3 R23, R16, -0x1, RZ ; /* 0xffffffff10177810 */
/* 0x000fe40007ffe0ff */
/*0610*/ IADD3 R22, R8, R16, RZ ; /* 0x0000001008167210 */
/* 0x000fe20007ffe0ff */
/*0620*/ IMAD.WIDE R14, R15, R26, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x000fc800078e021a */
/*0630*/ IMAD.MOV.U32 R25, RZ, RZ, R15 ; /* 0x000000ffff197224 */
/* 0x000fe200078e000f */
/*0640*/ MOV R24, R14 ; /* 0x0000000e00187202 */
/* 0x000fe20000000f00 */
/*0650*/ IMAD.IADD R14, R3, 0x1, R16 ; /* 0x00000001030e7824 */
/* 0x000fca00078e0210 */
/*0660*/ IMNMX R14, RZ, R14, !PT ; /* 0x0000000eff0e7217 */
/* 0x000fc80007800200 */
/*0670*/ ISETP.GE.AND P1, PT, R14, c[0x0][0x168], PT ; /* 0x00005a000e007a0c */
/* 0x000fc80003f26270 */
/*0680*/ SEL R14, R14, UR5, !P1 ; /* 0x000000050e0e7c07 */
/* 0x000fca000c800000 */
/*0690*/ IMAD R15, R13, c[0x0][0x168], R14 ; /* 0x00005a000d0f7a24 */
/* 0x000fc800078e020e */
/*06a0*/ IMAD.WIDE R14, R15, R18, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fca00078e0212 */
/*06b0*/ LDG.E.U8 R28, [R14.64] ; /* 0x000000080e1c7981 */
/* 0x0000a8000c1e1100 */
/*06c0*/ LDG.E.U8 R26, [R14.64+0x1] ; /* 0x000001080e1a7981 */
/* 0x0000e8000c1e1100 */
/*06d0*/ LDG.E.U8 R27, [R14.64+0x2] ; /* 0x000002080e1b7981 */
/* 0x000124000c1e1100 */
/*06e0*/ MOV R14, R24 ; /* 0x00000018000e7202 */
/* 0x001fe20000000f00 */
/*06f0*/ IMAD.MOV.U32 R15, RZ, RZ, R25 ; /* 0x000000ffff0f7224 */
/* 0x000fca00078e0019 */
/*0700*/ LDG.E R24, [R14.64] ; /* 0x000000080e187981 */
/* 0x000f62000c1e1900 */
/*0710*/ IADD3 R25, R22, -0x2, RZ ; /* 0xfffffffe16197810 */
/* 0x000fc80007ffe0ff */
/*0720*/ IMNMX R25, RZ, R25, !PT ; /* 0x00000019ff197217 */
/* 0x000fc80007800200 */
/*0730*/ ISETP.GE.AND P1, PT, R25, c[0x0][0x168], PT ; /* 0x00005a0019007a0c */
/* 0x000fc80003f26270 */
/*0740*/ SEL R25, R25, UR5, !P1 ; /* 0x0000000519197c07 */
/* 0x000fca000c800000 */
/*0750*/ IMAD R25, R13, c[0x0][0x168], R25 ; /* 0x00005a000d197a24 */
/* 0x000fe200078e0219 */
/*0760*/ I2F.U16 R16, R28 ; /* 0x0000001c00107306 */
/* 0x004f700000101000 */
/*0770*/ I2F.U16 R17, R26 ; /* 0x0000001a00117306 */
/* 0x008e300000101000 */
/*0780*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x010e620000101000 */
/*0790*/ FFMA R21, R16, R24, R21 ; /* 0x0000001810157223 */
/* 0x020fc40000000015 */
/*07a0*/ FFMA R20, R24, R17, R20 ; /* 0x0000001118147223 */
/* 0x001fe40000000014 */
/*07b0*/ IMAD.WIDE R16, R25, R18, c[0x0][0x160] ; /* 0x0000580019107625 */
/* 0x000fc800078e0212 */
/*07c0*/ FFMA R19, R24, R27, R19 ; /* 0x0000001b18137223 */
/* 0x002fe20000000013 */
/*07d0*/ LDG.E.U8 R26, [R16.64] ; /* 0x00000008101a7981 */
/* 0x0000a8000c1e1100 */
/*07e0*/ LDG.E.U8 R28, [R16.64+0x1] ; /* 0x00000108101c7981 */
/* 0x0000e8000c1e1100 */
/*07f0*/ LDG.E.U8 R25, [R16.64+0x2] ; /* 0x0000020810197981 */
/* 0x000128000c1e1100 */
/*0800*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004080e187981 */
/* 0x000f62000c1e1900 */
/*0810*/ IADD3 R29, R22, -0x1, RZ ; /* 0xffffffff161d7810 */
/* 0x000fc80007ffe0ff */
/*0820*/ IMNMX R29, RZ, R29, !PT ; /* 0x0000001dff1d7217 */
/* 0x000fc80007800200 */
/*0830*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x168], PT ; /* 0x00005a001d007a0c */
/* 0x000fc80003f26270 */
/*0840*/ SEL R29, R29, UR5, !P1 ; /* 0x000000051d1d7c07 */
/* 0x000fca000c800000 */
/*0850*/ IMAD R29, R13, c[0x0][0x168], R29 ; /* 0x00005a000d1d7a24 */
/* 0x000fc800078e021d */
/*0860*/ IMAD.WIDE R16, R29, R18, c[0x0][0x160] ; /* 0x000058001d107625 */
/* 0x001fe200078e0212 */
/*0870*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x004f700000101000 */
/*0880*/ I2F.U16 R27, R28 ; /* 0x0000001c001b7306 */
/* 0x0080700000101000 */
/*0890*/ I2F.U16 R25, R25 ; /* 0x0000001900197306 */
/* 0x010ea20000101000 */
/*08a0*/ FFMA R21, R26, R24, R21 ; /* 0x000000181a157223 */
/* 0x020fe20000000015 */
/*08b0*/ LDG.E.U8 R28, [R16.64+0x2] ; /* 0x00000208101c7981 */
/* 0x0010e8000c1e1100 */
/*08c0*/ LDG.E.U8 R26, [R16.64] ; /* 0x00000008101a7981 */
/* 0x000122000c1e1100 */
/*08d0*/ FFMA R20, R24, R27, R20 ; /* 0x0000001b18147223 */
/* 0x002fc60000000014 */
/*08e0*/ LDG.E.U8 R27, [R16.64+0x1] ; /* 0x00000108101b7981 */
/* 0x000162000c1e1100 */
/*08f0*/ FFMA R19, R24, R25, R19 ; /* 0x0000001918137223 */
/* 0x004fc60000000013 */
/*0900*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008080e187981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMNMX R29, RZ, R22, !PT ; /* 0x00000016ff1d7217 */
/* 0x000fc80007800200 */
/*0920*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x168], PT ; /* 0x00005a001d007a0c */
/* 0x000fc80003f26270 */
/*0930*/ SEL R29, R29, UR5, !P1 ; /* 0x000000051d1d7c07 */
/* 0x000fca000c800000 */
/*0940*/ IMAD R29, R13, c[0x0][0x168], R29 ; /* 0x00005a000d1d7a24 */
/* 0x000fc800078e021d */
/*0950*/ IMAD.WIDE R16, R29, R18, c[0x0][0x160] ; /* 0x000058001d107625 */
/* 0x001fca00078e0212 */
/*0960*/ LDG.E.U8 R29, [R16.64] ; /* 0x00000008101d7981 */
/* 0x000ea2000c1e1100 */
/*0970*/ I2F.U16 R25, R28 ; /* 0x0000001c00197306 */
/* 0x008eb00000101000 */
/*0980*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x010e300000101000 */
/*0990*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x020e620000101000 */
/*09a0*/ FFMA R19, R24, R25, R19 ; /* 0x0000001918137223 */
/* 0x004fc40000000013 */
/*09b0*/ FFMA R21, R26, R24, R21 ; /* 0x000000181a157223 */
/* 0x001fe40000000015 */
/*09c0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ FFMA R20, R24, R27, R20 ; /* 0x0000001b18147223 */
/* 0x002fc60000000014 */
/*09e0*/ LDG.E.U8 R24, [R16.64+0x1] ; /* 0x0000010810187981 */
/* 0x000ee8000c1e1100 */
/*09f0*/ LDG.E.U8 R27, [R16.64+0x2] ; /* 0x00000208101b7981 */
/* 0x000f22000c1e1100 */
/*0a00*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007ffe0ff */
/*0a10*/ I2F.U16 R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000ea60000101000 */
/*0a20*/ ISETP.GE.AND P1, PT, R23, R2, PT ; /* 0x000000021700720c */
/* 0x000fe40003f26270 */
/*0a30*/ IADD3 R28, R22, 0x4, RZ ; /* 0x00000004161c7810 */
/* 0x000fc60007ffe0ff */
/*0a40*/ I2F.U16 R25, R24 ; /* 0x0000001800197306 */
/* 0x0080700000101000 */
/*0a50*/ I2F.U16 R27, R27 ; /* 0x0000001b001b7306 */
/* 0x010ee20000101000 */
/*0a60*/ IADD3 R24, P2, R14, 0x10, RZ ; /* 0x000000100e187810 */
/* 0x001fe20007f5e0ff */
/*0a70*/ FFMA R21, R29, R26, R21 ; /* 0x0000001a1d157223 */
/* 0x004fe20000000015 */
/*0a80*/ IADD3 R14, R22, 0x1, RZ ; /* 0x00000001160e7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.MOV.U32 R22, RZ, RZ, R28 ; /* 0x000000ffff167224 */
/* 0x000fc400078e001c */
/*0aa0*/ FFMA R20, R26.reuse, R25, R20 ; /* 0x000000191a147223 */
/* 0x042fe20000000014 */
/*0ab0*/ IADD3.X R25, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff197210 */
/* 0x000fe200017fe4ff */
/*0ac0*/ FFMA R19, R26, R27, R19 ; /* 0x0000001b1a137223 */
/* 0x008fe20000000013 */
/*0ad0*/ @!P1 BRA 0x660 ; /* 0xfffffb8000009947 */
/* 0x000fea000383ffff */
/*0ae0*/ @!P0 BRA 0x2a0 ; /* 0xfffff7b000008947 */
/* 0x000fea000383ffff */
/*0af0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e22000020f100 */
/*0b00*/ HFMA2.MMA R2, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff027435 */
/* 0x000fe200000001ff */
/*0b10*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fcc00078e0203 */
/*0b20*/ F2I.TRUNC.NTZ R5, R20 ; /* 0x0000001400057305 */
/* 0x000e66000020f100 */
/*0b30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0b40*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000ea2000020f100 */
/*0b50*/ STG.E.U8 [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x001fe8000c101108 */
/*0b60*/ STG.E.U8 [R2.64+0x1], R5 ; /* 0x0000010502007986 */
/* 0x002fe8000c101108 */
/*0b70*/ STG.E.U8 [R2.64+0x2], R19 ; /* 0x0000021302007986 */
/* 0x004fe2000c101108 */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.globl _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.p2align 8
.type _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_,@function
_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v1, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s10, s[0:1], 0x18
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, -1
s_cbranch_scc1 .LBB0_8
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_lshr_b32 s8, s10, 31
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_add_i32 s8, s10, s8
v_mov_b32_e32 v4, 0
s_ashr_i32 s8, s8, 1
s_add_i32 s12, s5, -1
s_abs_i32 s13, s8
v_subrev_nc_u32_e32 v3, s8, v1
s_add_i32 s16, s8, s13
s_sub_i32 s14, 0, s8
s_add_i32 s15, s4, -1
s_add_i32 s16, s16, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v6, s14, v0
s_mov_b32 s8, s11
s_mov_b32 s17, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v6, 0, v6
v_cmp_gt_i32_e32 vcc_lo, s5, v6
v_cndmask_b32_e32 v6, s12, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v6, v6, s4
.p2align 6
.LBB0_4:
v_max_i32_e32 v8, 0, v7
s_ashr_i32 s9, s8, 31
v_add_nc_u32_e32 v7, 1, v7
s_lshl_b64 s[18:19], s[8:9], 2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v8
s_waitcnt lgkmcnt(0)
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_add_i32 s17, s17, -1
s_add_i32 s8, s8, 1
v_cndmask_b32_e32 v8, s15, v8, vcc_lo
s_cmp_eq_u32 s17, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, v8, v6
v_mad_i64_i32 v[8:9], null, v10, 3, s[2:3]
s_clause 0x2
global_load_u8 v10, v[8:9], off
global_load_u8 v11, v[8:9], off offset:1
global_load_u8 v8, v[8:9], off offset:2
s_load_b32 s9, s[18:19], 0x0
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v9, v10
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v10, v11
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v8, v8
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, s9, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_fmac_f32 v4, s9, v10 :: v_dual_fmac_f32 v5, s9, v8
s_cbranch_scc0 .LBB0_4
s_add_i32 s8, s14, 1
s_add_i32 s11, s11, s10
s_cmp_eq_u32 s14, s13
s_cbranch_scc1 .LBB0_7
s_mov_b32 s14, s8
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
v_cvt_i32_f32_e32 v2, v2
v_cvt_i32_f32_e32 v3, v4
v_cvt_i32_f32_e32 v4, v5
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v5, 3, s[0:1]
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v3, off offset:1
global_store_b8 v[0:1], v4, off offset:2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, .Lfunc_end0-_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ void timeTest1(int *a){
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
*a +=5;
}
}
__global__ void timeTest() {
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
int a = 0;
for(int i = 0; i < 10000000; i++){
timeTest1(&a);
}
}
} | code for sm_80
Function : _Z8timeTestv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void timeTest1(int *a){
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
*a +=5;
}
}
__global__ void timeTest() {
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
int a = 0;
for(int i = 0; i < 10000000; i++){
timeTest1(&a);
}
}
} | .file "tmpxft_00096ce8_00000000-6_timeTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9timeTest1Pi
.type _Z9timeTest1Pi, @function
_Z9timeTest1Pi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9timeTest1Pi, .-_Z9timeTest1Pi
.globl _Z26__device_stub__Z8timeTestvv
.type _Z26__device_stub__Z8timeTestvv, @function
_Z26__device_stub__Z8timeTestvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8timeTestv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z8timeTestvv, .-_Z26__device_stub__Z8timeTestvv
.globl _Z8timeTestv
.type _Z8timeTestv, @function
_Z8timeTestv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8timeTestvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8timeTestv, .-_Z8timeTestv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8timeTestv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8timeTestv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void timeTest1(int *a){
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
*a +=5;
}
}
__global__ void timeTest() {
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
int a = 0;
for(int i = 0; i < 10000000; i++){
timeTest1(&a);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void timeTest1(int *a){
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
*a +=5;
}
}
__global__ void timeTest() {
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
int a = 0;
for(int i = 0; i < 10000000; i++){
timeTest1(&a);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void timeTest1(int *a){
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
*a +=5;
}
}
__global__ void timeTest() {
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
int a = 0;
for(int i = 0; i < 10000000; i++){
timeTest1(&a);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8timeTestv
.globl _Z8timeTestv
.p2align 8
.type _Z8timeTestv,@function
_Z8timeTestv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8timeTestv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8timeTestv, .Lfunc_end0-_Z8timeTestv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8timeTestv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8timeTestv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void timeTest1(int *a){
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
*a +=5;
}
}
__global__ void timeTest() {
int t_index = threadIdx.x + (blockIdx.x * blockDim.x);
if (t_index < SIZE) {
int a = 0;
for(int i = 0; i < 10000000; i++){
timeTest1(&a);
}
}
} | .text
.file "timeTest.hip"
.globl _Z23__device_stub__timeTestv # -- Begin function _Z23__device_stub__timeTestv
.p2align 4, 0x90
.type _Z23__device_stub__timeTestv,@function
_Z23__device_stub__timeTestv: # @_Z23__device_stub__timeTestv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8timeTestv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__timeTestv, .Lfunc_end0-_Z23__device_stub__timeTestv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8timeTestv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8timeTestv,@object # @_Z8timeTestv
.section .rodata,"a",@progbits
.globl _Z8timeTestv
.p2align 3, 0x0
_Z8timeTestv:
.quad _Z23__device_stub__timeTestv
.size _Z8timeTestv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8timeTestv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__timeTestv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8timeTestv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8timeTestv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8timeTestv
.globl _Z8timeTestv
.p2align 8
.type _Z8timeTestv,@function
_Z8timeTestv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8timeTestv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8timeTestv, .Lfunc_end0-_Z8timeTestv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8timeTestv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8timeTestv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00096ce8_00000000-6_timeTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9timeTest1Pi
.type _Z9timeTest1Pi, @function
_Z9timeTest1Pi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9timeTest1Pi, .-_Z9timeTest1Pi
.globl _Z26__device_stub__Z8timeTestvv
.type _Z26__device_stub__Z8timeTestvv, @function
_Z26__device_stub__Z8timeTestvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8timeTestv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z8timeTestvv, .-_Z26__device_stub__Z8timeTestvv
.globl _Z8timeTestv
.type _Z8timeTestv, @function
_Z8timeTestv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8timeTestvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8timeTestv, .-_Z8timeTestv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8timeTestv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8timeTestv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "timeTest.hip"
.globl _Z23__device_stub__timeTestv # -- Begin function _Z23__device_stub__timeTestv
.p2align 4, 0x90
.type _Z23__device_stub__timeTestv,@function
_Z23__device_stub__timeTestv: # @_Z23__device_stub__timeTestv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8timeTestv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__timeTestv, .Lfunc_end0-_Z23__device_stub__timeTestv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8timeTestv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8timeTestv,@object # @_Z8timeTestv
.section .rodata,"a",@progbits
.globl _Z8timeTestv
.p2align 3, 0x0
_Z8timeTestv:
.quad _Z23__device_stub__timeTestv
.size _Z8timeTestv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8timeTestv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__timeTestv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8timeTestv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define EPS 1e-8
#define N 10000000
#define MAX_ERR 1e-6
//#define nb 23814 //no. of n bodies
//#define nb 1350
//#define nb 294
//#define nb 5766
//#define p 31 //no of threads in each block
#define PI 3.14159265358979323846
#define PIx8 25.132741228718345
extern "C" __device__ double smoothfun2(double x)
{
double a = erf(x);
double b = (4.0*x*x*x*x - 14.0*x*x + 3.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double smoothfun1(double x)
{
double a = erf(x);
double b = (2.0*x*x - 5.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double3 bodyBodyInteractionStokes(double3 bi, double3 bj, double3 fj, double3 ai, double delta)
{
//TODO: add delta parameter as input reg parameter
//33 FLOP ; change this to include regularization
//fj in shared memory too, fj has SL density,pou, area element, mesh size already in it
double3 r;
//double delta = 0.1114403363930094; //0.20795502088527543; //0.38805779048337563;
//delta = 0.20795502088527543; //0.38805779048337563;
//double delta = 0.38805779048337563;
r.x = bj.x - bi.x;
r.y = bj.y - bi.y;
r.z = bj.z - bi.z;
double distSqr_zc; //zero corrected
double distSqr = r.x *r.x + r.y*r.y + r.z*r.z;
distSqr_zc = distSqr;
if(distSqr <= 0.0) distSqr_zc = 1.0;
double dist = sqrt(distSqr);
double distSixth = distSqr_zc*distSqr_zc*distSqr_zc;
double invDistCube = 1.0/sqrt(distSixth);
double invDist = 1.0/sqrt(distSqr_zc);
double fdotr = fj.x*r.x + fj.y*r.y + fj.z*r.z;
double s1 = invDist*smoothfun1(dist/delta); //smoothing function 1
double s2 = fdotr*invDistCube*smoothfun2(dist/delta); //smoothing function 2
if(distSqr<=0.0)
{
s1 = 16.0/(3*sqrt(M_PI)*delta);
s2 = fdotr*32.0/(3*sqrt(M_PI)*delta*delta*delta);
}
//ai.x += fj.x*s1;
//ai.y += fj.y*s1;
//ai.z += fj.z*s1;
ai.x += fj.x*s1 + r.x*s2;
ai.y += fj.y*s1 + r.y*s2;
ai.z += fj.z*s1 + r.z*s2;
return ai;
}
extern "C" __global__ void calculate_forces_stokes(void *devX, void *devY, void *devF, void *devA, void *delta, int nb_x, int p_x, int nb_y, int p_y)
{
//devX is target points, devY is source points
//extern __shared__ float3 shPosition[];
//extern __shared__ float3 shDensity[];
extern __shared__ double3 shPosDen[];
double3 *globalX = (double3 *)devX;
double3 *globalY = (double3 *)devY;
double3 *globalF = (double3 *)devF; //SL density
double3 *globalA = (double3 *)devA;
double *globalDelta = (double *)delta; //reg parameter
double3 myPosition;
double myDelta;
int i, tile;
double3 acc = {0.0, 0.0, 0.0};
int gtid;
gtid = blockIdx.x * blockDim.x + threadIdx.x;
myPosition = globalX[gtid];
myDelta = globalDelta[gtid];
for(i=0, tile=0; i< nb_y; i+=p_y, tile++)
{
int idx = tile*blockDim.x + threadIdx.x;
//shPosition[threadIdx.x] = globalX[idx];
//shDensity[threadIdx.x] = globalF[idx];
shPosDen[2*threadIdx.x+0] = globalY[idx];
shPosDen[2*threadIdx.x+1] = globalF[idx];
__syncthreads();
//acc = tile_calculation(myPosition, acc);
#pragma unroll
for(unsigned int counter = 0; counter < p_y; counter++)
{
acc = bodyBodyInteractionStokes(myPosition, shPosDen[2*counter+0], shPosDen[2*counter+1], acc, myDelta);
}
__syncthreads();
}
//save result in global memory
double3 acc3 = {1.0/(8*M_PI)*acc.x, 1.0/(8*M_PI)*acc.y, 1.0/(8*M_PI)*acc.z};
globalA[gtid] = acc3;
} | .file "tmpxft_000636af_00000000-6_stokesSourceTarget.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl smoothfun2
.type smoothfun2, @function
smoothfun2:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size smoothfun2, .-smoothfun2
.globl smoothfun1
.type smoothfun1, @function
smoothfun1:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size smoothfun1, .-smoothfun1
.globl bodyBodyInteractionStokes
.type bodyBodyInteractionStokes, @function
bodyBodyInteractionStokes:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size bodyBodyInteractionStokes, .-bodyBodyInteractionStokes
.globl _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii
.type _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii, @function
_Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq calculate_forces_stokes(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii, .-_Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii
.globl calculate_forces_stokes
.type calculate_forces_stokes, @function
calculate_forces_stokes:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size calculate_forces_stokes, .-calculate_forces_stokes
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "calculate_forces_stokes"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq calculate_forces_stokes(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define EPS 1e-8
#define N 10000000
#define MAX_ERR 1e-6
//#define nb 23814 //no. of n bodies
//#define nb 1350
//#define nb 294
//#define nb 5766
//#define p 31 //no of threads in each block
#define PI 3.14159265358979323846
#define PIx8 25.132741228718345
extern "C" __device__ double smoothfun2(double x)
{
double a = erf(x);
double b = (4.0*x*x*x*x - 14.0*x*x + 3.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double smoothfun1(double x)
{
double a = erf(x);
double b = (2.0*x*x - 5.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double3 bodyBodyInteractionStokes(double3 bi, double3 bj, double3 fj, double3 ai, double delta)
{
//TODO: add delta parameter as input reg parameter
//33 FLOP ; change this to include regularization
//fj in shared memory too, fj has SL density,pou, area element, mesh size already in it
double3 r;
//double delta = 0.1114403363930094; //0.20795502088527543; //0.38805779048337563;
//delta = 0.20795502088527543; //0.38805779048337563;
//double delta = 0.38805779048337563;
r.x = bj.x - bi.x;
r.y = bj.y - bi.y;
r.z = bj.z - bi.z;
double distSqr_zc; //zero corrected
double distSqr = r.x *r.x + r.y*r.y + r.z*r.z;
distSqr_zc = distSqr;
if(distSqr <= 0.0) distSqr_zc = 1.0;
double dist = sqrt(distSqr);
double distSixth = distSqr_zc*distSqr_zc*distSqr_zc;
double invDistCube = 1.0/sqrt(distSixth);
double invDist = 1.0/sqrt(distSqr_zc);
double fdotr = fj.x*r.x + fj.y*r.y + fj.z*r.z;
double s1 = invDist*smoothfun1(dist/delta); //smoothing function 1
double s2 = fdotr*invDistCube*smoothfun2(dist/delta); //smoothing function 2
if(distSqr<=0.0)
{
s1 = 16.0/(3*sqrt(M_PI)*delta);
s2 = fdotr*32.0/(3*sqrt(M_PI)*delta*delta*delta);
}
//ai.x += fj.x*s1;
//ai.y += fj.y*s1;
//ai.z += fj.z*s1;
ai.x += fj.x*s1 + r.x*s2;
ai.y += fj.y*s1 + r.y*s2;
ai.z += fj.z*s1 + r.z*s2;
return ai;
}
extern "C" __global__ void calculate_forces_stokes(void *devX, void *devY, void *devF, void *devA, void *delta, int nb_x, int p_x, int nb_y, int p_y)
{
//devX is target points, devY is source points
//extern __shared__ float3 shPosition[];
//extern __shared__ float3 shDensity[];
extern __shared__ double3 shPosDen[];
double3 *globalX = (double3 *)devX;
double3 *globalY = (double3 *)devY;
double3 *globalF = (double3 *)devF; //SL density
double3 *globalA = (double3 *)devA;
double *globalDelta = (double *)delta; //reg parameter
double3 myPosition;
double myDelta;
int i, tile;
double3 acc = {0.0, 0.0, 0.0};
int gtid;
gtid = blockIdx.x * blockDim.x + threadIdx.x;
myPosition = globalX[gtid];
myDelta = globalDelta[gtid];
for(i=0, tile=0; i< nb_y; i+=p_y, tile++)
{
int idx = tile*blockDim.x + threadIdx.x;
//shPosition[threadIdx.x] = globalX[idx];
//shDensity[threadIdx.x] = globalF[idx];
shPosDen[2*threadIdx.x+0] = globalY[idx];
shPosDen[2*threadIdx.x+1] = globalF[idx];
__syncthreads();
//acc = tile_calculation(myPosition, acc);
#pragma unroll
for(unsigned int counter = 0; counter < p_y; counter++)
{
acc = bodyBodyInteractionStokes(myPosition, shPosDen[2*counter+0], shPosDen[2*counter+1], acc, myDelta);
}
__syncthreads();
}
//save result in global memory
double3 acc3 = {1.0/(8*M_PI)*acc.x, 1.0/(8*M_PI)*acc.y, 1.0/(8*M_PI)*acc.z};
globalA[gtid] = acc3;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define EPS 1e-8
#define N 10000000
#define MAX_ERR 1e-6
//#define nb 23814 //no. of n bodies
//#define nb 1350
//#define nb 294
//#define nb 5766
//#define p 31 //no of threads in each block
#define PI 3.14159265358979323846
#define PIx8 25.132741228718345
extern "C" __device__ double smoothfun2(double x)
{
double a = erf(x);
double b = (4.0*x*x*x*x - 14.0*x*x + 3.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double smoothfun1(double x)
{
double a = erf(x);
double b = (2.0*x*x - 5.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double3 bodyBodyInteractionStokes(double3 bi, double3 bj, double3 fj, double3 ai, double delta)
{
//TODO: add delta parameter as input reg parameter
//33 FLOP ; change this to include regularization
//fj in shared memory too, fj has SL density,pou, area element, mesh size already in it
double3 r;
//double delta = 0.1114403363930094; //0.20795502088527543; //0.38805779048337563;
//delta = 0.20795502088527543; //0.38805779048337563;
//double delta = 0.38805779048337563;
r.x = bj.x - bi.x;
r.y = bj.y - bi.y;
r.z = bj.z - bi.z;
double distSqr_zc; //zero corrected
double distSqr = r.x *r.x + r.y*r.y + r.z*r.z;
distSqr_zc = distSqr;
if(distSqr <= 0.0) distSqr_zc = 1.0;
double dist = sqrt(distSqr);
double distSixth = distSqr_zc*distSqr_zc*distSqr_zc;
double invDistCube = 1.0/sqrt(distSixth);
double invDist = 1.0/sqrt(distSqr_zc);
double fdotr = fj.x*r.x + fj.y*r.y + fj.z*r.z;
double s1 = invDist*smoothfun1(dist/delta); //smoothing function 1
double s2 = fdotr*invDistCube*smoothfun2(dist/delta); //smoothing function 2
if(distSqr<=0.0)
{
s1 = 16.0/(3*sqrt(M_PI)*delta);
s2 = fdotr*32.0/(3*sqrt(M_PI)*delta*delta*delta);
}
//ai.x += fj.x*s1;
//ai.y += fj.y*s1;
//ai.z += fj.z*s1;
ai.x += fj.x*s1 + r.x*s2;
ai.y += fj.y*s1 + r.y*s2;
ai.z += fj.z*s1 + r.z*s2;
return ai;
}
extern "C" __global__ void calculate_forces_stokes(void *devX, void *devY, void *devF, void *devA, void *delta, int nb_x, int p_x, int nb_y, int p_y)
{
//devX is target points, devY is source points
//extern __shared__ float3 shPosition[];
//extern __shared__ float3 shDensity[];
extern __shared__ double3 shPosDen[];
double3 *globalX = (double3 *)devX;
double3 *globalY = (double3 *)devY;
double3 *globalF = (double3 *)devF; //SL density
double3 *globalA = (double3 *)devA;
double *globalDelta = (double *)delta; //reg parameter
double3 myPosition;
double myDelta;
int i, tile;
double3 acc = {0.0, 0.0, 0.0};
int gtid;
gtid = blockIdx.x * blockDim.x + threadIdx.x;
myPosition = globalX[gtid];
myDelta = globalDelta[gtid];
for(i=0, tile=0; i< nb_y; i+=p_y, tile++)
{
int idx = tile*blockDim.x + threadIdx.x;
//shPosition[threadIdx.x] = globalX[idx];
//shDensity[threadIdx.x] = globalF[idx];
shPosDen[2*threadIdx.x+0] = globalY[idx];
shPosDen[2*threadIdx.x+1] = globalF[idx];
__syncthreads();
//acc = tile_calculation(myPosition, acc);
#pragma unroll
for(unsigned int counter = 0; counter < p_y; counter++)
{
acc = bodyBodyInteractionStokes(myPosition, shPosDen[2*counter+0], shPosDen[2*counter+1], acc, myDelta);
}
__syncthreads();
}
//save result in global memory
double3 acc3 = {1.0/(8*M_PI)*acc.x, 1.0/(8*M_PI)*acc.y, 1.0/(8*M_PI)*acc.z};
globalA[gtid] = acc3;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define EPS 1e-8
#define N 10000000
#define MAX_ERR 1e-6
//#define nb 23814 //no. of n bodies
//#define nb 1350
//#define nb 294
//#define nb 5766
//#define p 31 //no of threads in each block
#define PI 3.14159265358979323846
#define PIx8 25.132741228718345
extern "C" __device__ double smoothfun2(double x)
{
double a = erf(x);
double b = (4.0*x*x*x*x - 14.0*x*x + 3.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double smoothfun1(double x)
{
double a = erf(x);
double b = (2.0*x*x - 5.0);
double c = -(2.0/3.0)*x*b*exp(-1.0*x*x)*(1.0/sqrt(M_PI));
return a+c;
}
extern "C" __device__ double3 bodyBodyInteractionStokes(double3 bi, double3 bj, double3 fj, double3 ai, double delta)
{
//TODO: add delta parameter as input reg parameter
//33 FLOP ; change this to include regularization
//fj in shared memory too, fj has SL density,pou, area element, mesh size already in it
double3 r;
//double delta = 0.1114403363930094; //0.20795502088527543; //0.38805779048337563;
//delta = 0.20795502088527543; //0.38805779048337563;
//double delta = 0.38805779048337563;
r.x = bj.x - bi.x;
r.y = bj.y - bi.y;
r.z = bj.z - bi.z;
double distSqr_zc; //zero corrected
double distSqr = r.x *r.x + r.y*r.y + r.z*r.z;
distSqr_zc = distSqr;
if(distSqr <= 0.0) distSqr_zc = 1.0;
double dist = sqrt(distSqr);
double distSixth = distSqr_zc*distSqr_zc*distSqr_zc;
double invDistCube = 1.0/sqrt(distSixth);
double invDist = 1.0/sqrt(distSqr_zc);
double fdotr = fj.x*r.x + fj.y*r.y + fj.z*r.z;
double s1 = invDist*smoothfun1(dist/delta); //smoothing function 1
double s2 = fdotr*invDistCube*smoothfun2(dist/delta); //smoothing function 2
if(distSqr<=0.0)
{
s1 = 16.0/(3*sqrt(M_PI)*delta);
s2 = fdotr*32.0/(3*sqrt(M_PI)*delta*delta*delta);
}
//ai.x += fj.x*s1;
//ai.y += fj.y*s1;
//ai.z += fj.z*s1;
ai.x += fj.x*s1 + r.x*s2;
ai.y += fj.y*s1 + r.y*s2;
ai.z += fj.z*s1 + r.z*s2;
return ai;
}
extern "C" __global__ void calculate_forces_stokes(void *devX, void *devY, void *devF, void *devA, void *delta, int nb_x, int p_x, int nb_y, int p_y)
{
//devX is target points, devY is source points
//extern __shared__ float3 shPosition[];
//extern __shared__ float3 shDensity[];
extern __shared__ double3 shPosDen[];
double3 *globalX = (double3 *)devX;
double3 *globalY = (double3 *)devY;
double3 *globalF = (double3 *)devF; //SL density
double3 *globalA = (double3 *)devA;
double *globalDelta = (double *)delta; //reg parameter
double3 myPosition;
double myDelta;
int i, tile;
double3 acc = {0.0, 0.0, 0.0};
int gtid;
gtid = blockIdx.x * blockDim.x + threadIdx.x;
myPosition = globalX[gtid];
myDelta = globalDelta[gtid];
for(i=0, tile=0; i< nb_y; i+=p_y, tile++)
{
int idx = tile*blockDim.x + threadIdx.x;
//shPosition[threadIdx.x] = globalX[idx];
//shDensity[threadIdx.x] = globalF[idx];
shPosDen[2*threadIdx.x+0] = globalY[idx];
shPosDen[2*threadIdx.x+1] = globalF[idx];
__syncthreads();
//acc = tile_calculation(myPosition, acc);
#pragma unroll
for(unsigned int counter = 0; counter < p_y; counter++)
{
acc = bodyBodyInteractionStokes(myPosition, shPosDen[2*counter+0], shPosDen[2*counter+1], acc, myDelta);
}
__syncthreads();
}
//save result in global memory
double3 acc3 = {1.0/(8*M_PI)*acc.x, 1.0/(8*M_PI)*acc.y, 1.0/(8*M_PI)*acc.z};
globalA[gtid] = acc3;
} | .text
.file "stokesSourceTarget.hip"
.globl __device_stub__calculate_forces_stokes # -- Begin function __device_stub__calculate_forces_stokes
.p2align 4, 0x90
.type __device_stub__calculate_forces_stokes,@function
__device_stub__calculate_forces_stokes: # @__device_stub__calculate_forces_stokes
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $calculate_forces_stokes, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__calculate_forces_stokes, .Lfunc_end0-__device_stub__calculate_forces_stokes
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $calculate_forces_stokes, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type calculate_forces_stokes,@object # @calculate_forces_stokes
.section .rodata,"a",@progbits
.globl calculate_forces_stokes
.p2align 3, 0x0
calculate_forces_stokes:
.quad __device_stub__calculate_forces_stokes
.size calculate_forces_stokes, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "calculate_forces_stokes"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__calculate_forces_stokes
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym calculate_forces_stokes
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000636af_00000000-6_stokesSourceTarget.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl smoothfun2
.type smoothfun2, @function
smoothfun2:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size smoothfun2, .-smoothfun2
.globl smoothfun1
.type smoothfun1, @function
smoothfun1:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size smoothfun1, .-smoothfun1
.globl bodyBodyInteractionStokes
.type bodyBodyInteractionStokes, @function
bodyBodyInteractionStokes:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size bodyBodyInteractionStokes, .-bodyBodyInteractionStokes
.globl _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii
.type _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii, @function
_Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq calculate_forces_stokes(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii, .-_Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii
.globl calculate_forces_stokes
.type calculate_forces_stokes, @function
calculate_forces_stokes:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z55__device_stub__Z23calculate_forces_stokesPvS_S_S_S_iiiiPvS_S_S_S_iiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size calculate_forces_stokes, .-calculate_forces_stokes
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "calculate_forces_stokes"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq calculate_forces_stokes(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stokesSourceTarget.hip"
.globl __device_stub__calculate_forces_stokes # -- Begin function __device_stub__calculate_forces_stokes
.p2align 4, 0x90
.type __device_stub__calculate_forces_stokes,@function
__device_stub__calculate_forces_stokes: # @__device_stub__calculate_forces_stokes
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $calculate_forces_stokes, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__calculate_forces_stokes, .Lfunc_end0-__device_stub__calculate_forces_stokes
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $calculate_forces_stokes, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type calculate_forces_stokes,@object # @calculate_forces_stokes
.section .rodata,"a",@progbits
.globl calculate_forces_stokes
.p2align 3, 0x0
calculate_forces_stokes:
.quad __device_stub__calculate_forces_stokes
.size calculate_forces_stokes, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "calculate_forces_stokes"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__calculate_forces_stokes
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym calculate_forces_stokes
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void d_putgaps(float *sne7, float *snaw, int *aw2ali, const int snno)
{
//sino index
int sni = threadIdx.x + blockIdx.y*blockDim.x;
//sino bin index
int awi = blockIdx.x;
if (sni<snno) {
sne7[aw2ali[awi] * snno + sni] = snaw[awi*snno + sni];
}
} | code for sm_80
Function : _Z9d_putgapsPfS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R4, R3, R7, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x001fc800078e0207 */
/*00a0*/ IMAD R2, R3, c[0x0][0x178], R0 ; /* 0x00005e0003027a24 */
/* 0x000fe400078e0200 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ IMAD R6, R5, c[0x0][0x178], R0 ; /* 0x00005e0005067a24 */
/* 0x004fc800078e0200 */
/*00f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0207 */
/*0100*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x008fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void d_putgaps(float *sne7, float *snaw, int *aw2ali, const int snno)
{
//sino index
int sni = threadIdx.x + blockIdx.y*blockDim.x;
//sino bin index
int awi = blockIdx.x;
if (sni<snno) {
sne7[aw2ali[awi] * snno + sni] = snaw[awi*snno + sni];
}
} | .file "tmpxft_0001b74d_00000000-6_d_putgaps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii
.type _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii, @function
_Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9d_putgapsPfS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii, .-_Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii
.globl _Z9d_putgapsPfS_Pii
.type _Z9d_putgapsPfS_Pii, @function
_Z9d_putgapsPfS_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9d_putgapsPfS_Pii, .-_Z9d_putgapsPfS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9d_putgapsPfS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9d_putgapsPfS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void d_putgaps(float *sne7, float *snaw, int *aw2ali, const int snno)
{
//sino index
int sni = threadIdx.x + blockIdx.y*blockDim.x;
//sino bin index
int awi = blockIdx.x;
if (sni<snno) {
sne7[aw2ali[awi] * snno + sni] = snaw[awi*snno + sni];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void d_putgaps(float *sne7, float *snaw, int *aw2ali, const int snno)
{
//sino index
int sni = threadIdx.x + blockIdx.y*blockDim.x;
//sino bin index
int awi = blockIdx.x;
if (sni<snno) {
sne7[aw2ali[awi] * snno + sni] = snaw[awi*snno + sni];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void d_putgaps(float *sne7, float *snaw, int *aw2ali, const int snno)
{
//sino index
int sni = threadIdx.x + blockIdx.y*blockDim.x;
//sino bin index
int awi = blockIdx.x;
if (sni<snno) {
sne7[aw2ali[awi] * snno + sni] = snaw[awi*snno + sni];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9d_putgapsPfS_Pii
.globl _Z9d_putgapsPfS_Pii
.p2align 8
.type _Z9d_putgapsPfS_Pii,@function
_Z9d_putgapsPfS_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s15, s14, 31
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_lshl_b64 s[6:7], s[14:15], 2
s_add_u32 s0, s0, s6
global_load_b32 v4, v[2:3], off
s_addc_u32 s1, s1, s7
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9d_putgapsPfS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9d_putgapsPfS_Pii, .Lfunc_end0-_Z9d_putgapsPfS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9d_putgapsPfS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9d_putgapsPfS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void d_putgaps(float *sne7, float *snaw, int *aw2ali, const int snno)
{
//sino index
int sni = threadIdx.x + blockIdx.y*blockDim.x;
//sino bin index
int awi = blockIdx.x;
if (sni<snno) {
sne7[aw2ali[awi] * snno + sni] = snaw[awi*snno + sni];
}
} | .text
.file "d_putgaps.hip"
.globl _Z24__device_stub__d_putgapsPfS_Pii # -- Begin function _Z24__device_stub__d_putgapsPfS_Pii
.p2align 4, 0x90
.type _Z24__device_stub__d_putgapsPfS_Pii,@function
_Z24__device_stub__d_putgapsPfS_Pii: # @_Z24__device_stub__d_putgapsPfS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9d_putgapsPfS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__d_putgapsPfS_Pii, .Lfunc_end0-_Z24__device_stub__d_putgapsPfS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9d_putgapsPfS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9d_putgapsPfS_Pii,@object # @_Z9d_putgapsPfS_Pii
.section .rodata,"a",@progbits
.globl _Z9d_putgapsPfS_Pii
.p2align 3, 0x0
_Z9d_putgapsPfS_Pii:
.quad _Z24__device_stub__d_putgapsPfS_Pii
.size _Z9d_putgapsPfS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9d_putgapsPfS_Pii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__d_putgapsPfS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9d_putgapsPfS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9d_putgapsPfS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R4, R3, R7, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x001fc800078e0207 */
/*00a0*/ IMAD R2, R3, c[0x0][0x178], R0 ; /* 0x00005e0003027a24 */
/* 0x000fe400078e0200 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ IMAD R6, R5, c[0x0][0x178], R0 ; /* 0x00005e0005067a24 */
/* 0x004fc800078e0200 */
/*00f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0207 */
/*0100*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x008fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9d_putgapsPfS_Pii
.globl _Z9d_putgapsPfS_Pii
.p2align 8
.type _Z9d_putgapsPfS_Pii,@function
_Z9d_putgapsPfS_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s15, s14, 31
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_lshl_b64 s[6:7], s[14:15], 2
s_add_u32 s0, s0, s6
global_load_b32 v4, v[2:3], off
s_addc_u32 s1, s1, s7
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9d_putgapsPfS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9d_putgapsPfS_Pii, .Lfunc_end0-_Z9d_putgapsPfS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9d_putgapsPfS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9d_putgapsPfS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b74d_00000000-6_d_putgaps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii
.type _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii, @function
_Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9d_putgapsPfS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii, .-_Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii
.globl _Z9d_putgapsPfS_Pii
.type _Z9d_putgapsPfS_Pii, @function
_Z9d_putgapsPfS_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9d_putgapsPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9d_putgapsPfS_Pii, .-_Z9d_putgapsPfS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9d_putgapsPfS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9d_putgapsPfS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "d_putgaps.hip"
.globl _Z24__device_stub__d_putgapsPfS_Pii # -- Begin function _Z24__device_stub__d_putgapsPfS_Pii
.p2align 4, 0x90
.type _Z24__device_stub__d_putgapsPfS_Pii,@function
_Z24__device_stub__d_putgapsPfS_Pii: # @_Z24__device_stub__d_putgapsPfS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9d_putgapsPfS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__d_putgapsPfS_Pii, .Lfunc_end0-_Z24__device_stub__d_putgapsPfS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9d_putgapsPfS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9d_putgapsPfS_Pii,@object # @_Z9d_putgapsPfS_Pii
.section .rodata,"a",@progbits
.globl _Z9d_putgapsPfS_Pii
.p2align 3, 0x0
_Z9d_putgapsPfS_Pii:
.quad _Z24__device_stub__d_putgapsPfS_Pii
.size _Z9d_putgapsPfS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9d_putgapsPfS_Pii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__d_putgapsPfS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9d_putgapsPfS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#define TILE_SIZE 4
#define INPUT_SIZE 12
#define MASK_WIDTH 5
__constant__ float M[MASK_WIDTH];
__global__ void convolution_shared_memory(float *N, float *P){
int i = blockIdx.x*blockDim.x+threadIdx.x;
__shared__ float N_s[TILE_SIZE];
N_s[threadIdx.x]=N[i];
__syncthreads();
int this_title_start_point = blockIdx.x*blockDim.x;
int next_tile_start_point = (blockIdx.x+1)*blockDim.x;
int n_start_point = i-(MASK_WIDTH/2);
float Pvalue = 0;
for(int j =0; j < MASK_WIDTH; j++){
int N_index = n_start_point+j;
if(N_index >= 0 && N_index < INPUT_SIZE){
if((N_index >= this_title_start_point) && (N_index < next_tile_start_point)){
Pvalue+=N_s[threadIdx.x+j-(MASK_WIDTH/2)]*M[j];
}
else{
Pvalue+=N[N_index]*M[j];
}
}
}
P[i]=Pvalue;
}
__global__ void convolution_constant_memory(float *N, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
__global__ void convolution_global_memory(float *N, float *M, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
int main(){
//device input and output
float *d_N = 0;
float *d_P = 0;
cudaMalloc(&d_N,INPUT_SIZE*sizeof(float));
cudaMalloc(&d_P,INPUT_SIZE*sizeof(float));
//host input and output
float *h_N = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_P = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_M = (float*)malloc(MASK_WIDTH*sizeof(float));
//initialize input on host
for(int i=0;i<INPUT_SIZE;++i){
h_N[i]=(float)i;
}
//transfer input to device
cudaMemcpy(d_N,h_N,INPUT_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_P,h_P,INPUT_SIZE*sizeof(float),cudaMemcpyHostToDevice);
//initialize mask on host
for(int j=0;j<MASK_WIDTH;++j){
h_M[j]=(float)j;
}
//transfer mask to constant memory
cudaMemcpyToSymbol(M,h_M,MASK_WIDTH*sizeof(float));
//call convolution kernel
convolution_shared_memory<<<(INPUT_SIZE+TILE_SIZE-1)/TILE_SIZE,TILE_SIZE >>>(d_N,d_P);
//retrieve result from device
cudaMemcpy(h_P,d_P,INPUT_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
for(int i=0; i<INPUT_SIZE;++i){
printf("%f\n", h_P[i]);
}
cudaFree(d_N);
cudaFree(d_P);
cudaFree(M);
free(h_N);
free(h_P);
free(h_M);
} | code for sm_80
Function : _Z25convolution_global_memoryPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE R2, R6.reuse, R17, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe200078e0211 */
/*0090*/ IADD3 R0, R6.reuse, -0x2, RZ ; /* 0xfffffffe06007810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ ISETP.GT.AND P2, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f44270 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06270 */
/*00c0*/ IADD3 R0, R6.reuse, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.LT.OR P0, PT, R6.reuse, 0x2, P0 ; /* 0x000000020600780c */
/* 0x040fe40000701670 */
/*00e0*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc40003f26270 */
/*00f0*/ ISETP.LT.OR P2, PT, R6, 0x1, P2 ; /* 0x000000010600780c */
/* 0x000fe40001741670 */
/*0100*/ ISETP.GE.AND P4, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f86270 */
/*0110*/ IADD3 R0, R6.reuse, 0x2, RZ ; /* 0x0000000206007810 */
/* 0x040fe40007ffe0ff */
/*0120*/ ISETP.LT.OR P1, PT, R6, RZ, P1 ; /* 0x000000ff0600720c */
/* 0x000fe40000f21670 */
/*0130*/ ISETP.GE.AND P3, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f66270 */
/*0140*/ @!P0 LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402078981 */
/* 0x000ea2000c1e1900 */
/*0150*/ ISETP.LT.OR P4, PT, R6, -0x1, P4 ; /* 0xffffffff0600780c */
/* 0x000fc60002781670 */
/*0160*/ @!P0 LDG.E R0, [R4.64] ; /* 0x0000000404008981 */
/* 0x000ea2000c1e1900 */
/*0170*/ ISETP.LT.OR P3, PT, R6, -0x2, P3 ; /* 0xfffffffe0600780c */
/* 0x000fc60001f61670 */
/*0180*/ @!P2 LDG.E R8, [R4.64+0x4] ; /* 0x000004040408a981 */
/* 0x000ee8000c1e1900 */
/*0190*/ @!P2 LDG.E R10, [R2.64+-0x4] ; /* 0xfffffc04020aa981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ @!P1 LDG.E R12, [R2.64] ; /* 0x00000004020c9981 */
/* 0x000f28000c1e1900 */
/*01b0*/ @!P1 LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b9981 */
/* 0x000f28000c1e1900 */
/*01c0*/ @!P4 LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040ec981 */
/* 0x000f68000c1e1900 */
/*01d0*/ @!P4 LDG.E R13, [R2.64+0x4] ; /* 0x00000404020dc981 */
/* 0x000f68000c1e1900 */
/*01e0*/ @!P3 LDG.E R16, [R4.64+0x10] ; /* 0x000010040410b981 */
/* 0x000f68000c1e1900 */
/*01f0*/ @!P3 LDG.E R15, [R2.64+0x8] ; /* 0x00000804020fb981 */
/* 0x000f62000c1e1900 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc400078e00ff */
/*0210*/ @!P0 FFMA R9, R0, R7, RZ ; /* 0x0000000700098223 */
/* 0x004fc800000000ff */
/*0220*/ @!P2 FFMA R9, R8, R10, R9 ; /* 0x0000000a0809a223 */
/* 0x008fc80000000009 */
/*0230*/ @!P1 FFMA R9, R12, R11, R9 ; /* 0x0000000b0c099223 */
/* 0x010fe40000000009 */
/*0240*/ IMAD.WIDE R6, R6, R17, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0211 */
/*0250*/ @!P4 FFMA R9, R14, R13, R9 ; /* 0x0000000d0e09c223 */
/* 0x020fc80000000009 */
/*0260*/ @!P3 FFMA R9, R16, R15, R9 ; /* 0x0000000f1009b223 */
/* 0x000fca0000000009 */
/*0270*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z27convolution_constant_memoryPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R4.reuse, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e0205 */
/*0070*/ IADD3 R0, R4.reuse, -0x2, RZ ; /* 0xfffffffe04007810 */
/* 0x040fe40007ffe0ff */
/*0080*/ ISETP.GT.AND P2, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f44270 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06270 */
/*00a0*/ IADD3 R0, R4.reuse, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ ISETP.LT.OR P0, PT, R4.reuse, 0x2, P0 ; /* 0x000000020400780c */
/* 0x040fe40000701670 */
/*00c0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc40003f26270 */
/*00d0*/ ISETP.LT.OR P2, PT, R4, 0x1, P2 ; /* 0x000000010400780c */
/* 0x000fe40001741670 */
/*00e0*/ ISETP.GE.AND P4, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f86270 */
/*00f0*/ IADD3 R0, R4.reuse, 0x2, RZ ; /* 0x0000000204007810 */
/* 0x040fe40007ffe0ff */
/*0100*/ ISETP.LT.OR P1, PT, R4, RZ, P1 ; /* 0x000000ff0400720c */
/* 0x000fe40000f21670 */
/*0110*/ ISETP.GE.AND P3, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f66270 */
/*0120*/ @!P0 LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402098981 */
/* 0x000ea2000c1e1900 */
/*0130*/ ISETP.LT.OR P4, PT, R4, -0x1, P4 ; /* 0xffffffff0400780c */
/* 0x000fc40002781670 */
/*0140*/ ISETP.LT.OR P3, PT, R4, -0x2, P3 ; /* 0xfffffffe0400780c */
/* 0x000fe20001f61670 */
/*0150*/ @!P2 LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc040200a981 */
/* 0x000eec000c1e1900 */
/*0160*/ @!P1 LDG.E R6, [R2.64] ; /* 0x0000000402069981 */
/* 0x000f28000c1e1900 */
/*0170*/ @!P4 LDG.E R8, [R2.64+0x4] ; /* 0x000004040208c981 */
/* 0x000f68000c1e1900 */
/*0180*/ @!P3 LDG.E R10, [R2.64+0x8] ; /* 0x00000804020ab981 */
/* 0x000f62000c1e1900 */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc400078e00ff */
/*01a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*01b0*/ @!P0 FFMA R7, R9, c[0x3][0x0], RZ ; /* 0x00c0000009078a23 */
/* 0x004fc800000000ff */
/*01c0*/ @!P2 FFMA R7, R0, c[0x3][0x4], R7 ; /* 0x00c001000007aa23 */
/* 0x008fc80000000007 */
/*01d0*/ @!P1 FFMA R7, R6, c[0x3][0x8], R7 ; /* 0x00c0020006079a23 */
/* 0x010fc80000000007 */
/*01e0*/ @!P4 FFMA R7, R8, c[0x3][0xc], R7 ; /* 0x00c003000807ca23 */
/* 0x020fc80000000007 */
/*01f0*/ @!P3 FFMA R7, R10, c[0x3][0x10], R7 ; /* 0x00c004000a07ba23 */
/* 0x000fca0000000007 */
/*0200*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z25convolution_shared_memoryPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fcc000f8e023f */
/*0070*/ IADD3 R0, R9, UR4, RZ ; /* 0x0000000409007c10 */
/* 0x002fca000fffe0ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IADD3 R5, R0, -0x2, RZ ; /* 0xfffffffe00057810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ UIADD3 UR5, UR4, UR5, URZ ; /* 0x0000000504057290 */
/* 0x000fe2000fffe03f */
/*00c0*/ BSSY B0, 0x1c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R5, 0xb, PT ; /* 0x0000000b0500780c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*0100*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @P0 BRA 0x1b0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.AND P0, PT, R5.reuse, UR4, PT ; /* 0x0000000405007c0c */
/* 0x041fe4000bf06270 */
/*0140*/ ISETP.LT.AND P1, PT, R5, UR5, PT ; /* 0x0000000505007c0c */
/* 0x000fda000bf21270 */
/*0150*/ @P0 BRA P1, 0x190 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0160*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80602077981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x004fe200000000ff */
/*0180*/ BRA 0x1b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0190*/ LDS R7, [R9.X4+-0x8] ; /* 0xfffff80009077984 */
/* 0x000e240000004800 */
/*01a0*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x001fe400000000ff */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01c0*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ BSSY B0, 0x290 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R4, 0xb, PT ; /* 0x0000000b0400780c */
/* 0x000fda0003f04070 */
/*01f0*/ @P0 BRA 0x280 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe4000bf04270 */
/*0210*/ ISETP.LE.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf23270 */
/*0220*/ @P0 BRA P1, 0x260 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0230*/ LDG.E R4, [R2.64+-0x4] ; /* 0xfffffc0602047981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R7, R4, c[0x3][0x4], R7 ; /* 0x00c0010004077a23 */
/* 0x004fe20000000007 */
/*0250*/ BRA 0x280 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0260*/ LDS R4, [R9.X4+-0x4] ; /* 0xfffffc0009047984 */
/* 0x000e240000004800 */
/*0270*/ FFMA R7, R4, c[0x3][0x4], R7 ; /* 0x00c0010004077a23 */
/* 0x001fe40000000007 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GT.U32.AND P0, PT, R0, 0xb, PT ; /* 0x0000000b0000780c */
/* 0x000fe20003f04070 */
/*02a0*/ BSSY B0, 0x350 ; /* 0x000000a000007945 */
/* 0x000fd80003800000 */
/*02b0*/ @P0 BRA 0x340 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.GE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe4000bf06270 */
/*02d0*/ ISETP.LT.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf21270 */
/*02e0*/ @P0 BRA P1, 0x320 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*02f0*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R7, R4, c[0x3][0x8], R7 ; /* 0x00c0020004077a23 */
/* 0x004fe20000000007 */
/*0310*/ BRA 0x340 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0320*/ LDS R4, [R9.X4] ; /* 0x0000000009047984 */
/* 0x000e240000004800 */
/*0330*/ FFMA R7, R4, c[0x3][0x8], R7 ; /* 0x00c0020004077a23 */
/* 0x001fe40000000007 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fe20007ffe0ff */
/*0360*/ BSSY B0, 0x420 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0370*/ ISETP.GT.U32.AND P0, PT, R4, 0xb, PT ; /* 0x0000000b0400780c */
/* 0x000fda0003f04070 */
/*0380*/ @P0 BRA 0x410 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R4.reuse, UR4, PT ; /* 0x0000000404007c0c */
/* 0x040fe4000bf06270 */
/*03a0*/ ISETP.LT.AND P1, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fda000bf21270 */
/*03b0*/ @P0 BRA P1, 0x3f0 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*03c0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040602047981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R7, R4, c[0x3][0xc], R7 ; /* 0x00c0030004077a23 */
/* 0x004fe20000000007 */
/*03e0*/ BRA 0x410 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*03f0*/ LDS R4, [R9.X4+0x4] ; /* 0x0000040009047984 */
/* 0x000e240000004800 */
/*0400*/ FFMA R7, R4, c[0x3][0xc], R7 ; /* 0x00c0030004077a23 */
/* 0x001fe40000000007 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0430*/ BSSY B0, 0x4f0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0440*/ ISETP.GT.U32.AND P0, PT, R4, 0xb, PT ; /* 0x0000000b0400780c */
/* 0x000fda0003f04070 */
/*0450*/ @P0 BRA 0x4e0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.GE.AND P0, PT, R4.reuse, UR4, PT ; /* 0x0000000404007c0c */
/* 0x040fe4000bf06270 */
/*0470*/ ISETP.LT.AND P1, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fda000bf21270 */
/*0480*/ @P0 BRA P1, 0x4c0 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0490*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080602027981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ FFMA R7, R2, c[0x3][0x10], R7 ; /* 0x00c0040002077a23 */
/* 0x004fe20000000007 */
/*04b0*/ BRA 0x4e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*04c0*/ LDS R2, [R9.X4+0x8] ; /* 0x0000080009027984 */
/* 0x000e240000004800 */
/*04d0*/ FFMA R7, R2, c[0x3][0x10], R7 ; /* 0x00c0040002077a23 */
/* 0x001fe40000000007 */
/*04e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04f0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0500*/ LEA.HI.X R3, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f140b */
/*0510*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#define TILE_SIZE 4
#define INPUT_SIZE 12
#define MASK_WIDTH 5
__constant__ float M[MASK_WIDTH];
__global__ void convolution_shared_memory(float *N, float *P){
int i = blockIdx.x*blockDim.x+threadIdx.x;
__shared__ float N_s[TILE_SIZE];
N_s[threadIdx.x]=N[i];
__syncthreads();
int this_title_start_point = blockIdx.x*blockDim.x;
int next_tile_start_point = (blockIdx.x+1)*blockDim.x;
int n_start_point = i-(MASK_WIDTH/2);
float Pvalue = 0;
for(int j =0; j < MASK_WIDTH; j++){
int N_index = n_start_point+j;
if(N_index >= 0 && N_index < INPUT_SIZE){
if((N_index >= this_title_start_point) && (N_index < next_tile_start_point)){
Pvalue+=N_s[threadIdx.x+j-(MASK_WIDTH/2)]*M[j];
}
else{
Pvalue+=N[N_index]*M[j];
}
}
}
P[i]=Pvalue;
}
__global__ void convolution_constant_memory(float *N, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
__global__ void convolution_global_memory(float *N, float *M, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
int main(){
//device input and output
float *d_N = 0;
float *d_P = 0;
cudaMalloc(&d_N,INPUT_SIZE*sizeof(float));
cudaMalloc(&d_P,INPUT_SIZE*sizeof(float));
//host input and output
float *h_N = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_P = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_M = (float*)malloc(MASK_WIDTH*sizeof(float));
//initialize input on host
for(int i=0;i<INPUT_SIZE;++i){
h_N[i]=(float)i;
}
//transfer input to device
cudaMemcpy(d_N,h_N,INPUT_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_P,h_P,INPUT_SIZE*sizeof(float),cudaMemcpyHostToDevice);
//initialize mask on host
for(int j=0;j<MASK_WIDTH;++j){
h_M[j]=(float)j;
}
//transfer mask to constant memory
cudaMemcpyToSymbol(M,h_M,MASK_WIDTH*sizeof(float));
//call convolution kernel
convolution_shared_memory<<<(INPUT_SIZE+TILE_SIZE-1)/TILE_SIZE,TILE_SIZE >>>(d_N,d_P);
//retrieve result from device
cudaMemcpy(h_P,d_P,INPUT_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
for(int i=0; i<INPUT_SIZE;++i){
printf("%f\n", h_P[i]);
}
cudaFree(d_N);
cudaFree(d_P);
cudaFree(M);
free(h_N);
free(h_P);
free(h_M);
} | .file "tmpxft_001944fb_00000000-6_convolve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
.type _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_, @function
_Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25convolution_shared_memoryPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_, .-_Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
.globl _Z25convolution_shared_memoryPfS_
.type _Z25convolution_shared_memoryPfS_, @function
_Z25convolution_shared_memoryPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25convolution_shared_memoryPfS_, .-_Z25convolution_shared_memoryPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
movl $48, %edi
call malloc@PLT
movq %rax, %rbp
movl $48, %edi
call malloc@PLT
movq %rax, %r14
movl $20, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $12, %rax
jne .L12
movl $1, %ecx
movl $48, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $48, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 0(%r13)
movl $0x3f800000, 4(%r13)
movl $0x40000000, 8(%r13)
movl $0x40400000, 12(%r13)
movl $0x40800000, 16(%r13)
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
movq %r13, %rsi
leaq _ZL1M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $3, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $48, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbx
leaq 48(%r14), %r15
leaq .LC5(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq _ZL1M(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i
.type _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i, @function
_Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_constant_memoryPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i, .-_Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i
.globl _Z27convolution_constant_memoryPfS_i
.type _Z27convolution_constant_memoryPfS_i, @function
_Z27convolution_constant_memoryPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z27convolution_constant_memoryPfS_i, .-_Z27convolution_constant_memoryPfS_i
.globl _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i
.type _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25convolution_global_memoryPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i, .-_Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i
.globl _Z25convolution_global_memoryPfS_S_i
.type _Z25convolution_global_memoryPfS_S_i, @function
_Z25convolution_global_memoryPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z25convolution_global_memoryPfS_S_i, .-_Z25convolution_global_memoryPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z25convolution_global_memoryPfS_S_i"
.align 8
.LC7:
.string "_Z27convolution_constant_memoryPfS_i"
.align 8
.LC8:
.string "_Z25convolution_shared_memoryPfS_"
.section .rodata.str1.1
.LC9:
.string "M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z25convolution_global_memoryPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_constant_memoryPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z25convolution_shared_memoryPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1M
.comm _ZL1M,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#define TILE_SIZE 4
#define INPUT_SIZE 12
#define MASK_WIDTH 5
__constant__ float M[MASK_WIDTH];
__global__ void convolution_shared_memory(float *N, float *P){
int i = blockIdx.x*blockDim.x+threadIdx.x;
__shared__ float N_s[TILE_SIZE];
N_s[threadIdx.x]=N[i];
__syncthreads();
int this_title_start_point = blockIdx.x*blockDim.x;
int next_tile_start_point = (blockIdx.x+1)*blockDim.x;
int n_start_point = i-(MASK_WIDTH/2);
float Pvalue = 0;
for(int j =0; j < MASK_WIDTH; j++){
int N_index = n_start_point+j;
if(N_index >= 0 && N_index < INPUT_SIZE){
if((N_index >= this_title_start_point) && (N_index < next_tile_start_point)){
Pvalue+=N_s[threadIdx.x+j-(MASK_WIDTH/2)]*M[j];
}
else{
Pvalue+=N[N_index]*M[j];
}
}
}
P[i]=Pvalue;
}
__global__ void convolution_constant_memory(float *N, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
__global__ void convolution_global_memory(float *N, float *M, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
int main(){
//device input and output
float *d_N = 0;
float *d_P = 0;
cudaMalloc(&d_N,INPUT_SIZE*sizeof(float));
cudaMalloc(&d_P,INPUT_SIZE*sizeof(float));
//host input and output
float *h_N = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_P = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_M = (float*)malloc(MASK_WIDTH*sizeof(float));
//initialize input on host
for(int i=0;i<INPUT_SIZE;++i){
h_N[i]=(float)i;
}
//transfer input to device
cudaMemcpy(d_N,h_N,INPUT_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_P,h_P,INPUT_SIZE*sizeof(float),cudaMemcpyHostToDevice);
//initialize mask on host
for(int j=0;j<MASK_WIDTH;++j){
h_M[j]=(float)j;
}
//transfer mask to constant memory
cudaMemcpyToSymbol(M,h_M,MASK_WIDTH*sizeof(float));
//call convolution kernel
convolution_shared_memory<<<(INPUT_SIZE+TILE_SIZE-1)/TILE_SIZE,TILE_SIZE >>>(d_N,d_P);
//retrieve result from device
cudaMemcpy(h_P,d_P,INPUT_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
for(int i=0; i<INPUT_SIZE;++i){
printf("%f\n", h_P[i]);
}
cudaFree(d_N);
cudaFree(d_P);
cudaFree(M);
free(h_N);
free(h_P);
free(h_M);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SIZE 4
#define INPUT_SIZE 12
#define MASK_WIDTH 5
__constant__ float M[MASK_WIDTH];
__global__ void convolution_shared_memory(float *N, float *P){
int i = blockIdx.x*blockDim.x+threadIdx.x;
__shared__ float N_s[TILE_SIZE];
N_s[threadIdx.x]=N[i];
__syncthreads();
int this_title_start_point = blockIdx.x*blockDim.x;
int next_tile_start_point = (blockIdx.x+1)*blockDim.x;
int n_start_point = i-(MASK_WIDTH/2);
float Pvalue = 0;
for(int j =0; j < MASK_WIDTH; j++){
int N_index = n_start_point+j;
if(N_index >= 0 && N_index < INPUT_SIZE){
if((N_index >= this_title_start_point) && (N_index < next_tile_start_point)){
Pvalue+=N_s[threadIdx.x+j-(MASK_WIDTH/2)]*M[j];
}
else{
Pvalue+=N[N_index]*M[j];
}
}
}
P[i]=Pvalue;
}
__global__ void convolution_constant_memory(float *N, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
__global__ void convolution_global_memory(float *N, float *M, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
int main(){
//device input and output
float *d_N = 0;
float *d_P = 0;
hipMalloc(&d_N,INPUT_SIZE*sizeof(float));
hipMalloc(&d_P,INPUT_SIZE*sizeof(float));
//host input and output
float *h_N = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_P = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_M = (float*)malloc(MASK_WIDTH*sizeof(float));
//initialize input on host
for(int i=0;i<INPUT_SIZE;++i){
h_N[i]=(float)i;
}
//transfer input to device
hipMemcpy(d_N,h_N,INPUT_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_P,h_P,INPUT_SIZE*sizeof(float),hipMemcpyHostToDevice);
//initialize mask on host
for(int j=0;j<MASK_WIDTH;++j){
h_M[j]=(float)j;
}
//transfer mask to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,MASK_WIDTH*sizeof(float));
//call convolution kernel
convolution_shared_memory<<<(INPUT_SIZE+TILE_SIZE-1)/TILE_SIZE,TILE_SIZE >>>(d_N,d_P);
//retrieve result from device
hipMemcpy(h_P,d_P,INPUT_SIZE*sizeof(float),hipMemcpyDeviceToHost);
for(int i=0; i<INPUT_SIZE;++i){
printf("%f\n", h_P[i]);
}
hipFree(d_N);
hipFree(d_P);
hipFree(M);
free(h_N);
free(h_P);
free(h_M);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SIZE 4
#define INPUT_SIZE 12
#define MASK_WIDTH 5
__constant__ float M[MASK_WIDTH];
__global__ void convolution_shared_memory(float *N, float *P){
int i = blockIdx.x*blockDim.x+threadIdx.x;
__shared__ float N_s[TILE_SIZE];
N_s[threadIdx.x]=N[i];
__syncthreads();
int this_title_start_point = blockIdx.x*blockDim.x;
int next_tile_start_point = (blockIdx.x+1)*blockDim.x;
int n_start_point = i-(MASK_WIDTH/2);
float Pvalue = 0;
for(int j =0; j < MASK_WIDTH; j++){
int N_index = n_start_point+j;
if(N_index >= 0 && N_index < INPUT_SIZE){
if((N_index >= this_title_start_point) && (N_index < next_tile_start_point)){
Pvalue+=N_s[threadIdx.x+j-(MASK_WIDTH/2)]*M[j];
}
else{
Pvalue+=N[N_index]*M[j];
}
}
}
P[i]=Pvalue;
}
__global__ void convolution_constant_memory(float *N, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
__global__ void convolution_global_memory(float *N, float *M, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
int main(){
//device input and output
float *d_N = 0;
float *d_P = 0;
hipMalloc(&d_N,INPUT_SIZE*sizeof(float));
hipMalloc(&d_P,INPUT_SIZE*sizeof(float));
//host input and output
float *h_N = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_P = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_M = (float*)malloc(MASK_WIDTH*sizeof(float));
//initialize input on host
for(int i=0;i<INPUT_SIZE;++i){
h_N[i]=(float)i;
}
//transfer input to device
hipMemcpy(d_N,h_N,INPUT_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_P,h_P,INPUT_SIZE*sizeof(float),hipMemcpyHostToDevice);
//initialize mask on host
for(int j=0;j<MASK_WIDTH;++j){
h_M[j]=(float)j;
}
//transfer mask to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,MASK_WIDTH*sizeof(float));
//call convolution kernel
convolution_shared_memory<<<(INPUT_SIZE+TILE_SIZE-1)/TILE_SIZE,TILE_SIZE >>>(d_N,d_P);
//retrieve result from device
hipMemcpy(h_P,d_P,INPUT_SIZE*sizeof(float),hipMemcpyDeviceToHost);
for(int i=0; i<INPUT_SIZE;++i){
printf("%f\n", h_P[i]);
}
hipFree(d_N);
hipFree(d_P);
hipFree(M);
free(h_N);
free(h_P);
free(h_M);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25convolution_shared_memoryPfS_
.globl _Z25convolution_shared_memoryPfS_
.p2align 8
.type _Z25convolution_shared_memoryPfS_,@function
_Z25convolution_shared_memoryPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s8, -8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, M@rel32@lo+4
s_addc_u32 s7, s7, M@rel32@hi+12
s_mul_i32 s3, s15, s2
s_add_i32 s9, s15, 1
v_add_nc_u32_e32 v1, s3, v0
s_mul_i32 s9, s9, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v6, v[3:4], off
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_add_nc_u32 v3, -2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s8, s8, 4
v_add_nc_u32_e32 v3, 1, v3
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 12
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_mov_b32 s10, exec_lo
v_cmpx_gt_u32_e32 12, v3
s_cbranch_execz .LBB0_2
s_waitcnt lgkmcnt(0)
s_load_b32 s11, s[6:7], 0x0
v_cmp_gt_i32_e32 vcc_lo, s3, v3
v_cmp_le_i32_e64 s2, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s12
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s11, v6
.LBB0_6:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v6, s8, v5
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s11, v6
s_branch .LBB0_1
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25convolution_shared_memoryPfS_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25convolution_shared_memoryPfS_, .Lfunc_end0-_Z25convolution_shared_memoryPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27convolution_constant_memoryPfS_i
.globl _Z27convolution_constant_memoryPfS_i
.p2align 8
.type _Z27convolution_constant_memoryPfS_i,@function
_Z27convolution_constant_memoryPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -2, v1
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s6, 20
s_cbranch_scc1 .LBB1_4
.LBB1_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s2, s3, v2
s_and_b32 s8, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s8
s_cbranch_execz .LBB1_1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, M@rel32@lo+4
s_addc_u32 s9, s9, M@rel32@hi+12
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
s_load_b32 s8, s[8:9], 0x0
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v4
s_branch .LBB1_1
.LBB1_4:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_constant_memoryPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z27convolution_constant_memoryPfS_i, .Lfunc_end1-_Z27convolution_constant_memoryPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25convolution_global_memoryPfS_S_i
.globl _Z25convolution_global_memoryPfS_S_i
.p2align 8
.type _Z25convolution_global_memoryPfS_S_i,@function
_Z25convolution_global_memoryPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x18
v_mov_b32_e32 v3, 0
s_mov_b32 s8, -2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s8, s8, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 3
s_cbranch_scc1 .LBB2_4
.LBB2_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s8, v1
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, vcc_lo, s2
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB2_1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s9, v2
s_branch .LBB2_1
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25convolution_global_memoryPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z25convolution_global_memoryPfS_S_i, .Lfunc_end2-_Z25convolution_global_memoryPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected M
.type M,@object
.section .bss,"aw",@nobits
.globl M
.p2align 4, 0x0
M:
.zero 20
.size M, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25convolution_shared_memoryPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25convolution_shared_memoryPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27convolution_constant_memoryPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27convolution_constant_memoryPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25convolution_global_memoryPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25convolution_global_memoryPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SIZE 4
#define INPUT_SIZE 12
#define MASK_WIDTH 5
__constant__ float M[MASK_WIDTH];
__global__ void convolution_shared_memory(float *N, float *P){
int i = blockIdx.x*blockDim.x+threadIdx.x;
__shared__ float N_s[TILE_SIZE];
N_s[threadIdx.x]=N[i];
__syncthreads();
int this_title_start_point = blockIdx.x*blockDim.x;
int next_tile_start_point = (blockIdx.x+1)*blockDim.x;
int n_start_point = i-(MASK_WIDTH/2);
float Pvalue = 0;
for(int j =0; j < MASK_WIDTH; j++){
int N_index = n_start_point+j;
if(N_index >= 0 && N_index < INPUT_SIZE){
if((N_index >= this_title_start_point) && (N_index < next_tile_start_point)){
Pvalue+=N_s[threadIdx.x+j-(MASK_WIDTH/2)]*M[j];
}
else{
Pvalue+=N[N_index]*M[j];
}
}
}
P[i]=Pvalue;
}
__global__ void convolution_constant_memory(float *N, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
__global__ void convolution_global_memory(float *N, float *M, float *P, int Width){
int i = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue = 0;
int n_start_point = i-(MASK_WIDTH/2);
for(int j =0; j<MASK_WIDTH;j++){
if(n_start_point+j >=0 && n_start_point+j < Width){
Pvalue+= N[n_start_point+j]*M[j];
}
}
P[i]=Pvalue;
}
int main(){
//device input and output
float *d_N = 0;
float *d_P = 0;
hipMalloc(&d_N,INPUT_SIZE*sizeof(float));
hipMalloc(&d_P,INPUT_SIZE*sizeof(float));
//host input and output
float *h_N = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_P = (float*)malloc(INPUT_SIZE*sizeof(float));
float *h_M = (float*)malloc(MASK_WIDTH*sizeof(float));
//initialize input on host
for(int i=0;i<INPUT_SIZE;++i){
h_N[i]=(float)i;
}
//transfer input to device
hipMemcpy(d_N,h_N,INPUT_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_P,h_P,INPUT_SIZE*sizeof(float),hipMemcpyHostToDevice);
//initialize mask on host
for(int j=0;j<MASK_WIDTH;++j){
h_M[j]=(float)j;
}
//transfer mask to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,MASK_WIDTH*sizeof(float));
//call convolution kernel
convolution_shared_memory<<<(INPUT_SIZE+TILE_SIZE-1)/TILE_SIZE,TILE_SIZE >>>(d_N,d_P);
//retrieve result from device
hipMemcpy(h_P,d_P,INPUT_SIZE*sizeof(float),hipMemcpyDeviceToHost);
for(int i=0; i<INPUT_SIZE;++i){
printf("%f\n", h_P[i]);
}
hipFree(d_N);
hipFree(d_P);
hipFree(M);
free(h_N);
free(h_P);
free(h_M);
} | .text
.file "convolve.hip"
.globl _Z40__device_stub__convolution_shared_memoryPfS_ # -- Begin function _Z40__device_stub__convolution_shared_memoryPfS_
.p2align 4, 0x90
.type _Z40__device_stub__convolution_shared_memoryPfS_,@function
_Z40__device_stub__convolution_shared_memoryPfS_: # @_Z40__device_stub__convolution_shared_memoryPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25convolution_shared_memoryPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__convolution_shared_memoryPfS_, .Lfunc_end0-_Z40__device_stub__convolution_shared_memoryPfS_
.cfi_endproc
# -- End function
.globl _Z42__device_stub__convolution_constant_memoryPfS_i # -- Begin function _Z42__device_stub__convolution_constant_memoryPfS_i
.p2align 4, 0x90
.type _Z42__device_stub__convolution_constant_memoryPfS_i,@function
_Z42__device_stub__convolution_constant_memoryPfS_i: # @_Z42__device_stub__convolution_constant_memoryPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_constant_memoryPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z42__device_stub__convolution_constant_memoryPfS_i, .Lfunc_end1-_Z42__device_stub__convolution_constant_memoryPfS_i
.cfi_endproc
# -- End function
.globl _Z40__device_stub__convolution_global_memoryPfS_S_i # -- Begin function _Z40__device_stub__convolution_global_memoryPfS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__convolution_global_memoryPfS_S_i,@function
_Z40__device_stub__convolution_global_memoryPfS_S_i: # @_Z40__device_stub__convolution_global_memoryPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25convolution_global_memoryPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z40__device_stub__convolution_global_memoryPfS_S_i, .Lfunc_end2-_Z40__device_stub__convolution_global_memoryPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $48, %esi
callq hipMalloc
movq %rsp, %rdi
movl $48, %esi
callq hipMalloc
movl $48, %edi
callq malloc
movq %rax, %rbx
movl $48, %edi
callq malloc
movq %rax, %r14
movl $20, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $12, %rax
jne .LBB3_1
# %bb.2:
movq 8(%rsp), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $48, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB3_3
# %bb.4:
movl $M, %edi
movl $20, %edx
movq %r15, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25convolution_shared_memoryPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
movl $48, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $12, %r12
jne .LBB3_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $M, %edi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25convolution_shared_memoryPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_constant_memoryPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25convolution_global_memoryPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $M, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.local M
.comm M,20,16
.type _Z25convolution_shared_memoryPfS_,@object # @_Z25convolution_shared_memoryPfS_
.section .rodata,"a",@progbits
.globl _Z25convolution_shared_memoryPfS_
.p2align 3, 0x0
_Z25convolution_shared_memoryPfS_:
.quad _Z40__device_stub__convolution_shared_memoryPfS_
.size _Z25convolution_shared_memoryPfS_, 8
.type _Z27convolution_constant_memoryPfS_i,@object # @_Z27convolution_constant_memoryPfS_i
.globl _Z27convolution_constant_memoryPfS_i
.p2align 3, 0x0
_Z27convolution_constant_memoryPfS_i:
.quad _Z42__device_stub__convolution_constant_memoryPfS_i
.size _Z27convolution_constant_memoryPfS_i, 8
.type _Z25convolution_global_memoryPfS_S_i,@object # @_Z25convolution_global_memoryPfS_S_i
.globl _Z25convolution_global_memoryPfS_S_i
.p2align 3, 0x0
_Z25convolution_global_memoryPfS_S_i:
.quad _Z40__device_stub__convolution_global_memoryPfS_S_i
.size _Z25convolution_global_memoryPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25convolution_shared_memoryPfS_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z27convolution_constant_memoryPfS_i"
.size .L__unnamed_2, 37
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z25convolution_global_memoryPfS_S_i"
.size .L__unnamed_3, 37
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "M"
.size .L__unnamed_4, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__convolution_shared_memoryPfS_
.addrsig_sym _Z42__device_stub__convolution_constant_memoryPfS_i
.addrsig_sym _Z40__device_stub__convolution_global_memoryPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym _Z25convolution_shared_memoryPfS_
.addrsig_sym _Z27convolution_constant_memoryPfS_i
.addrsig_sym _Z25convolution_global_memoryPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25convolution_global_memoryPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE R2, R6.reuse, R17, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe200078e0211 */
/*0090*/ IADD3 R0, R6.reuse, -0x2, RZ ; /* 0xfffffffe06007810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ ISETP.GT.AND P2, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f44270 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06270 */
/*00c0*/ IADD3 R0, R6.reuse, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.LT.OR P0, PT, R6.reuse, 0x2, P0 ; /* 0x000000020600780c */
/* 0x040fe40000701670 */
/*00e0*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc40003f26270 */
/*00f0*/ ISETP.LT.OR P2, PT, R6, 0x1, P2 ; /* 0x000000010600780c */
/* 0x000fe40001741670 */
/*0100*/ ISETP.GE.AND P4, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f86270 */
/*0110*/ IADD3 R0, R6.reuse, 0x2, RZ ; /* 0x0000000206007810 */
/* 0x040fe40007ffe0ff */
/*0120*/ ISETP.LT.OR P1, PT, R6, RZ, P1 ; /* 0x000000ff0600720c */
/* 0x000fe40000f21670 */
/*0130*/ ISETP.GE.AND P3, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f66270 */
/*0140*/ @!P0 LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402078981 */
/* 0x000ea2000c1e1900 */
/*0150*/ ISETP.LT.OR P4, PT, R6, -0x1, P4 ; /* 0xffffffff0600780c */
/* 0x000fc60002781670 */
/*0160*/ @!P0 LDG.E R0, [R4.64] ; /* 0x0000000404008981 */
/* 0x000ea2000c1e1900 */
/*0170*/ ISETP.LT.OR P3, PT, R6, -0x2, P3 ; /* 0xfffffffe0600780c */
/* 0x000fc60001f61670 */
/*0180*/ @!P2 LDG.E R8, [R4.64+0x4] ; /* 0x000004040408a981 */
/* 0x000ee8000c1e1900 */
/*0190*/ @!P2 LDG.E R10, [R2.64+-0x4] ; /* 0xfffffc04020aa981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ @!P1 LDG.E R12, [R2.64] ; /* 0x00000004020c9981 */
/* 0x000f28000c1e1900 */
/*01b0*/ @!P1 LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b9981 */
/* 0x000f28000c1e1900 */
/*01c0*/ @!P4 LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040ec981 */
/* 0x000f68000c1e1900 */
/*01d0*/ @!P4 LDG.E R13, [R2.64+0x4] ; /* 0x00000404020dc981 */
/* 0x000f68000c1e1900 */
/*01e0*/ @!P3 LDG.E R16, [R4.64+0x10] ; /* 0x000010040410b981 */
/* 0x000f68000c1e1900 */
/*01f0*/ @!P3 LDG.E R15, [R2.64+0x8] ; /* 0x00000804020fb981 */
/* 0x000f62000c1e1900 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc400078e00ff */
/*0210*/ @!P0 FFMA R9, R0, R7, RZ ; /* 0x0000000700098223 */
/* 0x004fc800000000ff */
/*0220*/ @!P2 FFMA R9, R8, R10, R9 ; /* 0x0000000a0809a223 */
/* 0x008fc80000000009 */
/*0230*/ @!P1 FFMA R9, R12, R11, R9 ; /* 0x0000000b0c099223 */
/* 0x010fe40000000009 */
/*0240*/ IMAD.WIDE R6, R6, R17, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0211 */
/*0250*/ @!P4 FFMA R9, R14, R13, R9 ; /* 0x0000000d0e09c223 */
/* 0x020fc80000000009 */
/*0260*/ @!P3 FFMA R9, R16, R15, R9 ; /* 0x0000000f1009b223 */
/* 0x000fca0000000009 */
/*0270*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z27convolution_constant_memoryPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R4.reuse, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e0205 */
/*0070*/ IADD3 R0, R4.reuse, -0x2, RZ ; /* 0xfffffffe04007810 */
/* 0x040fe40007ffe0ff */
/*0080*/ ISETP.GT.AND P2, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f44270 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06270 */
/*00a0*/ IADD3 R0, R4.reuse, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ ISETP.LT.OR P0, PT, R4.reuse, 0x2, P0 ; /* 0x000000020400780c */
/* 0x040fe40000701670 */
/*00c0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc40003f26270 */
/*00d0*/ ISETP.LT.OR P2, PT, R4, 0x1, P2 ; /* 0x000000010400780c */
/* 0x000fe40001741670 */
/*00e0*/ ISETP.GE.AND P4, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f86270 */
/*00f0*/ IADD3 R0, R4.reuse, 0x2, RZ ; /* 0x0000000204007810 */
/* 0x040fe40007ffe0ff */
/*0100*/ ISETP.LT.OR P1, PT, R4, RZ, P1 ; /* 0x000000ff0400720c */
/* 0x000fe40000f21670 */
/*0110*/ ISETP.GE.AND P3, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f66270 */
/*0120*/ @!P0 LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402098981 */
/* 0x000ea2000c1e1900 */
/*0130*/ ISETP.LT.OR P4, PT, R4, -0x1, P4 ; /* 0xffffffff0400780c */
/* 0x000fc40002781670 */
/*0140*/ ISETP.LT.OR P3, PT, R4, -0x2, P3 ; /* 0xfffffffe0400780c */
/* 0x000fe20001f61670 */
/*0150*/ @!P2 LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc040200a981 */
/* 0x000eec000c1e1900 */
/*0160*/ @!P1 LDG.E R6, [R2.64] ; /* 0x0000000402069981 */
/* 0x000f28000c1e1900 */
/*0170*/ @!P4 LDG.E R8, [R2.64+0x4] ; /* 0x000004040208c981 */
/* 0x000f68000c1e1900 */
/*0180*/ @!P3 LDG.E R10, [R2.64+0x8] ; /* 0x00000804020ab981 */
/* 0x000f62000c1e1900 */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc400078e00ff */
/*01a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*01b0*/ @!P0 FFMA R7, R9, c[0x3][0x0], RZ ; /* 0x00c0000009078a23 */
/* 0x004fc800000000ff */
/*01c0*/ @!P2 FFMA R7, R0, c[0x3][0x4], R7 ; /* 0x00c001000007aa23 */
/* 0x008fc80000000007 */
/*01d0*/ @!P1 FFMA R7, R6, c[0x3][0x8], R7 ; /* 0x00c0020006079a23 */
/* 0x010fc80000000007 */
/*01e0*/ @!P4 FFMA R7, R8, c[0x3][0xc], R7 ; /* 0x00c003000807ca23 */
/* 0x020fc80000000007 */
/*01f0*/ @!P3 FFMA R7, R10, c[0x3][0x10], R7 ; /* 0x00c004000a07ba23 */
/* 0x000fca0000000007 */
/*0200*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z25convolution_shared_memoryPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fcc000f8e023f */
/*0070*/ IADD3 R0, R9, UR4, RZ ; /* 0x0000000409007c10 */
/* 0x002fca000fffe0ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IADD3 R5, R0, -0x2, RZ ; /* 0xfffffffe00057810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ UIADD3 UR5, UR4, UR5, URZ ; /* 0x0000000504057290 */
/* 0x000fe2000fffe03f */
/*00c0*/ BSSY B0, 0x1c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R5, 0xb, PT ; /* 0x0000000b0500780c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*0100*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @P0 BRA 0x1b0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.AND P0, PT, R5.reuse, UR4, PT ; /* 0x0000000405007c0c */
/* 0x041fe4000bf06270 */
/*0140*/ ISETP.LT.AND P1, PT, R5, UR5, PT ; /* 0x0000000505007c0c */
/* 0x000fda000bf21270 */
/*0150*/ @P0 BRA P1, 0x190 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0160*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80602077981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x004fe200000000ff */
/*0180*/ BRA 0x1b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0190*/ LDS R7, [R9.X4+-0x8] ; /* 0xfffff80009077984 */
/* 0x000e240000004800 */
/*01a0*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x001fe400000000ff */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01c0*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ BSSY B0, 0x290 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R4, 0xb, PT ; /* 0x0000000b0400780c */
/* 0x000fda0003f04070 */
/*01f0*/ @P0 BRA 0x280 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe4000bf04270 */
/*0210*/ ISETP.LE.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf23270 */
/*0220*/ @P0 BRA P1, 0x260 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0230*/ LDG.E R4, [R2.64+-0x4] ; /* 0xfffffc0602047981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FFMA R7, R4, c[0x3][0x4], R7 ; /* 0x00c0010004077a23 */
/* 0x004fe20000000007 */
/*0250*/ BRA 0x280 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0260*/ LDS R4, [R9.X4+-0x4] ; /* 0xfffffc0009047984 */
/* 0x000e240000004800 */
/*0270*/ FFMA R7, R4, c[0x3][0x4], R7 ; /* 0x00c0010004077a23 */
/* 0x001fe40000000007 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GT.U32.AND P0, PT, R0, 0xb, PT ; /* 0x0000000b0000780c */
/* 0x000fe20003f04070 */
/*02a0*/ BSSY B0, 0x350 ; /* 0x000000a000007945 */
/* 0x000fd80003800000 */
/*02b0*/ @P0 BRA 0x340 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.GE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe4000bf06270 */
/*02d0*/ ISETP.LT.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf21270 */
/*02e0*/ @P0 BRA P1, 0x320 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*02f0*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R7, R4, c[0x3][0x8], R7 ; /* 0x00c0020004077a23 */
/* 0x004fe20000000007 */
/*0310*/ BRA 0x340 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0320*/ LDS R4, [R9.X4] ; /* 0x0000000009047984 */
/* 0x000e240000004800 */
/*0330*/ FFMA R7, R4, c[0x3][0x8], R7 ; /* 0x00c0020004077a23 */
/* 0x001fe40000000007 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fe20007ffe0ff */
/*0360*/ BSSY B0, 0x420 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0370*/ ISETP.GT.U32.AND P0, PT, R4, 0xb, PT ; /* 0x0000000b0400780c */
/* 0x000fda0003f04070 */
/*0380*/ @P0 BRA 0x410 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R4.reuse, UR4, PT ; /* 0x0000000404007c0c */
/* 0x040fe4000bf06270 */
/*03a0*/ ISETP.LT.AND P1, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fda000bf21270 */
/*03b0*/ @P0 BRA P1, 0x3f0 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*03c0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040602047981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R7, R4, c[0x3][0xc], R7 ; /* 0x00c0030004077a23 */
/* 0x004fe20000000007 */
/*03e0*/ BRA 0x410 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*03f0*/ LDS R4, [R9.X4+0x4] ; /* 0x0000040009047984 */
/* 0x000e240000004800 */
/*0400*/ FFMA R7, R4, c[0x3][0xc], R7 ; /* 0x00c0030004077a23 */
/* 0x001fe40000000007 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0430*/ BSSY B0, 0x4f0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0440*/ ISETP.GT.U32.AND P0, PT, R4, 0xb, PT ; /* 0x0000000b0400780c */
/* 0x000fda0003f04070 */
/*0450*/ @P0 BRA 0x4e0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.GE.AND P0, PT, R4.reuse, UR4, PT ; /* 0x0000000404007c0c */
/* 0x040fe4000bf06270 */
/*0470*/ ISETP.LT.AND P1, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fda000bf21270 */
/*0480*/ @P0 BRA P1, 0x4c0 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0490*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080602027981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ FFMA R7, R2, c[0x3][0x10], R7 ; /* 0x00c0040002077a23 */
/* 0x004fe20000000007 */
/*04b0*/ BRA 0x4e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*04c0*/ LDS R2, [R9.X4+0x8] ; /* 0x0000080009027984 */
/* 0x000e240000004800 */
/*04d0*/ FFMA R7, R2, c[0x3][0x10], R7 ; /* 0x00c0040002077a23 */
/* 0x001fe40000000007 */
/*04e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04f0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0500*/ LEA.HI.X R3, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f140b */
/*0510*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25convolution_shared_memoryPfS_
.globl _Z25convolution_shared_memoryPfS_
.p2align 8
.type _Z25convolution_shared_memoryPfS_,@function
_Z25convolution_shared_memoryPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s8, -8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, M@rel32@lo+4
s_addc_u32 s7, s7, M@rel32@hi+12
s_mul_i32 s3, s15, s2
s_add_i32 s9, s15, 1
v_add_nc_u32_e32 v1, s3, v0
s_mul_i32 s9, s9, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v6, v[3:4], off
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_add_nc_u32 v3, -2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s8, s8, 4
v_add_nc_u32_e32 v3, 1, v3
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 12
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_mov_b32 s10, exec_lo
v_cmpx_gt_u32_e32 12, v3
s_cbranch_execz .LBB0_2
s_waitcnt lgkmcnt(0)
s_load_b32 s11, s[6:7], 0x0
v_cmp_gt_i32_e32 vcc_lo, s3, v3
v_cmp_le_i32_e64 s2, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s12
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s11, v6
.LBB0_6:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v6, s8, v5
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s11, v6
s_branch .LBB0_1
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25convolution_shared_memoryPfS_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25convolution_shared_memoryPfS_, .Lfunc_end0-_Z25convolution_shared_memoryPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27convolution_constant_memoryPfS_i
.globl _Z27convolution_constant_memoryPfS_i
.p2align 8
.type _Z27convolution_constant_memoryPfS_i,@function
_Z27convolution_constant_memoryPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -2, v1
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s6, 20
s_cbranch_scc1 .LBB1_4
.LBB1_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s2, s3, v2
s_and_b32 s8, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s8
s_cbranch_execz .LBB1_1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, M@rel32@lo+4
s_addc_u32 s9, s9, M@rel32@hi+12
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
s_load_b32 s8, s[8:9], 0x0
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v4
s_branch .LBB1_1
.LBB1_4:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_constant_memoryPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z27convolution_constant_memoryPfS_i, .Lfunc_end1-_Z27convolution_constant_memoryPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25convolution_global_memoryPfS_S_i
.globl _Z25convolution_global_memoryPfS_S_i
.p2align 8
.type _Z25convolution_global_memoryPfS_S_i,@function
_Z25convolution_global_memoryPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x18
v_mov_b32_e32 v3, 0
s_mov_b32 s8, -2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s8, s8, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 3
s_cbranch_scc1 .LBB2_4
.LBB2_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s8, v1
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, vcc_lo, s2
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB2_1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s9, v2
s_branch .LBB2_1
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25convolution_global_memoryPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z25convolution_global_memoryPfS_S_i, .Lfunc_end2-_Z25convolution_global_memoryPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected M
.type M,@object
.section .bss,"aw",@nobits
.globl M
.p2align 4, 0x0
M:
.zero 20
.size M, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25convolution_shared_memoryPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25convolution_shared_memoryPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27convolution_constant_memoryPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27convolution_constant_memoryPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25convolution_global_memoryPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25convolution_global_memoryPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001944fb_00000000-6_convolve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
.type _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_, @function
_Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25convolution_shared_memoryPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_, .-_Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
.globl _Z25convolution_shared_memoryPfS_
.type _Z25convolution_shared_memoryPfS_, @function
_Z25convolution_shared_memoryPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25convolution_shared_memoryPfS_, .-_Z25convolution_shared_memoryPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
movl $48, %edi
call malloc@PLT
movq %rax, %rbp
movl $48, %edi
call malloc@PLT
movq %rax, %r14
movl $20, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $12, %rax
jne .L12
movl $1, %ecx
movl $48, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $48, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 0(%r13)
movl $0x3f800000, 4(%r13)
movl $0x40000000, 8(%r13)
movl $0x40400000, 12(%r13)
movl $0x40800000, 16(%r13)
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
movq %r13, %rsi
leaq _ZL1M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $3, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $48, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbx
leaq 48(%r14), %r15
leaq .LC5(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq _ZL1M(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z47__device_stub__Z25convolution_shared_memoryPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i
.type _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i, @function
_Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_constant_memoryPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i, .-_Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i
.globl _Z27convolution_constant_memoryPfS_i
.type _Z27convolution_constant_memoryPfS_i, @function
_Z27convolution_constant_memoryPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z27convolution_constant_memoryPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z27convolution_constant_memoryPfS_i, .-_Z27convolution_constant_memoryPfS_i
.globl _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i
.type _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25convolution_global_memoryPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i, .-_Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i
.globl _Z25convolution_global_memoryPfS_S_i
.type _Z25convolution_global_memoryPfS_S_i, @function
_Z25convolution_global_memoryPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25convolution_global_memoryPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z25convolution_global_memoryPfS_S_i, .-_Z25convolution_global_memoryPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z25convolution_global_memoryPfS_S_i"
.align 8
.LC7:
.string "_Z27convolution_constant_memoryPfS_i"
.align 8
.LC8:
.string "_Z25convolution_shared_memoryPfS_"
.section .rodata.str1.1
.LC9:
.string "M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z25convolution_global_memoryPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_constant_memoryPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z25convolution_shared_memoryPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1M
.comm _ZL1M,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolve.hip"
.globl _Z40__device_stub__convolution_shared_memoryPfS_ # -- Begin function _Z40__device_stub__convolution_shared_memoryPfS_
.p2align 4, 0x90
.type _Z40__device_stub__convolution_shared_memoryPfS_,@function
_Z40__device_stub__convolution_shared_memoryPfS_: # @_Z40__device_stub__convolution_shared_memoryPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25convolution_shared_memoryPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__convolution_shared_memoryPfS_, .Lfunc_end0-_Z40__device_stub__convolution_shared_memoryPfS_
.cfi_endproc
# -- End function
.globl _Z42__device_stub__convolution_constant_memoryPfS_i # -- Begin function _Z42__device_stub__convolution_constant_memoryPfS_i
.p2align 4, 0x90
.type _Z42__device_stub__convolution_constant_memoryPfS_i,@function
_Z42__device_stub__convolution_constant_memoryPfS_i: # @_Z42__device_stub__convolution_constant_memoryPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_constant_memoryPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z42__device_stub__convolution_constant_memoryPfS_i, .Lfunc_end1-_Z42__device_stub__convolution_constant_memoryPfS_i
.cfi_endproc
# -- End function
.globl _Z40__device_stub__convolution_global_memoryPfS_S_i # -- Begin function _Z40__device_stub__convolution_global_memoryPfS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__convolution_global_memoryPfS_S_i,@function
_Z40__device_stub__convolution_global_memoryPfS_S_i: # @_Z40__device_stub__convolution_global_memoryPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25convolution_global_memoryPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z40__device_stub__convolution_global_memoryPfS_S_i, .Lfunc_end2-_Z40__device_stub__convolution_global_memoryPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $48, %esi
callq hipMalloc
movq %rsp, %rdi
movl $48, %esi
callq hipMalloc
movl $48, %edi
callq malloc
movq %rax, %rbx
movl $48, %edi
callq malloc
movq %rax, %r14
movl $20, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $12, %rax
jne .LBB3_1
# %bb.2:
movq 8(%rsp), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $48, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB3_3
# %bb.4:
movl $M, %edi
movl $20, %edx
movq %r15, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25convolution_shared_memoryPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
movl $48, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $12, %r12
jne .LBB3_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $M, %edi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25convolution_shared_memoryPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_constant_memoryPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25convolution_global_memoryPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $M, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.local M
.comm M,20,16
.type _Z25convolution_shared_memoryPfS_,@object # @_Z25convolution_shared_memoryPfS_
.section .rodata,"a",@progbits
.globl _Z25convolution_shared_memoryPfS_
.p2align 3, 0x0
_Z25convolution_shared_memoryPfS_:
.quad _Z40__device_stub__convolution_shared_memoryPfS_
.size _Z25convolution_shared_memoryPfS_, 8
.type _Z27convolution_constant_memoryPfS_i,@object # @_Z27convolution_constant_memoryPfS_i
.globl _Z27convolution_constant_memoryPfS_i
.p2align 3, 0x0
_Z27convolution_constant_memoryPfS_i:
.quad _Z42__device_stub__convolution_constant_memoryPfS_i
.size _Z27convolution_constant_memoryPfS_i, 8
.type _Z25convolution_global_memoryPfS_S_i,@object # @_Z25convolution_global_memoryPfS_S_i
.globl _Z25convolution_global_memoryPfS_S_i
.p2align 3, 0x0
_Z25convolution_global_memoryPfS_S_i:
.quad _Z40__device_stub__convolution_global_memoryPfS_S_i
.size _Z25convolution_global_memoryPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25convolution_shared_memoryPfS_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z27convolution_constant_memoryPfS_i"
.size .L__unnamed_2, 37
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z25convolution_global_memoryPfS_S_i"
.size .L__unnamed_3, 37
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "M"
.size .L__unnamed_4, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__convolution_shared_memoryPfS_
.addrsig_sym _Z42__device_stub__convolution_constant_memoryPfS_i
.addrsig_sym _Z40__device_stub__convolution_global_memoryPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym _Z25convolution_shared_memoryPfS_
.addrsig_sym _Z27convolution_constant_memoryPfS_i
.addrsig_sym _Z25convolution_global_memoryPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scaleWalkers ( const int n, const float c, const float *a, float *d ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < n ) {
d[i] = c * a[i];
}
} | code for sm_80
Function : _Z12scaleWalkersifPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x164] ; /* 0x0000590002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scaleWalkers ( const int n, const float c, const float *a, float *d ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < n ) {
d[i] = c * a[i];
}
} | .file "tmpxft_000d011b_00000000-6_scaleWalkers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf
.type _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf, @function
_Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12scaleWalkersifPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf, .-_Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf
.globl _Z12scaleWalkersifPKfPf
.type _Z12scaleWalkersifPKfPf, @function
_Z12scaleWalkersifPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12scaleWalkersifPKfPf, .-_Z12scaleWalkersifPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12scaleWalkersifPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12scaleWalkersifPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scaleWalkers ( const int n, const float c, const float *a, float *d ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < n ) {
d[i] = c * a[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scaleWalkers ( const int n, const float c, const float *a, float *d ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < n ) {
d[i] = c * a[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scaleWalkers ( const int n, const float c, const float *a, float *d ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < n ) {
d[i] = c * a[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12scaleWalkersifPKfPf
.globl _Z12scaleWalkersifPKfPf
.p2align 8
.type _Z12scaleWalkersifPKfPf,@function
_Z12scaleWalkersifPKfPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12scaleWalkersifPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12scaleWalkersifPKfPf, .Lfunc_end0-_Z12scaleWalkersifPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12scaleWalkersifPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12scaleWalkersifPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scaleWalkers ( const int n, const float c, const float *a, float *d ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < n ) {
d[i] = c * a[i];
}
} | .text
.file "scaleWalkers.hip"
.globl _Z27__device_stub__scaleWalkersifPKfPf # -- Begin function _Z27__device_stub__scaleWalkersifPKfPf
.p2align 4, 0x90
.type _Z27__device_stub__scaleWalkersifPKfPf,@function
_Z27__device_stub__scaleWalkersifPKfPf: # @_Z27__device_stub__scaleWalkersifPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12scaleWalkersifPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__scaleWalkersifPKfPf, .Lfunc_end0-_Z27__device_stub__scaleWalkersifPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12scaleWalkersifPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12scaleWalkersifPKfPf,@object # @_Z12scaleWalkersifPKfPf
.section .rodata,"a",@progbits
.globl _Z12scaleWalkersifPKfPf
.p2align 3, 0x0
_Z12scaleWalkersifPKfPf:
.quad _Z27__device_stub__scaleWalkersifPKfPf
.size _Z12scaleWalkersifPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12scaleWalkersifPKfPf"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__scaleWalkersifPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12scaleWalkersifPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12scaleWalkersifPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x164] ; /* 0x0000590002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12scaleWalkersifPKfPf
.globl _Z12scaleWalkersifPKfPf
.p2align 8
.type _Z12scaleWalkersifPKfPf,@function
_Z12scaleWalkersifPKfPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12scaleWalkersifPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12scaleWalkersifPKfPf, .Lfunc_end0-_Z12scaleWalkersifPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12scaleWalkersifPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12scaleWalkersifPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d011b_00000000-6_scaleWalkers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf
.type _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf, @function
_Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12scaleWalkersifPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf, .-_Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf
.globl _Z12scaleWalkersifPKfPf
.type _Z12scaleWalkersifPKfPf, @function
_Z12scaleWalkersifPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12scaleWalkersifPKfPfifPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12scaleWalkersifPKfPf, .-_Z12scaleWalkersifPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12scaleWalkersifPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12scaleWalkersifPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scaleWalkers.hip"
.globl _Z27__device_stub__scaleWalkersifPKfPf # -- Begin function _Z27__device_stub__scaleWalkersifPKfPf
.p2align 4, 0x90
.type _Z27__device_stub__scaleWalkersifPKfPf,@function
_Z27__device_stub__scaleWalkersifPKfPf: # @_Z27__device_stub__scaleWalkersifPKfPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12scaleWalkersifPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__scaleWalkersifPKfPf, .Lfunc_end0-_Z27__device_stub__scaleWalkersifPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12scaleWalkersifPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12scaleWalkersifPKfPf,@object # @_Z12scaleWalkersifPKfPf
.section .rodata,"a",@progbits
.globl _Z12scaleWalkersifPKfPf
.p2align 3, 0x0
_Z12scaleWalkersifPKfPf:
.quad _Z27__device_stub__scaleWalkersifPKfPf
.size _Z12scaleWalkersifPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12scaleWalkersifPKfPf"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__scaleWalkersifPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12scaleWalkersifPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <float.h>
__device__ float euclid2(
float* items,
float* centers,
int itemId,
int centerId,
int paramsCount)
{
float sum = 0.0;
for(int j = 0; j < paramsCount; j++)
{
sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j])
* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
}
return sum;
}
__global__ void clusreringKernel(
float* items,
float* deviceCenters,
int* clustersIds,
int itemsCount,
int clustersCount,
int paramsCount)
{
extern __shared__ float centers[];
for (int i = threadIdx.x; i < clustersCount; i += blockDim.x)
{
for (int j = 0; j < paramsCount; j++)
{
centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
}
}
__syncthreads();
int itemId = blockDim.x * blockIdx.x + threadIdx.x;
if(itemId < itemsCount)
{
float minDistance = FLT_MAX;
float distance;
int index;
for(int i = 0; i < clustersCount; i++)
{
distance = euclid2(items, centers, itemId, i, paramsCount);
if(minDistance >= distance)
{
minDistance = distance;
index = i;
}
}
clustersIds[itemId] = index;
}
}
__global__ void newCentersKernel(
float* items,
int* clustersIds,
float* newCenters,
int* itemsPerClusters,
int itemsCount,
int clustersCount,
int paramsCount
)
{
extern __shared__ float center[];
int clusterId = blockIdx.x;
int paramId = threadIdx.x;
center[paramId] = 0.0;
int count = 0;
__syncthreads();
for(int i = 0; i < itemsCount; i++)
{
if(clusterId == clustersIds[i])
{
center[paramId] += items[i * paramsCount + paramId];
count += 1;
}
}
newCenters[clusterId * paramsCount + paramId] = center[paramId];
itemsPerClusters[clusterId] = count;
} | .file "tmpxft_001bafaf_00000000-6_clustering_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7euclid2PfS_iii
.type _Z7euclid2PfS_iii, @function
_Z7euclid2PfS_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7euclid2PfS_iii, .-_Z7euclid2PfS_iii
.globl _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
.type _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii, @function
_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16clusreringKernelPfS_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii, .-_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
.globl _Z16clusreringKernelPfS_Piiii
.type _Z16clusreringKernelPfS_Piiii, @function
_Z16clusreringKernelPfS_Piiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16clusreringKernelPfS_Piiii, .-_Z16clusreringKernelPfS_Piiii
.globl _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
.type _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii, @function
_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16newCentersKernelPfPiS_S0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii, .-_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
.globl _Z16newCentersKernelPfPiS_S0_iii
.type _Z16newCentersKernelPfPiS_S0_iii, @function
_Z16newCentersKernelPfPiS_S0_iii:
.LFB2055:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z16newCentersKernelPfPiS_S0_iii, .-_Z16newCentersKernelPfPiS_S0_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16newCentersKernelPfPiS_S0_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z16clusreringKernelPfS_Piiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16newCentersKernelPfPiS_S0_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16clusreringKernelPfS_Piiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <float.h>
__device__ float euclid2(
float* items,
float* centers,
int itemId,
int centerId,
int paramsCount)
{
float sum = 0.0;
for(int j = 0; j < paramsCount; j++)
{
sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j])
* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
}
return sum;
}
__global__ void clusreringKernel(
float* items,
float* deviceCenters,
int* clustersIds,
int itemsCount,
int clustersCount,
int paramsCount)
{
extern __shared__ float centers[];
for (int i = threadIdx.x; i < clustersCount; i += blockDim.x)
{
for (int j = 0; j < paramsCount; j++)
{
centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
}
}
__syncthreads();
int itemId = blockDim.x * blockIdx.x + threadIdx.x;
if(itemId < itemsCount)
{
float minDistance = FLT_MAX;
float distance;
int index;
for(int i = 0; i < clustersCount; i++)
{
distance = euclid2(items, centers, itemId, i, paramsCount);
if(minDistance >= distance)
{
minDistance = distance;
index = i;
}
}
clustersIds[itemId] = index;
}
}
__global__ void newCentersKernel(
float* items,
int* clustersIds,
float* newCenters,
int* itemsPerClusters,
int itemsCount,
int clustersCount,
int paramsCount
)
{
extern __shared__ float center[];
int clusterId = blockIdx.x;
int paramId = threadIdx.x;
center[paramId] = 0.0;
int count = 0;
__syncthreads();
for(int i = 0; i < itemsCount; i++)
{
if(clusterId == clustersIds[i])
{
center[paramId] += items[i * paramsCount + paramId];
count += 1;
}
}
newCenters[clusterId * paramsCount + paramId] = center[paramId];
itemsPerClusters[clusterId] = count;
} | #include <hip/hip_runtime.h>
#include <float.h>
__device__ float euclid2(
float* items,
float* centers,
int itemId,
int centerId,
int paramsCount)
{
float sum = 0.0;
for(int j = 0; j < paramsCount; j++)
{
sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j])
* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
}
return sum;
}
__global__ void clusreringKernel(
float* items,
float* deviceCenters,
int* clustersIds,
int itemsCount,
int clustersCount,
int paramsCount)
{
extern __shared__ float centers[];
for (int i = threadIdx.x; i < clustersCount; i += blockDim.x)
{
for (int j = 0; j < paramsCount; j++)
{
centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
}
}
__syncthreads();
int itemId = blockDim.x * blockIdx.x + threadIdx.x;
if(itemId < itemsCount)
{
float minDistance = FLT_MAX;
float distance;
int index;
for(int i = 0; i < clustersCount; i++)
{
distance = euclid2(items, centers, itemId, i, paramsCount);
if(minDistance >= distance)
{
minDistance = distance;
index = i;
}
}
clustersIds[itemId] = index;
}
}
__global__ void newCentersKernel(
float* items,
int* clustersIds,
float* newCenters,
int* itemsPerClusters,
int itemsCount,
int clustersCount,
int paramsCount
)
{
extern __shared__ float center[];
int clusterId = blockIdx.x;
int paramId = threadIdx.x;
center[paramId] = 0.0;
int count = 0;
__syncthreads();
for(int i = 0; i < itemsCount; i++)
{
if(clusterId == clustersIds[i])
{
center[paramId] += items[i * paramsCount + paramId];
count += 1;
}
}
newCenters[clusterId * paramsCount + paramId] = center[paramId];
itemsPerClusters[clusterId] = count;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <float.h>
__device__ float euclid2(
float* items,
float* centers,
int itemId,
int centerId,
int paramsCount)
{
float sum = 0.0;
for(int j = 0; j < paramsCount; j++)
{
sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j])
* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
}
return sum;
}
__global__ void clusreringKernel(
float* items,
float* deviceCenters,
int* clustersIds,
int itemsCount,
int clustersCount,
int paramsCount)
{
extern __shared__ float centers[];
for (int i = threadIdx.x; i < clustersCount; i += blockDim.x)
{
for (int j = 0; j < paramsCount; j++)
{
centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
}
}
__syncthreads();
int itemId = blockDim.x * blockIdx.x + threadIdx.x;
if(itemId < itemsCount)
{
float minDistance = FLT_MAX;
float distance;
int index;
for(int i = 0; i < clustersCount; i++)
{
distance = euclid2(items, centers, itemId, i, paramsCount);
if(minDistance >= distance)
{
minDistance = distance;
index = i;
}
}
clustersIds[itemId] = index;
}
}
__global__ void newCentersKernel(
float* items,
int* clustersIds,
float* newCenters,
int* itemsPerClusters,
int itemsCount,
int clustersCount,
int paramsCount
)
{
extern __shared__ float center[];
int clusterId = blockIdx.x;
int paramId = threadIdx.x;
center[paramId] = 0.0;
int count = 0;
__syncthreads();
for(int i = 0; i < itemsCount; i++)
{
if(clusterId == clustersIds[i])
{
center[paramId] += items[i * paramsCount + paramId];
count += 1;
}
}
newCenters[clusterId * paramsCount + paramId] = center[paramId];
itemsPerClusters[clusterId] = count;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16clusreringKernelPfS_Piiii
.globl _Z16clusreringKernelPfS_Piiii
.p2align 8
.type _Z16clusreringKernelPfS_Piiii,@function
_Z16clusreringKernelPfS_Piiii:
s_load_b64 s[2:3], s[0:1], 0x1c
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x8
s_cmp_gt_i32 s3, 0
v_lshl_add_u32 v4, v0, 2, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s6, s2
s_cselect_b32 s10, -1, 0
s_mov_b32 s9, 0
s_lshl_b32 s11, s2, 2
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s7, 0xffff
s_ashr_i32 s7, s2, 31
s_lshl_b32 s13, s12, 2
s_lshl_b64 s[6:7], s[6:7], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v1, s12, v1
v_add_nc_u32_e32 v4, s13, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, v4
s_mov_b32 s14, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_5:
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_add_i32 s14, s14, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, 0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
v_add_nc_u32_e32 v5, s11, v5
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_15
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s3
v_mov_b32_e32 v6, 0x7f7fffff
s_cmp_gt_i32 s3, 0
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_cselect_b32 s4, -1, 0
s_mov_b32 s5, 0
s_lshl_b32 s6, s3, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_nge_f32_e32 vcc_lo, v6, v7
s_add_i32 s5, s5, s6
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
v_cndmask_b32_e32 v0, s7, v0, vcc_lo
s_add_i32 s7, s7, 1
s_cmp_eq_u32 s7, s2
s_cbranch_scc1 .LBB0_14
.LBB0_10:
v_mov_b32_e32 v7, 0
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_9
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_mov_b32 s8, s5
s_mov_b32 s9, s3
.LBB0_12:
global_load_b32 v8, v[4:5], off
v_mov_b32_e32 v9, s8
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
ds_load_b32 v9, v9
s_add_i32 s9, s9, -1
s_add_i32 s8, s8, 4
s_cmp_lg_u32 s9, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v8
s_cbranch_scc1 .LBB0_12
s_branch .LBB0_9
.LBB0_13:
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16clusreringKernelPfS_Piiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16clusreringKernelPfS_Piiii, .Lfunc_end0-_Z16clusreringKernelPfS_Piiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16newCentersKernelPfPiS_S0_iii
.globl _Z16newCentersKernelPfPiS_S0_iii
.p2align 8
.type _Z16newCentersKernelPfPiS_S0_iii,@function
_Z16newCentersKernelPfPiS_S0_iii:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x28
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, s15
s_mov_b32 s8, 0
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_add_i32 s9, s9, -1
v_add_nc_u32_e32 v1, s3, v1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s9, 0
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, s10
s_cbranch_scc1 .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s8, s8, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
ds_load_b32 v4, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
ds_store_b32 v3, v2
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_load_b128 s[4:7], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
ds_load_b32 v3, v3
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v4, s8
s_lshl_b64 s[0:1], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
global_store_b32 v[0:1], v3, off
global_store_b32 v2, v4, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16newCentersKernelPfPiS_S0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16newCentersKernelPfPiS_S0_iii, .Lfunc_end1-_Z16newCentersKernelPfPiS_S0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16clusreringKernelPfS_Piiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16clusreringKernelPfS_Piiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16newCentersKernelPfPiS_S0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16newCentersKernelPfPiS_S0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <float.h>
__device__ float euclid2(
float* items,
float* centers,
int itemId,
int centerId,
int paramsCount)
{
float sum = 0.0;
for(int j = 0; j < paramsCount; j++)
{
sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j])
* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
}
return sum;
}
__global__ void clusreringKernel(
float* items,
float* deviceCenters,
int* clustersIds,
int itemsCount,
int clustersCount,
int paramsCount)
{
extern __shared__ float centers[];
for (int i = threadIdx.x; i < clustersCount; i += blockDim.x)
{
for (int j = 0; j < paramsCount; j++)
{
centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
}
}
__syncthreads();
int itemId = blockDim.x * blockIdx.x + threadIdx.x;
if(itemId < itemsCount)
{
float minDistance = FLT_MAX;
float distance;
int index;
for(int i = 0; i < clustersCount; i++)
{
distance = euclid2(items, centers, itemId, i, paramsCount);
if(minDistance >= distance)
{
minDistance = distance;
index = i;
}
}
clustersIds[itemId] = index;
}
}
__global__ void newCentersKernel(
float* items,
int* clustersIds,
float* newCenters,
int* itemsPerClusters,
int itemsCount,
int clustersCount,
int paramsCount
)
{
extern __shared__ float center[];
int clusterId = blockIdx.x;
int paramId = threadIdx.x;
center[paramId] = 0.0;
int count = 0;
__syncthreads();
for(int i = 0; i < itemsCount; i++)
{
if(clusterId == clustersIds[i])
{
center[paramId] += items[i * paramsCount + paramId];
count += 1;
}
}
newCenters[clusterId * paramsCount + paramId] = center[paramId];
itemsPerClusters[clusterId] = count;
} | .text
.file "clustering_kernels.hip"
.globl _Z31__device_stub__clusreringKernelPfS_Piiii # -- Begin function _Z31__device_stub__clusreringKernelPfS_Piiii
.p2align 4, 0x90
.type _Z31__device_stub__clusreringKernelPfS_Piiii,@function
_Z31__device_stub__clusreringKernelPfS_Piiii: # @_Z31__device_stub__clusreringKernelPfS_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16clusreringKernelPfS_Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__clusreringKernelPfS_Piiii, .Lfunc_end0-_Z31__device_stub__clusreringKernelPfS_Piiii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__newCentersKernelPfPiS_S0_iii # -- Begin function _Z31__device_stub__newCentersKernelPfPiS_S0_iii
.p2align 4, 0x90
.type _Z31__device_stub__newCentersKernelPfPiS_S0_iii,@function
_Z31__device_stub__newCentersKernelPfPiS_S0_iii: # @_Z31__device_stub__newCentersKernelPfPiS_S0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16newCentersKernelPfPiS_S0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z31__device_stub__newCentersKernelPfPiS_S0_iii, .Lfunc_end1-_Z31__device_stub__newCentersKernelPfPiS_S0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16clusreringKernelPfS_Piiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16newCentersKernelPfPiS_S0_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16clusreringKernelPfS_Piiii,@object # @_Z16clusreringKernelPfS_Piiii
.section .rodata,"a",@progbits
.globl _Z16clusreringKernelPfS_Piiii
.p2align 3, 0x0
_Z16clusreringKernelPfS_Piiii:
.quad _Z31__device_stub__clusreringKernelPfS_Piiii
.size _Z16clusreringKernelPfS_Piiii, 8
.type _Z16newCentersKernelPfPiS_S0_iii,@object # @_Z16newCentersKernelPfPiS_S0_iii
.globl _Z16newCentersKernelPfPiS_S0_iii
.p2align 3, 0x0
_Z16newCentersKernelPfPiS_S0_iii:
.quad _Z31__device_stub__newCentersKernelPfPiS_S0_iii
.size _Z16newCentersKernelPfPiS_S0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16clusreringKernelPfS_Piiii"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16newCentersKernelPfPiS_S0_iii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__clusreringKernelPfS_Piiii
.addrsig_sym _Z31__device_stub__newCentersKernelPfPiS_S0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16clusreringKernelPfS_Piiii
.addrsig_sym _Z16newCentersKernelPfPiS_S0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bafaf_00000000-6_clustering_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7euclid2PfS_iii
.type _Z7euclid2PfS_iii, @function
_Z7euclid2PfS_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7euclid2PfS_iii, .-_Z7euclid2PfS_iii
.globl _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
.type _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii, @function
_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16clusreringKernelPfS_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii, .-_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
.globl _Z16clusreringKernelPfS_Piiii
.type _Z16clusreringKernelPfS_Piiii, @function
_Z16clusreringKernelPfS_Piiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16clusreringKernelPfS_Piiii, .-_Z16clusreringKernelPfS_Piiii
.globl _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
.type _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii, @function
_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16newCentersKernelPfPiS_S0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii, .-_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
.globl _Z16newCentersKernelPfPiS_S0_iii
.type _Z16newCentersKernelPfPiS_S0_iii, @function
_Z16newCentersKernelPfPiS_S0_iii:
.LFB2055:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z16newCentersKernelPfPiS_S0_iii, .-_Z16newCentersKernelPfPiS_S0_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16newCentersKernelPfPiS_S0_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z16clusreringKernelPfS_Piiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16newCentersKernelPfPiS_S0_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16clusreringKernelPfS_Piiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "clustering_kernels.hip"
.globl _Z31__device_stub__clusreringKernelPfS_Piiii # -- Begin function _Z31__device_stub__clusreringKernelPfS_Piiii
.p2align 4, 0x90
.type _Z31__device_stub__clusreringKernelPfS_Piiii,@function
_Z31__device_stub__clusreringKernelPfS_Piiii: # @_Z31__device_stub__clusreringKernelPfS_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16clusreringKernelPfS_Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__clusreringKernelPfS_Piiii, .Lfunc_end0-_Z31__device_stub__clusreringKernelPfS_Piiii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__newCentersKernelPfPiS_S0_iii # -- Begin function _Z31__device_stub__newCentersKernelPfPiS_S0_iii
.p2align 4, 0x90
.type _Z31__device_stub__newCentersKernelPfPiS_S0_iii,@function
_Z31__device_stub__newCentersKernelPfPiS_S0_iii: # @_Z31__device_stub__newCentersKernelPfPiS_S0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16newCentersKernelPfPiS_S0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z31__device_stub__newCentersKernelPfPiS_S0_iii, .Lfunc_end1-_Z31__device_stub__newCentersKernelPfPiS_S0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16clusreringKernelPfS_Piiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16newCentersKernelPfPiS_S0_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16clusreringKernelPfS_Piiii,@object # @_Z16clusreringKernelPfS_Piiii
.section .rodata,"a",@progbits
.globl _Z16clusreringKernelPfS_Piiii
.p2align 3, 0x0
_Z16clusreringKernelPfS_Piiii:
.quad _Z31__device_stub__clusreringKernelPfS_Piiii
.size _Z16clusreringKernelPfS_Piiii, 8
.type _Z16newCentersKernelPfPiS_S0_iii,@object # @_Z16newCentersKernelPfPiS_S0_iii
.globl _Z16newCentersKernelPfPiS_S0_iii
.p2align 3, 0x0
_Z16newCentersKernelPfPiS_S0_iii:
.quad _Z31__device_stub__newCentersKernelPfPiS_S0_iii
.size _Z16newCentersKernelPfPiS_S0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16clusreringKernelPfS_Piiii"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16newCentersKernelPfPiS_S0_iii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__clusreringKernelPfS_Piiii
.addrsig_sym _Z31__device_stub__newCentersKernelPfPiS_S0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16clusreringKernelPfS_Piiii
.addrsig_sym _Z16newCentersKernelPfPiS_S0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<string.h>
/* if poly[blockIdx.x]=',', set result[blockIdx.x]=1. The number of vertices is the number of 1 in result plus 1 */
__global__ void kernel(char *poly, int *result, int len){
if(blockIdx.x<len){
if(poly[blockIdx.x]==',')
result[blockIdx.x] = 1;
else result[blockIdx.x] = 0;
}
}
int countv(char *polygon)
{
char * dev_poly;
int * dev_result;
int * host_result;
int i,result;
int len = strlen(polygon);
cudaMalloc((void **)&dev_poly, len);
cudaMalloc((void **)&dev_result, len*sizeof(int));
cudaMemcpy(dev_poly, polygon, len, cudaMemcpyHostToDevice);
kernel<<<len,1>>> (dev_poly, dev_result, len);
host_result = (int *)malloc(len*sizeof(int));
cudaMemcpy(host_result, dev_result, len*sizeof(int), cudaMemcpyDeviceToHost);
//count the 1's in host_result
result = 0;
for(i=0;i<len;i++){
if(host_result[i]==1)result++;
}
result ++;
return result;
} | code for sm_80
Function : _Z6kernelPcPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fe20007f1e0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0060*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0003 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, 0x2c, PT ; /* 0x0000002c0400780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101904 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<string.h>
/* if poly[blockIdx.x]=',', set result[blockIdx.x]=1. The number of vertices is the number of 1 in result plus 1 */
__global__ void kernel(char *poly, int *result, int len){
if(blockIdx.x<len){
if(poly[blockIdx.x]==',')
result[blockIdx.x] = 1;
else result[blockIdx.x] = 0;
}
}
int countv(char *polygon)
{
char * dev_poly;
int * dev_result;
int * host_result;
int i,result;
int len = strlen(polygon);
cudaMalloc((void **)&dev_poly, len);
cudaMalloc((void **)&dev_result, len*sizeof(int));
cudaMemcpy(dev_poly, polygon, len, cudaMemcpyHostToDevice);
kernel<<<len,1>>> (dev_poly, dev_result, len);
host_result = (int *)malloc(len*sizeof(int));
cudaMemcpy(host_result, dev_result, len*sizeof(int), cudaMemcpyDeviceToHost);
//count the 1's in host_result
result = 0;
for(i=0;i<len;i++){
if(host_result[i]==1)result++;
}
result ++;
return result;
} | .file "tmpxft_000f9c42_00000000-6_countv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6kernelPcPiiPcPii
.type _Z28__device_stub__Z6kernelPcPiiPcPii, @function
_Z28__device_stub__Z6kernelPcPiiPcPii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPcPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6kernelPcPiiPcPii, .-_Z28__device_stub__Z6kernelPcPiiPcPii
.globl _Z6kernelPcPii
.type _Z6kernelPcPii, @function
_Z6kernelPcPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6kernelPcPiiPcPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPcPii, .-_Z6kernelPcPii
.globl _Z6countvPc
.type _Z6countvPc, @function
_Z6countvPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call strlen@PLT
movq %rax, %rbx
movslq %eax, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 0(,%r13,4), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L17
movq %rbp, %rdx
movl %ebx, %ebx
leaq 0(%rbp,%rbx,4), %rsi
movl $0, %eax
.L15:
cmpl $1, (%rdx)
sete %cl
movzbl %cl, %ecx
addl %ecx, %eax
addq $4, %rdx
cmpq %rsi, %rdx
jne .L15
.L13:
addl $1, %eax
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z6kernelPcPiiPcPii
jmp .L12
.L17:
movl $0, %eax
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6countvPc, .-_Z6countvPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPcPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPcPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<string.h>
/* if poly[blockIdx.x]=',', set result[blockIdx.x]=1. The number of vertices is the number of 1 in result plus 1 */
__global__ void kernel(char *poly, int *result, int len){
if(blockIdx.x<len){
if(poly[blockIdx.x]==',')
result[blockIdx.x] = 1;
else result[blockIdx.x] = 0;
}
}
int countv(char *polygon)
{
char * dev_poly;
int * dev_result;
int * host_result;
int i,result;
int len = strlen(polygon);
cudaMalloc((void **)&dev_poly, len);
cudaMalloc((void **)&dev_result, len*sizeof(int));
cudaMemcpy(dev_poly, polygon, len, cudaMemcpyHostToDevice);
kernel<<<len,1>>> (dev_poly, dev_result, len);
host_result = (int *)malloc(len*sizeof(int));
cudaMemcpy(host_result, dev_result, len*sizeof(int), cudaMemcpyDeviceToHost);
//count the 1's in host_result
result = 0;
for(i=0;i<len;i++){
if(host_result[i]==1)result++;
}
result ++;
return result;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<string.h>
/* if poly[blockIdx.x]=',', set result[blockIdx.x]=1. The number of vertices is the number of 1 in result plus 1 */
__global__ void kernel(char *poly, int *result, int len){
if(blockIdx.x<len){
if(poly[blockIdx.x]==',')
result[blockIdx.x] = 1;
else result[blockIdx.x] = 0;
}
}
int countv(char *polygon)
{
char * dev_poly;
int * dev_result;
int * host_result;
int i,result;
int len = strlen(polygon);
hipMalloc((void **)&dev_poly, len);
hipMalloc((void **)&dev_result, len*sizeof(int));
hipMemcpy(dev_poly, polygon, len, hipMemcpyHostToDevice);
kernel<<<len,1>>> (dev_poly, dev_result, len);
host_result = (int *)malloc(len*sizeof(int));
hipMemcpy(host_result, dev_result, len*sizeof(int), hipMemcpyDeviceToHost);
//count the 1's in host_result
result = 0;
for(i=0;i<len;i++){
if(host_result[i]==1)result++;
}
result ++;
return result;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<string.h>
/* if poly[blockIdx.x]=',', set result[blockIdx.x]=1. The number of vertices is the number of 1 in result plus 1 */
__global__ void kernel(char *poly, int *result, int len){
if(blockIdx.x<len){
if(poly[blockIdx.x]==',')
result[blockIdx.x] = 1;
else result[blockIdx.x] = 0;
}
}
int countv(char *polygon)
{
char * dev_poly;
int * dev_result;
int * host_result;
int i,result;
int len = strlen(polygon);
hipMalloc((void **)&dev_poly, len);
hipMalloc((void **)&dev_result, len*sizeof(int));
hipMemcpy(dev_poly, polygon, len, hipMemcpyHostToDevice);
kernel<<<len,1>>> (dev_poly, dev_result, len);
host_result = (int *)malloc(len*sizeof(int));
hipMemcpy(host_result, dev_result, len*sizeof(int), hipMemcpyDeviceToHost);
//count the 1's in host_result
result = 0;
for(i=0;i<len;i++){
if(host_result[i]==1)result++;
}
result ++;
return result;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPcPii
.globl _Z6kernelPcPii
.p2align 8
.type _Z6kernelPcPii,@function
_Z6kernelPcPii:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v0, s15 :: v_dual_mov_b32 v1, 0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
global_load_u8 v0, v0, s[4:5]
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 44, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPcPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPcPii, .Lfunc_end0-_Z6kernelPcPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPcPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPcPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<string.h>
/* if poly[blockIdx.x]=',', set result[blockIdx.x]=1. The number of vertices is the number of 1 in result plus 1 */
__global__ void kernel(char *poly, int *result, int len){
if(blockIdx.x<len){
if(poly[blockIdx.x]==',')
result[blockIdx.x] = 1;
else result[blockIdx.x] = 0;
}
}
int countv(char *polygon)
{
char * dev_poly;
int * dev_result;
int * host_result;
int i,result;
int len = strlen(polygon);
hipMalloc((void **)&dev_poly, len);
hipMalloc((void **)&dev_result, len*sizeof(int));
hipMemcpy(dev_poly, polygon, len, hipMemcpyHostToDevice);
kernel<<<len,1>>> (dev_poly, dev_result, len);
host_result = (int *)malloc(len*sizeof(int));
hipMemcpy(host_result, dev_result, len*sizeof(int), hipMemcpyDeviceToHost);
//count the 1's in host_result
result = 0;
for(i=0;i<len;i++){
if(host_result[i]==1)result++;
}
result ++;
return result;
} | .text
.file "countv.hip"
.globl _Z21__device_stub__kernelPcPii # -- Begin function _Z21__device_stub__kernelPcPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPcPii,@function
_Z21__device_stub__kernelPcPii: # @_Z21__device_stub__kernelPcPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPcPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPcPii, .Lfunc_end0-_Z21__device_stub__kernelPcPii
.cfi_endproc
# -- End function
.globl _Z6countvPc # -- Begin function _Z6countvPc
.p2align 4, 0x90
.type _Z6countvPc,@function
_Z6countvPc: # @_Z6countvPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r12
callq strlen
movq %rax, %r14
movslq %r14d, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq (,%r13,4), %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movl $1, %ebx
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPcPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB1_6
# %bb.3: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorl %edx, %edx
cmpl $1, (%r12,%rcx,4)
sete %dl
addl %edx, %ebx
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
# %bb.5: # %._crit_edge.loopexit
incl %ebx
.LBB1_6: # %._crit_edge
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6countvPc, .Lfunc_end1-_Z6countvPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPcPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPcPii,@object # @_Z6kernelPcPii
.section .rodata,"a",@progbits
.globl _Z6kernelPcPii
.p2align 3, 0x0
_Z6kernelPcPii:
.quad _Z21__device_stub__kernelPcPii
.size _Z6kernelPcPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPcPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPcPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPcPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPcPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fe20007f1e0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0060*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0003 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, 0x2c, PT ; /* 0x0000002c0400780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101904 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPcPii
.globl _Z6kernelPcPii
.p2align 8
.type _Z6kernelPcPii,@function
_Z6kernelPcPii:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v0, s15 :: v_dual_mov_b32 v1, 0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
global_load_u8 v0, v0, s[4:5]
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 44, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPcPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPcPii, .Lfunc_end0-_Z6kernelPcPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPcPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPcPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f9c42_00000000-6_countv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6kernelPcPiiPcPii
.type _Z28__device_stub__Z6kernelPcPiiPcPii, @function
_Z28__device_stub__Z6kernelPcPiiPcPii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPcPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6kernelPcPiiPcPii, .-_Z28__device_stub__Z6kernelPcPiiPcPii
.globl _Z6kernelPcPii
.type _Z6kernelPcPii, @function
_Z6kernelPcPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6kernelPcPiiPcPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPcPii, .-_Z6kernelPcPii
.globl _Z6countvPc
.type _Z6countvPc, @function
_Z6countvPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call strlen@PLT
movq %rax, %rbx
movslq %eax, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 0(,%r13,4), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L17
movq %rbp, %rdx
movl %ebx, %ebx
leaq 0(%rbp,%rbx,4), %rsi
movl $0, %eax
.L15:
cmpl $1, (%rdx)
sete %cl
movzbl %cl, %ecx
addl %ecx, %eax
addq $4, %rdx
cmpq %rsi, %rdx
jne .L15
.L13:
addl $1, %eax
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z6kernelPcPiiPcPii
jmp .L12
.L17:
movl $0, %eax
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6countvPc, .-_Z6countvPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPcPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPcPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "countv.hip"
.globl _Z21__device_stub__kernelPcPii # -- Begin function _Z21__device_stub__kernelPcPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPcPii,@function
_Z21__device_stub__kernelPcPii: # @_Z21__device_stub__kernelPcPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPcPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPcPii, .Lfunc_end0-_Z21__device_stub__kernelPcPii
.cfi_endproc
# -- End function
.globl _Z6countvPc # -- Begin function _Z6countvPc
.p2align 4, 0x90
.type _Z6countvPc,@function
_Z6countvPc: # @_Z6countvPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r12
callq strlen
movq %rax, %r14
movslq %r14d, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq (,%r13,4), %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movl $1, %ebx
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPcPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB1_6
# %bb.3: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorl %edx, %edx
cmpl $1, (%r12,%rcx,4)
sete %dl
addl %edx, %ebx
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
# %bb.5: # %._crit_edge.loopexit
incl %ebx
.LBB1_6: # %._crit_edge
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6countvPc, .Lfunc_end1-_Z6countvPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPcPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPcPii,@object # @_Z6kernelPcPii
.section .rodata,"a",@progbits
.globl _Z6kernelPcPii
.p2align 3, 0x0
_Z6kernelPcPii:
.quad _Z21__device_stub__kernelPcPii
.size _Z6kernelPcPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPcPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPcPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPcPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
//// notes
// based on the examples given in the CUDE programming guide
// this one makes a list of gals, one list for ra and one for dec.
// it can then calcs the separation between gal pairs.
// note that it's not returning anythign from the calculation!
// just calculating how long each process takes.
// Try playing with ngals - time scales as you'd expect with CPU
// ans CPU is fatser with fewer gals.
// then again, this isn't exactly optimised code....
// my numbers:
// 100 gals: 0.6 ms w/ CPU, 13 ms w/ GPU
// 1000 gals: 61 ms w/ CPU, 185 w/ GPU
// 10000 gals: 6085 ms w/ CPU, 4871 w/ GPU
//device code
__global__ void CalcSep(float* raA, float* decA, int ngals)
{
//does all the i's simultaneously - one for each thread
int ix = blockDim.x * blockIdx.x + threadIdx.x;
float sep=0;
// Do 1 ``column"
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
// Then the ngals-ix ``column"
ix = (ngals - 1) - ix;
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
}
//Host code
int main(int argc, char **argv)
{
int ngals = 100;
// Grab the number of galaxies from the command line *if* they have
// been specified.
if (argc>1)
{
ngals = atoi(argv[1]);
}
size_t sizeneededin = ngals * sizeof(float);
//allocate vectors in host memory
float* h_raA = (float*)malloc(sizeneededin);
float* h_decA = (float*)malloc(sizeneededin);
srand(time(0));
//initailise input vectors - place galaxies at rando coords between 0 and 1
for(int i=0;i<ngals;i++)
{
h_raA[i] = rand();
h_decA[i] = rand();
}
//calculate separation in CPU and calculate time needed
clock_t teststart = clock();
float testsep=0;
for(int i=0;i<ngals;i++){
for(int j=i+1;j<ngals;j++){
testsep = acos( sin(h_decA[i])*sin(h_decA[j]) + cos(h_decA[i])*cos(h_decA[j])*cos(fabs(h_raA[i]-h_raA[j])) );
}
}
clock_t testend = clock();
float testelapsed = (float)(testend-teststart);
printf("elapsed time for CPU in ms: %f", testelapsed/CLOCKS_PER_SEC*1000);
printf("\n");
//allocate vectors in device memory
float* d_raA; float* d_decA;
cudaMalloc(&d_raA, sizeneededin);
cudaMalloc(&d_decA, sizeneededin);
//copy vectors from host to device memory
cudaMemcpy(d_raA, h_raA, sizeneededin, cudaMemcpyHostToDevice);
cudaMemcpy(d_decA, h_decA, sizeneededin, cudaMemcpyHostToDevice);
//invoke kernel
int threadsPerBlock = 256;
//int threadsPerBlock = 64;
//int blocksPerGrid = (ngals + threadsPerBlock -1) / threadsPerBlock; //???????
// Only need 1/2 as many threads
int blocksPerGrid = (ngals/2 + threadsPerBlock -1) / threadsPerBlock; //???????
//set up the cuda timer.
//can't use simple CPU timer since that would only time the kernel launch overhead.
// Need to make sure all threads have finished before stop the timer - so can synchronise threads before and after kernel launch if using cpu timer? I didn't get sensible results when I've tried that though.
cudaEvent_t cudastart, cudaend;
cudaEventCreate(&cudastart);
cudaEventCreate(&cudaend);
//record the start time
cudaEventRecord(cudastart,0);
//run the kernel!
CalcSep<<<blocksPerGrid, threadsPerBlock>>>(d_raA, d_decA, ngals);
//record the end time
cudaEventRecord(cudaend,0);
cudaEventSynchronize(cudaend);
//how long did the kernel take? this gives time in ms
float cudaelapsed=0;
cudaEventElapsedTime(&cudaelapsed, cudastart, cudaend);
printf("elapsed time for GPU in ms: %f",cudaelapsed);
printf("\n");
//delete memory
cudaEventDestroy(cudastart);
cudaEventDestroy(cudaend);
//free device memory
cudaFree(d_raA); cudaFree(d_decA);
//free host memory
free(h_raA); free(h_decA);
} | code for sm_80
Function : _Z7CalcSepPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
//// notes
// based on the examples given in the CUDE programming guide
// this one makes a list of gals, one list for ra and one for dec.
// it can then calcs the separation between gal pairs.
// note that it's not returning anythign from the calculation!
// just calculating how long each process takes.
// Try playing with ngals - time scales as you'd expect with CPU
// ans CPU is fatser with fewer gals.
// then again, this isn't exactly optimised code....
// my numbers:
// 100 gals: 0.6 ms w/ CPU, 13 ms w/ GPU
// 1000 gals: 61 ms w/ CPU, 185 w/ GPU
// 10000 gals: 6085 ms w/ CPU, 4871 w/ GPU
//device code
__global__ void CalcSep(float* raA, float* decA, int ngals)
{
//does all the i's simultaneously - one for each thread
int ix = blockDim.x * blockIdx.x + threadIdx.x;
float sep=0;
// Do 1 ``column"
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
// Then the ngals-ix ``column"
ix = (ngals - 1) - ix;
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
}
//Host code
int main(int argc, char **argv)
{
int ngals = 100;
// Grab the number of galaxies from the command line *if* they have
// been specified.
if (argc>1)
{
ngals = atoi(argv[1]);
}
size_t sizeneededin = ngals * sizeof(float);
//allocate vectors in host memory
float* h_raA = (float*)malloc(sizeneededin);
float* h_decA = (float*)malloc(sizeneededin);
srand(time(0));
//initailise input vectors - place galaxies at rando coords between 0 and 1
for(int i=0;i<ngals;i++)
{
h_raA[i] = rand();
h_decA[i] = rand();
}
//calculate separation in CPU and calculate time needed
clock_t teststart = clock();
float testsep=0;
for(int i=0;i<ngals;i++){
for(int j=i+1;j<ngals;j++){
testsep = acos( sin(h_decA[i])*sin(h_decA[j]) + cos(h_decA[i])*cos(h_decA[j])*cos(fabs(h_raA[i]-h_raA[j])) );
}
}
clock_t testend = clock();
float testelapsed = (float)(testend-teststart);
printf("elapsed time for CPU in ms: %f", testelapsed/CLOCKS_PER_SEC*1000);
printf("\n");
//allocate vectors in device memory
float* d_raA; float* d_decA;
cudaMalloc(&d_raA, sizeneededin);
cudaMalloc(&d_decA, sizeneededin);
//copy vectors from host to device memory
cudaMemcpy(d_raA, h_raA, sizeneededin, cudaMemcpyHostToDevice);
cudaMemcpy(d_decA, h_decA, sizeneededin, cudaMemcpyHostToDevice);
//invoke kernel
int threadsPerBlock = 256;
//int threadsPerBlock = 64;
//int blocksPerGrid = (ngals + threadsPerBlock -1) / threadsPerBlock; //???????
// Only need 1/2 as many threads
int blocksPerGrid = (ngals/2 + threadsPerBlock -1) / threadsPerBlock; //???????
//set up the cuda timer.
//can't use simple CPU timer since that would only time the kernel launch overhead.
// Need to make sure all threads have finished before stop the timer - so can synchronise threads before and after kernel launch if using cpu timer? I didn't get sensible results when I've tried that though.
cudaEvent_t cudastart, cudaend;
cudaEventCreate(&cudastart);
cudaEventCreate(&cudaend);
//record the start time
cudaEventRecord(cudastart,0);
//run the kernel!
CalcSep<<<blocksPerGrid, threadsPerBlock>>>(d_raA, d_decA, ngals);
//record the end time
cudaEventRecord(cudaend,0);
cudaEventSynchronize(cudaend);
//how long did the kernel take? this gives time in ms
float cudaelapsed=0;
cudaEventElapsedTime(&cudaelapsed, cudastart, cudaend);
printf("elapsed time for GPU in ms: %f",cudaelapsed);
printf("\n");
//delete memory
cudaEventDestroy(cudastart);
cudaEventDestroy(cudaend);
//free device memory
cudaFree(d_raA); cudaFree(d_decA);
//free host memory
free(h_raA); free(h_decA);
} | .file "tmpxft_0005b55d_00000000-6_calc_separation_timer_Debbie.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7CalcSepPfS_iPfS_i
.type _Z29__device_stub__Z7CalcSepPfS_iPfS_i, @function
_Z29__device_stub__Z7CalcSepPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7CalcSepPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7CalcSepPfS_iPfS_i, .-_Z29__device_stub__Z7CalcSepPfS_iPfS_i
.globl _Z7CalcSepPfS_i
.type _Z7CalcSepPfS_i, @function
_Z7CalcSepPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7CalcSepPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7CalcSepPfS_i, .-_Z7CalcSepPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "elapsed time for CPU in ms: %f"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "elapsed time for GPU in ms: %f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L30
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $400, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq $400, 40(%rsp)
movl $100, 20(%rsp)
movq $100, 32(%rsp)
.L22:
movq %r13, %rbx
movq %r14, %rbp
movq 40(%rsp), %rax
leaq (%rax,%r13), %r12
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L14
call clock@PLT
movq %rax, 48(%rsp)
movl 20(%rsp), %eax
movq %rax, 24(%rsp)
movl $1, %ebp
leaq 60(%rsp), %r15
jmp .L20
.L30:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 20(%rsp)
cltq
movq %rax, 32(%rsp)
leaq 0(,%rax,4), %r15
movq %r15, 40(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jg .L22
call clock@PLT
movq %rax, 48(%rsp)
.L15:
call clock@PLT
movq 48(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movq 40(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl 20(%rsp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal 510(%rax), %edx
addl $255, %eax
cmovs %edx, %eax
sarl $8, %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 108(%rsp)
leaq 108(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq %rax, %rbp
.L20:
movq 24(%rsp), %rax
cmpq %rax, %rbp
je .L15
movq %rbp, %rbx
leaq 56(%rsp), %r12
.L19:
movss -4(%r14,%rbp,4), %xmm0
movq %r12, %rsi
movq %r15, %rdi
call sincosf@PLT
movss 56(%rsp), %xmm2
movss %xmm2, 12(%rsp)
movss 60(%rsp), %xmm3
movss %xmm3, 16(%rsp)
movss (%r14,%rbx,4), %xmm0
movq %r12, %rsi
movq %r15, %rdi
call sincosf@PLT
movss -4(%r13,%rbp,4), %xmm0
subss 0(%r13,%rbx,4), %xmm0
call cosf@PLT
movaps %xmm0, %xmm1
movss 12(%rsp), %xmm0
mulss 56(%rsp), %xmm0
mulss %xmm1, %xmm0
movss 16(%rsp), %xmm1
mulss 60(%rsp), %xmm1
addss %xmm1, %xmm0
ucomiss .LC0(%rip), %xmm0
ja .L16
movss .LC1(%rip), %xmm4
ucomiss %xmm0, %xmm4
ja .L16
.L18:
addq $1, %rbx
cmpl %ebx, 20(%rsp)
jg .L19
leaq 1(%rbp), %rax
cmpq %rbp, 32(%rsp)
jne .L24
jmp .L15
.L16:
call acosf@PLT
jmp .L18
.L31:
movl 20(%rsp), %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z29__device_stub__Z7CalcSepPfS_iPfS_i
jmp .L21
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7CalcSepPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7CalcSepPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long -1082130432
.align 4
.LC2:
.long 1232348160
.align 4
.LC3:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
//// notes
// based on the examples given in the CUDE programming guide
// this one makes a list of gals, one list for ra and one for dec.
// it can then calcs the separation between gal pairs.
// note that it's not returning anythign from the calculation!
// just calculating how long each process takes.
// Try playing with ngals - time scales as you'd expect with CPU
// ans CPU is fatser with fewer gals.
// then again, this isn't exactly optimised code....
// my numbers:
// 100 gals: 0.6 ms w/ CPU, 13 ms w/ GPU
// 1000 gals: 61 ms w/ CPU, 185 w/ GPU
// 10000 gals: 6085 ms w/ CPU, 4871 w/ GPU
//device code
__global__ void CalcSep(float* raA, float* decA, int ngals)
{
//does all the i's simultaneously - one for each thread
int ix = blockDim.x * blockIdx.x + threadIdx.x;
float sep=0;
// Do 1 ``column"
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
// Then the ngals-ix ``column"
ix = (ngals - 1) - ix;
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
}
//Host code
int main(int argc, char **argv)
{
int ngals = 100;
// Grab the number of galaxies from the command line *if* they have
// been specified.
if (argc>1)
{
ngals = atoi(argv[1]);
}
size_t sizeneededin = ngals * sizeof(float);
//allocate vectors in host memory
float* h_raA = (float*)malloc(sizeneededin);
float* h_decA = (float*)malloc(sizeneededin);
srand(time(0));
//initailise input vectors - place galaxies at rando coords between 0 and 1
for(int i=0;i<ngals;i++)
{
h_raA[i] = rand();
h_decA[i] = rand();
}
//calculate separation in CPU and calculate time needed
clock_t teststart = clock();
float testsep=0;
for(int i=0;i<ngals;i++){
for(int j=i+1;j<ngals;j++){
testsep = acos( sin(h_decA[i])*sin(h_decA[j]) + cos(h_decA[i])*cos(h_decA[j])*cos(fabs(h_raA[i]-h_raA[j])) );
}
}
clock_t testend = clock();
float testelapsed = (float)(testend-teststart);
printf("elapsed time for CPU in ms: %f", testelapsed/CLOCKS_PER_SEC*1000);
printf("\n");
//allocate vectors in device memory
float* d_raA; float* d_decA;
cudaMalloc(&d_raA, sizeneededin);
cudaMalloc(&d_decA, sizeneededin);
//copy vectors from host to device memory
cudaMemcpy(d_raA, h_raA, sizeneededin, cudaMemcpyHostToDevice);
cudaMemcpy(d_decA, h_decA, sizeneededin, cudaMemcpyHostToDevice);
//invoke kernel
int threadsPerBlock = 256;
//int threadsPerBlock = 64;
//int blocksPerGrid = (ngals + threadsPerBlock -1) / threadsPerBlock; //???????
// Only need 1/2 as many threads
int blocksPerGrid = (ngals/2 + threadsPerBlock -1) / threadsPerBlock; //???????
//set up the cuda timer.
//can't use simple CPU timer since that would only time the kernel launch overhead.
// Need to make sure all threads have finished before stop the timer - so can synchronise threads before and after kernel launch if using cpu timer? I didn't get sensible results when I've tried that though.
cudaEvent_t cudastart, cudaend;
cudaEventCreate(&cudastart);
cudaEventCreate(&cudaend);
//record the start time
cudaEventRecord(cudastart,0);
//run the kernel!
CalcSep<<<blocksPerGrid, threadsPerBlock>>>(d_raA, d_decA, ngals);
//record the end time
cudaEventRecord(cudaend,0);
cudaEventSynchronize(cudaend);
//how long did the kernel take? this gives time in ms
float cudaelapsed=0;
cudaEventElapsedTime(&cudaelapsed, cudastart, cudaend);
printf("elapsed time for GPU in ms: %f",cudaelapsed);
printf("\n");
//delete memory
cudaEventDestroy(cudastart);
cudaEventDestroy(cudaend);
//free device memory
cudaFree(d_raA); cudaFree(d_decA);
//free host memory
free(h_raA); free(h_decA);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
//// notes
// based on the examples given in the CUDE programming guide
// this one makes a list of gals, one list for ra and one for dec.
// it can then calcs the separation between gal pairs.
// note that it's not returning anythign from the calculation!
// just calculating how long each process takes.
// Try playing with ngals - time scales as you'd expect with CPU
// ans CPU is fatser with fewer gals.
// then again, this isn't exactly optimised code....
// my numbers:
// 100 gals: 0.6 ms w/ CPU, 13 ms w/ GPU
// 1000 gals: 61 ms w/ CPU, 185 w/ GPU
// 10000 gals: 6085 ms w/ CPU, 4871 w/ GPU
//device code
__global__ void CalcSep(float* raA, float* decA, int ngals)
{
//does all the i's simultaneously - one for each thread
int ix = blockDim.x * blockIdx.x + threadIdx.x;
float sep=0;
// Do 1 ``column"
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
// Then the ngals-ix ``column"
ix = (ngals - 1) - ix;
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
}
//Host code
int main(int argc, char **argv)
{
int ngals = 100;
// Grab the number of galaxies from the command line *if* they have
// been specified.
if (argc>1)
{
ngals = atoi(argv[1]);
}
size_t sizeneededin = ngals * sizeof(float);
//allocate vectors in host memory
float* h_raA = (float*)malloc(sizeneededin);
float* h_decA = (float*)malloc(sizeneededin);
srand(time(0));
//initailise input vectors - place galaxies at rando coords between 0 and 1
for(int i=0;i<ngals;i++)
{
h_raA[i] = rand();
h_decA[i] = rand();
}
//calculate separation in CPU and calculate time needed
clock_t teststart = clock();
float testsep=0;
for(int i=0;i<ngals;i++){
for(int j=i+1;j<ngals;j++){
testsep = acos( sin(h_decA[i])*sin(h_decA[j]) + cos(h_decA[i])*cos(h_decA[j])*cos(fabs(h_raA[i]-h_raA[j])) );
}
}
clock_t testend = clock();
float testelapsed = (float)(testend-teststart);
printf("elapsed time for CPU in ms: %f", testelapsed/CLOCKS_PER_SEC*1000);
printf("\n");
//allocate vectors in device memory
float* d_raA; float* d_decA;
hipMalloc(&d_raA, sizeneededin);
hipMalloc(&d_decA, sizeneededin);
//copy vectors from host to device memory
hipMemcpy(d_raA, h_raA, sizeneededin, hipMemcpyHostToDevice);
hipMemcpy(d_decA, h_decA, sizeneededin, hipMemcpyHostToDevice);
//invoke kernel
int threadsPerBlock = 256;
//int threadsPerBlock = 64;
//int blocksPerGrid = (ngals + threadsPerBlock -1) / threadsPerBlock; //???????
// Only need 1/2 as many threads
int blocksPerGrid = (ngals/2 + threadsPerBlock -1) / threadsPerBlock; //???????
//set up the cuda timer.
//can't use simple CPU timer since that would only time the kernel launch overhead.
// Need to make sure all threads have finished before stop the timer - so can synchronise threads before and after kernel launch if using cpu timer? I didn't get sensible results when I've tried that though.
hipEvent_t cudastart, cudaend;
hipEventCreate(&cudastart);
hipEventCreate(&cudaend);
//record the start time
hipEventRecord(cudastart,0);
//run the kernel!
CalcSep<<<blocksPerGrid, threadsPerBlock>>>(d_raA, d_decA, ngals);
//record the end time
hipEventRecord(cudaend,0);
hipEventSynchronize(cudaend);
//how long did the kernel take? this gives time in ms
float cudaelapsed=0;
hipEventElapsedTime(&cudaelapsed, cudastart, cudaend);
printf("elapsed time for GPU in ms: %f",cudaelapsed);
printf("\n");
//delete memory
hipEventDestroy(cudastart);
hipEventDestroy(cudaend);
//free device memory
hipFree(d_raA); hipFree(d_decA);
//free host memory
free(h_raA); free(h_decA);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
//// notes
// based on the examples given in the CUDE programming guide
// this one makes a list of gals, one list for ra and one for dec.
// it can then calcs the separation between gal pairs.
// note that it's not returning anythign from the calculation!
// just calculating how long each process takes.
// Try playing with ngals - time scales as you'd expect with CPU
// ans CPU is fatser with fewer gals.
// then again, this isn't exactly optimised code....
// my numbers:
// 100 gals: 0.6 ms w/ CPU, 13 ms w/ GPU
// 1000 gals: 61 ms w/ CPU, 185 w/ GPU
// 10000 gals: 6085 ms w/ CPU, 4871 w/ GPU
//device code
__global__ void CalcSep(float* raA, float* decA, int ngals)
{
//does all the i's simultaneously - one for each thread
int ix = blockDim.x * blockIdx.x + threadIdx.x;
float sep=0;
// Do 1 ``column"
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
// Then the ngals-ix ``column"
ix = (ngals - 1) - ix;
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
}
//Host code
int main(int argc, char **argv)
{
int ngals = 100;
// Grab the number of galaxies from the command line *if* they have
// been specified.
if (argc>1)
{
ngals = atoi(argv[1]);
}
size_t sizeneededin = ngals * sizeof(float);
//allocate vectors in host memory
float* h_raA = (float*)malloc(sizeneededin);
float* h_decA = (float*)malloc(sizeneededin);
srand(time(0));
//initailise input vectors - place galaxies at rando coords between 0 and 1
for(int i=0;i<ngals;i++)
{
h_raA[i] = rand();
h_decA[i] = rand();
}
//calculate separation in CPU and calculate time needed
clock_t teststart = clock();
float testsep=0;
for(int i=0;i<ngals;i++){
for(int j=i+1;j<ngals;j++){
testsep = acos( sin(h_decA[i])*sin(h_decA[j]) + cos(h_decA[i])*cos(h_decA[j])*cos(fabs(h_raA[i]-h_raA[j])) );
}
}
clock_t testend = clock();
float testelapsed = (float)(testend-teststart);
printf("elapsed time for CPU in ms: %f", testelapsed/CLOCKS_PER_SEC*1000);
printf("\n");
//allocate vectors in device memory
float* d_raA; float* d_decA;
hipMalloc(&d_raA, sizeneededin);
hipMalloc(&d_decA, sizeneededin);
//copy vectors from host to device memory
hipMemcpy(d_raA, h_raA, sizeneededin, hipMemcpyHostToDevice);
hipMemcpy(d_decA, h_decA, sizeneededin, hipMemcpyHostToDevice);
//invoke kernel
int threadsPerBlock = 256;
//int threadsPerBlock = 64;
//int blocksPerGrid = (ngals + threadsPerBlock -1) / threadsPerBlock; //???????
// Only need 1/2 as many threads
int blocksPerGrid = (ngals/2 + threadsPerBlock -1) / threadsPerBlock; //???????
//set up the cuda timer.
//can't use simple CPU timer since that would only time the kernel launch overhead.
// Need to make sure all threads have finished before stop the timer - so can synchronise threads before and after kernel launch if using cpu timer? I didn't get sensible results when I've tried that though.
hipEvent_t cudastart, cudaend;
hipEventCreate(&cudastart);
hipEventCreate(&cudaend);
//record the start time
hipEventRecord(cudastart,0);
//run the kernel!
CalcSep<<<blocksPerGrid, threadsPerBlock>>>(d_raA, d_decA, ngals);
//record the end time
hipEventRecord(cudaend,0);
hipEventSynchronize(cudaend);
//how long did the kernel take? this gives time in ms
float cudaelapsed=0;
hipEventElapsedTime(&cudaelapsed, cudastart, cudaend);
printf("elapsed time for GPU in ms: %f",cudaelapsed);
printf("\n");
//delete memory
hipEventDestroy(cudastart);
hipEventDestroy(cudaend);
//free device memory
hipFree(d_raA); hipFree(d_decA);
//free host memory
free(h_raA); free(h_decA);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7CalcSepPfS_i
.globl _Z7CalcSepPfS_i
.p2align 8
.type _Z7CalcSepPfS_i,@function
_Z7CalcSepPfS_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7CalcSepPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7CalcSepPfS_i, .Lfunc_end0-_Z7CalcSepPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7CalcSepPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7CalcSepPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
//// notes
// based on the examples given in the CUDE programming guide
// this one makes a list of gals, one list for ra and one for dec.
// it can then calcs the separation between gal pairs.
// note that it's not returning anythign from the calculation!
// just calculating how long each process takes.
// Try playing with ngals - time scales as you'd expect with CPU
// ans CPU is fatser with fewer gals.
// then again, this isn't exactly optimised code....
// my numbers:
// 100 gals: 0.6 ms w/ CPU, 13 ms w/ GPU
// 1000 gals: 61 ms w/ CPU, 185 w/ GPU
// 10000 gals: 6085 ms w/ CPU, 4871 w/ GPU
//device code
__global__ void CalcSep(float* raA, float* decA, int ngals)
{
//does all the i's simultaneously - one for each thread
int ix = blockDim.x * blockIdx.x + threadIdx.x;
float sep=0;
// Do 1 ``column"
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
// Then the ngals-ix ``column"
ix = (ngals - 1) - ix;
for(int ij=ix+1;ij<ngals;ij++)
{
sep = acos( sin(decA[ix])*sin(decA[ij]) + \
cos(decA[ix])*cos(decA[ij])*cos(fabs(raA[ix]-raA[ij])) );
}//loop over gals
}
//Host code
int main(int argc, char **argv)
{
int ngals = 100;
// Grab the number of galaxies from the command line *if* they have
// been specified.
if (argc>1)
{
ngals = atoi(argv[1]);
}
size_t sizeneededin = ngals * sizeof(float);
//allocate vectors in host memory
float* h_raA = (float*)malloc(sizeneededin);
float* h_decA = (float*)malloc(sizeneededin);
srand(time(0));
//initailise input vectors - place galaxies at rando coords between 0 and 1
for(int i=0;i<ngals;i++)
{
h_raA[i] = rand();
h_decA[i] = rand();
}
//calculate separation in CPU and calculate time needed
clock_t teststart = clock();
float testsep=0;
for(int i=0;i<ngals;i++){
for(int j=i+1;j<ngals;j++){
testsep = acos( sin(h_decA[i])*sin(h_decA[j]) + cos(h_decA[i])*cos(h_decA[j])*cos(fabs(h_raA[i]-h_raA[j])) );
}
}
clock_t testend = clock();
float testelapsed = (float)(testend-teststart);
printf("elapsed time for CPU in ms: %f", testelapsed/CLOCKS_PER_SEC*1000);
printf("\n");
//allocate vectors in device memory
float* d_raA; float* d_decA;
hipMalloc(&d_raA, sizeneededin);
hipMalloc(&d_decA, sizeneededin);
//copy vectors from host to device memory
hipMemcpy(d_raA, h_raA, sizeneededin, hipMemcpyHostToDevice);
hipMemcpy(d_decA, h_decA, sizeneededin, hipMemcpyHostToDevice);
//invoke kernel
int threadsPerBlock = 256;
//int threadsPerBlock = 64;
//int blocksPerGrid = (ngals + threadsPerBlock -1) / threadsPerBlock; //???????
// Only need 1/2 as many threads
int blocksPerGrid = (ngals/2 + threadsPerBlock -1) / threadsPerBlock; //???????
//set up the cuda timer.
//can't use simple CPU timer since that would only time the kernel launch overhead.
// Need to make sure all threads have finished before stop the timer - so can synchronise threads before and after kernel launch if using cpu timer? I didn't get sensible results when I've tried that though.
hipEvent_t cudastart, cudaend;
hipEventCreate(&cudastart);
hipEventCreate(&cudaend);
//record the start time
hipEventRecord(cudastart,0);
//run the kernel!
CalcSep<<<blocksPerGrid, threadsPerBlock>>>(d_raA, d_decA, ngals);
//record the end time
hipEventRecord(cudaend,0);
hipEventSynchronize(cudaend);
//how long did the kernel take? this gives time in ms
float cudaelapsed=0;
hipEventElapsedTime(&cudaelapsed, cudastart, cudaend);
printf("elapsed time for GPU in ms: %f",cudaelapsed);
printf("\n");
//delete memory
hipEventDestroy(cudastart);
hipEventDestroy(cudaend);
//free device memory
hipFree(d_raA); hipFree(d_decA);
//free host memory
free(h_raA); free(h_decA);
} | .text
.file "calc_separation_timer_Debbie.hip"
.globl _Z22__device_stub__CalcSepPfS_i # -- Begin function _Z22__device_stub__CalcSepPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__CalcSepPfS_i,@function
_Z22__device_stub__CalcSepPfS_i: # @_Z22__device_stub__CalcSepPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7CalcSepPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__CalcSepPfS_i, .Lfunc_end0-_Z22__device_stub__CalcSepPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0xbf800000 # float -1
.LCPI1_2:
.long 0x3f800000 # float 1
.LCPI1_3:
.long 0x49742400 # float 1.0E+6
.LCPI1_4:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100, %r12d
cmpl $2, %edi
jl .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
.LBB1_2:
movslq %r12d, %rbx
leaq (,%rbx,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, 104(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r12d, %r13d
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rbx,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq %r15, 24(%rsp) # 8-byte Spill
movq %r14, 16(%rsp) # 8-byte Spill
callq clock
movq %rax, 96(%rsp) # 8-byte Spill
movq %r12, 112(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB1_9
# %bb.6: # %.lr.ph63.preheader
xorl %ecx, %ecx
movq %r13, %rbp
movq 24(%rsp), %r14 # 8-byte Reload
movq 16(%rsp), %rbx # 8-byte Reload
movq %r13, 120(%rsp) # 8-byte Spill
movq 24(%rsp), %r12 # 8-byte Reload
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_8: # %.loopexit
# in Loop: Header=BB1_7 Depth=1
addq $4, %rbx
addq $4, %r14
decq %rbp
movq 120(%rsp), %r13 # 8-byte Reload
movq 128(%rsp), %rcx # 8-byte Reload
cmpq %r13, %rcx
je .LBB1_9
.LBB1_7: # %.lr.ph63
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movq %r13, %rax
movq %rcx, %r13
incq %rcx
movq %rcx, 128(%rsp) # 8-byte Spill
cmpq %rax, %rcx
jae .LBB1_8
# %bb.12: # %.lr.ph60
# in Loop: Header=BB1_7 Depth=1
movl $1, %r15d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq sinf
movss %xmm0, 4(%rsp) # 4-byte Spill
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq sinf
mulss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 4(%rsp) # 4-byte Spill
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq cosf
movss %xmm0, (%rsp) # 4-byte Spill
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq cosf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rsp) # 4-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
movss (%rax,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm0
andps .LCPI1_0(%rip), %xmm0
callq cosf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
addss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=2
ucomiss .LCPI1_2(%rip), %xmm0
ja .LBB1_15
.LBB1_16: # %cdce.end
# in Loop: Header=BB1_13 Depth=2
incq %r15
cmpq %r15, %rbp
jne .LBB1_13
jmp .LBB1_8
.LBB1_15: # %cdce.call
# in Loop: Header=BB1_13 Depth=2
callq acosf
jmp .LBB1_16
.LBB1_9: # %._crit_edge64
callq clock
subq 96(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_3(%rip), %xmm0
mulss .LCPI1_4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
leaq 48(%rsp), %rdi
movq 104(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 16(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 24(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp), %r12 # 8-byte Reload
movl %r12d, %r14d
shrl $31, %r14d
addl %r12d, %r14d
sarl %r14d
leal 255(%r14), %eax
addl $510, %r14d # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $8, %r14d
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r14
orq $256, %rdx # imm = 0x100
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl %r12d, 60(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7CalcSepPfS_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 64(%rsp)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7CalcSepPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7CalcSepPfS_i,@object # @_Z7CalcSepPfS_i
.section .rodata,"a",@progbits
.globl _Z7CalcSepPfS_i
.p2align 3, 0x0
_Z7CalcSepPfS_i:
.quad _Z22__device_stub__CalcSepPfS_i
.size _Z7CalcSepPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "elapsed time for CPU in ms: %f"
.size .L.str, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "elapsed time for GPU in ms: %f"
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7CalcSepPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__CalcSepPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7CalcSepPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7CalcSepPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7CalcSepPfS_i
.globl _Z7CalcSepPfS_i
.p2align 8
.type _Z7CalcSepPfS_i,@function
_Z7CalcSepPfS_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7CalcSepPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7CalcSepPfS_i, .Lfunc_end0-_Z7CalcSepPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7CalcSepPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7CalcSepPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005b55d_00000000-6_calc_separation_timer_Debbie.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7CalcSepPfS_iPfS_i
.type _Z29__device_stub__Z7CalcSepPfS_iPfS_i, @function
_Z29__device_stub__Z7CalcSepPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7CalcSepPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7CalcSepPfS_iPfS_i, .-_Z29__device_stub__Z7CalcSepPfS_iPfS_i
.globl _Z7CalcSepPfS_i
.type _Z7CalcSepPfS_i, @function
_Z7CalcSepPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7CalcSepPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7CalcSepPfS_i, .-_Z7CalcSepPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "elapsed time for CPU in ms: %f"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "elapsed time for GPU in ms: %f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L30
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $400, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq $400, 40(%rsp)
movl $100, 20(%rsp)
movq $100, 32(%rsp)
.L22:
movq %r13, %rbx
movq %r14, %rbp
movq 40(%rsp), %rax
leaq (%rax,%r13), %r12
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L14
call clock@PLT
movq %rax, 48(%rsp)
movl 20(%rsp), %eax
movq %rax, 24(%rsp)
movl $1, %ebp
leaq 60(%rsp), %r15
jmp .L20
.L30:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 20(%rsp)
cltq
movq %rax, 32(%rsp)
leaq 0(,%rax,4), %r15
movq %r15, 40(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jg .L22
call clock@PLT
movq %rax, 48(%rsp)
.L15:
call clock@PLT
movq 48(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movq 40(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl 20(%rsp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal 510(%rax), %edx
addl $255, %eax
cmovs %edx, %eax
sarl $8, %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 108(%rsp)
leaq 108(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq %rax, %rbp
.L20:
movq 24(%rsp), %rax
cmpq %rax, %rbp
je .L15
movq %rbp, %rbx
leaq 56(%rsp), %r12
.L19:
movss -4(%r14,%rbp,4), %xmm0
movq %r12, %rsi
movq %r15, %rdi
call sincosf@PLT
movss 56(%rsp), %xmm2
movss %xmm2, 12(%rsp)
movss 60(%rsp), %xmm3
movss %xmm3, 16(%rsp)
movss (%r14,%rbx,4), %xmm0
movq %r12, %rsi
movq %r15, %rdi
call sincosf@PLT
movss -4(%r13,%rbp,4), %xmm0
subss 0(%r13,%rbx,4), %xmm0
call cosf@PLT
movaps %xmm0, %xmm1
movss 12(%rsp), %xmm0
mulss 56(%rsp), %xmm0
mulss %xmm1, %xmm0
movss 16(%rsp), %xmm1
mulss 60(%rsp), %xmm1
addss %xmm1, %xmm0
ucomiss .LC0(%rip), %xmm0
ja .L16
movss .LC1(%rip), %xmm4
ucomiss %xmm0, %xmm4
ja .L16
.L18:
addq $1, %rbx
cmpl %ebx, 20(%rsp)
jg .L19
leaq 1(%rbp), %rax
cmpq %rbp, 32(%rsp)
jne .L24
jmp .L15
.L16:
call acosf@PLT
jmp .L18
.L31:
movl 20(%rsp), %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z29__device_stub__Z7CalcSepPfS_iPfS_i
jmp .L21
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7CalcSepPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7CalcSepPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long -1082130432
.align 4
.LC2:
.long 1232348160
.align 4
.LC3:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calc_separation_timer_Debbie.hip"
.globl _Z22__device_stub__CalcSepPfS_i # -- Begin function _Z22__device_stub__CalcSepPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__CalcSepPfS_i,@function
_Z22__device_stub__CalcSepPfS_i: # @_Z22__device_stub__CalcSepPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7CalcSepPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__CalcSepPfS_i, .Lfunc_end0-_Z22__device_stub__CalcSepPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0xbf800000 # float -1
.LCPI1_2:
.long 0x3f800000 # float 1
.LCPI1_3:
.long 0x49742400 # float 1.0E+6
.LCPI1_4:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100, %r12d
cmpl $2, %edi
jl .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
.LBB1_2:
movslq %r12d, %rbx
leaq (,%rbx,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, 104(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r12d, %r13d
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rbx,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq %r15, 24(%rsp) # 8-byte Spill
movq %r14, 16(%rsp) # 8-byte Spill
callq clock
movq %rax, 96(%rsp) # 8-byte Spill
movq %r12, 112(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB1_9
# %bb.6: # %.lr.ph63.preheader
xorl %ecx, %ecx
movq %r13, %rbp
movq 24(%rsp), %r14 # 8-byte Reload
movq 16(%rsp), %rbx # 8-byte Reload
movq %r13, 120(%rsp) # 8-byte Spill
movq 24(%rsp), %r12 # 8-byte Reload
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_8: # %.loopexit
# in Loop: Header=BB1_7 Depth=1
addq $4, %rbx
addq $4, %r14
decq %rbp
movq 120(%rsp), %r13 # 8-byte Reload
movq 128(%rsp), %rcx # 8-byte Reload
cmpq %r13, %rcx
je .LBB1_9
.LBB1_7: # %.lr.ph63
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movq %r13, %rax
movq %rcx, %r13
incq %rcx
movq %rcx, 128(%rsp) # 8-byte Spill
cmpq %rax, %rcx
jae .LBB1_8
# %bb.12: # %.lr.ph60
# in Loop: Header=BB1_7 Depth=1
movl $1, %r15d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq sinf
movss %xmm0, 4(%rsp) # 4-byte Spill
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq sinf
mulss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 4(%rsp) # 4-byte Spill
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq cosf
movss %xmm0, (%rsp) # 4-byte Spill
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq cosf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rsp) # 4-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
movss (%rax,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm0
andps .LCPI1_0(%rip), %xmm0
callq cosf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
addss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=2
ucomiss .LCPI1_2(%rip), %xmm0
ja .LBB1_15
.LBB1_16: # %cdce.end
# in Loop: Header=BB1_13 Depth=2
incq %r15
cmpq %r15, %rbp
jne .LBB1_13
jmp .LBB1_8
.LBB1_15: # %cdce.call
# in Loop: Header=BB1_13 Depth=2
callq acosf
jmp .LBB1_16
.LBB1_9: # %._crit_edge64
callq clock
subq 96(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_3(%rip), %xmm0
mulss .LCPI1_4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
leaq 48(%rsp), %rdi
movq 104(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 16(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 24(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp), %r12 # 8-byte Reload
movl %r12d, %r14d
shrl $31, %r14d
addl %r12d, %r14d
sarl %r14d
leal 255(%r14), %eax
addl $510, %r14d # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $8, %r14d
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r14
orq $256, %rdx # imm = 0x100
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl %r12d, 60(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7CalcSepPfS_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 64(%rsp)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7CalcSepPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7CalcSepPfS_i,@object # @_Z7CalcSepPfS_i
.section .rodata,"a",@progbits
.globl _Z7CalcSepPfS_i
.p2align 3, 0x0
_Z7CalcSepPfS_i:
.quad _Z22__device_stub__CalcSepPfS_i
.size _Z7CalcSepPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "elapsed time for CPU in ms: %f"
.size .L.str, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "elapsed time for GPU in ms: %f"
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7CalcSepPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__CalcSepPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7CalcSepPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "iostream"
__global__ void feelScreenGPU(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations) {
int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
//if (threadNum < ScreenWidth * ScreenHeight) {
int count = 0;
double r1 = 0;
double r2 = leftB + pWidth * (threadNum % ScreenWidth);
double c1 = 0;
double c2 = downB + pHeight * (threadNum / ScreenHeight);
while (count < iterations)
{
double r1Temp = r1;
r1 = r1 * r1 - c1 * c1 + r2;
c1 = 2 * r1Temp * c1 + c2;
if ((r1 * r1 + c1 * c1) > 4) {
break;
}
count++;
}
screen[threadNum] = count;
//}
}
void CalculateScreen(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations, int Blocks, int Threads) {
feelScreenGPU <<<Blocks, Threads>>> (screen, ScreenWidth, ScreenHeight, leftB, downB, pWidth, pHeight, iterations);
cudaDeviceSynchronize();
}
void FreeMem(int* screen) {
cudaFree(screen);
}
int* AllocateMem(int* screen, int memSize) {
cudaMallocManaged(&screen, memSize * sizeof(int));
return screen;
} | code for sm_80
Function : _Z13feelScreenGPUPiiiddddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R3, c[0x0][0x16c] ; /* 0x00005b0000037a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0030*/ IABS R2, c[0x0][0x168] ; /* 0x00005a0000027a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ I2F.RP R8, R3 ; /* 0x0000000300087306 */
/* 0x000e620000209400 */
/*0060*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0070*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f85270 */
/*0080*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e00ff */
/*0090*/ I2F.RP R0, R2 ; /* 0x0000000200007306 */
/* 0x000eb00000209400 */
/*00a0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e700000001000 */
/*00b0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x004ea20000001000 */
/*00c0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fce0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002e2000021f000 */
/*00e0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x004fe20007ffe0ff */
/*00f0*/ IMAD R0, R9, c[0x0][0x0], R10 ; /* 0x0000000009007a24 */
/* 0x001fcc00078e020a */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0000a2000021f000 */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x002fe200000001ff */
/*0120*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0130*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0140*/ IMAD.MOV R12, RZ, RZ, -R7 ; /* 0x000000ffff0c7224 */
/* 0x008fe400078e0a07 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fc600078e00ff */
/*0160*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x004fc800078e0a05 */
/*0180*/ IMAD R9, R11, R2, RZ ; /* 0x000000020b097224 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD R11, R10, R3, RZ ; /* 0x000000030a0b7224 */
/* 0x000fe400078e02ff */
/*01a0*/ IMAD.HI.U32 R4, R5, R9, R4 ; /* 0x0000000905047227 */
/* 0x000fc800078e0004 */
/*01b0*/ IMAD.HI.U32 R6, R7, R11, R6 ; /* 0x0000000b07067227 */
/* 0x000fc800078e0006 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0008 */
/*01d0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0a7624 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.HI.U32 R4, R4, R9, RZ ; /* 0x0000000904047227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.HI.U32 R6, R6, R9, RZ ; /* 0x0000000906067227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a04 */
/*0210*/ IMAD.MOV R8, RZ, RZ, -R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0a06 */
/*0220*/ IMAD R5, R2.reuse, R4, R9.reuse ; /* 0x0000000402057224 */
/* 0x140fe400078e0209 */
/*0230*/ IMAD R4, R3.reuse, R8, R9 ; /* 0x0000000803047224 */
/* 0x040fe200078e0209 */
/*0240*/ MOV R8, c[0x0][0x188] ; /* 0x0000620000087a02 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe200078e00ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f24070 */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff097624 */
/* 0x000fe200078e00ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fd60003f04070 */
/*0290*/ @!P1 IADD3 R5, R5, -R2, RZ ; /* 0x8000000205059210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R3 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a03 */
/*02b0*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.GT.U32.AND P5, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003fa4070 */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fe40003f26070 */
/*02e0*/ LOP3.LUT R3, R0, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0000037a12 */
/* 0x000fe400078e3cff */
/*02f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fc40003f05270 */
/*0300*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f66270 */
/*0310*/ @!P5 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x000000010505d824 */
/* 0x000fe400078e0a02 */
/*0320*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fc60007ffe0ff */
/*0330*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0350*/ @!P4 LOP3.LUT R5, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff05ca12 */
/* 0x000fe400078e33ff */
/*0360*/ MOV R6, c[0x0][0x180] ; /* 0x0000600000067a02 */
/* 0x000fe20000000f00 */
/*0370*/ @!P3 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04b224 */
/* 0x000fe200078e0a04 */
/*0380*/ @!P0 LOP3.LUT R4, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff048a12 */
/* 0x000fe200078e33ff */
/*0390*/ I2F.F64 R2, R5 ; /* 0x0000000500027312 */
/* 0x000e220000201c00 */
/*03a0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fce0003f06270 */
/*03b0*/ I2F.F64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e620000201c00 */
/*03c0*/ DFMA R2, R2, R6, c[0x0][0x170] ; /* 0x00005c000202762b */
/* 0x0010880000000006 */
/*03d0*/ DFMA R10, R4, R8, c[0x0][0x178] ; /* 0x00005e00040a762b */
/* 0x0020620000000008 */
/*03e0*/ @!P0 BRA 0x520 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*03f0*/ BSSY B0, 0x520 ; /* 0x0000012000007945 */
/* 0x004fe20003800000 */
/*0400*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*0410*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x001fe2000001ff00 */
/*0420*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fca000001ff00 */
/*0430*/ DMUL R8, R4, R4 ; /* 0x0000000404087228 */
/* 0x000e0c0000000000 */
/*0440*/ DFMA R8, R6, R6, -R8 ; /* 0x000000060608722b */
/* 0x001e080000000808 */
/*0450*/ DADD R6, R6, R6 ; /* 0x0000000006067229 */
/* 0x000e880000000006 */
/*0460*/ DADD R8, R2, R8 ; /* 0x0000000002087229 */
/* 0x001e080000000008 */
/*0470*/ DFMA R4, R6, R4, R10 ; /* 0x000000040604722b */
/* 0x006fc8000000000a */
/*0480*/ DMUL R6, R8, R8 ; /* 0x0000000808067228 */
/* 0x001e0c0000000000 */
/*0490*/ DFMA R6, R4, R4, R6 ; /* 0x000000040406722b */
/* 0x001e0c0000000006 */
/*04a0*/ DSETP.GT.AND P0, PT, R6, 4, PT ; /* 0x401000000600742a */
/* 0x001e1c0003f04000 */
/*04b0*/ @P0 BRA 0x510 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*04c0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*04e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*04f0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x190], PT ; /* 0x000064000d007a0c */
/* 0x000fda0003f06270 */
/*0500*/ @!P0 BRA 0x430 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0520*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x004fca0000000f00 */
/*0530*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0540*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "iostream"
__global__ void feelScreenGPU(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations) {
int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
//if (threadNum < ScreenWidth * ScreenHeight) {
int count = 0;
double r1 = 0;
double r2 = leftB + pWidth * (threadNum % ScreenWidth);
double c1 = 0;
double c2 = downB + pHeight * (threadNum / ScreenHeight);
while (count < iterations)
{
double r1Temp = r1;
r1 = r1 * r1 - c1 * c1 + r2;
c1 = 2 * r1Temp * c1 + c2;
if ((r1 * r1 + c1 * c1) > 4) {
break;
}
count++;
}
screen[threadNum] = count;
//}
}
void CalculateScreen(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations, int Blocks, int Threads) {
feelScreenGPU <<<Blocks, Threads>>> (screen, ScreenWidth, ScreenHeight, leftB, downB, pWidth, pHeight, iterations);
cudaDeviceSynchronize();
}
void FreeMem(int* screen) {
cudaFree(screen);
}
int* AllocateMem(int* screen, int memSize) {
cudaMallocManaged(&screen, memSize * sizeof(int));
return screen;
} | .file "tmpxft_001087f9_00000000-6_KernelFunction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7FreeMemPi
.type _Z7FreeMemPi, @function
_Z7FreeMemPi:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z7FreeMemPi, .-_Z7FreeMemPi
.globl _Z11AllocateMemPii
.type _Z11AllocateMemPii, @function
_Z11AllocateMemPii:
.LFB3671:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, 8(%rsp)
movslq %esi, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z11AllocateMemPii, .-_Z11AllocateMemPii
.globl _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
.type _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi, @function
_Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi:
.LFB3696:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movsd %xmm3, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13feelScreenGPUPiiiddddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi, .-_Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
.globl _Z13feelScreenGPUPiiiddddi
.type _Z13feelScreenGPUPiiiddddi, @function
_Z13feelScreenGPUPiiiddddi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z13feelScreenGPUPiiiddddi, .-_Z13feelScreenGPUPiiiddddi
.globl _Z15CalculateScreenPiiiddddiii
.type _Z15CalculateScreenPiiiddddiii, @function
_Z15CalculateScreenPiiiddddiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movsd %xmm0, (%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 24(%rsp)
movl %ecx, %r13d
movl %r9d, 52(%rsp)
movl $1, 56(%rsp)
movl %r8d, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %r13d, %ecx
movsd 24(%rsp), %xmm3
movsd 16(%rsp), %xmm2
movsd 8(%rsp), %xmm1
movsd (%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
jmp .L16
.cfi_endproc
.LFE3669:
.size _Z15CalculateScreenPiiiddddiii, .-_Z15CalculateScreenPiiiddddiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13feelScreenGPUPiiiddddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13feelScreenGPUPiiiddddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "iostream"
__global__ void feelScreenGPU(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations) {
int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
//if (threadNum < ScreenWidth * ScreenHeight) {
int count = 0;
double r1 = 0;
double r2 = leftB + pWidth * (threadNum % ScreenWidth);
double c1 = 0;
double c2 = downB + pHeight * (threadNum / ScreenHeight);
while (count < iterations)
{
double r1Temp = r1;
r1 = r1 * r1 - c1 * c1 + r2;
c1 = 2 * r1Temp * c1 + c2;
if ((r1 * r1 + c1 * c1) > 4) {
break;
}
count++;
}
screen[threadNum] = count;
//}
}
void CalculateScreen(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations, int Blocks, int Threads) {
feelScreenGPU <<<Blocks, Threads>>> (screen, ScreenWidth, ScreenHeight, leftB, downB, pWidth, pHeight, iterations);
cudaDeviceSynchronize();
}
void FreeMem(int* screen) {
cudaFree(screen);
}
int* AllocateMem(int* screen, int memSize) {
cudaMallocManaged(&screen, memSize * sizeof(int));
return screen;
} | #include "hip/hip_runtime.h"
#include "iostream"
__global__ void feelScreenGPU(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations) {
int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
//if (threadNum < ScreenWidth * ScreenHeight) {
int count = 0;
double r1 = 0;
double r2 = leftB + pWidth * (threadNum % ScreenWidth);
double c1 = 0;
double c2 = downB + pHeight * (threadNum / ScreenHeight);
while (count < iterations)
{
double r1Temp = r1;
r1 = r1 * r1 - c1 * c1 + r2;
c1 = 2 * r1Temp * c1 + c2;
if ((r1 * r1 + c1 * c1) > 4) {
break;
}
count++;
}
screen[threadNum] = count;
//}
}
void CalculateScreen(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations, int Blocks, int Threads) {
feelScreenGPU <<<Blocks, Threads>>> (screen, ScreenWidth, ScreenHeight, leftB, downB, pWidth, pHeight, iterations);
hipDeviceSynchronize();
}
void FreeMem(int* screen) {
hipFree(screen);
}
int* AllocateMem(int* screen, int memSize) {
hipMallocManaged(&screen, memSize * sizeof(int));
return screen;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "iostream"
__global__ void feelScreenGPU(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations) {
int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
//if (threadNum < ScreenWidth * ScreenHeight) {
int count = 0;
double r1 = 0;
double r2 = leftB + pWidth * (threadNum % ScreenWidth);
double c1 = 0;
double c2 = downB + pHeight * (threadNum / ScreenHeight);
while (count < iterations)
{
double r1Temp = r1;
r1 = r1 * r1 - c1 * c1 + r2;
c1 = 2 * r1Temp * c1 + c2;
if ((r1 * r1 + c1 * c1) > 4) {
break;
}
count++;
}
screen[threadNum] = count;
//}
}
void CalculateScreen(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations, int Blocks, int Threads) {
feelScreenGPU <<<Blocks, Threads>>> (screen, ScreenWidth, ScreenHeight, leftB, downB, pWidth, pHeight, iterations);
hipDeviceSynchronize();
}
void FreeMem(int* screen) {
hipFree(screen);
}
int* AllocateMem(int* screen, int memSize) {
hipMallocManaged(&screen, memSize * sizeof(int));
return screen;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13feelScreenGPUPiiiddddi
.globl _Z13feelScreenGPUPiiiddddi
.p2align 8
.type _Z13feelScreenGPUPiiiddddi,@function
_Z13feelScreenGPUPiiiddddi:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s4, 31
s_ashr_i32 s12, s5, 31
s_add_i32 s4, s4, s2
s_and_b32 s3, s3, 0xffff
s_xor_b32 s2, s4, s2
s_add_i32 s4, s5, s12
v_cvt_f32_u32_e32 v1, s2
s_xor_b32 s4, s4, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v2, s4
v_rcp_iflag_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_f32_e32 v3, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v4, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s3, v4
s_sub_i32 s3, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v1
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v1, v5
v_cvt_u32_f32_e32 v0, v3
v_xor_b32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s3, v0
v_add_nc_u32_e32 v2, v4, v2
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_lo_u32 v2, v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v6, v2
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, v0, s4
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v6, v3
v_subrev_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_xor_b32_e32 v7, s12, v5
v_add_nc_u32_e32 v6, 1, v0
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x30
v_xor_b32_e32 v2, v2, v5
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v0, v0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[2:3], v2
v_sub_nc_u32_e32 v0, v0, v7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[4:5], v0
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
v_fma_f64 v[2:3], v[2:3], s[10:11], s[6:7]
s_waitcnt lgkmcnt(0)
s_max_i32 s6, s3, 0
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[4:5], v[4:5], s[4:5], s[8:9]
s_mov_b32 s5, 0
s_mov_b32 s8, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_1:
v_mul_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[12:13], v[8:9], v[8:9]
s_and_not1_b32 s10, s10, exec_lo
s_and_not1_b32 s9, s9, exec_lo
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[6:7], v[6:7], v[12:13], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[2:3], v[8:9]
v_mul_f64 v[10:11], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[8:9], v[8:9], v[10:11]
v_cmp_nlt_f64_e32 vcc_lo, 4.0, v[10:11]
v_cmp_lt_f64_e64 s2, 4.0, v[10:11]
s_and_b32 s12, vcc_lo, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s10, s10, s12
s_or_b32 s9, s9, s2
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s9
v_mov_b32_e32 v0, s6
s_or_b32 s5, s2, s5
v_mov_b32_e32 v10, s8
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s7, s11, exec_lo
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s11, s10, exec_lo
s_or_b32 s7, s2, s7
s_or_b32 s4, s4, s11
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_5
.LBB0_3:
s_add_i32 s8, s8, 1
s_and_not1_b32 s10, s10, exec_lo
s_or_b32 s9, s9, exec_lo
s_cmp_ge_i32 s8, s3
s_cbranch_scc0 .LBB0_1
s_mov_b32 s11, -1
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
s_xor_b32 s2, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
v_cndmask_b32_e64 v0, 0, 1, s4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v10
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13feelScreenGPUPiiiddddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13feelScreenGPUPiiiddddi, .Lfunc_end0-_Z13feelScreenGPUPiiiddddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13feelScreenGPUPiiiddddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13feelScreenGPUPiiiddddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "iostream"
__global__ void feelScreenGPU(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations) {
int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
//if (threadNum < ScreenWidth * ScreenHeight) {
int count = 0;
double r1 = 0;
double r2 = leftB + pWidth * (threadNum % ScreenWidth);
double c1 = 0;
double c2 = downB + pHeight * (threadNum / ScreenHeight);
while (count < iterations)
{
double r1Temp = r1;
r1 = r1 * r1 - c1 * c1 + r2;
c1 = 2 * r1Temp * c1 + c2;
if ((r1 * r1 + c1 * c1) > 4) {
break;
}
count++;
}
screen[threadNum] = count;
//}
}
void CalculateScreen(int* screen, int ScreenWidth, int ScreenHeight, double leftB, double downB, double pWidth, double pHeight, int iterations, int Blocks, int Threads) {
feelScreenGPU <<<Blocks, Threads>>> (screen, ScreenWidth, ScreenHeight, leftB, downB, pWidth, pHeight, iterations);
hipDeviceSynchronize();
}
void FreeMem(int* screen) {
hipFree(screen);
}
int* AllocateMem(int* screen, int memSize) {
hipMallocManaged(&screen, memSize * sizeof(int));
return screen;
} | .text
.file "KernelFunction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__feelScreenGPUPiiiddddi # -- Begin function _Z28__device_stub__feelScreenGPUPiiiddddi
.p2align 4, 0x90
.type _Z28__device_stub__feelScreenGPUPiiiddddi,@function
_Z28__device_stub__feelScreenGPUPiiiddddi: # @_Z28__device_stub__feelScreenGPUPiiiddddi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movsd %xmm0, 96(%rsp)
movsd %xmm1, 88(%rsp)
movsd %xmm2, 80(%rsp)
movsd %xmm3, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13feelScreenGPUPiiiddddi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z28__device_stub__feelScreenGPUPiiiddddi, .Lfunc_end0-_Z28__device_stub__feelScreenGPUPiiiddddi
.cfi_endproc
# -- End function
.globl _Z15CalculateScreenPiiiddddiii # -- Begin function _Z15CalculateScreenPiiiddddiii
.p2align 4, 0x90
.type _Z15CalculateScreenPiiiddddiii,@function
_Z15CalculateScreenPiiiddddiii: # @_Z15CalculateScreenPiiiddddiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $216, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movsd %xmm3, 48(%rsp) # 8-byte Spill
movsd %xmm2, 40(%rsp) # 8-byte Spill
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl %edx, %ebp
movl %esi, %r14d
movq %rdi, %r15
movl %r8d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r9d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 136(%rsp)
movl %r14d, 20(%rsp)
movl %ebp, 16(%rsp)
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 128(%rsp)
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 120(%rsp)
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp)
movl %ebx, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 128(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13feelScreenGPUPiiiddddi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $216, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15CalculateScreenPiiiddddiii, .Lfunc_end1-_Z15CalculateScreenPiiiddddiii
.cfi_endproc
# -- End function
.globl _Z7FreeMemPi # -- Begin function _Z7FreeMemPi
.p2align 4, 0x90
.type _Z7FreeMemPi,@function
_Z7FreeMemPi: # @_Z7FreeMemPi
.cfi_startproc
# %bb.0:
jmp hipFree # TAILCALL
.Lfunc_end2:
.size _Z7FreeMemPi, .Lfunc_end2-_Z7FreeMemPi
.cfi_endproc
# -- End function
.globl _Z11AllocateMemPii # -- Begin function _Z11AllocateMemPii
.p2align 4, 0x90
.type _Z11AllocateMemPii,@function
_Z11AllocateMemPii: # @_Z11AllocateMemPii
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, (%rsp)
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11AllocateMemPii, .Lfunc_end3-_Z11AllocateMemPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13feelScreenGPUPiiiddddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13feelScreenGPUPiiiddddi,@object # @_Z13feelScreenGPUPiiiddddi
.section .rodata,"a",@progbits
.globl _Z13feelScreenGPUPiiiddddi
.p2align 3, 0x0
_Z13feelScreenGPUPiiiddddi:
.quad _Z28__device_stub__feelScreenGPUPiiiddddi
.size _Z13feelScreenGPUPiiiddddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13feelScreenGPUPiiiddddi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__feelScreenGPUPiiiddddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13feelScreenGPUPiiiddddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13feelScreenGPUPiiiddddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R3, c[0x0][0x16c] ; /* 0x00005b0000037a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0030*/ IABS R2, c[0x0][0x168] ; /* 0x00005a0000027a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ I2F.RP R8, R3 ; /* 0x0000000300087306 */
/* 0x000e620000209400 */
/*0060*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0070*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f85270 */
/*0080*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e00ff */
/*0090*/ I2F.RP R0, R2 ; /* 0x0000000200007306 */
/* 0x000eb00000209400 */
/*00a0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e700000001000 */
/*00b0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x004ea20000001000 */
/*00c0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fce0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002e2000021f000 */
/*00e0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x004fe20007ffe0ff */
/*00f0*/ IMAD R0, R9, c[0x0][0x0], R10 ; /* 0x0000000009007a24 */
/* 0x001fcc00078e020a */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0000a2000021f000 */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x002fe200000001ff */
/*0120*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0130*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0140*/ IMAD.MOV R12, RZ, RZ, -R7 ; /* 0x000000ffff0c7224 */
/* 0x008fe400078e0a07 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fc600078e00ff */
/*0160*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x004fc800078e0a05 */
/*0180*/ IMAD R9, R11, R2, RZ ; /* 0x000000020b097224 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD R11, R10, R3, RZ ; /* 0x000000030a0b7224 */
/* 0x000fe400078e02ff */
/*01a0*/ IMAD.HI.U32 R4, R5, R9, R4 ; /* 0x0000000905047227 */
/* 0x000fc800078e0004 */
/*01b0*/ IMAD.HI.U32 R6, R7, R11, R6 ; /* 0x0000000b07067227 */
/* 0x000fc800078e0006 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0008 */
/*01d0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0a7624 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.HI.U32 R4, R4, R9, RZ ; /* 0x0000000904047227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.HI.U32 R6, R6, R9, RZ ; /* 0x0000000906067227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a04 */
/*0210*/ IMAD.MOV R8, RZ, RZ, -R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0a06 */
/*0220*/ IMAD R5, R2.reuse, R4, R9.reuse ; /* 0x0000000402057224 */
/* 0x140fe400078e0209 */
/*0230*/ IMAD R4, R3.reuse, R8, R9 ; /* 0x0000000803047224 */
/* 0x040fe200078e0209 */
/*0240*/ MOV R8, c[0x0][0x188] ; /* 0x0000620000087a02 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe200078e00ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f24070 */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff097624 */
/* 0x000fe200078e00ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fd60003f04070 */
/*0290*/ @!P1 IADD3 R5, R5, -R2, RZ ; /* 0x8000000205059210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R3 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a03 */
/*02b0*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.GT.U32.AND P5, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003fa4070 */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fe40003f26070 */
/*02e0*/ LOP3.LUT R3, R0, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0000037a12 */
/* 0x000fe400078e3cff */
/*02f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fc40003f05270 */
/*0300*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f66270 */
/*0310*/ @!P5 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x000000010505d824 */
/* 0x000fe400078e0a02 */
/*0320*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fc60007ffe0ff */
/*0330*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0350*/ @!P4 LOP3.LUT R5, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff05ca12 */
/* 0x000fe400078e33ff */
/*0360*/ MOV R6, c[0x0][0x180] ; /* 0x0000600000067a02 */
/* 0x000fe20000000f00 */
/*0370*/ @!P3 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04b224 */
/* 0x000fe200078e0a04 */
/*0380*/ @!P0 LOP3.LUT R4, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff048a12 */
/* 0x000fe200078e33ff */
/*0390*/ I2F.F64 R2, R5 ; /* 0x0000000500027312 */
/* 0x000e220000201c00 */
/*03a0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fce0003f06270 */
/*03b0*/ I2F.F64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e620000201c00 */
/*03c0*/ DFMA R2, R2, R6, c[0x0][0x170] ; /* 0x00005c000202762b */
/* 0x0010880000000006 */
/*03d0*/ DFMA R10, R4, R8, c[0x0][0x178] ; /* 0x00005e00040a762b */
/* 0x0020620000000008 */
/*03e0*/ @!P0 BRA 0x520 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*03f0*/ BSSY B0, 0x520 ; /* 0x0000012000007945 */
/* 0x004fe20003800000 */
/*0400*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*0410*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x001fe2000001ff00 */
/*0420*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fca000001ff00 */
/*0430*/ DMUL R8, R4, R4 ; /* 0x0000000404087228 */
/* 0x000e0c0000000000 */
/*0440*/ DFMA R8, R6, R6, -R8 ; /* 0x000000060608722b */
/* 0x001e080000000808 */
/*0450*/ DADD R6, R6, R6 ; /* 0x0000000006067229 */
/* 0x000e880000000006 */
/*0460*/ DADD R8, R2, R8 ; /* 0x0000000002087229 */
/* 0x001e080000000008 */
/*0470*/ DFMA R4, R6, R4, R10 ; /* 0x000000040604722b */
/* 0x006fc8000000000a */
/*0480*/ DMUL R6, R8, R8 ; /* 0x0000000808067228 */
/* 0x001e0c0000000000 */
/*0490*/ DFMA R6, R4, R4, R6 ; /* 0x000000040406722b */
/* 0x001e0c0000000006 */
/*04a0*/ DSETP.GT.AND P0, PT, R6, 4, PT ; /* 0x401000000600742a */
/* 0x001e1c0003f04000 */
/*04b0*/ @P0 BRA 0x510 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*04c0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*04e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*04f0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x190], PT ; /* 0x000064000d007a0c */
/* 0x000fda0003f06270 */
/*0500*/ @!P0 BRA 0x430 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0520*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x004fca0000000f00 */
/*0530*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0540*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13feelScreenGPUPiiiddddi
.globl _Z13feelScreenGPUPiiiddddi
.p2align 8
.type _Z13feelScreenGPUPiiiddddi,@function
_Z13feelScreenGPUPiiiddddi:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s4, 31
s_ashr_i32 s12, s5, 31
s_add_i32 s4, s4, s2
s_and_b32 s3, s3, 0xffff
s_xor_b32 s2, s4, s2
s_add_i32 s4, s5, s12
v_cvt_f32_u32_e32 v1, s2
s_xor_b32 s4, s4, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v2, s4
v_rcp_iflag_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_f32_e32 v3, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v4, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s3, v4
s_sub_i32 s3, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v1
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v1, v5
v_cvt_u32_f32_e32 v0, v3
v_xor_b32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s3, v0
v_add_nc_u32_e32 v2, v4, v2
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_lo_u32 v2, v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v6, v2
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, v0, s4
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v6, v3
v_subrev_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_xor_b32_e32 v7, s12, v5
v_add_nc_u32_e32 v6, 1, v0
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x30
v_xor_b32_e32 v2, v2, v5
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v0, v0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[2:3], v2
v_sub_nc_u32_e32 v0, v0, v7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[4:5], v0
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
v_fma_f64 v[2:3], v[2:3], s[10:11], s[6:7]
s_waitcnt lgkmcnt(0)
s_max_i32 s6, s3, 0
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[4:5], v[4:5], s[4:5], s[8:9]
s_mov_b32 s5, 0
s_mov_b32 s8, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_1:
v_mul_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[12:13], v[8:9], v[8:9]
s_and_not1_b32 s10, s10, exec_lo
s_and_not1_b32 s9, s9, exec_lo
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[6:7], v[6:7], v[12:13], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[2:3], v[8:9]
v_mul_f64 v[10:11], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[8:9], v[8:9], v[10:11]
v_cmp_nlt_f64_e32 vcc_lo, 4.0, v[10:11]
v_cmp_lt_f64_e64 s2, 4.0, v[10:11]
s_and_b32 s12, vcc_lo, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s10, s10, s12
s_or_b32 s9, s9, s2
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s9
v_mov_b32_e32 v0, s6
s_or_b32 s5, s2, s5
v_mov_b32_e32 v10, s8
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s7, s11, exec_lo
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s11, s10, exec_lo
s_or_b32 s7, s2, s7
s_or_b32 s4, s4, s11
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_5
.LBB0_3:
s_add_i32 s8, s8, 1
s_and_not1_b32 s10, s10, exec_lo
s_or_b32 s9, s9, exec_lo
s_cmp_ge_i32 s8, s3
s_cbranch_scc0 .LBB0_1
s_mov_b32 s11, -1
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
s_xor_b32 s2, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
v_cndmask_b32_e64 v0, 0, 1, s4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v10
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13feelScreenGPUPiiiddddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13feelScreenGPUPiiiddddi, .Lfunc_end0-_Z13feelScreenGPUPiiiddddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13feelScreenGPUPiiiddddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13feelScreenGPUPiiiddddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001087f9_00000000-6_KernelFunction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7FreeMemPi
.type _Z7FreeMemPi, @function
_Z7FreeMemPi:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z7FreeMemPi, .-_Z7FreeMemPi
.globl _Z11AllocateMemPii
.type _Z11AllocateMemPii, @function
_Z11AllocateMemPii:
.LFB3671:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, 8(%rsp)
movslq %esi, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z11AllocateMemPii, .-_Z11AllocateMemPii
.globl _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
.type _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi, @function
_Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi:
.LFB3696:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movsd %xmm3, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13feelScreenGPUPiiiddddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi, .-_Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
.globl _Z13feelScreenGPUPiiiddddi
.type _Z13feelScreenGPUPiiiddddi, @function
_Z13feelScreenGPUPiiiddddi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z13feelScreenGPUPiiiddddi, .-_Z13feelScreenGPUPiiiddddi
.globl _Z15CalculateScreenPiiiddddiii
.type _Z15CalculateScreenPiiiddddiii, @function
_Z15CalculateScreenPiiiddddiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movsd %xmm0, (%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 24(%rsp)
movl %ecx, %r13d
movl %r9d, 52(%rsp)
movl $1, 56(%rsp)
movl %r8d, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %r13d, %ecx
movsd 24(%rsp), %xmm3
movsd 16(%rsp), %xmm2
movsd 8(%rsp), %xmm1
movsd (%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z40__device_stub__Z13feelScreenGPUPiiiddddiPiiiddddi
jmp .L16
.cfi_endproc
.LFE3669:
.size _Z15CalculateScreenPiiiddddiii, .-_Z15CalculateScreenPiiiddddiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13feelScreenGPUPiiiddddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13feelScreenGPUPiiiddddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KernelFunction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__feelScreenGPUPiiiddddi # -- Begin function _Z28__device_stub__feelScreenGPUPiiiddddi
.p2align 4, 0x90
.type _Z28__device_stub__feelScreenGPUPiiiddddi,@function
_Z28__device_stub__feelScreenGPUPiiiddddi: # @_Z28__device_stub__feelScreenGPUPiiiddddi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movsd %xmm0, 96(%rsp)
movsd %xmm1, 88(%rsp)
movsd %xmm2, 80(%rsp)
movsd %xmm3, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13feelScreenGPUPiiiddddi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z28__device_stub__feelScreenGPUPiiiddddi, .Lfunc_end0-_Z28__device_stub__feelScreenGPUPiiiddddi
.cfi_endproc
# -- End function
.globl _Z15CalculateScreenPiiiddddiii # -- Begin function _Z15CalculateScreenPiiiddddiii
.p2align 4, 0x90
.type _Z15CalculateScreenPiiiddddiii,@function
_Z15CalculateScreenPiiiddddiii: # @_Z15CalculateScreenPiiiddddiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $216, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movsd %xmm3, 48(%rsp) # 8-byte Spill
movsd %xmm2, 40(%rsp) # 8-byte Spill
movsd %xmm1, 32(%rsp) # 8-byte Spill
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl %edx, %ebp
movl %esi, %r14d
movq %rdi, %r15
movl %r8d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r9d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 136(%rsp)
movl %r14d, 20(%rsp)
movl %ebp, 16(%rsp)
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 128(%rsp)
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 120(%rsp)
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp)
movl %ebx, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 128(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13feelScreenGPUPiiiddddi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $216, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15CalculateScreenPiiiddddiii, .Lfunc_end1-_Z15CalculateScreenPiiiddddiii
.cfi_endproc
# -- End function
.globl _Z7FreeMemPi # -- Begin function _Z7FreeMemPi
.p2align 4, 0x90
.type _Z7FreeMemPi,@function
_Z7FreeMemPi: # @_Z7FreeMemPi
.cfi_startproc
# %bb.0:
jmp hipFree # TAILCALL
.Lfunc_end2:
.size _Z7FreeMemPi, .Lfunc_end2-_Z7FreeMemPi
.cfi_endproc
# -- End function
.globl _Z11AllocateMemPii # -- Begin function _Z11AllocateMemPii
.p2align 4, 0x90
.type _Z11AllocateMemPii,@function
_Z11AllocateMemPii: # @_Z11AllocateMemPii
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, (%rsp)
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11AllocateMemPii, .Lfunc_end3-_Z11AllocateMemPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13feelScreenGPUPiiiddddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13feelScreenGPUPiiiddddi,@object # @_Z13feelScreenGPUPiiiddddi
.section .rodata,"a",@progbits
.globl _Z13feelScreenGPUPiiiddddi
.p2align 3, 0x0
_Z13feelScreenGPUPiiiddddi:
.quad _Z28__device_stub__feelScreenGPUPiiiddddi
.size _Z13feelScreenGPUPiiiddddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13feelScreenGPUPiiiddddi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__feelScreenGPUPiiiddddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13feelScreenGPUPiiiddddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <curand_kernel.h>
#include <time.h>
#define X 1
#define O -1
#define BLANK 0
#define NUM_THREAD 500
#define RUNS_PER_THREAD 20
#define NUM_BLOCKS 20
#define NUM_SEQ_LOOPS 200000
//When a subBoard is won, it should be filled with that mark. (All X or all O) This is needed as a speed optimization
__device__ __host__ void printSquare(int x){
switch(x)
{
case X:
printf("X");
break;
case O:
printf("O");
break;
case BLANK:
printf("_");
break;
}
}
bool printSquareWithNumber(int x, int num){
switch(x)
{
case X:
printf("XX");
return false;
case O:
printf("OO");
return false;
case BLANK:
printf("%d", num);
if(num<=9) { printf(" ");}
return true;
}
return false;
}
void PrintBoardWithNumbers(int* board){
int x,y,j,i, num;
num = 0;
for(x = 0; x <3; x++)
{
printf("_____________\n");
for(i = 0; i < 3; i++)
{
printf("|");
for(y = 0; y < 3; y++)
{
for(j = 0; j< 3; j++)
{
if(printSquareWithNumber(board[(3*x+y)*9+(3*i+j)],num))
{
num++;
}
}
printf("|");
}
printf("\n");
}
}
printf("_____________\n");
}
void PrintBoard(int* board){
int x,y,j,i;
for(x = 0; x <3; x++)
{
printf("_____________\n");
for(i = 0; i < 3; i++)
{
printf("|");
for(y = 0; y < 3; y++)
{
for(j = 0; j< 3; j++)
{
printSquare(board[(3*x+y)*9+(3*i+j)]);
}
printf("|");
}
printf("\n");
}
}
printf("_____________\n");
}
void PrintSubBoardWithNumbers(int* subBoard){
int x,y, num;
num = 0;
for(x = 0; x < 3; x++)
{
printf("|");
for(y = 0; y < 3; y++)
{
if(printSquareWithNumber(subBoard[3*x+y],num))
{
num++;
}
}
printf("|\n");
}
}
void PrintSubBoard(int* subBoard){
int x,y;
for(x = 0; x < 3; x++)
{
printf("|");
for(y = 0; y < 3; y++)
{
printSquare(subBoard[3*x+y]);
}
printf("|\n");
}
}
__device__ __host__ int SubBoardWinner(int* subBoard){
int i, total;
//left to right wins
for(i = 0; i < 3; i++)
{
total = subBoard[3*i] + subBoard[3*i +1 ] + subBoard[3*i+2];
// printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
}
//up to down
for(i = 0; i < 3; i++)
{
total = subBoard[i] + subBoard[3+i] + subBoard[6+i];
// printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
}
//Diagonals
total = subBoard[0] + subBoard[4] + subBoard[8];
//printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
total = subBoard[2] + subBoard[4] + subBoard[6];
// printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
return 0;
}
int SubBoardWinner(double* subBoard){
int i, total;
//left to right wins
for(i = 0; i < 3; i++)
{
total = subBoard[3*i] + subBoard[3*i +1 ] + subBoard[3*i+2];
if(abs(total) == 3)
{
return (total/3);
}
}
//up to down
for(i = 0; i < 3; i++)
{
total = subBoard[i] + subBoard[ 3+i ] + subBoard[6+i];
if(abs(total) == 3)
{
return (total/3);
}
}
//Diagonals
total = subBoard[0] + subBoard[4] + subBoard[8];
if(abs(total) == 3)
{
return (total/3);
}
total = subBoard[2] + subBoard[4] + subBoard[6];
if(abs(total) == 3)
{
return (total/3);
}
return 0;
}
__device__ __host__ int BoardWinner(int* board){
int i,metaBoard[9];
for(i = 0; i < 9; i++)
{
metaBoard[i] = SubBoardWinner(board+(i*9));
}
return SubBoardWinner(metaBoard);
}
__device__ __host__ bool IsSubBoardFull(int* subBoard){
int i;
for(i = 0; i < 9; i++)
{
if(subBoard[i] == 0)
{
return false;
}
}
return true;
}
__device__ __host__ bool IsSubBoardFull(double* subBoard){
int i;
for(i = 0; i < 9; i++)
{
if(subBoard[i] != 1 || subBoard[i] != -1)
{
return false;
}
}
return true;
}
__device__ __host__ bool IsBoardFull(int* board){
for(int i = 0; i < 81; i++)
{
if(board[i] == BLANK)
{
return false;
}
}
return true;
}
__device__ __host__ int NumberOfFreeSquaresInFullBoard(int* board){
int i, count = 0;
for(i = 0; i < 81; i++)
{
if(board[i] == 0)
{
count++;
}
}
return count;
}
__device__ __host__ int NumberOfFreeSquaresInSubBoard(int* subBoard){
int i, count = 0;
for(i = 0; i < 9; i++)
{
if(subBoard[i] == 0)
{
count++;
}
}
return count;
}
__device__ __host__ int NumberOfPossibleMoves(int* board, int lastMove, bool fullBoard){
int subBoard = lastMove % 9;
if(fullBoard)
{
return NumberOfFreeSquaresInFullBoard(board);
}
else
{
return NumberOfFreeSquaresInSubBoard(board + 9*subBoard);
}
}
int DoEvalRow(int a, int b, int c){
int count = 0;
int sum = a + b + c;
if(a != 0) {count++;}
if(b != 0) {count++;}
if(c != 0) {count++;}
return sum * count;
}
double DoEvalRow(double a, double b, double c){
int count = 0;
double sum = a + b + c;
if(sum > 0)
{
if(a > 0) {count++;}
if(b > 0) {count++;}
if(c > 0) {count++;}
}
else
{
if(a < 0) {count++;}
if(b < 0) {count++;}
if(c < 0) {count++;}
}
return sum * (double)count;
}
int EvalRow(int a, int b, int c){
if( a >= 0 && b >= 0 && c >= 0)
{
return DoEvalRow(a,b,c);
}
else if( a <= 0 && b <= 0 && c <= 0)
{
return DoEvalRow(a,b,c);
}
else
{
return 0;
}
}
double EvalSubBoard(int* subBoard){
double sum = 0;
int winner = SubBoardWinner(subBoard);
switch (winner)
{
case BLANK:
if(IsSubBoardFull(subBoard))
{
return 0;
}
sum += EvalRow(subBoard[0],subBoard[1],subBoard[2]);
sum += EvalRow(subBoard[3],subBoard[4],subBoard[5]);
sum += EvalRow(subBoard[6],subBoard[7],subBoard[8]);
sum += EvalRow(subBoard[0],subBoard[3],subBoard[6]);
sum += EvalRow(subBoard[1],subBoard[4],subBoard[7]);
sum += EvalRow(subBoard[2],subBoard[5],subBoard[8]);
sum += EvalRow(subBoard[0],subBoard[4],subBoard[8]);
sum += EvalRow(subBoard[2],subBoard[4],subBoard[6]);
sum /= 21;
break;
case X:
sum = 1;
break;
case O:
sum = -1;
break;
}
return sum;
}
double EvalMetaRow(double a, double b, double c){
if( a > -1 && b > -1 && c > -1)
{
return DoEvalRow(a,b,c);
}
else if( a < 1 && b < 1 && c < 1)
{
return DoEvalRow(a,b,c);
}
else
{
return 0;
}
}
double EvalMetaBoard(double* subBoard){
double sum = 0;
int winner = SubBoardWinner(subBoard);
switch (winner)
{
case BLANK:
if(IsSubBoardFull(subBoard))
{
return 0;
}
sum += EvalMetaRow(subBoard[0],subBoard[1],subBoard[2]);
sum += EvalMetaRow(subBoard[3],subBoard[4],subBoard[5]);
sum += EvalMetaRow(subBoard[6],subBoard[7],subBoard[8]);
sum += EvalMetaRow(subBoard[0],subBoard[3],subBoard[6]);
sum += EvalMetaRow(subBoard[1],subBoard[4],subBoard[7]);
sum += EvalMetaRow(subBoard[2],subBoard[5],subBoard[8]);
sum += EvalMetaRow(subBoard[0],subBoard[4],subBoard[8]);
sum += EvalMetaRow(subBoard[2],subBoard[4],subBoard[6]);
break;
case X:
sum = 21;
break;
case O:
sum = -21;
break;
}
return sum;
}
double EvalFullBoard(int* board){
int i;
double metaBoard[9];
int winner = BoardWinner(board);
switch(winner)
{
case BLANK:
if(IsBoardFull(board))
{
return 0;
}
for(i = 0; i < 9; i++)
{
metaBoard[i] = EvalSubBoard(board + 9*i);
}
return EvalMetaBoard(metaBoard);
case X:
return (double)21;
case O:
return (double)-21;
}
return 98;
}
__device__ int EvalFullBoardKenel(int* board){
switch(BoardWinner(board))
{
case X:
return 1;
case O:
return -1;
case BLANK:
return 0;
}
return 0;
}
__device__ __host__ int PlaceMoveinSubBoard(int* board, int lastMove, int placement, int mark){
int subBoard, freeSquares, i;
subBoard = lastMove % 9;
freeSquares = 0;
for(i = 0; i < 9; i++)
{
if(board[subBoard* 9 + i] == 0)
{
if(freeSquares == placement)
{
board[subBoard* 9 + i] = mark;
freeSquares = i;
break;
}
freeSquares++;
}
}
if( SubBoardWinner(board + subBoard * 9 ) != 0 )
{
for(i = 0; i < 9; i++)
{
board[subBoard* 9 + i] = mark;
}
}
return subBoard * 9 + freeSquares;
}
__device__ __host__ int PlaceMarkinNthFree(int* board, int lastMove, int placement, int mark){
int subBoard, freeSquares, i;
freeSquares = 0;
for(i = 0; i < 81; i++)
{
if(board[i] == 0)
{
if(freeSquares == placement)
{
board[i] = mark;
freeSquares = i;
break;
}
freeSquares++;
}
}
subBoard = i / 9;
if( SubBoardWinner(board + subBoard * 9 ) != 0 )
{
for(i = 0; i < 9; i++)
{
board[subBoard* 9 + i] = mark;
}
}
return subBoard * 9 + freeSquares;
}
int playRandomMove(int* board, int lastMove, int mark){
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9) ;
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
int index = rand() % (numOfMoves);
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, index, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, index, mark);
}
}
__device__ int playRandomMove(int* board, int lastMove, int mark, curandState_t state){
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9) ;
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
int index = curand(&state) % (numOfMoves);
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, index, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, index, mark);
}
}
int MonteCarlo(int* board, int lastMove, int mark, int numRuns){
int fakeBoard[81];
int fakeLastMove;
int fakeMark;
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9) ;
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
double score [70];
for(int i = 0; i < 70; i++)
{
score[i] = 0;
}
for(int i = 0; i < numRuns; i++)
{
for(int j = 0; j < 81; j++)
{
fakeBoard[j] = board[j];
fakeLastMove = lastMove;
}
int index = i % (numOfMoves);
fakeMark = mark;
if(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard)){
if(fullBoard)
{
fakeLastMove = PlaceMarkinNthFree(fakeBoard, fakeLastMove, index, fakeMark);
}
else
{
fakeLastMove = PlaceMoveinSubBoard(fakeBoard, fakeLastMove, index, fakeMark);
}
fakeMark = fakeMark * -1;
while(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard))
{
fakeLastMove = playRandomMove(fakeBoard, fakeLastMove, fakeMark);
fakeMark = -1 * fakeMark;
}
}
score[i % numOfMoves] = EvalFullBoard(fakeBoard) + score[i % numOfMoves];
}
int winningIndex = 0;
if(mark == X)
{
double max = score[0];
for(int i = 0; i < numOfMoves; i++)
{
if(score[i] > max)
{
winningIndex = i;
max = score[i];
}
}
}
else
{
double min = score[0];
for(int i = 0; i < numOfMoves; i++)
{
if(score[i] < min)
{
winningIndex = i;
min = score[i];
}
}
}
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, winningIndex, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, winningIndex, mark);
}
}
__global__ void MonteCarloKernel(int* board, int* lastMove, int* mark, bool* fullBoard, int* numOfMoves, int* score, int Runs){
extern __shared__ int shared[];
int tId = threadIdx.x + (blockIdx.x * blockDim.x);
int thread = threadIdx.x;
curandState_t state;
curand_init((unsigned long long)clock() + tId, 0, 0, &state);
int o_board[81];
int fakeBoard[81];
int fakeLastMove;
int fakeMark;
if(thread < *numOfMoves)
{
shared[thread] = 0;
}
for(int j = 0; j < 81; j++)
{
o_board[j] = board[j];
}
__syncthreads();
//offset by tID to reduce collisions on the scores
for(int i = 0+tId; i < Runs +tId; i++)
{
//reset the board in local mem
for(int j = 0; j < 81; j++)
{
fakeBoard[j] = o_board[j];
}
int index = i % (*numOfMoves);
fakeMark = *mark;
fakeLastMove = *lastMove;
if(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard)){
if(*fullBoard)
{
fakeLastMove = PlaceMarkinNthFree(fakeBoard, fakeLastMove, index, fakeMark);
}
else
{
fakeLastMove = PlaceMoveinSubBoard(fakeBoard, fakeLastMove, index, fakeMark);
}
fakeMark = fakeMark * -1;
while(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard))
{
fakeLastMove = playRandomMove(fakeBoard, fakeLastMove, fakeMark, state);
fakeMark = -1 * fakeMark;
}
}
atomicAdd(&shared[i%(*numOfMoves)], EvalFullBoardKenel(fakeBoard));
}
__syncthreads();
if(thread < *numOfMoves)
{
atomicAdd(&score[thread], shared[thread]);
}
}
int ParMonteCarlo(int* board, int lastMove, int mark, int Runs)
{
int *d_board, *d_score ,*d_numOfMoves, *d_mark, *d_lastMove;
bool *d_fullBoard;
int score[70];
memset(score, 0, sizeof(int) * 70);
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9);
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
cudaMalloc(&d_board, sizeof(int) * 81);
cudaMalloc(&d_score, sizeof(int) * 70);
cudaMalloc(&d_mark ,sizeof(int));
cudaMalloc(&d_lastMove ,sizeof(int));
cudaMalloc(&d_numOfMoves ,sizeof(int));
cudaMalloc(&d_fullBoard ,sizeof(bool));
cudaMemset(d_score, 0, sizeof(int) * 70);
cudaMemcpy(d_board, board, sizeof(int) *81, cudaMemcpyHostToDevice);
cudaMemcpy(d_mark,&mark,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_numOfMoves,&numOfMoves,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_lastMove,&lastMove,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_fullBoard,&fullBoard,sizeof(bool),cudaMemcpyHostToDevice);
MonteCarloKernel<<<NUM_BLOCKS,NUM_THREAD, sizeof(int) * 70>>>(d_board, d_lastMove, d_mark, d_fullBoard, d_numOfMoves, d_score, Runs);
cudaDeviceSynchronize();
cudaMemcpy(score, d_score, sizeof(int)*70, cudaMemcpyDeviceToHost);
int winningIndex = 0;
if(mark == X)
{
double max = score[0];
for(int i = 0; i < 70; i++)
{
if(score[i] > max)
{
winningIndex = i;
max = score[i];
}
}
}
else
{
double min = score[0];
for(int i = 0; i < 70; i++)
{
if(score[i] < min)
{
winningIndex = i;
min = score[i];
}
}
}
cudaFree(d_board);
cudaFree(d_score);
cudaFree(d_mark);
cudaFree(d_numOfMoves);
cudaFree(d_lastMove);
cudaFree(d_fullBoard);
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, winningIndex, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, winningIndex, mark);
}
}
int main()
{
clock_t start;
clock_t diff;
clock_t end;
clock_t ParTime = 0;
clock_t SeqTime = 0;
int Xwin = 0;
int Ywin = 0;
srand(time(NULL));
for(int i = 0; i < 10; i++)
{
ParTime = 0;
SeqTime = 0;
int board[81];
memset(board, BLANK, sizeof(int)*81);
int lastMove = 0;
int mark = 1;
bool test= true;
while(BoardWinner(board) == 0 && !IsBoardFull(board) )
{
if(test)
{
printf("Monte Carlo Turn in Parallel\n");
start = clock();
lastMove = ParMonteCarlo(board, lastMove, mark, RUNS_PER_THREAD);
end = clock();
diff =end -start;
ParTime += diff;
printf("Par Time: %d\n", diff);
}
else
{
printf("Monte Carlo Turn in Sequence\n");
start = clock();
lastMove = MonteCarlo(board, lastMove, mark, NUM_SEQ_LOOPS);
end = clock();
diff = end-start;
SeqTime += diff;
printf("Seq Time: %d\n", diff);
}
mark = mark * -1;
test = !test;
PrintBoard(board);
}
if(BoardWinner(board) == X)
{
Xwin++;
}
else if (BoardWinner(board)== O)
{
Ywin++;
}
printf("Parallel Time Total %d, Seq Time Total: %d\n",ParTime, SeqTime );
printf("BoardWinner: ");
printSquare(BoardWinner(board));
printf("\n");
}
printf("X won %d times\n out of 10\n",Xwin);
printf("O won %d times\n out of 10\n",Ywin);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand_kernel.h>
#include <time.h>
#define X 1
#define O -1
#define BLANK 0
#define NUM_THREAD 500
#define RUNS_PER_THREAD 20
#define NUM_BLOCKS 20
#define NUM_SEQ_LOOPS 200000
//When a subBoard is won, it should be filled with that mark. (All X or all O) This is needed as a speed optimization
__device__ __host__ void printSquare(int x){
switch(x)
{
case X:
printf("X");
break;
case O:
printf("O");
break;
case BLANK:
printf("_");
break;
}
}
bool printSquareWithNumber(int x, int num){
switch(x)
{
case X:
printf("XX");
return false;
case O:
printf("OO");
return false;
case BLANK:
printf("%d", num);
if(num<=9) { printf(" ");}
return true;
}
return false;
}
void PrintBoardWithNumbers(int* board){
int x,y,j,i, num;
num = 0;
for(x = 0; x <3; x++)
{
printf("_____________\n");
for(i = 0; i < 3; i++)
{
printf("|");
for(y = 0; y < 3; y++)
{
for(j = 0; j< 3; j++)
{
if(printSquareWithNumber(board[(3*x+y)*9+(3*i+j)],num))
{
num++;
}
}
printf("|");
}
printf("\n");
}
}
printf("_____________\n");
}
void PrintBoard(int* board){
int x,y,j,i;
for(x = 0; x <3; x++)
{
printf("_____________\n");
for(i = 0; i < 3; i++)
{
printf("|");
for(y = 0; y < 3; y++)
{
for(j = 0; j< 3; j++)
{
printSquare(board[(3*x+y)*9+(3*i+j)]);
}
printf("|");
}
printf("\n");
}
}
printf("_____________\n");
}
void PrintSubBoardWithNumbers(int* subBoard){
int x,y, num;
num = 0;
for(x = 0; x < 3; x++)
{
printf("|");
for(y = 0; y < 3; y++)
{
if(printSquareWithNumber(subBoard[3*x+y],num))
{
num++;
}
}
printf("|\n");
}
}
void PrintSubBoard(int* subBoard){
int x,y;
for(x = 0; x < 3; x++)
{
printf("|");
for(y = 0; y < 3; y++)
{
printSquare(subBoard[3*x+y]);
}
printf("|\n");
}
}
__device__ __host__ int SubBoardWinner(int* subBoard){
int i, total;
//left to right wins
for(i = 0; i < 3; i++)
{
total = subBoard[3*i] + subBoard[3*i +1 ] + subBoard[3*i+2];
// printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
}
//up to down
for(i = 0; i < 3; i++)
{
total = subBoard[i] + subBoard[3+i] + subBoard[6+i];
// printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
}
//Diagonals
total = subBoard[0] + subBoard[4] + subBoard[8];
//printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
total = subBoard[2] + subBoard[4] + subBoard[6];
// printf("total: %d\n",total);
if(abs(total) == 3)
{
return (total/3);
}
return 0;
}
int SubBoardWinner(double* subBoard){
int i, total;
//left to right wins
for(i = 0; i < 3; i++)
{
total = subBoard[3*i] + subBoard[3*i +1 ] + subBoard[3*i+2];
if(abs(total) == 3)
{
return (total/3);
}
}
//up to down
for(i = 0; i < 3; i++)
{
total = subBoard[i] + subBoard[ 3+i ] + subBoard[6+i];
if(abs(total) == 3)
{
return (total/3);
}
}
//Diagonals
total = subBoard[0] + subBoard[4] + subBoard[8];
if(abs(total) == 3)
{
return (total/3);
}
total = subBoard[2] + subBoard[4] + subBoard[6];
if(abs(total) == 3)
{
return (total/3);
}
return 0;
}
__device__ __host__ int BoardWinner(int* board){
int i,metaBoard[9];
for(i = 0; i < 9; i++)
{
metaBoard[i] = SubBoardWinner(board+(i*9));
}
return SubBoardWinner(metaBoard);
}
__device__ __host__ bool IsSubBoardFull(int* subBoard){
int i;
for(i = 0; i < 9; i++)
{
if(subBoard[i] == 0)
{
return false;
}
}
return true;
}
__device__ __host__ bool IsSubBoardFull(double* subBoard){
int i;
for(i = 0; i < 9; i++)
{
if(subBoard[i] != 1 || subBoard[i] != -1)
{
return false;
}
}
return true;
}
__device__ __host__ bool IsBoardFull(int* board){
for(int i = 0; i < 81; i++)
{
if(board[i] == BLANK)
{
return false;
}
}
return true;
}
__device__ __host__ int NumberOfFreeSquaresInFullBoard(int* board){
int i, count = 0;
for(i = 0; i < 81; i++)
{
if(board[i] == 0)
{
count++;
}
}
return count;
}
__device__ __host__ int NumberOfFreeSquaresInSubBoard(int* subBoard){
int i, count = 0;
for(i = 0; i < 9; i++)
{
if(subBoard[i] == 0)
{
count++;
}
}
return count;
}
__device__ __host__ int NumberOfPossibleMoves(int* board, int lastMove, bool fullBoard){
int subBoard = lastMove % 9;
if(fullBoard)
{
return NumberOfFreeSquaresInFullBoard(board);
}
else
{
return NumberOfFreeSquaresInSubBoard(board + 9*subBoard);
}
}
int DoEvalRow(int a, int b, int c){
int count = 0;
int sum = a + b + c;
if(a != 0) {count++;}
if(b != 0) {count++;}
if(c != 0) {count++;}
return sum * count;
}
double DoEvalRow(double a, double b, double c){
int count = 0;
double sum = a + b + c;
if(sum > 0)
{
if(a > 0) {count++;}
if(b > 0) {count++;}
if(c > 0) {count++;}
}
else
{
if(a < 0) {count++;}
if(b < 0) {count++;}
if(c < 0) {count++;}
}
return sum * (double)count;
}
int EvalRow(int a, int b, int c){
if( a >= 0 && b >= 0 && c >= 0)
{
return DoEvalRow(a,b,c);
}
else if( a <= 0 && b <= 0 && c <= 0)
{
return DoEvalRow(a,b,c);
}
else
{
return 0;
}
}
double EvalSubBoard(int* subBoard){
double sum = 0;
int winner = SubBoardWinner(subBoard);
switch (winner)
{
case BLANK:
if(IsSubBoardFull(subBoard))
{
return 0;
}
sum += EvalRow(subBoard[0],subBoard[1],subBoard[2]);
sum += EvalRow(subBoard[3],subBoard[4],subBoard[5]);
sum += EvalRow(subBoard[6],subBoard[7],subBoard[8]);
sum += EvalRow(subBoard[0],subBoard[3],subBoard[6]);
sum += EvalRow(subBoard[1],subBoard[4],subBoard[7]);
sum += EvalRow(subBoard[2],subBoard[5],subBoard[8]);
sum += EvalRow(subBoard[0],subBoard[4],subBoard[8]);
sum += EvalRow(subBoard[2],subBoard[4],subBoard[6]);
sum /= 21;
break;
case X:
sum = 1;
break;
case O:
sum = -1;
break;
}
return sum;
}
double EvalMetaRow(double a, double b, double c){
if( a > -1 && b > -1 && c > -1)
{
return DoEvalRow(a,b,c);
}
else if( a < 1 && b < 1 && c < 1)
{
return DoEvalRow(a,b,c);
}
else
{
return 0;
}
}
double EvalMetaBoard(double* subBoard){
double sum = 0;
int winner = SubBoardWinner(subBoard);
switch (winner)
{
case BLANK:
if(IsSubBoardFull(subBoard))
{
return 0;
}
sum += EvalMetaRow(subBoard[0],subBoard[1],subBoard[2]);
sum += EvalMetaRow(subBoard[3],subBoard[4],subBoard[5]);
sum += EvalMetaRow(subBoard[6],subBoard[7],subBoard[8]);
sum += EvalMetaRow(subBoard[0],subBoard[3],subBoard[6]);
sum += EvalMetaRow(subBoard[1],subBoard[4],subBoard[7]);
sum += EvalMetaRow(subBoard[2],subBoard[5],subBoard[8]);
sum += EvalMetaRow(subBoard[0],subBoard[4],subBoard[8]);
sum += EvalMetaRow(subBoard[2],subBoard[4],subBoard[6]);
break;
case X:
sum = 21;
break;
case O:
sum = -21;
break;
}
return sum;
}
double EvalFullBoard(int* board){
int i;
double metaBoard[9];
int winner = BoardWinner(board);
switch(winner)
{
case BLANK:
if(IsBoardFull(board))
{
return 0;
}
for(i = 0; i < 9; i++)
{
metaBoard[i] = EvalSubBoard(board + 9*i);
}
return EvalMetaBoard(metaBoard);
case X:
return (double)21;
case O:
return (double)-21;
}
return 98;
}
__device__ int EvalFullBoardKenel(int* board){
switch(BoardWinner(board))
{
case X:
return 1;
case O:
return -1;
case BLANK:
return 0;
}
return 0;
}
__device__ __host__ int PlaceMoveinSubBoard(int* board, int lastMove, int placement, int mark){
int subBoard, freeSquares, i;
subBoard = lastMove % 9;
freeSquares = 0;
for(i = 0; i < 9; i++)
{
if(board[subBoard* 9 + i] == 0)
{
if(freeSquares == placement)
{
board[subBoard* 9 + i] = mark;
freeSquares = i;
break;
}
freeSquares++;
}
}
if( SubBoardWinner(board + subBoard * 9 ) != 0 )
{
for(i = 0; i < 9; i++)
{
board[subBoard* 9 + i] = mark;
}
}
return subBoard * 9 + freeSquares;
}
__device__ __host__ int PlaceMarkinNthFree(int* board, int lastMove, int placement, int mark){
int subBoard, freeSquares, i;
freeSquares = 0;
for(i = 0; i < 81; i++)
{
if(board[i] == 0)
{
if(freeSquares == placement)
{
board[i] = mark;
freeSquares = i;
break;
}
freeSquares++;
}
}
subBoard = i / 9;
if( SubBoardWinner(board + subBoard * 9 ) != 0 )
{
for(i = 0; i < 9; i++)
{
board[subBoard* 9 + i] = mark;
}
}
return subBoard * 9 + freeSquares;
}
int playRandomMove(int* board, int lastMove, int mark){
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9) ;
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
int index = rand() % (numOfMoves);
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, index, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, index, mark);
}
}
__device__ int playRandomMove(int* board, int lastMove, int mark, hiprandState_t state){
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9) ;
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
int index = hiprand(&state) % (numOfMoves);
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, index, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, index, mark);
}
}
int MonteCarlo(int* board, int lastMove, int mark, int numRuns){
int fakeBoard[81];
int fakeLastMove;
int fakeMark;
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9) ;
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
double score [70];
for(int i = 0; i < 70; i++)
{
score[i] = 0;
}
for(int i = 0; i < numRuns; i++)
{
for(int j = 0; j < 81; j++)
{
fakeBoard[j] = board[j];
fakeLastMove = lastMove;
}
int index = i % (numOfMoves);
fakeMark = mark;
if(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard)){
if(fullBoard)
{
fakeLastMove = PlaceMarkinNthFree(fakeBoard, fakeLastMove, index, fakeMark);
}
else
{
fakeLastMove = PlaceMoveinSubBoard(fakeBoard, fakeLastMove, index, fakeMark);
}
fakeMark = fakeMark * -1;
while(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard))
{
fakeLastMove = playRandomMove(fakeBoard, fakeLastMove, fakeMark);
fakeMark = -1 * fakeMark;
}
}
score[i % numOfMoves] = EvalFullBoard(fakeBoard) + score[i % numOfMoves];
}
int winningIndex = 0;
if(mark == X)
{
double max = score[0];
for(int i = 0; i < numOfMoves; i++)
{
if(score[i] > max)
{
winningIndex = i;
max = score[i];
}
}
}
else
{
double min = score[0];
for(int i = 0; i < numOfMoves; i++)
{
if(score[i] < min)
{
winningIndex = i;
min = score[i];
}
}
}
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, winningIndex, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, winningIndex, mark);
}
}
__global__ void MonteCarloKernel(int* board, int* lastMove, int* mark, bool* fullBoard, int* numOfMoves, int* score, int Runs){
extern __shared__ int shared[];
int tId = threadIdx.x + (blockIdx.x * blockDim.x);
int thread = threadIdx.x;
hiprandState_t state;
hiprand_init((unsigned long long)clock() + tId, 0, 0, &state);
int o_board[81];
int fakeBoard[81];
int fakeLastMove;
int fakeMark;
if(thread < *numOfMoves)
{
shared[thread] = 0;
}
for(int j = 0; j < 81; j++)
{
o_board[j] = board[j];
}
__syncthreads();
//offset by tID to reduce collisions on the scores
for(int i = 0+tId; i < Runs +tId; i++)
{
//reset the board in local mem
for(int j = 0; j < 81; j++)
{
fakeBoard[j] = o_board[j];
}
int index = i % (*numOfMoves);
fakeMark = *mark;
fakeLastMove = *lastMove;
if(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard)){
if(*fullBoard)
{
fakeLastMove = PlaceMarkinNthFree(fakeBoard, fakeLastMove, index, fakeMark);
}
else
{
fakeLastMove = PlaceMoveinSubBoard(fakeBoard, fakeLastMove, index, fakeMark);
}
fakeMark = fakeMark * -1;
while(BoardWinner(fakeBoard) == 0 && !IsBoardFull(fakeBoard))
{
fakeLastMove = playRandomMove(fakeBoard, fakeLastMove, fakeMark, state);
fakeMark = -1 * fakeMark;
}
}
atomicAdd(&shared[i%(*numOfMoves)], EvalFullBoardKenel(fakeBoard));
}
__syncthreads();
if(thread < *numOfMoves)
{
atomicAdd(&score[thread], shared[thread]);
}
}
int ParMonteCarlo(int* board, int lastMove, int mark, int Runs)
{
int *d_board, *d_score ,*d_numOfMoves, *d_mark, *d_lastMove;
bool *d_fullBoard;
int score[70];
memset(score, 0, sizeof(int) * 70);
int subBoard = lastMove%9;
bool fullBoard = SubBoardWinner(board+9*subBoard) != 0 || IsSubBoardFull(board+subBoard*9);
int numOfMoves = NumberOfPossibleMoves(board, lastMove, fullBoard);
hipMalloc(&d_board, sizeof(int) * 81);
hipMalloc(&d_score, sizeof(int) * 70);
hipMalloc(&d_mark ,sizeof(int));
hipMalloc(&d_lastMove ,sizeof(int));
hipMalloc(&d_numOfMoves ,sizeof(int));
hipMalloc(&d_fullBoard ,sizeof(bool));
hipMemset(d_score, 0, sizeof(int) * 70);
hipMemcpy(d_board, board, sizeof(int) *81, hipMemcpyHostToDevice);
hipMemcpy(d_mark,&mark,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_numOfMoves,&numOfMoves,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_lastMove,&lastMove,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_fullBoard,&fullBoard,sizeof(bool),hipMemcpyHostToDevice);
MonteCarloKernel<<<NUM_BLOCKS,NUM_THREAD, sizeof(int) * 70>>>(d_board, d_lastMove, d_mark, d_fullBoard, d_numOfMoves, d_score, Runs);
hipDeviceSynchronize();
hipMemcpy(score, d_score, sizeof(int)*70, hipMemcpyDeviceToHost);
int winningIndex = 0;
if(mark == X)
{
double max = score[0];
for(int i = 0; i < 70; i++)
{
if(score[i] > max)
{
winningIndex = i;
max = score[i];
}
}
}
else
{
double min = score[0];
for(int i = 0; i < 70; i++)
{
if(score[i] < min)
{
winningIndex = i;
min = score[i];
}
}
}
hipFree(d_board);
hipFree(d_score);
hipFree(d_mark);
hipFree(d_numOfMoves);
hipFree(d_lastMove);
hipFree(d_fullBoard);
if(fullBoard)
{
return PlaceMarkinNthFree(board, lastMove, winningIndex, mark);
}
else
{
return PlaceMoveinSubBoard(board, lastMove, winningIndex, mark);
}
}
int main()
{
clock_t start;
clock_t diff;
clock_t end;
clock_t ParTime = 0;
clock_t SeqTime = 0;
int Xwin = 0;
int Ywin = 0;
srand(time(NULL));
for(int i = 0; i < 10; i++)
{
ParTime = 0;
SeqTime = 0;
int board[81];
memset(board, BLANK, sizeof(int)*81);
int lastMove = 0;
int mark = 1;
bool test= true;
while(BoardWinner(board) == 0 && !IsBoardFull(board) )
{
if(test)
{
printf("Monte Carlo Turn in Parallel\n");
start = clock();
lastMove = ParMonteCarlo(board, lastMove, mark, RUNS_PER_THREAD);
end = clock();
diff =end -start;
ParTime += diff;
printf("Par Time: %d\n", diff);
}
else
{
printf("Monte Carlo Turn in Sequence\n");
start = clock();
lastMove = MonteCarlo(board, lastMove, mark, NUM_SEQ_LOOPS);
end = clock();
diff = end-start;
SeqTime += diff;
printf("Seq Time: %d\n", diff);
}
mark = mark * -1;
test = !test;
PrintBoard(board);
}
if(BoardWinner(board) == X)
{
Xwin++;
}
else if (BoardWinner(board)== O)
{
Ywin++;
}
printf("Parallel Time Total %d, Seq Time Total: %d\n",ParTime, SeqTime );
printf("BoardWinner: ");
printSquare(BoardWinner(board));
printf("\n");
}
printf("X won %d times\n out of 10\n",Xwin);
printf("O won %d times\n out of 10\n",Ywin);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel1(float *dW, float *dWcurr, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dWcurr[id] = dW[id];
}
} | code for sm_80
Function : _Z7kernel1PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel1(float *dW, float *dWcurr, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dWcurr[id] = dW[id];
}
} | .file "tmpxft_0010817f_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7kernel1PfS_iPfS_i
.type _Z29__device_stub__Z7kernel1PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel1PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7kernel1PfS_iPfS_i, .-_Z29__device_stub__Z7kernel1PfS_iPfS_i
.globl _Z7kernel1PfS_i
.type _Z7kernel1PfS_i, @function
_Z7kernel1PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kernel1PfS_i, .-_Z7kernel1PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel1(float *dW, float *dWcurr, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dWcurr[id] = dW[id];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel1(float *dW, float *dWcurr, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dWcurr[id] = dW[id];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel1(float *dW, float *dWcurr, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dWcurr[id] = dW[id];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PfS_i
.globl _Z7kernel1PfS_i
.p2align 8
.type _Z7kernel1PfS_i,@function
_Z7kernel1PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PfS_i, .Lfunc_end0-_Z7kernel1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel1(float *dW, float *dWcurr, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dWcurr[id] = dW[id];
}
} | .text
.file "kernel1.hip"
.globl _Z22__device_stub__kernel1PfS_i # -- Begin function _Z22__device_stub__kernel1PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PfS_i,@function
_Z22__device_stub__kernel1PfS_i: # @_Z22__device_stub__kernel1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PfS_i, .Lfunc_end0-_Z22__device_stub__kernel1PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1PfS_i,@object # @_Z7kernel1PfS_i
.section .rodata,"a",@progbits
.globl _Z7kernel1PfS_i
.p2align 3, 0x0
_Z7kernel1PfS_i:
.quad _Z22__device_stub__kernel1PfS_i
.size _Z7kernel1PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel1PfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel1PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PfS_i
.globl _Z7kernel1PfS_i
.p2align 8
.type _Z7kernel1PfS_i,@function
_Z7kernel1PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PfS_i, .Lfunc_end0-_Z7kernel1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010817f_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7kernel1PfS_iPfS_i
.type _Z29__device_stub__Z7kernel1PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel1PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7kernel1PfS_iPfS_i, .-_Z29__device_stub__Z7kernel1PfS_iPfS_i
.globl _Z7kernel1PfS_i
.type _Z7kernel1PfS_i, @function
_Z7kernel1PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kernel1PfS_i, .-_Z7kernel1PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel1.hip"
.globl _Z22__device_stub__kernel1PfS_i # -- Begin function _Z22__device_stub__kernel1PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PfS_i,@function
_Z22__device_stub__kernel1PfS_i: # @_Z22__device_stub__kernel1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PfS_i, .Lfunc_end0-_Z22__device_stub__kernel1PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1PfS_i,@object # @_Z7kernel1PfS_i
.section .rodata,"a",@progbits
.globl _Z7kernel1PfS_i
.p2align 3, 0x0
_Z7kernel1PfS_i:
.quad _Z22__device_stub__kernel1PfS_i
.size _Z7kernel1PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel1PfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 10000, NrankMax = 3, nt0max=81, NchanMax = 17;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void maxChannels(const double *Params, const float *dataraw, const float *data, const int *iC, int *st, int *id, int *counter){
int nt0, indx, tid, tid0, i, bid, NT, Nchan, NchanNear,j,iChan, nt0min;
double Cf, d;
float spkTh;
bool flag;
NT = (int) Params[0];
Nchan = (int) Params[1];
NchanNear = (int) Params[2];
nt0 = (int) Params[3];
nt0min = (int) Params[4];
spkTh = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
tid0 = tid + bid * blockDim.x;
while (tid0<NT-nt0-nt0min){
for (i=0; i<Nchan;i++){
iChan = iC[0 + NchanNear * i];
Cf = (double) data[tid0 + NT * iChan];
flag = true;
for(j=1; j<NchanNear; j++){
iChan = iC[j+ NchanNear * i];
if (data[tid0 + NT * iChan] > Cf){
flag = false;
break;
}
}
if (flag){
iChan = iC[NchanNear * i];
if (Cf>spkTh){
d = (double) dataraw[tid0+nt0min-1 + NT*iChan]; //
if (d > Cf-1e-6){
// this is a hit, atomicAdd and return spikes
indx = atomicAdd(&counter[0], 1);
if (indx<maxFR){
st[indx] = tid0;
id[indx] = iChan;
}
}
}
}
}
tid0 += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000c52bc_00000000-6_maxChannels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_
.type _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_, @function
_Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_, .-_Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_
.globl _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.type _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, @function
_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, .-_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int Nthreads = 1024, maxFR = 10000, NrankMax = 3, nt0max=81, NchanMax = 17;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void maxChannels(const double *Params, const float *dataraw, const float *data, const int *iC, int *st, int *id, int *counter){
int nt0, indx, tid, tid0, i, bid, NT, Nchan, NchanNear,j,iChan, nt0min;
double Cf, d;
float spkTh;
bool flag;
NT = (int) Params[0];
Nchan = (int) Params[1];
NchanNear = (int) Params[2];
nt0 = (int) Params[3];
nt0min = (int) Params[4];
spkTh = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
tid0 = tid + bid * blockDim.x;
while (tid0<NT-nt0-nt0min){
for (i=0; i<Nchan;i++){
iChan = iC[0 + NchanNear * i];
Cf = (double) data[tid0 + NT * iChan];
flag = true;
for(j=1; j<NchanNear; j++){
iChan = iC[j+ NchanNear * i];
if (data[tid0 + NT * iChan] > Cf){
flag = false;
break;
}
}
if (flag){
iChan = iC[NchanNear * i];
if (Cf>spkTh){
d = (double) dataraw[tid0+nt0min-1 + NT*iChan]; //
if (d > Cf-1e-6){
// this is a hit, atomicAdd and return spikes
indx = atomicAdd(&counter[0], 1);
if (indx<maxFR){
st[indx] = tid0;
id[indx] = iChan;
}
}
}
}
}
tid0 += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 10000, NrankMax = 3, nt0max=81, NchanMax = 17;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void maxChannels(const double *Params, const float *dataraw, const float *data, const int *iC, int *st, int *id, int *counter){
int nt0, indx, tid, tid0, i, bid, NT, Nchan, NchanNear,j,iChan, nt0min;
double Cf, d;
float spkTh;
bool flag;
NT = (int) Params[0];
Nchan = (int) Params[1];
NchanNear = (int) Params[2];
nt0 = (int) Params[3];
nt0min = (int) Params[4];
spkTh = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
tid0 = tid + bid * blockDim.x;
while (tid0<NT-nt0-nt0min){
for (i=0; i<Nchan;i++){
iChan = iC[0 + NchanNear * i];
Cf = (double) data[tid0 + NT * iChan];
flag = true;
for(j=1; j<NchanNear; j++){
iChan = iC[j+ NchanNear * i];
if (data[tid0 + NT * iChan] > Cf){
flag = false;
break;
}
}
if (flag){
iChan = iC[NchanNear * i];
if (Cf>spkTh){
d = (double) dataraw[tid0+nt0min-1 + NT*iChan]; //
if (d > Cf-1e-6){
// this is a hit, atomicAdd and return spikes
indx = atomicAdd(&counter[0], 1);
if (indx<maxFR){
st[indx] = tid0;
id[indx] = iChan;
}
}
}
}
}
tid0 += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 10000, NrankMax = 3, nt0max=81, NchanMax = 17;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void maxChannels(const double *Params, const float *dataraw, const float *data, const int *iC, int *st, int *id, int *counter){
int nt0, indx, tid, tid0, i, bid, NT, Nchan, NchanNear,j,iChan, nt0min;
double Cf, d;
float spkTh;
bool flag;
NT = (int) Params[0];
Nchan = (int) Params[1];
NchanNear = (int) Params[2];
nt0 = (int) Params[3];
nt0min = (int) Params[4];
spkTh = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
tid0 = tid + bid * blockDim.x;
while (tid0<NT-nt0-nt0min){
for (i=0; i<Nchan;i++){
iChan = iC[0 + NchanNear * i];
Cf = (double) data[tid0 + NT * iChan];
flag = true;
for(j=1; j<NchanNear; j++){
iChan = iC[j+ NchanNear * i];
if (data[tid0 + NT * iChan] > Cf){
flag = false;
break;
}
}
if (flag){
iChan = iC[NchanNear * i];
if (Cf>spkTh){
d = (double) dataraw[tid0+nt0min-1 + NT*iChan]; //
if (d > Cf-1e-6){
// this is a hit, atomicAdd and return spikes
indx = atomicAdd(&counter[0], 1);
if (indx<maxFR){
st[indx] = tid0;
id[indx] = iChan;
}
}
}
}
}
tid0 += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.globl _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.p2align 8
.type _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_,@function
_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_clause 0x1
s_load_b128 s[4:7], s[2:3], 0x18
s_load_b64 s[8:9], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[4:5]
v_cvt_i32_f64_e32 v3, s[6:7]
v_cvt_i32_f64_e32 v4, s[8:9]
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_and_b32 s16, s10, 0xffff
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v1, v3
v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
v_sub_nc_u32_e32 v0, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v0
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b128 s[8:11], s[2:3], 0x8
s_load_b64 s[2:3], s[2:3], 0x28
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -1, v3
s_mov_b32 s17, 0xbeb0c6f7
s_mov_b32 s22, 0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v2, s[10:11]
v_cvt_i32_f64_e32 v5, s[8:9]
v_cvt_f32_f64_e32 v6, s[2:3]
s_load_b32 s20, s[4:5], 0x0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b128 s[12:15], s[0:1], 0x28
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s20, s20, s16
s_mov_b32 s16, 0xa0b5ed8d
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_readfirstlane_b32 s21, v2
v_add_nc_u32_e32 v9, -1, v2
v_cmp_lt_i32_e64 s0, 0, v5
v_cmp_lt_i32_e64 s1, 1, v2
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v1, s20, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v0
s_or_b32 s22, vcc_lo, s22
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB0_19
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_add_nc_u32_e32 v10, v7, v1
s_mov_b32 s23, 0
s_mov_b32 s2, 1
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s18
s_add_i32 s23, s23, 1
s_add_i32 s2, s2, s21
v_cmp_ne_u32_e32 vcc_lo, s23, v5
s_cbranch_vccz .LBB0_2
.LBB0_6:
s_mul_i32 s18, s23, s21
s_mov_b32 s24, -1
s_ashr_i32 s19, s18, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[18:19], s[18:19], 2
s_add_u32 s18, s8, s18
s_addc_u32 s19, s9, s19
global_load_b32 v11, v8, s[18:19]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v3, v11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, v3, v1
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s1
global_load_b32 v2, v[12:13], off
s_cbranch_vccnz .LBB0_12
s_lshl_b64 s[18:19], s[2:3], 2
v_mov_b32_e32 v12, v9
s_add_u32 s18, s8, s18
s_addc_u32 s19, s9, s19
s_mov_b32 s25, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s28
s_xor_b32 s28, s26, -1
s_and_b32 s29, exec_lo, s27
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s25, s29, s25
s_and_not1_b32 s24, s24, exec_lo
s_and_b32 s28, s28, exec_lo
s_or_b32 s24, s24, s28
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execz .LBB0_11
.LBB0_9:
global_load_b32 v15, v8, s[18:19]
s_or_b32 s26, s26, exec_lo
s_or_b32 s27, s27, exec_lo
s_mov_b32 s28, exec_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[13:14], null, v15, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v13, v2
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v12, -1, v12
s_add_u32 s18, s18, 4
s_addc_u32 s19, s19, 0
s_and_not1_b32 s27, s27, exec_lo
s_and_not1_b32 s26, s26, exec_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_and_b32 s29, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s27, s27, s29
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s25
.LBB0_12:
s_and_saveexec_b32 s18, s24
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v2, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v12, v10, v3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v12, v[12:13], off
v_add_f64 v[2:3], v[2:3], s[16:17]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[12:13], v12
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e32 vcc_lo, v[2:3], v[12:13]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
s_mov_b32 s24, exec_lo
s_mov_b32 s19, exec_lo
v_mbcnt_lo_u32_b32 v2, s24, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_17
s_bcnt1_i32_b32 s24, s24
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s24
global_atomic_add_u32 v3, v8, v3, s[14:15] glc
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s19
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s19, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s19, v2
v_cmp_gt_i32_e32 vcc_lo, 0x2710, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v12, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
global_store_b32 v[12:13], v1, off
global_store_b32 v[2:3], v11, off
s_branch .LBB0_5
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 30
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, .Lfunc_end0-_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.private_segment_fixed_size: 0
.sgpr_count: 32
.sgpr_spill_count: 0
.symbol: _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 10000, NrankMax = 3, nt0max=81, NchanMax = 17;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void maxChannels(const double *Params, const float *dataraw, const float *data, const int *iC, int *st, int *id, int *counter){
int nt0, indx, tid, tid0, i, bid, NT, Nchan, NchanNear,j,iChan, nt0min;
double Cf, d;
float spkTh;
bool flag;
NT = (int) Params[0];
Nchan = (int) Params[1];
NchanNear = (int) Params[2];
nt0 = (int) Params[3];
nt0min = (int) Params[4];
spkTh = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
tid0 = tid + bid * blockDim.x;
while (tid0<NT-nt0-nt0min){
for (i=0; i<Nchan;i++){
iChan = iC[0 + NchanNear * i];
Cf = (double) data[tid0 + NT * iChan];
flag = true;
for(j=1; j<NchanNear; j++){
iChan = iC[j+ NchanNear * i];
if (data[tid0 + NT * iChan] > Cf){
flag = false;
break;
}
}
if (flag){
iChan = iC[NchanNear * i];
if (Cf>spkTh){
d = (double) dataraw[tid0+nt0min-1 + NT*iChan]; //
if (d > Cf-1e-6){
// this is a hit, atomicAdd and return spikes
indx = atomicAdd(&counter[0], 1);
if (indx<maxFR){
st[indx] = tid0;
id[indx] = iChan;
}
}
}
}
}
tid0 += blockDim.x * gridDim.x;
}
} | .text
.file "maxChannels.hip"
.globl _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_ # -- Begin function _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.p2align 4, 0x90
.type _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_,@function
_Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_: # @_Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_, .Lfunc_end0-_Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_,@object # @_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.section .rodata,"a",@progbits
.globl _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.p2align 3, 0x0
_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_:
.quad _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.size _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c52bc_00000000-6_maxChannels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_
.type _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_, @function
_Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_, .-_Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_
.globl _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.type _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, @function
_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z11maxChannelsPKdPKfS2_PKiPiS5_S5_PKdPKfS2_PKiPiS5_S5_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, .-_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxChannels.hip"
.globl _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_ # -- Begin function _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.p2align 4, 0x90
.type _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_,@function
_Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_: # @_Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_, .Lfunc_end0-_Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_,@object # @_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.section .rodata,"a",@progbits
.globl _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.p2align 3, 0x0
_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_:
.quad _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.size _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11maxChannelsPKdPKfS2_PKiPiS5_S5_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__maxChannelsPKdPKfS2_PKiPiS5_S5_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11maxChannelsPKdPKfS2_PKiPiS5_S5_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scale_bias_kernel(float *output, float *scale, int batch, int filters, int spatial, int current_size)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index >= current_size) return;
int f = (index / spatial) % filters;
output[index] *= scale[f];
} | code for sm_80
Function : _Z17scale_bias_kernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IABS R7, c[0x0][0x174] ; /* 0x00005d0000077a13 */
/* 0x000fe40000000000 */
/*0090*/ I2F.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc40007ffe0ff */
/*00c0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fc80000000000 */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R5, R8, RZ ; /* 0x0000000805057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*0120*/ I2F.RP R5, R7 ; /* 0x0000000700057306 */
/* 0x000e280000209400 */
/*0130*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fca00078e00ff */
/*0140*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0150*/ IMAD R3, R8, R3, R4 ; /* 0x0000000308037224 */
/* 0x000fe200078e0204 */
/*0160*/ LOP3.LUT R4, R0, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0000047a12 */
/* 0x000fe200078e3cff */
/*0170*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e260000001000 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe40003f44070 */
/*0190*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f26270 */
/*01a0*/ @!P2 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a08 */
/*01b0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fe40007ffe0ff */
/*01c0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R6 ; /* 0x0000000600037305 */
/* 0x000e22000021f000 */
/*01f0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fd40003f45270 */
/*0200*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0220*/ IADD3 R2, RZ, -R3, RZ ; /* 0x80000003ff027210 */
/* 0x001fc60007ffe0ff */
/*0230*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0240*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff04aa12 */
/* 0x000fe200078e33ff */
/*0250*/ IMAD R5, R2, R7, RZ ; /* 0x0000000702057224 */
/* 0x000fe400078e02ff */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0270*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fe40000000000 */
/*0280*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f46270 */
/*0290*/ IMAD.HI.U32 R2, R3, R5, R2 ; /* 0x0000000503027227 */
/* 0x000fe200078e0002 */
/*02a0*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fca0000000f00 */
/*02b0*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a02 */
/*02d0*/ IMAD R2, R7, R2, R3 ; /* 0x0000000207027224 */
/* 0x000fe200078e0203 */
/*02e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fcc0003f04070 */
/*0300*/ IMAD.WIDE R4, R0, R3, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0203 */
/*0310*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0320*/ @!P0 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102028824 */
/* 0x000fe200078e0a07 */
/*0330*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fc80003f05270 */
/*0340*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0350*/ @!P1 IADD3 R2, R2, -R7, RZ ; /* 0x8000000702029210 */
/* 0x000fca0007ffe0ff */
/*0360*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe200078e0a02 */
/*0370*/ @!P0 LOP3.LUT R2, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff028a12 */
/* 0x000fca00078e33ff */
/*0380*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0390*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */
/* 0x004fca0000400000 */
/*03b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scale_bias_kernel(float *output, float *scale, int batch, int filters, int spatial, int current_size)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index >= current_size) return;
int f = (index / spatial) % filters;
output[index] *= scale[f];
} | .file "tmpxft_000c3d4e_00000000-6_scale_bias_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii
.type _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii, @function
_Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17scale_bias_kernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii, .-_Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii
.globl _Z17scale_bias_kernelPfS_iiii
.type _Z17scale_bias_kernelPfS_iiii, @function
_Z17scale_bias_kernelPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17scale_bias_kernelPfS_iiii, .-_Z17scale_bias_kernelPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17scale_bias_kernelPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17scale_bias_kernelPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scale_bias_kernel(float *output, float *scale, int batch, int filters, int spatial, int current_size)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index >= current_size) return;
int f = (index / spatial) % filters;
output[index] *= scale[f];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scale_bias_kernel(float *output, float *scale, int batch, int filters, int spatial, int current_size)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index >= current_size) return;
int f = (index / spatial) % filters;
output[index] *= scale[f];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scale_bias_kernel(float *output, float *scale, int batch, int filters, int spatial, int current_size)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index >= current_size) return;
int f = (index / spatial) % filters;
output[index] *= scale[f];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17scale_bias_kernelPfS_iiii
.globl _Z17scale_bias_kernelPfS_iiii
.p2align 8
.type _Z17scale_bias_kernelPfS_iiii,@function
_Z17scale_bias_kernelPfS_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
v_xor_b32_e32 v3, s4, v3
s_xor_b32 s3, s3, s4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s5, v0
s_ashr_i32 s5, s2, 31
s_add_i32 s2, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s5
v_cvt_f32_u32_e32 v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cvt_u32_f32_e32 v2, v5
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_lo_u32 v4, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17scale_bias_kernelPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17scale_bias_kernelPfS_iiii, .Lfunc_end0-_Z17scale_bias_kernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17scale_bias_kernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17scale_bias_kernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scale_bias_kernel(float *output, float *scale, int batch, int filters, int spatial, int current_size)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index >= current_size) return;
int f = (index / spatial) % filters;
output[index] *= scale[f];
} | .text
.file "scale_bias_kernel.hip"
.globl _Z32__device_stub__scale_bias_kernelPfS_iiii # -- Begin function _Z32__device_stub__scale_bias_kernelPfS_iiii
.p2align 4, 0x90
.type _Z32__device_stub__scale_bias_kernelPfS_iiii,@function
_Z32__device_stub__scale_bias_kernelPfS_iiii: # @_Z32__device_stub__scale_bias_kernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17scale_bias_kernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z32__device_stub__scale_bias_kernelPfS_iiii, .Lfunc_end0-_Z32__device_stub__scale_bias_kernelPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17scale_bias_kernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17scale_bias_kernelPfS_iiii,@object # @_Z17scale_bias_kernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z17scale_bias_kernelPfS_iiii
.p2align 3, 0x0
_Z17scale_bias_kernelPfS_iiii:
.quad _Z32__device_stub__scale_bias_kernelPfS_iiii
.size _Z17scale_bias_kernelPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17scale_bias_kernelPfS_iiii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__scale_bias_kernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17scale_bias_kernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17scale_bias_kernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IABS R7, c[0x0][0x174] ; /* 0x00005d0000077a13 */
/* 0x000fe40000000000 */
/*0090*/ I2F.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc40007ffe0ff */
/*00c0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fc80000000000 */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R5, R8, RZ ; /* 0x0000000805057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*0120*/ I2F.RP R5, R7 ; /* 0x0000000700057306 */
/* 0x000e280000209400 */
/*0130*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fca00078e00ff */
/*0140*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0150*/ IMAD R3, R8, R3, R4 ; /* 0x0000000308037224 */
/* 0x000fe200078e0204 */
/*0160*/ LOP3.LUT R4, R0, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0000047a12 */
/* 0x000fe200078e3cff */
/*0170*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e260000001000 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe40003f44070 */
/*0190*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f26270 */
/*01a0*/ @!P2 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a08 */
/*01b0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fe40007ffe0ff */
/*01c0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R6 ; /* 0x0000000600037305 */
/* 0x000e22000021f000 */
/*01f0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fd40003f45270 */
/*0200*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0220*/ IADD3 R2, RZ, -R3, RZ ; /* 0x80000003ff027210 */
/* 0x001fc60007ffe0ff */
/*0230*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0240*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff04aa12 */
/* 0x000fe200078e33ff */
/*0250*/ IMAD R5, R2, R7, RZ ; /* 0x0000000702057224 */
/* 0x000fe400078e02ff */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0270*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fe40000000000 */
/*0280*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f46270 */
/*0290*/ IMAD.HI.U32 R2, R3, R5, R2 ; /* 0x0000000503027227 */
/* 0x000fe200078e0002 */
/*02a0*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fca0000000f00 */
/*02b0*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a02 */
/*02d0*/ IMAD R2, R7, R2, R3 ; /* 0x0000000207027224 */
/* 0x000fe200078e0203 */
/*02e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fcc0003f04070 */
/*0300*/ IMAD.WIDE R4, R0, R3, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0203 */
/*0310*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0320*/ @!P0 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102028824 */
/* 0x000fe200078e0a07 */
/*0330*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fc80003f05270 */
/*0340*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0350*/ @!P1 IADD3 R2, R2, -R7, RZ ; /* 0x8000000702029210 */
/* 0x000fca0007ffe0ff */
/*0360*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe200078e0a02 */
/*0370*/ @!P0 LOP3.LUT R2, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff028a12 */
/* 0x000fca00078e33ff */
/*0380*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0390*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */
/* 0x004fca0000400000 */
/*03b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17scale_bias_kernelPfS_iiii
.globl _Z17scale_bias_kernelPfS_iiii
.p2align 8
.type _Z17scale_bias_kernelPfS_iiii,@function
_Z17scale_bias_kernelPfS_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
v_xor_b32_e32 v3, s4, v3
s_xor_b32 s3, s3, s4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s5, v0
s_ashr_i32 s5, s2, 31
s_add_i32 s2, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s5
v_cvt_f32_u32_e32 v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cvt_u32_f32_e32 v2, v5
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_lo_u32 v4, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17scale_bias_kernelPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17scale_bias_kernelPfS_iiii, .Lfunc_end0-_Z17scale_bias_kernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17scale_bias_kernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17scale_bias_kernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3d4e_00000000-6_scale_bias_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii
.type _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii, @function
_Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17scale_bias_kernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii, .-_Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii
.globl _Z17scale_bias_kernelPfS_iiii
.type _Z17scale_bias_kernelPfS_iiii, @function
_Z17scale_bias_kernelPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17scale_bias_kernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17scale_bias_kernelPfS_iiii, .-_Z17scale_bias_kernelPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17scale_bias_kernelPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17scale_bias_kernelPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scale_bias_kernel.hip"
.globl _Z32__device_stub__scale_bias_kernelPfS_iiii # -- Begin function _Z32__device_stub__scale_bias_kernelPfS_iiii
.p2align 4, 0x90
.type _Z32__device_stub__scale_bias_kernelPfS_iiii,@function
_Z32__device_stub__scale_bias_kernelPfS_iiii: # @_Z32__device_stub__scale_bias_kernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17scale_bias_kernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z32__device_stub__scale_bias_kernelPfS_iiii, .Lfunc_end0-_Z32__device_stub__scale_bias_kernelPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17scale_bias_kernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17scale_bias_kernelPfS_iiii,@object # @_Z17scale_bias_kernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z17scale_bias_kernelPfS_iiii
.p2align 3, 0x0
_Z17scale_bias_kernelPfS_iiii:
.quad _Z32__device_stub__scale_bias_kernelPfS_iiii
.size _Z17scale_bias_kernelPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17scale_bias_kernelPfS_iiii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__scale_bias_kernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17scale_bias_kernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ker_gkylCartFieldAssignAll(unsigned s, unsigned nv, double val, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] = val;
} | code for sm_80
Function : _Z26ker_gkylCartFieldAssignAlljjdPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fcc0000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*0100*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e8000c101b06 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0120*/ @!P0 BRA 0xe0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ker_gkylCartFieldAssignAll(unsigned s, unsigned nv, double val, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] = val;
} | .file "tmpxft_0010831b_00000000-6_ker_gkylCartFieldAssignAll.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd
.type _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd, @function
_Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26ker_gkylCartFieldAssignAlljjdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd, .-_Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd
.globl _Z26ker_gkylCartFieldAssignAlljjdPd
.type _Z26ker_gkylCartFieldAssignAlljjdPd, @function
_Z26ker_gkylCartFieldAssignAlljjdPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26ker_gkylCartFieldAssignAlljjdPd, .-_Z26ker_gkylCartFieldAssignAlljjdPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26ker_gkylCartFieldAssignAlljjdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26ker_gkylCartFieldAssignAlljjdPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ker_gkylCartFieldAssignAll(unsigned s, unsigned nv, double val, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] = val;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ker_gkylCartFieldAssignAll(unsigned s, unsigned nv, double val, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] = val;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ker_gkylCartFieldAssignAll(unsigned s, unsigned nv, double val, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] = val;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26ker_gkylCartFieldAssignAlljjdPd
.globl _Z26ker_gkylCartFieldAssignAlljjdPd
.p2align 8
.type _Z26ker_gkylCartFieldAssignAlljjdPd,@function
_Z26ker_gkylCartFieldAssignAlljjdPd:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_add_i32 s6, s3, s2
s_mul_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s2, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
s_mul_i32 s1, s4, s7
s_mov_b32 s4, 0
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_cmp_le_u32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_or_b32 s4, vcc_lo, s4
global_store_b64 v[4:5], v[2:3], off
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26ker_gkylCartFieldAssignAlljjdPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26ker_gkylCartFieldAssignAlljjdPd, .Lfunc_end0-_Z26ker_gkylCartFieldAssignAlljjdPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26ker_gkylCartFieldAssignAlljjdPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26ker_gkylCartFieldAssignAlljjdPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ker_gkylCartFieldAssignAll(unsigned s, unsigned nv, double val, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] = val;
} | .text
.file "ker_gkylCartFieldAssignAll.hip"
.globl _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd # -- Begin function _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.p2align 4, 0x90
.type _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd,@function
_Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd: # @_Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movsd %xmm0, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26ker_gkylCartFieldAssignAlljjdPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd, .Lfunc_end0-_Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26ker_gkylCartFieldAssignAlljjdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26ker_gkylCartFieldAssignAlljjdPd,@object # @_Z26ker_gkylCartFieldAssignAlljjdPd
.section .rodata,"a",@progbits
.globl _Z26ker_gkylCartFieldAssignAlljjdPd
.p2align 3, 0x0
_Z26ker_gkylCartFieldAssignAlljjdPd:
.quad _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.size _Z26ker_gkylCartFieldAssignAlljjdPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26ker_gkylCartFieldAssignAlljjdPd"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26ker_gkylCartFieldAssignAlljjdPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26ker_gkylCartFieldAssignAlljjdPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fcc0000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*0100*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e8000c101b06 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0120*/ @!P0 BRA 0xe0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26ker_gkylCartFieldAssignAlljjdPd
.globl _Z26ker_gkylCartFieldAssignAlljjdPd
.p2align 8
.type _Z26ker_gkylCartFieldAssignAlljjdPd,@function
_Z26ker_gkylCartFieldAssignAlljjdPd:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_add_i32 s6, s3, s2
s_mul_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s2, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
s_mul_i32 s1, s4, s7
s_mov_b32 s4, 0
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_cmp_le_u32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_or_b32 s4, vcc_lo, s4
global_store_b64 v[4:5], v[2:3], off
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26ker_gkylCartFieldAssignAlljjdPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26ker_gkylCartFieldAssignAlljjdPd, .Lfunc_end0-_Z26ker_gkylCartFieldAssignAlljjdPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26ker_gkylCartFieldAssignAlljjdPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26ker_gkylCartFieldAssignAlljjdPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010831b_00000000-6_ker_gkylCartFieldAssignAll.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd
.type _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd, @function
_Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26ker_gkylCartFieldAssignAlljjdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd, .-_Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd
.globl _Z26ker_gkylCartFieldAssignAlljjdPd
.type _Z26ker_gkylCartFieldAssignAlljjdPd, @function
_Z26ker_gkylCartFieldAssignAlljjdPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26ker_gkylCartFieldAssignAlljjdPdjjdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26ker_gkylCartFieldAssignAlljjdPd, .-_Z26ker_gkylCartFieldAssignAlljjdPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26ker_gkylCartFieldAssignAlljjdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26ker_gkylCartFieldAssignAlljjdPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ker_gkylCartFieldAssignAll.hip"
.globl _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd # -- Begin function _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.p2align 4, 0x90
.type _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd,@function
_Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd: # @_Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movsd %xmm0, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26ker_gkylCartFieldAssignAlljjdPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd, .Lfunc_end0-_Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26ker_gkylCartFieldAssignAlljjdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26ker_gkylCartFieldAssignAlljjdPd,@object # @_Z26ker_gkylCartFieldAssignAlljjdPd
.section .rodata,"a",@progbits
.globl _Z26ker_gkylCartFieldAssignAlljjdPd
.p2align 3, 0x0
_Z26ker_gkylCartFieldAssignAlljjdPd:
.quad _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.size _Z26ker_gkylCartFieldAssignAlljjdPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26ker_gkylCartFieldAssignAlljjdPd"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__ker_gkylCartFieldAssignAlljjdPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26ker_gkylCartFieldAssignAlljjdPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Include files
// Parameters
#define N_ATOMS 343
#define MASS_ATOM 1.0f
#define time_step 0.01f
#define L 10.5f
#define T 0.728f
#define NUM_STEPS 10000
const int BLOCK_SIZE = 1024;
//const int L = ;
const int scheme = 1; // 0 for explicit, 1 for implicit
/*************************************************************************************************************/
/************* INITIALIZATION CODE **********/
/*************************************************************************************************************/
__global__ void forcered_simple(float * force, float * forcered){
int index = threadIdx.x + blockDim.x*blockIdx.x;
int i = 0;
int findex;
__shared__ float forcered_sh[3 * N_ATOMS];
//if (index == 0){ printf("In force reduction kernel! \n"); }
if (index < 3 * N_ATOMS){
forcered_sh[index] = 0.0f;
}
__syncthreads();
if (index < 3 * N_ATOMS){
findex = int(index / N_ATOMS)*N_ATOMS*N_ATOMS + index % N_ATOMS;
for (i = 0; i < N_ATOMS; i++){
forcered_sh[index] += force[findex + i*N_ATOMS];
}
}
__syncthreads();
if (index < 3 * N_ATOMS){
forcered[index] = forcered_sh[index];
}
/*if (index == 0){
printf("forcered [0]= %f \n", forcered[0]);
printf("forcered [2]= %f \n", forcered[2]);
printf("forcered [4]= %f \n \n", forcered[4]);
}*/
} | code for sm_80
Function : _Z15forcered_simplePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xf10 ; /* 0x00000ed000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P1, PT, R0, 0x404, PT ; /* 0x000004040000780c */
/* 0x000fda0003f24270 */
/*0070*/ @!P1 STS [R0.X4], RZ ; /* 0x000000ff00009388 */
/* 0x0001e80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ @P1 BRA 0xf00 ; /* 0x00000e6000001947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.HI R2, R0, 0x2fc44aa3, RZ ; /* 0x2fc44aa300027827 */
/* 0x001fe200078e02ff */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.0444393157958984375e-05 ; /* 0x00000157ff057435 */
/* 0x000fc800000001ff */
/*00c0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*00d0*/ LEA.HI.SX32 R3, R2, R3, 0x1a ; /* 0x0000000302037211 */
/* 0x000fe400078fd2ff */
/*00e0*/ IMAD R6, R0, R5, 0x405 ; /* 0x0000040500067424 */
/* 0x000fe200078e0205 */
/*00f0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e240000004800 */
/*0100*/ IMAD R3, R3, -0x157, R0 ; /* 0xfffffea903037824 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD R5, R3.reuse, 0x156, RZ ; /* 0x0000015603057824 */
/* 0x040fe400078e02ff */
/*0120*/ IMAD R6, R3, -0x156, R6 ; /* 0xfffffeaa03067824 */
/* 0x000fe200078e0206 */
/*0130*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD R4, R0, 0x157, -R5 ; /* 0x0000015700047824 */
/* 0x000fc600078e0a05 */
/*0150*/ IADD3 R10, R6, -0x2ae, RZ ; /* 0xfffffd52060a7810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.WIDE R12, R4, R3, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD.WIDE R10, R10, R3, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe400078e0203 */
/*0180*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000e28000c1e1900 */
/*0190*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R17, [R10.64+0x55c] ; /* 0x00055c040a117981 */
/* 0x000ee2000c1e1900 */
/*01b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 4.088878631591796875e-05 ; /* 0x000002aeff087435 */
/* 0x000fe200000001ff */
/*01c0*/ FADD R2, R2, R13 ; /* 0x0000000d02027221 */
/* 0x001fc80000000000 */
/*01d0*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x004fc80000000000 */
/*01e0*/ FADD R17, R2, R17 ; /* 0x0000001102117221 */
/* 0x008fe40000000000 */
/*01f0*/ IADD3 R12, R4, 0x55c, RZ ; /* 0x0000055c040c7810 */
/* 0x000fe20007ffe0ff */
/*0200*/ LDG.E R21, [R10.64+0xab8] ; /* 0x000ab8040a157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ IADD3 R24, R6, 0x2ae, RZ ; /* 0x000002ae06187810 */
/* 0x000fc60007ffe0ff */
/*0220*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0203 */
/*0230*/ IMAD.WIDE R24, R24, R3, c[0x0][0x160] ; /* 0x0000580018187625 */
/* 0x000fe200078e0203 */
/*0240*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x0002e8000c1e1900 */
/*0250*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x000968000c1e1900 */
/*0260*/ LDG.E R9, [R24.64+0x55c] ; /* 0x00055c0418097981 */
/* 0x000962000c1e1900 */
/*0270*/ IADD3 R26, R4, 0xab8, RZ ; /* 0x00000ab8041a7810 */
/* 0x000fc60007ffe0ff */
/*0280*/ LDG.E R7, [R24.64+0xab8] ; /* 0x000ab80418077981 */
/* 0x000964000c1e1900 */
/*0290*/ IMAD.WIDE R26, R26, R3, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fca00078e0203 */
/*02a0*/ LDG.E R2, [R26.64] ; /* 0x000000041a027981 */
/* 0x000162000c1e1900 */
/*02b0*/ IADD3 R22, R6, 0x80a, RZ ; /* 0x0000080a06167810 */
/* 0x000fca0007ffe0ff */
/*02c0*/ IMAD.WIDE R22, R22, R3, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fca00078e0203 */
/*02d0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000162000c1e1900 */
/*02e0*/ IADD3 R28, R4, 0x1014, RZ ; /* 0x00001014041c7810 */
/* 0x000fc60007ffe0ff */
/*02f0*/ LDG.E R14, [R22.64+0x55c] ; /* 0x00055c04160e7981 */
/* 0x000162000c1e1900 */
/*0300*/ IADD3 R12, R6, 0xd66, RZ ; /* 0x00000d66060c7810 */
/* 0x002fe20007ffe0ff */
/*0310*/ IMAD.WIDE R28, R28, R3.reuse, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x080fe400078e0203 */
/*0320*/ LDG.E R18, [R22.64+0xab8] ; /* 0x000ab80416127981 */
/* 0x000364000c1e1900 */
/*0330*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe400078e0203 */
/*0340*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001168000c1e1900 */
/*0360*/ LDG.E R10, [R12.64+0x55c] ; /* 0x00055c040c0a7981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R24, [R12.64+0xab8] ; /* 0x000ab8040c187981 */
/* 0x010122000c1e1900 */
/*0380*/ IADD3 R26, R4, 0x1570, RZ ; /* 0x00001570041a7810 */
/* 0x000fc40007ffe0ff */
/*0390*/ IADD3 R20, R6, 0x12c2, RZ ; /* 0x000012c206147810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ IMAD.WIDE R26, R26, R3, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fc800078e0203 */
/*03b0*/ IMAD.WIDE R22, R20, R3, c[0x0][0x160] ; /* 0x0000580014167625 */
/* 0x002fe200078e0203 */
/*03c0*/ LDG.E R5, [R26.64] ; /* 0x000000041a057981 */
/* 0x000322000c1e1900 */
/*03d0*/ IADD3 R25, R4, 0x1acc, RZ ; /* 0x00001acc04197810 */
/* 0x000fc60007ffe0ff */
/*03e0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000322000c1e1900 */
/*03f0*/ IADD3 R13, R6, 0x181e, RZ ; /* 0x0000181e060d7810 */
/* 0x001fc60007ffe0ff */
/*0400*/ LDG.E R29, [R22.64+0xab8] ; /* 0x000ab804161d7981 */
/* 0x000122000c1e1900 */
/*0410*/ FADD R17, R21, R17 ; /* 0x0000001115117221 */
/* 0x004fc60000000000 */
/*0420*/ LDG.E R21, [R22.64+0x55c] ; /* 0x00055c0416157981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FADD R12, R17, R16 ; /* 0x00000010110c7221 */
/* 0x008fe40000000000 */
/*0440*/ IMAD.WIDE R16, R25, R3, c[0x0][0x160] ; /* 0x0000580019107625 */
/* 0x000fc800078e0203 */
/*0450*/ FADD R19, R12, R19 ; /* 0x000000130c137221 */
/* 0x020fe40000000000 */
/*0460*/ IMAD.WIDE R12, R13, R3, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe200078e0203 */
/*0470*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000766000c1e1900 */
/*0480*/ FADD R9, R19, R9 ; /* 0x0000000913097221 */
/* 0x000fe20000000000 */
/*0490*/ IADD3 R19, R4, 0x2028, RZ ; /* 0x0000202804137810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ LDG.E R27, [R12.64+0x55c] ; /* 0x00055c040c1b7981 */
/* 0x002362000c1e1900 */
/*04b0*/ IADD3 R22, R6, 0x1d7a, RZ ; /* 0x00001d7a06167810 */
/* 0x001fc60007ffe0ff */
/*04c0*/ LDG.E R26, [R12.64+0xab8] ; /* 0x000ab8040c1a7981 */
/* 0x000368000c1e1900 */
/*04d0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x0082e2000c1e1900 */
/*04e0*/ FADD R7, R9, R7 ; /* 0x0000000709077221 */
/* 0x000fe40000000000 */
/*04f0*/ IMAD.WIDE R22, R22, R3, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fca00078e0203 */
/*0500*/ LDG.E R25, [R22.64+0xab8] ; /* 0x000ab80416197981 */
/* 0x0000e2000c1e1900 */
/*0510*/ IMAD.WIDE R12, R19, R3, c[0x0][0x160] ; /* 0x00005800130c7625 */
/* 0x002fca00078e0203 */
/*0520*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0002e2000c1e1900 */
/*0530*/ FADD R19, R7, R2 ; /* 0x0000000207137221 */
/* 0x000fc60000000000 */
/*0540*/ LDG.E R2, [R22.64] ; /* 0x0000000416027981 */
/* 0x0000e8000c1e1900 */
/*0550*/ LDG.E R7, [R22.64+0x55c] ; /* 0x00055c0416077981 */
/* 0x0000e2000c1e1900 */
/*0560*/ IADD3 R12, R4, 0x2584, RZ ; /* 0x00002584040c7810 */
/* 0x002fe20007ffe0ff */
/*0570*/ FADD R15, R19, R15 ; /* 0x0000000f130f7221 */
/* 0x000fc80000000000 */
/*0580*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e0203 */
/*0590*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x0002e4000c1e1900 */
/*05a0*/ IADD3 R12, R6, 0x22d6, RZ ; /* 0x000022d6060c7810 */
/* 0x002fe20007ffe0ff */
/*05b0*/ FADD R13, R15, R14 ; /* 0x0000000e0f0d7221 */
/* 0x000fc80000000000 */
/*05c0*/ IMAD.WIDE R14, R12, R3, c[0x0][0x160] ; /* 0x000058000c0e7625 */
/* 0x000fc800078e0203 */
/*05d0*/ FADD R13, R13, R18 ; /* 0x000000120d0d7221 */
/* 0x000fe20000000000 */
/*05e0*/ IADD3 R23, R4, 0x2ae0, RZ ; /* 0x00002ae004177810 */
/* 0x001fe20007ffe0ff */
/*05f0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x0000e4000c1e1900 */
/*0600*/ FADD R12, R13, R28 ; /* 0x0000001c0d0c7221 */
/* 0x000fe40000000000 */
/*0610*/ LDG.E R28, [R14.64+0x55c] ; /* 0x00055c040e1c7981 */
/* 0x0000e4000c1e1900 */
/*0620*/ FADD R11, R12, R11 ; /* 0x0000000b0c0b7221 */
/* 0x000fe40000000000 */
/*0630*/ IMAD.WIDE R12, R23, R3, c[0x0][0x160] ; /* 0x00005800170c7625 */
/* 0x000fe200078e0203 */
/*0640*/ LDG.E R22, [R14.64+0xab8] ; /* 0x000ab8040e167981 */
/* 0x0000e8000c1e1900 */
/*0650*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x0002e4000c1e1900 */
/*0660*/ IADD3 R12, R6, 0x2832, RZ ; /* 0x00002832060c7810 */
/* 0x002fe20007ffe0ff */
/*0670*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x000fc80000000000 */
/*0680*/ IMAD.WIDE R10, R12, R3, c[0x0][0x160] ; /* 0x000058000c0a7625 */
/* 0x000fc800078e0203 */
/*0690*/ FADD R12, R13, R24 ; /* 0x000000180d0c7221 */
/* 0x010fe40000000000 */
/*06a0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000324000c1e1900 */
/*06b0*/ FADD R5, R12, R5 ; /* 0x000000050c057221 */
/* 0x000fc80000000000 */
/*06c0*/ FADD R20, R5, R20 ; /* 0x0000001405147221 */
/* 0x000fe20000000000 */
/*06d0*/ IADD3 R14, R4, 0x303c, RZ ; /* 0x0000303c040e7810 */
/* 0x001fe20007ffe0ff */
/*06e0*/ LDG.E R5, [R10.64+0x55c] ; /* 0x00055c040a057981 */
/* 0x000328000c1e1900 */
/*06f0*/ IMAD.WIDE R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0203 */
/*0700*/ FADD R20, R20, R21 ; /* 0x0000001514147221 */
/* 0x004fe40000000000 */
/*0710*/ LDG.E R21, [R10.64+0xab8] ; /* 0x000ab8040a157981 */
/* 0x0002a4000c1e1900 */
/*0720*/ FADD R20, R20, R29 ; /* 0x0000001d14147221 */
/* 0x000fc80000000000 */
/*0730*/ FADD R17, R20, R17 ; /* 0x0000001114117221 */
/* 0x020fe20000000000 */
/*0740*/ IADD3 R20, R6, 0x2d8e, RZ ; /* 0x00002d8e06147810 */
/* 0x000fc60007ffe0ff */
/*0750*/ FADD R12, R17, R16 ; /* 0x00000010110c7221 */
/* 0x008fe40000000000 */
/*0760*/ IMAD.WIDE R16, R20, R3, c[0x0][0x160] ; /* 0x0000580014107625 */
/* 0x000fe400078e0203 */
/*0770*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000e4000c1e1900 */
/*0780*/ FADD R27, R12, R27 ; /* 0x0000001b0c1b7221 */
/* 0x000fe40000000000 */
/*0790*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x000ae4000c1e1900 */
/*07a0*/ FADD R26, R27, R26 ; /* 0x0000001a1b1a7221 */
/* 0x000fe20000000000 */
/*07b0*/ IADD3 R27, R4, 0x3598, RZ ; /* 0x00003598041b7810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ LDG.E R12, [R16.64+0x55c] ; /* 0x00055c04100c7981 */
/* 0x000ae2000c1e1900 */
/*07d0*/ IADD3 R11, R6, 0x32ea, RZ ; /* 0x000032ea060b7810 */
/* 0x002fe20007ffe0ff */
/*07e0*/ FADD R9, R26, R9 ; /* 0x000000091a097221 */
/* 0x000fc40000000000 */
/*07f0*/ LDG.E R10, [R16.64+0xab8] ; /* 0x000ab804100a7981 */
/* 0x000ae2000c1e1900 */
/*0800*/ IMAD.WIDE R26, R27, R3, c[0x0][0x160] ; /* 0x000058001b1a7625 */
/* 0x000fc800078e0203 */
/*0810*/ FADD R9, R9, R2 ; /* 0x0000000209097221 */
/* 0x000fe40000000000 */
/*0820*/ IMAD.WIDE R14, R11, R3, c[0x0][0x160] ; /* 0x000058000b0e7625 */
/* 0x001fe200078e0203 */
/*0830*/ LDG.E R2, [R26.64] ; /* 0x000000041a027981 */
/* 0x0000e6000c1e1900 */
/*0840*/ FADD R29, R9, R7 ; /* 0x00000007091d7221 */
/* 0x000fe20000000000 */
/*0850*/ LDG.E R11, [R14.64+0x55c] ; /* 0x00055c040e0b7981 */
/* 0x0002e8000c1e1900 */
/*0860*/ LDG.E R7, [R14.64] ; /* 0x000000040e077981 */
/* 0x0002e2000c1e1900 */
/*0870*/ IADD3 R26, R4, 0x3af4, RZ ; /* 0x00003af4041a7810 */
/* 0x001fc60007ffe0ff */
/*0880*/ LDG.E R9, [R14.64+0xab8] ; /* 0x000ab8040e097981 */
/* 0x0002e2000c1e1900 */
/*0890*/ IADD3 R16, R6, 0x3846, RZ ; /* 0x0000384606107810 */
/* 0x020fe20007ffe0ff */
/*08a0*/ FADD R29, R29, R25 ; /* 0x000000191d1d7221 */
/* 0x000fe40000000000 */
/*08b0*/ IMAD.WIDE R14, R26, R3, c[0x0][0x160] ; /* 0x000058001a0e7625 */
/* 0x002fca00078e0203 */
/*08c0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000162000c1e1900 */
/*08d0*/ IMAD.WIDE R16, R16, R3, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fca00078e0203 */
/*08e0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000362000c1e1900 */
/*08f0*/ FADD R19, R29, R19 ; /* 0x000000131d137221 */
/* 0x000fc60000000000 */
/*0900*/ LDG.E R27, [R16.64+0x55c] ; /* 0x00055c04101b7981 */
/* 0x000362000c1e1900 */
/*0910*/ IADD3 R14, R4, 0x4050, RZ ; /* 0x00004050040e7810 */
/* 0x001fe20007ffe0ff */
/*0920*/ FADD R15, R19, R18 ; /* 0x00000012130f7221 */
/* 0x000fe40000000000 */
/*0930*/ LDG.E R29, [R16.64+0xab8] ; /* 0x000ab804101d7981 */
/* 0x000364000c1e1900 */
/*0940*/ IMAD.WIDE R18, R14, R3, c[0x0][0x160] ; /* 0x000058000e127625 */
/* 0x000fe200078e0203 */
/*0950*/ IADD3 R14, R6, 0x3da2, RZ ; /* 0x00003da2060e7810 */
/* 0x000fc60007ffe0ff */
/*0960*/ FADD R28, R15, R28 ; /* 0x0000001c0f1c7221 */
/* 0x000fe40000000000 */
/*0970*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000162000c1e1900 */
/*0980*/ IMAD.WIDE R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0203 */
/*0990*/ FADD R28, R28, R22 ; /* 0x000000161c1c7221 */
/* 0x000fe40000000000 */
/*09a0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000164000c1e1900 */
/*09b0*/ FADD R17, R28, R23 ; /* 0x000000171c117221 */
/* 0x002fe40000000000 */
/*09c0*/ LDG.E R23, [R14.64+0x55c] ; /* 0x00055c040e177981 */
/* 0x000162000c1e1900 */
/*09d0*/ IADD3 R16, R4, 0x45ac, RZ ; /* 0x000045ac04107810 */
/* 0x000fc60007ffe0ff */
/*09e0*/ LDG.E R28, [R14.64+0xab8] ; /* 0x000ab8040e1c7981 */
/* 0x000162000c1e1900 */
/*09f0*/ FADD R24, R17, R24 ; /* 0x0000001811187221 */
/* 0x010fe40000000000 */
/*0a00*/ IMAD.WIDE R16, R16, R3, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fcc00078e0203 */
/*0a10*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0a20*/ FADD R24, R24, R5 ; /* 0x0000000518187221 */
/* 0x000fe20000000000 */
/*0a30*/ IADD3 R14, R4, 0x4b08, RZ ; /* 0x00004b08040e7810 */
/* 0x001fe40007ffe0ff */
/*0a40*/ IADD3 R19, R6, 0x4db6, RZ ; /* 0x00004db606137810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R21, R24, R21 ; /* 0x0000001518157221 */
/* 0x004fe20000000000 */
/*0a60*/ IADD3 R24, R6, 0x485a, RZ ; /* 0x0000485a06187810 */
/* 0x000fc60007ffe0ff */
/*0a70*/ FADD R20, R21, R20 ; /* 0x0000001415147221 */
/* 0x008fc80000000000 */
/*0a80*/ FADD R13, R20, R13 ; /* 0x0000000d140d7221 */
/* 0x000fe20000000000 */
/*0a90*/ IADD3 R20, R6, 0x42fe, RZ ; /* 0x000042fe06147810 */
/* 0x000fc60007ffe0ff */
/*0aa0*/ FADD R5, R13, R12 ; /* 0x0000000c0d057221 */
/* 0x000fe40000000000 */
/*0ab0*/ IMAD.WIDE R12, R20, R3, c[0x0][0x160] ; /* 0x00005800140c7625 */
/* 0x000fc800078e0203 */
/*0ac0*/ FADD R15, R5, R10 ; /* 0x0000000a050f7221 */
/* 0x000fe40000000000 */
/*0ad0*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x0000a4000c1e1900 */
/*0ae0*/ FADD R10, R15, R2 ; /* 0x000000020f0a7221 */
/* 0x000fe40000000000 */
/*0af0*/ LDG.E R2, [R12.64+0x55c] ; /* 0x00055c040c027981 */
/* 0x0000e2000c1e1900 */
/*0b00*/ IMAD.WIDE R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0203 */
/*0b10*/ FADD R10, R10, R7 ; /* 0x000000070a0a7221 */
/* 0x000fe20000000000 */
/*0b20*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x0022e8000c1e1900 */
/*0b30*/ LDG.E R7, [R12.64+0xab8] ; /* 0x000ab8040c077981 */
/* 0x0000e2000c1e1900 */
/*0b40*/ FADD R20, R10, R11 ; /* 0x0000000b0a147221 */
/* 0x000fe40000000000 */
/*0b50*/ IMAD.WIDE R10, R24, R3, c[0x0][0x160] ; /* 0x00005800180a7625 */
/* 0x000fc800078e0203 */
/*0b60*/ FADD R20, R20, R9 ; /* 0x0000000914147221 */
/* 0x000fe20000000000 */
/*0b70*/ IADD3 R24, R4, 0x5064, RZ ; /* 0x0000506404187810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ae2000c1e1900 */
/*0b90*/ IMAD.WIDE R14, R19, R3, c[0x0][0x160] ; /* 0x00005800130e7625 */
/* 0x002fc600078e0203 */
/*0ba0*/ LDG.E R21, [R10.64+0xab8] ; /* 0x000ab8040a157981 */
/* 0x0002e2000c1e1900 */
/*0bb0*/ FADD R25, R20, R25 ; /* 0x0000001914197221 */
/* 0x020fc60000000000 */
/*0bc0*/ LDG.E R20, [R10.64+0x55c] ; /* 0x00055c040a147981 */
/* 0x000362000c1e1900 */
/*0bd0*/ IMAD.WIDE R12, R24, R3, c[0x0][0x160] ; /* 0x00005800180c7625 */
/* 0x001fc800078e0203 */
/*0be0*/ FADD R26, R25, R26 ; /* 0x0000001a191a7221 */
/* 0x000fe20000000000 */
/*0bf0*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x000166000c1e1900 */
/*0c00*/ FADD R26, R26, R27 ; /* 0x0000001b1a1a7221 */
/* 0x000fe20000000000 */
/*0c10*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000362000c1e1900 */
/*0c20*/ IADD3 R19, R4, 0x55c0, RZ ; /* 0x000055c004137810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ FADD R29, R26, R29 ; /* 0x0000001d1a1d7221 */
/* 0x000fe20000000000 */
/*0c40*/ LDG.E R27, [R14.64+0xab8] ; /* 0x000ab8040e1b7981 */
/* 0x000362000c1e1900 */
/*0c50*/ IADD3 R12, R6, 0x5312, RZ ; /* 0x00005312060c7810 */
/* 0x001fc60007ffe0ff */
/*0c60*/ LDG.E R26, [R14.64+0x55c] ; /* 0x00055c040e1a7981 */
/* 0x000162000c1e1900 */
/*0c70*/ IMAD.WIDE R10, R19, R3, c[0x0][0x160] ; /* 0x00005800130a7625 */
/* 0x002fc800078e0203 */
/*0c80*/ FADD R13, R29, R18 ; /* 0x000000121d0d7221 */
/* 0x000fe40000000000 */
/*0c90*/ IMAD.WIDE R18, R12, R3.reuse, c[0x0][0x160] ; /* 0x000058000c127625 */
/* 0x080fe200078e0203 */
/*0ca0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001166000c1e1900 */
/*0cb0*/ FADD R22, R13, R22 ; /* 0x000000160d167221 */
/* 0x000fe20000000000 */
/*0cc0*/ IADD3 R4, R4, 0x5b1c, RZ ; /* 0x00005b1c04047810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000364000c1e1900 */
/*0ce0*/ FADD R23, R22, R23 ; /* 0x0000001716177221 */
/* 0x000fe20000000000 */
/*0cf0*/ IADD3 R22, R6, 0x586e, RZ ; /* 0x0000586e06167810 */
/* 0x000fe20007ffe0ff */
/*0d00*/ LDG.E R29, [R18.64+0x55c] ; /* 0x00055c04121d7981 */
/* 0x000362000c1e1900 */
/*0d10*/ IMAD.WIDE R12, R4, R3, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x000fc800078e0203 */
/*0d20*/ IMAD.WIDE R10, R22, R3, c[0x0][0x160] ; /* 0x00005800160a7625 */
/* 0x001fe400078e0203 */
/*0d30*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f68000c1e1900 */
/*0d40*/ LDG.E R18, [R18.64+0xab8] ; /* 0x000ab80412127981 */
/* 0x002162000c1e1900 */
/*0d50*/ FADD R23, R23, R28 ; /* 0x0000001c17177221 */
/* 0x000fc80000000000 */
/*0d60*/ FADD R22, R23, R16 ; /* 0x0000001017167221 */
/* 0x010fe40000000000 */
/*0d70*/ LDG.E R16, [R10.64+0x55c] ; /* 0x00055c040a107981 */
/* 0x000f28000c1e1900 */
/*0d80*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x001f22000c1e1900 */
/*0d90*/ IADD3 R8, R8, 0x5b1c, RZ ; /* 0x00005b1c08087810 */
/* 0x000fc80007ffe0ff */
/*0da0*/ ISETP.NE.AND P0, PT, R8, 0x1ca3a, PT ; /* 0x0001ca3a0800780c */
/* 0x000fe40003f05270 */
/*0db0*/ IADD3 R6, R6, 0x5b1c, RZ ; /* 0x00005b1c06067810 */
/* 0x000fe20007ffe0ff */
/*0dc0*/ FADD R5, R22, R5 ; /* 0x0000000516057221 */
/* 0x004fc80000000000 */
/*0dd0*/ FADD R2, R5, R2 ; /* 0x0000000205027221 */
/* 0x008fc80000000000 */
/*0de0*/ FADD R2, R2, R7 ; /* 0x0000000702027221 */
/* 0x000fc80000000000 */
/*0df0*/ FADD R2, R2, R17 ; /* 0x0000001102027221 */
/* 0x000fc80000000000 */
/*0e00*/ FADD R9, R2, R9 ; /* 0x0000000902097221 */
/* 0x000fc80000000000 */
/*0e10*/ FADD R20, R9, R20 ; /* 0x0000001409147221 */
/* 0x020fc80000000000 */
/*0e20*/ FADD R21, R20, R21 ; /* 0x0000001514157221 */
/* 0x000fc80000000000 */
/*0e30*/ FADD R24, R21, R24 ; /* 0x0000001815187221 */
/* 0x000fc80000000000 */
/*0e40*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x000fc80000000000 */
/*0e50*/ FADD R26, R25, R26 ; /* 0x0000001a191a7221 */
/* 0x000fc80000000000 */
/*0e60*/ FADD R26, R26, R27 ; /* 0x0000001b1a1a7221 */
/* 0x000fc80000000000 */
/*0e70*/ FADD R15, R26, R15 ; /* 0x0000000f1a0f7221 */
/* 0x000fc80000000000 */
/*0e80*/ FADD R14, R15, R14 ; /* 0x0000000e0f0e7221 */
/* 0x000fc80000000000 */
/*0e90*/ FADD R5, R14, R29 ; /* 0x0000001d0e057221 */
/* 0x000fc80000000000 */
/*0ea0*/ FADD R5, R18, R5 ; /* 0x0000000512057221 */
/* 0x000fc80000000000 */
/*0eb0*/ FADD R12, R5, R12 ; /* 0x0000000c050c7221 */
/* 0x000fc80000000000 */
/*0ec0*/ FADD R19, R12, R19 ; /* 0x000000130c137221 */
/* 0x010fc80000000000 */
/*0ed0*/ FADD R17, R19, R16 ; /* 0x0000001013117221 */
/* 0x000fe20000000000 */
/*0ee0*/ @P0 BRA 0x1f0 ; /* 0xfffff30000000947 */
/* 0x000fea000383ffff */
/*0ef0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0001e40000004800 */
/*0f00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0f10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0f20*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0f30*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e220000004800 */
/*0f40*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0f50*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0f60*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0f70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f80*/ BRA 0xf80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Include files
// Parameters
#define N_ATOMS 343
#define MASS_ATOM 1.0f
#define time_step 0.01f
#define L 10.5f
#define T 0.728f
#define NUM_STEPS 10000
const int BLOCK_SIZE = 1024;
//const int L = ;
const int scheme = 1; // 0 for explicit, 1 for implicit
/*************************************************************************************************************/
/************* INITIALIZATION CODE **********/
/*************************************************************************************************************/
__global__ void forcered_simple(float * force, float * forcered){
int index = threadIdx.x + blockDim.x*blockIdx.x;
int i = 0;
int findex;
__shared__ float forcered_sh[3 * N_ATOMS];
//if (index == 0){ printf("In force reduction kernel! \n"); }
if (index < 3 * N_ATOMS){
forcered_sh[index] = 0.0f;
}
__syncthreads();
if (index < 3 * N_ATOMS){
findex = int(index / N_ATOMS)*N_ATOMS*N_ATOMS + index % N_ATOMS;
for (i = 0; i < N_ATOMS; i++){
forcered_sh[index] += force[findex + i*N_ATOMS];
}
}
__syncthreads();
if (index < 3 * N_ATOMS){
forcered[index] = forcered_sh[index];
}
/*if (index == 0){
printf("forcered [0]= %f \n", forcered[0]);
printf("forcered [2]= %f \n", forcered[2]);
printf("forcered [4]= %f \n \n", forcered[4]);
}*/
} | .file "tmpxft_000282fc_00000000-6_forcered_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15forcered_simplePfS_PfS_
.type _Z37__device_stub__Z15forcered_simplePfS_PfS_, @function
_Z37__device_stub__Z15forcered_simplePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15forcered_simplePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z15forcered_simplePfS_PfS_, .-_Z37__device_stub__Z15forcered_simplePfS_PfS_
.globl _Z15forcered_simplePfS_
.type _Z15forcered_simplePfS_, @function
_Z15forcered_simplePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15forcered_simplePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15forcered_simplePfS_, .-_Z15forcered_simplePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15forcered_simplePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15forcered_simplePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Include files
// Parameters
#define N_ATOMS 343
#define MASS_ATOM 1.0f
#define time_step 0.01f
#define L 10.5f
#define T 0.728f
#define NUM_STEPS 10000
const int BLOCK_SIZE = 1024;
//const int L = ;
const int scheme = 1; // 0 for explicit, 1 for implicit
/*************************************************************************************************************/
/************* INITIALIZATION CODE **********/
/*************************************************************************************************************/
__global__ void forcered_simple(float * force, float * forcered){
int index = threadIdx.x + blockDim.x*blockIdx.x;
int i = 0;
int findex;
__shared__ float forcered_sh[3 * N_ATOMS];
//if (index == 0){ printf("In force reduction kernel! \n"); }
if (index < 3 * N_ATOMS){
forcered_sh[index] = 0.0f;
}
__syncthreads();
if (index < 3 * N_ATOMS){
findex = int(index / N_ATOMS)*N_ATOMS*N_ATOMS + index % N_ATOMS;
for (i = 0; i < N_ATOMS; i++){
forcered_sh[index] += force[findex + i*N_ATOMS];
}
}
__syncthreads();
if (index < 3 * N_ATOMS){
forcered[index] = forcered_sh[index];
}
/*if (index == 0){
printf("forcered [0]= %f \n", forcered[0]);
printf("forcered [2]= %f \n", forcered[2]);
printf("forcered [4]= %f \n \n", forcered[4]);
}*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Include files
// Parameters
#define N_ATOMS 343
#define MASS_ATOM 1.0f
#define time_step 0.01f
#define L 10.5f
#define T 0.728f
#define NUM_STEPS 10000
const int BLOCK_SIZE = 1024;
//const int L = ;
const int scheme = 1; // 0 for explicit, 1 for implicit
/*************************************************************************************************************/
/************* INITIALIZATION CODE **********/
/*************************************************************************************************************/
__global__ void forcered_simple(float * force, float * forcered){
int index = threadIdx.x + blockDim.x*blockIdx.x;
int i = 0;
int findex;
__shared__ float forcered_sh[3 * N_ATOMS];
//if (index == 0){ printf("In force reduction kernel! \n"); }
if (index < 3 * N_ATOMS){
forcered_sh[index] = 0.0f;
}
__syncthreads();
if (index < 3 * N_ATOMS){
findex = int(index / N_ATOMS)*N_ATOMS*N_ATOMS + index % N_ATOMS;
for (i = 0; i < N_ATOMS; i++){
forcered_sh[index] += force[findex + i*N_ATOMS];
}
}
__syncthreads();
if (index < 3 * N_ATOMS){
forcered[index] = forcered_sh[index];
}
/*if (index == 0){
printf("forcered [0]= %f \n", forcered[0]);
printf("forcered [2]= %f \n", forcered[2]);
printf("forcered [4]= %f \n \n", forcered[4]);
}*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Include files
// Parameters
#define N_ATOMS 343
#define MASS_ATOM 1.0f
#define time_step 0.01f
#define L 10.5f
#define T 0.728f
#define NUM_STEPS 10000
const int BLOCK_SIZE = 1024;
//const int L = ;
const int scheme = 1; // 0 for explicit, 1 for implicit
/*************************************************************************************************************/
/************* INITIALIZATION CODE **********/
/*************************************************************************************************************/
__global__ void forcered_simple(float * force, float * forcered){
int index = threadIdx.x + blockDim.x*blockIdx.x;
int i = 0;
int findex;
__shared__ float forcered_sh[3 * N_ATOMS];
//if (index == 0){ printf("In force reduction kernel! \n"); }
if (index < 3 * N_ATOMS){
forcered_sh[index] = 0.0f;
}
__syncthreads();
if (index < 3 * N_ATOMS){
findex = int(index / N_ATOMS)*N_ATOMS*N_ATOMS + index % N_ATOMS;
for (i = 0; i < N_ATOMS; i++){
forcered_sh[index] += force[findex + i*N_ATOMS];
}
}
__syncthreads();
if (index < 3 * N_ATOMS){
forcered[index] = forcered_sh[index];
}
/*if (index == 0){
printf("forcered [0]= %f \n", forcered[0]);
printf("forcered [2]= %f \n", forcered[2]);
printf("forcered [4]= %f \n \n", forcered[4]);
}*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15forcered_simplePfS_
.globl _Z15forcered_simplePfS_
.p2align 8
.type _Z15forcered_simplePfS_,@function
_Z15forcered_simplePfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, 0x405, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v0, 2, v1
v_mov_b32_e32 v2, 0
ds_store_b32 v0, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
v_mul_hi_i32 v0, v1, 0x2fc44aa3
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v4, v1, 0x157
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 6, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, 0x157
v_lshlrev_b32_e32 v0, 2, v1
ds_load_b32 v2, v0
v_sub_nc_u32_e32 v3, v1, v3
v_mul_lo_u32 v3, v3, 0x156
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v4, v3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s6, v3
s_addk_i32 s6, 0x157
s_cmp_lg_u32 s6, 0x1cb91
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s4, v4
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
s_cbranch_scc1 .LBB0_4
ds_store_b32 v0, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v1
v_ashrrev_i32_e32 v2, 31, v1
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15forcered_simplePfS_
.amdhsa_group_segment_fixed_size 4116
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15forcered_simplePfS_, .Lfunc_end0-_Z15forcered_simplePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4116
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15forcered_simplePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15forcered_simplePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Include files
// Parameters
#define N_ATOMS 343
#define MASS_ATOM 1.0f
#define time_step 0.01f
#define L 10.5f
#define T 0.728f
#define NUM_STEPS 10000
const int BLOCK_SIZE = 1024;
//const int L = ;
const int scheme = 1; // 0 for explicit, 1 for implicit
/*************************************************************************************************************/
/************* INITIALIZATION CODE **********/
/*************************************************************************************************************/
__global__ void forcered_simple(float * force, float * forcered){
int index = threadIdx.x + blockDim.x*blockIdx.x;
int i = 0;
int findex;
__shared__ float forcered_sh[3 * N_ATOMS];
//if (index == 0){ printf("In force reduction kernel! \n"); }
if (index < 3 * N_ATOMS){
forcered_sh[index] = 0.0f;
}
__syncthreads();
if (index < 3 * N_ATOMS){
findex = int(index / N_ATOMS)*N_ATOMS*N_ATOMS + index % N_ATOMS;
for (i = 0; i < N_ATOMS; i++){
forcered_sh[index] += force[findex + i*N_ATOMS];
}
}
__syncthreads();
if (index < 3 * N_ATOMS){
forcered[index] = forcered_sh[index];
}
/*if (index == 0){
printf("forcered [0]= %f \n", forcered[0]);
printf("forcered [2]= %f \n", forcered[2]);
printf("forcered [4]= %f \n \n", forcered[4]);
}*/
} | .text
.file "forcered_simple.hip"
.globl _Z30__device_stub__forcered_simplePfS_ # -- Begin function _Z30__device_stub__forcered_simplePfS_
.p2align 4, 0x90
.type _Z30__device_stub__forcered_simplePfS_,@function
_Z30__device_stub__forcered_simplePfS_: # @_Z30__device_stub__forcered_simplePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15forcered_simplePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__forcered_simplePfS_, .Lfunc_end0-_Z30__device_stub__forcered_simplePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15forcered_simplePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15forcered_simplePfS_,@object # @_Z15forcered_simplePfS_
.section .rodata,"a",@progbits
.globl _Z15forcered_simplePfS_
.p2align 3, 0x0
_Z15forcered_simplePfS_:
.quad _Z30__device_stub__forcered_simplePfS_
.size _Z15forcered_simplePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15forcered_simplePfS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__forcered_simplePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15forcered_simplePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15forcered_simplePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xf10 ; /* 0x00000ed000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P1, PT, R0, 0x404, PT ; /* 0x000004040000780c */
/* 0x000fda0003f24270 */
/*0070*/ @!P1 STS [R0.X4], RZ ; /* 0x000000ff00009388 */
/* 0x0001e80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ @P1 BRA 0xf00 ; /* 0x00000e6000001947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.HI R2, R0, 0x2fc44aa3, RZ ; /* 0x2fc44aa300027827 */
/* 0x001fe200078e02ff */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.0444393157958984375e-05 ; /* 0x00000157ff057435 */
/* 0x000fc800000001ff */
/*00c0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*00d0*/ LEA.HI.SX32 R3, R2, R3, 0x1a ; /* 0x0000000302037211 */
/* 0x000fe400078fd2ff */
/*00e0*/ IMAD R6, R0, R5, 0x405 ; /* 0x0000040500067424 */
/* 0x000fe200078e0205 */
/*00f0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e240000004800 */
/*0100*/ IMAD R3, R3, -0x157, R0 ; /* 0xfffffea903037824 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD R5, R3.reuse, 0x156, RZ ; /* 0x0000015603057824 */
/* 0x040fe400078e02ff */
/*0120*/ IMAD R6, R3, -0x156, R6 ; /* 0xfffffeaa03067824 */
/* 0x000fe200078e0206 */
/*0130*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD R4, R0, 0x157, -R5 ; /* 0x0000015700047824 */
/* 0x000fc600078e0a05 */
/*0150*/ IADD3 R10, R6, -0x2ae, RZ ; /* 0xfffffd52060a7810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.WIDE R12, R4, R3, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD.WIDE R10, R10, R3, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe400078e0203 */
/*0180*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000e28000c1e1900 */
/*0190*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R17, [R10.64+0x55c] ; /* 0x00055c040a117981 */
/* 0x000ee2000c1e1900 */
/*01b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 4.088878631591796875e-05 ; /* 0x000002aeff087435 */
/* 0x000fe200000001ff */
/*01c0*/ FADD R2, R2, R13 ; /* 0x0000000d02027221 */
/* 0x001fc80000000000 */
/*01d0*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x004fc80000000000 */
/*01e0*/ FADD R17, R2, R17 ; /* 0x0000001102117221 */
/* 0x008fe40000000000 */
/*01f0*/ IADD3 R12, R4, 0x55c, RZ ; /* 0x0000055c040c7810 */
/* 0x000fe20007ffe0ff */
/*0200*/ LDG.E R21, [R10.64+0xab8] ; /* 0x000ab8040a157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ IADD3 R24, R6, 0x2ae, RZ ; /* 0x000002ae06187810 */
/* 0x000fc60007ffe0ff */
/*0220*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0203 */
/*0230*/ IMAD.WIDE R24, R24, R3, c[0x0][0x160] ; /* 0x0000580018187625 */
/* 0x000fe200078e0203 */
/*0240*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x0002e8000c1e1900 */
/*0250*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x000968000c1e1900 */
/*0260*/ LDG.E R9, [R24.64+0x55c] ; /* 0x00055c0418097981 */
/* 0x000962000c1e1900 */
/*0270*/ IADD3 R26, R4, 0xab8, RZ ; /* 0x00000ab8041a7810 */
/* 0x000fc60007ffe0ff */
/*0280*/ LDG.E R7, [R24.64+0xab8] ; /* 0x000ab80418077981 */
/* 0x000964000c1e1900 */
/*0290*/ IMAD.WIDE R26, R26, R3, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fca00078e0203 */
/*02a0*/ LDG.E R2, [R26.64] ; /* 0x000000041a027981 */
/* 0x000162000c1e1900 */
/*02b0*/ IADD3 R22, R6, 0x80a, RZ ; /* 0x0000080a06167810 */
/* 0x000fca0007ffe0ff */
/*02c0*/ IMAD.WIDE R22, R22, R3, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fca00078e0203 */
/*02d0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000162000c1e1900 */
/*02e0*/ IADD3 R28, R4, 0x1014, RZ ; /* 0x00001014041c7810 */
/* 0x000fc60007ffe0ff */
/*02f0*/ LDG.E R14, [R22.64+0x55c] ; /* 0x00055c04160e7981 */
/* 0x000162000c1e1900 */
/*0300*/ IADD3 R12, R6, 0xd66, RZ ; /* 0x00000d66060c7810 */
/* 0x002fe20007ffe0ff */
/*0310*/ IMAD.WIDE R28, R28, R3.reuse, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x080fe400078e0203 */
/*0320*/ LDG.E R18, [R22.64+0xab8] ; /* 0x000ab80416127981 */
/* 0x000364000c1e1900 */
/*0330*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe400078e0203 */
/*0340*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001168000c1e1900 */
/*0360*/ LDG.E R10, [R12.64+0x55c] ; /* 0x00055c040c0a7981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R24, [R12.64+0xab8] ; /* 0x000ab8040c187981 */
/* 0x010122000c1e1900 */
/*0380*/ IADD3 R26, R4, 0x1570, RZ ; /* 0x00001570041a7810 */
/* 0x000fc40007ffe0ff */
/*0390*/ IADD3 R20, R6, 0x12c2, RZ ; /* 0x000012c206147810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ IMAD.WIDE R26, R26, R3, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fc800078e0203 */
/*03b0*/ IMAD.WIDE R22, R20, R3, c[0x0][0x160] ; /* 0x0000580014167625 */
/* 0x002fe200078e0203 */
/*03c0*/ LDG.E R5, [R26.64] ; /* 0x000000041a057981 */
/* 0x000322000c1e1900 */
/*03d0*/ IADD3 R25, R4, 0x1acc, RZ ; /* 0x00001acc04197810 */
/* 0x000fc60007ffe0ff */
/*03e0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000322000c1e1900 */
/*03f0*/ IADD3 R13, R6, 0x181e, RZ ; /* 0x0000181e060d7810 */
/* 0x001fc60007ffe0ff */
/*0400*/ LDG.E R29, [R22.64+0xab8] ; /* 0x000ab804161d7981 */
/* 0x000122000c1e1900 */
/*0410*/ FADD R17, R21, R17 ; /* 0x0000001115117221 */
/* 0x004fc60000000000 */
/*0420*/ LDG.E R21, [R22.64+0x55c] ; /* 0x00055c0416157981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FADD R12, R17, R16 ; /* 0x00000010110c7221 */
/* 0x008fe40000000000 */
/*0440*/ IMAD.WIDE R16, R25, R3, c[0x0][0x160] ; /* 0x0000580019107625 */
/* 0x000fc800078e0203 */
/*0450*/ FADD R19, R12, R19 ; /* 0x000000130c137221 */
/* 0x020fe40000000000 */
/*0460*/ IMAD.WIDE R12, R13, R3, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe200078e0203 */
/*0470*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000766000c1e1900 */
/*0480*/ FADD R9, R19, R9 ; /* 0x0000000913097221 */
/* 0x000fe20000000000 */
/*0490*/ IADD3 R19, R4, 0x2028, RZ ; /* 0x0000202804137810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ LDG.E R27, [R12.64+0x55c] ; /* 0x00055c040c1b7981 */
/* 0x002362000c1e1900 */
/*04b0*/ IADD3 R22, R6, 0x1d7a, RZ ; /* 0x00001d7a06167810 */
/* 0x001fc60007ffe0ff */
/*04c0*/ LDG.E R26, [R12.64+0xab8] ; /* 0x000ab8040c1a7981 */
/* 0x000368000c1e1900 */
/*04d0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x0082e2000c1e1900 */
/*04e0*/ FADD R7, R9, R7 ; /* 0x0000000709077221 */
/* 0x000fe40000000000 */
/*04f0*/ IMAD.WIDE R22, R22, R3, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fca00078e0203 */
/*0500*/ LDG.E R25, [R22.64+0xab8] ; /* 0x000ab80416197981 */
/* 0x0000e2000c1e1900 */
/*0510*/ IMAD.WIDE R12, R19, R3, c[0x0][0x160] ; /* 0x00005800130c7625 */
/* 0x002fca00078e0203 */
/*0520*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0002e2000c1e1900 */
/*0530*/ FADD R19, R7, R2 ; /* 0x0000000207137221 */
/* 0x000fc60000000000 */
/*0540*/ LDG.E R2, [R22.64] ; /* 0x0000000416027981 */
/* 0x0000e8000c1e1900 */
/*0550*/ LDG.E R7, [R22.64+0x55c] ; /* 0x00055c0416077981 */
/* 0x0000e2000c1e1900 */
/*0560*/ IADD3 R12, R4, 0x2584, RZ ; /* 0x00002584040c7810 */
/* 0x002fe20007ffe0ff */
/*0570*/ FADD R15, R19, R15 ; /* 0x0000000f130f7221 */
/* 0x000fc80000000000 */
/*0580*/ IMAD.WIDE R12, R12, R3, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e0203 */
/*0590*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x0002e4000c1e1900 */
/*05a0*/ IADD3 R12, R6, 0x22d6, RZ ; /* 0x000022d6060c7810 */
/* 0x002fe20007ffe0ff */
/*05b0*/ FADD R13, R15, R14 ; /* 0x0000000e0f0d7221 */
/* 0x000fc80000000000 */
/*05c0*/ IMAD.WIDE R14, R12, R3, c[0x0][0x160] ; /* 0x000058000c0e7625 */
/* 0x000fc800078e0203 */
/*05d0*/ FADD R13, R13, R18 ; /* 0x000000120d0d7221 */
/* 0x000fe20000000000 */
/*05e0*/ IADD3 R23, R4, 0x2ae0, RZ ; /* 0x00002ae004177810 */
/* 0x001fe20007ffe0ff */
/*05f0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x0000e4000c1e1900 */
/*0600*/ FADD R12, R13, R28 ; /* 0x0000001c0d0c7221 */
/* 0x000fe40000000000 */
/*0610*/ LDG.E R28, [R14.64+0x55c] ; /* 0x00055c040e1c7981 */
/* 0x0000e4000c1e1900 */
/*0620*/ FADD R11, R12, R11 ; /* 0x0000000b0c0b7221 */
/* 0x000fe40000000000 */
/*0630*/ IMAD.WIDE R12, R23, R3, c[0x0][0x160] ; /* 0x00005800170c7625 */
/* 0x000fe200078e0203 */
/*0640*/ LDG.E R22, [R14.64+0xab8] ; /* 0x000ab8040e167981 */
/* 0x0000e8000c1e1900 */
/*0650*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x0002e4000c1e1900 */
/*0660*/ IADD3 R12, R6, 0x2832, RZ ; /* 0x00002832060c7810 */
/* 0x002fe20007ffe0ff */
/*0670*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x000fc80000000000 */
/*0680*/ IMAD.WIDE R10, R12, R3, c[0x0][0x160] ; /* 0x000058000c0a7625 */
/* 0x000fc800078e0203 */
/*0690*/ FADD R12, R13, R24 ; /* 0x000000180d0c7221 */
/* 0x010fe40000000000 */
/*06a0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000324000c1e1900 */
/*06b0*/ FADD R5, R12, R5 ; /* 0x000000050c057221 */
/* 0x000fc80000000000 */
/*06c0*/ FADD R20, R5, R20 ; /* 0x0000001405147221 */
/* 0x000fe20000000000 */
/*06d0*/ IADD3 R14, R4, 0x303c, RZ ; /* 0x0000303c040e7810 */
/* 0x001fe20007ffe0ff */
/*06e0*/ LDG.E R5, [R10.64+0x55c] ; /* 0x00055c040a057981 */
/* 0x000328000c1e1900 */
/*06f0*/ IMAD.WIDE R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0203 */
/*0700*/ FADD R20, R20, R21 ; /* 0x0000001514147221 */
/* 0x004fe40000000000 */
/*0710*/ LDG.E R21, [R10.64+0xab8] ; /* 0x000ab8040a157981 */
/* 0x0002a4000c1e1900 */
/*0720*/ FADD R20, R20, R29 ; /* 0x0000001d14147221 */
/* 0x000fc80000000000 */
/*0730*/ FADD R17, R20, R17 ; /* 0x0000001114117221 */
/* 0x020fe20000000000 */
/*0740*/ IADD3 R20, R6, 0x2d8e, RZ ; /* 0x00002d8e06147810 */
/* 0x000fc60007ffe0ff */
/*0750*/ FADD R12, R17, R16 ; /* 0x00000010110c7221 */
/* 0x008fe40000000000 */
/*0760*/ IMAD.WIDE R16, R20, R3, c[0x0][0x160] ; /* 0x0000580014107625 */
/* 0x000fe400078e0203 */
/*0770*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000e4000c1e1900 */
/*0780*/ FADD R27, R12, R27 ; /* 0x0000001b0c1b7221 */
/* 0x000fe40000000000 */
/*0790*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x000ae4000c1e1900 */
/*07a0*/ FADD R26, R27, R26 ; /* 0x0000001a1b1a7221 */
/* 0x000fe20000000000 */
/*07b0*/ IADD3 R27, R4, 0x3598, RZ ; /* 0x00003598041b7810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ LDG.E R12, [R16.64+0x55c] ; /* 0x00055c04100c7981 */
/* 0x000ae2000c1e1900 */
/*07d0*/ IADD3 R11, R6, 0x32ea, RZ ; /* 0x000032ea060b7810 */
/* 0x002fe20007ffe0ff */
/*07e0*/ FADD R9, R26, R9 ; /* 0x000000091a097221 */
/* 0x000fc40000000000 */
/*07f0*/ LDG.E R10, [R16.64+0xab8] ; /* 0x000ab804100a7981 */
/* 0x000ae2000c1e1900 */
/*0800*/ IMAD.WIDE R26, R27, R3, c[0x0][0x160] ; /* 0x000058001b1a7625 */
/* 0x000fc800078e0203 */
/*0810*/ FADD R9, R9, R2 ; /* 0x0000000209097221 */
/* 0x000fe40000000000 */
/*0820*/ IMAD.WIDE R14, R11, R3, c[0x0][0x160] ; /* 0x000058000b0e7625 */
/* 0x001fe200078e0203 */
/*0830*/ LDG.E R2, [R26.64] ; /* 0x000000041a027981 */
/* 0x0000e6000c1e1900 */
/*0840*/ FADD R29, R9, R7 ; /* 0x00000007091d7221 */
/* 0x000fe20000000000 */
/*0850*/ LDG.E R11, [R14.64+0x55c] ; /* 0x00055c040e0b7981 */
/* 0x0002e8000c1e1900 */
/*0860*/ LDG.E R7, [R14.64] ; /* 0x000000040e077981 */
/* 0x0002e2000c1e1900 */
/*0870*/ IADD3 R26, R4, 0x3af4, RZ ; /* 0x00003af4041a7810 */
/* 0x001fc60007ffe0ff */
/*0880*/ LDG.E R9, [R14.64+0xab8] ; /* 0x000ab8040e097981 */
/* 0x0002e2000c1e1900 */
/*0890*/ IADD3 R16, R6, 0x3846, RZ ; /* 0x0000384606107810 */
/* 0x020fe20007ffe0ff */
/*08a0*/ FADD R29, R29, R25 ; /* 0x000000191d1d7221 */
/* 0x000fe40000000000 */
/*08b0*/ IMAD.WIDE R14, R26, R3, c[0x0][0x160] ; /* 0x000058001a0e7625 */
/* 0x002fca00078e0203 */
/*08c0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000162000c1e1900 */
/*08d0*/ IMAD.WIDE R16, R16, R3, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fca00078e0203 */
/*08e0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000362000c1e1900 */
/*08f0*/ FADD R19, R29, R19 ; /* 0x000000131d137221 */
/* 0x000fc60000000000 */
/*0900*/ LDG.E R27, [R16.64+0x55c] ; /* 0x00055c04101b7981 */
/* 0x000362000c1e1900 */
/*0910*/ IADD3 R14, R4, 0x4050, RZ ; /* 0x00004050040e7810 */
/* 0x001fe20007ffe0ff */
/*0920*/ FADD R15, R19, R18 ; /* 0x00000012130f7221 */
/* 0x000fe40000000000 */
/*0930*/ LDG.E R29, [R16.64+0xab8] ; /* 0x000ab804101d7981 */
/* 0x000364000c1e1900 */
/*0940*/ IMAD.WIDE R18, R14, R3, c[0x0][0x160] ; /* 0x000058000e127625 */
/* 0x000fe200078e0203 */
/*0950*/ IADD3 R14, R6, 0x3da2, RZ ; /* 0x00003da2060e7810 */
/* 0x000fc60007ffe0ff */
/*0960*/ FADD R28, R15, R28 ; /* 0x0000001c0f1c7221 */
/* 0x000fe40000000000 */
/*0970*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000162000c1e1900 */
/*0980*/ IMAD.WIDE R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0203 */
/*0990*/ FADD R28, R28, R22 ; /* 0x000000161c1c7221 */
/* 0x000fe40000000000 */
/*09a0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000164000c1e1900 */
/*09b0*/ FADD R17, R28, R23 ; /* 0x000000171c117221 */
/* 0x002fe40000000000 */
/*09c0*/ LDG.E R23, [R14.64+0x55c] ; /* 0x00055c040e177981 */
/* 0x000162000c1e1900 */
/*09d0*/ IADD3 R16, R4, 0x45ac, RZ ; /* 0x000045ac04107810 */
/* 0x000fc60007ffe0ff */
/*09e0*/ LDG.E R28, [R14.64+0xab8] ; /* 0x000ab8040e1c7981 */
/* 0x000162000c1e1900 */
/*09f0*/ FADD R24, R17, R24 ; /* 0x0000001811187221 */
/* 0x010fe40000000000 */
/*0a00*/ IMAD.WIDE R16, R16, R3, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fcc00078e0203 */
/*0a10*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0a20*/ FADD R24, R24, R5 ; /* 0x0000000518187221 */
/* 0x000fe20000000000 */
/*0a30*/ IADD3 R14, R4, 0x4b08, RZ ; /* 0x00004b08040e7810 */
/* 0x001fe40007ffe0ff */
/*0a40*/ IADD3 R19, R6, 0x4db6, RZ ; /* 0x00004db606137810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R21, R24, R21 ; /* 0x0000001518157221 */
/* 0x004fe20000000000 */
/*0a60*/ IADD3 R24, R6, 0x485a, RZ ; /* 0x0000485a06187810 */
/* 0x000fc60007ffe0ff */
/*0a70*/ FADD R20, R21, R20 ; /* 0x0000001415147221 */
/* 0x008fc80000000000 */
/*0a80*/ FADD R13, R20, R13 ; /* 0x0000000d140d7221 */
/* 0x000fe20000000000 */
/*0a90*/ IADD3 R20, R6, 0x42fe, RZ ; /* 0x000042fe06147810 */
/* 0x000fc60007ffe0ff */
/*0aa0*/ FADD R5, R13, R12 ; /* 0x0000000c0d057221 */
/* 0x000fe40000000000 */
/*0ab0*/ IMAD.WIDE R12, R20, R3, c[0x0][0x160] ; /* 0x00005800140c7625 */
/* 0x000fc800078e0203 */
/*0ac0*/ FADD R15, R5, R10 ; /* 0x0000000a050f7221 */
/* 0x000fe40000000000 */
/*0ad0*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x0000a4000c1e1900 */
/*0ae0*/ FADD R10, R15, R2 ; /* 0x000000020f0a7221 */
/* 0x000fe40000000000 */
/*0af0*/ LDG.E R2, [R12.64+0x55c] ; /* 0x00055c040c027981 */
/* 0x0000e2000c1e1900 */
/*0b00*/ IMAD.WIDE R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0203 */
/*0b10*/ FADD R10, R10, R7 ; /* 0x000000070a0a7221 */
/* 0x000fe20000000000 */
/*0b20*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x0022e8000c1e1900 */
/*0b30*/ LDG.E R7, [R12.64+0xab8] ; /* 0x000ab8040c077981 */
/* 0x0000e2000c1e1900 */
/*0b40*/ FADD R20, R10, R11 ; /* 0x0000000b0a147221 */
/* 0x000fe40000000000 */
/*0b50*/ IMAD.WIDE R10, R24, R3, c[0x0][0x160] ; /* 0x00005800180a7625 */
/* 0x000fc800078e0203 */
/*0b60*/ FADD R20, R20, R9 ; /* 0x0000000914147221 */
/* 0x000fe20000000000 */
/*0b70*/ IADD3 R24, R4, 0x5064, RZ ; /* 0x0000506404187810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ae2000c1e1900 */
/*0b90*/ IMAD.WIDE R14, R19, R3, c[0x0][0x160] ; /* 0x00005800130e7625 */
/* 0x002fc600078e0203 */
/*0ba0*/ LDG.E R21, [R10.64+0xab8] ; /* 0x000ab8040a157981 */
/* 0x0002e2000c1e1900 */
/*0bb0*/ FADD R25, R20, R25 ; /* 0x0000001914197221 */
/* 0x020fc60000000000 */
/*0bc0*/ LDG.E R20, [R10.64+0x55c] ; /* 0x00055c040a147981 */
/* 0x000362000c1e1900 */
/*0bd0*/ IMAD.WIDE R12, R24, R3, c[0x0][0x160] ; /* 0x00005800180c7625 */
/* 0x001fc800078e0203 */
/*0be0*/ FADD R26, R25, R26 ; /* 0x0000001a191a7221 */
/* 0x000fe20000000000 */
/*0bf0*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x000166000c1e1900 */
/*0c00*/ FADD R26, R26, R27 ; /* 0x0000001b1a1a7221 */
/* 0x000fe20000000000 */
/*0c10*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000362000c1e1900 */
/*0c20*/ IADD3 R19, R4, 0x55c0, RZ ; /* 0x000055c004137810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ FADD R29, R26, R29 ; /* 0x0000001d1a1d7221 */
/* 0x000fe20000000000 */
/*0c40*/ LDG.E R27, [R14.64+0xab8] ; /* 0x000ab8040e1b7981 */
/* 0x000362000c1e1900 */
/*0c50*/ IADD3 R12, R6, 0x5312, RZ ; /* 0x00005312060c7810 */
/* 0x001fc60007ffe0ff */
/*0c60*/ LDG.E R26, [R14.64+0x55c] ; /* 0x00055c040e1a7981 */
/* 0x000162000c1e1900 */
/*0c70*/ IMAD.WIDE R10, R19, R3, c[0x0][0x160] ; /* 0x00005800130a7625 */
/* 0x002fc800078e0203 */
/*0c80*/ FADD R13, R29, R18 ; /* 0x000000121d0d7221 */
/* 0x000fe40000000000 */
/*0c90*/ IMAD.WIDE R18, R12, R3.reuse, c[0x0][0x160] ; /* 0x000058000c127625 */
/* 0x080fe200078e0203 */
/*0ca0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001166000c1e1900 */
/*0cb0*/ FADD R22, R13, R22 ; /* 0x000000160d167221 */
/* 0x000fe20000000000 */
/*0cc0*/ IADD3 R4, R4, 0x5b1c, RZ ; /* 0x00005b1c04047810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000364000c1e1900 */
/*0ce0*/ FADD R23, R22, R23 ; /* 0x0000001716177221 */
/* 0x000fe20000000000 */
/*0cf0*/ IADD3 R22, R6, 0x586e, RZ ; /* 0x0000586e06167810 */
/* 0x000fe20007ffe0ff */
/*0d00*/ LDG.E R29, [R18.64+0x55c] ; /* 0x00055c04121d7981 */
/* 0x000362000c1e1900 */
/*0d10*/ IMAD.WIDE R12, R4, R3, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x000fc800078e0203 */
/*0d20*/ IMAD.WIDE R10, R22, R3, c[0x0][0x160] ; /* 0x00005800160a7625 */
/* 0x001fe400078e0203 */
/*0d30*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f68000c1e1900 */
/*0d40*/ LDG.E R18, [R18.64+0xab8] ; /* 0x000ab80412127981 */
/* 0x002162000c1e1900 */
/*0d50*/ FADD R23, R23, R28 ; /* 0x0000001c17177221 */
/* 0x000fc80000000000 */
/*0d60*/ FADD R22, R23, R16 ; /* 0x0000001017167221 */
/* 0x010fe40000000000 */
/*0d70*/ LDG.E R16, [R10.64+0x55c] ; /* 0x00055c040a107981 */
/* 0x000f28000c1e1900 */
/*0d80*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x001f22000c1e1900 */
/*0d90*/ IADD3 R8, R8, 0x5b1c, RZ ; /* 0x00005b1c08087810 */
/* 0x000fc80007ffe0ff */
/*0da0*/ ISETP.NE.AND P0, PT, R8, 0x1ca3a, PT ; /* 0x0001ca3a0800780c */
/* 0x000fe40003f05270 */
/*0db0*/ IADD3 R6, R6, 0x5b1c, RZ ; /* 0x00005b1c06067810 */
/* 0x000fe20007ffe0ff */
/*0dc0*/ FADD R5, R22, R5 ; /* 0x0000000516057221 */
/* 0x004fc80000000000 */
/*0dd0*/ FADD R2, R5, R2 ; /* 0x0000000205027221 */
/* 0x008fc80000000000 */
/*0de0*/ FADD R2, R2, R7 ; /* 0x0000000702027221 */
/* 0x000fc80000000000 */
/*0df0*/ FADD R2, R2, R17 ; /* 0x0000001102027221 */
/* 0x000fc80000000000 */
/*0e00*/ FADD R9, R2, R9 ; /* 0x0000000902097221 */
/* 0x000fc80000000000 */
/*0e10*/ FADD R20, R9, R20 ; /* 0x0000001409147221 */
/* 0x020fc80000000000 */
/*0e20*/ FADD R21, R20, R21 ; /* 0x0000001514157221 */
/* 0x000fc80000000000 */
/*0e30*/ FADD R24, R21, R24 ; /* 0x0000001815187221 */
/* 0x000fc80000000000 */
/*0e40*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x000fc80000000000 */
/*0e50*/ FADD R26, R25, R26 ; /* 0x0000001a191a7221 */
/* 0x000fc80000000000 */
/*0e60*/ FADD R26, R26, R27 ; /* 0x0000001b1a1a7221 */
/* 0x000fc80000000000 */
/*0e70*/ FADD R15, R26, R15 ; /* 0x0000000f1a0f7221 */
/* 0x000fc80000000000 */
/*0e80*/ FADD R14, R15, R14 ; /* 0x0000000e0f0e7221 */
/* 0x000fc80000000000 */
/*0e90*/ FADD R5, R14, R29 ; /* 0x0000001d0e057221 */
/* 0x000fc80000000000 */
/*0ea0*/ FADD R5, R18, R5 ; /* 0x0000000512057221 */
/* 0x000fc80000000000 */
/*0eb0*/ FADD R12, R5, R12 ; /* 0x0000000c050c7221 */
/* 0x000fc80000000000 */
/*0ec0*/ FADD R19, R12, R19 ; /* 0x000000130c137221 */
/* 0x010fc80000000000 */
/*0ed0*/ FADD R17, R19, R16 ; /* 0x0000001013117221 */
/* 0x000fe20000000000 */
/*0ee0*/ @P0 BRA 0x1f0 ; /* 0xfffff30000000947 */
/* 0x000fea000383ffff */
/*0ef0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0001e40000004800 */
/*0f00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0f10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0f20*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0f30*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e220000004800 */
/*0f40*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0f50*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0f60*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0f70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f80*/ BRA 0xf80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15forcered_simplePfS_
.globl _Z15forcered_simplePfS_
.p2align 8
.type _Z15forcered_simplePfS_,@function
_Z15forcered_simplePfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, 0x405, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v0, 2, v1
v_mov_b32_e32 v2, 0
ds_store_b32 v0, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
v_mul_hi_i32 v0, v1, 0x2fc44aa3
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v4, v1, 0x157
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 6, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, 0x157
v_lshlrev_b32_e32 v0, 2, v1
ds_load_b32 v2, v0
v_sub_nc_u32_e32 v3, v1, v3
v_mul_lo_u32 v3, v3, 0x156
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v4, v3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s6, v3
s_addk_i32 s6, 0x157
s_cmp_lg_u32 s6, 0x1cb91
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s4, v4
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
s_cbranch_scc1 .LBB0_4
ds_store_b32 v0, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v1
v_ashrrev_i32_e32 v2, 31, v1
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15forcered_simplePfS_
.amdhsa_group_segment_fixed_size 4116
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15forcered_simplePfS_, .Lfunc_end0-_Z15forcered_simplePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4116
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15forcered_simplePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15forcered_simplePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000282fc_00000000-6_forcered_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15forcered_simplePfS_PfS_
.type _Z37__device_stub__Z15forcered_simplePfS_PfS_, @function
_Z37__device_stub__Z15forcered_simplePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15forcered_simplePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z15forcered_simplePfS_PfS_, .-_Z37__device_stub__Z15forcered_simplePfS_PfS_
.globl _Z15forcered_simplePfS_
.type _Z15forcered_simplePfS_, @function
_Z15forcered_simplePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15forcered_simplePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15forcered_simplePfS_, .-_Z15forcered_simplePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15forcered_simplePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15forcered_simplePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "forcered_simple.hip"
.globl _Z30__device_stub__forcered_simplePfS_ # -- Begin function _Z30__device_stub__forcered_simplePfS_
.p2align 4, 0x90
.type _Z30__device_stub__forcered_simplePfS_,@function
_Z30__device_stub__forcered_simplePfS_: # @_Z30__device_stub__forcered_simplePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15forcered_simplePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__forcered_simplePfS_, .Lfunc_end0-_Z30__device_stub__forcered_simplePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15forcered_simplePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15forcered_simplePfS_,@object # @_Z15forcered_simplePfS_
.section .rodata,"a",@progbits
.globl _Z15forcered_simplePfS_
.p2align 3, 0x0
_Z15forcered_simplePfS_:
.quad _Z30__device_stub__forcered_simplePfS_
.size _Z15forcered_simplePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15forcered_simplePfS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__forcered_simplePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15forcered_simplePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Center assignments
Written by Jiageng Mao
*/
#include <math.h>
#include <stdio.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))
__device__ float limit_period(float val, float offset, float period){
float rval = val - floor(val / period + offset) * period;
return rval;
}
__device__ float gaussian_radius(float height, float width, float min_overlap){
float a1 = 1;
float b1 = (height + width);
float c1 = width * height * (1 - min_overlap) / (1 + min_overlap);
float sq1 = sqrt(b1 * b1 - 4 * a1 * c1);
float r1 = (b1 + sq1) / 2;
float a2 = 4;
float b2 = 2 * (height + width);
float c2 = (1 - min_overlap) * width * height;
float sq2 = sqrt(b2 * b2 - 4 * a2 * c2);
float r2 = (b2 + sq2) / 2;
float a3 = 4 * min_overlap;
float b3 = -2 * min_overlap * (height + width);
float c3 = (min_overlap - 1) * width * height;
float sq3 = sqrt(b3 * b3 - 4 * a3 * c3);
float r3 = (b3 + sq3) / 2;
return min(min(r1, r2), r3);
}
__global__ void draw_center_kernel(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
/*
Args:
gt_boxes: (B, max_boxes, 8 or 10) with class labels
heatmap: (B, num_cls, H, W)
gt_ind: (B, num_cls, max_objs)
gt_mask: (B, num_cls, max_objs)
gt_cat: (B, num_cls, max_objs)
gt_box_encoding: (B, num_cls, max_objs, code_size) sin/cos
gt_cnt: (B, num_cls)
*/
int bs_idx = blockIdx.x;
int box_idx = threadIdx.x;
if (bs_idx >= batch_size || box_idx >= max_boxes) return;
// move pointer
gt_boxes += bs_idx * max_boxes * code_size;
heatmap += bs_idx * num_cls * H * W;
gt_ind += bs_idx * num_cls * max_objs;
gt_mask += bs_idx * num_cls * max_objs;
gt_cat += bs_idx * num_cls * max_objs;
gt_box_encoding += bs_idx * num_cls * max_objs * code_size;
gt_cnt += bs_idx * num_cls;
// gt box parameters
float x = gt_boxes[box_idx * code_size + 0];
float y = gt_boxes[box_idx * code_size + 1];
float z = gt_boxes[box_idx * code_size + 2];
float dx = gt_boxes[box_idx * code_size + 3];
float dy = gt_boxes[box_idx * code_size + 4];
float dz = gt_boxes[box_idx * code_size + 5];
// origin dx/dy/dz is for box_encodings
float origin_dx = gt_boxes[box_idx * code_size + 3];
float origin_dy = gt_boxes[box_idx * code_size + 4];
float origin_dz = gt_boxes[box_idx * code_size + 5];
float rot = gt_boxes[box_idx * code_size + 6];
float vel_x = 0;
float vel_y = 0;
float cls = 0;
if (code_size == 10) {
vel_x = gt_boxes[box_idx * code_size + 7];
vel_y = gt_boxes[box_idx * code_size + 8];
cls = gt_boxes[box_idx * code_size + 9];
} else if (code_size == 8) {
cls = gt_boxes[box_idx * code_size + 7];
} else {
return;
}
// box not defined
if (dx == 0 || dy == 0 || dz == 0) return;
// cls begin from 1
int cls_idx = (int) cls - 1;
heatmap += cls_idx * H * W;
gt_ind += cls_idx * max_objs;
gt_mask += cls_idx * max_objs;
gt_cat += cls_idx * max_objs;
gt_box_encoding += cls_idx * max_objs * code_size;
gt_cnt += cls_idx;
// transform to bev map coords
float offset = 0.5;
float period = 6.283185307179586;
rot = limit_period(rot, offset, period);
dx = dx / voxel_x / out_factor;
dy = dy / voxel_y / out_factor;
float radius = gaussian_radius(dy, dx, gaussian_overlap);
int radius_int = max(min_radius, (int) radius);
float coor_x = (x - range_x) / voxel_x / out_factor;
float coor_y = (y - range_y) / voxel_y / out_factor;
int coor_x_int = (int) coor_x;
int coor_y_int = (int) coor_y;
if (coor_x_int >= W || coor_x_int < 0) return;
if (coor_y_int >= H || coor_y_int < 0) return;
// draw gaussian map
float div_factor = 6.0;
float sigma = (2 * radius_int + 1) / div_factor;
for (int scan_y = -radius_int; scan_y < radius_int + 1; scan_y++){
if (coor_y_int + scan_y < 0 || coor_y_int + scan_y >= H) continue;
for (int scan_x = -radius_int; scan_x < radius_int + 1; scan_x++){
if (coor_x_int + scan_x < 0 || coor_x_int + scan_x >= W) continue;
float weight = exp(-(scan_x * scan_x + scan_y * scan_y) / (2 * sigma * sigma)); // force convert float sigma
float eps = 0.0000001;
if (weight < eps) weight = 0;
float *w_addr = heatmap + (coor_y_int + scan_y) * W + (coor_x_int + scan_x);
float old_weight = atomicExch(w_addr, weight);
if (old_weight > weight) weight = atomicExch(w_addr, old_weight);
}
}
int obj_idx = atomicAdd(gt_cnt, 1);
if (obj_idx >= max_objs) return;
gt_ind[obj_idx] = coor_y_int * W + coor_x_int;
gt_mask[obj_idx] = 1;
gt_cat[obj_idx] = cls_idx + 1; // begin from 1
gt_box_encoding[obj_idx * code_size + 0] = coor_x - coor_x_int;
gt_box_encoding[obj_idx * code_size + 1] = coor_y - coor_y_int;
gt_box_encoding[obj_idx * code_size + 2] = z;
gt_box_encoding[obj_idx * code_size + 3] = origin_dx;
gt_box_encoding[obj_idx * code_size + 4] = origin_dy;
gt_box_encoding[obj_idx * code_size + 5] = origin_dz;
gt_box_encoding[obj_idx * code_size + 6] = sin(rot);
gt_box_encoding[obj_idx * code_size + 7] = cos(rot);
if (code_size == 10) {
gt_box_encoding[obj_idx * code_size + 8] = vel_x;
gt_box_encoding[obj_idx * code_size + 9] = vel_y;
}
return;
}
void draw_center_kernel_launcher(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
cudaError_t err;
dim3 blocks(batch_size);
dim3 threads(THREADS_PER_BLOCK);
draw_center_kernel<<<blocks, threads>>>(batch_size, max_boxes, max_objs, num_cls, H, W, code_size, min_radius,
voxel_x, voxel_y, range_x, range_y, out_factor, gaussian_overlap,
gt_boxes, heatmap, gt_ind, gt_mask, gt_cat, gt_box_encoding, gt_cnt);
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
#ifdef DEBUG
cudaDeviceSynchronize(); // for using printf in kernel function
#endif
} | .file "tmpxft_000336d3_00000000-6_draw_center_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12limit_periodfff
.type _Z12limit_periodfff, @function
_Z12limit_periodfff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12limit_periodfff, .-_Z12limit_periodfff
.globl _Z15gaussian_radiusfff
.type _Z15gaussian_radiusfff, @function
_Z15gaussian_radiusfff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z15gaussian_radiusfff, .-_Z15gaussian_radiusfff
.globl _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.type _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2084:
.cfi_startproc
endbr64
subq $360, %rsp
.cfi_def_cfa_offset 368
movl %edi, 108(%rsp)
movl %esi, 104(%rsp)
movl %edx, 100(%rsp)
movl %ecx, 96(%rsp)
movl %r8d, 92(%rsp)
movl %r9d, 88(%rsp)
movss %xmm0, 84(%rsp)
movss %xmm1, 80(%rsp)
movss %xmm2, 76(%rsp)
movss %xmm3, 72(%rsp)
movss %xmm4, 68(%rsp)
movss %xmm5, 64(%rsp)
movq 384(%rsp), %rax
movq %rax, 56(%rsp)
movq 392(%rsp), %rax
movq %rax, 48(%rsp)
movq 400(%rsp), %rax
movq %rax, 40(%rsp)
movq 408(%rsp), %rax
movq %rax, 32(%rsp)
movq 416(%rsp), %rax
movq %rax, 24(%rsp)
movq 424(%rsp), %rax
movq %rax, 16(%rsp)
movq 432(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 100(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 92(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 84(%rsp), %rax
movq %rax, 240(%rsp)
leaq 80(%rsp), %rax
movq %rax, 248(%rsp)
leaq 76(%rsp), %rax
movq %rax, 256(%rsp)
leaq 72(%rsp), %rax
movq %rax, 264(%rsp)
leaq 68(%rsp), %rax
movq %rax, 272(%rsp)
leaq 64(%rsp), %rax
movq %rax, 280(%rsp)
leaq 56(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 32(%rsp), %rax
movq %rax, 312(%rsp)
leaq 24(%rsp), %rax
movq %rax, 320(%rsp)
leaq 16(%rsp), %rax
movq %rax, 328(%rsp)
leaq 8(%rsp), %rax
movq %rax, 336(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 376
pushq 120(%rsp)
.cfi_def_cfa_offset 384
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.globl _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.type _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA kernel failed : %s\n"
.text
.globl _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.type _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 28(%rsp)
movl %edi, 40(%rsp)
movl $1, 44(%rsp)
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 200(%rsp)
.cfi_def_cfa_offset 144
pushq 200(%rsp)
.cfi_def_cfa_offset 152
pushq 200(%rsp)
.cfi_def_cfa_offset 160
pushq 200(%rsp)
.cfi_def_cfa_offset 168
pushq 200(%rsp)
.cfi_def_cfa_offset 176
pushq 200(%rsp)
.cfi_def_cfa_offset 184
pushq 200(%rsp)
.cfi_def_cfa_offset 192
movl 200(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 200
movl 200(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 208
movss 108(%rsp), %xmm5
movss 104(%rsp), %xmm4
movss 100(%rsp), %xmm3
movss 96(%rsp), %xmm2
movss 92(%rsp), %xmm1
movss 88(%rsp), %xmm0
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
addq $80, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Center assignments
Written by Jiageng Mao
*/
#include <math.h>
#include <stdio.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))
__device__ float limit_period(float val, float offset, float period){
float rval = val - floor(val / period + offset) * period;
return rval;
}
__device__ float gaussian_radius(float height, float width, float min_overlap){
float a1 = 1;
float b1 = (height + width);
float c1 = width * height * (1 - min_overlap) / (1 + min_overlap);
float sq1 = sqrt(b1 * b1 - 4 * a1 * c1);
float r1 = (b1 + sq1) / 2;
float a2 = 4;
float b2 = 2 * (height + width);
float c2 = (1 - min_overlap) * width * height;
float sq2 = sqrt(b2 * b2 - 4 * a2 * c2);
float r2 = (b2 + sq2) / 2;
float a3 = 4 * min_overlap;
float b3 = -2 * min_overlap * (height + width);
float c3 = (min_overlap - 1) * width * height;
float sq3 = sqrt(b3 * b3 - 4 * a3 * c3);
float r3 = (b3 + sq3) / 2;
return min(min(r1, r2), r3);
}
__global__ void draw_center_kernel(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
/*
Args:
gt_boxes: (B, max_boxes, 8 or 10) with class labels
heatmap: (B, num_cls, H, W)
gt_ind: (B, num_cls, max_objs)
gt_mask: (B, num_cls, max_objs)
gt_cat: (B, num_cls, max_objs)
gt_box_encoding: (B, num_cls, max_objs, code_size) sin/cos
gt_cnt: (B, num_cls)
*/
int bs_idx = blockIdx.x;
int box_idx = threadIdx.x;
if (bs_idx >= batch_size || box_idx >= max_boxes) return;
// move pointer
gt_boxes += bs_idx * max_boxes * code_size;
heatmap += bs_idx * num_cls * H * W;
gt_ind += bs_idx * num_cls * max_objs;
gt_mask += bs_idx * num_cls * max_objs;
gt_cat += bs_idx * num_cls * max_objs;
gt_box_encoding += bs_idx * num_cls * max_objs * code_size;
gt_cnt += bs_idx * num_cls;
// gt box parameters
float x = gt_boxes[box_idx * code_size + 0];
float y = gt_boxes[box_idx * code_size + 1];
float z = gt_boxes[box_idx * code_size + 2];
float dx = gt_boxes[box_idx * code_size + 3];
float dy = gt_boxes[box_idx * code_size + 4];
float dz = gt_boxes[box_idx * code_size + 5];
// origin dx/dy/dz is for box_encodings
float origin_dx = gt_boxes[box_idx * code_size + 3];
float origin_dy = gt_boxes[box_idx * code_size + 4];
float origin_dz = gt_boxes[box_idx * code_size + 5];
float rot = gt_boxes[box_idx * code_size + 6];
float vel_x = 0;
float vel_y = 0;
float cls = 0;
if (code_size == 10) {
vel_x = gt_boxes[box_idx * code_size + 7];
vel_y = gt_boxes[box_idx * code_size + 8];
cls = gt_boxes[box_idx * code_size + 9];
} else if (code_size == 8) {
cls = gt_boxes[box_idx * code_size + 7];
} else {
return;
}
// box not defined
if (dx == 0 || dy == 0 || dz == 0) return;
// cls begin from 1
int cls_idx = (int) cls - 1;
heatmap += cls_idx * H * W;
gt_ind += cls_idx * max_objs;
gt_mask += cls_idx * max_objs;
gt_cat += cls_idx * max_objs;
gt_box_encoding += cls_idx * max_objs * code_size;
gt_cnt += cls_idx;
// transform to bev map coords
float offset = 0.5;
float period = 6.283185307179586;
rot = limit_period(rot, offset, period);
dx = dx / voxel_x / out_factor;
dy = dy / voxel_y / out_factor;
float radius = gaussian_radius(dy, dx, gaussian_overlap);
int radius_int = max(min_radius, (int) radius);
float coor_x = (x - range_x) / voxel_x / out_factor;
float coor_y = (y - range_y) / voxel_y / out_factor;
int coor_x_int = (int) coor_x;
int coor_y_int = (int) coor_y;
if (coor_x_int >= W || coor_x_int < 0) return;
if (coor_y_int >= H || coor_y_int < 0) return;
// draw gaussian map
float div_factor = 6.0;
float sigma = (2 * radius_int + 1) / div_factor;
for (int scan_y = -radius_int; scan_y < radius_int + 1; scan_y++){
if (coor_y_int + scan_y < 0 || coor_y_int + scan_y >= H) continue;
for (int scan_x = -radius_int; scan_x < radius_int + 1; scan_x++){
if (coor_x_int + scan_x < 0 || coor_x_int + scan_x >= W) continue;
float weight = exp(-(scan_x * scan_x + scan_y * scan_y) / (2 * sigma * sigma)); // force convert float sigma
float eps = 0.0000001;
if (weight < eps) weight = 0;
float *w_addr = heatmap + (coor_y_int + scan_y) * W + (coor_x_int + scan_x);
float old_weight = atomicExch(w_addr, weight);
if (old_weight > weight) weight = atomicExch(w_addr, old_weight);
}
}
int obj_idx = atomicAdd(gt_cnt, 1);
if (obj_idx >= max_objs) return;
gt_ind[obj_idx] = coor_y_int * W + coor_x_int;
gt_mask[obj_idx] = 1;
gt_cat[obj_idx] = cls_idx + 1; // begin from 1
gt_box_encoding[obj_idx * code_size + 0] = coor_x - coor_x_int;
gt_box_encoding[obj_idx * code_size + 1] = coor_y - coor_y_int;
gt_box_encoding[obj_idx * code_size + 2] = z;
gt_box_encoding[obj_idx * code_size + 3] = origin_dx;
gt_box_encoding[obj_idx * code_size + 4] = origin_dy;
gt_box_encoding[obj_idx * code_size + 5] = origin_dz;
gt_box_encoding[obj_idx * code_size + 6] = sin(rot);
gt_box_encoding[obj_idx * code_size + 7] = cos(rot);
if (code_size == 10) {
gt_box_encoding[obj_idx * code_size + 8] = vel_x;
gt_box_encoding[obj_idx * code_size + 9] = vel_y;
}
return;
}
void draw_center_kernel_launcher(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
cudaError_t err;
dim3 blocks(batch_size);
dim3 threads(THREADS_PER_BLOCK);
draw_center_kernel<<<blocks, threads>>>(batch_size, max_boxes, max_objs, num_cls, H, W, code_size, min_radius,
voxel_x, voxel_y, range_x, range_y, out_factor, gaussian_overlap,
gt_boxes, heatmap, gt_ind, gt_mask, gt_cat, gt_box_encoding, gt_cnt);
err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
exit(-1);
}
#ifdef DEBUG
cudaDeviceSynchronize(); // for using printf in kernel function
#endif
} | /*
Center assignments
Written by Jiageng Mao
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))
__device__ float limit_period(float val, float offset, float period){
float rval = val - floor(val / period + offset) * period;
return rval;
}
__device__ float gaussian_radius(float height, float width, float min_overlap){
float a1 = 1;
float b1 = (height + width);
float c1 = width * height * (1 - min_overlap) / (1 + min_overlap);
float sq1 = sqrt(b1 * b1 - 4 * a1 * c1);
float r1 = (b1 + sq1) / 2;
float a2 = 4;
float b2 = 2 * (height + width);
float c2 = (1 - min_overlap) * width * height;
float sq2 = sqrt(b2 * b2 - 4 * a2 * c2);
float r2 = (b2 + sq2) / 2;
float a3 = 4 * min_overlap;
float b3 = -2 * min_overlap * (height + width);
float c3 = (min_overlap - 1) * width * height;
float sq3 = sqrt(b3 * b3 - 4 * a3 * c3);
float r3 = (b3 + sq3) / 2;
return min(min(r1, r2), r3);
}
__global__ void draw_center_kernel(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
/*
Args:
gt_boxes: (B, max_boxes, 8 or 10) with class labels
heatmap: (B, num_cls, H, W)
gt_ind: (B, num_cls, max_objs)
gt_mask: (B, num_cls, max_objs)
gt_cat: (B, num_cls, max_objs)
gt_box_encoding: (B, num_cls, max_objs, code_size) sin/cos
gt_cnt: (B, num_cls)
*/
int bs_idx = blockIdx.x;
int box_idx = threadIdx.x;
if (bs_idx >= batch_size || box_idx >= max_boxes) return;
// move pointer
gt_boxes += bs_idx * max_boxes * code_size;
heatmap += bs_idx * num_cls * H * W;
gt_ind += bs_idx * num_cls * max_objs;
gt_mask += bs_idx * num_cls * max_objs;
gt_cat += bs_idx * num_cls * max_objs;
gt_box_encoding += bs_idx * num_cls * max_objs * code_size;
gt_cnt += bs_idx * num_cls;
// gt box parameters
float x = gt_boxes[box_idx * code_size + 0];
float y = gt_boxes[box_idx * code_size + 1];
float z = gt_boxes[box_idx * code_size + 2];
float dx = gt_boxes[box_idx * code_size + 3];
float dy = gt_boxes[box_idx * code_size + 4];
float dz = gt_boxes[box_idx * code_size + 5];
// origin dx/dy/dz is for box_encodings
float origin_dx = gt_boxes[box_idx * code_size + 3];
float origin_dy = gt_boxes[box_idx * code_size + 4];
float origin_dz = gt_boxes[box_idx * code_size + 5];
float rot = gt_boxes[box_idx * code_size + 6];
float vel_x = 0;
float vel_y = 0;
float cls = 0;
if (code_size == 10) {
vel_x = gt_boxes[box_idx * code_size + 7];
vel_y = gt_boxes[box_idx * code_size + 8];
cls = gt_boxes[box_idx * code_size + 9];
} else if (code_size == 8) {
cls = gt_boxes[box_idx * code_size + 7];
} else {
return;
}
// box not defined
if (dx == 0 || dy == 0 || dz == 0) return;
// cls begin from 1
int cls_idx = (int) cls - 1;
heatmap += cls_idx * H * W;
gt_ind += cls_idx * max_objs;
gt_mask += cls_idx * max_objs;
gt_cat += cls_idx * max_objs;
gt_box_encoding += cls_idx * max_objs * code_size;
gt_cnt += cls_idx;
// transform to bev map coords
float offset = 0.5;
float period = 6.283185307179586;
rot = limit_period(rot, offset, period);
dx = dx / voxel_x / out_factor;
dy = dy / voxel_y / out_factor;
float radius = gaussian_radius(dy, dx, gaussian_overlap);
int radius_int = max(min_radius, (int) radius);
float coor_x = (x - range_x) / voxel_x / out_factor;
float coor_y = (y - range_y) / voxel_y / out_factor;
int coor_x_int = (int) coor_x;
int coor_y_int = (int) coor_y;
if (coor_x_int >= W || coor_x_int < 0) return;
if (coor_y_int >= H || coor_y_int < 0) return;
// draw gaussian map
float div_factor = 6.0;
float sigma = (2 * radius_int + 1) / div_factor;
for (int scan_y = -radius_int; scan_y < radius_int + 1; scan_y++){
if (coor_y_int + scan_y < 0 || coor_y_int + scan_y >= H) continue;
for (int scan_x = -radius_int; scan_x < radius_int + 1; scan_x++){
if (coor_x_int + scan_x < 0 || coor_x_int + scan_x >= W) continue;
float weight = exp(-(scan_x * scan_x + scan_y * scan_y) / (2 * sigma * sigma)); // force convert float sigma
float eps = 0.0000001;
if (weight < eps) weight = 0;
float *w_addr = heatmap + (coor_y_int + scan_y) * W + (coor_x_int + scan_x);
float old_weight = atomicExch(w_addr, weight);
if (old_weight > weight) weight = atomicExch(w_addr, old_weight);
}
}
int obj_idx = atomicAdd(gt_cnt, 1);
if (obj_idx >= max_objs) return;
gt_ind[obj_idx] = coor_y_int * W + coor_x_int;
gt_mask[obj_idx] = 1;
gt_cat[obj_idx] = cls_idx + 1; // begin from 1
gt_box_encoding[obj_idx * code_size + 0] = coor_x - coor_x_int;
gt_box_encoding[obj_idx * code_size + 1] = coor_y - coor_y_int;
gt_box_encoding[obj_idx * code_size + 2] = z;
gt_box_encoding[obj_idx * code_size + 3] = origin_dx;
gt_box_encoding[obj_idx * code_size + 4] = origin_dy;
gt_box_encoding[obj_idx * code_size + 5] = origin_dz;
gt_box_encoding[obj_idx * code_size + 6] = sin(rot);
gt_box_encoding[obj_idx * code_size + 7] = cos(rot);
if (code_size == 10) {
gt_box_encoding[obj_idx * code_size + 8] = vel_x;
gt_box_encoding[obj_idx * code_size + 9] = vel_y;
}
return;
}
void draw_center_kernel_launcher(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
hipError_t err;
dim3 blocks(batch_size);
dim3 threads(THREADS_PER_BLOCK);
draw_center_kernel<<<blocks, threads>>>(batch_size, max_boxes, max_objs, num_cls, H, W, code_size, min_radius,
voxel_x, voxel_y, range_x, range_y, out_factor, gaussian_overlap,
gt_boxes, heatmap, gt_ind, gt_mask, gt_cat, gt_box_encoding, gt_cnt);
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
#ifdef DEBUG
hipDeviceSynchronize(); // for using printf in kernel function
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Center assignments
Written by Jiageng Mao
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define THREADS_PER_BLOCK 256
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))
__device__ float limit_period(float val, float offset, float period){
float rval = val - floor(val / period + offset) * period;
return rval;
}
__device__ float gaussian_radius(float height, float width, float min_overlap){
float a1 = 1;
float b1 = (height + width);
float c1 = width * height * (1 - min_overlap) / (1 + min_overlap);
float sq1 = sqrt(b1 * b1 - 4 * a1 * c1);
float r1 = (b1 + sq1) / 2;
float a2 = 4;
float b2 = 2 * (height + width);
float c2 = (1 - min_overlap) * width * height;
float sq2 = sqrt(b2 * b2 - 4 * a2 * c2);
float r2 = (b2 + sq2) / 2;
float a3 = 4 * min_overlap;
float b3 = -2 * min_overlap * (height + width);
float c3 = (min_overlap - 1) * width * height;
float sq3 = sqrt(b3 * b3 - 4 * a3 * c3);
float r3 = (b3 + sq3) / 2;
return min(min(r1, r2), r3);
}
__global__ void draw_center_kernel(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
/*
Args:
gt_boxes: (B, max_boxes, 8 or 10) with class labels
heatmap: (B, num_cls, H, W)
gt_ind: (B, num_cls, max_objs)
gt_mask: (B, num_cls, max_objs)
gt_cat: (B, num_cls, max_objs)
gt_box_encoding: (B, num_cls, max_objs, code_size) sin/cos
gt_cnt: (B, num_cls)
*/
int bs_idx = blockIdx.x;
int box_idx = threadIdx.x;
if (bs_idx >= batch_size || box_idx >= max_boxes) return;
// move pointer
gt_boxes += bs_idx * max_boxes * code_size;
heatmap += bs_idx * num_cls * H * W;
gt_ind += bs_idx * num_cls * max_objs;
gt_mask += bs_idx * num_cls * max_objs;
gt_cat += bs_idx * num_cls * max_objs;
gt_box_encoding += bs_idx * num_cls * max_objs * code_size;
gt_cnt += bs_idx * num_cls;
// gt box parameters
float x = gt_boxes[box_idx * code_size + 0];
float y = gt_boxes[box_idx * code_size + 1];
float z = gt_boxes[box_idx * code_size + 2];
float dx = gt_boxes[box_idx * code_size + 3];
float dy = gt_boxes[box_idx * code_size + 4];
float dz = gt_boxes[box_idx * code_size + 5];
// origin dx/dy/dz is for box_encodings
float origin_dx = gt_boxes[box_idx * code_size + 3];
float origin_dy = gt_boxes[box_idx * code_size + 4];
float origin_dz = gt_boxes[box_idx * code_size + 5];
float rot = gt_boxes[box_idx * code_size + 6];
float vel_x = 0;
float vel_y = 0;
float cls = 0;
if (code_size == 10) {
vel_x = gt_boxes[box_idx * code_size + 7];
vel_y = gt_boxes[box_idx * code_size + 8];
cls = gt_boxes[box_idx * code_size + 9];
} else if (code_size == 8) {
cls = gt_boxes[box_idx * code_size + 7];
} else {
return;
}
// box not defined
if (dx == 0 || dy == 0 || dz == 0) return;
// cls begin from 1
int cls_idx = (int) cls - 1;
heatmap += cls_idx * H * W;
gt_ind += cls_idx * max_objs;
gt_mask += cls_idx * max_objs;
gt_cat += cls_idx * max_objs;
gt_box_encoding += cls_idx * max_objs * code_size;
gt_cnt += cls_idx;
// transform to bev map coords
float offset = 0.5;
float period = 6.283185307179586;
rot = limit_period(rot, offset, period);
dx = dx / voxel_x / out_factor;
dy = dy / voxel_y / out_factor;
float radius = gaussian_radius(dy, dx, gaussian_overlap);
int radius_int = max(min_radius, (int) radius);
float coor_x = (x - range_x) / voxel_x / out_factor;
float coor_y = (y - range_y) / voxel_y / out_factor;
int coor_x_int = (int) coor_x;
int coor_y_int = (int) coor_y;
if (coor_x_int >= W || coor_x_int < 0) return;
if (coor_y_int >= H || coor_y_int < 0) return;
// draw gaussian map
float div_factor = 6.0;
float sigma = (2 * radius_int + 1) / div_factor;
for (int scan_y = -radius_int; scan_y < radius_int + 1; scan_y++){
if (coor_y_int + scan_y < 0 || coor_y_int + scan_y >= H) continue;
for (int scan_x = -radius_int; scan_x < radius_int + 1; scan_x++){
if (coor_x_int + scan_x < 0 || coor_x_int + scan_x >= W) continue;
float weight = exp(-(scan_x * scan_x + scan_y * scan_y) / (2 * sigma * sigma)); // force convert float sigma
float eps = 0.0000001;
if (weight < eps) weight = 0;
float *w_addr = heatmap + (coor_y_int + scan_y) * W + (coor_x_int + scan_x);
float old_weight = atomicExch(w_addr, weight);
if (old_weight > weight) weight = atomicExch(w_addr, old_weight);
}
}
int obj_idx = atomicAdd(gt_cnt, 1);
if (obj_idx >= max_objs) return;
gt_ind[obj_idx] = coor_y_int * W + coor_x_int;
gt_mask[obj_idx] = 1;
gt_cat[obj_idx] = cls_idx + 1; // begin from 1
gt_box_encoding[obj_idx * code_size + 0] = coor_x - coor_x_int;
gt_box_encoding[obj_idx * code_size + 1] = coor_y - coor_y_int;
gt_box_encoding[obj_idx * code_size + 2] = z;
gt_box_encoding[obj_idx * code_size + 3] = origin_dx;
gt_box_encoding[obj_idx * code_size + 4] = origin_dy;
gt_box_encoding[obj_idx * code_size + 5] = origin_dz;
gt_box_encoding[obj_idx * code_size + 6] = sin(rot);
gt_box_encoding[obj_idx * code_size + 7] = cos(rot);
if (code_size == 10) {
gt_box_encoding[obj_idx * code_size + 8] = vel_x;
gt_box_encoding[obj_idx * code_size + 9] = vel_y;
}
return;
}
void draw_center_kernel_launcher(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
hipError_t err;
dim3 blocks(batch_size);
dim3 threads(THREADS_PER_BLOCK);
draw_center_kernel<<<blocks, threads>>>(batch_size, max_boxes, max_objs, num_cls, H, W, code_size, min_radius,
voxel_x, voxel_y, range_x, range_y, out_factor, gaussian_overlap,
gt_boxes, heatmap, gt_ind, gt_mask, gt_cat, gt_box_encoding, gt_cnt);
err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
exit(-1);
}
#ifdef DEBUG
hipDeviceSynchronize(); // for using printf in kernel function
#endif
} | .text
.file "draw_center_kernel.hip"
.globl _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ # -- Begin function _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.p2align 4, 0x90
.type _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: # @_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 272(%rsp), %rax
movq %rax, 144(%rsp)
leaq 280(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
leaq 336(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end0-_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_endproc
# -- End function
.globl _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ # -- Begin function _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.p2align 4, 0x90
.type _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: # @_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm5, 20(%rsp) # 4-byte Spill
movss %xmm4, 16(%rsp) # 4-byte Spill
movss %xmm3, 12(%rsp) # 4-byte Spill
movss %xmm2, 8(%rsp) # 4-byte Spill
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl 88(%rsp), %r10d
movl 80(%rsp), %eax
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl %r13d, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
movl %ebp, %r8d
movl %ebx, %r9d
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 28(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
addq $80, %rsp
.cfi_adjust_cfa_offset -80
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end1-_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@object # @_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.section .rodata,"a",@progbits
.globl _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.p2align 3, 0x0
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.quad _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.size _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : %s\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000336d3_00000000-6_draw_center_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12limit_periodfff
.type _Z12limit_periodfff, @function
_Z12limit_periodfff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12limit_periodfff, .-_Z12limit_periodfff
.globl _Z15gaussian_radiusfff
.type _Z15gaussian_radiusfff, @function
_Z15gaussian_radiusfff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z15gaussian_radiusfff, .-_Z15gaussian_radiusfff
.globl _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.type _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2084:
.cfi_startproc
endbr64
subq $360, %rsp
.cfi_def_cfa_offset 368
movl %edi, 108(%rsp)
movl %esi, 104(%rsp)
movl %edx, 100(%rsp)
movl %ecx, 96(%rsp)
movl %r8d, 92(%rsp)
movl %r9d, 88(%rsp)
movss %xmm0, 84(%rsp)
movss %xmm1, 80(%rsp)
movss %xmm2, 76(%rsp)
movss %xmm3, 72(%rsp)
movss %xmm4, 68(%rsp)
movss %xmm5, 64(%rsp)
movq 384(%rsp), %rax
movq %rax, 56(%rsp)
movq 392(%rsp), %rax
movq %rax, 48(%rsp)
movq 400(%rsp), %rax
movq %rax, 40(%rsp)
movq 408(%rsp), %rax
movq %rax, 32(%rsp)
movq 416(%rsp), %rax
movq %rax, 24(%rsp)
movq 424(%rsp), %rax
movq %rax, 16(%rsp)
movq 432(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 100(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 92(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 84(%rsp), %rax
movq %rax, 240(%rsp)
leaq 80(%rsp), %rax
movq %rax, 248(%rsp)
leaq 76(%rsp), %rax
movq %rax, 256(%rsp)
leaq 72(%rsp), %rax
movq %rax, 264(%rsp)
leaq 68(%rsp), %rax
movq %rax, 272(%rsp)
leaq 64(%rsp), %rax
movq %rax, 280(%rsp)
leaq 56(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 32(%rsp), %rax
movq %rax, 312(%rsp)
leaq 24(%rsp), %rax
movq %rax, 320(%rsp)
leaq 16(%rsp), %rax
movq %rax, 328(%rsp)
leaq 8(%rsp), %rax
movq %rax, 336(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 376
pushq 120(%rsp)
.cfi_def_cfa_offset 384
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.globl _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.type _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA kernel failed : %s\n"
.text
.globl _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.type _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 28(%rsp)
movl %edi, 40(%rsp)
movl $1, 44(%rsp)
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 200(%rsp)
.cfi_def_cfa_offset 144
pushq 200(%rsp)
.cfi_def_cfa_offset 152
pushq 200(%rsp)
.cfi_def_cfa_offset 160
pushq 200(%rsp)
.cfi_def_cfa_offset 168
pushq 200(%rsp)
.cfi_def_cfa_offset 176
pushq 200(%rsp)
.cfi_def_cfa_offset 184
pushq 200(%rsp)
.cfi_def_cfa_offset 192
movl 200(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 200
movl 200(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 208
movss 108(%rsp), %xmm5
movss 104(%rsp), %xmm4
movss 100(%rsp), %xmm3
movss 96(%rsp), %xmm2
movss 92(%rsp), %xmm1
movss 88(%rsp), %xmm0
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
addq $80, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "draw_center_kernel.hip"
.globl _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ # -- Begin function _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.p2align 4, 0x90
.type _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: # @_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 272(%rsp), %rax
movq %rax, 144(%rsp)
leaq 280(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
leaq 336(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end0-_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_endproc
# -- End function
.globl _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ # -- Begin function _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.p2align 4, 0x90
.type _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: # @_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm5, 20(%rsp) # 4-byte Spill
movss %xmm4, 16(%rsp) # 4-byte Spill
movss %xmm3, 12(%rsp) # 4-byte Spill
movss %xmm2, 8(%rsp) # 4-byte Spill
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl 88(%rsp), %r10d
movl 80(%rsp), %eax
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl %r13d, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
movl %ebp, %r8d
movl %ebx, %r9d
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 28(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
addq $80, %rsp
.cfi_adjust_cfa_offset -80
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end1-_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@object # @_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.section .rodata,"a",@progbits
.globl _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.p2align 3, 0x0
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.quad _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.size _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : %s\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
//Tamaño de matrices (cuadradas)
#define N 1024
//Kernel
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
//TODO -> Calcular elemento C(i,j)
}
int main(){
struct timeval t1, t2;
int *hA, *hB, *hC, *hC2; //Host Matrix
int *dA, *dB, *dC; //Device Matrix
//Reserva de memoria Host
hA = (int*)malloc(N*N*sizeof(int));
hB = (int*)malloc(N*N*sizeof(int));
hC = (int*)malloc(N*N*sizeof(int));
hC2 = (int*)malloc(N*N*sizeof(int));
//Inicialización de matrices
srand(time(NULL));
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
hA[i*N+j] = rand();
hB[i*N+j] = rand();
}
}
//Reserva de memoria GPU
//TODO -> Reservar Memoria (dA, dB, dC)
//Copia Host -> GPU
//TODO -> Copiar hA a dA y hB a dB
gettimeofday(&t1, 0);
//Ejecución Kernel
mul<<<N, N>>>(dA, dB, dC);
cudaDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia Device -> Host
//TODO -> Copiar dC a hC
//Multiplicación en Host
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
hC2[i*N + j] = 0;
for(int k = 0; k < N; k++){
hC2[i*N + j] += hA[i*N + k] * hB[k*N + j];
}
}
}
//Comprobación de errores
bool error = false;
for(int i = 0; i < N*N; i++){
if(hC[i] != hC2[i]){
error = true;
break;
}
}
if(error)
printf("La multiplicación de matrices ha fallado.\n");
else
printf("Multiplicación de matrices correcta.\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
//Liberar memoria
free(hA);
free(hB);
free(hC);
//TODO -> Liberar dA, dB y dC
} | code for sm_80
Function : _Z3mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.