system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "error.h"
#include <cuda.h>
#include <curand_kernel.h>
#include <cassert>
#include <iostream>
#include <string>
namespace
{
const char* curandGetErrorString(const curandStatus_t error)
{
switch (error)
{
case CURAND_STATUS_SUCCESS:
return "CURAND_STATUS_SUCCESS";
case CURAND_STATUS_VERSION_MISMATCH:
return "CURAND_STATUS_VERSION_MISMATCH";
case CURAND_STATUS_NOT_INITIALIZED:
return "CURAND_STATUS_NOT_INITIALIZED";
case CURAND_STATUS_ALLOCATION_FAILED:
return "CURAND_STATUS_ALLOCATION_FAILED";
case CURAND_STATUS_TYPE_ERROR:
return "CURAND_STATUS_TYPE_ERROR";
case CURAND_STATUS_OUT_OF_RANGE:
return "CURAND_STATUS_OUT_OF_RANGE";
case CURAND_STATUS_LENGTH_NOT_MULTIPLE:
return "CURAND_STATUS_LENGTH_NOT_MULTIPLE";
case CURAND_STATUS_DOUBLE_PRECISION_REQUIRED:
return "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED";
case CURAND_STATUS_LAUNCH_FAILURE:
return "CURAND_STATUS_LAUNCH_FAILURE";
case CURAND_STATUS_PREEXISTING_FAILURE:
return "CURAND_STATUS_PREEXISTING_FAILURE";
case CURAND_STATUS_INITIALIZATION_FAILED:
return "CURAND_STATUS_INITIALIZATION_FAILED";
case CURAND_STATUS_ARCH_MISMATCH:
return "CURAND_STATUS_ARCH_MISMATCH";
case CURAND_STATUS_INTERNAL_ERROR:
return "CURAND_STATUS_INTERNAL_ERROR";
}
return "<unknown>";
}
}
namespace cutw
{
void
cuassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != cudaSuccess)
{
std::string msg = "cutw: cuassert: ";
msg += cudaGetErrorString(static_cast<cudaError_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
void
curandassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != CURAND_STATUS_SUCCESS)
{
std::string msg = "cutw: curandassert: ";
msg += curandGetErrorString(static_cast<curandStatus_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
} | #include "error.h"
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <cassert>
#include <iostream>
#include <string>
namespace
{
const char* curandGetErrorString(const hiprandStatus_t error)
{
switch (error)
{
case HIPRAND_STATUS_SUCCESS:
return "CURAND_STATUS_SUCCESS";
case HIPRAND_STATUS_VERSION_MISMATCH:
return "CURAND_STATUS_VERSION_MISMATCH";
case HIPRAND_STATUS_NOT_INITIALIZED:
return "CURAND_STATUS_NOT_INITIALIZED";
case HIPRAND_STATUS_ALLOCATION_FAILED:
return "CURAND_STATUS_ALLOCATION_FAILED";
case HIPRAND_STATUS_TYPE_ERROR:
return "CURAND_STATUS_TYPE_ERROR";
case HIPRAND_STATUS_OUT_OF_RANGE:
return "CURAND_STATUS_OUT_OF_RANGE";
case HIPRAND_STATUS_LENGTH_NOT_MULTIPLE:
return "CURAND_STATUS_LENGTH_NOT_MULTIPLE";
case HIPRAND_STATUS_DOUBLE_PRECISION_REQUIRED:
return "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED";
case HIPRAND_STATUS_LAUNCH_FAILURE:
return "CURAND_STATUS_LAUNCH_FAILURE";
case HIPRAND_STATUS_PREEXISTING_FAILURE:
return "CURAND_STATUS_PREEXISTING_FAILURE";
case HIPRAND_STATUS_INITIALIZATION_FAILED:
return "CURAND_STATUS_INITIALIZATION_FAILED";
case HIPRAND_STATUS_ARCH_MISMATCH:
return "CURAND_STATUS_ARCH_MISMATCH";
case HIPRAND_STATUS_INTERNAL_ERROR:
return "CURAND_STATUS_INTERNAL_ERROR";
}
return "<unknown>";
}
}
namespace cutw
{
void
cuassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != hipSuccess)
{
std::string msg = "cutw: cuassert: ";
msg += hipGetErrorString(static_cast<hipError_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
void
curandassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != HIPRAND_STATUS_SUCCESS)
{
std::string msg = "cutw: curandassert: ";
msg += curandGetErrorString(static_cast<hiprandStatus_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "error.h"
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <cassert>
#include <iostream>
#include <string>
namespace
{
const char* curandGetErrorString(const hiprandStatus_t error)
{
switch (error)
{
case HIPRAND_STATUS_SUCCESS:
return "CURAND_STATUS_SUCCESS";
case HIPRAND_STATUS_VERSION_MISMATCH:
return "CURAND_STATUS_VERSION_MISMATCH";
case HIPRAND_STATUS_NOT_INITIALIZED:
return "CURAND_STATUS_NOT_INITIALIZED";
case HIPRAND_STATUS_ALLOCATION_FAILED:
return "CURAND_STATUS_ALLOCATION_FAILED";
case HIPRAND_STATUS_TYPE_ERROR:
return "CURAND_STATUS_TYPE_ERROR";
case HIPRAND_STATUS_OUT_OF_RANGE:
return "CURAND_STATUS_OUT_OF_RANGE";
case HIPRAND_STATUS_LENGTH_NOT_MULTIPLE:
return "CURAND_STATUS_LENGTH_NOT_MULTIPLE";
case HIPRAND_STATUS_DOUBLE_PRECISION_REQUIRED:
return "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED";
case HIPRAND_STATUS_LAUNCH_FAILURE:
return "CURAND_STATUS_LAUNCH_FAILURE";
case HIPRAND_STATUS_PREEXISTING_FAILURE:
return "CURAND_STATUS_PREEXISTING_FAILURE";
case HIPRAND_STATUS_INITIALIZATION_FAILED:
return "CURAND_STATUS_INITIALIZATION_FAILED";
case HIPRAND_STATUS_ARCH_MISMATCH:
return "CURAND_STATUS_ARCH_MISMATCH";
case HIPRAND_STATUS_INTERNAL_ERROR:
return "CURAND_STATUS_INTERNAL_ERROR";
}
return "<unknown>";
}
}
namespace cutw
{
void
cuassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != hipSuccess)
{
std::string msg = "cutw: cuassert: ";
msg += hipGetErrorString(static_cast<hipError_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
void
curandassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != HIPRAND_STATUS_SUCCESS)
{
std::string msg = "cutw: curandassert: ";
msg += curandGetErrorString(static_cast<hiprandStatus_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "error.h"
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <cassert>
#include <iostream>
#include <string>
namespace
{
const char* curandGetErrorString(const hiprandStatus_t error)
{
switch (error)
{
case HIPRAND_STATUS_SUCCESS:
return "CURAND_STATUS_SUCCESS";
case HIPRAND_STATUS_VERSION_MISMATCH:
return "CURAND_STATUS_VERSION_MISMATCH";
case HIPRAND_STATUS_NOT_INITIALIZED:
return "CURAND_STATUS_NOT_INITIALIZED";
case HIPRAND_STATUS_ALLOCATION_FAILED:
return "CURAND_STATUS_ALLOCATION_FAILED";
case HIPRAND_STATUS_TYPE_ERROR:
return "CURAND_STATUS_TYPE_ERROR";
case HIPRAND_STATUS_OUT_OF_RANGE:
return "CURAND_STATUS_OUT_OF_RANGE";
case HIPRAND_STATUS_LENGTH_NOT_MULTIPLE:
return "CURAND_STATUS_LENGTH_NOT_MULTIPLE";
case HIPRAND_STATUS_DOUBLE_PRECISION_REQUIRED:
return "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED";
case HIPRAND_STATUS_LAUNCH_FAILURE:
return "CURAND_STATUS_LAUNCH_FAILURE";
case HIPRAND_STATUS_PREEXISTING_FAILURE:
return "CURAND_STATUS_PREEXISTING_FAILURE";
case HIPRAND_STATUS_INITIALIZATION_FAILED:
return "CURAND_STATUS_INITIALIZATION_FAILED";
case HIPRAND_STATUS_ARCH_MISMATCH:
return "CURAND_STATUS_ARCH_MISMATCH";
case HIPRAND_STATUS_INTERNAL_ERROR:
return "CURAND_STATUS_INTERNAL_ERROR";
}
return "<unknown>";
}
}
namespace cutw
{
void
cuassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != hipSuccess)
{
std::string msg = "cutw: cuassert: ";
msg += hipGetErrorString(static_cast<hipError_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
void
curandassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != HIPRAND_STATUS_SUCCESS)
{
std::string msg = "cutw: curandassert: ";
msg += curandGetErrorString(static_cast<hiprandStatus_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
} | .text
.file "error.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _ZN4cutw8cuassertEiPKcib # -- Begin function _ZN4cutw8cuassertEiPKcib
.p2align 4, 0x90
.type _ZN4cutw8cuassertEiPKcib,@function
_ZN4cutw8cuassertEiPKcib: # @_ZN4cutw8cuassertEiPKcib
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
je .LBB0_87
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movl %edx, %r14d
movq %rsi, %r15
movl %edi, %ebp
movl %ecx, 36(%rsp) # 4-byte Spill
leaq 16(%rsp), %r13
movq %r13, (%rsp)
movl $17, %edi
callq _Znwm
movq %rax, (%rsp)
movq $16, 16(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movq $16, 8(%rsp)
movb $0, 16(%rax)
.Ltmp0:
movl %ebp, %edi
callq hipGetErrorString
.Ltmp1:
# %bb.2:
movq %rax, %r12
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
movq %rax, %rdi
callq strlen
movq 8(%rsp), %rsi
movq %rbp, %rcx
subq %rsi, %rcx
cmpq %rax, %rcx
jb .LBB0_27
# %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
leaq (%rsi,%rax), %rbx
movq (%rsp), %rdi
movl $15, %ecx
cmpq %r13, %rdi
je .LBB0_5
# %bb.4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
movq 16(%rsp), %rcx
.LBB0_5: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
cmpq %rcx, %rbx
jbe .LBB0_6
# %bb.10:
.Ltmp2:
movq %rsp, %rdi
xorl %edx, %edx
movq %r12, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp3:
jmp .LBB0_11
.LBB0_6:
testq %rax, %rax
je .LBB0_11
# %bb.7:
addq %rsi, %rdi
cmpq $1, %rax
jne .LBB0_9
# %bb.8:
movzbl (%r12), %eax
movb %al, (%rdi)
jmp .LBB0_11
.LBB0_9:
movq %r12, %rsi
movq %rax, %rdx
callq memcpy@PLT
.LBB0_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq 8(%rsp), %rsi
leaq -3(%rbp), %rax
cmpq %rax, %rsi
jg .LBB0_27
# %bb.12: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i15
leaq 3(%rsi), %rbx
movq (%rsp), %rax
movl $15, %ecx
cmpq %r13, %rax
je .LBB0_14
# %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i15
movq 16(%rsp), %rcx
.LBB0_14: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i15
cmpq %rcx, %rbx
jbe .LBB0_15
# %bb.16:
.Ltmp4:
movq %rsp, %rdi
movl $.L.str.1, %ecx
movl $3, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp5:
jmp .LBB0_17
.LBB0_15:
movb $32, 2(%rax,%rsi)
movw $16416, (%rax,%rsi) # imm = 0x4020
.LBB0_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit22
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq %r15, %rdi
callq strlen
movq 8(%rsp), %rsi
movq %rbp, %rcx
subq %rsi, %rcx
cmpq %rax, %rcx
jb .LBB0_27
# %bb.18: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i23
leaq (%rsi,%rax), %rbx
movq (%rsp), %rdi
movl $15, %ecx
cmpq %r13, %rdi
je .LBB0_20
# %bb.19: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i23
movq 16(%rsp), %rcx
.LBB0_20: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i23
cmpq %rcx, %rbx
jbe .LBB0_21
# %bb.25:
.Ltmp6:
movq %rsp, %rdi
xorl %edx, %edx
movq %r15, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp7:
jmp .LBB0_26
.LBB0_21:
testq %rax, %rax
je .LBB0_26
# %bb.22:
addq %rsi, %rdi
cmpq $1, %rax
jne .LBB0_24
# %bb.23:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB0_26
.LBB0_24:
movq %r15, %rsi
movq %rax, %rdx
callq memcpy@PLT
.LBB0_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit30
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq 8(%rsp), %rsi
cmpq %rbp, %rsi
je .LBB0_27
# %bb.29: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i31
leaq 1(%rsi), %rbx
movq (%rsp), %rax
movl $15, %ecx
cmpq %r13, %rax
je .LBB0_31
# %bb.30: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i31
movq 16(%rsp), %rcx
.LBB0_31: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i31
cmpq %rcx, %rbx
jbe .LBB0_32
# %bb.33:
.Ltmp8:
movq %rsp, %rdi
movl $.L.str.2, %ecx
movl $1, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp9:
jmp .LBB0_34
.LBB0_32:
movb $58, (%rax,%rsi)
.LBB0_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit38
movq %r13, %r12
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movl %r14d, %ebx
negl %ebx
cmovsl %r14d, %ebx
movl $1, %r13d
cmpl $10, %ebx
jb .LBB0_43
# %bb.35: # %.lr.ph.i.i.preheader
movl $4, %r13d
movl $3518437209, %eax # imm = 0xD1B71759
movl %ebx, %ecx
.p2align 4, 0x90
.LBB0_36: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
cmpl $99, %ecx
jbe .LBB0_37
# %bb.38: # in Loop: Header=BB0_36 Depth=1
cmpl $999, %ecx # imm = 0x3E7
jbe .LBB0_39
# %bb.40: # in Loop: Header=BB0_36 Depth=1
cmpl $10000, %ecx # imm = 0x2710
jb .LBB0_43
# %bb.41: # in Loop: Header=BB0_36 Depth=1
movl %ecx, %edx
imulq %rax, %rdx
shrq $45, %rdx
addl $4, %r13d
cmpl $99999, %ecx # imm = 0x1869F
movl %edx, %ecx
ja .LBB0_36
# %bb.42: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i.loopexit
addl $-3, %r13d
jmp .LBB0_43
.LBB0_37:
addl $-2, %r13d
jmp .LBB0_43
.LBB0_39:
decl %r13d
.LBB0_43: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i
shrl $31, %r14d
leal (%r14,%r13), %r15d
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
cmpl $16, %r15d
jb .LBB0_46
# %bb.44:
leaq 1(%r15), %rdi
.Ltmp10:
callq _Znwm
.Ltmp11:
# %bb.45: # %.noexc.i41
movq %rax, 40(%rsp)
movq %r15, 56(%rsp)
.LBB0_46:
testq %r15, %r15
je .LBB0_50
# %bb.47:
movq 40(%rsp), %rdi
cmpl $1, %r15d
jne .LBB0_49
# %bb.48:
movb $45, (%rdi)
jmp .LBB0_50
.LBB0_49:
movl $45, %esi
movq %r15, %rdx
callq memset@PLT
.LBB0_50: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit.i
movq %r15, 48(%rsp)
movq 40(%rsp), %rax
movb $0, (%rax,%r15)
movl %r14d, %eax
addq 40(%rsp), %rax
cmpl $100, %ebx
jb .LBB0_51
# %bb.52: # %.lr.ph.preheader.i.i
addl $-2, %r13d
.p2align 4, 0x90
.LBB0_53: # %.lr.ph.i11.i
# =>This Inner Loop Header: Depth=1
leal 1(%r13), %edx
movl %ebx, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %esi
movl %ebx, %edi
subl %esi, %edi
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdi,%rdi), %esi
movb %sil, (%rax,%rdx)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rdi,%rdi), %edx
movl %r13d, %esi
movb %dl, (%rax,%rsi)
addl $-2, %r13d
cmpl $9999, %ebx # imm = 0x270F
movl %ecx, %ebx
ja .LBB0_53
# %bb.54: # %._crit_edge.i.i
cmpl $10, %ecx
jb .LBB0_57
.LBB0_55:
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB0_58
.LBB0_51:
movl %ebx, %ecx
cmpl $10, %ecx
jae .LBB0_55
.LBB0_57:
orb $48, %cl
.LBB0_58: # %_ZNSt7__cxx119to_stringEi.exit
movq %r12, %r13
movb %cl, (%rax)
movq 48(%rsp), %r8
movq 8(%rsp), %rsi
subq %rsi, %rbp
cmpq %r8, %rbp
jb .LBB0_59
# %bb.61: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
leaq (%rsi,%r8), %rbx
movq (%rsp), %rdi
movl $15, %eax
cmpq %r13, %rdi
je .LBB0_63
# %bb.62: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
movq 16(%rsp), %rax
.LBB0_63: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
movq 40(%rsp), %rcx
cmpq %rax, %rbx
jbe .LBB0_64
# %bb.68:
.Ltmp13:
movq %rsp, %rdi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp14:
jmp .LBB0_69
.LBB0_64:
testq %r8, %r8
je .LBB0_69
# %bb.65:
addq %rsi, %rdi
cmpq $1, %r8
jne .LBB0_67
# %bb.66:
movzbl (%rcx), %eax
movb %al, (%rdi)
jmp .LBB0_69
.LBB0_67:
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.LBB0_69: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLERKS4_.exit
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_71
# %bb.70: # %.critedge.i.i
callq _ZdlPv
.LBB0_71: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp15:
movl $_ZSt4cerr, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
# %bb.72: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_73
# %bb.75: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_77
# %bb.76:
movzbl 67(%r15), %eax
jmp .LBB0_79
.LBB0_77:
.Ltmp17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp18:
# %bb.78: # %.noexc57
movq (%r15), %rax
.Ltmp19:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp20:
.LBB0_79: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp21:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp22:
# %bb.80: # %.noexc59
.Ltmp23:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp24:
# %bb.81: # %_ZNSolsEPFRSoS_E.exit
cmpb $0, 36(%rsp) # 1-byte Folded Reload
jne .LBB0_82
# %bb.85:
movq (%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_87
# %bb.86: # %.critedge.i.i49
callq _ZdlPv
.LBB0_87:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_27: # %.invoke
.cfi_def_cfa_offset 128
.Ltmp30:
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp31:
# %bb.28: # %.cont
.LBB0_59:
.Ltmp27:
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp28:
# %bb.60: # %.noexc42
.LBB0_73:
.Ltmp25:
callq _ZSt16__throw_bad_castv
.Ltmp26:
# %bb.74: # %.noexc56
.LBB0_82:
callq _ZSt9terminatev
.LBB0_56:
.Ltmp12:
movq %rax, %rdi
callq __clang_call_terminate
.LBB0_83:
.Ltmp29:
movq %rax, %rbx
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_89
# %bb.84: # %.critedge.i.i46
callq _ZdlPv
jmp .LBB0_89
.LBB0_88:
.Ltmp32:
movq %r13, %r12
movq %rax, %rbx
.LBB0_89:
movq (%rsp), %rdi
cmpq %r12, %rdi
je .LBB0_91
# %bb.90: # %.critedge.i.i52
callq _ZdlPv
.LBB0_91: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit54
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN4cutw8cuassertEiPKcib, .Lfunc_end0-_ZN4cutw8cuassertEiPKcib
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp4 # Call between .Ltmp4 and .Ltmp7
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp8-.Ltmp7 # Call between .Ltmp7 and .Ltmp8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 1 # On action: 1
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp13-.Ltmp11 # Call between .Ltmp11 and .Ltmp13
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp15 # Call between .Ltmp15 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Lfunc_end0-.Ltmp26 # Call between .Ltmp26 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _ZN4cutw12curandassertEiPKcib # -- Begin function _ZN4cutw12curandassertEiPKcib
.p2align 4, 0x90
.type _ZN4cutw12curandassertEiPKcib,@function
_ZN4cutw12curandassertEiPKcib: # @_ZN4cutw12curandassertEiPKcib
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
je .LBB1_102
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movl %edx, %r14d
movq %rsi, %r15
movl %edi, %r12d
movl %ecx, 36(%rsp) # 4-byte Spill
leaq 16(%rsp), %r13
movq %r13, (%rsp)
movl $21, %edi
callq _Znwm
movq %rax, (%rsp)
movq $20, 16(%rsp)
movups .L.str.3(%rip), %xmm0
movups %xmm0, (%rax)
movl $540701810, 16(%rax) # imm = 0x203A7472
movq $20, 8(%rsp)
movb $0, 20(%rax)
leal -100(%r12), %eax
cmpl $104, %eax
ja .LBB1_2
# %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
jmpq *.LJTI1_0(,%rax,8)
.LBB1_5:
movl $.L.str.8, %r12d
jmp .LBB1_17
.LBB1_2: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
cmpl $999, %r12d # imm = 0x3E7
jne .LBB1_16
# %bb.3:
movl $.L.str.19, %r12d
jmp .LBB1_17
.LBB1_16:
movl $.L.str.20, %r12d
jmp .LBB1_17
.LBB1_11:
movl $.L.str.14, %r12d
jmp .LBB1_17
.LBB1_10:
movl $.L.str.13, %r12d
jmp .LBB1_17
.LBB1_8:
movl $.L.str.11, %r12d
jmp .LBB1_17
.LBB1_7:
movl $.L.str.10, %r12d
jmp .LBB1_17
.LBB1_12:
movl $.L.str.15, %r12d
jmp .LBB1_17
.LBB1_9:
movl $.L.str.12, %r12d
jmp .LBB1_17
.LBB1_15:
movl $.L.str.18, %r12d
jmp .LBB1_17
.LBB1_6:
movl $.L.str.9, %r12d
jmp .LBB1_17
.LBB1_14:
movl $.L.str.17, %r12d
jmp .LBB1_17
.LBB1_13:
movl $.L.str.16, %r12d
.LBB1_17: # %_ZN12_GLOBAL__N_120curandGetErrorStringE13hiprandStatus.exit
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
movq %r12, %rdi
callq strlen
movq 8(%rsp), %rsi
movq %rbp, %rcx
subq %rsi, %rcx
cmpq %rax, %rcx
jb .LBB1_42
# %bb.18: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
leaq (%rsi,%rax), %rbx
movq (%rsp), %rdi
movl $15, %ecx
cmpq %r13, %rdi
je .LBB1_20
# %bb.19: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
movq 16(%rsp), %rcx
.LBB1_20: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
cmpq %rcx, %rbx
jbe .LBB1_21
# %bb.25:
.Ltmp33:
movq %rsp, %rdi
xorl %edx, %edx
movq %r12, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp34:
jmp .LBB1_26
.LBB1_21:
testq %rax, %rax
je .LBB1_26
# %bb.22:
addq %rsi, %rdi
cmpq $1, %rax
jne .LBB1_24
# %bb.23:
movzbl (%r12), %eax
movb %al, (%rdi)
jmp .LBB1_26
.LBB1_24:
movq %r12, %rsi
movq %rax, %rdx
callq memcpy@PLT
.LBB1_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq 8(%rsp), %rsi
leaq -3(%rbp), %rax
cmpq %rax, %rsi
jg .LBB1_42
# %bb.27: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i15
leaq 3(%rsi), %rbx
movq (%rsp), %rax
movl $15, %ecx
cmpq %r13, %rax
je .LBB1_29
# %bb.28: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i15
movq 16(%rsp), %rcx
.LBB1_29: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i15
cmpq %rcx, %rbx
jbe .LBB1_30
# %bb.31:
.Ltmp35:
movq %rsp, %rdi
movl $.L.str.1, %ecx
movl $3, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp36:
jmp .LBB1_32
.LBB1_30:
movb $32, 2(%rax,%rsi)
movw $16416, (%rax,%rsi) # imm = 0x4020
.LBB1_32: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit22
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq %r15, %rdi
callq strlen
movq 8(%rsp), %rsi
movq %rbp, %rcx
subq %rsi, %rcx
cmpq %rax, %rcx
jb .LBB1_42
# %bb.33: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i23
leaq (%rsi,%rax), %rbx
movq (%rsp), %rdi
movl $15, %ecx
cmpq %r13, %rdi
je .LBB1_35
# %bb.34: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i23
movq 16(%rsp), %rcx
.LBB1_35: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i23
cmpq %rcx, %rbx
jbe .LBB1_36
# %bb.40:
.Ltmp37:
movq %rsp, %rdi
xorl %edx, %edx
movq %r15, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp38:
jmp .LBB1_41
.LBB1_36:
testq %rax, %rax
je .LBB1_41
# %bb.37:
addq %rsi, %rdi
cmpq $1, %rax
jne .LBB1_39
# %bb.38:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB1_41
.LBB1_39:
movq %r15, %rsi
movq %rax, %rdx
callq memcpy@PLT
.LBB1_41: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit30
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq 8(%rsp), %rsi
cmpq %rbp, %rsi
je .LBB1_42
# %bb.44: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i31
leaq 1(%rsi), %rbx
movq (%rsp), %rax
movl $15, %ecx
cmpq %r13, %rax
je .LBB1_46
# %bb.45: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i31
movq 16(%rsp), %rcx
.LBB1_46: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i31
cmpq %rcx, %rbx
jbe .LBB1_47
# %bb.48:
.Ltmp39:
movq %rsp, %rdi
movl $.L.str.2, %ecx
movl $1, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp40:
jmp .LBB1_49
.LBB1_47:
movb $58, (%rax,%rsi)
.LBB1_49: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit38
movq %r13, %r12
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movl %r14d, %ebx
negl %ebx
cmovsl %r14d, %ebx
movl $1, %r13d
cmpl $10, %ebx
jb .LBB1_58
# %bb.50: # %.lr.ph.i.i.preheader
movl $4, %r13d
movl $3518437209, %eax # imm = 0xD1B71759
movl %ebx, %ecx
.p2align 4, 0x90
.LBB1_51: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
cmpl $99, %ecx
jbe .LBB1_52
# %bb.53: # in Loop: Header=BB1_51 Depth=1
cmpl $999, %ecx # imm = 0x3E7
jbe .LBB1_54
# %bb.55: # in Loop: Header=BB1_51 Depth=1
cmpl $10000, %ecx # imm = 0x2710
jb .LBB1_58
# %bb.56: # in Loop: Header=BB1_51 Depth=1
movl %ecx, %edx
imulq %rax, %rdx
shrq $45, %rdx
addl $4, %r13d
cmpl $99999, %ecx # imm = 0x1869F
movl %edx, %ecx
ja .LBB1_51
# %bb.57: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i.loopexit
addl $-3, %r13d
jmp .LBB1_58
.LBB1_52:
addl $-2, %r13d
jmp .LBB1_58
.LBB1_54:
decl %r13d
.LBB1_58: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i
shrl $31, %r14d
leal (%r14,%r13), %r15d
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
cmpl $16, %r15d
jb .LBB1_61
# %bb.59:
leaq 1(%r15), %rdi
.Ltmp41:
callq _Znwm
.Ltmp42:
# %bb.60: # %.noexc.i41
movq %rax, 40(%rsp)
movq %r15, 56(%rsp)
.LBB1_61:
testq %r15, %r15
je .LBB1_65
# %bb.62:
movq 40(%rsp), %rdi
cmpl $1, %r15d
jne .LBB1_64
# %bb.63:
movb $45, (%rdi)
jmp .LBB1_65
.LBB1_64:
movl $45, %esi
movq %r15, %rdx
callq memset@PLT
.LBB1_65: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit.i
movq %r15, 48(%rsp)
movq 40(%rsp), %rax
movb $0, (%rax,%r15)
movl %r14d, %eax
addq 40(%rsp), %rax
cmpl $100, %ebx
jb .LBB1_66
# %bb.67: # %.lr.ph.preheader.i.i
addl $-2, %r13d
.p2align 4, 0x90
.LBB1_68: # %.lr.ph.i11.i
# =>This Inner Loop Header: Depth=1
leal 1(%r13), %edx
movl %ebx, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %esi
movl %ebx, %edi
subl %esi, %edi
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdi,%rdi), %esi
movb %sil, (%rax,%rdx)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rdi,%rdi), %edx
movl %r13d, %esi
movb %dl, (%rax,%rsi)
addl $-2, %r13d
cmpl $9999, %ebx # imm = 0x270F
movl %ecx, %ebx
ja .LBB1_68
# %bb.69: # %._crit_edge.i.i
cmpl $10, %ecx
jb .LBB1_72
.LBB1_70:
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB1_73
.LBB1_66:
movl %ebx, %ecx
cmpl $10, %ecx
jae .LBB1_70
.LBB1_72:
orb $48, %cl
.LBB1_73: # %_ZNSt7__cxx119to_stringEi.exit
movq %r12, %r13
movb %cl, (%rax)
movq 48(%rsp), %r8
movq 8(%rsp), %rsi
subq %rsi, %rbp
cmpq %r8, %rbp
jb .LBB1_74
# %bb.76: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
leaq (%rsi,%r8), %rbx
movq (%rsp), %rdi
movl $15, %eax
cmpq %r13, %rdi
je .LBB1_78
# %bb.77: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
movq 16(%rsp), %rax
.LBB1_78: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
movq 40(%rsp), %rcx
cmpq %rax, %rbx
jbe .LBB1_79
# %bb.83:
.Ltmp44:
movq %rsp, %rdi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp45:
jmp .LBB1_84
.LBB1_79:
testq %r8, %r8
je .LBB1_84
# %bb.80:
addq %rsi, %rdi
cmpq $1, %r8
jne .LBB1_82
# %bb.81:
movzbl (%rcx), %eax
movb %al, (%rdi)
jmp .LBB1_84
.LBB1_82:
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.LBB1_84: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLERKS4_.exit
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_86
# %bb.85: # %.critedge.i.i
callq _ZdlPv
.LBB1_86: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp46:
movl $_ZSt4cerr, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp47:
# %bb.87: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_88
# %bb.90: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_92
# %bb.91:
movzbl 67(%r15), %eax
jmp .LBB1_94
.LBB1_92:
.Ltmp48:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp49:
# %bb.93: # %.noexc57
movq (%r15), %rax
.Ltmp50:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp51:
.LBB1_94: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp52:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp53:
# %bb.95: # %.noexc59
.Ltmp54:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp55:
# %bb.96: # %_ZNSolsEPFRSoS_E.exit
cmpb $0, 36(%rsp) # 1-byte Folded Reload
jne .LBB1_97
# %bb.100:
movq (%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_102
# %bb.101: # %.critedge.i.i49
callq _ZdlPv
.LBB1_102:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_42: # %.invoke
.cfi_def_cfa_offset 128
.Ltmp61:
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp62:
# %bb.43: # %.cont
.LBB1_74:
.Ltmp58:
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp59:
# %bb.75: # %.noexc42
.LBB1_88:
.Ltmp56:
callq _ZSt16__throw_bad_castv
.Ltmp57:
# %bb.89: # %.noexc56
.LBB1_97:
callq _ZSt9terminatev
.LBB1_71:
.Ltmp43:
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_98:
.Ltmp60:
movq %rax, %rbx
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_104
# %bb.99: # %.critedge.i.i46
callq _ZdlPv
jmp .LBB1_104
.LBB1_103:
.Ltmp63:
movq %r13, %r12
movq %rax, %rbx
.LBB1_104:
movq (%rsp), %rdi
cmpq %r12, %rdi
je .LBB1_106
# %bb.105: # %.critedge.i.i52
callq _ZdlPv
.LBB1_106: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit54
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN4cutw12curandassertEiPKcib, .Lfunc_end1-_ZN4cutw12curandassertEiPKcib
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_5
.quad .LBB1_6
.quad .LBB1_7
.quad .LBB1_8
.quad .LBB1_9
.quad .LBB1_10
.quad .LBB1_11
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_16
.quad .LBB1_12
.quad .LBB1_13
.quad .LBB1_14
.quad .LBB1_15
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp33-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp33
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp63-.Lfunc_begin1 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp35-.Ltmp34 # Call between .Ltmp34 and .Ltmp35
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp38-.Ltmp35 # Call between .Ltmp35 and .Ltmp38
.uleb128 .Ltmp63-.Lfunc_begin1 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp63-.Lfunc_begin1 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin1 # jumps to .Ltmp43
.byte 1 # On action: 1
.uleb128 .Ltmp42-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp44-.Ltmp42 # Call between .Ltmp42 and .Ltmp44
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp45-.Ltmp44 # Call between .Ltmp44 and .Ltmp45
.uleb128 .Ltmp60-.Lfunc_begin1 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp62-.Ltmp46 # Call between .Ltmp46 and .Ltmp62
.uleb128 .Ltmp63-.Lfunc_begin1 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp59-.Ltmp58 # Call between .Ltmp58 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin1 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Ltmp57-.Ltmp56 # Call between .Ltmp56 and .Ltmp57
.uleb128 .Ltmp63-.Lfunc_begin1 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin1 # >> Call Site 14 <<
.uleb128 .Lfunc_end1-.Ltmp57 # Call between .Ltmp57 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB3_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB3_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB3_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB3_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB3_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB3_6:
movq %rbp, %rdi
incq %rdi
js .LBB3_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB3_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB3_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB3_11
.LBB3_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB3_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB3_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB3_18
# %bb.13:
je .LBB3_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB3_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB3_17
.LBB3_16:
callq memcpy@PLT
.LBB3_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB3_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB3_23
# %bb.19:
subq %r14, %r12
je .LBB3_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB3_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB3_23
.LBB3_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB3_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB3_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB3_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB3_26:
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end3:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end3-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cutw: cuassert: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " @ "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ":"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cutw: curandassert: "
.size .L.str.3, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "basic_string::_M_create"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "basic_string::append"
.size .L.str.6, 21
.type .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits,@object # @__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits:
.asciz "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.size .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits, 201
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "CURAND_STATUS_VERSION_MISMATCH"
.size .L.str.8, 31
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CURAND_STATUS_NOT_INITIALIZED"
.size .L.str.9, 30
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CURAND_STATUS_ALLOCATION_FAILED"
.size .L.str.10, 32
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CURAND_STATUS_TYPE_ERROR"
.size .L.str.11, 25
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "CURAND_STATUS_OUT_OF_RANGE"
.size .L.str.12, 27
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "CURAND_STATUS_LENGTH_NOT_MULTIPLE"
.size .L.str.13, 34
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED"
.size .L.str.14, 40
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CURAND_STATUS_LAUNCH_FAILURE"
.size .L.str.15, 29
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "CURAND_STATUS_PREEXISTING_FAILURE"
.size .L.str.16, 34
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "CURAND_STATUS_INITIALIZATION_FAILED"
.size .L.str.17, 36
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "CURAND_STATUS_ARCH_MISMATCH"
.size .L.str.18, 28
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "CURAND_STATUS_INTERNAL_ERROR"
.size .L.str.19, 29
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "<unknown>"
.size .L.str.20, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void frontier_init_kernel(int* p_frontier_tail_d, int* c_frontier_tail_d, int* p_frontier_d, int* visited_d, int* label_d, int source) {
visited_d[source] = 1;
*c_frontier_tail_d = 0;
p_frontier_d[0] = source;
*p_frontier_tail_d = 1;
label_d[source] = 0;
} | code for sm_80
Function : _Z20frontier_init_kernelPiS_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0b7624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R14, c[0x0][0x168] ; /* 0x00005a00000e7a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IMAD.WIDE R2, R11, R8, c[0x0][0x178] ; /* 0x00005e000b027625 */
/* 0x000fe200078e0208 */
/*00b0*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD.WIDE R8, R11, R8, c[0x0][0x180] ; /* 0x000060000b087625 */
/* 0x000fe200078e0208 */
/*00d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x000fe8000c101904 */
/*00f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0100*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void frontier_init_kernel(int* p_frontier_tail_d, int* c_frontier_tail_d, int* p_frontier_d, int* visited_d, int* label_d, int source) {
visited_d[source] = 1;
*c_frontier_tail_d = 0;
p_frontier_d[0] = source;
*p_frontier_tail_d = 1;
label_d[source] = 0;
} | .file "tmpxft_0007556f_00000000-6_frontier_init_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i
.type _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i, @function
_Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20frontier_init_kernelPiS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i, .-_Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i
.globl _Z20frontier_init_kernelPiS_S_S_S_i
.type _Z20frontier_init_kernelPiS_S_S_S_i, @function
_Z20frontier_init_kernelPiS_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20frontier_init_kernelPiS_S_S_S_i, .-_Z20frontier_init_kernelPiS_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20frontier_init_kernelPiS_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20frontier_init_kernelPiS_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void frontier_init_kernel(int* p_frontier_tail_d, int* c_frontier_tail_d, int* p_frontier_d, int* visited_d, int* label_d, int source) {
visited_d[source] = 1;
*c_frontier_tail_d = 0;
p_frontier_d[0] = source;
*p_frontier_tail_d = 1;
label_d[source] = 0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void frontier_init_kernel(int* p_frontier_tail_d, int* c_frontier_tail_d, int* p_frontier_d, int* visited_d, int* label_d, int source) {
visited_d[source] = 1;
*c_frontier_tail_d = 0;
p_frontier_d[0] = source;
*p_frontier_tail_d = 1;
label_d[source] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void frontier_init_kernel(int* p_frontier_tail_d, int* c_frontier_tail_d, int* p_frontier_d, int* visited_d, int* label_d, int source) {
visited_d[source] = 1;
*c_frontier_tail_d = 0;
p_frontier_d[0] = source;
*p_frontier_tail_d = 1;
label_d[source] = 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20frontier_init_kernelPiS_S_S_S_i
.globl _Z20frontier_init_kernelPiS_S_S_S_i
.p2align 8
.type _Z20frontier_init_kernelPiS_S_S_S_i,@function
_Z20frontier_init_kernelPiS_S_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v2, s2
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s10, s12
s_addc_u32 s3, s11, s13
s_add_u32 s0, s0, s12
s_addc_u32 s1, s1, s13
s_clause 0x4
global_store_b32 v1, v0, s[2:3]
global_store_b32 v1, v1, s[6:7]
global_store_b32 v1, v2, s[8:9]
global_store_b32 v1, v0, s[4:5]
global_store_b32 v1, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20frontier_init_kernelPiS_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20frontier_init_kernelPiS_S_S_S_i, .Lfunc_end0-_Z20frontier_init_kernelPiS_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20frontier_init_kernelPiS_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z20frontier_init_kernelPiS_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void frontier_init_kernel(int* p_frontier_tail_d, int* c_frontier_tail_d, int* p_frontier_d, int* visited_d, int* label_d, int source) {
visited_d[source] = 1;
*c_frontier_tail_d = 0;
p_frontier_d[0] = source;
*p_frontier_tail_d = 1;
label_d[source] = 0;
} | .text
.file "frontier_init_kernel.hip"
.globl _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i # -- Begin function _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.p2align 4, 0x90
.type _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i,@function
_Z35__device_stub__frontier_init_kernelPiS_S_S_S_i: # @_Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20frontier_init_kernelPiS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i, .Lfunc_end0-_Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20frontier_init_kernelPiS_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20frontier_init_kernelPiS_S_S_S_i,@object # @_Z20frontier_init_kernelPiS_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z20frontier_init_kernelPiS_S_S_S_i
.p2align 3, 0x0
_Z20frontier_init_kernelPiS_S_S_S_i:
.quad _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.size _Z20frontier_init_kernelPiS_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20frontier_init_kernelPiS_S_S_S_i"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20frontier_init_kernelPiS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20frontier_init_kernelPiS_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0b7624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R14, c[0x0][0x168] ; /* 0x00005a00000e7a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IMAD.WIDE R2, R11, R8, c[0x0][0x178] ; /* 0x00005e000b027625 */
/* 0x000fe200078e0208 */
/*00b0*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD.WIDE R8, R11, R8, c[0x0][0x180] ; /* 0x000060000b087625 */
/* 0x000fe200078e0208 */
/*00d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x000fe8000c101904 */
/*00f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0100*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20frontier_init_kernelPiS_S_S_S_i
.globl _Z20frontier_init_kernelPiS_S_S_S_i
.p2align 8
.type _Z20frontier_init_kernelPiS_S_S_S_i,@function
_Z20frontier_init_kernelPiS_S_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v2, s2
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s10, s12
s_addc_u32 s3, s11, s13
s_add_u32 s0, s0, s12
s_addc_u32 s1, s1, s13
s_clause 0x4
global_store_b32 v1, v0, s[2:3]
global_store_b32 v1, v1, s[6:7]
global_store_b32 v1, v2, s[8:9]
global_store_b32 v1, v0, s[4:5]
global_store_b32 v1, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20frontier_init_kernelPiS_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20frontier_init_kernelPiS_S_S_S_i, .Lfunc_end0-_Z20frontier_init_kernelPiS_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20frontier_init_kernelPiS_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z20frontier_init_kernelPiS_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007556f_00000000-6_frontier_init_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i
.type _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i, @function
_Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20frontier_init_kernelPiS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i, .-_Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i
.globl _Z20frontier_init_kernelPiS_S_S_S_i
.type _Z20frontier_init_kernelPiS_S_S_S_i, @function
_Z20frontier_init_kernelPiS_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20frontier_init_kernelPiS_S_S_S_iPiS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20frontier_init_kernelPiS_S_S_S_i, .-_Z20frontier_init_kernelPiS_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20frontier_init_kernelPiS_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20frontier_init_kernelPiS_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "frontier_init_kernel.hip"
.globl _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i # -- Begin function _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.p2align 4, 0x90
.type _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i,@function
_Z35__device_stub__frontier_init_kernelPiS_S_S_S_i: # @_Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20frontier_init_kernelPiS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i, .Lfunc_end0-_Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20frontier_init_kernelPiS_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20frontier_init_kernelPiS_S_S_S_i,@object # @_Z20frontier_init_kernelPiS_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z20frontier_init_kernelPiS_S_S_S_i
.p2align 3, 0x0
_Z20frontier_init_kernelPiS_S_S_S_i:
.quad _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.size _Z20frontier_init_kernelPiS_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20frontier_init_kernelPiS_S_S_S_i"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__frontier_init_kernelPiS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20frontier_init_kernelPiS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__
void nekbone(double *w, double *u, double *g, double *d, double *dt, const int N) {
const int e_size = N * N * N;
const int e_offset = e_size * blockIdx.x;
__shared__ double ur[1024];
__shared__ double us[1024];
__shared__ double ut[1024];
__shared__ double ul[1024];
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
ul[it] = u[e_offset + it];
}
__syncthreads();
int i, j, k;
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double wr = 0.0;
double ws = 0.0;
double wt = 0.0;
for (int n = 0; n < N; ++n) {
wr += dt[i * N + n] * ul[N * (j + k * N) + n];
ws += dt[j * N + n] * ul[N * (n + k * N) + i];
wt += dt[k * N + n] * ul[N * (j + n * N) + i];
}
int g_offset = 6 * (e_offset + it);
ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
}
__syncthreads();
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double s = 0.0;
for (int n = 0; n < N; ++n) {
s += d[i * N + n] * ur[N * (j + N * k) + n] +
d[j * N + n] * us[N * (n + N * k) + i] +
d[k * N + n] * ut[N * (j + N * n) + i];
}
w[e_offset + it] = s;
}
} | .file "tmpxft_000604db_00000000-6_cuda1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i
.type _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i, @function
_Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7nekbonePdS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i, .-_Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i
.globl _Z7nekbonePdS_S_S_S_i
.type _Z7nekbonePdS_S_S_S_i, @function
_Z7nekbonePdS_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7nekbonePdS_S_S_S_i, .-_Z7nekbonePdS_S_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7nekbonePdS_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7nekbonePdS_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__
void nekbone(double *w, double *u, double *g, double *d, double *dt, const int N) {
const int e_size = N * N * N;
const int e_offset = e_size * blockIdx.x;
__shared__ double ur[1024];
__shared__ double us[1024];
__shared__ double ut[1024];
__shared__ double ul[1024];
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
ul[it] = u[e_offset + it];
}
__syncthreads();
int i, j, k;
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double wr = 0.0;
double ws = 0.0;
double wt = 0.0;
for (int n = 0; n < N; ++n) {
wr += dt[i * N + n] * ul[N * (j + k * N) + n];
ws += dt[j * N + n] * ul[N * (n + k * N) + i];
wt += dt[k * N + n] * ul[N * (j + n * N) + i];
}
int g_offset = 6 * (e_offset + it);
ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
}
__syncthreads();
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double s = 0.0;
for (int n = 0; n < N; ++n) {
s += d[i * N + n] * ur[N * (j + N * k) + n] +
d[j * N + n] * us[N * (n + N * k) + i] +
d[k * N + n] * ut[N * (j + N * n) + i];
}
w[e_offset + it] = s;
}
} | #include <hip/hip_runtime.h>
__global__
void nekbone(double *w, double *u, double *g, double *d, double *dt, const int N) {
const int e_size = N * N * N;
const int e_offset = e_size * blockIdx.x;
__shared__ double ur[1024];
__shared__ double us[1024];
__shared__ double ut[1024];
__shared__ double ul[1024];
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
ul[it] = u[e_offset + it];
}
__syncthreads();
int i, j, k;
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double wr = 0.0;
double ws = 0.0;
double wt = 0.0;
for (int n = 0; n < N; ++n) {
wr += dt[i * N + n] * ul[N * (j + k * N) + n];
ws += dt[j * N + n] * ul[N * (n + k * N) + i];
wt += dt[k * N + n] * ul[N * (j + n * N) + i];
}
int g_offset = 6 * (e_offset + it);
ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
}
__syncthreads();
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double s = 0.0;
for (int n = 0; n < N; ++n) {
s += d[i * N + n] * ur[N * (j + N * k) + n] +
d[j * N + n] * us[N * (n + N * k) + i] +
d[k * N + n] * ut[N * (j + N * n) + i];
}
w[e_offset + it] = s;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__
void nekbone(double *w, double *u, double *g, double *d, double *dt, const int N) {
const int e_size = N * N * N;
const int e_offset = e_size * blockIdx.x;
__shared__ double ur[1024];
__shared__ double us[1024];
__shared__ double ut[1024];
__shared__ double ul[1024];
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
ul[it] = u[e_offset + it];
}
__syncthreads();
int i, j, k;
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double wr = 0.0;
double ws = 0.0;
double wt = 0.0;
for (int n = 0; n < N; ++n) {
wr += dt[i * N + n] * ul[N * (j + k * N) + n];
ws += dt[j * N + n] * ul[N * (n + k * N) + i];
wt += dt[k * N + n] * ul[N * (j + n * N) + i];
}
int g_offset = 6 * (e_offset + it);
ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
}
__syncthreads();
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double s = 0.0;
for (int n = 0; n < N; ++n) {
s += d[i * N + n] * ur[N * (j + N * k) + n] +
d[j * N + n] * us[N * (n + N * k) + i] +
d[k * N + n] * ut[N * (j + N * n) + i];
}
w[e_offset + it] = s;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7nekbonePdS_S_S_S_i
.globl _Z7nekbonePdS_S_S_S_i
.p2align 8
.type _Z7nekbonePdS_S_S_S_i,@function
_Z7nekbonePdS_S_S_S_i:
s_load_b32 s8, s[0:1], 0x28
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s8, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s11, s8
s_mul_i32 s10, s9, s15
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s5, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v2, v0 :: v_dual_lshlrev_b32 v1, 3, v0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s6, s5, 3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v3, s10, v2
v_add_nc_u32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s9, v2
global_load_b64 v[3:4], v[3:4], off
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
ds_store_b64 v1, v[3:4]
v_add_nc_u32_e32 v1, s6, v1
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s12, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_9
s_cmp_gt_i32 s8, 0
v_mov_b32_e32 v17, v0
s_cselect_b32 s13, -1, 0
s_ashr_i32 s14, s8, 31
s_mov_b32 s16, 0
s_add_i32 s2, s8, s14
s_lshl_b32 s19, s8, 3
s_xor_b32 s15, s2, s14
s_load_b32 s2, s[0:1], 0x3c
v_cvt_f32_u32_e32 v1, s15
s_sub_i32 s3, 0, s15
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_lshl_b32 s20, s11, 3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v1
s_lshl_b32 s18, s17, 3
v_mul_lo_u32 v1, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v2, v1
v_lshlrev_b32_e32 v1, 3, v0
v_add_nc_u32_e32 v16, v2, v3
s_branch .LBB0_6
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v8, s10, v17
v_add_nc_u32_e32 v1, s18, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v8, 6
v_or_b32_e32 v10, 1, v8
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_co_u32 v18, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v11, vcc_lo
s_clause 0x3
global_load_b128 v[8:11], v[18:19], off offset:16
global_load_b64 v[20:21], v[12:13], off
global_load_b128 v[12:15], v[18:19], off offset:32
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(3)
v_mul_f64 v[10:11], v[4:5], v[10:11]
s_waitcnt vmcnt(2)
v_mul_f64 v[22:23], v[4:5], v[20:21]
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[4:5], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[6:7], v[20:21], v[10:11]
s_waitcnt vmcnt(0)
v_fma_f64 v[18:19], v[6:7], v[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[4:5], v[6:7], v[8:9], v[4:5]
v_fma_f64 v[6:7], v[2:3], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[2:3], v[8:9], v[18:19]
v_fma_f64 v[2:3], v[2:3], v[14:15], v[4:5]
v_lshlrev_b32_e32 v4, 3, v17
v_add_nc_u32_e32 v17, s17, v17
ds_store_2addr_stride64_b64 v4, v[8:9], v[6:7] offset0:16 offset1:32
ds_store_b64 v4, v[2:3] offset:24576
v_cmp_le_i32_e32 vcc_lo, s9, v17
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_9
.LBB0_6:
v_ashrrev_i32_e32 v8, 31, v17
s_and_not1_b32 vcc_lo, exec_lo, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v17, v8
v_xor_b32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v9, v2, v16
v_mul_lo_u32 v3, v9, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v4, v2, v3
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_subrev_nc_u32_e32 v5, s15, v4
v_cmp_le_u32_e64 s2, s15, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v4, v5, s2
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e64 s3, s15, v6
v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
s_cbranch_vccnz .LBB0_5
v_add_nc_u32_e32 v2, 1, v9
v_xor_b32_e32 v7, s14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v9, v2, s2
s_mov_b32 s2, s8
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v3, s3
v_xor_b32_e32 v10, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v10, v7
v_ashrrev_i32_e32 v12, 31, v11
v_mul_lo_u32 v18, s19, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v11, v12
v_xor_b32_e32 v4, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, v16, 0
v_mul_lo_u32 v2, v3, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v3, s15, v2
v_cmp_le_u32_e32 vcc_lo, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_mul_lo_u32 v3, v11, s8
v_subrev_nc_u32_e32 v4, s15, v2
v_cmp_le_u32_e32 vcc_lo, s15, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v17, v3
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, s8, v3
v_xor_b32_e32 v13, v2, v12
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v13, v7
v_sub_nc_u32_e32 v14, v13, v12
v_ashrrev_i32_e32 v5, 31, v4
v_sub_nc_u32_e32 v19, v12, v13
v_sub_nc_u32_e32 v15, v7, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v6, v14, s8
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_sub_nc_u32_e32 v10, v11, v14
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_sub_nc_u32_e32 v11, v15, v12
v_mad_u64_u32 v[12:13], null, s19, v19, v[1:2]
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_mad_u64_u32 v[13:14], null, s19, v11, v[1:2]
v_add_co_u32 v14, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v7, vcc_lo
v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
v_ashrrev_i32_e32 v11, 31, v10
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[19:20], 3, v[10:11]
v_add_nc_u32_e32 v10, 1, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v19, vcc_lo, s6, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
global_load_b64 v[21:22], v[8:9], off
global_load_b64 v[23:24], v[14:15], off
global_load_b64 v[19:20], v[19:20], off
ds_load_b64 v[25:26], v18
ds_load_b64 v[27:28], v12
ds_load_b64 v[29:30], v13
v_add_co_u32 v14, vcc_lo, v14, 8
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_nc_u32_e32 v13, s20, v13
v_add_nc_u32_e32 v12, s19, v12
v_add_nc_u32_e32 v18, 8, v18
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(2) lgkmcnt(2)
v_fma_f64 v[6:7], v[21:22], v[25:26], v[6:7]
s_waitcnt vmcnt(1) lgkmcnt(1)
v_fma_f64 v[4:5], v[23:24], v[27:28], v[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[2:3], v[19:20], v[29:30], v[2:3]
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_16
s_cmp_gt_i32 s8, 0
s_load_b32 s14, s[0:1], 0x3c
s_cselect_b32 s6, -1, 0
s_ashr_i32 s7, s8, 31
s_mov_b32 s13, 0
s_add_i32 s2, s8, s7
s_lshl_b32 s16, s8, 3
s_xor_b32 s12, s2, s7
s_lshl_b32 s11, s11, 3
v_cvt_f32_u32_e32 v1, s12
s_sub_i32 s2, 0, s12
v_lshlrev_b32_e32 v2, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s14, 0xffff
s_lshl_b32 s15, s14, 3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mul_lo_u32 v1, s2, v3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, v3, v1
v_or_b32_e32 v1, 0x6000, v2
v_or_b32_e32 v2, 0x4000, v2
v_add_nc_u32_e32 v14, v3, v4
s_branch .LBB0_13
.LBB0_11:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_12:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v5, s10, v0
v_add_nc_u32_e32 v0, s14, v0
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v2, s15, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_cmp_le_i32_e32 vcc_lo, s9, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_or_b32 s13, vcc_lo, s13
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_16
.LBB0_13:
v_ashrrev_i32_e32 v3, 31, v0
s_and_not1_b32 vcc_lo, exec_lo, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v3
v_xor_b32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v5, v14
v_mul_lo_u32 v6, v4, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v6
v_subrev_nc_u32_e32 v6, s12, v5
v_cmp_le_u32_e64 s0, s12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v6, s0
v_cmp_le_u32_e64 s1, s12, v5
s_cbranch_vccnz .LBB0_11
v_add_nc_u32_e32 v5, 1, v4
v_xor_b32_e32 v6, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v5, s0
s_mov_b32 s0, s8
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v4, v5, s1
v_xor_b32_e32 v10, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v10, v6
v_ashrrev_i32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v11, v15
v_xor_b32_e32 v5, v3, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, v14, 0
v_mul_lo_u32 v3, v4, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_mul_lo_u32 v5, v11, s8
v_subrev_nc_u32_e32 v4, s12, v3
v_cmp_le_u32_e32 vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s12, v3
v_cmp_le_u32_e32 vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_xor_b32_e32 v16, v3, v15
v_sub_nc_u32_e32 v3, v0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v12, v16, v6
v_sub_nc_u32_e32 v17, v16, v15
v_mul_lo_u32 v7, s8, v3
v_mad_u64_u32 v[5:6], null, s16, v11, 0x2000
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v18, v12, v10
v_mul_lo_u32 v9, v17, s8
v_sub_nc_u32_e32 v6, v11, v17
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v8, 31, v7
v_sub_nc_u32_e32 v11, v18, v15
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[12:13], 3, v[7:8]
v_sub_nc_u32_e32 v7, v15, v16
v_lshlrev_b64 v[15:16], 3, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, s16, v7, v[2:3]
v_mad_u64_u32 v[9:10], null, s16, v11, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v15
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
global_load_b64 v[15:16], v[10:11], off
global_load_b64 v[17:18], v[12:13], off
v_ashrrev_i32_e32 v7, 31, v6
ds_load_b64 v[21:22], v8
v_add_nc_u32_e32 v8, s16, v8
s_add_i32 s0, s0, -1
v_lshlrev_b64 v[19:20], 3, v[6:7]
v_add_nc_u32_e32 v6, 1, v6
s_cmp_eq_u32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, 8
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
global_load_b64 v[19:20], v[19:20], off
v_add_co_u32 v12, vcc_lo, v12, 8
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_waitcnt vmcnt(2) lgkmcnt(0)
v_mul_f64 v[15:16], v[15:16], v[21:22]
ds_load_b64 v[21:22], v5
v_add_nc_u32_e32 v5, 8, v5
s_waitcnt vmcnt(1) lgkmcnt(0)
v_fma_f64 v[15:16], v[17:18], v[21:22], v[15:16]
ds_load_b64 v[17:18], v9
v_add_nc_u32_e32 v9, s11, v9
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[15:16], v[19:20], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[15:16]
s_cbranch_scc0 .LBB0_15
s_branch .LBB0_12
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7nekbonePdS_S_S_S_i
.amdhsa_group_segment_fixed_size 32768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7nekbonePdS_S_S_S_i, .Lfunc_end0-_Z7nekbonePdS_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32768
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7nekbonePdS_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z7nekbonePdS_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__
void nekbone(double *w, double *u, double *g, double *d, double *dt, const int N) {
const int e_size = N * N * N;
const int e_offset = e_size * blockIdx.x;
__shared__ double ur[1024];
__shared__ double us[1024];
__shared__ double ut[1024];
__shared__ double ul[1024];
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
ul[it] = u[e_offset + it];
}
__syncthreads();
int i, j, k;
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double wr = 0.0;
double ws = 0.0;
double wt = 0.0;
for (int n = 0; n < N; ++n) {
wr += dt[i * N + n] * ul[N * (j + k * N) + n];
ws += dt[j * N + n] * ul[N * (n + k * N) + i];
wt += dt[k * N + n] * ul[N * (j + n * N) + i];
}
int g_offset = 6 * (e_offset + it);
ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
}
__syncthreads();
for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
j = it / N;
i = it - j * N;
k = j / N;
j -= k * N;
double s = 0.0;
for (int n = 0; n < N; ++n) {
s += d[i * N + n] * ur[N * (j + N * k) + n] +
d[j * N + n] * us[N * (n + N * k) + i] +
d[k * N + n] * ut[N * (j + N * n) + i];
}
w[e_offset + it] = s;
}
} | .text
.file "cuda1.hip"
.globl _Z22__device_stub__nekbonePdS_S_S_S_i # -- Begin function _Z22__device_stub__nekbonePdS_S_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__nekbonePdS_S_S_S_i,@function
_Z22__device_stub__nekbonePdS_S_S_S_i: # @_Z22__device_stub__nekbonePdS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7nekbonePdS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__nekbonePdS_S_S_S_i, .Lfunc_end0-_Z22__device_stub__nekbonePdS_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7nekbonePdS_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7nekbonePdS_S_S_S_i,@object # @_Z7nekbonePdS_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z7nekbonePdS_S_S_S_i
.p2align 3, 0x0
_Z7nekbonePdS_S_S_S_i:
.quad _Z22__device_stub__nekbonePdS_S_S_S_i
.size _Z7nekbonePdS_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7nekbonePdS_S_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__nekbonePdS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7nekbonePdS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000604db_00000000-6_cuda1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i
.type _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i, @function
_Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7nekbonePdS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i, .-_Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i
.globl _Z7nekbonePdS_S_S_S_i
.type _Z7nekbonePdS_S_S_S_i, @function
_Z7nekbonePdS_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7nekbonePdS_S_S_S_iPdS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7nekbonePdS_S_S_S_i, .-_Z7nekbonePdS_S_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7nekbonePdS_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7nekbonePdS_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda1.hip"
.globl _Z22__device_stub__nekbonePdS_S_S_S_i # -- Begin function _Z22__device_stub__nekbonePdS_S_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__nekbonePdS_S_S_S_i,@function
_Z22__device_stub__nekbonePdS_S_S_S_i: # @_Z22__device_stub__nekbonePdS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7nekbonePdS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__nekbonePdS_S_S_S_i, .Lfunc_end0-_Z22__device_stub__nekbonePdS_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7nekbonePdS_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7nekbonePdS_S_S_S_i,@object # @_Z7nekbonePdS_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z7nekbonePdS_S_S_S_i
.p2align 3, 0x0
_Z7nekbonePdS_S_S_S_i:
.quad _Z22__device_stub__nekbonePdS_S_S_S_i
.size _Z7nekbonePdS_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7nekbonePdS_S_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__nekbonePdS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7nekbonePdS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void per_row_kernel(int m,int n,int *A,int *B,int *C){
int idr;
idr=blockIdx.x*blockDim.x+threadIdx.x;
if(idr<m){
for(int j=0;j<n;j++){
C[idr*n+j]=A[idr*n+j]+B[idr*n+j];
}
}
}
__global__ void per_column_kernel(int m,int n,int *A,int *B,int *C){
int idc;
idc =blockDim.x*blockDim.y*blockIdx.x+ blockDim.x* threadIdx.y+threadIdx.x;
if(idc<n){
for(int j=0;j<m;j++){
C[idc*m+j]=A[idc*m+j]+B[idc*m+j];
}
}
}
__global__ void per_element_kernel(int m,int n,int *A,int *B,int *C){
int i,j,ide;
i = threadIdx.x + blockDim.x * threadIdx.y;
j = blockIdx.x + gridDim.x * blockIdx.y;
ide=j*blockDim.x*blockDim.y+i;
if(ide<(m*n))
C[ide]=A[ide]+B[ide];
} | .file "tmpxft_001254a4_00000000-6_CS20M027.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_
.type _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_, @function
_Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14per_row_kerneliiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_, .-_Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_
.globl _Z14per_row_kerneliiPiS_S_
.type _Z14per_row_kerneliiPiS_S_, @function
_Z14per_row_kerneliiPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14per_row_kerneliiPiS_S_, .-_Z14per_row_kerneliiPiS_S_
.globl _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_
.type _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_, @function
_Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17per_column_kerneliiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_, .-_Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_
.globl _Z17per_column_kerneliiPiS_S_
.type _Z17per_column_kerneliiPiS_S_, @function
_Z17per_column_kerneliiPiS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z17per_column_kerneliiPiS_S_, .-_Z17per_column_kerneliiPiS_S_
.globl _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_
.type _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_, @function
_Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18per_element_kerneliiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_, .-_Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_
.globl _Z18per_element_kerneliiPiS_S_
.type _Z18per_element_kerneliiPiS_S_, @function
_Z18per_element_kerneliiPiS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z18per_element_kerneliiPiS_S_, .-_Z18per_element_kerneliiPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18per_element_kerneliiPiS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z17per_column_kerneliiPiS_S_"
.LC2:
.string "_Z14per_row_kerneliiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18per_element_kerneliiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17per_column_kerneliiPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14per_row_kerneliiPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void per_row_kernel(int m,int n,int *A,int *B,int *C){
int idr;
idr=blockIdx.x*blockDim.x+threadIdx.x;
if(idr<m){
for(int j=0;j<n;j++){
C[idr*n+j]=A[idr*n+j]+B[idr*n+j];
}
}
}
__global__ void per_column_kernel(int m,int n,int *A,int *B,int *C){
int idc;
idc =blockDim.x*blockDim.y*blockIdx.x+ blockDim.x* threadIdx.y+threadIdx.x;
if(idc<n){
for(int j=0;j<m;j++){
C[idc*m+j]=A[idc*m+j]+B[idc*m+j];
}
}
}
__global__ void per_element_kernel(int m,int n,int *A,int *B,int *C){
int i,j,ide;
i = threadIdx.x + blockDim.x * threadIdx.y;
j = blockIdx.x + gridDim.x * blockIdx.y;
ide=j*blockDim.x*blockDim.y+i;
if(ide<(m*n))
C[ide]=A[ide]+B[ide];
} | #include <hip/hip_runtime.h>
__global__ void per_row_kernel(int m,int n,int *A,int *B,int *C){
int idr;
idr=blockIdx.x*blockDim.x+threadIdx.x;
if(idr<m){
for(int j=0;j<n;j++){
C[idr*n+j]=A[idr*n+j]+B[idr*n+j];
}
}
}
__global__ void per_column_kernel(int m,int n,int *A,int *B,int *C){
int idc;
idc =blockDim.x*blockDim.y*blockIdx.x+ blockDim.x* threadIdx.y+threadIdx.x;
if(idc<n){
for(int j=0;j<m;j++){
C[idc*m+j]=A[idc*m+j]+B[idc*m+j];
}
}
}
__global__ void per_element_kernel(int m,int n,int *A,int *B,int *C){
int i,j,ide;
i = threadIdx.x + blockDim.x * threadIdx.y;
j = blockIdx.x + gridDim.x * blockIdx.y;
ide=j*blockDim.x*blockDim.y+i;
if(ide<(m*n))
C[ide]=A[ide]+B[ide];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void per_row_kernel(int m,int n,int *A,int *B,int *C){
int idr;
idr=blockIdx.x*blockDim.x+threadIdx.x;
if(idr<m){
for(int j=0;j<n;j++){
C[idr*n+j]=A[idr*n+j]+B[idr*n+j];
}
}
}
__global__ void per_column_kernel(int m,int n,int *A,int *B,int *C){
int idc;
idc =blockDim.x*blockDim.y*blockIdx.x+ blockDim.x* threadIdx.y+threadIdx.x;
if(idc<n){
for(int j=0;j<m;j++){
C[idc*m+j]=A[idc*m+j]+B[idc*m+j];
}
}
}
__global__ void per_element_kernel(int m,int n,int *A,int *B,int *C){
int i,j,ide;
i = threadIdx.x + blockDim.x * threadIdx.y;
j = blockIdx.x + gridDim.x * blockIdx.y;
ide=j*blockDim.x*blockDim.y+i;
if(ide<(m*n))
C[ide]=A[ide]+B[ide];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14per_row_kerneliiPiS_S_
.globl _Z14per_row_kerneliiPiS_S_
.p2align 8
.type _Z14per_row_kerneliiPiS_S_,@function
_Z14per_row_kerneliiPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v0, v1, s3
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14per_row_kerneliiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14per_row_kerneliiPiS_S_, .Lfunc_end0-_Z14per_row_kerneliiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17per_column_kerneliiPiS_S_
.globl _Z17per_column_kerneliiPiS_S_
.p2align 8
.type _Z17per_column_kerneliiPiS_S_,@function
_Z17per_column_kerneliiPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_gt_i32 s2, 0
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_cselect_b32 s3, -1, 0
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v0, v0, s2
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.p2align 6
.LBB1_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17per_column_kerneliiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17per_column_kerneliiPiS_S_, .Lfunc_end1-_Z17per_column_kerneliiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18per_element_kerneliiPiS_S_
.globl _Z18per_element_kerneliiPiS_S_
.p2align 8
.type _Z18per_element_kerneliiPiS_S_,@function
_Z18per_element_kerneliiPiS_S_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_lshr_b32 s6, s5, 16
s_add_i32 s4, s4, s14
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[2:3], null, s4, s6, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s4, s5, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18per_element_kerneliiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18per_element_kerneliiPiS_S_, .Lfunc_end2-_Z18per_element_kerneliiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14per_row_kerneliiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14per_row_kerneliiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17per_column_kerneliiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17per_column_kerneliiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18per_element_kerneliiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18per_element_kerneliiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void per_row_kernel(int m,int n,int *A,int *B,int *C){
int idr;
idr=blockIdx.x*blockDim.x+threadIdx.x;
if(idr<m){
for(int j=0;j<n;j++){
C[idr*n+j]=A[idr*n+j]+B[idr*n+j];
}
}
}
__global__ void per_column_kernel(int m,int n,int *A,int *B,int *C){
int idc;
idc =blockDim.x*blockDim.y*blockIdx.x+ blockDim.x* threadIdx.y+threadIdx.x;
if(idc<n){
for(int j=0;j<m;j++){
C[idc*m+j]=A[idc*m+j]+B[idc*m+j];
}
}
}
__global__ void per_element_kernel(int m,int n,int *A,int *B,int *C){
int i,j,ide;
i = threadIdx.x + blockDim.x * threadIdx.y;
j = blockIdx.x + gridDim.x * blockIdx.y;
ide=j*blockDim.x*blockDim.y+i;
if(ide<(m*n))
C[ide]=A[ide]+B[ide];
} | .text
.file "CS20M027.hip"
.globl _Z29__device_stub__per_row_kerneliiPiS_S_ # -- Begin function _Z29__device_stub__per_row_kerneliiPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__per_row_kerneliiPiS_S_,@function
_Z29__device_stub__per_row_kerneliiPiS_S_: # @_Z29__device_stub__per_row_kerneliiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14per_row_kerneliiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__per_row_kerneliiPiS_S_, .Lfunc_end0-_Z29__device_stub__per_row_kerneliiPiS_S_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__per_column_kerneliiPiS_S_ # -- Begin function _Z32__device_stub__per_column_kerneliiPiS_S_
.p2align 4, 0x90
.type _Z32__device_stub__per_column_kerneliiPiS_S_,@function
_Z32__device_stub__per_column_kerneliiPiS_S_: # @_Z32__device_stub__per_column_kerneliiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17per_column_kerneliiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__per_column_kerneliiPiS_S_, .Lfunc_end1-_Z32__device_stub__per_column_kerneliiPiS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__per_element_kerneliiPiS_S_ # -- Begin function _Z33__device_stub__per_element_kerneliiPiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__per_element_kerneliiPiS_S_,@function
_Z33__device_stub__per_element_kerneliiPiS_S_: # @_Z33__device_stub__per_element_kerneliiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18per_element_kerneliiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__per_element_kerneliiPiS_S_, .Lfunc_end2-_Z33__device_stub__per_element_kerneliiPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14per_row_kerneliiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17per_column_kerneliiPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18per_element_kerneliiPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14per_row_kerneliiPiS_S_,@object # @_Z14per_row_kerneliiPiS_S_
.section .rodata,"a",@progbits
.globl _Z14per_row_kerneliiPiS_S_
.p2align 3, 0x0
_Z14per_row_kerneliiPiS_S_:
.quad _Z29__device_stub__per_row_kerneliiPiS_S_
.size _Z14per_row_kerneliiPiS_S_, 8
.type _Z17per_column_kerneliiPiS_S_,@object # @_Z17per_column_kerneliiPiS_S_
.globl _Z17per_column_kerneliiPiS_S_
.p2align 3, 0x0
_Z17per_column_kerneliiPiS_S_:
.quad _Z32__device_stub__per_column_kerneliiPiS_S_
.size _Z17per_column_kerneliiPiS_S_, 8
.type _Z18per_element_kerneliiPiS_S_,@object # @_Z18per_element_kerneliiPiS_S_
.globl _Z18per_element_kerneliiPiS_S_
.p2align 3, 0x0
_Z18per_element_kerneliiPiS_S_:
.quad _Z33__device_stub__per_element_kerneliiPiS_S_
.size _Z18per_element_kerneliiPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14per_row_kerneliiPiS_S_"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17per_column_kerneliiPiS_S_"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18per_element_kerneliiPiS_S_"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__per_row_kerneliiPiS_S_
.addrsig_sym _Z32__device_stub__per_column_kerneliiPiS_S_
.addrsig_sym _Z33__device_stub__per_element_kerneliiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14per_row_kerneliiPiS_S_
.addrsig_sym _Z17per_column_kerneliiPiS_S_
.addrsig_sym _Z18per_element_kerneliiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001254a4_00000000-6_CS20M027.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_
.type _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_, @function
_Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14per_row_kerneliiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_, .-_Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_
.globl _Z14per_row_kerneliiPiS_S_
.type _Z14per_row_kerneliiPiS_S_, @function
_Z14per_row_kerneliiPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14per_row_kerneliiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14per_row_kerneliiPiS_S_, .-_Z14per_row_kerneliiPiS_S_
.globl _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_
.type _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_, @function
_Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17per_column_kerneliiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_, .-_Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_
.globl _Z17per_column_kerneliiPiS_S_
.type _Z17per_column_kerneliiPiS_S_, @function
_Z17per_column_kerneliiPiS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17per_column_kerneliiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z17per_column_kerneliiPiS_S_, .-_Z17per_column_kerneliiPiS_S_
.globl _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_
.type _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_, @function
_Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18per_element_kerneliiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_, .-_Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_
.globl _Z18per_element_kerneliiPiS_S_
.type _Z18per_element_kerneliiPiS_S_, @function
_Z18per_element_kerneliiPiS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18per_element_kerneliiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z18per_element_kerneliiPiS_S_, .-_Z18per_element_kerneliiPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18per_element_kerneliiPiS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z17per_column_kerneliiPiS_S_"
.LC2:
.string "_Z14per_row_kerneliiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18per_element_kerneliiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17per_column_kerneliiPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14per_row_kerneliiPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CS20M027.hip"
.globl _Z29__device_stub__per_row_kerneliiPiS_S_ # -- Begin function _Z29__device_stub__per_row_kerneliiPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__per_row_kerneliiPiS_S_,@function
_Z29__device_stub__per_row_kerneliiPiS_S_: # @_Z29__device_stub__per_row_kerneliiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14per_row_kerneliiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__per_row_kerneliiPiS_S_, .Lfunc_end0-_Z29__device_stub__per_row_kerneliiPiS_S_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__per_column_kerneliiPiS_S_ # -- Begin function _Z32__device_stub__per_column_kerneliiPiS_S_
.p2align 4, 0x90
.type _Z32__device_stub__per_column_kerneliiPiS_S_,@function
_Z32__device_stub__per_column_kerneliiPiS_S_: # @_Z32__device_stub__per_column_kerneliiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17per_column_kerneliiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__per_column_kerneliiPiS_S_, .Lfunc_end1-_Z32__device_stub__per_column_kerneliiPiS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__per_element_kerneliiPiS_S_ # -- Begin function _Z33__device_stub__per_element_kerneliiPiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__per_element_kerneliiPiS_S_,@function
_Z33__device_stub__per_element_kerneliiPiS_S_: # @_Z33__device_stub__per_element_kerneliiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18per_element_kerneliiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__per_element_kerneliiPiS_S_, .Lfunc_end2-_Z33__device_stub__per_element_kerneliiPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14per_row_kerneliiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17per_column_kerneliiPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18per_element_kerneliiPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14per_row_kerneliiPiS_S_,@object # @_Z14per_row_kerneliiPiS_S_
.section .rodata,"a",@progbits
.globl _Z14per_row_kerneliiPiS_S_
.p2align 3, 0x0
_Z14per_row_kerneliiPiS_S_:
.quad _Z29__device_stub__per_row_kerneliiPiS_S_
.size _Z14per_row_kerneliiPiS_S_, 8
.type _Z17per_column_kerneliiPiS_S_,@object # @_Z17per_column_kerneliiPiS_S_
.globl _Z17per_column_kerneliiPiS_S_
.p2align 3, 0x0
_Z17per_column_kerneliiPiS_S_:
.quad _Z32__device_stub__per_column_kerneliiPiS_S_
.size _Z17per_column_kerneliiPiS_S_, 8
.type _Z18per_element_kerneliiPiS_S_,@object # @_Z18per_element_kerneliiPiS_S_
.globl _Z18per_element_kerneliiPiS_S_
.p2align 3, 0x0
_Z18per_element_kerneliiPiS_S_:
.quad _Z33__device_stub__per_element_kerneliiPiS_S_
.size _Z18per_element_kerneliiPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14per_row_kerneliiPiS_S_"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17per_column_kerneliiPiS_S_"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18per_element_kerneliiPiS_S_"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__per_row_kerneliiPiS_S_
.addrsig_sym _Z32__device_stub__per_column_kerneliiPiS_S_
.addrsig_sym _Z33__device_stub__per_element_kerneliiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14per_row_kerneliiPiS_S_
.addrsig_sym _Z17per_column_kerneliiPiS_S_
.addrsig_sym _Z18per_element_kerneliiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "k_hilbert.cuh"
namespace timemachine {
// k_coords_to_kv_gather assigns coordinates to the relevant hilbert curve bin.
// Note that this kernel requires the use of double precision as imaging into the home box
// with float precision can result in the final coordinates being outside of the home box for
// coordinates with large magnitudes.
void __global__ k_coords_to_kv_gather(
const int N,
const unsigned int *__restrict__ atom_idxs,
const double *__restrict__ coords,
const double *__restrict__ box,
const unsigned int *__restrict__ bin_to_idx,
unsigned int *__restrict__ keys,
unsigned int *__restrict__ vals) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
const double bx = box[0 * 3 + 0];
const double by = box[1 * 3 + 1];
const double bz = box[2 * 3 + 2];
const double inv_bx = 1 / bx;
const double inv_by = 1 / by;
const double inv_bz = 1 / bz;
const double inv_bin_width = min(min(inv_bx, inv_by), inv_bz) * (HILBERT_GRID_DIM - 1.0);
while (idx < N) {
int atom_idx = atom_idxs[idx];
double x = coords[atom_idx * 3 + 0];
double y = coords[atom_idx * 3 + 1];
double z = coords[atom_idx * 3 + 2];
// floor is used in place of nearbyint here to ensure all particles are imaged into the home box. This differs
// from distances calculations where the nearest possible image is calculated rather than imaging into
// the home box.
x -= bx * floor(x * inv_bx);
y -= by * floor(y * inv_by);
z -= bz * floor(z * inv_bz);
unsigned int bin_x = static_cast<unsigned int>(x * inv_bin_width);
unsigned int bin_y = static_cast<unsigned int>(y * inv_bin_width);
unsigned int bin_z = static_cast<unsigned int>(z * inv_bin_width);
keys[idx] = bin_to_idx[bin_x * HILBERT_GRID_DIM * HILBERT_GRID_DIM + bin_y * HILBERT_GRID_DIM + bin_z];
// uncomment below if you want to preserve the atom ordering
// keys[idx] = atom_idx;
vals[idx] = atom_idx;
idx += gridDim.x * blockDim.x;
}
}
} // namespace timemachine | code for sm_80
Function : _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0d7624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64.CONSTANT R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e9b00 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x001fe200078e020b */
/*0080*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x004e220000001800 */
/*0090*/ IADD3 R4, R3, 0x300402, RZ ; /* 0x0030040203047810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*00b0*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*00c0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*00d0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*00e0*/ DFMA R8, -R2, R6, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000106 */
/*00f0*/ DFMA R4, R6, R8, R6 ; /* 0x000000080604722b */
/* 0x0010620000000006 */
/*0100*/ @P0 BRA 0x190 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0110*/ LOP3.LUT R18, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03127812 */
/* 0x000fe200078ec0ff */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0130*/ MOV R16, 0x170 ; /* 0x0000017000107802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0150*/ IADD3 R18, R18, -0x100000, RZ ; /* 0xfff0000012127810 */
/* 0x000fe40007ffe0ff */
/*0160*/ CALL.REL.NOINC 0x740 ; /* 0x000005d000007944 */
/* 0x003fea0003c00000 */
/*0170*/ MOV R4, R14 ; /* 0x0000000e00047202 */
/* 0x003fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0190*/ LDG.E.64.CONSTANT R6, [R12.64+0x20] ; /* 0x000020040c067981 */
/* 0x001ea4000c1e9b00 */
/*01a0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x004e220000001800 */
/*01b0*/ IADD3 R8, R7, 0x300402, RZ ; /* 0x0030040207087810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ; /* 0x004004020800780b */
/* 0x000fe40003f0e200 */
/*01d0*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*01e0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*01f0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0200*/ DFMA R14, -R6, R10, 1 ; /* 0x3ff00000060e742b */
/* 0x001e0c000000010a */
/*0210*/ DFMA R8, R10, R14, R10 ; /* 0x0000000e0a08722b */
/* 0x0010a2000000000a */
/*0220*/ @P0 BRA 0x2b0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0230*/ LOP3.LUT R18, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07127812 */
/* 0x000fe200078ec0ff */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e0006 */
/*0250*/ MOV R16, 0x290 ; /* 0x0000029000107802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*0270*/ IADD3 R18, R18, -0x100000, RZ ; /* 0xfff0000012127810 */
/* 0x000fe40007ffe0ff */
/*0280*/ CALL.REL.NOINC 0x740 ; /* 0x000004b000007944 */
/* 0x006fea0003c00000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x003fe200078e000e */
/*02a0*/ MOV R9, R15 ; /* 0x0000000f00097202 */
/* 0x000fe40000000f00 */
/*02b0*/ LDG.E.64.CONSTANT R12, [R12.64+0x40] ; /* 0x000040040c0c7981 */
/* 0x000ee4000c1e9b00 */
/*02c0*/ MUFU.RCP64H R11, R13 ; /* 0x0000000d000b7308 */
/* 0x009e220000001800 */
/*02d0*/ IADD3 R10, R13, 0x300402, RZ ; /* 0x003004020d0a7810 */
/* 0x000fc80007ffe0ff */
/*02e0*/ FSETP.GEU.AND P0, PT, |R10|, 5.8789094863358348022e-39, PT ; /* 0x004004020a00780b */
/* 0x000fe40003f0e200 */
/*02f0*/ DFMA R14, -R12, R10, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c000000010a */
/*0300*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0310*/ DFMA R14, R10, R14, R10 ; /* 0x0000000e0a0e722b */
/* 0x001e0c000000000a */
/*0320*/ DFMA R16, -R12, R14, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c000000010e */
/*0330*/ DFMA R14, R14, R16, R14 ; /* 0x000000100e0e722b */
/* 0x0010e2000000000e */
/*0340*/ @P0 BRA 0x3b0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT R18, R13, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0d127812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0370*/ MOV R16, 0x3b0 ; /* 0x000003b000107802 */
/* 0x001fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000d */
/*0390*/ IADD3 R18, R18, -0x100000, RZ ; /* 0xfff0000012127810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ CALL.REL.NOINC 0x740 ; /* 0x0000039000007944 */
/* 0x00efea0003c00000 */
/*03b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ DSETP.MIN.AND P0, P1, R8, R4, PT ; /* 0x000000040800722a */
/* 0x006e620003900000 */
/*03e0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0009 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0005 */
/*0400*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0004 */
/*0410*/ FSEL R19, R10, R17, P0 ; /* 0x000000110a137208 */
/* 0x002fe40000000000 */
/*0420*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fc80000000f00 */
/*0430*/ @P1 LOP3.LUT R19, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011131812 */
/* 0x000fe400078efcff */
/*0440*/ SEL R10, R10, R11, P0 ; /* 0x0000000b0a0a7207 */
/* 0x000fe40000000000 */
/*0450*/ MOV R17, R14 ; /* 0x0000000e00117202 */
/* 0x008fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0013 */
/*0470*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x000fe400078e000f */
/*0480*/ IMAD.MOV.U32 R16, RZ, RZ, R11 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000b */
/*0490*/ DSETP.MIN.AND P0, P1, R10, R14, PT ; /* 0x0000000e0a00722a */
/* 0x000e0c0003900000 */
/*04a0*/ FSEL R21, R16, R19, P0 ; /* 0x0000001310157208 */
/* 0x001fe40000000000 */
/*04b0*/ SEL R10, R10, R17, P0 ; /* 0x000000110a0a7207 */
/* 0x000fcc0000000000 */
/*04c0*/ @P1 LOP3.LUT R21, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000013151812 */
/* 0x000fca00078efcff */
/*04d0*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e0015 */
/*04e0*/ DMUL R10, R10, 127 ; /* 0x405fc0000a0a7828 */
/* 0x000e080000000000 */
/*04f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff157424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE R22, R0, R21, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x001fca00078e0215 */
/*0510*/ LDG.E.CONSTANT R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000ea2000c1e9900 */
/*0520*/ IMAD.MOV.U32 R27, RZ, RZ, 0x8 ; /* 0x00000008ff1b7424 */
/* 0x000fe400078e00ff */
/*0530*/ IMAD R26, R20, 0x3, RZ ; /* 0x00000003141a7824 */
/* 0x004fc800078e02ff */
/*0540*/ IMAD.WIDE R26, R26, R27, c[0x0][0x170] ; /* 0x00005c001a1a7625 */
/* 0x000fca00078e021b */
/*0550*/ LDG.E.64.CONSTANT R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000ea8000c1e9b00 */
/*0560*/ LDG.E.64.CONSTANT R24, [R26.64+0x8] ; /* 0x000008041a187981 */
/* 0x000ee8000c1e9b00 */
/*0570*/ LDG.E.64.CONSTANT R16, [R26.64+0x10] ; /* 0x000010041a107981 */
/* 0x000f22000c1e9b00 */
/*0580*/ DMUL R28, R18, R4 ; /* 0x00000004121c7228 */
/* 0x004e540000000000 */
/*0590*/ FRND.F64.FLOOR R28, R28 ; /* 0x0000001c001c7313 */
/* 0x002e640000305800 */
/*05a0*/ DFMA R18, -R2, R28, R18 ; /* 0x0000001c0212722b */
/* 0x002e480000000112 */
/*05b0*/ DMUL R28, R24, R8 ; /* 0x00000008181c7228 */
/* 0x008e880000000000 */
/*05c0*/ DMUL R18, R10, R18 ; /* 0x000000120a127228 */
/* 0x003e240000000000 */
/*05d0*/ FRND.F64.FLOOR R22, R28 ; /* 0x0000001c00167313 */
/* 0x004e700000305800 */
/*05e0*/ F2I.U32.F64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x001fe2000030d000 */
/*05f0*/ DFMA R24, -R6, R22, R24 ; /* 0x000000160618722b */
/* 0x002e080000000118 */
/*0600*/ DMUL R22, R16, R14 ; /* 0x0000000e10167228 */
/* 0x010e480000000000 */
/*0610*/ DMUL R24, R10, R24 ; /* 0x000000180a187228 */
/* 0x001e0c0000000000 */
/*0620*/ FRND.F64.FLOOR R22, R22 ; /* 0x0000001600167313 */
/* 0x002e700000305800 */
/*0630*/ F2I.U32.F64.TRUNC R25, R24 ; /* 0x0000001800197311 */
/* 0x001e22000030d000 */
/*0640*/ DFMA R16, -R12, R22, R16 ; /* 0x000000160c10722b */
/* 0x002e4c0000000110 */
/*0650*/ DMUL R16, R10, R16 ; /* 0x000000100a107228 */
/* 0x002e620000000000 */
/*0660*/ LEA R27, R18, R25, 0x7 ; /* 0x00000019121b7211 */
/* 0x001fd200078e38ff */
/*0670*/ F2I.U32.F64.TRUNC R16, R16 ; /* 0x0000001000107311 */
/* 0x002e24000030d000 */
/*0680*/ IMAD.U32 R26, R27, 0x80, R16 ; /* 0x000000801b1a7824 */
/* 0x001fc800078e0010 */
/*0690*/ IMAD.WIDE.U32 R26, R26, R21, c[0x0][0x180] ; /* 0x000060001a1a7625 */
/* 0x000fcc00078e0015 */
/*06a0*/ LDG.E.CONSTANT R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea2000c1e9900 */
/*06b0*/ IMAD.WIDE R22, R0, R21, c[0x0][0x188] ; /* 0x0000620000167625 */
/* 0x000fc800078e0215 */
/*06c0*/ IMAD.WIDE R18, R0, R21, c[0x0][0x190] ; /* 0x0000640000127625 */
/* 0x000fc800078e0215 */
/*06d0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff157624 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD R0, R21, c[0x0][0x0], R0 ; /* 0x0000000015007a24 */
/* 0x000fca00078e0200 */
/*06f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0700*/ STG.E [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0041e8000c101904 */
/*0710*/ STG.E [R18.64], R20 ; /* 0x0000001412007986 */
/* 0x0001f0000c101904 */
/*0720*/ @!P0 BRA 0x4f0 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f0c200 */
/*0750*/ @P0 BRA 0x940 ; /* 0x000001e000000947 */
/* 0x001fea0003800000 */
/*0760*/ LOP3.LUT R17, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b117812 */
/* 0x000fc800078ec0ff */
/*0770*/ IADD3 R14, R17, -0x1, RZ ; /* 0xffffffff110e7810 */
/* 0x000fc80007ffe0ff */
/*0780*/ ISETP.GE.U32.AND P0, PT, R14, 0x7fefffff, PT ; /* 0x7fefffff0e00780c */
/* 0x000fda0003f06070 */
/*0790*/ @P0 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff000000b0f0812 */
/* 0x000fe200078e3cff */
/*07a0*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe200078e00ff */
/*07b0*/ @P0 BRA 0x960 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R17, 0x1000001, PT ; /* 0x010000011100780c */
/* 0x000fda0003f06070 */
/*07d0*/ @!P0 BRA 0x8b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*07e0*/ IADD3 R15, R11, -0x3fe00000, RZ ; /* 0xc02000000b0f7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fe40000000f00 */
/*0800*/ MUFU.RCP64H R19, R15 ; /* 0x0000000f00137308 */
/* 0x000e280000001800 */
/*0810*/ DFMA R20, -R14, R18, 1 ; /* 0x3ff000000e14742b */
/* 0x001e0c0000000112 */
/*0820*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e0c0000000014 */
/*0830*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e0c0000000012 */
/*0840*/ DFMA R18, -R14, R20, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0c0000000114 */
/*0850*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x001e0c0000000014 */
/*0860*/ DMUL R18, R18, 2.2250738585072013831e-308 ; /* 0x0010000012127828 */
/* 0x001e0c0000000000 */
/*0870*/ DFMA R10, -R10, R18, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e0c0000000112 */
/*0880*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0890*/ DFMA R14, R18, R10, R18 ; /* 0x0000000a120e722b */
/* 0x0010620000000012 */
/*08a0*/ BRA 0x960 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*08b0*/ DMUL R10, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0a7828 */
/* 0x000e0c0000000000 */
/*08c0*/ MUFU.RCP64H R19, R11 ; /* 0x0000000b00137308 */
/* 0x001e240000001800 */
/*08d0*/ DFMA R14, -R10, R18, 1 ; /* 0x3ff000000a0e742b */
/* 0x001e0c0000000112 */
/*08e0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*08f0*/ DFMA R14, R18, R14, R18 ; /* 0x0000000e120e722b */
/* 0x001e0c0000000012 */
/*0900*/ DFMA R18, -R10, R14, 1 ; /* 0x3ff000000a12742b */
/* 0x001e0c000000010e */
/*0910*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*0920*/ DMUL R14, R14, 8.11296384146066816958e+31 ; /* 0x469000000e0e7828 */
/* 0x001e220000000000 */
/*0930*/ BRA 0x960 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0f7812 */
/* 0x000fe200078efcff */
/*0950*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e000a */
/*0960*/ IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; /* 0x00000000ff117424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff68010007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "k_hilbert.cuh"
namespace timemachine {
// k_coords_to_kv_gather assigns coordinates to the relevant hilbert curve bin.
// Note that this kernel requires the use of double precision as imaging into the home box
// with float precision can result in the final coordinates being outside of the home box for
// coordinates with large magnitudes.
void __global__ k_coords_to_kv_gather(
const int N,
const unsigned int *__restrict__ atom_idxs,
const double *__restrict__ coords,
const double *__restrict__ box,
const unsigned int *__restrict__ bin_to_idx,
unsigned int *__restrict__ keys,
unsigned int *__restrict__ vals) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
const double bx = box[0 * 3 + 0];
const double by = box[1 * 3 + 1];
const double bz = box[2 * 3 + 2];
const double inv_bx = 1 / bx;
const double inv_by = 1 / by;
const double inv_bz = 1 / bz;
const double inv_bin_width = min(min(inv_bx, inv_by), inv_bz) * (HILBERT_GRID_DIM - 1.0);
while (idx < N) {
int atom_idx = atom_idxs[idx];
double x = coords[atom_idx * 3 + 0];
double y = coords[atom_idx * 3 + 1];
double z = coords[atom_idx * 3 + 2];
// floor is used in place of nearbyint here to ensure all particles are imaged into the home box. This differs
// from distances calculations where the nearest possible image is calculated rather than imaging into
// the home box.
x -= bx * floor(x * inv_bx);
y -= by * floor(y * inv_by);
z -= bz * floor(z * inv_bz);
unsigned int bin_x = static_cast<unsigned int>(x * inv_bin_width);
unsigned int bin_y = static_cast<unsigned int>(y * inv_bin_width);
unsigned int bin_z = static_cast<unsigned int>(z * inv_bin_width);
keys[idx] = bin_to_idx[bin_x * HILBERT_GRID_DIM * HILBERT_GRID_DIM + bin_y * HILBERT_GRID_DIM + bin_z];
// uncomment below if you want to preserve the atom ordering
// keys[idx] = atom_idx;
vals[idx] = atom_idx;
idx += gridDim.x * blockDim.x;
}
}
} // namespace timemachine | .file "tmpxft_0016695e_00000000-6_k_hilbert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_
.type _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_, @function
_Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
movq 208(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_, .-_Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_
.globl _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.type _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, @function
_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, .-_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "k_hilbert.cuh"
namespace timemachine {
// k_coords_to_kv_gather assigns coordinates to the relevant hilbert curve bin.
// Note that this kernel requires the use of double precision as imaging into the home box
// with float precision can result in the final coordinates being outside of the home box for
// coordinates with large magnitudes.
void __global__ k_coords_to_kv_gather(
const int N,
const unsigned int *__restrict__ atom_idxs,
const double *__restrict__ coords,
const double *__restrict__ box,
const unsigned int *__restrict__ bin_to_idx,
unsigned int *__restrict__ keys,
unsigned int *__restrict__ vals) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
const double bx = box[0 * 3 + 0];
const double by = box[1 * 3 + 1];
const double bz = box[2 * 3 + 2];
const double inv_bx = 1 / bx;
const double inv_by = 1 / by;
const double inv_bz = 1 / bz;
const double inv_bin_width = min(min(inv_bx, inv_by), inv_bz) * (HILBERT_GRID_DIM - 1.0);
while (idx < N) {
int atom_idx = atom_idxs[idx];
double x = coords[atom_idx * 3 + 0];
double y = coords[atom_idx * 3 + 1];
double z = coords[atom_idx * 3 + 2];
// floor is used in place of nearbyint here to ensure all particles are imaged into the home box. This differs
// from distances calculations where the nearest possible image is calculated rather than imaging into
// the home box.
x -= bx * floor(x * inv_bx);
y -= by * floor(y * inv_by);
z -= bz * floor(z * inv_bz);
unsigned int bin_x = static_cast<unsigned int>(x * inv_bin_width);
unsigned int bin_y = static_cast<unsigned int>(y * inv_bin_width);
unsigned int bin_z = static_cast<unsigned int>(z * inv_bin_width);
keys[idx] = bin_to_idx[bin_x * HILBERT_GRID_DIM * HILBERT_GRID_DIM + bin_y * HILBERT_GRID_DIM + bin_z];
// uncomment below if you want to preserve the atom ordering
// keys[idx] = atom_idx;
vals[idx] = atom_idx;
idx += gridDim.x * blockDim.x;
}
}
} // namespace timemachine | #include <hip/hip_runtime.h>
#include "k_hilbert.cuh"
namespace timemachine {
// k_coords_to_kv_gather assigns coordinates to the relevant hilbert curve bin.
// Note that this kernel requires the use of double precision as imaging into the home box
// with float precision can result in the final coordinates being outside of the home box for
// coordinates with large magnitudes.
void __global__ k_coords_to_kv_gather(
const int N,
const unsigned int *__restrict__ atom_idxs,
const double *__restrict__ coords,
const double *__restrict__ box,
const unsigned int *__restrict__ bin_to_idx,
unsigned int *__restrict__ keys,
unsigned int *__restrict__ vals) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
const double bx = box[0 * 3 + 0];
const double by = box[1 * 3 + 1];
const double bz = box[2 * 3 + 2];
const double inv_bx = 1 / bx;
const double inv_by = 1 / by;
const double inv_bz = 1 / bz;
const double inv_bin_width = min(min(inv_bx, inv_by), inv_bz) * (HILBERT_GRID_DIM - 1.0);
while (idx < N) {
int atom_idx = atom_idxs[idx];
double x = coords[atom_idx * 3 + 0];
double y = coords[atom_idx * 3 + 1];
double z = coords[atom_idx * 3 + 2];
// floor is used in place of nearbyint here to ensure all particles are imaged into the home box. This differs
// from distances calculations where the nearest possible image is calculated rather than imaging into
// the home box.
x -= bx * floor(x * inv_bx);
y -= by * floor(y * inv_by);
z -= bz * floor(z * inv_bz);
unsigned int bin_x = static_cast<unsigned int>(x * inv_bin_width);
unsigned int bin_y = static_cast<unsigned int>(y * inv_bin_width);
unsigned int bin_z = static_cast<unsigned int>(z * inv_bin_width);
keys[idx] = bin_to_idx[bin_x * HILBERT_GRID_DIM * HILBERT_GRID_DIM + bin_y * HILBERT_GRID_DIM + bin_z];
// uncomment below if you want to preserve the atom ordering
// keys[idx] = atom_idx;
vals[idx] = atom_idx;
idx += gridDim.x * blockDim.x;
}
}
} // namespace timemachine |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "k_hilbert.cuh"
namespace timemachine {
// k_coords_to_kv_gather assigns coordinates to the relevant hilbert curve bin.
// Note that this kernel requires the use of double precision as imaging into the home box
// with float precision can result in the final coordinates being outside of the home box for
// coordinates with large magnitudes.
void __global__ k_coords_to_kv_gather(
const int N,
const unsigned int *__restrict__ atom_idxs,
const double *__restrict__ coords,
const double *__restrict__ box,
const unsigned int *__restrict__ bin_to_idx,
unsigned int *__restrict__ keys,
unsigned int *__restrict__ vals) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
const double bx = box[0 * 3 + 0];
const double by = box[1 * 3 + 1];
const double bz = box[2 * 3 + 2];
const double inv_bx = 1 / bx;
const double inv_by = 1 / by;
const double inv_bz = 1 / bz;
const double inv_bin_width = min(min(inv_bx, inv_by), inv_bz) * (HILBERT_GRID_DIM - 1.0);
while (idx < N) {
int atom_idx = atom_idxs[idx];
double x = coords[atom_idx * 3 + 0];
double y = coords[atom_idx * 3 + 1];
double z = coords[atom_idx * 3 + 2];
// floor is used in place of nearbyint here to ensure all particles are imaged into the home box. This differs
// from distances calculations where the nearest possible image is calculated rather than imaging into
// the home box.
x -= bx * floor(x * inv_bx);
y -= by * floor(y * inv_by);
z -= bz * floor(z * inv_bz);
unsigned int bin_x = static_cast<unsigned int>(x * inv_bin_width);
unsigned int bin_y = static_cast<unsigned int>(y * inv_bin_width);
unsigned int bin_z = static_cast<unsigned int>(z * inv_bin_width);
keys[idx] = bin_to_idx[bin_x * HILBERT_GRID_DIM * HILBERT_GRID_DIM + bin_y * HILBERT_GRID_DIM + bin_z];
// uncomment below if you want to preserve the atom ordering
// keys[idx] = atom_idx;
vals[idx] = atom_idx;
idx += gridDim.x * blockDim.x;
}
}
} // namespace timemachine | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.globl _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.p2align 8
.type _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_,@function
_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s20, s[0:1], 0x0
s_add_u32 s12, s0, 56
s_addc_u32 s13, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s21, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s21, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s20, v1
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b64 s[16:17], s[8:9], 0x0
s_load_b64 s[18:19], s[8:9], 0x20
s_load_b64 s[8:9], s[8:9], 0x40
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[2:3], null, s[16:17], s[16:17], 1.0
v_div_scale_f64 v[4:5], null, s[18:19], s[18:19], 1.0
v_div_scale_f64 v[8:9], null, s[8:9], s[8:9], 1.0
v_div_scale_f64 v[18:19], vcc_lo, 1.0, s[16:17], 1.0
v_div_scale_f64 v[20:21], s2, 1.0, s[18:19], 1.0
v_rcp_f64_e32 v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f64_e32 v[10:11], v[4:5]
v_rcp_f64_e32 v[12:13], v[8:9]
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], -v[2:3], v[6:7], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[4:5], v[10:11], 1.0
v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], -v[2:3], v[6:7], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], -v[4:5], v[10:11], 1.0
v_fma_f64 v[6:7], v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
v_div_scale_f64 v[14:15], s3, 1.0, s[8:9], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[22:23], v[18:19], v[6:7]
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[16:17], v[20:21], v[10:11]
v_fma_f64 v[2:3], -v[2:3], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[18:19], v[14:15], v[12:13]
v_fma_f64 v[4:5], -v[4:5], v[16:17], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[22:23]
s_mov_b32 vcc_lo, s2
v_fma_f64 v[6:7], -v[8:9], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[4:5], v[10:11], v[16:17]
s_mov_b32 vcc_lo, s3
s_load_b32 s2, s[12:13], 0x0
s_load_b128 s[12:15], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s21
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[3:4], v[2:3], s[16:17], 1.0
v_div_fmas_f64 v[10:11], v[6:7], v[12:13], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[5:6], v[8:9], s[18:19], 1.0
v_mov_b32_e32 v12, 0
v_div_fixup_f64 v[7:8], v[10:11], s[8:9], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_f64 v[9:10], v[3:4], v[5:6]
v_min_f64 v[9:10], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], 0x405fc000
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[17:18], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v13, vcc_lo, s4, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
global_load_b32 v0, v[13:14], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v13, v0, 1, v0
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v19, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v14, vcc_lo
s_clause 0x1
global_load_b128 v[13:16], v[19:20], off
global_load_b64 v[19:20], v[19:20], off offset:16
s_waitcnt vmcnt(1)
v_mul_f64 v[21:22], v[3:4], v[13:14]
v_mul_f64 v[23:24], v[5:6], v[15:16]
s_waitcnt vmcnt(0)
v_mul_f64 v[25:26], v[7:8], v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f64_e32 v[21:22], v[21:22]
v_floor_f64_e32 v[23:24], v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f64_e32 v[25:26], v[25:26]
v_fma_f64 v[13:14], -s[16:17], v[21:22], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], -s[18:19], v[23:24], v[15:16]
v_fma_f64 v[19:20], -s[8:9], v[25:26], v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[13:14], v[9:10], v[13:14]
v_mul_f64 v[15:16], v[9:10], v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[19:20], v[9:10], v[19:20]
v_cvt_u32_f64_e32 v2, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f64_e32 v11, v[15:16]
v_cvt_u32_f64_e32 v13, v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v2, 14, v2
v_lshlrev_b32_e32 v11, 7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v11, v11, v2, v13
v_lshlrev_b64 v[13:14], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s20, v1
global_load_b32 v2, v[13:14], off
v_add_co_u32 v13, s0, s12, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s13, v18, s0
v_add_co_u32 v15, s0, s14, v17
v_add_co_ci_u32_e64 v16, s0, s15, v18, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b32 v[13:14], v2, off
global_store_b32 v[15:16], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, .Lfunc_end0-_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "k_hilbert.cuh"
namespace timemachine {
// k_coords_to_kv_gather assigns coordinates to the relevant hilbert curve bin.
// Note that this kernel requires the use of double precision as imaging into the home box
// with float precision can result in the final coordinates being outside of the home box for
// coordinates with large magnitudes.
void __global__ k_coords_to_kv_gather(
const int N,
const unsigned int *__restrict__ atom_idxs,
const double *__restrict__ coords,
const double *__restrict__ box,
const unsigned int *__restrict__ bin_to_idx,
unsigned int *__restrict__ keys,
unsigned int *__restrict__ vals) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
const double bx = box[0 * 3 + 0];
const double by = box[1 * 3 + 1];
const double bz = box[2 * 3 + 2];
const double inv_bx = 1 / bx;
const double inv_by = 1 / by;
const double inv_bz = 1 / bz;
const double inv_bin_width = min(min(inv_bx, inv_by), inv_bz) * (HILBERT_GRID_DIM - 1.0);
while (idx < N) {
int atom_idx = atom_idxs[idx];
double x = coords[atom_idx * 3 + 0];
double y = coords[atom_idx * 3 + 1];
double z = coords[atom_idx * 3 + 2];
// floor is used in place of nearbyint here to ensure all particles are imaged into the home box. This differs
// from distances calculations where the nearest possible image is calculated rather than imaging into
// the home box.
x -= bx * floor(x * inv_bx);
y -= by * floor(y * inv_by);
z -= bz * floor(z * inv_bz);
unsigned int bin_x = static_cast<unsigned int>(x * inv_bin_width);
unsigned int bin_y = static_cast<unsigned int>(y * inv_bin_width);
unsigned int bin_z = static_cast<unsigned int>(z * inv_bin_width);
keys[idx] = bin_to_idx[bin_x * HILBERT_GRID_DIM * HILBERT_GRID_DIM + bin_y * HILBERT_GRID_DIM + bin_z];
// uncomment below if you want to preserve the atom ordering
// keys[idx] = atom_idx;
vals[idx] = atom_idx;
idx += gridDim.x * blockDim.x;
}
}
} // namespace timemachine | .text
.file "k_hilbert.hip"
.globl _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_ # -- Begin function _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.p2align 4, 0x90
.type _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_,@function
_ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_: # @_ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, .Lfunc_end0-_ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_,@object # @_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.section .rodata,"a",@progbits
.globl _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.p2align 3, 0x0
_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_:
.quad _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.size _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_"
.size .L__unnamed_1, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0d7624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64.CONSTANT R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e9b00 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x001fe200078e020b */
/*0080*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x004e220000001800 */
/*0090*/ IADD3 R4, R3, 0x300402, RZ ; /* 0x0030040203047810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*00b0*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*00c0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*00d0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*00e0*/ DFMA R8, -R2, R6, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000106 */
/*00f0*/ DFMA R4, R6, R8, R6 ; /* 0x000000080604722b */
/* 0x0010620000000006 */
/*0100*/ @P0 BRA 0x190 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0110*/ LOP3.LUT R18, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03127812 */
/* 0x000fe200078ec0ff */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0130*/ MOV R16, 0x170 ; /* 0x0000017000107802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0150*/ IADD3 R18, R18, -0x100000, RZ ; /* 0xfff0000012127810 */
/* 0x000fe40007ffe0ff */
/*0160*/ CALL.REL.NOINC 0x740 ; /* 0x000005d000007944 */
/* 0x003fea0003c00000 */
/*0170*/ MOV R4, R14 ; /* 0x0000000e00047202 */
/* 0x003fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0190*/ LDG.E.64.CONSTANT R6, [R12.64+0x20] ; /* 0x000020040c067981 */
/* 0x001ea4000c1e9b00 */
/*01a0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x004e220000001800 */
/*01b0*/ IADD3 R8, R7, 0x300402, RZ ; /* 0x0030040207087810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ; /* 0x004004020800780b */
/* 0x000fe40003f0e200 */
/*01d0*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*01e0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*01f0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0200*/ DFMA R14, -R6, R10, 1 ; /* 0x3ff00000060e742b */
/* 0x001e0c000000010a */
/*0210*/ DFMA R8, R10, R14, R10 ; /* 0x0000000e0a08722b */
/* 0x0010a2000000000a */
/*0220*/ @P0 BRA 0x2b0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0230*/ LOP3.LUT R18, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07127812 */
/* 0x000fe200078ec0ff */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e0006 */
/*0250*/ MOV R16, 0x290 ; /* 0x0000029000107802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*0270*/ IADD3 R18, R18, -0x100000, RZ ; /* 0xfff0000012127810 */
/* 0x000fe40007ffe0ff */
/*0280*/ CALL.REL.NOINC 0x740 ; /* 0x000004b000007944 */
/* 0x006fea0003c00000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x003fe200078e000e */
/*02a0*/ MOV R9, R15 ; /* 0x0000000f00097202 */
/* 0x000fe40000000f00 */
/*02b0*/ LDG.E.64.CONSTANT R12, [R12.64+0x40] ; /* 0x000040040c0c7981 */
/* 0x000ee4000c1e9b00 */
/*02c0*/ MUFU.RCP64H R11, R13 ; /* 0x0000000d000b7308 */
/* 0x009e220000001800 */
/*02d0*/ IADD3 R10, R13, 0x300402, RZ ; /* 0x003004020d0a7810 */
/* 0x000fc80007ffe0ff */
/*02e0*/ FSETP.GEU.AND P0, PT, |R10|, 5.8789094863358348022e-39, PT ; /* 0x004004020a00780b */
/* 0x000fe40003f0e200 */
/*02f0*/ DFMA R14, -R12, R10, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c000000010a */
/*0300*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0310*/ DFMA R14, R10, R14, R10 ; /* 0x0000000e0a0e722b */
/* 0x001e0c000000000a */
/*0320*/ DFMA R16, -R12, R14, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c000000010e */
/*0330*/ DFMA R14, R14, R16, R14 ; /* 0x000000100e0e722b */
/* 0x0010e2000000000e */
/*0340*/ @P0 BRA 0x3b0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT R18, R13, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0d127812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0370*/ MOV R16, 0x3b0 ; /* 0x000003b000107802 */
/* 0x001fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000d */
/*0390*/ IADD3 R18, R18, -0x100000, RZ ; /* 0xfff0000012127810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ CALL.REL.NOINC 0x740 ; /* 0x0000039000007944 */
/* 0x00efea0003c00000 */
/*03b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ DSETP.MIN.AND P0, P1, R8, R4, PT ; /* 0x000000040800722a */
/* 0x006e620003900000 */
/*03e0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0009 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0005 */
/*0400*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0004 */
/*0410*/ FSEL R19, R10, R17, P0 ; /* 0x000000110a137208 */
/* 0x002fe40000000000 */
/*0420*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fc80000000f00 */
/*0430*/ @P1 LOP3.LUT R19, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011131812 */
/* 0x000fe400078efcff */
/*0440*/ SEL R10, R10, R11, P0 ; /* 0x0000000b0a0a7207 */
/* 0x000fe40000000000 */
/*0450*/ MOV R17, R14 ; /* 0x0000000e00117202 */
/* 0x008fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0013 */
/*0470*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x000fe400078e000f */
/*0480*/ IMAD.MOV.U32 R16, RZ, RZ, R11 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000b */
/*0490*/ DSETP.MIN.AND P0, P1, R10, R14, PT ; /* 0x0000000e0a00722a */
/* 0x000e0c0003900000 */
/*04a0*/ FSEL R21, R16, R19, P0 ; /* 0x0000001310157208 */
/* 0x001fe40000000000 */
/*04b0*/ SEL R10, R10, R17, P0 ; /* 0x000000110a0a7207 */
/* 0x000fcc0000000000 */
/*04c0*/ @P1 LOP3.LUT R21, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000013151812 */
/* 0x000fca00078efcff */
/*04d0*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e0015 */
/*04e0*/ DMUL R10, R10, 127 ; /* 0x405fc0000a0a7828 */
/* 0x000e080000000000 */
/*04f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff157424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE R22, R0, R21, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x001fca00078e0215 */
/*0510*/ LDG.E.CONSTANT R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000ea2000c1e9900 */
/*0520*/ IMAD.MOV.U32 R27, RZ, RZ, 0x8 ; /* 0x00000008ff1b7424 */
/* 0x000fe400078e00ff */
/*0530*/ IMAD R26, R20, 0x3, RZ ; /* 0x00000003141a7824 */
/* 0x004fc800078e02ff */
/*0540*/ IMAD.WIDE R26, R26, R27, c[0x0][0x170] ; /* 0x00005c001a1a7625 */
/* 0x000fca00078e021b */
/*0550*/ LDG.E.64.CONSTANT R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000ea8000c1e9b00 */
/*0560*/ LDG.E.64.CONSTANT R24, [R26.64+0x8] ; /* 0x000008041a187981 */
/* 0x000ee8000c1e9b00 */
/*0570*/ LDG.E.64.CONSTANT R16, [R26.64+0x10] ; /* 0x000010041a107981 */
/* 0x000f22000c1e9b00 */
/*0580*/ DMUL R28, R18, R4 ; /* 0x00000004121c7228 */
/* 0x004e540000000000 */
/*0590*/ FRND.F64.FLOOR R28, R28 ; /* 0x0000001c001c7313 */
/* 0x002e640000305800 */
/*05a0*/ DFMA R18, -R2, R28, R18 ; /* 0x0000001c0212722b */
/* 0x002e480000000112 */
/*05b0*/ DMUL R28, R24, R8 ; /* 0x00000008181c7228 */
/* 0x008e880000000000 */
/*05c0*/ DMUL R18, R10, R18 ; /* 0x000000120a127228 */
/* 0x003e240000000000 */
/*05d0*/ FRND.F64.FLOOR R22, R28 ; /* 0x0000001c00167313 */
/* 0x004e700000305800 */
/*05e0*/ F2I.U32.F64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x001fe2000030d000 */
/*05f0*/ DFMA R24, -R6, R22, R24 ; /* 0x000000160618722b */
/* 0x002e080000000118 */
/*0600*/ DMUL R22, R16, R14 ; /* 0x0000000e10167228 */
/* 0x010e480000000000 */
/*0610*/ DMUL R24, R10, R24 ; /* 0x000000180a187228 */
/* 0x001e0c0000000000 */
/*0620*/ FRND.F64.FLOOR R22, R22 ; /* 0x0000001600167313 */
/* 0x002e700000305800 */
/*0630*/ F2I.U32.F64.TRUNC R25, R24 ; /* 0x0000001800197311 */
/* 0x001e22000030d000 */
/*0640*/ DFMA R16, -R12, R22, R16 ; /* 0x000000160c10722b */
/* 0x002e4c0000000110 */
/*0650*/ DMUL R16, R10, R16 ; /* 0x000000100a107228 */
/* 0x002e620000000000 */
/*0660*/ LEA R27, R18, R25, 0x7 ; /* 0x00000019121b7211 */
/* 0x001fd200078e38ff */
/*0670*/ F2I.U32.F64.TRUNC R16, R16 ; /* 0x0000001000107311 */
/* 0x002e24000030d000 */
/*0680*/ IMAD.U32 R26, R27, 0x80, R16 ; /* 0x000000801b1a7824 */
/* 0x001fc800078e0010 */
/*0690*/ IMAD.WIDE.U32 R26, R26, R21, c[0x0][0x180] ; /* 0x000060001a1a7625 */
/* 0x000fcc00078e0015 */
/*06a0*/ LDG.E.CONSTANT R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea2000c1e9900 */
/*06b0*/ IMAD.WIDE R22, R0, R21, c[0x0][0x188] ; /* 0x0000620000167625 */
/* 0x000fc800078e0215 */
/*06c0*/ IMAD.WIDE R18, R0, R21, c[0x0][0x190] ; /* 0x0000640000127625 */
/* 0x000fc800078e0215 */
/*06d0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff157624 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD R0, R21, c[0x0][0x0], R0 ; /* 0x0000000015007a24 */
/* 0x000fca00078e0200 */
/*06f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0700*/ STG.E [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0041e8000c101904 */
/*0710*/ STG.E [R18.64], R20 ; /* 0x0000001412007986 */
/* 0x0001f0000c101904 */
/*0720*/ @!P0 BRA 0x4f0 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f0c200 */
/*0750*/ @P0 BRA 0x940 ; /* 0x000001e000000947 */
/* 0x001fea0003800000 */
/*0760*/ LOP3.LUT R17, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b117812 */
/* 0x000fc800078ec0ff */
/*0770*/ IADD3 R14, R17, -0x1, RZ ; /* 0xffffffff110e7810 */
/* 0x000fc80007ffe0ff */
/*0780*/ ISETP.GE.U32.AND P0, PT, R14, 0x7fefffff, PT ; /* 0x7fefffff0e00780c */
/* 0x000fda0003f06070 */
/*0790*/ @P0 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff000000b0f0812 */
/* 0x000fe200078e3cff */
/*07a0*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe200078e00ff */
/*07b0*/ @P0 BRA 0x960 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R17, 0x1000001, PT ; /* 0x010000011100780c */
/* 0x000fda0003f06070 */
/*07d0*/ @!P0 BRA 0x8b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*07e0*/ IADD3 R15, R11, -0x3fe00000, RZ ; /* 0xc02000000b0f7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fe40000000f00 */
/*0800*/ MUFU.RCP64H R19, R15 ; /* 0x0000000f00137308 */
/* 0x000e280000001800 */
/*0810*/ DFMA R20, -R14, R18, 1 ; /* 0x3ff000000e14742b */
/* 0x001e0c0000000112 */
/*0820*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e0c0000000014 */
/*0830*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e0c0000000012 */
/*0840*/ DFMA R18, -R14, R20, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0c0000000114 */
/*0850*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x001e0c0000000014 */
/*0860*/ DMUL R18, R18, 2.2250738585072013831e-308 ; /* 0x0010000012127828 */
/* 0x001e0c0000000000 */
/*0870*/ DFMA R10, -R10, R18, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e0c0000000112 */
/*0880*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0890*/ DFMA R14, R18, R10, R18 ; /* 0x0000000a120e722b */
/* 0x0010620000000012 */
/*08a0*/ BRA 0x960 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*08b0*/ DMUL R10, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0a7828 */
/* 0x000e0c0000000000 */
/*08c0*/ MUFU.RCP64H R19, R11 ; /* 0x0000000b00137308 */
/* 0x001e240000001800 */
/*08d0*/ DFMA R14, -R10, R18, 1 ; /* 0x3ff000000a0e742b */
/* 0x001e0c0000000112 */
/*08e0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*08f0*/ DFMA R14, R18, R14, R18 ; /* 0x0000000e120e722b */
/* 0x001e0c0000000012 */
/*0900*/ DFMA R18, -R10, R14, 1 ; /* 0x3ff000000a12742b */
/* 0x001e0c000000010e */
/*0910*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*0920*/ DMUL R14, R14, 8.11296384146066816958e+31 ; /* 0x469000000e0e7828 */
/* 0x001e220000000000 */
/*0930*/ BRA 0x960 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0f7812 */
/* 0x000fe200078efcff */
/*0950*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e000a */
/*0960*/ IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; /* 0x00000000ff117424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff68010007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.globl _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.p2align 8
.type _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_,@function
_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s20, s[0:1], 0x0
s_add_u32 s12, s0, 56
s_addc_u32 s13, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s21, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s21, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s20, v1
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b64 s[16:17], s[8:9], 0x0
s_load_b64 s[18:19], s[8:9], 0x20
s_load_b64 s[8:9], s[8:9], 0x40
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[2:3], null, s[16:17], s[16:17], 1.0
v_div_scale_f64 v[4:5], null, s[18:19], s[18:19], 1.0
v_div_scale_f64 v[8:9], null, s[8:9], s[8:9], 1.0
v_div_scale_f64 v[18:19], vcc_lo, 1.0, s[16:17], 1.0
v_div_scale_f64 v[20:21], s2, 1.0, s[18:19], 1.0
v_rcp_f64_e32 v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f64_e32 v[10:11], v[4:5]
v_rcp_f64_e32 v[12:13], v[8:9]
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], -v[2:3], v[6:7], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[4:5], v[10:11], 1.0
v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], -v[2:3], v[6:7], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], -v[4:5], v[10:11], 1.0
v_fma_f64 v[6:7], v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
v_div_scale_f64 v[14:15], s3, 1.0, s[8:9], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[22:23], v[18:19], v[6:7]
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[16:17], v[20:21], v[10:11]
v_fma_f64 v[2:3], -v[2:3], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[18:19], v[14:15], v[12:13]
v_fma_f64 v[4:5], -v[4:5], v[16:17], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[22:23]
s_mov_b32 vcc_lo, s2
v_fma_f64 v[6:7], -v[8:9], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[4:5], v[10:11], v[16:17]
s_mov_b32 vcc_lo, s3
s_load_b32 s2, s[12:13], 0x0
s_load_b128 s[12:15], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s21
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[3:4], v[2:3], s[16:17], 1.0
v_div_fmas_f64 v[10:11], v[6:7], v[12:13], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[5:6], v[8:9], s[18:19], 1.0
v_mov_b32_e32 v12, 0
v_div_fixup_f64 v[7:8], v[10:11], s[8:9], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_f64 v[9:10], v[3:4], v[5:6]
v_min_f64 v[9:10], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], 0x405fc000
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[17:18], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v13, vcc_lo, s4, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
global_load_b32 v0, v[13:14], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v13, v0, 1, v0
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v19, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v14, vcc_lo
s_clause 0x1
global_load_b128 v[13:16], v[19:20], off
global_load_b64 v[19:20], v[19:20], off offset:16
s_waitcnt vmcnt(1)
v_mul_f64 v[21:22], v[3:4], v[13:14]
v_mul_f64 v[23:24], v[5:6], v[15:16]
s_waitcnt vmcnt(0)
v_mul_f64 v[25:26], v[7:8], v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f64_e32 v[21:22], v[21:22]
v_floor_f64_e32 v[23:24], v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f64_e32 v[25:26], v[25:26]
v_fma_f64 v[13:14], -s[16:17], v[21:22], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], -s[18:19], v[23:24], v[15:16]
v_fma_f64 v[19:20], -s[8:9], v[25:26], v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[13:14], v[9:10], v[13:14]
v_mul_f64 v[15:16], v[9:10], v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[19:20], v[9:10], v[19:20]
v_cvt_u32_f64_e32 v2, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f64_e32 v11, v[15:16]
v_cvt_u32_f64_e32 v13, v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v2, 14, v2
v_lshlrev_b32_e32 v11, 7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v11, v11, v2, v13
v_lshlrev_b64 v[13:14], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s20, v1
global_load_b32 v2, v[13:14], off
v_add_co_u32 v13, s0, s12, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s13, v18, s0
v_add_co_u32 v15, s0, s14, v17
v_add_co_ci_u32_e64 v16, s0, s15, v18, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b32 v[13:14], v2, off
global_store_b32 v[15:16], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, .Lfunc_end0-_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016695e_00000000-6_k_hilbert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_
.type _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_, @function
_Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
movq 208(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_, .-_Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_
.globl _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.type _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, @function
_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z72__device_stub__ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_iPKjPKdS2_S0_PjS3_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, .-_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "k_hilbert.hip"
.globl _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_ # -- Begin function _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.p2align 4, 0x90
.type _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_,@function
_ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_: # @_ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, .Lfunc_end0-_ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_,@object # @_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.section .rodata,"a",@progbits
.globl _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.p2align 3, 0x0
_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_:
.quad _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.size _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_"
.size .L__unnamed_1, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN11timemachine36__device_stub__k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN11timemachine21k_coords_to_kv_gatherEiPKjPKdS3_S1_PjS4_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
/*
Measure Time
Maximum Matrix Size
*/
const int TILE_DIM = 32;
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("CUDA Runtime Error: %s\n", cudaGetErrorString(result));
exit(1);
}
return result;
}
__global__ void transposeMatrix(float *B, float *A, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
tile[threadIdx.y][threadIdx.x] = A[y*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
B[y*width + x] = tile[threadIdx.x][threadIdx.y];
}
int main(int argc, char **argv)
{
if (argc < 1) {
printf("matrix size is a mandatory parameter");
exit(1);
}
// Number of rows and columns must be a multiple of 32
int rows = atoi(argv[1]);
if (rows % TILE_DIM ) {
printf("number of rows must be multiple of 32\n");
exit(1);
}
const int columns = rows;
const int width = rows;
const int size = rows*columns*sizeof(float);
dim3 dimGrid(width/TILE_DIM, width/TILE_DIM);
dim3 dimBlock(TILE_DIM, TILE_DIM);
float *A, *B, *C;
checkCuda( cudaMallocHost(&A, size) );
checkCuda( cudaMallocHost(&B, size) );
checkCuda( cudaMallocHost(&C, size) );
/*
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
*/
float *dA, *dB;
checkCuda( cudaMalloc(&dA, size) );
checkCuda( cudaMalloc(&dB, size) );
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
A[j*width + i] = 0.15*i + 0.1*j;
clock_t tStart = clock();
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
C[j*width + i] = A[i*width + j];
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( cudaMemcpy(dA, A, size, cudaMemcpyHostToDevice) );
tStart = clock();
transposeMatrix<<<dimGrid, dimBlock>>>(dB, dA, width);
checkCuda( cudaDeviceSynchronize() );
printf("Time taken by GPU: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( cudaMemcpy(B, dB, size, cudaMemcpyDeviceToHost) );
for (int i = 0; i < rows * columns; i++)
{
if (B[i] != C[i]) {
printf("%d %f %f INVALID RESULTS \n", i, B[i], C[i]);
goto finished;
}
}
printf("Matrix Transpose Successful");
finished:
checkCuda( cudaFree(dA) );
checkCuda( cudaFree(dB) );
checkCuda(cudaFreeHost(A));
checkCuda(cudaFreeHost(B));
checkCuda(cudaFreeHost(C));
} | code for sm_80
Function : _Z15transposeMatrixPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0060*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002200 */
/*0070*/ LEA R0, R5, R4, 0x5 ; /* 0x0000000405007211 */
/* 0x001fc400078e28ff */
/*0080*/ LEA R3, R9, R6, 0x5 ; /* 0x0000000609037211 */
/* 0x002fca00078e28ff */
/*0090*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LEA R11, R6, R4.reuse, 0x5 ; /* 0x00000004060b7211 */
/* 0x080fe200078e28ff */
/*00d0*/ IMAD R7, R4, 0x20, R6 ; /* 0x0000002004077824 */
/* 0x000fe200078e0206 */
/*00e0*/ LEA R0, R9, R4, 0x5 ; /* 0x0000000409007211 */
/* 0x000fe400078e28ff */
/*00f0*/ LEA R5, R5, R6, 0x5 ; /* 0x0000000605057211 */
/* 0x000fca00078e28ff */
/*0100*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R4, R5, R8, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0208 */
/*0120*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
/*
Measure Time
Maximum Matrix Size
*/
const int TILE_DIM = 32;
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("CUDA Runtime Error: %s\n", cudaGetErrorString(result));
exit(1);
}
return result;
}
__global__ void transposeMatrix(float *B, float *A, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
tile[threadIdx.y][threadIdx.x] = A[y*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
B[y*width + x] = tile[threadIdx.x][threadIdx.y];
}
int main(int argc, char **argv)
{
if (argc < 1) {
printf("matrix size is a mandatory parameter");
exit(1);
}
// Number of rows and columns must be a multiple of 32
int rows = atoi(argv[1]);
if (rows % TILE_DIM ) {
printf("number of rows must be multiple of 32\n");
exit(1);
}
const int columns = rows;
const int width = rows;
const int size = rows*columns*sizeof(float);
dim3 dimGrid(width/TILE_DIM, width/TILE_DIM);
dim3 dimBlock(TILE_DIM, TILE_DIM);
float *A, *B, *C;
checkCuda( cudaMallocHost(&A, size) );
checkCuda( cudaMallocHost(&B, size) );
checkCuda( cudaMallocHost(&C, size) );
/*
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
*/
float *dA, *dB;
checkCuda( cudaMalloc(&dA, size) );
checkCuda( cudaMalloc(&dB, size) );
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
A[j*width + i] = 0.15*i + 0.1*j;
clock_t tStart = clock();
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
C[j*width + i] = A[i*width + j];
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( cudaMemcpy(dA, A, size, cudaMemcpyHostToDevice) );
tStart = clock();
transposeMatrix<<<dimGrid, dimBlock>>>(dB, dA, width);
checkCuda( cudaDeviceSynchronize() );
printf("Time taken by GPU: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( cudaMemcpy(B, dB, size, cudaMemcpyDeviceToHost) );
for (int i = 0; i < rows * columns; i++)
{
if (B[i] != C[i]) {
printf("%d %f %f INVALID RESULTS \n", i, B[i], C[i]);
goto finished;
}
}
printf("Matrix Transpose Successful");
finished:
checkCuda( cudaFree(dA) );
checkCuda( cudaFree(dB) );
checkCuda(cudaFreeHost(A));
checkCuda(cudaFreeHost(B));
checkCuda(cudaFreeHost(C));
} | .file "tmpxft_00173e90_00000000-6_matrix_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Runtime Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
movl $0, %eax
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.text
.globl _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
.type _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i, @function
_Z38__device_stub__Z15transposeMatrixPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15transposeMatrixPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i, .-_Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
.globl _Z15transposeMatrixPfS_i
.type _Z15transposeMatrixPfS_i, @function
_Z15transposeMatrixPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15transposeMatrixPfS_i, .-_Z15transposeMatrixPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "matrix size is a mandatory parameter"
.align 8
.LC2:
.string "number of rows must be multiple of 32\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Time taken by Host: %.6fs\n"
.LC7:
.string "Time taken by GPU: %.6fs\n"
.LC8:
.string "%d %f %f INVALID RESULTS \n"
.LC9:
.string "Matrix Transpose Successful"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
testl %edi, %edi
jle .L40
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebp
testb $31, %al
jne .L41
movl %eax, %r15d
imull %eax, %r15d
movslq %r15d, %r14
leal 31(%rax), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
movl %eax, 64(%rsp)
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $32, 76(%rsp)
movl $32, 80(%rsp)
movl $1, 84(%rsp)
leal 0(,%r15,4), %r13d
movslq %r13d, %r13
leaq 24(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 32(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 40(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
testl %r12d, %r12d
jle .L20
movslq %r12d, %rbx
salq $2, %rbx
movl $0, %edi
movl $0, %esi
movsd .LC4(%rip), %xmm3
movsd .LC3(%rip), %xmm2
.L21:
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
mulsd %xmm3, %xmm1
movq %rdi, %rdx
movl $0, %eax
.L22:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 24(%rsp), %rcx
movss %xmm0, (%rcx,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ebp, %eax
jne .L22
addl $1, %esi
addq %rbx, %rdi
cmpl %ebp, %esi
jne .L21
call clock@PLT
movq %rax, 8(%rsp)
movl %r12d, %r9d
leaq 0(,%r9,4), %rsi
movl $0, %edi
movl %r12d, %r12d
negq %r12
leaq 0(,%r12,4), %r8
.L24:
leaq 0(,%rdi,4), %rdx
leaq (%r8,%rsi), %rax
.L25:
movq 24(%rsp), %rcx
movss (%rcx,%rdx), %xmm0
movq 40(%rsp), %rcx
movss %xmm0, (%rcx,%rax)
addq %rbx, %rdx
addq $4, %rax
cmpq %rsi, %rax
jne .L25
addq $1, %rdi
addq %rbx, %rsi
cmpq %r9, %rdi
jne .L24
.L26:
call clock@PLT
movq 8(%rsp), %rbx
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call clock@PLT
movq %rax, %rbx
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L27:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
testl %r15d, %r15d
jle .L28
movq 32(%rsp), %rcx
movq 40(%rsp), %rax
movl $0, %edx
.L32:
movss (%rcx,%rdx,4), %xmm0
movss (%rax,%rdx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L34
jne .L34
addq $1, %rdx
cmpq %rdx, %r14
jne .L32
.L28:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L31:
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %ebp, %edx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
jmp .L27
.L34:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L31
.L20:
call clock@PLT
movq %rax, 8(%rsp)
jmp .L26
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15transposeMatrixPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15transposeMatrixPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 858993459
.long 1069757235
.align 8
.LC4:
.long -1717986918
.long 1069128089
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
/*
Measure Time
Maximum Matrix Size
*/
const int TILE_DIM = 32;
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("CUDA Runtime Error: %s\n", cudaGetErrorString(result));
exit(1);
}
return result;
}
__global__ void transposeMatrix(float *B, float *A, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
tile[threadIdx.y][threadIdx.x] = A[y*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
B[y*width + x] = tile[threadIdx.x][threadIdx.y];
}
int main(int argc, char **argv)
{
if (argc < 1) {
printf("matrix size is a mandatory parameter");
exit(1);
}
// Number of rows and columns must be a multiple of 32
int rows = atoi(argv[1]);
if (rows % TILE_DIM ) {
printf("number of rows must be multiple of 32\n");
exit(1);
}
const int columns = rows;
const int width = rows;
const int size = rows*columns*sizeof(float);
dim3 dimGrid(width/TILE_DIM, width/TILE_DIM);
dim3 dimBlock(TILE_DIM, TILE_DIM);
float *A, *B, *C;
checkCuda( cudaMallocHost(&A, size) );
checkCuda( cudaMallocHost(&B, size) );
checkCuda( cudaMallocHost(&C, size) );
/*
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
*/
float *dA, *dB;
checkCuda( cudaMalloc(&dA, size) );
checkCuda( cudaMalloc(&dB, size) );
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
A[j*width + i] = 0.15*i + 0.1*j;
clock_t tStart = clock();
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
C[j*width + i] = A[i*width + j];
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( cudaMemcpy(dA, A, size, cudaMemcpyHostToDevice) );
tStart = clock();
transposeMatrix<<<dimGrid, dimBlock>>>(dB, dA, width);
checkCuda( cudaDeviceSynchronize() );
printf("Time taken by GPU: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( cudaMemcpy(B, dB, size, cudaMemcpyDeviceToHost) );
for (int i = 0; i < rows * columns; i++)
{
if (B[i] != C[i]) {
printf("%d %f %f INVALID RESULTS \n", i, B[i], C[i]);
goto finished;
}
}
printf("Matrix Transpose Successful");
finished:
checkCuda( cudaFree(dA) );
checkCuda( cudaFree(dB) );
checkCuda(cudaFreeHost(A));
checkCuda(cudaFreeHost(B));
checkCuda(cudaFreeHost(C));
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
/*
Measure Time
Maximum Matrix Size
*/
const int TILE_DIM = 32;
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("CUDA Runtime Error: %s\n", hipGetErrorString(result));
exit(1);
}
return result;
}
__global__ void transposeMatrix(float *B, float *A, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
tile[threadIdx.y][threadIdx.x] = A[y*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
B[y*width + x] = tile[threadIdx.x][threadIdx.y];
}
int main(int argc, char **argv)
{
if (argc < 1) {
printf("matrix size is a mandatory parameter");
exit(1);
}
// Number of rows and columns must be a multiple of 32
int rows = atoi(argv[1]);
if (rows % TILE_DIM ) {
printf("number of rows must be multiple of 32\n");
exit(1);
}
const int columns = rows;
const int width = rows;
const int size = rows*columns*sizeof(float);
dim3 dimGrid(width/TILE_DIM, width/TILE_DIM);
dim3 dimBlock(TILE_DIM, TILE_DIM);
float *A, *B, *C;
checkCuda( hipHostMalloc(&A, size, hipHostMallocDefault) );
checkCuda( hipHostMalloc(&B, size, hipHostMallocDefault) );
checkCuda( hipHostMalloc(&C, size, hipHostMallocDefault) );
/*
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
*/
float *dA, *dB;
checkCuda( hipMalloc(&dA, size) );
checkCuda( hipMalloc(&dB, size) );
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
A[j*width + i] = 0.15*i + 0.1*j;
clock_t tStart = clock();
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
C[j*width + i] = A[i*width + j];
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( hipMemcpy(dA, A, size, hipMemcpyHostToDevice) );
tStart = clock();
transposeMatrix<<<dimGrid, dimBlock>>>(dB, dA, width);
checkCuda( hipDeviceSynchronize() );
printf("Time taken by GPU: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( hipMemcpy(B, dB, size, hipMemcpyDeviceToHost) );
for (int i = 0; i < rows * columns; i++)
{
if (B[i] != C[i]) {
printf("%d %f %f INVALID RESULTS \n", i, B[i], C[i]);
goto finished;
}
}
printf("Matrix Transpose Successful");
finished:
checkCuda( hipFree(dA) );
checkCuda( hipFree(dB) );
checkCuda(hipHostFree(A));
checkCuda(hipHostFree(B));
checkCuda(hipHostFree(C));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
/*
Measure Time
Maximum Matrix Size
*/
const int TILE_DIM = 32;
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("CUDA Runtime Error: %s\n", hipGetErrorString(result));
exit(1);
}
return result;
}
__global__ void transposeMatrix(float *B, float *A, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
tile[threadIdx.y][threadIdx.x] = A[y*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
B[y*width + x] = tile[threadIdx.x][threadIdx.y];
}
int main(int argc, char **argv)
{
if (argc < 1) {
printf("matrix size is a mandatory parameter");
exit(1);
}
// Number of rows and columns must be a multiple of 32
int rows = atoi(argv[1]);
if (rows % TILE_DIM ) {
printf("number of rows must be multiple of 32\n");
exit(1);
}
const int columns = rows;
const int width = rows;
const int size = rows*columns*sizeof(float);
dim3 dimGrid(width/TILE_DIM, width/TILE_DIM);
dim3 dimBlock(TILE_DIM, TILE_DIM);
float *A, *B, *C;
checkCuda( hipHostMalloc(&A, size, hipHostMallocDefault) );
checkCuda( hipHostMalloc(&B, size, hipHostMallocDefault) );
checkCuda( hipHostMalloc(&C, size, hipHostMallocDefault) );
/*
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
*/
float *dA, *dB;
checkCuda( hipMalloc(&dA, size) );
checkCuda( hipMalloc(&dB, size) );
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
A[j*width + i] = 0.15*i + 0.1*j;
clock_t tStart = clock();
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
C[j*width + i] = A[i*width + j];
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( hipMemcpy(dA, A, size, hipMemcpyHostToDevice) );
tStart = clock();
transposeMatrix<<<dimGrid, dimBlock>>>(dB, dA, width);
checkCuda( hipDeviceSynchronize() );
printf("Time taken by GPU: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( hipMemcpy(B, dB, size, hipMemcpyDeviceToHost) );
for (int i = 0; i < rows * columns; i++)
{
if (B[i] != C[i]) {
printf("%d %f %f INVALID RESULTS \n", i, B[i], C[i]);
goto finished;
}
}
printf("Matrix Transpose Successful");
finished:
checkCuda( hipFree(dA) );
checkCuda( hipFree(dB) );
checkCuda(hipHostFree(A));
checkCuda(hipHostFree(B));
checkCuda(hipHostFree(C));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15transposeMatrixPfS_i
.globl _Z15transposeMatrixPfS_i
.p2align 8
.type _Z15transposeMatrixPfS_i,@function
_Z15transposeMatrixPfS_i:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s6, s14, 5
v_add_nc_u32_e32 v1, s5, v2
v_lshlrev_b32_e32 v5, 2, v2
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s4
v_add3_u32 v0, s6, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_add_nc_u32_e32 v0, s6, v2
v_lshl_add_u32 v2, v2, 7, v4
v_lshl_add_u32 v4, v3, 7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_add3_u32 v0, s5, v3, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15transposeMatrixPfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15transposeMatrixPfS_i, .Lfunc_end0-_Z15transposeMatrixPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15transposeMatrixPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15transposeMatrixPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
/*
Measure Time
Maximum Matrix Size
*/
const int TILE_DIM = 32;
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("CUDA Runtime Error: %s\n", hipGetErrorString(result));
exit(1);
}
return result;
}
__global__ void transposeMatrix(float *B, float *A, int width)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
tile[threadIdx.y][threadIdx.x] = A[y*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
B[y*width + x] = tile[threadIdx.x][threadIdx.y];
}
int main(int argc, char **argv)
{
if (argc < 1) {
printf("matrix size is a mandatory parameter");
exit(1);
}
// Number of rows and columns must be a multiple of 32
int rows = atoi(argv[1]);
if (rows % TILE_DIM ) {
printf("number of rows must be multiple of 32\n");
exit(1);
}
const int columns = rows;
const int width = rows;
const int size = rows*columns*sizeof(float);
dim3 dimGrid(width/TILE_DIM, width/TILE_DIM);
dim3 dimBlock(TILE_DIM, TILE_DIM);
float *A, *B, *C;
checkCuda( hipHostMalloc(&A, size, hipHostMallocDefault) );
checkCuda( hipHostMalloc(&B, size, hipHostMallocDefault) );
checkCuda( hipHostMalloc(&C, size, hipHostMallocDefault) );
/*
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
*/
float *dA, *dB;
checkCuda( hipMalloc(&dA, size) );
checkCuda( hipMalloc(&dB, size) );
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
A[j*width + i] = 0.15*i + 0.1*j;
clock_t tStart = clock();
for (int j = 0; j < rows; j++)
for (int i = 0; i < columns; i++)
C[j*width + i] = A[i*width + j];
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( hipMemcpy(dA, A, size, hipMemcpyHostToDevice) );
tStart = clock();
transposeMatrix<<<dimGrid, dimBlock>>>(dB, dA, width);
checkCuda( hipDeviceSynchronize() );
printf("Time taken by GPU: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
checkCuda( hipMemcpy(B, dB, size, hipMemcpyDeviceToHost) );
for (int i = 0; i < rows * columns; i++)
{
if (B[i] != C[i]) {
printf("%d %f %f INVALID RESULTS \n", i, B[i], C[i]);
goto finished;
}
}
printf("Matrix Transpose Successful");
finished:
checkCuda( hipFree(dA) );
checkCuda( hipFree(dB) );
checkCuda(hipHostFree(A));
checkCuda(hipHostFree(B));
checkCuda(hipHostFree(C));
} | .text
.file "matrix_transpose.hip"
.globl _Z30__device_stub__transposeMatrixPfS_i # -- Begin function _Z30__device_stub__transposeMatrixPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__transposeMatrixPfS_i,@function
_Z30__device_stub__transposeMatrixPfS_i: # @_Z30__device_stub__transposeMatrixPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15transposeMatrixPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__transposeMatrixPfS_i, .Lfunc_end0-_Z30__device_stub__transposeMatrixPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fb999999999999a # double 0.10000000000000001
.LCPI1_1:
.quad 0x3fc3333333333333 # double 0.14999999999999999
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edi, %edi
jle .LBB1_36
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
testb $31, %bl
jne .LBB1_37
# %bb.2:
movl %ebx, %r13d
imull %r13d, %r13d
leal (,%r13,4), %eax
movslq %eax, %r14
movq %rsp, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.3: # %_Z9checkCuda10hipError_t.exit
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.4: # %_Z9checkCuda10hipError_t.exit68
leaq 24(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.5: # %_Z9checkCuda10hipError_t.exit70
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.6: # %_Z9checkCuda10hipError_t.exit72
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.7: # %_Z9checkCuda10hipError_t.exit74.preheader
testl %ebx, %ebx
jle .LBB1_12
# %bb.8: # %.preheader94.lr.ph
movq (%rsp), %rax
movl %ebx, %ecx
xorl %edx, %edx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_9: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorps %xmm2, %xmm2
cvtsi2sd %esi, %xmm2
mulsd %xmm0, %xmm2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm3, %xmm3
cvtsi2sd %r8d, %xmm3
mulsd %xmm1, %xmm3
addsd %xmm2, %xmm3
cvtsd2ss %xmm3, %xmm3
movss %xmm3, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB1_10
# %bb.11: # %_Z9checkCuda10hipError_t.exit74
# in Loop: Header=BB1_9 Depth=1
incq %rsi
addl %ebx, %edx
cmpq %rcx, %rsi
jne .LBB1_9
.LBB1_12: # %_Z9checkCuda10hipError_t.exit74._crit_edge
callq clock
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_17
# %bb.13: # %.preheader.lr.ph
movq (%rsp), %rax
movq 24(%rsp), %rcx
movl %ebx, %edx
leaq (,%rdx,4), %rsi
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
movl %edi, %r9d
leaq (%rcx,%r9,4), %r9
movq %rax, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB1_15: # Parent Loop BB1_14 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r9,%r11,4)
incq %r11
addq %rsi, %r10
cmpq %r11, %rdx
jne .LBB1_15
# %bb.16: # %._crit_edge102
# in Loop: Header=BB1_14 Depth=1
incq %r8
addl %ebx, %edi
addq $4, %rax
cmpq %rdx, %r8
jne .LBB1_14
.LBB1_17: # %._crit_edge104
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_38
# %bb.18: # %_Z9checkCuda10hipError_t.exit76
movl %ebx, %eax
sarl $5, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
callq clock
movq %rax, %r15
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %ebx, 44(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15transposeMatrixPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_38
# %bb.21: # %_Z9checkCuda10hipError_t.exit78
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_38
# %bb.22: # %_Z9checkCuda10hipError_t.exit80.preheader
testl %ebx, %ebx
setne %bl
je .LBB1_29
# %bb.23: # %.lr.ph108
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
cmpl $1, %r13d
movl %r13d, %edx
adcl $0, %edx
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %esi, %esi
ucomiss %xmm1, %xmm0
jne .LBB1_28
jp .LBB1_28
# %bb.24: # %_Z9checkCuda10hipError_t.exit80.preheader154
movl %r13d, %edi
decq %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_25: # %_Z9checkCuda10hipError_t.exit80
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %rdx
je .LBB1_29
# %bb.26: # in Loop: Header=BB1_25 Depth=1
movss 4(%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rcx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB1_27
jnp .LBB1_25
.LBB1_27: # %._crit_edge
cmpq %rdi, %rsi
setb %bl
.LBB1_28:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
testb %bl, %bl
jne .LBB1_30
.LBB1_29: # %.critedge
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB1_30:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_38
# %bb.31: # %_Z9checkCuda10hipError_t.exit82
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_38
# %bb.32: # %_Z9checkCuda10hipError_t.exit84
movq (%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB1_38
# %bb.33: # %_Z9checkCuda10hipError_t.exit86
movq 32(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB1_38
# %bb.34: # %_Z9checkCuda10hipError_t.exit88
movq 24(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB1_38
# %bb.35: # %_Z9checkCuda10hipError_t.exit90
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_38:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_36:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_37:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15transposeMatrixPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15transposeMatrixPfS_i,@object # @_Z15transposeMatrixPfS_i
.section .rodata,"a",@progbits
.globl _Z15transposeMatrixPfS_i
.p2align 3, 0x0
_Z15transposeMatrixPfS_i:
.quad _Z30__device_stub__transposeMatrixPfS_i
.size _Z15transposeMatrixPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix size is a mandatory parameter"
.size .L.str, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken by Host: %.6fs\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time taken by GPU: %.6fs\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %f %f INVALID RESULTS \n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix Transpose Successful"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.6, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15transposeMatrixPfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "number of rows must be multiple of 32"
.size .Lstr, 38
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__transposeMatrixPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15transposeMatrixPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15transposeMatrixPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0060*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002200 */
/*0070*/ LEA R0, R5, R4, 0x5 ; /* 0x0000000405007211 */
/* 0x001fc400078e28ff */
/*0080*/ LEA R3, R9, R6, 0x5 ; /* 0x0000000609037211 */
/* 0x002fca00078e28ff */
/*0090*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0208 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LEA R11, R6, R4.reuse, 0x5 ; /* 0x00000004060b7211 */
/* 0x080fe200078e28ff */
/*00d0*/ IMAD R7, R4, 0x20, R6 ; /* 0x0000002004077824 */
/* 0x000fe200078e0206 */
/*00e0*/ LEA R0, R9, R4, 0x5 ; /* 0x0000000409007211 */
/* 0x000fe400078e28ff */
/*00f0*/ LEA R5, R5, R6, 0x5 ; /* 0x0000000605057211 */
/* 0x000fca00078e28ff */
/*0100*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R4, R5, R8, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0208 */
/*0120*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15transposeMatrixPfS_i
.globl _Z15transposeMatrixPfS_i
.p2align 8
.type _Z15transposeMatrixPfS_i,@function
_Z15transposeMatrixPfS_i:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s6, s14, 5
v_add_nc_u32_e32 v1, s5, v2
v_lshlrev_b32_e32 v5, 2, v2
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s4
v_add3_u32 v0, s6, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_add_nc_u32_e32 v0, s6, v2
v_lshl_add_u32 v2, v2, 7, v4
v_lshl_add_u32 v4, v3, 7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_add3_u32 v0, s5, v3, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15transposeMatrixPfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15transposeMatrixPfS_i, .Lfunc_end0-_Z15transposeMatrixPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15transposeMatrixPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15transposeMatrixPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00173e90_00000000-6_matrix_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Runtime Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
movl $0, %eax
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.text
.globl _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
.type _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i, @function
_Z38__device_stub__Z15transposeMatrixPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15transposeMatrixPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i, .-_Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
.globl _Z15transposeMatrixPfS_i
.type _Z15transposeMatrixPfS_i, @function
_Z15transposeMatrixPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15transposeMatrixPfS_i, .-_Z15transposeMatrixPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "matrix size is a mandatory parameter"
.align 8
.LC2:
.string "number of rows must be multiple of 32\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Time taken by Host: %.6fs\n"
.LC7:
.string "Time taken by GPU: %.6fs\n"
.LC8:
.string "%d %f %f INVALID RESULTS \n"
.LC9:
.string "Matrix Transpose Successful"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
testl %edi, %edi
jle .L40
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebp
testb $31, %al
jne .L41
movl %eax, %r15d
imull %eax, %r15d
movslq %r15d, %r14
leal 31(%rax), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
movl %eax, 64(%rsp)
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $32, 76(%rsp)
movl $32, 80(%rsp)
movl $1, 84(%rsp)
leal 0(,%r15,4), %r13d
movslq %r13d, %r13
leaq 24(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 32(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 40(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
testl %r12d, %r12d
jle .L20
movslq %r12d, %rbx
salq $2, %rbx
movl $0, %edi
movl $0, %esi
movsd .LC4(%rip), %xmm3
movsd .LC3(%rip), %xmm2
.L21:
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
mulsd %xmm3, %xmm1
movq %rdi, %rdx
movl $0, %eax
.L22:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 24(%rsp), %rcx
movss %xmm0, (%rcx,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ebp, %eax
jne .L22
addl $1, %esi
addq %rbx, %rdi
cmpl %ebp, %esi
jne .L21
call clock@PLT
movq %rax, 8(%rsp)
movl %r12d, %r9d
leaq 0(,%r9,4), %rsi
movl $0, %edi
movl %r12d, %r12d
negq %r12
leaq 0(,%r12,4), %r8
.L24:
leaq 0(,%rdi,4), %rdx
leaq (%r8,%rsi), %rax
.L25:
movq 24(%rsp), %rcx
movss (%rcx,%rdx), %xmm0
movq 40(%rsp), %rcx
movss %xmm0, (%rcx,%rax)
addq %rbx, %rdx
addq $4, %rax
cmpq %rsi, %rax
jne .L25
addq $1, %rdi
addq %rbx, %rsi
cmpq %r9, %rdi
jne .L24
.L26:
call clock@PLT
movq 8(%rsp), %rbx
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call clock@PLT
movq %rax, %rbx
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L27:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
testl %r15d, %r15d
jle .L28
movq 32(%rsp), %rcx
movq 40(%rsp), %rax
movl $0, %edx
.L32:
movss (%rcx,%rdx,4), %xmm0
movss (%rax,%rdx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L34
jne .L34
addq $1, %rdx
cmpq %rdx, %r14
jne .L32
.L28:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L31:
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %ebp, %edx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z15transposeMatrixPfS_iPfS_i
jmp .L27
.L34:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L31
.L20:
call clock@PLT
movq %rax, 8(%rsp)
jmp .L26
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15transposeMatrixPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15transposeMatrixPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 858993459
.long 1069757235
.align 8
.LC4:
.long -1717986918
.long 1069128089
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_transpose.hip"
.globl _Z30__device_stub__transposeMatrixPfS_i # -- Begin function _Z30__device_stub__transposeMatrixPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__transposeMatrixPfS_i,@function
_Z30__device_stub__transposeMatrixPfS_i: # @_Z30__device_stub__transposeMatrixPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15transposeMatrixPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__transposeMatrixPfS_i, .Lfunc_end0-_Z30__device_stub__transposeMatrixPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fb999999999999a # double 0.10000000000000001
.LCPI1_1:
.quad 0x3fc3333333333333 # double 0.14999999999999999
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edi, %edi
jle .LBB1_36
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
testb $31, %bl
jne .LBB1_37
# %bb.2:
movl %ebx, %r13d
imull %r13d, %r13d
leal (,%r13,4), %eax
movslq %eax, %r14
movq %rsp, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.3: # %_Z9checkCuda10hipError_t.exit
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.4: # %_Z9checkCuda10hipError_t.exit68
leaq 24(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.5: # %_Z9checkCuda10hipError_t.exit70
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.6: # %_Z9checkCuda10hipError_t.exit72
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.7: # %_Z9checkCuda10hipError_t.exit74.preheader
testl %ebx, %ebx
jle .LBB1_12
# %bb.8: # %.preheader94.lr.ph
movq (%rsp), %rax
movl %ebx, %ecx
xorl %edx, %edx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_9: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorps %xmm2, %xmm2
cvtsi2sd %esi, %xmm2
mulsd %xmm0, %xmm2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm3, %xmm3
cvtsi2sd %r8d, %xmm3
mulsd %xmm1, %xmm3
addsd %xmm2, %xmm3
cvtsd2ss %xmm3, %xmm3
movss %xmm3, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB1_10
# %bb.11: # %_Z9checkCuda10hipError_t.exit74
# in Loop: Header=BB1_9 Depth=1
incq %rsi
addl %ebx, %edx
cmpq %rcx, %rsi
jne .LBB1_9
.LBB1_12: # %_Z9checkCuda10hipError_t.exit74._crit_edge
callq clock
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_17
# %bb.13: # %.preheader.lr.ph
movq (%rsp), %rax
movq 24(%rsp), %rcx
movl %ebx, %edx
leaq (,%rdx,4), %rsi
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
movl %edi, %r9d
leaq (%rcx,%r9,4), %r9
movq %rax, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB1_15: # Parent Loop BB1_14 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r9,%r11,4)
incq %r11
addq %rsi, %r10
cmpq %r11, %rdx
jne .LBB1_15
# %bb.16: # %._crit_edge102
# in Loop: Header=BB1_14 Depth=1
incq %r8
addl %ebx, %edi
addq $4, %rax
cmpq %rdx, %r8
jne .LBB1_14
.LBB1_17: # %._crit_edge104
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_38
# %bb.18: # %_Z9checkCuda10hipError_t.exit76
movl %ebx, %eax
sarl $5, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
callq clock
movq %rax, %r15
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %ebx, 44(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15transposeMatrixPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_38
# %bb.21: # %_Z9checkCuda10hipError_t.exit78
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_38
# %bb.22: # %_Z9checkCuda10hipError_t.exit80.preheader
testl %ebx, %ebx
setne %bl
je .LBB1_29
# %bb.23: # %.lr.ph108
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
cmpl $1, %r13d
movl %r13d, %edx
adcl $0, %edx
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %esi, %esi
ucomiss %xmm1, %xmm0
jne .LBB1_28
jp .LBB1_28
# %bb.24: # %_Z9checkCuda10hipError_t.exit80.preheader154
movl %r13d, %edi
decq %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_25: # %_Z9checkCuda10hipError_t.exit80
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %rdx
je .LBB1_29
# %bb.26: # in Loop: Header=BB1_25 Depth=1
movss 4(%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rcx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB1_27
jnp .LBB1_25
.LBB1_27: # %._crit_edge
cmpq %rdi, %rsi
setb %bl
.LBB1_28:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
testb %bl, %bl
jne .LBB1_30
.LBB1_29: # %.critedge
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB1_30:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_38
# %bb.31: # %_Z9checkCuda10hipError_t.exit82
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_38
# %bb.32: # %_Z9checkCuda10hipError_t.exit84
movq (%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB1_38
# %bb.33: # %_Z9checkCuda10hipError_t.exit86
movq 32(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB1_38
# %bb.34: # %_Z9checkCuda10hipError_t.exit88
movq 24(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB1_38
# %bb.35: # %_Z9checkCuda10hipError_t.exit90
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_38:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_36:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_37:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15transposeMatrixPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15transposeMatrixPfS_i,@object # @_Z15transposeMatrixPfS_i
.section .rodata,"a",@progbits
.globl _Z15transposeMatrixPfS_i
.p2align 3, 0x0
_Z15transposeMatrixPfS_i:
.quad _Z30__device_stub__transposeMatrixPfS_i
.size _Z15transposeMatrixPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix size is a mandatory parameter"
.size .L.str, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken by Host: %.6fs\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time taken by GPU: %.6fs\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %f %f INVALID RESULTS \n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix Transpose Successful"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.6, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15transposeMatrixPfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "number of rows must be multiple of 32"
.size .Lstr, 38
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__transposeMatrixPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15transposeMatrixPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#define N 1000000
__global__ void vecadd(int *a, int *b, int *c){
// determine global thread id
int idx = threadIdx.x + blockIdx.x * blockDim.x;
// do vector add, check if index is < N
if(idx<N) {
c[idx]=a[idx]+b[idx];
}
}
int main (int argc, char **argv){
int a_host[N], b_host[N], c_host[N];
int *a_device, *b_device, *c_device;
int i;
int blocksize=256;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil(N/(float)blocksize));
for (i=0;i<N;i++) a_host[i]=i;
for (i=0;i<N;i++) b_host[i]=i;
// alloc GPU memory
cudaMalloc((void**)&a_device,N*sizeof(int));
cudaMalloc((void**)&b_device,N*sizeof(int));
cudaMalloc((void**)&c_device,N*sizeof(int));
// transfer data
cudaMemcpy(a_device,a_host,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(b_device,b_host,N*sizeof(int),cudaMemcpyHostToDevice);
// invoke kernel
vecadd<<<dimGrid,dimBlock>>>(a_device,b_device,c_device);
// transfer result
cudaMemcpy(c_host,c_device,N*sizeof(int),cudaMemcpyDeviceToHost);
// check for correctness
for (i=0;i<N;i++) assert (c_host[i] == a_host[i] + b_host[i]);
// free GPU memory
for (i=0;i<N;i++) {
cudaFree(a_device);
cudaFree(b_device);
cudaFree(c_device);
}
return 0;
} | code for sm_80
Function : _Z6vecaddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xf423f, PT ; /* 0x000f423f0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#define N 1000000
__global__ void vecadd(int *a, int *b, int *c){
// determine global thread id
int idx = threadIdx.x + blockIdx.x * blockDim.x;
// do vector add, check if index is < N
if(idx<N) {
c[idx]=a[idx]+b[idx];
}
}
int main (int argc, char **argv){
int a_host[N], b_host[N], c_host[N];
int *a_device, *b_device, *c_device;
int i;
int blocksize=256;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil(N/(float)blocksize));
for (i=0;i<N;i++) a_host[i]=i;
for (i=0;i<N;i++) b_host[i]=i;
// alloc GPU memory
cudaMalloc((void**)&a_device,N*sizeof(int));
cudaMalloc((void**)&b_device,N*sizeof(int));
cudaMalloc((void**)&c_device,N*sizeof(int));
// transfer data
cudaMemcpy(a_device,a_host,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(b_device,b_host,N*sizeof(int),cudaMemcpyHostToDevice);
// invoke kernel
vecadd<<<dimGrid,dimBlock>>>(a_device,b_device,c_device);
// transfer result
cudaMemcpy(c_host,c_device,N*sizeof(int),cudaMemcpyDeviceToHost);
// check for correctness
for (i=0;i<N;i++) assert (c_host[i] == a_host[i] + b_host[i]);
// free GPU memory
for (i=0;i<N;i++) {
cudaFree(a_device);
cudaFree(b_device);
cudaFree(c_device);
}
return 0;
} | .file "tmpxft_000812c0_00000000-6_lab2-2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecaddPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecaddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.globl _Z6vecaddPiS_S_
.type _Z6vecaddPiS_S_, @function
_Z6vecaddPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecaddPiS_S_, .-_Z6vecaddPiS_S_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -11997184(%rsp), %r11
.cfi_def_cfa 11, 11997200
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2880, %rsp
.cfi_def_cfa_offset 12000080
movq %fs:40, %rax
movq %rax, 12000056(%rsp)
xorl %eax, %eax
movl $256, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $3907, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
.L12:
movl %eax, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L12
movl $0, %eax
.L13:
movl %eax, 4000048(%rsp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L13
movq %rsp, %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4000048(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L14:
leaq 8000048(%rsp), %rdi
movl $2, %ecx
movl $4000000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $1000000, %eax
.L15:
subl $1, %eax
jne .L15
movl $1000000, %ebx
.L16:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
subl $1, %ebx
jne .L16
movq 12000056(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $12000064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
jmp .L14
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecaddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecaddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#define N 1000000
__global__ void vecadd(int *a, int *b, int *c){
// determine global thread id
int idx = threadIdx.x + blockIdx.x * blockDim.x;
// do vector add, check if index is < N
if(idx<N) {
c[idx]=a[idx]+b[idx];
}
}
int main (int argc, char **argv){
int a_host[N], b_host[N], c_host[N];
int *a_device, *b_device, *c_device;
int i;
int blocksize=256;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil(N/(float)blocksize));
for (i=0;i<N;i++) a_host[i]=i;
for (i=0;i<N;i++) b_host[i]=i;
// alloc GPU memory
cudaMalloc((void**)&a_device,N*sizeof(int));
cudaMalloc((void**)&b_device,N*sizeof(int));
cudaMalloc((void**)&c_device,N*sizeof(int));
// transfer data
cudaMemcpy(a_device,a_host,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(b_device,b_host,N*sizeof(int),cudaMemcpyHostToDevice);
// invoke kernel
vecadd<<<dimGrid,dimBlock>>>(a_device,b_device,c_device);
// transfer result
cudaMemcpy(c_host,c_device,N*sizeof(int),cudaMemcpyDeviceToHost);
// check for correctness
for (i=0;i<N;i++) assert (c_host[i] == a_host[i] + b_host[i]);
// free GPU memory
for (i=0;i<N;i++) {
cudaFree(a_device);
cudaFree(b_device);
cudaFree(c_device);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 1000000
__global__ void vecadd(int *a, int *b, int *c){
// determine global thread id
int idx = threadIdx.x + blockIdx.x * blockDim.x;
// do vector add, check if index is < N
if(idx<N) {
c[idx]=a[idx]+b[idx];
}
}
int main (int argc, char **argv){
int a_host[N], b_host[N], c_host[N];
int *a_device, *b_device, *c_device;
int i;
int blocksize=256;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil(N/(float)blocksize));
for (i=0;i<N;i++) a_host[i]=i;
for (i=0;i<N;i++) b_host[i]=i;
// alloc GPU memory
hipMalloc((void**)&a_device,N*sizeof(int));
hipMalloc((void**)&b_device,N*sizeof(int));
hipMalloc((void**)&c_device,N*sizeof(int));
// transfer data
hipMemcpy(a_device,a_host,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(b_device,b_host,N*sizeof(int),hipMemcpyHostToDevice);
// invoke kernel
vecadd<<<dimGrid,dimBlock>>>(a_device,b_device,c_device);
// transfer result
hipMemcpy(c_host,c_device,N*sizeof(int),hipMemcpyDeviceToHost);
// check for correctness
for (i=0;i<N;i++) assert (c_host[i] == a_host[i] + b_host[i]);
// free GPU memory
for (i=0;i<N;i++) {
hipFree(a_device);
hipFree(b_device);
hipFree(c_device);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 1000000
__global__ void vecadd(int *a, int *b, int *c){
// determine global thread id
int idx = threadIdx.x + blockIdx.x * blockDim.x;
// do vector add, check if index is < N
if(idx<N) {
c[idx]=a[idx]+b[idx];
}
}
int main (int argc, char **argv){
int a_host[N], b_host[N], c_host[N];
int *a_device, *b_device, *c_device;
int i;
int blocksize=256;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil(N/(float)blocksize));
for (i=0;i<N;i++) a_host[i]=i;
for (i=0;i<N;i++) b_host[i]=i;
// alloc GPU memory
hipMalloc((void**)&a_device,N*sizeof(int));
hipMalloc((void**)&b_device,N*sizeof(int));
hipMalloc((void**)&c_device,N*sizeof(int));
// transfer data
hipMemcpy(a_device,a_host,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(b_device,b_host,N*sizeof(int),hipMemcpyHostToDevice);
// invoke kernel
vecadd<<<dimGrid,dimBlock>>>(a_device,b_device,c_device);
// transfer result
hipMemcpy(c_host,c_device,N*sizeof(int),hipMemcpyDeviceToHost);
// check for correctness
for (i=0;i<N;i++) assert (c_host[i] == a_host[i] + b_host[i]);
// free GPU memory
for (i=0;i<N;i++) {
hipFree(a_device);
hipFree(b_device);
hipFree(c_device);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecaddPiS_S_
.globl _Z6vecaddPiS_S_
.p2align 8
.type _Z6vecaddPiS_S_,@function
_Z6vecaddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0xf4240, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecaddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecaddPiS_S_, .Lfunc_end0-_Z6vecaddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecaddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecaddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 1000000
__global__ void vecadd(int *a, int *b, int *c){
// determine global thread id
int idx = threadIdx.x + blockIdx.x * blockDim.x;
// do vector add, check if index is < N
if(idx<N) {
c[idx]=a[idx]+b[idx];
}
}
int main (int argc, char **argv){
int a_host[N], b_host[N], c_host[N];
int *a_device, *b_device, *c_device;
int i;
int blocksize=256;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil(N/(float)blocksize));
for (i=0;i<N;i++) a_host[i]=i;
for (i=0;i<N;i++) b_host[i]=i;
// alloc GPU memory
hipMalloc((void**)&a_device,N*sizeof(int));
hipMalloc((void**)&b_device,N*sizeof(int));
hipMalloc((void**)&c_device,N*sizeof(int));
// transfer data
hipMemcpy(a_device,a_host,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(b_device,b_host,N*sizeof(int),hipMemcpyHostToDevice);
// invoke kernel
vecadd<<<dimGrid,dimBlock>>>(a_device,b_device,c_device);
// transfer result
hipMemcpy(c_host,c_device,N*sizeof(int),hipMemcpyDeviceToHost);
// check for correctness
for (i=0;i<N;i++) assert (c_host[i] == a_host[i] + b_host[i]);
// free GPU memory
for (i=0;i<N;i++) {
hipFree(a_device);
hipFree(b_device);
hipFree(c_device);
}
return 0;
} | .text
.file "lab2-2.hip"
.globl _Z21__device_stub__vecaddPiS_S_ # -- Begin function _Z21__device_stub__vecaddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecaddPiS_S_,@function
_Z21__device_stub__vecaddPiS_S_: # @_Z21__device_stub__vecaddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecaddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecaddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecaddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12000096, %rsp # imm = 0xB71B60
.cfi_def_cfa_offset 12000112
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 8000096(%rsp,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_1
# %bb.2: # %.preheader22.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader22
# =>This Inner Loop Header: Depth=1
movl %eax, 4000096(%rsp,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq %rsp, %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 16(%rsp), %rdi
leaq 8000096(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 4000096(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3651(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecaddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6: # %.preheader.preheader
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
movl $1000000, %ebx # imm = 0xF4240
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
decl %ebx
jne .LBB1_7
# %bb.8:
xorl %eax, %eax
addq $12000096, %rsp # imm = 0xB71B60
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecaddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecaddPiS_S_,@object # @_Z6vecaddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecaddPiS_S_
.p2align 3, 0x0
_Z6vecaddPiS_S_:
.quad _Z21__device_stub__vecaddPiS_S_
.size _Z6vecaddPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecaddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecaddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecaddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecaddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xf423f, PT ; /* 0x000f423f0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecaddPiS_S_
.globl _Z6vecaddPiS_S_
.p2align 8
.type _Z6vecaddPiS_S_,@function
_Z6vecaddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0xf4240, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecaddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecaddPiS_S_, .Lfunc_end0-_Z6vecaddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecaddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecaddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000812c0_00000000-6_lab2-2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecaddPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecaddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.globl _Z6vecaddPiS_S_
.type _Z6vecaddPiS_S_, @function
_Z6vecaddPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecaddPiS_S_, .-_Z6vecaddPiS_S_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -11997184(%rsp), %r11
.cfi_def_cfa 11, 11997200
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2880, %rsp
.cfi_def_cfa_offset 12000080
movq %fs:40, %rax
movq %rax, 12000056(%rsp)
xorl %eax, %eax
movl $256, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $3907, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
.L12:
movl %eax, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L12
movl $0, %eax
.L13:
movl %eax, 4000048(%rsp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L13
movq %rsp, %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4000048(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L14:
leaq 8000048(%rsp), %rdi
movl $2, %ecx
movl $4000000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $1000000, %eax
.L15:
subl $1, %eax
jne .L15
movl $1000000, %ebx
.L16:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
subl $1, %ebx
jne .L16
movq 12000056(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $12000064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
jmp .L14
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecaddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecaddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab2-2.hip"
.globl _Z21__device_stub__vecaddPiS_S_ # -- Begin function _Z21__device_stub__vecaddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecaddPiS_S_,@function
_Z21__device_stub__vecaddPiS_S_: # @_Z21__device_stub__vecaddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecaddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecaddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecaddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12000096, %rsp # imm = 0xB71B60
.cfi_def_cfa_offset 12000112
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 8000096(%rsp,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_1
# %bb.2: # %.preheader22.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader22
# =>This Inner Loop Header: Depth=1
movl %eax, 4000096(%rsp,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq %rsp, %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 16(%rsp), %rdi
leaq 8000096(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 4000096(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3651(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecaddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6: # %.preheader.preheader
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
movl $1000000, %ebx # imm = 0xF4240
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
decl %ebx
jne .LBB1_7
# %bb.8:
xorl %eax, %eax
addq $12000096, %rsp # imm = 0xB71B60
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecaddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecaddPiS_S_,@object # @_Z6vecaddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecaddPiS_S_
.p2align 3, 0x0
_Z6vecaddPiS_S_:
.quad _Z21__device_stub__vecaddPiS_S_
.size _Z6vecaddPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecaddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecaddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecaddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// (C) 2021, E. Wes Bethel
// sobel_gpu.cpp
// usage:
// sobel_gpu [no args, all is hard coded]
//
#include <iostream>
#include <vector>
#include <chrono>
#include <unistd.h>
#include <string.h>
#include <math.h>
// see https://en.wikipedia.org/wiki/Sobel_operator
// easy-to-find and change variables for the input.
// specify the name of a file containing data to be read in as bytes, along with
// dimensions [columns, rows]
// this is the original laughing zebra image
//static char input_fname[] = "../data/zebra-gray-int8";
//static int data_dims[2] = {3556, 2573}; // width=ncols, height=nrows
//char output_fname[] = "../data/processed-raw-int8-cpu.dat";
// this one is a 4x augmentation of the laughing zebra
static char input_fname[] = "../data/zebra-gray-int8-4x";
static int data_dims[2] = {7112, 5146}; // width=ncols, height=nrows
char output_fname[] = "../data/processed-raw-int8-4x-cpu.dat";
// see https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// macro to check for cuda errors. basic idea: wrap this macro around every cuda call
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//
// this function is callable only from device code
//
// perform the sobel filtering at a given i,j location
// input: float *s - the source data
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
//
// this routine computes Gx=gx*s centered at (i,j), Gy=gy*s centered at (i,j),
// and returns G = sqrt(Gx^2 + Gy^2)
// see https://en.wikipedia.org/wiki/Sobel_operator
//
__device__ float
sobel_filtered_pixel(float *s, int i, int j , int ncols, int nrows, float *gx, float *gy)
{
float gradX = 0.0;
float gradY = 0.0;
// ADD CODE HERE: add your code here for computing the sobel stencil computation at location (i,j)
// of input s, returning a float
if ((i > 0 && i < nrows -1) && (j > 0 && j < ncols -1)){
float gradX = gradX + gx[0] * s[(i * ncols + j) - ncols - 1] +
gx[1] * s[(i * ncols + j) - ncols] +
gx[2] * s[(i * ncols + j) - (ncols + 1)] +
gx[3] * s[(i * ncols + j) - 1] +
gx[4] * s[(i * ncols + j)] +
gx[5] * s[(i * ncols + j) + 1] +
gx[6] * s[(i * ncols + j) + ncols - 1] +
gx[7] * s[(i * ncols + j) + ncols] +
gx[8] * s[(i * ncols + j) + ncols + 1];
float gradY = gradY + gy[0] * s[(i * ncols + j) - ncols - 1] +
gy[1] * s[(i * ncols + j) - ncols] +
gy[2] * s[(i * ncols + j) - ncols + 1] +
gy[3] * s[(i * ncols + j) - 1] +
gy[4] * s[(i * ncols + j)] +
gy[5] * s[(i * ncols + j) + 1] +
gy[6] * s[(i * ncols + j) + ncols - 1] +
gy[7] * s[(i * ncols + j) + ncols] +
gy[8] * s[(i * ncols + j) + ncols + 1];
}
float gradXsquared = gradX * gradX;
float gradYsquared = gradY * gradY;
return sqrt(gradXsquared + gradYsquared);
}
//
// this function is the kernel that runs on the device
//
// this code will look at CUDA variables: blockIdx, blockDim, threadIdx, blockDim and gridDim
// to compute the index/stride to use in striding through the source array, calling the
// sobel_filtered_pixel() function at each location to do the work.
//
// input: float *s - the source data, size=rows*cols
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
// output: float *d - the buffer for the output, size=rows*cols.
//
__global__ void
sobel_kernel_gpu(float *s, // source image pixels
float *d, // dst image pixels
int n, // size of image cols*rows,
int nrows,
int ncols,
float *gx, float *gy) // gx and gy are stencil weights for the sobel filter
{
// ADD CODE HERE: insert your code here that iterates over every (i,j) of input, makes a call
// to sobel_filtered_pixel, and assigns the resulting value at location (i,j) in the output.
// because this is CUDA, you need to use CUDA built-in variables to compute an index and stride
// your processing motif will be very similar here to that we used for vector add in Lab #2
int dim = blockDim.x * gridDim.x;
int index = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = index; i < n; i += dim){
int row = i / ncols;
int col = i % ncols;
d[i] = sobel_filtered_pixel(s, row, col, ncols, nrows, gx, gy);
}
}
int
main (int ac, char *av[])
{
// input, output file names hard coded at top of file
// load the input file
off_t nvalues = data_dims[0]*data_dims[1];
unsigned char *in_data_bytes = (unsigned char *)malloc(sizeof(unsigned char)*nvalues);
FILE *f = fopen(input_fname,"r");
if (fread((void *)in_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error reading input file. \n");
fclose(f);
return 1;
}
else
printf(" Read data from the file %s \n", input_fname);
fclose(f);
#define ONE_OVER_255 0.003921568627451
// now convert input from byte, in range 0..255, to float, in range 0..1
float *in_data_floats;
gpuErrchk( cudaMallocManaged(&in_data_floats, sizeof(float)*nvalues) );
for (off_t i=0; i<nvalues; i++)
in_data_floats[i] = (float)in_data_bytes[i] * ONE_OVER_255;
// now, create a buffer for output
float *out_data_floats;
gpuErrchk( cudaMallocManaged(&out_data_floats, sizeof(float)*nvalues) );
for (int i=0;i<nvalues;i++)
out_data_floats[i] = 1.0; // assign "white" to all output values for debug
// define sobel filter weights, copy to a device accessible buffer
float Gx[9] = {1.0, 0.0, -1.0, 2.0, 0.0, -2.0, 1.0, 0.0, -1.0};
float Gy[9] = {1.0, 2.0, 1.0, 0.0, 0.0, 0.0, -1.0, -2.0, -1.0};
float *device_gx, *device_gy;
gpuErrchk( cudaMallocManaged(&device_gx, sizeof(float)*sizeof(Gx)) );
gpuErrchk( cudaMallocManaged(&device_gy, sizeof(float)*sizeof(Gy)) );
for (int i=0;i<9;i++) // copy from Gx/Gy to device_gx/device_gy
{
device_gx[i] = Gx[i];
device_gy[i] = Gy[i];
}
// now, induce memory movement to the GPU of the data in unified memory buffers
int deviceID=0; // assume GPU#0, always. OK assumption for this program
cudaMemPrefetchAsync((void *)in_data_floats, nvalues*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)out_data_floats, nvalues*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)device_gx, sizeof(Gx)*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)device_gy, sizeof(Gy)*sizeof(float), deviceID);
// set up to run the kernel
int nBlocks=1, nThreadsPerBlock=256;
// ADD CODE HERE: insert your code here to set a different number of thread blocks or # of threads per block
if (ac > 1){
nThreadsPerBlock = atoi(av[1]);
nBlocks = atoi(av[2]);
}
printf(" GPU configuration: %d blocks, %d threads per block \n", nBlocks, nThreadsPerBlock);
// invoke the kernel on the device
sobel_kernel_gpu<<<nBlocks, nThreadsPerBlock>>>(in_data_floats, out_data_floats, nvalues, data_dims[1], data_dims[0], device_gx, device_gy);
// wait for it to finish, check errors
gpuErrchk ( cudaDeviceSynchronize() );
// write output after converting from floats in range 0..1 to bytes in range 0..255
unsigned char *out_data_bytes = in_data_bytes; // just reuse the buffer from before
for (off_t i=0; i<nvalues; i++)
out_data_bytes[i] = (unsigned char)(out_data_floats[i] * 255.0);
f = fopen(output_fname,"w");
if (fwrite((void *)out_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error writing output file. \n");
fclose(f);
return 1;
}
else
printf(" Wrote the output file %s \n", output_fname);
fclose(f);
}
// eof | code for sm_80
Function : _Z16sobel_kernel_gpuPfS_iiiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, R2 ; /* 0x00000002000b7202 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x2e0 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000209000 */
/*00c0*/ IMAD.IADD R2, R0.reuse, 0x1, R11 ; /* 0x0000000100027824 */
/* 0x040fe200078e020b */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45070 */
/*00e0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a00 */
/*00f0*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0110*/ IADD3 R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a10 */
/* 0x000fe20007ffe000 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0150*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*0160*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fca00078e00ff */
/*0180*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0190*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fca00078e0205 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*01c0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0220*/ LOP3.LUT P0, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000780c0ff */
/*0230*/ @!P0 BRA 0x2d0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0250*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fc60000000f00 */
/*0260*/ IMAD.WIDE R2, R11, R2, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fc800078e0202 */
/*0270*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0290*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x000fe400078e020b */
/*02a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R2, R0, 0x4, R2 ; /* 0x0000000400027825 */
/* 0x001fd800078e0202 */
/*02c0*/ @P0 BRA 0x270 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fd400000001ff */
/*0300*/ IMAD.WIDE R2, R11, R10, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x001fe200078e020a */
/*0310*/ IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b7210 */
/* 0x000fc80007ffe000 */
/*0320*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0330*/ IMAD.WIDE R4, R0.reuse, 0x4, R2 ; /* 0x0000000400047825 */
/* 0x040fe200078e0202 */
/*0340*/ IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b7210 */
/* 0x000fc80007ffe000 */
/*0350*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101904 */
/*0360*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fe200078e0204 */
/*0370*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fc80003f06270 */
/*0380*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e2000c101904 */
/*0390*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fca00078e0206 */
/*03a0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0001e6000c101904 */
/*03b0*/ @!P0 BRA 0x300 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// (C) 2021, E. Wes Bethel
// sobel_gpu.cpp
// usage:
// sobel_gpu [no args, all is hard coded]
//
#include <iostream>
#include <vector>
#include <chrono>
#include <unistd.h>
#include <string.h>
#include <math.h>
// see https://en.wikipedia.org/wiki/Sobel_operator
// easy-to-find and change variables for the input.
// specify the name of a file containing data to be read in as bytes, along with
// dimensions [columns, rows]
// this is the original laughing zebra image
//static char input_fname[] = "../data/zebra-gray-int8";
//static int data_dims[2] = {3556, 2573}; // width=ncols, height=nrows
//char output_fname[] = "../data/processed-raw-int8-cpu.dat";
// this one is a 4x augmentation of the laughing zebra
static char input_fname[] = "../data/zebra-gray-int8-4x";
static int data_dims[2] = {7112, 5146}; // width=ncols, height=nrows
char output_fname[] = "../data/processed-raw-int8-4x-cpu.dat";
// see https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// macro to check for cuda errors. basic idea: wrap this macro around every cuda call
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//
// this function is callable only from device code
//
// perform the sobel filtering at a given i,j location
// input: float *s - the source data
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
//
// this routine computes Gx=gx*s centered at (i,j), Gy=gy*s centered at (i,j),
// and returns G = sqrt(Gx^2 + Gy^2)
// see https://en.wikipedia.org/wiki/Sobel_operator
//
__device__ float
sobel_filtered_pixel(float *s, int i, int j , int ncols, int nrows, float *gx, float *gy)
{
float gradX = 0.0;
float gradY = 0.0;
// ADD CODE HERE: add your code here for computing the sobel stencil computation at location (i,j)
// of input s, returning a float
if ((i > 0 && i < nrows -1) && (j > 0 && j < ncols -1)){
float gradX = gradX + gx[0] * s[(i * ncols + j) - ncols - 1] +
gx[1] * s[(i * ncols + j) - ncols] +
gx[2] * s[(i * ncols + j) - (ncols + 1)] +
gx[3] * s[(i * ncols + j) - 1] +
gx[4] * s[(i * ncols + j)] +
gx[5] * s[(i * ncols + j) + 1] +
gx[6] * s[(i * ncols + j) + ncols - 1] +
gx[7] * s[(i * ncols + j) + ncols] +
gx[8] * s[(i * ncols + j) + ncols + 1];
float gradY = gradY + gy[0] * s[(i * ncols + j) - ncols - 1] +
gy[1] * s[(i * ncols + j) - ncols] +
gy[2] * s[(i * ncols + j) - ncols + 1] +
gy[3] * s[(i * ncols + j) - 1] +
gy[4] * s[(i * ncols + j)] +
gy[5] * s[(i * ncols + j) + 1] +
gy[6] * s[(i * ncols + j) + ncols - 1] +
gy[7] * s[(i * ncols + j) + ncols] +
gy[8] * s[(i * ncols + j) + ncols + 1];
}
float gradXsquared = gradX * gradX;
float gradYsquared = gradY * gradY;
return sqrt(gradXsquared + gradYsquared);
}
//
// this function is the kernel that runs on the device
//
// this code will look at CUDA variables: blockIdx, blockDim, threadIdx, blockDim and gridDim
// to compute the index/stride to use in striding through the source array, calling the
// sobel_filtered_pixel() function at each location to do the work.
//
// input: float *s - the source data, size=rows*cols
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
// output: float *d - the buffer for the output, size=rows*cols.
//
__global__ void
sobel_kernel_gpu(float *s, // source image pixels
float *d, // dst image pixels
int n, // size of image cols*rows,
int nrows,
int ncols,
float *gx, float *gy) // gx and gy are stencil weights for the sobel filter
{
// ADD CODE HERE: insert your code here that iterates over every (i,j) of input, makes a call
// to sobel_filtered_pixel, and assigns the resulting value at location (i,j) in the output.
// because this is CUDA, you need to use CUDA built-in variables to compute an index and stride
// your processing motif will be very similar here to that we used for vector add in Lab #2
int dim = blockDim.x * gridDim.x;
int index = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = index; i < n; i += dim){
int row = i / ncols;
int col = i % ncols;
d[i] = sobel_filtered_pixel(s, row, col, ncols, nrows, gx, gy);
}
}
int
main (int ac, char *av[])
{
// input, output file names hard coded at top of file
// load the input file
off_t nvalues = data_dims[0]*data_dims[1];
unsigned char *in_data_bytes = (unsigned char *)malloc(sizeof(unsigned char)*nvalues);
FILE *f = fopen(input_fname,"r");
if (fread((void *)in_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error reading input file. \n");
fclose(f);
return 1;
}
else
printf(" Read data from the file %s \n", input_fname);
fclose(f);
#define ONE_OVER_255 0.003921568627451
// now convert input from byte, in range 0..255, to float, in range 0..1
float *in_data_floats;
gpuErrchk( cudaMallocManaged(&in_data_floats, sizeof(float)*nvalues) );
for (off_t i=0; i<nvalues; i++)
in_data_floats[i] = (float)in_data_bytes[i] * ONE_OVER_255;
// now, create a buffer for output
float *out_data_floats;
gpuErrchk( cudaMallocManaged(&out_data_floats, sizeof(float)*nvalues) );
for (int i=0;i<nvalues;i++)
out_data_floats[i] = 1.0; // assign "white" to all output values for debug
// define sobel filter weights, copy to a device accessible buffer
float Gx[9] = {1.0, 0.0, -1.0, 2.0, 0.0, -2.0, 1.0, 0.0, -1.0};
float Gy[9] = {1.0, 2.0, 1.0, 0.0, 0.0, 0.0, -1.0, -2.0, -1.0};
float *device_gx, *device_gy;
gpuErrchk( cudaMallocManaged(&device_gx, sizeof(float)*sizeof(Gx)) );
gpuErrchk( cudaMallocManaged(&device_gy, sizeof(float)*sizeof(Gy)) );
for (int i=0;i<9;i++) // copy from Gx/Gy to device_gx/device_gy
{
device_gx[i] = Gx[i];
device_gy[i] = Gy[i];
}
// now, induce memory movement to the GPU of the data in unified memory buffers
int deviceID=0; // assume GPU#0, always. OK assumption for this program
cudaMemPrefetchAsync((void *)in_data_floats, nvalues*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)out_data_floats, nvalues*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)device_gx, sizeof(Gx)*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)device_gy, sizeof(Gy)*sizeof(float), deviceID);
// set up to run the kernel
int nBlocks=1, nThreadsPerBlock=256;
// ADD CODE HERE: insert your code here to set a different number of thread blocks or # of threads per block
if (ac > 1){
nThreadsPerBlock = atoi(av[1]);
nBlocks = atoi(av[2]);
}
printf(" GPU configuration: %d blocks, %d threads per block \n", nBlocks, nThreadsPerBlock);
// invoke the kernel on the device
sobel_kernel_gpu<<<nBlocks, nThreadsPerBlock>>>(in_data_floats, out_data_floats, nvalues, data_dims[1], data_dims[0], device_gx, device_gy);
// wait for it to finish, check errors
gpuErrchk ( cudaDeviceSynchronize() );
// write output after converting from floats in range 0..1 to bytes in range 0..255
unsigned char *out_data_bytes = in_data_bytes; // just reuse the buffer from before
for (off_t i=0; i<nvalues; i++)
out_data_bytes[i] = (unsigned char)(out_data_floats[i] * 255.0);
f = fopen(output_fname,"w");
if (fwrite((void *)out_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error writing output file. \n");
fclose(f);
return 1;
}
else
printf(" Wrote the output file %s \n", output_fname);
fclose(f);
}
// eof | .file "tmpxft_0012b23b_00000000-6_sobel_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4149:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4149:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4144:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4144:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z20sobel_filtered_pixelPfiiiiS_S_
.type _Z20sobel_filtered_pixelPfiiiiS_S_, @function
_Z20sobel_filtered_pixelPfiiiiS_S_:
.LFB4145:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4145:
.size _Z20sobel_filtered_pixelPfiiiiS_S_, .-_Z20sobel_filtered_pixelPfiiiiS_S_
.globl _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
.type _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_, @function
_Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_:
.LFB4171:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16sobel_kernel_gpuPfS_iiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4171:
.size _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_, .-_Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
.globl _Z16sobel_kernel_gpuPfS_iiiS_S_
.type _Z16sobel_kernel_gpuPfS_iiiS_S_, @function
_Z16sobel_kernel_gpuPfS_iiiS_S_:
.LFB4172:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4172:
.size _Z16sobel_kernel_gpuPfS_iiiS_S_, .-_Z16sobel_kernel_gpuPfS_iiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "Error reading input file. \n"
.LC3:
.string " Read data from the file %s \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ItsJes/csc_746_hw5/main/sobel_gpu.cu"
.align 8
.LC11:
.string " GPU configuration: %d blocks, %d threads per block \n"
.section .rodata.str1.1
.LC13:
.string "w"
.LC14:
.string "Error writing output file. \n"
.LC15:
.string " Wrote the output file %s \n"
.text
.globl main
.type main, @function
main:
.LFB4146:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $36598352, %edi
call malloc@PLT
movq %rax, %rbx
leaq .LC1(%rip), %rsi
leaq _ZL11input_fname(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rax, %r8
movl $36598352, %ecx
movl $1, %edx
movl $36598352, %esi
movq %rbx, %rdi
call __fread_chk@PLT
cmpq $36598352, %rax
je .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movl $1, %eax
.L21:
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq _ZL11input_fname(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $146393408, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $161, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
movsd .LC5(%rip), %xmm1
.L24:
movzbl (%rbx,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $36598352, %rax
jne .L24
leaq 16(%rsp), %rdi
movl $1, %edx
movl $146393408, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $168, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
movss .LC6(%rip), %xmm0
.L25:
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $146393408, %rax
jne .L25
movss .LC6(%rip), %xmm1
movss %xmm1, 64(%rsp)
movl $0x00000000, 68(%rsp)
movss .LC8(%rip), %xmm0
movss %xmm0, 72(%rsp)
movss .LC9(%rip), %xmm3
movss %xmm3, 76(%rsp)
movl $0x00000000, 80(%rsp)
movss .LC10(%rip), %xmm2
movss %xmm2, 84(%rsp)
movss %xmm1, 88(%rsp)
movl $0x00000000, 92(%rsp)
movss %xmm0, 96(%rsp)
movss %xmm1, 112(%rsp)
movss %xmm3, 116(%rsp)
movss %xmm1, 120(%rsp)
movl $0x00000000, 124(%rsp)
movl $0x00000000, 128(%rsp)
movl $0x00000000, 132(%rsp)
movss %xmm0, 136(%rsp)
movss %xmm2, 140(%rsp)
movss %xmm0, 144(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $144, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $176, %edx
leaq .LC4(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movl $1, %edx
movl $144, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $177, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
.L26:
movss 64(%rsp,%rax), %xmm0
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movss 112(%rsp,%rax), %xmm0
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $36, %rax
jne .L26
movl $0, %ecx
movl $0, %edx
movl $146393408, %esi
movq 8(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $0, %edx
movl $146393408, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $0, %edx
movl $144, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $0, %edx
movl $144, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
cmpl $1, %ebp
jg .L39
movl $256, %r13d
movl $1, %ebp
.L27:
movl %r13d, %ecx
movl %ebp, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L28:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $209, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rcx
movl $0, %eax
movsd .LC12(%rip), %xmm1
.L29:
pxor %xmm0, %xmm0
cvtss2sd (%rcx,%rax,4), %xmm0
mulsd %xmm1, %xmm0
cvttsd2sil %xmm0, %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq $36598352, %rax
jne .L29
leaq .LC13(%rip), %rsi
leaq output_fname(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, %rcx
movl $36598352, %edx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
cmpq $36598352, %rax
je .L30
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movl $1, %eax
jmp .L21
.L39:
movq 8(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L27
.L40:
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq 40(%rsp)
.cfi_def_cfa_offset 224
movq 40(%rsp), %r9
movl $7112, %r8d
movl $5146, %ecx
movl $36598352, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L28
.L30:
leaq output_fname(%rip), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movl $0, %eax
jmp .L21
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4146:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z16sobel_kernel_gpuPfS_iiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4174:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sobel_kernel_gpuPfS_iiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4174:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl output_fname
.data
.align 32
.type output_fname, @object
.size output_fname, 38
output_fname:
.string "../data/processed-raw-int8-4x-cpu.dat"
.align 16
.type _ZL11input_fname, @object
.size _ZL11input_fname, 27
_ZL11input_fname:
.string "../data/zebra-gray-int8-4x"
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 269488167
.long 1064308752
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.align 4
.LC8:
.long -1082130432
.align 4
.LC9:
.long 1073741824
.align 4
.LC10:
.long -1073741824
.section .rodata.cst8
.align 8
.LC12:
.long 0
.long 1081073664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// (C) 2021, E. Wes Bethel
// sobel_gpu.cpp
// usage:
// sobel_gpu [no args, all is hard coded]
//
#include <iostream>
#include <vector>
#include <chrono>
#include <unistd.h>
#include <string.h>
#include <math.h>
// see https://en.wikipedia.org/wiki/Sobel_operator
// easy-to-find and change variables for the input.
// specify the name of a file containing data to be read in as bytes, along with
// dimensions [columns, rows]
// this is the original laughing zebra image
//static char input_fname[] = "../data/zebra-gray-int8";
//static int data_dims[2] = {3556, 2573}; // width=ncols, height=nrows
//char output_fname[] = "../data/processed-raw-int8-cpu.dat";
// this one is a 4x augmentation of the laughing zebra
static char input_fname[] = "../data/zebra-gray-int8-4x";
static int data_dims[2] = {7112, 5146}; // width=ncols, height=nrows
char output_fname[] = "../data/processed-raw-int8-4x-cpu.dat";
// see https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// macro to check for cuda errors. basic idea: wrap this macro around every cuda call
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//
// this function is callable only from device code
//
// perform the sobel filtering at a given i,j location
// input: float *s - the source data
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
//
// this routine computes Gx=gx*s centered at (i,j), Gy=gy*s centered at (i,j),
// and returns G = sqrt(Gx^2 + Gy^2)
// see https://en.wikipedia.org/wiki/Sobel_operator
//
__device__ float
sobel_filtered_pixel(float *s, int i, int j , int ncols, int nrows, float *gx, float *gy)
{
float gradX = 0.0;
float gradY = 0.0;
// ADD CODE HERE: add your code here for computing the sobel stencil computation at location (i,j)
// of input s, returning a float
if ((i > 0 && i < nrows -1) && (j > 0 && j < ncols -1)){
float gradX = gradX + gx[0] * s[(i * ncols + j) - ncols - 1] +
gx[1] * s[(i * ncols + j) - ncols] +
gx[2] * s[(i * ncols + j) - (ncols + 1)] +
gx[3] * s[(i * ncols + j) - 1] +
gx[4] * s[(i * ncols + j)] +
gx[5] * s[(i * ncols + j) + 1] +
gx[6] * s[(i * ncols + j) + ncols - 1] +
gx[7] * s[(i * ncols + j) + ncols] +
gx[8] * s[(i * ncols + j) + ncols + 1];
float gradY = gradY + gy[0] * s[(i * ncols + j) - ncols - 1] +
gy[1] * s[(i * ncols + j) - ncols] +
gy[2] * s[(i * ncols + j) - ncols + 1] +
gy[3] * s[(i * ncols + j) - 1] +
gy[4] * s[(i * ncols + j)] +
gy[5] * s[(i * ncols + j) + 1] +
gy[6] * s[(i * ncols + j) + ncols - 1] +
gy[7] * s[(i * ncols + j) + ncols] +
gy[8] * s[(i * ncols + j) + ncols + 1];
}
float gradXsquared = gradX * gradX;
float gradYsquared = gradY * gradY;
return sqrt(gradXsquared + gradYsquared);
}
//
// this function is the kernel that runs on the device
//
// this code will look at CUDA variables: blockIdx, blockDim, threadIdx, blockDim and gridDim
// to compute the index/stride to use in striding through the source array, calling the
// sobel_filtered_pixel() function at each location to do the work.
//
// input: float *s - the source data, size=rows*cols
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
// output: float *d - the buffer for the output, size=rows*cols.
//
__global__ void
sobel_kernel_gpu(float *s, // source image pixels
float *d, // dst image pixels
int n, // size of image cols*rows,
int nrows,
int ncols,
float *gx, float *gy) // gx and gy are stencil weights for the sobel filter
{
// ADD CODE HERE: insert your code here that iterates over every (i,j) of input, makes a call
// to sobel_filtered_pixel, and assigns the resulting value at location (i,j) in the output.
// because this is CUDA, you need to use CUDA built-in variables to compute an index and stride
// your processing motif will be very similar here to that we used for vector add in Lab #2
int dim = blockDim.x * gridDim.x;
int index = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = index; i < n; i += dim){
int row = i / ncols;
int col = i % ncols;
d[i] = sobel_filtered_pixel(s, row, col, ncols, nrows, gx, gy);
}
}
int
main (int ac, char *av[])
{
// input, output file names hard coded at top of file
// load the input file
off_t nvalues = data_dims[0]*data_dims[1];
unsigned char *in_data_bytes = (unsigned char *)malloc(sizeof(unsigned char)*nvalues);
FILE *f = fopen(input_fname,"r");
if (fread((void *)in_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error reading input file. \n");
fclose(f);
return 1;
}
else
printf(" Read data from the file %s \n", input_fname);
fclose(f);
#define ONE_OVER_255 0.003921568627451
// now convert input from byte, in range 0..255, to float, in range 0..1
float *in_data_floats;
gpuErrchk( cudaMallocManaged(&in_data_floats, sizeof(float)*nvalues) );
for (off_t i=0; i<nvalues; i++)
in_data_floats[i] = (float)in_data_bytes[i] * ONE_OVER_255;
// now, create a buffer for output
float *out_data_floats;
gpuErrchk( cudaMallocManaged(&out_data_floats, sizeof(float)*nvalues) );
for (int i=0;i<nvalues;i++)
out_data_floats[i] = 1.0; // assign "white" to all output values for debug
// define sobel filter weights, copy to a device accessible buffer
float Gx[9] = {1.0, 0.0, -1.0, 2.0, 0.0, -2.0, 1.0, 0.0, -1.0};
float Gy[9] = {1.0, 2.0, 1.0, 0.0, 0.0, 0.0, -1.0, -2.0, -1.0};
float *device_gx, *device_gy;
gpuErrchk( cudaMallocManaged(&device_gx, sizeof(float)*sizeof(Gx)) );
gpuErrchk( cudaMallocManaged(&device_gy, sizeof(float)*sizeof(Gy)) );
for (int i=0;i<9;i++) // copy from Gx/Gy to device_gx/device_gy
{
device_gx[i] = Gx[i];
device_gy[i] = Gy[i];
}
// now, induce memory movement to the GPU of the data in unified memory buffers
int deviceID=0; // assume GPU#0, always. OK assumption for this program
cudaMemPrefetchAsync((void *)in_data_floats, nvalues*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)out_data_floats, nvalues*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)device_gx, sizeof(Gx)*sizeof(float), deviceID);
cudaMemPrefetchAsync((void *)device_gy, sizeof(Gy)*sizeof(float), deviceID);
// set up to run the kernel
int nBlocks=1, nThreadsPerBlock=256;
// ADD CODE HERE: insert your code here to set a different number of thread blocks or # of threads per block
if (ac > 1){
nThreadsPerBlock = atoi(av[1]);
nBlocks = atoi(av[2]);
}
printf(" GPU configuration: %d blocks, %d threads per block \n", nBlocks, nThreadsPerBlock);
// invoke the kernel on the device
sobel_kernel_gpu<<<nBlocks, nThreadsPerBlock>>>(in_data_floats, out_data_floats, nvalues, data_dims[1], data_dims[0], device_gx, device_gy);
// wait for it to finish, check errors
gpuErrchk ( cudaDeviceSynchronize() );
// write output after converting from floats in range 0..1 to bytes in range 0..255
unsigned char *out_data_bytes = in_data_bytes; // just reuse the buffer from before
for (off_t i=0; i<nvalues; i++)
out_data_bytes[i] = (unsigned char)(out_data_floats[i] * 255.0);
f = fopen(output_fname,"w");
if (fwrite((void *)out_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error writing output file. \n");
fclose(f);
return 1;
}
else
printf(" Wrote the output file %s \n", output_fname);
fclose(f);
}
// eof | //
// (C) 2021, E. Wes Bethel
// sobel_gpu.cpp
// usage:
// sobel_gpu [no args, all is hard coded]
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <chrono>
#include <unistd.h>
#include <string.h>
#include <math.h>
// see https://en.wikipedia.org/wiki/Sobel_operator
// easy-to-find and change variables for the input.
// specify the name of a file containing data to be read in as bytes, along with
// dimensions [columns, rows]
// this is the original laughing zebra image
//static char input_fname[] = "../data/zebra-gray-int8";
//static int data_dims[2] = {3556, 2573}; // width=ncols, height=nrows
//char output_fname[] = "../data/processed-raw-int8-cpu.dat";
// this one is a 4x augmentation of the laughing zebra
static char input_fname[] = "../data/zebra-gray-int8-4x";
static int data_dims[2] = {7112, 5146}; // width=ncols, height=nrows
char output_fname[] = "../data/processed-raw-int8-4x-cpu.dat";
// see https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// macro to check for cuda errors. basic idea: wrap this macro around every cuda call
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//
// this function is callable only from device code
//
// perform the sobel filtering at a given i,j location
// input: float *s - the source data
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
//
// this routine computes Gx=gx*s centered at (i,j), Gy=gy*s centered at (i,j),
// and returns G = sqrt(Gx^2 + Gy^2)
// see https://en.wikipedia.org/wiki/Sobel_operator
//
__device__ float
sobel_filtered_pixel(float *s, int i, int j , int ncols, int nrows, float *gx, float *gy)
{
float gradX = 0.0;
float gradY = 0.0;
// ADD CODE HERE: add your code here for computing the sobel stencil computation at location (i,j)
// of input s, returning a float
if ((i > 0 && i < nrows -1) && (j > 0 && j < ncols -1)){
float gradX = gradX + gx[0] * s[(i * ncols + j) - ncols - 1] +
gx[1] * s[(i * ncols + j) - ncols] +
gx[2] * s[(i * ncols + j) - (ncols + 1)] +
gx[3] * s[(i * ncols + j) - 1] +
gx[4] * s[(i * ncols + j)] +
gx[5] * s[(i * ncols + j) + 1] +
gx[6] * s[(i * ncols + j) + ncols - 1] +
gx[7] * s[(i * ncols + j) + ncols] +
gx[8] * s[(i * ncols + j) + ncols + 1];
float gradY = gradY + gy[0] * s[(i * ncols + j) - ncols - 1] +
gy[1] * s[(i * ncols + j) - ncols] +
gy[2] * s[(i * ncols + j) - ncols + 1] +
gy[3] * s[(i * ncols + j) - 1] +
gy[4] * s[(i * ncols + j)] +
gy[5] * s[(i * ncols + j) + 1] +
gy[6] * s[(i * ncols + j) + ncols - 1] +
gy[7] * s[(i * ncols + j) + ncols] +
gy[8] * s[(i * ncols + j) + ncols + 1];
}
float gradXsquared = gradX * gradX;
float gradYsquared = gradY * gradY;
return sqrt(gradXsquared + gradYsquared);
}
//
// this function is the kernel that runs on the device
//
// this code will look at CUDA variables: blockIdx, blockDim, threadIdx, blockDim and gridDim
// to compute the index/stride to use in striding through the source array, calling the
// sobel_filtered_pixel() function at each location to do the work.
//
// input: float *s - the source data, size=rows*cols
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
// output: float *d - the buffer for the output, size=rows*cols.
//
__global__ void
sobel_kernel_gpu(float *s, // source image pixels
float *d, // dst image pixels
int n, // size of image cols*rows,
int nrows,
int ncols,
float *gx, float *gy) // gx and gy are stencil weights for the sobel filter
{
// ADD CODE HERE: insert your code here that iterates over every (i,j) of input, makes a call
// to sobel_filtered_pixel, and assigns the resulting value at location (i,j) in the output.
// because this is CUDA, you need to use CUDA built-in variables to compute an index and stride
// your processing motif will be very similar here to that we used for vector add in Lab #2
int dim = blockDim.x * gridDim.x;
int index = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = index; i < n; i += dim){
int row = i / ncols;
int col = i % ncols;
d[i] = sobel_filtered_pixel(s, row, col, ncols, nrows, gx, gy);
}
}
int
main (int ac, char *av[])
{
// input, output file names hard coded at top of file
// load the input file
off_t nvalues = data_dims[0]*data_dims[1];
unsigned char *in_data_bytes = (unsigned char *)malloc(sizeof(unsigned char)*nvalues);
FILE *f = fopen(input_fname,"r");
if (fread((void *)in_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error reading input file. \n");
fclose(f);
return 1;
}
else
printf(" Read data from the file %s \n", input_fname);
fclose(f);
#define ONE_OVER_255 0.003921568627451
// now convert input from byte, in range 0..255, to float, in range 0..1
float *in_data_floats;
gpuErrchk( hipMallocManaged(&in_data_floats, sizeof(float)*nvalues) );
for (off_t i=0; i<nvalues; i++)
in_data_floats[i] = (float)in_data_bytes[i] * ONE_OVER_255;
// now, create a buffer for output
float *out_data_floats;
gpuErrchk( hipMallocManaged(&out_data_floats, sizeof(float)*nvalues) );
for (int i=0;i<nvalues;i++)
out_data_floats[i] = 1.0; // assign "white" to all output values for debug
// define sobel filter weights, copy to a device accessible buffer
float Gx[9] = {1.0, 0.0, -1.0, 2.0, 0.0, -2.0, 1.0, 0.0, -1.0};
float Gy[9] = {1.0, 2.0, 1.0, 0.0, 0.0, 0.0, -1.0, -2.0, -1.0};
float *device_gx, *device_gy;
gpuErrchk( hipMallocManaged(&device_gx, sizeof(float)*sizeof(Gx)) );
gpuErrchk( hipMallocManaged(&device_gy, sizeof(float)*sizeof(Gy)) );
for (int i=0;i<9;i++) // copy from Gx/Gy to device_gx/device_gy
{
device_gx[i] = Gx[i];
device_gy[i] = Gy[i];
}
// now, induce memory movement to the GPU of the data in unified memory buffers
int deviceID=0; // assume GPU#0, always. OK assumption for this program
hipMemPrefetchAsync((void *)in_data_floats, nvalues*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)out_data_floats, nvalues*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)device_gx, sizeof(Gx)*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)device_gy, sizeof(Gy)*sizeof(float), deviceID);
// set up to run the kernel
int nBlocks=1, nThreadsPerBlock=256;
// ADD CODE HERE: insert your code here to set a different number of thread blocks or # of threads per block
if (ac > 1){
nThreadsPerBlock = atoi(av[1]);
nBlocks = atoi(av[2]);
}
printf(" GPU configuration: %d blocks, %d threads per block \n", nBlocks, nThreadsPerBlock);
// invoke the kernel on the device
sobel_kernel_gpu<<<nBlocks, nThreadsPerBlock>>>(in_data_floats, out_data_floats, nvalues, data_dims[1], data_dims[0], device_gx, device_gy);
// wait for it to finish, check errors
gpuErrchk ( hipDeviceSynchronize() );
// write output after converting from floats in range 0..1 to bytes in range 0..255
unsigned char *out_data_bytes = in_data_bytes; // just reuse the buffer from before
for (off_t i=0; i<nvalues; i++)
out_data_bytes[i] = (unsigned char)(out_data_floats[i] * 255.0);
f = fopen(output_fname,"w");
if (fwrite((void *)out_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error writing output file. \n");
fclose(f);
return 1;
}
else
printf(" Wrote the output file %s \n", output_fname);
fclose(f);
}
// eof |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// (C) 2021, E. Wes Bethel
// sobel_gpu.cpp
// usage:
// sobel_gpu [no args, all is hard coded]
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <chrono>
#include <unistd.h>
#include <string.h>
#include <math.h>
// see https://en.wikipedia.org/wiki/Sobel_operator
// easy-to-find and change variables for the input.
// specify the name of a file containing data to be read in as bytes, along with
// dimensions [columns, rows]
// this is the original laughing zebra image
//static char input_fname[] = "../data/zebra-gray-int8";
//static int data_dims[2] = {3556, 2573}; // width=ncols, height=nrows
//char output_fname[] = "../data/processed-raw-int8-cpu.dat";
// this one is a 4x augmentation of the laughing zebra
static char input_fname[] = "../data/zebra-gray-int8-4x";
static int data_dims[2] = {7112, 5146}; // width=ncols, height=nrows
char output_fname[] = "../data/processed-raw-int8-4x-cpu.dat";
// see https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// macro to check for cuda errors. basic idea: wrap this macro around every cuda call
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//
// this function is callable only from device code
//
// perform the sobel filtering at a given i,j location
// input: float *s - the source data
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
//
// this routine computes Gx=gx*s centered at (i,j), Gy=gy*s centered at (i,j),
// and returns G = sqrt(Gx^2 + Gy^2)
// see https://en.wikipedia.org/wiki/Sobel_operator
//
__device__ float
sobel_filtered_pixel(float *s, int i, int j , int ncols, int nrows, float *gx, float *gy)
{
float gradX = 0.0;
float gradY = 0.0;
// ADD CODE HERE: add your code here for computing the sobel stencil computation at location (i,j)
// of input s, returning a float
if ((i > 0 && i < nrows -1) && (j > 0 && j < ncols -1)){
float gradX = gradX + gx[0] * s[(i * ncols + j) - ncols - 1] +
gx[1] * s[(i * ncols + j) - ncols] +
gx[2] * s[(i * ncols + j) - (ncols + 1)] +
gx[3] * s[(i * ncols + j) - 1] +
gx[4] * s[(i * ncols + j)] +
gx[5] * s[(i * ncols + j) + 1] +
gx[6] * s[(i * ncols + j) + ncols - 1] +
gx[7] * s[(i * ncols + j) + ncols] +
gx[8] * s[(i * ncols + j) + ncols + 1];
float gradY = gradY + gy[0] * s[(i * ncols + j) - ncols - 1] +
gy[1] * s[(i * ncols + j) - ncols] +
gy[2] * s[(i * ncols + j) - ncols + 1] +
gy[3] * s[(i * ncols + j) - 1] +
gy[4] * s[(i * ncols + j)] +
gy[5] * s[(i * ncols + j) + 1] +
gy[6] * s[(i * ncols + j) + ncols - 1] +
gy[7] * s[(i * ncols + j) + ncols] +
gy[8] * s[(i * ncols + j) + ncols + 1];
}
float gradXsquared = gradX * gradX;
float gradYsquared = gradY * gradY;
return sqrt(gradXsquared + gradYsquared);
}
//
// this function is the kernel that runs on the device
//
// this code will look at CUDA variables: blockIdx, blockDim, threadIdx, blockDim and gridDim
// to compute the index/stride to use in striding through the source array, calling the
// sobel_filtered_pixel() function at each location to do the work.
//
// input: float *s - the source data, size=rows*cols
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
// output: float *d - the buffer for the output, size=rows*cols.
//
__global__ void
sobel_kernel_gpu(float *s, // source image pixels
float *d, // dst image pixels
int n, // size of image cols*rows,
int nrows,
int ncols,
float *gx, float *gy) // gx and gy are stencil weights for the sobel filter
{
// ADD CODE HERE: insert your code here that iterates over every (i,j) of input, makes a call
// to sobel_filtered_pixel, and assigns the resulting value at location (i,j) in the output.
// because this is CUDA, you need to use CUDA built-in variables to compute an index and stride
// your processing motif will be very similar here to that we used for vector add in Lab #2
int dim = blockDim.x * gridDim.x;
int index = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = index; i < n; i += dim){
int row = i / ncols;
int col = i % ncols;
d[i] = sobel_filtered_pixel(s, row, col, ncols, nrows, gx, gy);
}
}
int
main (int ac, char *av[])
{
// input, output file names hard coded at top of file
// load the input file
off_t nvalues = data_dims[0]*data_dims[1];
unsigned char *in_data_bytes = (unsigned char *)malloc(sizeof(unsigned char)*nvalues);
FILE *f = fopen(input_fname,"r");
if (fread((void *)in_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error reading input file. \n");
fclose(f);
return 1;
}
else
printf(" Read data from the file %s \n", input_fname);
fclose(f);
#define ONE_OVER_255 0.003921568627451
// now convert input from byte, in range 0..255, to float, in range 0..1
float *in_data_floats;
gpuErrchk( hipMallocManaged(&in_data_floats, sizeof(float)*nvalues) );
for (off_t i=0; i<nvalues; i++)
in_data_floats[i] = (float)in_data_bytes[i] * ONE_OVER_255;
// now, create a buffer for output
float *out_data_floats;
gpuErrchk( hipMallocManaged(&out_data_floats, sizeof(float)*nvalues) );
for (int i=0;i<nvalues;i++)
out_data_floats[i] = 1.0; // assign "white" to all output values for debug
// define sobel filter weights, copy to a device accessible buffer
float Gx[9] = {1.0, 0.0, -1.0, 2.0, 0.0, -2.0, 1.0, 0.0, -1.0};
float Gy[9] = {1.0, 2.0, 1.0, 0.0, 0.0, 0.0, -1.0, -2.0, -1.0};
float *device_gx, *device_gy;
gpuErrchk( hipMallocManaged(&device_gx, sizeof(float)*sizeof(Gx)) );
gpuErrchk( hipMallocManaged(&device_gy, sizeof(float)*sizeof(Gy)) );
for (int i=0;i<9;i++) // copy from Gx/Gy to device_gx/device_gy
{
device_gx[i] = Gx[i];
device_gy[i] = Gy[i];
}
// now, induce memory movement to the GPU of the data in unified memory buffers
int deviceID=0; // assume GPU#0, always. OK assumption for this program
hipMemPrefetchAsync((void *)in_data_floats, nvalues*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)out_data_floats, nvalues*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)device_gx, sizeof(Gx)*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)device_gy, sizeof(Gy)*sizeof(float), deviceID);
// set up to run the kernel
int nBlocks=1, nThreadsPerBlock=256;
// ADD CODE HERE: insert your code here to set a different number of thread blocks or # of threads per block
if (ac > 1){
nThreadsPerBlock = atoi(av[1]);
nBlocks = atoi(av[2]);
}
printf(" GPU configuration: %d blocks, %d threads per block \n", nBlocks, nThreadsPerBlock);
// invoke the kernel on the device
sobel_kernel_gpu<<<nBlocks, nThreadsPerBlock>>>(in_data_floats, out_data_floats, nvalues, data_dims[1], data_dims[0], device_gx, device_gy);
// wait for it to finish, check errors
gpuErrchk ( hipDeviceSynchronize() );
// write output after converting from floats in range 0..1 to bytes in range 0..255
unsigned char *out_data_bytes = in_data_bytes; // just reuse the buffer from before
for (off_t i=0; i<nvalues; i++)
out_data_bytes[i] = (unsigned char)(out_data_floats[i] * 255.0);
f = fopen(output_fname,"w");
if (fwrite((void *)out_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error writing output file. \n");
fclose(f);
return 1;
}
else
printf(" Wrote the output file %s \n", output_fname);
fclose(f);
}
// eof | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sobel_kernel_gpuPfS_iiiS_S_
.globl _Z16sobel_kernel_gpuPfS_iiiS_S_
.p2align 8
.type _Z16sobel_kernel_gpuPfS_iiiS_S_,@function
_Z16sobel_kernel_gpuPfS_iiiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_mov_b32 s1, 0
s_lshl_b64 s[4:5], s[2:3], 2
.LBB0_2:
v_add_nc_u32_e32 v1, s2, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sobel_kernel_gpuPfS_iiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sobel_kernel_gpuPfS_iiiS_S_, .Lfunc_end0-_Z16sobel_kernel_gpuPfS_iiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sobel_kernel_gpuPfS_iiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sobel_kernel_gpuPfS_iiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// (C) 2021, E. Wes Bethel
// sobel_gpu.cpp
// usage:
// sobel_gpu [no args, all is hard coded]
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <chrono>
#include <unistd.h>
#include <string.h>
#include <math.h>
// see https://en.wikipedia.org/wiki/Sobel_operator
// easy-to-find and change variables for the input.
// specify the name of a file containing data to be read in as bytes, along with
// dimensions [columns, rows]
// this is the original laughing zebra image
//static char input_fname[] = "../data/zebra-gray-int8";
//static int data_dims[2] = {3556, 2573}; // width=ncols, height=nrows
//char output_fname[] = "../data/processed-raw-int8-cpu.dat";
// this one is a 4x augmentation of the laughing zebra
static char input_fname[] = "../data/zebra-gray-int8-4x";
static int data_dims[2] = {7112, 5146}; // width=ncols, height=nrows
char output_fname[] = "../data/processed-raw-int8-4x-cpu.dat";
// see https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// macro to check for cuda errors. basic idea: wrap this macro around every cuda call
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//
// this function is callable only from device code
//
// perform the sobel filtering at a given i,j location
// input: float *s - the source data
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
//
// this routine computes Gx=gx*s centered at (i,j), Gy=gy*s centered at (i,j),
// and returns G = sqrt(Gx^2 + Gy^2)
// see https://en.wikipedia.org/wiki/Sobel_operator
//
__device__ float
sobel_filtered_pixel(float *s, int i, int j , int ncols, int nrows, float *gx, float *gy)
{
float gradX = 0.0;
float gradY = 0.0;
// ADD CODE HERE: add your code here for computing the sobel stencil computation at location (i,j)
// of input s, returning a float
if ((i > 0 && i < nrows -1) && (j > 0 && j < ncols -1)){
float gradX = gradX + gx[0] * s[(i * ncols + j) - ncols - 1] +
gx[1] * s[(i * ncols + j) - ncols] +
gx[2] * s[(i * ncols + j) - (ncols + 1)] +
gx[3] * s[(i * ncols + j) - 1] +
gx[4] * s[(i * ncols + j)] +
gx[5] * s[(i * ncols + j) + 1] +
gx[6] * s[(i * ncols + j) + ncols - 1] +
gx[7] * s[(i * ncols + j) + ncols] +
gx[8] * s[(i * ncols + j) + ncols + 1];
float gradY = gradY + gy[0] * s[(i * ncols + j) - ncols - 1] +
gy[1] * s[(i * ncols + j) - ncols] +
gy[2] * s[(i * ncols + j) - ncols + 1] +
gy[3] * s[(i * ncols + j) - 1] +
gy[4] * s[(i * ncols + j)] +
gy[5] * s[(i * ncols + j) + 1] +
gy[6] * s[(i * ncols + j) + ncols - 1] +
gy[7] * s[(i * ncols + j) + ncols] +
gy[8] * s[(i * ncols + j) + ncols + 1];
}
float gradXsquared = gradX * gradX;
float gradYsquared = gradY * gradY;
return sqrt(gradXsquared + gradYsquared);
}
//
// this function is the kernel that runs on the device
//
// this code will look at CUDA variables: blockIdx, blockDim, threadIdx, blockDim and gridDim
// to compute the index/stride to use in striding through the source array, calling the
// sobel_filtered_pixel() function at each location to do the work.
//
// input: float *s - the source data, size=rows*cols
// input: int i,j - the location of the pixel in the source data where we want to center our sobel convolution
// input: int nrows, ncols: the dimensions of the input and output image buffers
// input: float *gx, gy: arrays of length 9 each, these are logically 3x3 arrays of sobel filter weights
// output: float *d - the buffer for the output, size=rows*cols.
//
__global__ void
sobel_kernel_gpu(float *s, // source image pixels
float *d, // dst image pixels
int n, // size of image cols*rows,
int nrows,
int ncols,
float *gx, float *gy) // gx and gy are stencil weights for the sobel filter
{
// ADD CODE HERE: insert your code here that iterates over every (i,j) of input, makes a call
// to sobel_filtered_pixel, and assigns the resulting value at location (i,j) in the output.
// because this is CUDA, you need to use CUDA built-in variables to compute an index and stride
// your processing motif will be very similar here to that we used for vector add in Lab #2
int dim = blockDim.x * gridDim.x;
int index = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = index; i < n; i += dim){
int row = i / ncols;
int col = i % ncols;
d[i] = sobel_filtered_pixel(s, row, col, ncols, nrows, gx, gy);
}
}
int
main (int ac, char *av[])
{
// input, output file names hard coded at top of file
// load the input file
off_t nvalues = data_dims[0]*data_dims[1];
unsigned char *in_data_bytes = (unsigned char *)malloc(sizeof(unsigned char)*nvalues);
FILE *f = fopen(input_fname,"r");
if (fread((void *)in_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error reading input file. \n");
fclose(f);
return 1;
}
else
printf(" Read data from the file %s \n", input_fname);
fclose(f);
#define ONE_OVER_255 0.003921568627451
// now convert input from byte, in range 0..255, to float, in range 0..1
float *in_data_floats;
gpuErrchk( hipMallocManaged(&in_data_floats, sizeof(float)*nvalues) );
for (off_t i=0; i<nvalues; i++)
in_data_floats[i] = (float)in_data_bytes[i] * ONE_OVER_255;
// now, create a buffer for output
float *out_data_floats;
gpuErrchk( hipMallocManaged(&out_data_floats, sizeof(float)*nvalues) );
for (int i=0;i<nvalues;i++)
out_data_floats[i] = 1.0; // assign "white" to all output values for debug
// define sobel filter weights, copy to a device accessible buffer
float Gx[9] = {1.0, 0.0, -1.0, 2.0, 0.0, -2.0, 1.0, 0.0, -1.0};
float Gy[9] = {1.0, 2.0, 1.0, 0.0, 0.0, 0.0, -1.0, -2.0, -1.0};
float *device_gx, *device_gy;
gpuErrchk( hipMallocManaged(&device_gx, sizeof(float)*sizeof(Gx)) );
gpuErrchk( hipMallocManaged(&device_gy, sizeof(float)*sizeof(Gy)) );
for (int i=0;i<9;i++) // copy from Gx/Gy to device_gx/device_gy
{
device_gx[i] = Gx[i];
device_gy[i] = Gy[i];
}
// now, induce memory movement to the GPU of the data in unified memory buffers
int deviceID=0; // assume GPU#0, always. OK assumption for this program
hipMemPrefetchAsync((void *)in_data_floats, nvalues*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)out_data_floats, nvalues*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)device_gx, sizeof(Gx)*sizeof(float), deviceID);
hipMemPrefetchAsync((void *)device_gy, sizeof(Gy)*sizeof(float), deviceID);
// set up to run the kernel
int nBlocks=1, nThreadsPerBlock=256;
// ADD CODE HERE: insert your code here to set a different number of thread blocks or # of threads per block
if (ac > 1){
nThreadsPerBlock = atoi(av[1]);
nBlocks = atoi(av[2]);
}
printf(" GPU configuration: %d blocks, %d threads per block \n", nBlocks, nThreadsPerBlock);
// invoke the kernel on the device
sobel_kernel_gpu<<<nBlocks, nThreadsPerBlock>>>(in_data_floats, out_data_floats, nvalues, data_dims[1], data_dims[0], device_gx, device_gy);
// wait for it to finish, check errors
gpuErrchk ( hipDeviceSynchronize() );
// write output after converting from floats in range 0..1 to bytes in range 0..255
unsigned char *out_data_bytes = in_data_bytes; // just reuse the buffer from before
for (off_t i=0; i<nvalues; i++)
out_data_bytes[i] = (unsigned char)(out_data_floats[i] * 255.0);
f = fopen(output_fname,"w");
if (fwrite((void *)out_data_bytes, sizeof(unsigned char), nvalues, f) != nvalues*sizeof(unsigned char))
{
printf("Error writing output file. \n");
fclose(f);
return 1;
}
else
printf(" Wrote the output file %s \n", output_fname);
fclose(f);
}
// eof | .text
.file "sobel_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_ # -- Begin function _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.p2align 4, 0x90
.type _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_,@function
_Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_: # @_Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16sobel_kernel_gpuPfS_iiiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_, .Lfunc_end0-_Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70101010101027 # double 0.0039215686274510003
.LCPI1_1:
.quad 0x406fe00000000000 # double 255
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movl $36598352, %edi # imm = 0x22E7250
callq malloc
movq %rax, %rbx
movl $_ZL11input_fname, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
movl $1, %esi
movl $36598352, %edx # imm = 0x22E7250
movq %rbx, %rdi
movq %rax, %rcx
callq fread
cmpq $36598352, %rax # imm = 0x22E7250
jne .LBB1_1
# %bb.2:
movl $.L.str.2, %edi
movl $_ZL11input_fname, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq fclose
leaq 24(%rsp), %rdi
movl $146393408, %esi # imm = 0x8B9C940
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_10
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit.preheader
movq 24(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_4: # %_Z9gpuAssert10hipError_tPKcib.exit
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
xorps %xmm1, %xmm1
cvtsi2sd %edx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rax,%rcx,4)
incq %rcx
cmpq $36598352, %rcx # imm = 0x22E7250
jne .LBB1_4
# %bb.5:
movq %rsp, %rdi
movl $146393408, %esi # imm = 0x8B9C940
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_12
# %bb.6: # %_Z9gpuAssert10hipError_tPKcib.exit66.preheader
movq (%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_7: # %_Z9gpuAssert10hipError_tPKcib.exit66
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq $36598352, %rcx # imm = 0x22E7250
jne .LBB1_7
# %bb.8:
xorpd %xmm0, %xmm0
movapd %xmm0, 176(%rsp)
movapd %xmm0, 192(%rsp)
movl $1065353216, 176(%rsp) # imm = 0x3F800000
movabsq $4611686021640224768, %rax # imm = 0x40000000BF800000
movq %rax, 184(%rsp)
movabsq $4575657224629649408, %rax # imm = 0x3F800000C0000000
movq %rax, 196(%rsp)
movl $-1082130432, 208(%rsp) # imm = 0xBF800000
movapd %xmm0, 128(%rsp)
movapd %xmm0, 144(%rsp)
movabsq $4611686019492741120, %rax # imm = 0x400000003F800000
movq %rax, 128(%rsp)
movl $1065353216, 136(%rsp) # imm = 0x3F800000
movabsq $-4611686015214551040, %rax # imm = 0xC0000000BF800000
movq %rax, 152(%rsp)
movl $-1082130432, 160(%rsp) # imm = 0xBF800000
leaq 16(%rsp), %rdi
movl $144, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_9
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit68
leaq 8(%rsp), %rdi
movl $144, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_29
# %bb.14: # %_Z9gpuAssert10hipError_tPKcib.exit70.preheader
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_15: # %_Z9gpuAssert10hipError_tPKcib.exit70
# =>This Inner Loop Header: Depth=1
movss 176(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rax,%rdx,4)
movss 128(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq $9, %rdx
jne .LBB1_15
# %bb.16:
movq 24(%rsp), %rdi
movl $146393408, %esi # imm = 0x8B9C940
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq (%rsp), %rdi
movl $146393408, %esi # imm = 0x8B9C940
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 16(%rsp), %rdi
movl $144, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl $144, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
cmpl $1, %ebp
jle .LBB1_17
# %bb.18:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB1_19
.LBB1_1:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r15, %rdi
callq fclose
movl $1, %ebx
jmp .LBB1_28
.LBB1_17:
movl $256, %r15d # imm = 0x100
movl $1, %r14d
.LBB1_19:
movl $.L.str.4, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
movl %r14d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $36598352, 44(%rsp) # imm = 0x22E7250
movl $5146, 40(%rsp) # imm = 0x141A
movl $7112, 36(%rsp) # imm = 0x1BC8
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 112(%rsp), %rax
movq %rax, 232(%rsp)
leaq 44(%rsp), %rax
movq %rax, 240(%rsp)
leaq 40(%rsp), %rax
movq %rax, 248(%rsp)
leaq 36(%rsp), %rax
movq %rax, 256(%rsp)
leaq 104(%rsp), %rax
movq %rax, 264(%rsp)
leaq 96(%rsp), %rax
movq %rax, 272(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z16sobel_kernel_gpuPfS_iiiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_30
# %bb.22: # %_Z9gpuAssert10hipError_tPKcib.exit72.preheader
movq (%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_23: # %_Z9gpuAssert10hipError_tPKcib.exit72
# =>This Inner Loop Header: Depth=1
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %edx
movb %dl, (%rbx,%rcx)
incq %rcx
cmpq $36598352, %rcx # imm = 0x22E7250
jne .LBB1_23
# %bb.24:
movl $output_fname, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %r14
movl $1, %esi
movl $36598352, %edx # imm = 0x22E7250
movq %rbx, %rdi
movq %rax, %rcx
callq fwrite
cmpq $36598352, %rax # imm = 0x22E7250
jne .LBB1_25
# %bb.26:
xorl %ebx, %ebx
movl $.L.str.7, %edi
movl $output_fname, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_27
.LBB1_25:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
.LBB1_27:
movq %r14, %rdi
callq fclose
.LBB1_28:
movl %ebx, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 320
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
jmp .LBB1_11
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $170, %r8d
jmp .LBB1_11
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $178, %r8d
jmp .LBB1_11
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $179, %r8d
jmp .LBB1_11
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $211, %r8d
.LBB1_11:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sobel_kernel_gpuPfS_iiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type output_fname,@object # @output_fname
.data
.globl output_fname
.p2align 4, 0x0
output_fname:
.asciz "../data/processed-raw-int8-4x-cpu.dat"
.size output_fname, 38
.type _Z16sobel_kernel_gpuPfS_iiiS_S_,@object # @_Z16sobel_kernel_gpuPfS_iiiS_S_
.section .rodata,"a",@progbits
.globl _Z16sobel_kernel_gpuPfS_iiiS_S_
.p2align 3, 0x0
_Z16sobel_kernel_gpuPfS_iiiS_S_:
.quad _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.size _Z16sobel_kernel_gpuPfS_iiiS_S_, 8
.type _ZL11input_fname,@object # @_ZL11input_fname
.data
.p2align 4, 0x0
_ZL11input_fname:
.asciz "../data/zebra-gray-int8-4x"
.size _ZL11input_fname, 27
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Read data from the file %s \n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ItsJes/csc_746_hw5/main/sobel_gpu.hip"
.size .L.str.3, 95
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " GPU configuration: %d blocks, %d threads per block \n"
.size .L.str.4, 54
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Wrote the output file %s \n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16sobel_kernel_gpuPfS_iiiS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error writing output file. "
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error reading input file. "
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym output_fname
.addrsig_sym _Z16sobel_kernel_gpuPfS_iiiS_S_
.addrsig_sym _ZL11input_fname
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16sobel_kernel_gpuPfS_iiiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, R2 ; /* 0x00000002000b7202 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x2e0 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000209000 */
/*00c0*/ IMAD.IADD R2, R0.reuse, 0x1, R11 ; /* 0x0000000100027824 */
/* 0x040fe200078e020b */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45070 */
/*00e0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a00 */
/*00f0*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0110*/ IADD3 R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a10 */
/* 0x000fe20007ffe000 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0150*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*0160*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fca00078e00ff */
/*0180*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0190*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fca00078e0205 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*01c0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0220*/ LOP3.LUT P0, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000780c0ff */
/*0230*/ @!P0 BRA 0x2d0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0250*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fc60000000f00 */
/*0260*/ IMAD.WIDE R2, R11, R2, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fc800078e0202 */
/*0270*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0290*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x000fe400078e020b */
/*02a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R2, R0, 0x4, R2 ; /* 0x0000000400027825 */
/* 0x001fd800078e0202 */
/*02c0*/ @P0 BRA 0x270 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fd400000001ff */
/*0300*/ IMAD.WIDE R2, R11, R10, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x001fe200078e020a */
/*0310*/ IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b7210 */
/* 0x000fc80007ffe000 */
/*0320*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0330*/ IMAD.WIDE R4, R0.reuse, 0x4, R2 ; /* 0x0000000400047825 */
/* 0x040fe200078e0202 */
/*0340*/ IADD3 R11, R0, R11, R0 ; /* 0x0000000b000b7210 */
/* 0x000fc80007ffe000 */
/*0350*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101904 */
/*0360*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fe200078e0204 */
/*0370*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fc80003f06270 */
/*0380*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e2000c101904 */
/*0390*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fca00078e0206 */
/*03a0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0001e6000c101904 */
/*03b0*/ @!P0 BRA 0x300 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sobel_kernel_gpuPfS_iiiS_S_
.globl _Z16sobel_kernel_gpuPfS_iiiS_S_
.p2align 8
.type _Z16sobel_kernel_gpuPfS_iiiS_S_,@function
_Z16sobel_kernel_gpuPfS_iiiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_mov_b32 s1, 0
s_lshl_b64 s[4:5], s[2:3], 2
.LBB0_2:
v_add_nc_u32_e32 v1, s2, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sobel_kernel_gpuPfS_iiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sobel_kernel_gpuPfS_iiiS_S_, .Lfunc_end0-_Z16sobel_kernel_gpuPfS_iiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sobel_kernel_gpuPfS_iiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sobel_kernel_gpuPfS_iiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012b23b_00000000-6_sobel_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4149:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4149:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4144:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4144:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z20sobel_filtered_pixelPfiiiiS_S_
.type _Z20sobel_filtered_pixelPfiiiiS_S_, @function
_Z20sobel_filtered_pixelPfiiiiS_S_:
.LFB4145:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4145:
.size _Z20sobel_filtered_pixelPfiiiiS_S_, .-_Z20sobel_filtered_pixelPfiiiiS_S_
.globl _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
.type _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_, @function
_Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_:
.LFB4171:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16sobel_kernel_gpuPfS_iiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4171:
.size _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_, .-_Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
.globl _Z16sobel_kernel_gpuPfS_iiiS_S_
.type _Z16sobel_kernel_gpuPfS_iiiS_S_, @function
_Z16sobel_kernel_gpuPfS_iiiS_S_:
.LFB4172:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4172:
.size _Z16sobel_kernel_gpuPfS_iiiS_S_, .-_Z16sobel_kernel_gpuPfS_iiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "Error reading input file. \n"
.LC3:
.string " Read data from the file %s \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ItsJes/csc_746_hw5/main/sobel_gpu.cu"
.align 8
.LC11:
.string " GPU configuration: %d blocks, %d threads per block \n"
.section .rodata.str1.1
.LC13:
.string "w"
.LC14:
.string "Error writing output file. \n"
.LC15:
.string " Wrote the output file %s \n"
.text
.globl main
.type main, @function
main:
.LFB4146:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $36598352, %edi
call malloc@PLT
movq %rax, %rbx
leaq .LC1(%rip), %rsi
leaq _ZL11input_fname(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rax, %r8
movl $36598352, %ecx
movl $1, %edx
movl $36598352, %esi
movq %rbx, %rdi
call __fread_chk@PLT
cmpq $36598352, %rax
je .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movl $1, %eax
.L21:
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq _ZL11input_fname(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $146393408, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $161, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
movsd .LC5(%rip), %xmm1
.L24:
movzbl (%rbx,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $36598352, %rax
jne .L24
leaq 16(%rsp), %rdi
movl $1, %edx
movl $146393408, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $168, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
movss .LC6(%rip), %xmm0
.L25:
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $146393408, %rax
jne .L25
movss .LC6(%rip), %xmm1
movss %xmm1, 64(%rsp)
movl $0x00000000, 68(%rsp)
movss .LC8(%rip), %xmm0
movss %xmm0, 72(%rsp)
movss .LC9(%rip), %xmm3
movss %xmm3, 76(%rsp)
movl $0x00000000, 80(%rsp)
movss .LC10(%rip), %xmm2
movss %xmm2, 84(%rsp)
movss %xmm1, 88(%rsp)
movl $0x00000000, 92(%rsp)
movss %xmm0, 96(%rsp)
movss %xmm1, 112(%rsp)
movss %xmm3, 116(%rsp)
movss %xmm1, 120(%rsp)
movl $0x00000000, 124(%rsp)
movl $0x00000000, 128(%rsp)
movl $0x00000000, 132(%rsp)
movss %xmm0, 136(%rsp)
movss %xmm2, 140(%rsp)
movss %xmm0, 144(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $144, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $176, %edx
leaq .LC4(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movl $1, %edx
movl $144, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $177, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
.L26:
movss 64(%rsp,%rax), %xmm0
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movss 112(%rsp,%rax), %xmm0
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $36, %rax
jne .L26
movl $0, %ecx
movl $0, %edx
movl $146393408, %esi
movq 8(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $0, %edx
movl $146393408, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $0, %edx
movl $144, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $0, %edx
movl $144, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
cmpl $1, %ebp
jg .L39
movl $256, %r13d
movl $1, %ebp
.L27:
movl %r13d, %ecx
movl %ebp, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L28:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $209, %edx
leaq .LC4(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rcx
movl $0, %eax
movsd .LC12(%rip), %xmm1
.L29:
pxor %xmm0, %xmm0
cvtss2sd (%rcx,%rax,4), %xmm0
mulsd %xmm1, %xmm0
cvttsd2sil %xmm0, %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq $36598352, %rax
jne .L29
leaq .LC13(%rip), %rsi
leaq output_fname(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, %rcx
movl $36598352, %edx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
cmpq $36598352, %rax
je .L30
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movl $1, %eax
jmp .L21
.L39:
movq 8(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L27
.L40:
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq 40(%rsp)
.cfi_def_cfa_offset 224
movq 40(%rsp), %r9
movl $7112, %r8d
movl $5146, %ecx
movl $36598352, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z45__device_stub__Z16sobel_kernel_gpuPfS_iiiS_S_PfS_iiiS_S_
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L28
.L30:
leaq output_fname(%rip), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movl $0, %eax
jmp .L21
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4146:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z16sobel_kernel_gpuPfS_iiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4174:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sobel_kernel_gpuPfS_iiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4174:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl output_fname
.data
.align 32
.type output_fname, @object
.size output_fname, 38
output_fname:
.string "../data/processed-raw-int8-4x-cpu.dat"
.align 16
.type _ZL11input_fname, @object
.size _ZL11input_fname, 27
_ZL11input_fname:
.string "../data/zebra-gray-int8-4x"
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 269488167
.long 1064308752
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.align 4
.LC8:
.long -1082130432
.align 4
.LC9:
.long 1073741824
.align 4
.LC10:
.long -1073741824
.section .rodata.cst8
.align 8
.LC12:
.long 0
.long 1081073664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sobel_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_ # -- Begin function _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.p2align 4, 0x90
.type _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_,@function
_Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_: # @_Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16sobel_kernel_gpuPfS_iiiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_, .Lfunc_end0-_Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70101010101027 # double 0.0039215686274510003
.LCPI1_1:
.quad 0x406fe00000000000 # double 255
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movl $36598352, %edi # imm = 0x22E7250
callq malloc
movq %rax, %rbx
movl $_ZL11input_fname, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
movl $1, %esi
movl $36598352, %edx # imm = 0x22E7250
movq %rbx, %rdi
movq %rax, %rcx
callq fread
cmpq $36598352, %rax # imm = 0x22E7250
jne .LBB1_1
# %bb.2:
movl $.L.str.2, %edi
movl $_ZL11input_fname, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq fclose
leaq 24(%rsp), %rdi
movl $146393408, %esi # imm = 0x8B9C940
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_10
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit.preheader
movq 24(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_4: # %_Z9gpuAssert10hipError_tPKcib.exit
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
xorps %xmm1, %xmm1
cvtsi2sd %edx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rax,%rcx,4)
incq %rcx
cmpq $36598352, %rcx # imm = 0x22E7250
jne .LBB1_4
# %bb.5:
movq %rsp, %rdi
movl $146393408, %esi # imm = 0x8B9C940
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_12
# %bb.6: # %_Z9gpuAssert10hipError_tPKcib.exit66.preheader
movq (%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_7: # %_Z9gpuAssert10hipError_tPKcib.exit66
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq $36598352, %rcx # imm = 0x22E7250
jne .LBB1_7
# %bb.8:
xorpd %xmm0, %xmm0
movapd %xmm0, 176(%rsp)
movapd %xmm0, 192(%rsp)
movl $1065353216, 176(%rsp) # imm = 0x3F800000
movabsq $4611686021640224768, %rax # imm = 0x40000000BF800000
movq %rax, 184(%rsp)
movabsq $4575657224629649408, %rax # imm = 0x3F800000C0000000
movq %rax, 196(%rsp)
movl $-1082130432, 208(%rsp) # imm = 0xBF800000
movapd %xmm0, 128(%rsp)
movapd %xmm0, 144(%rsp)
movabsq $4611686019492741120, %rax # imm = 0x400000003F800000
movq %rax, 128(%rsp)
movl $1065353216, 136(%rsp) # imm = 0x3F800000
movabsq $-4611686015214551040, %rax # imm = 0xC0000000BF800000
movq %rax, 152(%rsp)
movl $-1082130432, 160(%rsp) # imm = 0xBF800000
leaq 16(%rsp), %rdi
movl $144, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_9
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit68
leaq 8(%rsp), %rdi
movl $144, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_29
# %bb.14: # %_Z9gpuAssert10hipError_tPKcib.exit70.preheader
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_15: # %_Z9gpuAssert10hipError_tPKcib.exit70
# =>This Inner Loop Header: Depth=1
movss 176(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rax,%rdx,4)
movss 128(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq $9, %rdx
jne .LBB1_15
# %bb.16:
movq 24(%rsp), %rdi
movl $146393408, %esi # imm = 0x8B9C940
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq (%rsp), %rdi
movl $146393408, %esi # imm = 0x8B9C940
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 16(%rsp), %rdi
movl $144, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl $144, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
cmpl $1, %ebp
jle .LBB1_17
# %bb.18:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB1_19
.LBB1_1:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r15, %rdi
callq fclose
movl $1, %ebx
jmp .LBB1_28
.LBB1_17:
movl $256, %r15d # imm = 0x100
movl $1, %r14d
.LBB1_19:
movl $.L.str.4, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
movl %r14d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $36598352, 44(%rsp) # imm = 0x22E7250
movl $5146, 40(%rsp) # imm = 0x141A
movl $7112, 36(%rsp) # imm = 0x1BC8
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 112(%rsp), %rax
movq %rax, 232(%rsp)
leaq 44(%rsp), %rax
movq %rax, 240(%rsp)
leaq 40(%rsp), %rax
movq %rax, 248(%rsp)
leaq 36(%rsp), %rax
movq %rax, 256(%rsp)
leaq 104(%rsp), %rax
movq %rax, 264(%rsp)
leaq 96(%rsp), %rax
movq %rax, 272(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z16sobel_kernel_gpuPfS_iiiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_30
# %bb.22: # %_Z9gpuAssert10hipError_tPKcib.exit72.preheader
movq (%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_23: # %_Z9gpuAssert10hipError_tPKcib.exit72
# =>This Inner Loop Header: Depth=1
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %edx
movb %dl, (%rbx,%rcx)
incq %rcx
cmpq $36598352, %rcx # imm = 0x22E7250
jne .LBB1_23
# %bb.24:
movl $output_fname, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %r14
movl $1, %esi
movl $36598352, %edx # imm = 0x22E7250
movq %rbx, %rdi
movq %rax, %rcx
callq fwrite
cmpq $36598352, %rax # imm = 0x22E7250
jne .LBB1_25
# %bb.26:
xorl %ebx, %ebx
movl $.L.str.7, %edi
movl $output_fname, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_27
.LBB1_25:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
.LBB1_27:
movq %r14, %rdi
callq fclose
.LBB1_28:
movl %ebx, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 320
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
jmp .LBB1_11
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $170, %r8d
jmp .LBB1_11
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $178, %r8d
jmp .LBB1_11
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $179, %r8d
jmp .LBB1_11
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $211, %r8d
.LBB1_11:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sobel_kernel_gpuPfS_iiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type output_fname,@object # @output_fname
.data
.globl output_fname
.p2align 4, 0x0
output_fname:
.asciz "../data/processed-raw-int8-4x-cpu.dat"
.size output_fname, 38
.type _Z16sobel_kernel_gpuPfS_iiiS_S_,@object # @_Z16sobel_kernel_gpuPfS_iiiS_S_
.section .rodata,"a",@progbits
.globl _Z16sobel_kernel_gpuPfS_iiiS_S_
.p2align 3, 0x0
_Z16sobel_kernel_gpuPfS_iiiS_S_:
.quad _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.size _Z16sobel_kernel_gpuPfS_iiiS_S_, 8
.type _ZL11input_fname,@object # @_ZL11input_fname
.data
.p2align 4, 0x0
_ZL11input_fname:
.asciz "../data/zebra-gray-int8-4x"
.size _ZL11input_fname, 27
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Read data from the file %s \n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ItsJes/csc_746_hw5/main/sobel_gpu.hip"
.size .L.str.3, 95
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " GPU configuration: %d blocks, %d threads per block \n"
.size .L.str.4, 54
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Wrote the output file %s \n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16sobel_kernel_gpuPfS_iiiS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error writing output file. "
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error reading input file. "
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sobel_kernel_gpuPfS_iiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym output_fname
.addrsig_sym _Z16sobel_kernel_gpuPfS_iiiS_S_
.addrsig_sym _ZL11input_fname
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "vectorAdd.cuh"
// ---------------------------------------------------------------------------
// C = A + B
// ---------------------------------------------------------------------------
__global__ void vectorAdd(
const float* A,
const float* B,
float* const C,
int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
C[i] = A[i] + B[i];
} | code for sm_80
Function : _Z9vectorAddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "vectorAdd.cuh"
// ---------------------------------------------------------------------------
// C = A + B
// ---------------------------------------------------------------------------
__global__ void vectorAdd(
const float* A,
const float* B,
float* const C,
int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
C[i] = A[i] + B[i];
} | .file "tmpxft_00089fdb_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.type _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, @function
_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, .-_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.globl _Z9vectorAddPKfS0_Pfi
.type _Z9vectorAddPKfS0_Pfi, @function
_Z9vectorAddPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vectorAddPKfS0_Pfi, .-_Z9vectorAddPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "vectorAdd.cuh"
// ---------------------------------------------------------------------------
// C = A + B
// ---------------------------------------------------------------------------
__global__ void vectorAdd(
const float* A,
const float* B,
float* const C,
int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
C[i] = A[i] + B[i];
} | #ifndef VECTOR_ADD_H
#define VECTOR_ADD_H
__global__ void vectorAdd(
const float* A,
const float* B,
float* const C,
int numElements);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef VECTOR_ADD_H
#define VECTOR_ADD_H
__global__ void vectorAdd(
const float* A,
const float* B,
float* const C,
int numElements);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef VECTOR_ADD_H
#define VECTOR_ADD_H
__global__ void vectorAdd(
const float* A,
const float* B,
float* const C,
int numElements);
#endif | .text
.file "vectorAdd.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectorAddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00089fdb_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.type _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, @function
_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, .-_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.globl _Z9vectorAddPKfS0_Pfi
.type _Z9vectorAddPKfS0_Pfi, @function
_Z9vectorAddPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vectorAddPKfS0_Pfi, .-_Z9vectorAddPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; Version 2 of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************
* Compile with:
* Windows:
system('"c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat"')
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin')
Window 64 bit:
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin" -I"c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\include" ')
Linux:
* File sudo vi /usr/local/cuda/bin/nvcc.profile
* needs the flag -fPIC in the include line
system('nvcc -c cudaArith.cu -v -I/usr/local/cuda/include/')
*/
// To suppress the unused variable argument for ARM targets
#pragma diag_suppress 177
#ifndef NAN // should be part of math.h
#define NAN (0.0/0.0)
#endif
#define ACCU_ARRTYPE double // Type of the tempory arrays for reduce operations
#define IMUL(a, b) __mul24(a, b)
//#define BLOCKSIZE 512
//#define BLOCKSIZE 512
// below is blocksize for temporary array for reduce operations. Has to be a power of 2 in size
#ifndef CUIMAGE_REDUCE_THREADS // this can be defined at compile time via the flag NVCCFLAG='-D CUIMAGE_REDUCE_THREADS=512'
#define CUIMAGE_REDUCE_THREADS 512
#endif
// (prop.maxThreadsPerBlock)
// #define CUIMAGE_REDUCE_THREADS 512
// #define CUIMAGE_REDUCE_THREADS 128
//#define CUIMAGE_REDUCE_BLOCKS 64
#define NBLOCKS(N,blockSize) (N/blockSize+(N%blockSize==0?0:1))
#define NBLOCKSL(N,blockSize) 1
// min((N/blockSize+(N%blockSize==0?0:1)),prop.maxGridSize[0])
__global__ void rotate(float*a,float b, float * c, size_t sx,size_t sy,size_t sz, size_t dx, size_t dy, size_t dz, size_t ux, size_t uy, size_t uz)
{
// id of this processor
size_t id=((blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x);
size_t Processes=blockDim.x * gridDim.x;
size_t chains=ux*uy*uz; // total number of independent chains
size_t N=sx*sy*sz; // total size of array, has to be chains*length_of_chain
size_t length=N/chains; // chain length
size_t steps=N/Processes; // this is how many steps each processor has to do
size_t step,nl,nx,ny,nz,x,y,z,i,idd;
float swp, nswp;
//if (id != 0) return;
//for (id=0;id<Processes;id++)
{
step=steps*id; // my starting step as the id times the number of steps
nl=step%length; // current position in chain length
nx=(step/length)%ux; // current position in unit cell x
ny=(step/(length*ux))%uy; // current position in unit cell y
nz=(step/(length*ux*uy))%uz; // current position in unit cell z
i=0;
//if (step/steps != 4 && step/steps != 5) return;
while(nz<uz)
{
while(ny<uy)
{
while (nx<ux)
{
x=(nx+nl*dx)%sx; // advance by the offset steps along the chain
y=(ny+nl*dy)%sy;
z=(nz+nl*dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps) {
swp=a[idd];
// a[idd]=a[idd]+0.1;
__syncthreads();
}
while (nl<length-1)
{
if (i > steps-1)
goto nextProcessor; // return;
if (step >= N) // this thread has reached the end of the total data to process
goto nextProcessor; // return;
step++;
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps-1) {
nswp=a[idd];
__syncthreads();
//a[idd]=a[idd]+0.1;
}
c[idd]=swp+0.1; // c[idd]+ny+0.1; // c[idd]+i; // swp+0.1; // c[idd]+(step/steps);
i++; // counts number of writes
if (i > steps-1)
goto nextProcessor; // return;
nl++;
if (i < steps) {
swp=nswp;
}
}
nx++; nl=0;
//if (nx < ux) {
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
c[idd]=swp+0.1; // no need to save this value as this is the end of the line
//}
i++;
if (i > steps-1)
goto nextProcessor; // return;
// if (nx <ux) x=(x+1)%sx;
}
ny++;
// if (ny <uy) y=(y+1)%sy;
nx=0;x=0;
}
nz++;
// if (nz <uz) z=(z+1)%sz;
ny=0;y=0;
}
nextProcessor:
nz=0;
}
return;
} | .file "tmpxft_00180cf5_00000000-6_rotate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
.type _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm, @function
_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movss %xmm0, 52(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6rotatePffS_mmmmmmmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm, .-_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
.globl _Z6rotatePffS_mmmmmmmmm
.type _Z6rotatePffS_mmmmmmmmm, @function
_Z6rotatePffS_mmmmmmmmm:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6rotatePffS_mmmmmmmmm, .-_Z6rotatePffS_mmmmmmmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6rotatePffS_mmmmmmmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rotatePffS_mmmmmmmmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; Version 2 of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************
* Compile with:
* Windows:
system('"c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat"')
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin')
Window 64 bit:
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin" -I"c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\include" ')
Linux:
* File sudo vi /usr/local/cuda/bin/nvcc.profile
* needs the flag -fPIC in the include line
system('nvcc -c cudaArith.cu -v -I/usr/local/cuda/include/')
*/
// To suppress the unused variable argument for ARM targets
#pragma diag_suppress 177
#ifndef NAN // should be part of math.h
#define NAN (0.0/0.0)
#endif
#define ACCU_ARRTYPE double // Type of the tempory arrays for reduce operations
#define IMUL(a, b) __mul24(a, b)
//#define BLOCKSIZE 512
//#define BLOCKSIZE 512
// below is blocksize for temporary array for reduce operations. Has to be a power of 2 in size
#ifndef CUIMAGE_REDUCE_THREADS // this can be defined at compile time via the flag NVCCFLAG='-D CUIMAGE_REDUCE_THREADS=512'
#define CUIMAGE_REDUCE_THREADS 512
#endif
// (prop.maxThreadsPerBlock)
// #define CUIMAGE_REDUCE_THREADS 512
// #define CUIMAGE_REDUCE_THREADS 128
//#define CUIMAGE_REDUCE_BLOCKS 64
#define NBLOCKS(N,blockSize) (N/blockSize+(N%blockSize==0?0:1))
#define NBLOCKSL(N,blockSize) 1
// min((N/blockSize+(N%blockSize==0?0:1)),prop.maxGridSize[0])
__global__ void rotate(float*a,float b, float * c, size_t sx,size_t sy,size_t sz, size_t dx, size_t dy, size_t dz, size_t ux, size_t uy, size_t uz)
{
// id of this processor
size_t id=((blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x);
size_t Processes=blockDim.x * gridDim.x;
size_t chains=ux*uy*uz; // total number of independent chains
size_t N=sx*sy*sz; // total size of array, has to be chains*length_of_chain
size_t length=N/chains; // chain length
size_t steps=N/Processes; // this is how many steps each processor has to do
size_t step,nl,nx,ny,nz,x,y,z,i,idd;
float swp, nswp;
//if (id != 0) return;
//for (id=0;id<Processes;id++)
{
step=steps*id; // my starting step as the id times the number of steps
nl=step%length; // current position in chain length
nx=(step/length)%ux; // current position in unit cell x
ny=(step/(length*ux))%uy; // current position in unit cell y
nz=(step/(length*ux*uy))%uz; // current position in unit cell z
i=0;
//if (step/steps != 4 && step/steps != 5) return;
while(nz<uz)
{
while(ny<uy)
{
while (nx<ux)
{
x=(nx+nl*dx)%sx; // advance by the offset steps along the chain
y=(ny+nl*dy)%sy;
z=(nz+nl*dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps) {
swp=a[idd];
// a[idd]=a[idd]+0.1;
__syncthreads();
}
while (nl<length-1)
{
if (i > steps-1)
goto nextProcessor; // return;
if (step >= N) // this thread has reached the end of the total data to process
goto nextProcessor; // return;
step++;
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps-1) {
nswp=a[idd];
__syncthreads();
//a[idd]=a[idd]+0.1;
}
c[idd]=swp+0.1; // c[idd]+ny+0.1; // c[idd]+i; // swp+0.1; // c[idd]+(step/steps);
i++; // counts number of writes
if (i > steps-1)
goto nextProcessor; // return;
nl++;
if (i < steps) {
swp=nswp;
}
}
nx++; nl=0;
//if (nx < ux) {
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
c[idd]=swp+0.1; // no need to save this value as this is the end of the line
//}
i++;
if (i > steps-1)
goto nextProcessor; // return;
// if (nx <ux) x=(x+1)%sx;
}
ny++;
// if (ny <uy) y=(y+1)%sy;
nx=0;x=0;
}
nz++;
// if (nz <uz) z=(z+1)%sz;
ny=0;y=0;
}
nextProcessor:
nz=0;
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; Version 2 of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************
* Compile with:
* Windows:
system('"c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat"')
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin')
Window 64 bit:
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin" -I"c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\include" ')
Linux:
* File sudo vi /usr/local/cuda/bin/nvcc.profile
* needs the flag -fPIC in the include line
system('nvcc -c cudaArith.cu -v -I/usr/local/cuda/include/')
*/
// To suppress the unused variable argument for ARM targets
#pragma diag_suppress 177
#ifndef NAN // should be part of math.h
#define NAN (0.0/0.0)
#endif
#define ACCU_ARRTYPE double // Type of the tempory arrays for reduce operations
#define IMUL(a, b) __mul24(a, b)
//#define BLOCKSIZE 512
//#define BLOCKSIZE 512
// below is blocksize for temporary array for reduce operations. Has to be a power of 2 in size
#ifndef CUIMAGE_REDUCE_THREADS // this can be defined at compile time via the flag NVCCFLAG='-D CUIMAGE_REDUCE_THREADS=512'
#define CUIMAGE_REDUCE_THREADS 512
#endif
// (prop.maxThreadsPerBlock)
// #define CUIMAGE_REDUCE_THREADS 512
// #define CUIMAGE_REDUCE_THREADS 128
//#define CUIMAGE_REDUCE_BLOCKS 64
#define NBLOCKS(N,blockSize) (N/blockSize+(N%blockSize==0?0:1))
#define NBLOCKSL(N,blockSize) 1
// min((N/blockSize+(N%blockSize==0?0:1)),prop.maxGridSize[0])
__global__ void rotate(float*a,float b, float * c, size_t sx,size_t sy,size_t sz, size_t dx, size_t dy, size_t dz, size_t ux, size_t uy, size_t uz)
{
// id of this processor
size_t id=((blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x);
size_t Processes=blockDim.x * gridDim.x;
size_t chains=ux*uy*uz; // total number of independent chains
size_t N=sx*sy*sz; // total size of array, has to be chains*length_of_chain
size_t length=N/chains; // chain length
size_t steps=N/Processes; // this is how many steps each processor has to do
size_t step,nl,nx,ny,nz,x,y,z,i,idd;
float swp, nswp;
//if (id != 0) return;
//for (id=0;id<Processes;id++)
{
step=steps*id; // my starting step as the id times the number of steps
nl=step%length; // current position in chain length
nx=(step/length)%ux; // current position in unit cell x
ny=(step/(length*ux))%uy; // current position in unit cell y
nz=(step/(length*ux*uy))%uz; // current position in unit cell z
i=0;
//if (step/steps != 4 && step/steps != 5) return;
while(nz<uz)
{
while(ny<uy)
{
while (nx<ux)
{
x=(nx+nl*dx)%sx; // advance by the offset steps along the chain
y=(ny+nl*dy)%sy;
z=(nz+nl*dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps) {
swp=a[idd];
// a[idd]=a[idd]+0.1;
__syncthreads();
}
while (nl<length-1)
{
if (i > steps-1)
goto nextProcessor; // return;
if (step >= N) // this thread has reached the end of the total data to process
goto nextProcessor; // return;
step++;
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps-1) {
nswp=a[idd];
__syncthreads();
//a[idd]=a[idd]+0.1;
}
c[idd]=swp+0.1; // c[idd]+ny+0.1; // c[idd]+i; // swp+0.1; // c[idd]+(step/steps);
i++; // counts number of writes
if (i > steps-1)
goto nextProcessor; // return;
nl++;
if (i < steps) {
swp=nswp;
}
}
nx++; nl=0;
//if (nx < ux) {
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
c[idd]=swp+0.1; // no need to save this value as this is the end of the line
//}
i++;
if (i > steps-1)
goto nextProcessor; // return;
// if (nx <ux) x=(x+1)%sx;
}
ny++;
// if (ny <uy) y=(y+1)%sy;
nx=0;x=0;
}
nz++;
// if (nz <uz) z=(z+1)%sz;
ny=0;y=0;
}
nextProcessor:
nz=0;
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; Version 2 of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************
* Compile with:
* Windows:
system('"c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat"')
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin')
Window 64 bit:
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin" -I"c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\include" ')
Linux:
* File sudo vi /usr/local/cuda/bin/nvcc.profile
* needs the flag -fPIC in the include line
system('nvcc -c cudaArith.cu -v -I/usr/local/cuda/include/')
*/
// To suppress the unused variable argument for ARM targets
#pragma diag_suppress 177
#ifndef NAN // should be part of math.h
#define NAN (0.0/0.0)
#endif
#define ACCU_ARRTYPE double // Type of the tempory arrays for reduce operations
#define IMUL(a, b) __mul24(a, b)
//#define BLOCKSIZE 512
//#define BLOCKSIZE 512
// below is blocksize for temporary array for reduce operations. Has to be a power of 2 in size
#ifndef CUIMAGE_REDUCE_THREADS // this can be defined at compile time via the flag NVCCFLAG='-D CUIMAGE_REDUCE_THREADS=512'
#define CUIMAGE_REDUCE_THREADS 512
#endif
// (prop.maxThreadsPerBlock)
// #define CUIMAGE_REDUCE_THREADS 512
// #define CUIMAGE_REDUCE_THREADS 128
//#define CUIMAGE_REDUCE_BLOCKS 64
#define NBLOCKS(N,blockSize) (N/blockSize+(N%blockSize==0?0:1))
#define NBLOCKSL(N,blockSize) 1
// min((N/blockSize+(N%blockSize==0?0:1)),prop.maxGridSize[0])
__global__ void rotate(float*a,float b, float * c, size_t sx,size_t sy,size_t sz, size_t dx, size_t dy, size_t dz, size_t ux, size_t uy, size_t uz)
{
// id of this processor
size_t id=((blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x);
size_t Processes=blockDim.x * gridDim.x;
size_t chains=ux*uy*uz; // total number of independent chains
size_t N=sx*sy*sz; // total size of array, has to be chains*length_of_chain
size_t length=N/chains; // chain length
size_t steps=N/Processes; // this is how many steps each processor has to do
size_t step,nl,nx,ny,nz,x,y,z,i,idd;
float swp, nswp;
//if (id != 0) return;
//for (id=0;id<Processes;id++)
{
step=steps*id; // my starting step as the id times the number of steps
nl=step%length; // current position in chain length
nx=(step/length)%ux; // current position in unit cell x
ny=(step/(length*ux))%uy; // current position in unit cell y
nz=(step/(length*ux*uy))%uz; // current position in unit cell z
i=0;
//if (step/steps != 4 && step/steps != 5) return;
while(nz<uz)
{
while(ny<uy)
{
while (nx<ux)
{
x=(nx+nl*dx)%sx; // advance by the offset steps along the chain
y=(ny+nl*dy)%sy;
z=(nz+nl*dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps) {
swp=a[idd];
// a[idd]=a[idd]+0.1;
__syncthreads();
}
while (nl<length-1)
{
if (i > steps-1)
goto nextProcessor; // return;
if (step >= N) // this thread has reached the end of the total data to process
goto nextProcessor; // return;
step++;
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps-1) {
nswp=a[idd];
__syncthreads();
//a[idd]=a[idd]+0.1;
}
c[idd]=swp+0.1; // c[idd]+ny+0.1; // c[idd]+i; // swp+0.1; // c[idd]+(step/steps);
i++; // counts number of writes
if (i > steps-1)
goto nextProcessor; // return;
nl++;
if (i < steps) {
swp=nswp;
}
}
nx++; nl=0;
//if (nx < ux) {
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
c[idd]=swp+0.1; // no need to save this value as this is the end of the line
//}
i++;
if (i > steps-1)
goto nextProcessor; // return;
// if (nx <ux) x=(x+1)%sx;
}
ny++;
// if (ny <uy) y=(y+1)%sy;
nx=0;x=0;
}
nz++;
// if (nz <uz) z=(z+1)%sz;
ny=0;y=0;
}
nextProcessor:
nz=0;
}
return;
} | .text
.file "rotate.hip"
.globl _Z21__device_stub__rotatePffS_mmmmmmmmm # -- Begin function _Z21__device_stub__rotatePffS_mmmmmmmmm
.p2align 4, 0x90
.type _Z21__device_stub__rotatePffS_mmmmmmmmm,@function
_Z21__device_stub__rotatePffS_mmmmmmmmm: # @_Z21__device_stub__rotatePffS_mmmmmmmmm
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 224(%rsp), %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6rotatePffS_mmmmmmmmm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z21__device_stub__rotatePffS_mmmmmmmmm, .Lfunc_end0-_Z21__device_stub__rotatePffS_mmmmmmmmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rotatePffS_mmmmmmmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6rotatePffS_mmmmmmmmm,@object # @_Z6rotatePffS_mmmmmmmmm
.section .rodata,"a",@progbits
.globl _Z6rotatePffS_mmmmmmmmm
.p2align 3, 0x0
_Z6rotatePffS_mmmmmmmmm:
.quad _Z21__device_stub__rotatePffS_mmmmmmmmm
.size _Z6rotatePffS_mmmmmmmmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6rotatePffS_mmmmmmmmm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__rotatePffS_mmmmmmmmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6rotatePffS_mmmmmmmmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00180cf5_00000000-6_rotate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
.type _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm, @function
_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movss %xmm0, 52(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6rotatePffS_mmmmmmmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm, .-_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
.globl _Z6rotatePffS_mmmmmmmmm
.type _Z6rotatePffS_mmmmmmmmm, @function
_Z6rotatePffS_mmmmmmmmm:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6rotatePffS_mmmmmmmmm, .-_Z6rotatePffS_mmmmmmmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6rotatePffS_mmmmmmmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rotatePffS_mmmmmmmmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rotate.hip"
.globl _Z21__device_stub__rotatePffS_mmmmmmmmm # -- Begin function _Z21__device_stub__rotatePffS_mmmmmmmmm
.p2align 4, 0x90
.type _Z21__device_stub__rotatePffS_mmmmmmmmm,@function
_Z21__device_stub__rotatePffS_mmmmmmmmm: # @_Z21__device_stub__rotatePffS_mmmmmmmmm
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 224(%rsp), %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6rotatePffS_mmmmmmmmm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z21__device_stub__rotatePffS_mmmmmmmmm, .Lfunc_end0-_Z21__device_stub__rotatePffS_mmmmmmmmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rotatePffS_mmmmmmmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6rotatePffS_mmmmmmmmm,@object # @_Z6rotatePffS_mmmmmmmmm
.section .rodata,"a",@progbits
.globl _Z6rotatePffS_mmmmmmmmm
.p2align 3, 0x0
_Z6rotatePffS_mmmmmmmmm:
.quad _Z21__device_stub__rotatePffS_mmmmmmmmm
.size _Z6rotatePffS_mmmmmmmmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6rotatePffS_mmmmmmmmm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__rotatePffS_mmmmmmmmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6rotatePffS_mmmmmmmmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double outjc0ic0;
double outjp1ic0;
double outjp2ic0;
double outjp3ic0;
outjc0ic0 = 3.18622 * in[j][i];
outjc0ic0 += 3.18622 * in[j][i+8];
outjc0ic0 += 3.18622 * in[j+8][i];
outjc0ic0 += 3.18622 * in[j+8][i+8];
outjc0ic0 += 4.5339 * in[j][i+1];
outjc0ic0 += 4.5339 * in[j][i+7];
outjc0ic0 += 4.5339 * in[j+1][i];
outjc0ic0 += 4.5339 * in[j+1][i+8];
outjc0ic0 += 4.5339 * in[j+7][i];
outjc0ic0 += 4.5339 * in[j+7][i+8];
outjc0ic0 += 4.5339 * in[j+8][i+1];
outjc0ic0 += 4.5339 * in[j+8][i+7];
outjc0ic0 += -0.000357 * in[j][i+2];
outjc0ic0 += -0.000357 * in[j][i+6];
outjc0ic0 += -0.000357 * in[j+2][i];
outjc0ic0 += -0.000357 * in[j+2][i+8];
outjc0ic0 += -0.000357 * in[j+6][i];
outjc0ic0 += -0.000357 * in[j+6][i+8];
outjc0ic0 += -0.000357 * in[j+8][i+2];
outjc0ic0 += -0.000357 * in[j+8][i+6];
outjc0ic0 += 0.002856 * in[j][i+3];
outjc0ic0 += 0.002856 * in[j][i+5];
outjc0ic0 += 0.002856 * in[j+3][i];
outjc0ic0 += 0.002856 * in[j+3][i+8];
outjc0ic0 += 0.002856 * in[j+5][i];
outjc0ic0 += 0.002856 * in[j+5][i+8];
outjc0ic0 += 0.002856 * in[j+8][i+3];
outjc0ic0 += 0.002856 * in[j+8][i+5];
outjc0ic0 += -0.00508225 * in[j][i+4];
outjc0ic0 += -0.00508225 * in[j+4][i+8];
outjc0ic0 += -0.00508225 * in[j+4][i];
outjc0ic0 += -0.00508225 * in[j+8][i+4];
outjc0ic0 += 0.00064516 * in[j+1][i+1];
outjc0ic0 += 0.00064516 * in[j+1][i+7];
outjc0ic0 += 0.00064516 * in[j+7][i+1];
outjc0ic0 += 0.00064516 * in[j+7][i+7];
outjc0ic0 += -0.00508 * in[j+1][i+2];
outjc0ic0 += -0.00508 * in[j+1][i+6];
outjc0ic0 += -0.00508 * in[j+2][i+1];
outjc0ic0 += -0.00508 * in[j+2][i+7];
outjc0ic0 += -0.00508 * in[j+6][i+1];
outjc0ic0 += -0.00508 * in[j+6][i+7];
outjc0ic0 += -0.00508 * in[j+7][i+2];
outjc0ic0 += -0.00508 * in[j+7][i+6];
outjc0ic0 += 0.04064 * in[j+1][i+3];
outjc0ic0 += 0.04064 * in[j+1][i+5];
outjc0ic0 += 0.04064 * in[j+3][i+1];
outjc0ic0 += 0.04064 * in[j+3][i+7];
outjc0ic0 += 0.04064 * in[j+5][i+1];
outjc0ic0 += 0.04064 * in[j+5][i+7];
outjc0ic0 += 0.04064 * in[j+7][i+3];
outjc0ic0 += 0.04064 * in[j+7][i+5];
outjc0ic0 += -0.0723189 * in[j+1][i+4];
outjc0ic0 += -0.0723189 * in[j+4][i+1];
outjc0ic0 += -0.0723189 * in[j+4][i+7];
outjc0ic0 += -0.0723189 * in[j+7][i+4];
outjc0ic0 += 0.04 * in[j+2][i+2];
outjc0ic0 += 0.04 * in[j+2][i+6];
outjc0ic0 += 0.04 * in[j+6][i+2];
outjc0ic0 += 0.04 * in[j+6][i+6];
outjc0ic0 += -0.32 * in[j+2][i+3];
outjc0ic0 += -0.32 * in[j+2][i+5];
outjc0ic0 += -0.32 * in[j+3][i+2];
outjc0ic0 += -0.32 * in[j+3][i+6];
outjc0ic0 += -0.32 * in[j+5][i+2];
outjc0ic0 += -0.32 * in[j+5][i+6];
outjc0ic0 += -0.32 * in[j+6][i+3];
outjc0ic0 += -0.32 * in[j+6][i+5];
outjc0ic0 += 0.56944 * in[j+2][i+4];
outjc0ic0 += 0.56944 * in[j+4][i+2];
outjc0ic0 += 0.56944 * in[j+4][i+6];
outjc0ic0 += 0.56944 * in[j+6][i+4];
outjc0ic0 += 2.56 * in[j+3][i+3];
outjc0ic0 += 2.56 * in[j+3][i+5];
outjc0ic0 += 2.56 * in[j+5][i+3];
outjc0ic0 += 2.56 * in[j+5][i+5];
outjc0ic0 += -4.55552 * in[j+3][i+4];
outjc0ic0 += -4.55552 * in[j+4][i+3];
outjc0ic0 += -4.55552 * in[j+4][i+5];
outjc0ic0 += -4.55552 * in[j+5][i+4];
outjc0ic0 += in[j+4][i+4] * 8.10655;
out[j][i] = outjc0ic0;
outjp1ic0 = 3.18622 * in[j+1][i];
outjp1ic0 += 3.18622 * in[j+1][i+8];
outjp1ic0 += 3.18622 * in[j+9][i];
outjp1ic0 += 3.18622 * in[j+9][i+8];
outjp1ic0 += 4.5339 * in[j+1][i+1];
outjp1ic0 += 4.5339 * in[j+1][i+7];
outjp1ic0 += 4.5339 * in[j+2][i];
outjp1ic0 += 4.5339 * in[j+2][i+8];
outjp1ic0 += 4.5339 * in[j+8][i];
outjp1ic0 += 4.5339 * in[j+8][i+8];
outjp1ic0 += 4.5339 * in[j+9][i+1];
outjp1ic0 += 4.5339 * in[j+9][i+7];
outjp1ic0 += -0.000357 * in[j+1][i+2];
outjp1ic0 += -0.000357 * in[j+1][i+6];
outjp1ic0 += -0.000357 * in[j+3][i];
outjp1ic0 += -0.000357 * in[j+3][i+8];
outjp1ic0 += -0.000357 * in[j+7][i];
outjp1ic0 += -0.000357 * in[j+7][i+8];
outjp1ic0 += -0.000357 * in[j+9][i+2];
outjp1ic0 += -0.000357 * in[j+9][i+6];
outjp1ic0 += 0.002856 * in[j+1][i+3];
outjp1ic0 += 0.002856 * in[j+1][i+5];
outjp1ic0 += 0.002856 * in[j+4][i];
outjp1ic0 += 0.002856 * in[j+4][i+8];
outjp1ic0 += 0.002856 * in[j+6][i];
outjp1ic0 += 0.002856 * in[j+6][i+8];
outjp1ic0 += 0.002856 * in[j+9][i+3];
outjp1ic0 += 0.002856 * in[j+9][i+5];
outjp1ic0 += -0.00508225 * in[j+1][i+4];
outjp1ic0 += -0.00508225 * in[j+5][i+8];
outjp1ic0 += -0.00508225 * in[j+5][i];
outjp1ic0 += -0.00508225 * in[j+9][i+4];
outjp1ic0 += 0.00064516 * in[j+2][i+1];
outjp1ic0 += 0.00064516 * in[j+2][i+7];
outjp1ic0 += 0.00064516 * in[j+8][i+1];
outjp1ic0 += 0.00064516 * in[j+8][i+7];
outjp1ic0 += -0.00508 * in[j+2][i+2];
outjp1ic0 += -0.00508 * in[j+2][i+6];
outjp1ic0 += -0.00508 * in[j+3][i+1];
outjp1ic0 += -0.00508 * in[j+3][i+7];
outjp1ic0 += -0.00508 * in[j+7][i+1];
outjp1ic0 += -0.00508 * in[j+7][i+7];
outjp1ic0 += -0.00508 * in[j+8][i+2];
outjp1ic0 += -0.00508 * in[j+8][i+6];
outjp1ic0 += 0.04064 * in[j+2][i+3];
outjp1ic0 += 0.04064 * in[j+2][i+5];
outjp1ic0 += 0.04064 * in[j+4][i+1];
outjp1ic0 += 0.04064 * in[j+4][i+7];
outjp1ic0 += 0.04064 * in[j+6][i+1];
outjp1ic0 += 0.04064 * in[j+6][i+7];
outjp1ic0 += 0.04064 * in[j+8][i+3];
outjp1ic0 += 0.04064 * in[j+8][i+5];
outjp1ic0 += -0.0723189 * in[j+2][i+4];
outjp1ic0 += -0.0723189 * in[j+5][i+1];
outjp1ic0 += -0.0723189 * in[j+5][i+7];
outjp1ic0 += -0.0723189 * in[j+8][i+4];
outjp1ic0 += 0.04 * in[j+3][i+2];
outjp1ic0 += 0.04 * in[j+3][i+6];
outjp1ic0 += 0.04 * in[j+7][i+2];
outjp1ic0 += 0.04 * in[j+7][i+6];
outjp1ic0 += -0.32 * in[j+3][i+3];
outjp1ic0 += -0.32 * in[j+3][i+5];
outjp1ic0 += -0.32 * in[j+4][i+2];
outjp1ic0 += -0.32 * in[j+4][i+6];
outjp1ic0 += -0.32 * in[j+6][i+2];
outjp1ic0 += -0.32 * in[j+6][i+6];
outjp1ic0 += -0.32 * in[j+7][i+3];
outjp1ic0 += -0.32 * in[j+7][i+5];
outjp1ic0 += 0.56944 * in[j+3][i+4];
outjp1ic0 += 0.56944 * in[j+5][i+2];
outjp1ic0 += 0.56944 * in[j+5][i+6];
outjp1ic0 += 0.56944 * in[j+7][i+4];
outjp1ic0 += 2.56 * in[j+4][i+3];
outjp1ic0 += 2.56 * in[j+4][i+5];
outjp1ic0 += 2.56 * in[j+6][i+3];
outjp1ic0 += 2.56 * in[j+6][i+5];
outjp1ic0 += -4.55552 * in[j+4][i+4];
outjp1ic0 += -4.55552 * in[j+5][i+3];
outjp1ic0 += -4.55552 * in[j+5][i+5];
outjp1ic0 += -4.55552 * in[j+6][i+4];
outjp1ic0 += in[j+5][i+4] * 8.10655;
out[j+1][i] = outjp1ic0;
outjp2ic0 = 3.18622 * in[j+2][i];
outjp2ic0 += 3.18622 * in[j+2][i+8];
outjp2ic0 += 3.18622 * in[j+10][i];
outjp2ic0 += 3.18622 * in[j+10][i+8];
outjp2ic0 += 4.5339 * in[j+2][i+1];
outjp2ic0 += 4.5339 * in[j+2][i+7];
outjp2ic0 += 4.5339 * in[j+3][i];
outjp2ic0 += 4.5339 * in[j+3][i+8];
outjp2ic0 += 4.5339 * in[j+9][i];
outjp2ic0 += 4.5339 * in[j+9][i+8];
outjp2ic0 += 4.5339 * in[j+10][i+1];
outjp2ic0 += 4.5339 * in[j+10][i+7];
outjp2ic0 += -0.000357 * in[j+2][i+2];
outjp2ic0 += -0.000357 * in[j+2][i+6];
outjp2ic0 += -0.000357 * in[j+4][i];
outjp2ic0 += -0.000357 * in[j+4][i+8];
outjp2ic0 += -0.000357 * in[j+8][i];
outjp2ic0 += -0.000357 * in[j+8][i+8];
outjp2ic0 += -0.000357 * in[j+10][i+2];
outjp2ic0 += -0.000357 * in[j+10][i+6];
outjp2ic0 += 0.002856 * in[j+2][i+3];
outjp2ic0 += 0.002856 * in[j+2][i+5];
outjp2ic0 += 0.002856 * in[j+5][i];
outjp2ic0 += 0.002856 * in[j+5][i+8];
outjp2ic0 += 0.002856 * in[j+7][i];
outjp2ic0 += 0.002856 * in[j+7][i+8];
outjp2ic0 += 0.002856 * in[j+10][i+3];
outjp2ic0 += 0.002856 * in[j+10][i+5];
outjp2ic0 += -0.00508225 * in[j+2][i+4];
outjp2ic0 += -0.00508225 * in[j+6][i+8];
outjp2ic0 += -0.00508225 * in[j+6][i];
outjp2ic0 += -0.00508225 * in[j+10][i+4];
outjp2ic0 += 0.00064516 * in[j+3][i+1];
outjp2ic0 += 0.00064516 * in[j+3][i+7];
outjp2ic0 += 0.00064516 * in[j+9][i+1];
outjp2ic0 += 0.00064516 * in[j+9][i+7];
outjp2ic0 += -0.00508 * in[j+3][i+2];
outjp2ic0 += -0.00508 * in[j+3][i+6];
outjp2ic0 += -0.00508 * in[j+4][i+1];
outjp2ic0 += -0.00508 * in[j+4][i+7];
outjp2ic0 += -0.00508 * in[j+8][i+1];
outjp2ic0 += -0.00508 * in[j+8][i+7];
outjp2ic0 += -0.00508 * in[j+9][i+2];
outjp2ic0 += -0.00508 * in[j+9][i+6];
outjp2ic0 += 0.04064 * in[j+3][i+3];
outjp2ic0 += 0.04064 * in[j+3][i+5];
outjp2ic0 += 0.04064 * in[j+5][i+1];
outjp2ic0 += 0.04064 * in[j+5][i+7];
outjp2ic0 += 0.04064 * in[j+7][i+1];
outjp2ic0 += 0.04064 * in[j+7][i+7];
outjp2ic0 += 0.04064 * in[j+9][i+3];
outjp2ic0 += 0.04064 * in[j+9][i+5];
outjp2ic0 += -0.0723189 * in[j+3][i+4];
outjp2ic0 += -0.0723189 * in[j+6][i+1];
outjp2ic0 += -0.0723189 * in[j+6][i+7];
outjp2ic0 += -0.0723189 * in[j+9][i+4];
outjp2ic0 += 0.04 * in[j+4][i+2];
outjp2ic0 += 0.04 * in[j+4][i+6];
outjp2ic0 += 0.04 * in[j+8][i+2];
outjp2ic0 += 0.04 * in[j+8][i+6];
outjp2ic0 += -0.32 * in[j+4][i+3];
outjp2ic0 += -0.32 * in[j+4][i+5];
outjp2ic0 += -0.32 * in[j+5][i+2];
outjp2ic0 += -0.32 * in[j+5][i+6];
outjp2ic0 += -0.32 * in[j+7][i+2];
outjp2ic0 += -0.32 * in[j+7][i+6];
outjp2ic0 += -0.32 * in[j+8][i+3];
outjp2ic0 += -0.32 * in[j+8][i+5];
outjp2ic0 += 0.56944 * in[j+4][i+4];
outjp2ic0 += 0.56944 * in[j+6][i+2];
outjp2ic0 += 0.56944 * in[j+6][i+6];
outjp2ic0 += 0.56944 * in[j+8][i+4];
outjp2ic0 += 2.56 * in[j+5][i+3];
outjp2ic0 += 2.56 * in[j+5][i+5];
outjp2ic0 += 2.56 * in[j+7][i+3];
outjp2ic0 += 2.56 * in[j+7][i+5];
outjp2ic0 += -4.55552 * in[j+5][i+4];
outjp2ic0 += -4.55552 * in[j+6][i+3];
outjp2ic0 += -4.55552 * in[j+6][i+5];
outjp2ic0 += -4.55552 * in[j+7][i+4];
outjp2ic0 += in[j+6][i+4] * 8.10655;
out[j+2][i] = outjp2ic0;
outjp3ic0 = 3.18622 * in[j+3][i];
outjp3ic0 += 3.18622 * in[j+3][i+8];
outjp3ic0 += 3.18622 * in[j+11][i];
outjp3ic0 += 3.18622 * in[j+11][i+8];
outjp3ic0 += 4.5339 * in[j+3][i+1];
outjp3ic0 += 4.5339 * in[j+3][i+7];
outjp3ic0 += 4.5339 * in[j+4][i];
outjp3ic0 += 4.5339 * in[j+4][i+8];
outjp3ic0 += 4.5339 * in[j+10][i];
outjp3ic0 += 4.5339 * in[j+10][i+8];
outjp3ic0 += 4.5339 * in[j+11][i+1];
outjp3ic0 += 4.5339 * in[j+11][i+7];
outjp3ic0 += -0.000357 * in[j+3][i+2];
outjp3ic0 += -0.000357 * in[j+3][i+6];
outjp3ic0 += -0.000357 * in[j+5][i];
outjp3ic0 += -0.000357 * in[j+5][i+8];
outjp3ic0 += -0.000357 * in[j+9][i];
outjp3ic0 += -0.000357 * in[j+9][i+8];
outjp3ic0 += -0.000357 * in[j+11][i+2];
outjp3ic0 += -0.000357 * in[j+11][i+6];
outjp3ic0 += 0.002856 * in[j+3][i+3];
outjp3ic0 += 0.002856 * in[j+3][i+5];
outjp3ic0 += 0.002856 * in[j+6][i];
outjp3ic0 += 0.002856 * in[j+6][i+8];
outjp3ic0 += 0.002856 * in[j+8][i];
outjp3ic0 += 0.002856 * in[j+8][i+8];
outjp3ic0 += 0.002856 * in[j+11][i+3];
outjp3ic0 += 0.002856 * in[j+11][i+5];
outjp3ic0 += -0.00508225 * in[j+3][i+4];
outjp3ic0 += -0.00508225 * in[j+7][i+8];
outjp3ic0 += -0.00508225 * in[j+7][i];
outjp3ic0 += -0.00508225 * in[j+11][i+4];
outjp3ic0 += 0.00064516 * in[j+4][i+1];
outjp3ic0 += 0.00064516 * in[j+4][i+7];
outjp3ic0 += 0.00064516 * in[j+10][i+1];
outjp3ic0 += 0.00064516 * in[j+10][i+7];
outjp3ic0 += -0.00508 * in[j+4][i+2];
outjp3ic0 += -0.00508 * in[j+4][i+6];
outjp3ic0 += -0.00508 * in[j+5][i+1];
outjp3ic0 += -0.00508 * in[j+5][i+7];
outjp3ic0 += -0.00508 * in[j+9][i+1];
outjp3ic0 += -0.00508 * in[j+9][i+7];
outjp3ic0 += -0.00508 * in[j+10][i+2];
outjp3ic0 += -0.00508 * in[j+10][i+6];
outjp3ic0 += 0.04064 * in[j+4][i+3];
outjp3ic0 += 0.04064 * in[j+4][i+5];
outjp3ic0 += 0.04064 * in[j+6][i+1];
outjp3ic0 += 0.04064 * in[j+6][i+7];
outjp3ic0 += 0.04064 * in[j+8][i+1];
outjp3ic0 += 0.04064 * in[j+8][i+7];
outjp3ic0 += 0.04064 * in[j+10][i+3];
outjp3ic0 += 0.04064 * in[j+10][i+5];
outjp3ic0 += -0.0723189 * in[j+4][i+4];
outjp3ic0 += -0.0723189 * in[j+7][i+1];
outjp3ic0 += -0.0723189 * in[j+7][i+7];
outjp3ic0 += -0.0723189 * in[j+10][i+4];
outjp3ic0 += 0.04 * in[j+5][i+2];
outjp3ic0 += 0.04 * in[j+5][i+6];
outjp3ic0 += 0.04 * in[j+9][i+2];
outjp3ic0 += 0.04 * in[j+9][i+6];
outjp3ic0 += -0.32 * in[j+5][i+3];
outjp3ic0 += -0.32 * in[j+5][i+5];
outjp3ic0 += -0.32 * in[j+6][i+2];
outjp3ic0 += -0.32 * in[j+6][i+6];
outjp3ic0 += -0.32 * in[j+8][i+2];
outjp3ic0 += -0.32 * in[j+8][i+6];
outjp3ic0 += -0.32 * in[j+9][i+3];
outjp3ic0 += -0.32 * in[j+9][i+5];
outjp3ic0 += 0.56944 * in[j+5][i+4];
outjp3ic0 += 0.56944 * in[j+7][i+2];
outjp3ic0 += 0.56944 * in[j+7][i+6];
outjp3ic0 += 0.56944 * in[j+9][i+4];
outjp3ic0 += 2.56 * in[j+6][i+3];
outjp3ic0 += 2.56 * in[j+6][i+5];
outjp3ic0 += 2.56 * in[j+8][i+3];
outjp3ic0 += 2.56 * in[j+8][i+5];
outjp3ic0 += -4.55552 * in[j+6][i+4];
outjp3ic0 += -4.55552 * in[j+7][i+3];
outjp3ic0 += -4.55552 * in[j+7][i+5];
outjp3ic0 += -4.55552 * in[j+8][i+4];
outjp3ic0 += in[j+7][i+4] * 8.10655;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
cudaMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
double *out;
cudaMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
cudaFree (in);
cudaFree (out);
} | .file "tmpxft_001513c6_00000000-6_reordered-d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.type _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d81ptPdS_iPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7j2d81ptPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.globl _Z7j2d81ptPdS_i
.type _Z7j2d81ptPdS_i, @function
_Z7j2d81ptPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7j2d81ptPdS_i, .-_Z7j2d81ptPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for in\n"
.align 8
.LC2:
.string "Failed to allocate device memory for out\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, 24(%rsp)
testb $31, %bpl
jne .L16
movl %ebp, %eax
shrl $5, %eax
.L17:
movl %ebp, %edx
shrl $4, %edx
.L19:
movl %edx, 28(%rsp)
movl %eax, 32(%rsp)
movl $16, 16(%rsp)
movl $8, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %eax
shrl $5, %eax
addl $1, %eax
testb $15, %bpl
je .L17
movl %ebp, %edx
shrl $4, %edx
addl $1, %edx
jmp .L19
.L23:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC3:
.string "_Z7j2d81ptPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7j2d81ptPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double outjc0ic0;
double outjp1ic0;
double outjp2ic0;
double outjp3ic0;
outjc0ic0 = 3.18622 * in[j][i];
outjc0ic0 += 3.18622 * in[j][i+8];
outjc0ic0 += 3.18622 * in[j+8][i];
outjc0ic0 += 3.18622 * in[j+8][i+8];
outjc0ic0 += 4.5339 * in[j][i+1];
outjc0ic0 += 4.5339 * in[j][i+7];
outjc0ic0 += 4.5339 * in[j+1][i];
outjc0ic0 += 4.5339 * in[j+1][i+8];
outjc0ic0 += 4.5339 * in[j+7][i];
outjc0ic0 += 4.5339 * in[j+7][i+8];
outjc0ic0 += 4.5339 * in[j+8][i+1];
outjc0ic0 += 4.5339 * in[j+8][i+7];
outjc0ic0 += -0.000357 * in[j][i+2];
outjc0ic0 += -0.000357 * in[j][i+6];
outjc0ic0 += -0.000357 * in[j+2][i];
outjc0ic0 += -0.000357 * in[j+2][i+8];
outjc0ic0 += -0.000357 * in[j+6][i];
outjc0ic0 += -0.000357 * in[j+6][i+8];
outjc0ic0 += -0.000357 * in[j+8][i+2];
outjc0ic0 += -0.000357 * in[j+8][i+6];
outjc0ic0 += 0.002856 * in[j][i+3];
outjc0ic0 += 0.002856 * in[j][i+5];
outjc0ic0 += 0.002856 * in[j+3][i];
outjc0ic0 += 0.002856 * in[j+3][i+8];
outjc0ic0 += 0.002856 * in[j+5][i];
outjc0ic0 += 0.002856 * in[j+5][i+8];
outjc0ic0 += 0.002856 * in[j+8][i+3];
outjc0ic0 += 0.002856 * in[j+8][i+5];
outjc0ic0 += -0.00508225 * in[j][i+4];
outjc0ic0 += -0.00508225 * in[j+4][i+8];
outjc0ic0 += -0.00508225 * in[j+4][i];
outjc0ic0 += -0.00508225 * in[j+8][i+4];
outjc0ic0 += 0.00064516 * in[j+1][i+1];
outjc0ic0 += 0.00064516 * in[j+1][i+7];
outjc0ic0 += 0.00064516 * in[j+7][i+1];
outjc0ic0 += 0.00064516 * in[j+7][i+7];
outjc0ic0 += -0.00508 * in[j+1][i+2];
outjc0ic0 += -0.00508 * in[j+1][i+6];
outjc0ic0 += -0.00508 * in[j+2][i+1];
outjc0ic0 += -0.00508 * in[j+2][i+7];
outjc0ic0 += -0.00508 * in[j+6][i+1];
outjc0ic0 += -0.00508 * in[j+6][i+7];
outjc0ic0 += -0.00508 * in[j+7][i+2];
outjc0ic0 += -0.00508 * in[j+7][i+6];
outjc0ic0 += 0.04064 * in[j+1][i+3];
outjc0ic0 += 0.04064 * in[j+1][i+5];
outjc0ic0 += 0.04064 * in[j+3][i+1];
outjc0ic0 += 0.04064 * in[j+3][i+7];
outjc0ic0 += 0.04064 * in[j+5][i+1];
outjc0ic0 += 0.04064 * in[j+5][i+7];
outjc0ic0 += 0.04064 * in[j+7][i+3];
outjc0ic0 += 0.04064 * in[j+7][i+5];
outjc0ic0 += -0.0723189 * in[j+1][i+4];
outjc0ic0 += -0.0723189 * in[j+4][i+1];
outjc0ic0 += -0.0723189 * in[j+4][i+7];
outjc0ic0 += -0.0723189 * in[j+7][i+4];
outjc0ic0 += 0.04 * in[j+2][i+2];
outjc0ic0 += 0.04 * in[j+2][i+6];
outjc0ic0 += 0.04 * in[j+6][i+2];
outjc0ic0 += 0.04 * in[j+6][i+6];
outjc0ic0 += -0.32 * in[j+2][i+3];
outjc0ic0 += -0.32 * in[j+2][i+5];
outjc0ic0 += -0.32 * in[j+3][i+2];
outjc0ic0 += -0.32 * in[j+3][i+6];
outjc0ic0 += -0.32 * in[j+5][i+2];
outjc0ic0 += -0.32 * in[j+5][i+6];
outjc0ic0 += -0.32 * in[j+6][i+3];
outjc0ic0 += -0.32 * in[j+6][i+5];
outjc0ic0 += 0.56944 * in[j+2][i+4];
outjc0ic0 += 0.56944 * in[j+4][i+2];
outjc0ic0 += 0.56944 * in[j+4][i+6];
outjc0ic0 += 0.56944 * in[j+6][i+4];
outjc0ic0 += 2.56 * in[j+3][i+3];
outjc0ic0 += 2.56 * in[j+3][i+5];
outjc0ic0 += 2.56 * in[j+5][i+3];
outjc0ic0 += 2.56 * in[j+5][i+5];
outjc0ic0 += -4.55552 * in[j+3][i+4];
outjc0ic0 += -4.55552 * in[j+4][i+3];
outjc0ic0 += -4.55552 * in[j+4][i+5];
outjc0ic0 += -4.55552 * in[j+5][i+4];
outjc0ic0 += in[j+4][i+4] * 8.10655;
out[j][i] = outjc0ic0;
outjp1ic0 = 3.18622 * in[j+1][i];
outjp1ic0 += 3.18622 * in[j+1][i+8];
outjp1ic0 += 3.18622 * in[j+9][i];
outjp1ic0 += 3.18622 * in[j+9][i+8];
outjp1ic0 += 4.5339 * in[j+1][i+1];
outjp1ic0 += 4.5339 * in[j+1][i+7];
outjp1ic0 += 4.5339 * in[j+2][i];
outjp1ic0 += 4.5339 * in[j+2][i+8];
outjp1ic0 += 4.5339 * in[j+8][i];
outjp1ic0 += 4.5339 * in[j+8][i+8];
outjp1ic0 += 4.5339 * in[j+9][i+1];
outjp1ic0 += 4.5339 * in[j+9][i+7];
outjp1ic0 += -0.000357 * in[j+1][i+2];
outjp1ic0 += -0.000357 * in[j+1][i+6];
outjp1ic0 += -0.000357 * in[j+3][i];
outjp1ic0 += -0.000357 * in[j+3][i+8];
outjp1ic0 += -0.000357 * in[j+7][i];
outjp1ic0 += -0.000357 * in[j+7][i+8];
outjp1ic0 += -0.000357 * in[j+9][i+2];
outjp1ic0 += -0.000357 * in[j+9][i+6];
outjp1ic0 += 0.002856 * in[j+1][i+3];
outjp1ic0 += 0.002856 * in[j+1][i+5];
outjp1ic0 += 0.002856 * in[j+4][i];
outjp1ic0 += 0.002856 * in[j+4][i+8];
outjp1ic0 += 0.002856 * in[j+6][i];
outjp1ic0 += 0.002856 * in[j+6][i+8];
outjp1ic0 += 0.002856 * in[j+9][i+3];
outjp1ic0 += 0.002856 * in[j+9][i+5];
outjp1ic0 += -0.00508225 * in[j+1][i+4];
outjp1ic0 += -0.00508225 * in[j+5][i+8];
outjp1ic0 += -0.00508225 * in[j+5][i];
outjp1ic0 += -0.00508225 * in[j+9][i+4];
outjp1ic0 += 0.00064516 * in[j+2][i+1];
outjp1ic0 += 0.00064516 * in[j+2][i+7];
outjp1ic0 += 0.00064516 * in[j+8][i+1];
outjp1ic0 += 0.00064516 * in[j+8][i+7];
outjp1ic0 += -0.00508 * in[j+2][i+2];
outjp1ic0 += -0.00508 * in[j+2][i+6];
outjp1ic0 += -0.00508 * in[j+3][i+1];
outjp1ic0 += -0.00508 * in[j+3][i+7];
outjp1ic0 += -0.00508 * in[j+7][i+1];
outjp1ic0 += -0.00508 * in[j+7][i+7];
outjp1ic0 += -0.00508 * in[j+8][i+2];
outjp1ic0 += -0.00508 * in[j+8][i+6];
outjp1ic0 += 0.04064 * in[j+2][i+3];
outjp1ic0 += 0.04064 * in[j+2][i+5];
outjp1ic0 += 0.04064 * in[j+4][i+1];
outjp1ic0 += 0.04064 * in[j+4][i+7];
outjp1ic0 += 0.04064 * in[j+6][i+1];
outjp1ic0 += 0.04064 * in[j+6][i+7];
outjp1ic0 += 0.04064 * in[j+8][i+3];
outjp1ic0 += 0.04064 * in[j+8][i+5];
outjp1ic0 += -0.0723189 * in[j+2][i+4];
outjp1ic0 += -0.0723189 * in[j+5][i+1];
outjp1ic0 += -0.0723189 * in[j+5][i+7];
outjp1ic0 += -0.0723189 * in[j+8][i+4];
outjp1ic0 += 0.04 * in[j+3][i+2];
outjp1ic0 += 0.04 * in[j+3][i+6];
outjp1ic0 += 0.04 * in[j+7][i+2];
outjp1ic0 += 0.04 * in[j+7][i+6];
outjp1ic0 += -0.32 * in[j+3][i+3];
outjp1ic0 += -0.32 * in[j+3][i+5];
outjp1ic0 += -0.32 * in[j+4][i+2];
outjp1ic0 += -0.32 * in[j+4][i+6];
outjp1ic0 += -0.32 * in[j+6][i+2];
outjp1ic0 += -0.32 * in[j+6][i+6];
outjp1ic0 += -0.32 * in[j+7][i+3];
outjp1ic0 += -0.32 * in[j+7][i+5];
outjp1ic0 += 0.56944 * in[j+3][i+4];
outjp1ic0 += 0.56944 * in[j+5][i+2];
outjp1ic0 += 0.56944 * in[j+5][i+6];
outjp1ic0 += 0.56944 * in[j+7][i+4];
outjp1ic0 += 2.56 * in[j+4][i+3];
outjp1ic0 += 2.56 * in[j+4][i+5];
outjp1ic0 += 2.56 * in[j+6][i+3];
outjp1ic0 += 2.56 * in[j+6][i+5];
outjp1ic0 += -4.55552 * in[j+4][i+4];
outjp1ic0 += -4.55552 * in[j+5][i+3];
outjp1ic0 += -4.55552 * in[j+5][i+5];
outjp1ic0 += -4.55552 * in[j+6][i+4];
outjp1ic0 += in[j+5][i+4] * 8.10655;
out[j+1][i] = outjp1ic0;
outjp2ic0 = 3.18622 * in[j+2][i];
outjp2ic0 += 3.18622 * in[j+2][i+8];
outjp2ic0 += 3.18622 * in[j+10][i];
outjp2ic0 += 3.18622 * in[j+10][i+8];
outjp2ic0 += 4.5339 * in[j+2][i+1];
outjp2ic0 += 4.5339 * in[j+2][i+7];
outjp2ic0 += 4.5339 * in[j+3][i];
outjp2ic0 += 4.5339 * in[j+3][i+8];
outjp2ic0 += 4.5339 * in[j+9][i];
outjp2ic0 += 4.5339 * in[j+9][i+8];
outjp2ic0 += 4.5339 * in[j+10][i+1];
outjp2ic0 += 4.5339 * in[j+10][i+7];
outjp2ic0 += -0.000357 * in[j+2][i+2];
outjp2ic0 += -0.000357 * in[j+2][i+6];
outjp2ic0 += -0.000357 * in[j+4][i];
outjp2ic0 += -0.000357 * in[j+4][i+8];
outjp2ic0 += -0.000357 * in[j+8][i];
outjp2ic0 += -0.000357 * in[j+8][i+8];
outjp2ic0 += -0.000357 * in[j+10][i+2];
outjp2ic0 += -0.000357 * in[j+10][i+6];
outjp2ic0 += 0.002856 * in[j+2][i+3];
outjp2ic0 += 0.002856 * in[j+2][i+5];
outjp2ic0 += 0.002856 * in[j+5][i];
outjp2ic0 += 0.002856 * in[j+5][i+8];
outjp2ic0 += 0.002856 * in[j+7][i];
outjp2ic0 += 0.002856 * in[j+7][i+8];
outjp2ic0 += 0.002856 * in[j+10][i+3];
outjp2ic0 += 0.002856 * in[j+10][i+5];
outjp2ic0 += -0.00508225 * in[j+2][i+4];
outjp2ic0 += -0.00508225 * in[j+6][i+8];
outjp2ic0 += -0.00508225 * in[j+6][i];
outjp2ic0 += -0.00508225 * in[j+10][i+4];
outjp2ic0 += 0.00064516 * in[j+3][i+1];
outjp2ic0 += 0.00064516 * in[j+3][i+7];
outjp2ic0 += 0.00064516 * in[j+9][i+1];
outjp2ic0 += 0.00064516 * in[j+9][i+7];
outjp2ic0 += -0.00508 * in[j+3][i+2];
outjp2ic0 += -0.00508 * in[j+3][i+6];
outjp2ic0 += -0.00508 * in[j+4][i+1];
outjp2ic0 += -0.00508 * in[j+4][i+7];
outjp2ic0 += -0.00508 * in[j+8][i+1];
outjp2ic0 += -0.00508 * in[j+8][i+7];
outjp2ic0 += -0.00508 * in[j+9][i+2];
outjp2ic0 += -0.00508 * in[j+9][i+6];
outjp2ic0 += 0.04064 * in[j+3][i+3];
outjp2ic0 += 0.04064 * in[j+3][i+5];
outjp2ic0 += 0.04064 * in[j+5][i+1];
outjp2ic0 += 0.04064 * in[j+5][i+7];
outjp2ic0 += 0.04064 * in[j+7][i+1];
outjp2ic0 += 0.04064 * in[j+7][i+7];
outjp2ic0 += 0.04064 * in[j+9][i+3];
outjp2ic0 += 0.04064 * in[j+9][i+5];
outjp2ic0 += -0.0723189 * in[j+3][i+4];
outjp2ic0 += -0.0723189 * in[j+6][i+1];
outjp2ic0 += -0.0723189 * in[j+6][i+7];
outjp2ic0 += -0.0723189 * in[j+9][i+4];
outjp2ic0 += 0.04 * in[j+4][i+2];
outjp2ic0 += 0.04 * in[j+4][i+6];
outjp2ic0 += 0.04 * in[j+8][i+2];
outjp2ic0 += 0.04 * in[j+8][i+6];
outjp2ic0 += -0.32 * in[j+4][i+3];
outjp2ic0 += -0.32 * in[j+4][i+5];
outjp2ic0 += -0.32 * in[j+5][i+2];
outjp2ic0 += -0.32 * in[j+5][i+6];
outjp2ic0 += -0.32 * in[j+7][i+2];
outjp2ic0 += -0.32 * in[j+7][i+6];
outjp2ic0 += -0.32 * in[j+8][i+3];
outjp2ic0 += -0.32 * in[j+8][i+5];
outjp2ic0 += 0.56944 * in[j+4][i+4];
outjp2ic0 += 0.56944 * in[j+6][i+2];
outjp2ic0 += 0.56944 * in[j+6][i+6];
outjp2ic0 += 0.56944 * in[j+8][i+4];
outjp2ic0 += 2.56 * in[j+5][i+3];
outjp2ic0 += 2.56 * in[j+5][i+5];
outjp2ic0 += 2.56 * in[j+7][i+3];
outjp2ic0 += 2.56 * in[j+7][i+5];
outjp2ic0 += -4.55552 * in[j+5][i+4];
outjp2ic0 += -4.55552 * in[j+6][i+3];
outjp2ic0 += -4.55552 * in[j+6][i+5];
outjp2ic0 += -4.55552 * in[j+7][i+4];
outjp2ic0 += in[j+6][i+4] * 8.10655;
out[j+2][i] = outjp2ic0;
outjp3ic0 = 3.18622 * in[j+3][i];
outjp3ic0 += 3.18622 * in[j+3][i+8];
outjp3ic0 += 3.18622 * in[j+11][i];
outjp3ic0 += 3.18622 * in[j+11][i+8];
outjp3ic0 += 4.5339 * in[j+3][i+1];
outjp3ic0 += 4.5339 * in[j+3][i+7];
outjp3ic0 += 4.5339 * in[j+4][i];
outjp3ic0 += 4.5339 * in[j+4][i+8];
outjp3ic0 += 4.5339 * in[j+10][i];
outjp3ic0 += 4.5339 * in[j+10][i+8];
outjp3ic0 += 4.5339 * in[j+11][i+1];
outjp3ic0 += 4.5339 * in[j+11][i+7];
outjp3ic0 += -0.000357 * in[j+3][i+2];
outjp3ic0 += -0.000357 * in[j+3][i+6];
outjp3ic0 += -0.000357 * in[j+5][i];
outjp3ic0 += -0.000357 * in[j+5][i+8];
outjp3ic0 += -0.000357 * in[j+9][i];
outjp3ic0 += -0.000357 * in[j+9][i+8];
outjp3ic0 += -0.000357 * in[j+11][i+2];
outjp3ic0 += -0.000357 * in[j+11][i+6];
outjp3ic0 += 0.002856 * in[j+3][i+3];
outjp3ic0 += 0.002856 * in[j+3][i+5];
outjp3ic0 += 0.002856 * in[j+6][i];
outjp3ic0 += 0.002856 * in[j+6][i+8];
outjp3ic0 += 0.002856 * in[j+8][i];
outjp3ic0 += 0.002856 * in[j+8][i+8];
outjp3ic0 += 0.002856 * in[j+11][i+3];
outjp3ic0 += 0.002856 * in[j+11][i+5];
outjp3ic0 += -0.00508225 * in[j+3][i+4];
outjp3ic0 += -0.00508225 * in[j+7][i+8];
outjp3ic0 += -0.00508225 * in[j+7][i];
outjp3ic0 += -0.00508225 * in[j+11][i+4];
outjp3ic0 += 0.00064516 * in[j+4][i+1];
outjp3ic0 += 0.00064516 * in[j+4][i+7];
outjp3ic0 += 0.00064516 * in[j+10][i+1];
outjp3ic0 += 0.00064516 * in[j+10][i+7];
outjp3ic0 += -0.00508 * in[j+4][i+2];
outjp3ic0 += -0.00508 * in[j+4][i+6];
outjp3ic0 += -0.00508 * in[j+5][i+1];
outjp3ic0 += -0.00508 * in[j+5][i+7];
outjp3ic0 += -0.00508 * in[j+9][i+1];
outjp3ic0 += -0.00508 * in[j+9][i+7];
outjp3ic0 += -0.00508 * in[j+10][i+2];
outjp3ic0 += -0.00508 * in[j+10][i+6];
outjp3ic0 += 0.04064 * in[j+4][i+3];
outjp3ic0 += 0.04064 * in[j+4][i+5];
outjp3ic0 += 0.04064 * in[j+6][i+1];
outjp3ic0 += 0.04064 * in[j+6][i+7];
outjp3ic0 += 0.04064 * in[j+8][i+1];
outjp3ic0 += 0.04064 * in[j+8][i+7];
outjp3ic0 += 0.04064 * in[j+10][i+3];
outjp3ic0 += 0.04064 * in[j+10][i+5];
outjp3ic0 += -0.0723189 * in[j+4][i+4];
outjp3ic0 += -0.0723189 * in[j+7][i+1];
outjp3ic0 += -0.0723189 * in[j+7][i+7];
outjp3ic0 += -0.0723189 * in[j+10][i+4];
outjp3ic0 += 0.04 * in[j+5][i+2];
outjp3ic0 += 0.04 * in[j+5][i+6];
outjp3ic0 += 0.04 * in[j+9][i+2];
outjp3ic0 += 0.04 * in[j+9][i+6];
outjp3ic0 += -0.32 * in[j+5][i+3];
outjp3ic0 += -0.32 * in[j+5][i+5];
outjp3ic0 += -0.32 * in[j+6][i+2];
outjp3ic0 += -0.32 * in[j+6][i+6];
outjp3ic0 += -0.32 * in[j+8][i+2];
outjp3ic0 += -0.32 * in[j+8][i+6];
outjp3ic0 += -0.32 * in[j+9][i+3];
outjp3ic0 += -0.32 * in[j+9][i+5];
outjp3ic0 += 0.56944 * in[j+5][i+4];
outjp3ic0 += 0.56944 * in[j+7][i+2];
outjp3ic0 += 0.56944 * in[j+7][i+6];
outjp3ic0 += 0.56944 * in[j+9][i+4];
outjp3ic0 += 2.56 * in[j+6][i+3];
outjp3ic0 += 2.56 * in[j+6][i+5];
outjp3ic0 += 2.56 * in[j+8][i+3];
outjp3ic0 += 2.56 * in[j+8][i+5];
outjp3ic0 += -4.55552 * in[j+6][i+4];
outjp3ic0 += -4.55552 * in[j+7][i+3];
outjp3ic0 += -4.55552 * in[j+7][i+5];
outjp3ic0 += -4.55552 * in[j+8][i+4];
outjp3ic0 += in[j+7][i+4] * 8.10655;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
cudaMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
double *out;
cudaMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
cudaFree (in);
cudaFree (out);
} | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double outjc0ic0;
double outjp1ic0;
double outjp2ic0;
double outjp3ic0;
outjc0ic0 = 3.18622 * in[j][i];
outjc0ic0 += 3.18622 * in[j][i+8];
outjc0ic0 += 3.18622 * in[j+8][i];
outjc0ic0 += 3.18622 * in[j+8][i+8];
outjc0ic0 += 4.5339 * in[j][i+1];
outjc0ic0 += 4.5339 * in[j][i+7];
outjc0ic0 += 4.5339 * in[j+1][i];
outjc0ic0 += 4.5339 * in[j+1][i+8];
outjc0ic0 += 4.5339 * in[j+7][i];
outjc0ic0 += 4.5339 * in[j+7][i+8];
outjc0ic0 += 4.5339 * in[j+8][i+1];
outjc0ic0 += 4.5339 * in[j+8][i+7];
outjc0ic0 += -0.000357 * in[j][i+2];
outjc0ic0 += -0.000357 * in[j][i+6];
outjc0ic0 += -0.000357 * in[j+2][i];
outjc0ic0 += -0.000357 * in[j+2][i+8];
outjc0ic0 += -0.000357 * in[j+6][i];
outjc0ic0 += -0.000357 * in[j+6][i+8];
outjc0ic0 += -0.000357 * in[j+8][i+2];
outjc0ic0 += -0.000357 * in[j+8][i+6];
outjc0ic0 += 0.002856 * in[j][i+3];
outjc0ic0 += 0.002856 * in[j][i+5];
outjc0ic0 += 0.002856 * in[j+3][i];
outjc0ic0 += 0.002856 * in[j+3][i+8];
outjc0ic0 += 0.002856 * in[j+5][i];
outjc0ic0 += 0.002856 * in[j+5][i+8];
outjc0ic0 += 0.002856 * in[j+8][i+3];
outjc0ic0 += 0.002856 * in[j+8][i+5];
outjc0ic0 += -0.00508225 * in[j][i+4];
outjc0ic0 += -0.00508225 * in[j+4][i+8];
outjc0ic0 += -0.00508225 * in[j+4][i];
outjc0ic0 += -0.00508225 * in[j+8][i+4];
outjc0ic0 += 0.00064516 * in[j+1][i+1];
outjc0ic0 += 0.00064516 * in[j+1][i+7];
outjc0ic0 += 0.00064516 * in[j+7][i+1];
outjc0ic0 += 0.00064516 * in[j+7][i+7];
outjc0ic0 += -0.00508 * in[j+1][i+2];
outjc0ic0 += -0.00508 * in[j+1][i+6];
outjc0ic0 += -0.00508 * in[j+2][i+1];
outjc0ic0 += -0.00508 * in[j+2][i+7];
outjc0ic0 += -0.00508 * in[j+6][i+1];
outjc0ic0 += -0.00508 * in[j+6][i+7];
outjc0ic0 += -0.00508 * in[j+7][i+2];
outjc0ic0 += -0.00508 * in[j+7][i+6];
outjc0ic0 += 0.04064 * in[j+1][i+3];
outjc0ic0 += 0.04064 * in[j+1][i+5];
outjc0ic0 += 0.04064 * in[j+3][i+1];
outjc0ic0 += 0.04064 * in[j+3][i+7];
outjc0ic0 += 0.04064 * in[j+5][i+1];
outjc0ic0 += 0.04064 * in[j+5][i+7];
outjc0ic0 += 0.04064 * in[j+7][i+3];
outjc0ic0 += 0.04064 * in[j+7][i+5];
outjc0ic0 += -0.0723189 * in[j+1][i+4];
outjc0ic0 += -0.0723189 * in[j+4][i+1];
outjc0ic0 += -0.0723189 * in[j+4][i+7];
outjc0ic0 += -0.0723189 * in[j+7][i+4];
outjc0ic0 += 0.04 * in[j+2][i+2];
outjc0ic0 += 0.04 * in[j+2][i+6];
outjc0ic0 += 0.04 * in[j+6][i+2];
outjc0ic0 += 0.04 * in[j+6][i+6];
outjc0ic0 += -0.32 * in[j+2][i+3];
outjc0ic0 += -0.32 * in[j+2][i+5];
outjc0ic0 += -0.32 * in[j+3][i+2];
outjc0ic0 += -0.32 * in[j+3][i+6];
outjc0ic0 += -0.32 * in[j+5][i+2];
outjc0ic0 += -0.32 * in[j+5][i+6];
outjc0ic0 += -0.32 * in[j+6][i+3];
outjc0ic0 += -0.32 * in[j+6][i+5];
outjc0ic0 += 0.56944 * in[j+2][i+4];
outjc0ic0 += 0.56944 * in[j+4][i+2];
outjc0ic0 += 0.56944 * in[j+4][i+6];
outjc0ic0 += 0.56944 * in[j+6][i+4];
outjc0ic0 += 2.56 * in[j+3][i+3];
outjc0ic0 += 2.56 * in[j+3][i+5];
outjc0ic0 += 2.56 * in[j+5][i+3];
outjc0ic0 += 2.56 * in[j+5][i+5];
outjc0ic0 += -4.55552 * in[j+3][i+4];
outjc0ic0 += -4.55552 * in[j+4][i+3];
outjc0ic0 += -4.55552 * in[j+4][i+5];
outjc0ic0 += -4.55552 * in[j+5][i+4];
outjc0ic0 += in[j+4][i+4] * 8.10655;
out[j][i] = outjc0ic0;
outjp1ic0 = 3.18622 * in[j+1][i];
outjp1ic0 += 3.18622 * in[j+1][i+8];
outjp1ic0 += 3.18622 * in[j+9][i];
outjp1ic0 += 3.18622 * in[j+9][i+8];
outjp1ic0 += 4.5339 * in[j+1][i+1];
outjp1ic0 += 4.5339 * in[j+1][i+7];
outjp1ic0 += 4.5339 * in[j+2][i];
outjp1ic0 += 4.5339 * in[j+2][i+8];
outjp1ic0 += 4.5339 * in[j+8][i];
outjp1ic0 += 4.5339 * in[j+8][i+8];
outjp1ic0 += 4.5339 * in[j+9][i+1];
outjp1ic0 += 4.5339 * in[j+9][i+7];
outjp1ic0 += -0.000357 * in[j+1][i+2];
outjp1ic0 += -0.000357 * in[j+1][i+6];
outjp1ic0 += -0.000357 * in[j+3][i];
outjp1ic0 += -0.000357 * in[j+3][i+8];
outjp1ic0 += -0.000357 * in[j+7][i];
outjp1ic0 += -0.000357 * in[j+7][i+8];
outjp1ic0 += -0.000357 * in[j+9][i+2];
outjp1ic0 += -0.000357 * in[j+9][i+6];
outjp1ic0 += 0.002856 * in[j+1][i+3];
outjp1ic0 += 0.002856 * in[j+1][i+5];
outjp1ic0 += 0.002856 * in[j+4][i];
outjp1ic0 += 0.002856 * in[j+4][i+8];
outjp1ic0 += 0.002856 * in[j+6][i];
outjp1ic0 += 0.002856 * in[j+6][i+8];
outjp1ic0 += 0.002856 * in[j+9][i+3];
outjp1ic0 += 0.002856 * in[j+9][i+5];
outjp1ic0 += -0.00508225 * in[j+1][i+4];
outjp1ic0 += -0.00508225 * in[j+5][i+8];
outjp1ic0 += -0.00508225 * in[j+5][i];
outjp1ic0 += -0.00508225 * in[j+9][i+4];
outjp1ic0 += 0.00064516 * in[j+2][i+1];
outjp1ic0 += 0.00064516 * in[j+2][i+7];
outjp1ic0 += 0.00064516 * in[j+8][i+1];
outjp1ic0 += 0.00064516 * in[j+8][i+7];
outjp1ic0 += -0.00508 * in[j+2][i+2];
outjp1ic0 += -0.00508 * in[j+2][i+6];
outjp1ic0 += -0.00508 * in[j+3][i+1];
outjp1ic0 += -0.00508 * in[j+3][i+7];
outjp1ic0 += -0.00508 * in[j+7][i+1];
outjp1ic0 += -0.00508 * in[j+7][i+7];
outjp1ic0 += -0.00508 * in[j+8][i+2];
outjp1ic0 += -0.00508 * in[j+8][i+6];
outjp1ic0 += 0.04064 * in[j+2][i+3];
outjp1ic0 += 0.04064 * in[j+2][i+5];
outjp1ic0 += 0.04064 * in[j+4][i+1];
outjp1ic0 += 0.04064 * in[j+4][i+7];
outjp1ic0 += 0.04064 * in[j+6][i+1];
outjp1ic0 += 0.04064 * in[j+6][i+7];
outjp1ic0 += 0.04064 * in[j+8][i+3];
outjp1ic0 += 0.04064 * in[j+8][i+5];
outjp1ic0 += -0.0723189 * in[j+2][i+4];
outjp1ic0 += -0.0723189 * in[j+5][i+1];
outjp1ic0 += -0.0723189 * in[j+5][i+7];
outjp1ic0 += -0.0723189 * in[j+8][i+4];
outjp1ic0 += 0.04 * in[j+3][i+2];
outjp1ic0 += 0.04 * in[j+3][i+6];
outjp1ic0 += 0.04 * in[j+7][i+2];
outjp1ic0 += 0.04 * in[j+7][i+6];
outjp1ic0 += -0.32 * in[j+3][i+3];
outjp1ic0 += -0.32 * in[j+3][i+5];
outjp1ic0 += -0.32 * in[j+4][i+2];
outjp1ic0 += -0.32 * in[j+4][i+6];
outjp1ic0 += -0.32 * in[j+6][i+2];
outjp1ic0 += -0.32 * in[j+6][i+6];
outjp1ic0 += -0.32 * in[j+7][i+3];
outjp1ic0 += -0.32 * in[j+7][i+5];
outjp1ic0 += 0.56944 * in[j+3][i+4];
outjp1ic0 += 0.56944 * in[j+5][i+2];
outjp1ic0 += 0.56944 * in[j+5][i+6];
outjp1ic0 += 0.56944 * in[j+7][i+4];
outjp1ic0 += 2.56 * in[j+4][i+3];
outjp1ic0 += 2.56 * in[j+4][i+5];
outjp1ic0 += 2.56 * in[j+6][i+3];
outjp1ic0 += 2.56 * in[j+6][i+5];
outjp1ic0 += -4.55552 * in[j+4][i+4];
outjp1ic0 += -4.55552 * in[j+5][i+3];
outjp1ic0 += -4.55552 * in[j+5][i+5];
outjp1ic0 += -4.55552 * in[j+6][i+4];
outjp1ic0 += in[j+5][i+4] * 8.10655;
out[j+1][i] = outjp1ic0;
outjp2ic0 = 3.18622 * in[j+2][i];
outjp2ic0 += 3.18622 * in[j+2][i+8];
outjp2ic0 += 3.18622 * in[j+10][i];
outjp2ic0 += 3.18622 * in[j+10][i+8];
outjp2ic0 += 4.5339 * in[j+2][i+1];
outjp2ic0 += 4.5339 * in[j+2][i+7];
outjp2ic0 += 4.5339 * in[j+3][i];
outjp2ic0 += 4.5339 * in[j+3][i+8];
outjp2ic0 += 4.5339 * in[j+9][i];
outjp2ic0 += 4.5339 * in[j+9][i+8];
outjp2ic0 += 4.5339 * in[j+10][i+1];
outjp2ic0 += 4.5339 * in[j+10][i+7];
outjp2ic0 += -0.000357 * in[j+2][i+2];
outjp2ic0 += -0.000357 * in[j+2][i+6];
outjp2ic0 += -0.000357 * in[j+4][i];
outjp2ic0 += -0.000357 * in[j+4][i+8];
outjp2ic0 += -0.000357 * in[j+8][i];
outjp2ic0 += -0.000357 * in[j+8][i+8];
outjp2ic0 += -0.000357 * in[j+10][i+2];
outjp2ic0 += -0.000357 * in[j+10][i+6];
outjp2ic0 += 0.002856 * in[j+2][i+3];
outjp2ic0 += 0.002856 * in[j+2][i+5];
outjp2ic0 += 0.002856 * in[j+5][i];
outjp2ic0 += 0.002856 * in[j+5][i+8];
outjp2ic0 += 0.002856 * in[j+7][i];
outjp2ic0 += 0.002856 * in[j+7][i+8];
outjp2ic0 += 0.002856 * in[j+10][i+3];
outjp2ic0 += 0.002856 * in[j+10][i+5];
outjp2ic0 += -0.00508225 * in[j+2][i+4];
outjp2ic0 += -0.00508225 * in[j+6][i+8];
outjp2ic0 += -0.00508225 * in[j+6][i];
outjp2ic0 += -0.00508225 * in[j+10][i+4];
outjp2ic0 += 0.00064516 * in[j+3][i+1];
outjp2ic0 += 0.00064516 * in[j+3][i+7];
outjp2ic0 += 0.00064516 * in[j+9][i+1];
outjp2ic0 += 0.00064516 * in[j+9][i+7];
outjp2ic0 += -0.00508 * in[j+3][i+2];
outjp2ic0 += -0.00508 * in[j+3][i+6];
outjp2ic0 += -0.00508 * in[j+4][i+1];
outjp2ic0 += -0.00508 * in[j+4][i+7];
outjp2ic0 += -0.00508 * in[j+8][i+1];
outjp2ic0 += -0.00508 * in[j+8][i+7];
outjp2ic0 += -0.00508 * in[j+9][i+2];
outjp2ic0 += -0.00508 * in[j+9][i+6];
outjp2ic0 += 0.04064 * in[j+3][i+3];
outjp2ic0 += 0.04064 * in[j+3][i+5];
outjp2ic0 += 0.04064 * in[j+5][i+1];
outjp2ic0 += 0.04064 * in[j+5][i+7];
outjp2ic0 += 0.04064 * in[j+7][i+1];
outjp2ic0 += 0.04064 * in[j+7][i+7];
outjp2ic0 += 0.04064 * in[j+9][i+3];
outjp2ic0 += 0.04064 * in[j+9][i+5];
outjp2ic0 += -0.0723189 * in[j+3][i+4];
outjp2ic0 += -0.0723189 * in[j+6][i+1];
outjp2ic0 += -0.0723189 * in[j+6][i+7];
outjp2ic0 += -0.0723189 * in[j+9][i+4];
outjp2ic0 += 0.04 * in[j+4][i+2];
outjp2ic0 += 0.04 * in[j+4][i+6];
outjp2ic0 += 0.04 * in[j+8][i+2];
outjp2ic0 += 0.04 * in[j+8][i+6];
outjp2ic0 += -0.32 * in[j+4][i+3];
outjp2ic0 += -0.32 * in[j+4][i+5];
outjp2ic0 += -0.32 * in[j+5][i+2];
outjp2ic0 += -0.32 * in[j+5][i+6];
outjp2ic0 += -0.32 * in[j+7][i+2];
outjp2ic0 += -0.32 * in[j+7][i+6];
outjp2ic0 += -0.32 * in[j+8][i+3];
outjp2ic0 += -0.32 * in[j+8][i+5];
outjp2ic0 += 0.56944 * in[j+4][i+4];
outjp2ic0 += 0.56944 * in[j+6][i+2];
outjp2ic0 += 0.56944 * in[j+6][i+6];
outjp2ic0 += 0.56944 * in[j+8][i+4];
outjp2ic0 += 2.56 * in[j+5][i+3];
outjp2ic0 += 2.56 * in[j+5][i+5];
outjp2ic0 += 2.56 * in[j+7][i+3];
outjp2ic0 += 2.56 * in[j+7][i+5];
outjp2ic0 += -4.55552 * in[j+5][i+4];
outjp2ic0 += -4.55552 * in[j+6][i+3];
outjp2ic0 += -4.55552 * in[j+6][i+5];
outjp2ic0 += -4.55552 * in[j+7][i+4];
outjp2ic0 += in[j+6][i+4] * 8.10655;
out[j+2][i] = outjp2ic0;
outjp3ic0 = 3.18622 * in[j+3][i];
outjp3ic0 += 3.18622 * in[j+3][i+8];
outjp3ic0 += 3.18622 * in[j+11][i];
outjp3ic0 += 3.18622 * in[j+11][i+8];
outjp3ic0 += 4.5339 * in[j+3][i+1];
outjp3ic0 += 4.5339 * in[j+3][i+7];
outjp3ic0 += 4.5339 * in[j+4][i];
outjp3ic0 += 4.5339 * in[j+4][i+8];
outjp3ic0 += 4.5339 * in[j+10][i];
outjp3ic0 += 4.5339 * in[j+10][i+8];
outjp3ic0 += 4.5339 * in[j+11][i+1];
outjp3ic0 += 4.5339 * in[j+11][i+7];
outjp3ic0 += -0.000357 * in[j+3][i+2];
outjp3ic0 += -0.000357 * in[j+3][i+6];
outjp3ic0 += -0.000357 * in[j+5][i];
outjp3ic0 += -0.000357 * in[j+5][i+8];
outjp3ic0 += -0.000357 * in[j+9][i];
outjp3ic0 += -0.000357 * in[j+9][i+8];
outjp3ic0 += -0.000357 * in[j+11][i+2];
outjp3ic0 += -0.000357 * in[j+11][i+6];
outjp3ic0 += 0.002856 * in[j+3][i+3];
outjp3ic0 += 0.002856 * in[j+3][i+5];
outjp3ic0 += 0.002856 * in[j+6][i];
outjp3ic0 += 0.002856 * in[j+6][i+8];
outjp3ic0 += 0.002856 * in[j+8][i];
outjp3ic0 += 0.002856 * in[j+8][i+8];
outjp3ic0 += 0.002856 * in[j+11][i+3];
outjp3ic0 += 0.002856 * in[j+11][i+5];
outjp3ic0 += -0.00508225 * in[j+3][i+4];
outjp3ic0 += -0.00508225 * in[j+7][i+8];
outjp3ic0 += -0.00508225 * in[j+7][i];
outjp3ic0 += -0.00508225 * in[j+11][i+4];
outjp3ic0 += 0.00064516 * in[j+4][i+1];
outjp3ic0 += 0.00064516 * in[j+4][i+7];
outjp3ic0 += 0.00064516 * in[j+10][i+1];
outjp3ic0 += 0.00064516 * in[j+10][i+7];
outjp3ic0 += -0.00508 * in[j+4][i+2];
outjp3ic0 += -0.00508 * in[j+4][i+6];
outjp3ic0 += -0.00508 * in[j+5][i+1];
outjp3ic0 += -0.00508 * in[j+5][i+7];
outjp3ic0 += -0.00508 * in[j+9][i+1];
outjp3ic0 += -0.00508 * in[j+9][i+7];
outjp3ic0 += -0.00508 * in[j+10][i+2];
outjp3ic0 += -0.00508 * in[j+10][i+6];
outjp3ic0 += 0.04064 * in[j+4][i+3];
outjp3ic0 += 0.04064 * in[j+4][i+5];
outjp3ic0 += 0.04064 * in[j+6][i+1];
outjp3ic0 += 0.04064 * in[j+6][i+7];
outjp3ic0 += 0.04064 * in[j+8][i+1];
outjp3ic0 += 0.04064 * in[j+8][i+7];
outjp3ic0 += 0.04064 * in[j+10][i+3];
outjp3ic0 += 0.04064 * in[j+10][i+5];
outjp3ic0 += -0.0723189 * in[j+4][i+4];
outjp3ic0 += -0.0723189 * in[j+7][i+1];
outjp3ic0 += -0.0723189 * in[j+7][i+7];
outjp3ic0 += -0.0723189 * in[j+10][i+4];
outjp3ic0 += 0.04 * in[j+5][i+2];
outjp3ic0 += 0.04 * in[j+5][i+6];
outjp3ic0 += 0.04 * in[j+9][i+2];
outjp3ic0 += 0.04 * in[j+9][i+6];
outjp3ic0 += -0.32 * in[j+5][i+3];
outjp3ic0 += -0.32 * in[j+5][i+5];
outjp3ic0 += -0.32 * in[j+6][i+2];
outjp3ic0 += -0.32 * in[j+6][i+6];
outjp3ic0 += -0.32 * in[j+8][i+2];
outjp3ic0 += -0.32 * in[j+8][i+6];
outjp3ic0 += -0.32 * in[j+9][i+3];
outjp3ic0 += -0.32 * in[j+9][i+5];
outjp3ic0 += 0.56944 * in[j+5][i+4];
outjp3ic0 += 0.56944 * in[j+7][i+2];
outjp3ic0 += 0.56944 * in[j+7][i+6];
outjp3ic0 += 0.56944 * in[j+9][i+4];
outjp3ic0 += 2.56 * in[j+6][i+3];
outjp3ic0 += 2.56 * in[j+6][i+5];
outjp3ic0 += 2.56 * in[j+8][i+3];
outjp3ic0 += 2.56 * in[j+8][i+5];
outjp3ic0 += -4.55552 * in[j+6][i+4];
outjp3ic0 += -4.55552 * in[j+7][i+3];
outjp3ic0 += -4.55552 * in[j+7][i+5];
outjp3ic0 += -4.55552 * in[j+8][i+4];
outjp3ic0 += in[j+7][i+4] * 8.10655;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
hipMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
double *out;
hipMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
hipFree (in);
hipFree (out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double outjc0ic0;
double outjp1ic0;
double outjp2ic0;
double outjp3ic0;
outjc0ic0 = 3.18622 * in[j][i];
outjc0ic0 += 3.18622 * in[j][i+8];
outjc0ic0 += 3.18622 * in[j+8][i];
outjc0ic0 += 3.18622 * in[j+8][i+8];
outjc0ic0 += 4.5339 * in[j][i+1];
outjc0ic0 += 4.5339 * in[j][i+7];
outjc0ic0 += 4.5339 * in[j+1][i];
outjc0ic0 += 4.5339 * in[j+1][i+8];
outjc0ic0 += 4.5339 * in[j+7][i];
outjc0ic0 += 4.5339 * in[j+7][i+8];
outjc0ic0 += 4.5339 * in[j+8][i+1];
outjc0ic0 += 4.5339 * in[j+8][i+7];
outjc0ic0 += -0.000357 * in[j][i+2];
outjc0ic0 += -0.000357 * in[j][i+6];
outjc0ic0 += -0.000357 * in[j+2][i];
outjc0ic0 += -0.000357 * in[j+2][i+8];
outjc0ic0 += -0.000357 * in[j+6][i];
outjc0ic0 += -0.000357 * in[j+6][i+8];
outjc0ic0 += -0.000357 * in[j+8][i+2];
outjc0ic0 += -0.000357 * in[j+8][i+6];
outjc0ic0 += 0.002856 * in[j][i+3];
outjc0ic0 += 0.002856 * in[j][i+5];
outjc0ic0 += 0.002856 * in[j+3][i];
outjc0ic0 += 0.002856 * in[j+3][i+8];
outjc0ic0 += 0.002856 * in[j+5][i];
outjc0ic0 += 0.002856 * in[j+5][i+8];
outjc0ic0 += 0.002856 * in[j+8][i+3];
outjc0ic0 += 0.002856 * in[j+8][i+5];
outjc0ic0 += -0.00508225 * in[j][i+4];
outjc0ic0 += -0.00508225 * in[j+4][i+8];
outjc0ic0 += -0.00508225 * in[j+4][i];
outjc0ic0 += -0.00508225 * in[j+8][i+4];
outjc0ic0 += 0.00064516 * in[j+1][i+1];
outjc0ic0 += 0.00064516 * in[j+1][i+7];
outjc0ic0 += 0.00064516 * in[j+7][i+1];
outjc0ic0 += 0.00064516 * in[j+7][i+7];
outjc0ic0 += -0.00508 * in[j+1][i+2];
outjc0ic0 += -0.00508 * in[j+1][i+6];
outjc0ic0 += -0.00508 * in[j+2][i+1];
outjc0ic0 += -0.00508 * in[j+2][i+7];
outjc0ic0 += -0.00508 * in[j+6][i+1];
outjc0ic0 += -0.00508 * in[j+6][i+7];
outjc0ic0 += -0.00508 * in[j+7][i+2];
outjc0ic0 += -0.00508 * in[j+7][i+6];
outjc0ic0 += 0.04064 * in[j+1][i+3];
outjc0ic0 += 0.04064 * in[j+1][i+5];
outjc0ic0 += 0.04064 * in[j+3][i+1];
outjc0ic0 += 0.04064 * in[j+3][i+7];
outjc0ic0 += 0.04064 * in[j+5][i+1];
outjc0ic0 += 0.04064 * in[j+5][i+7];
outjc0ic0 += 0.04064 * in[j+7][i+3];
outjc0ic0 += 0.04064 * in[j+7][i+5];
outjc0ic0 += -0.0723189 * in[j+1][i+4];
outjc0ic0 += -0.0723189 * in[j+4][i+1];
outjc0ic0 += -0.0723189 * in[j+4][i+7];
outjc0ic0 += -0.0723189 * in[j+7][i+4];
outjc0ic0 += 0.04 * in[j+2][i+2];
outjc0ic0 += 0.04 * in[j+2][i+6];
outjc0ic0 += 0.04 * in[j+6][i+2];
outjc0ic0 += 0.04 * in[j+6][i+6];
outjc0ic0 += -0.32 * in[j+2][i+3];
outjc0ic0 += -0.32 * in[j+2][i+5];
outjc0ic0 += -0.32 * in[j+3][i+2];
outjc0ic0 += -0.32 * in[j+3][i+6];
outjc0ic0 += -0.32 * in[j+5][i+2];
outjc0ic0 += -0.32 * in[j+5][i+6];
outjc0ic0 += -0.32 * in[j+6][i+3];
outjc0ic0 += -0.32 * in[j+6][i+5];
outjc0ic0 += 0.56944 * in[j+2][i+4];
outjc0ic0 += 0.56944 * in[j+4][i+2];
outjc0ic0 += 0.56944 * in[j+4][i+6];
outjc0ic0 += 0.56944 * in[j+6][i+4];
outjc0ic0 += 2.56 * in[j+3][i+3];
outjc0ic0 += 2.56 * in[j+3][i+5];
outjc0ic0 += 2.56 * in[j+5][i+3];
outjc0ic0 += 2.56 * in[j+5][i+5];
outjc0ic0 += -4.55552 * in[j+3][i+4];
outjc0ic0 += -4.55552 * in[j+4][i+3];
outjc0ic0 += -4.55552 * in[j+4][i+5];
outjc0ic0 += -4.55552 * in[j+5][i+4];
outjc0ic0 += in[j+4][i+4] * 8.10655;
out[j][i] = outjc0ic0;
outjp1ic0 = 3.18622 * in[j+1][i];
outjp1ic0 += 3.18622 * in[j+1][i+8];
outjp1ic0 += 3.18622 * in[j+9][i];
outjp1ic0 += 3.18622 * in[j+9][i+8];
outjp1ic0 += 4.5339 * in[j+1][i+1];
outjp1ic0 += 4.5339 * in[j+1][i+7];
outjp1ic0 += 4.5339 * in[j+2][i];
outjp1ic0 += 4.5339 * in[j+2][i+8];
outjp1ic0 += 4.5339 * in[j+8][i];
outjp1ic0 += 4.5339 * in[j+8][i+8];
outjp1ic0 += 4.5339 * in[j+9][i+1];
outjp1ic0 += 4.5339 * in[j+9][i+7];
outjp1ic0 += -0.000357 * in[j+1][i+2];
outjp1ic0 += -0.000357 * in[j+1][i+6];
outjp1ic0 += -0.000357 * in[j+3][i];
outjp1ic0 += -0.000357 * in[j+3][i+8];
outjp1ic0 += -0.000357 * in[j+7][i];
outjp1ic0 += -0.000357 * in[j+7][i+8];
outjp1ic0 += -0.000357 * in[j+9][i+2];
outjp1ic0 += -0.000357 * in[j+9][i+6];
outjp1ic0 += 0.002856 * in[j+1][i+3];
outjp1ic0 += 0.002856 * in[j+1][i+5];
outjp1ic0 += 0.002856 * in[j+4][i];
outjp1ic0 += 0.002856 * in[j+4][i+8];
outjp1ic0 += 0.002856 * in[j+6][i];
outjp1ic0 += 0.002856 * in[j+6][i+8];
outjp1ic0 += 0.002856 * in[j+9][i+3];
outjp1ic0 += 0.002856 * in[j+9][i+5];
outjp1ic0 += -0.00508225 * in[j+1][i+4];
outjp1ic0 += -0.00508225 * in[j+5][i+8];
outjp1ic0 += -0.00508225 * in[j+5][i];
outjp1ic0 += -0.00508225 * in[j+9][i+4];
outjp1ic0 += 0.00064516 * in[j+2][i+1];
outjp1ic0 += 0.00064516 * in[j+2][i+7];
outjp1ic0 += 0.00064516 * in[j+8][i+1];
outjp1ic0 += 0.00064516 * in[j+8][i+7];
outjp1ic0 += -0.00508 * in[j+2][i+2];
outjp1ic0 += -0.00508 * in[j+2][i+6];
outjp1ic0 += -0.00508 * in[j+3][i+1];
outjp1ic0 += -0.00508 * in[j+3][i+7];
outjp1ic0 += -0.00508 * in[j+7][i+1];
outjp1ic0 += -0.00508 * in[j+7][i+7];
outjp1ic0 += -0.00508 * in[j+8][i+2];
outjp1ic0 += -0.00508 * in[j+8][i+6];
outjp1ic0 += 0.04064 * in[j+2][i+3];
outjp1ic0 += 0.04064 * in[j+2][i+5];
outjp1ic0 += 0.04064 * in[j+4][i+1];
outjp1ic0 += 0.04064 * in[j+4][i+7];
outjp1ic0 += 0.04064 * in[j+6][i+1];
outjp1ic0 += 0.04064 * in[j+6][i+7];
outjp1ic0 += 0.04064 * in[j+8][i+3];
outjp1ic0 += 0.04064 * in[j+8][i+5];
outjp1ic0 += -0.0723189 * in[j+2][i+4];
outjp1ic0 += -0.0723189 * in[j+5][i+1];
outjp1ic0 += -0.0723189 * in[j+5][i+7];
outjp1ic0 += -0.0723189 * in[j+8][i+4];
outjp1ic0 += 0.04 * in[j+3][i+2];
outjp1ic0 += 0.04 * in[j+3][i+6];
outjp1ic0 += 0.04 * in[j+7][i+2];
outjp1ic0 += 0.04 * in[j+7][i+6];
outjp1ic0 += -0.32 * in[j+3][i+3];
outjp1ic0 += -0.32 * in[j+3][i+5];
outjp1ic0 += -0.32 * in[j+4][i+2];
outjp1ic0 += -0.32 * in[j+4][i+6];
outjp1ic0 += -0.32 * in[j+6][i+2];
outjp1ic0 += -0.32 * in[j+6][i+6];
outjp1ic0 += -0.32 * in[j+7][i+3];
outjp1ic0 += -0.32 * in[j+7][i+5];
outjp1ic0 += 0.56944 * in[j+3][i+4];
outjp1ic0 += 0.56944 * in[j+5][i+2];
outjp1ic0 += 0.56944 * in[j+5][i+6];
outjp1ic0 += 0.56944 * in[j+7][i+4];
outjp1ic0 += 2.56 * in[j+4][i+3];
outjp1ic0 += 2.56 * in[j+4][i+5];
outjp1ic0 += 2.56 * in[j+6][i+3];
outjp1ic0 += 2.56 * in[j+6][i+5];
outjp1ic0 += -4.55552 * in[j+4][i+4];
outjp1ic0 += -4.55552 * in[j+5][i+3];
outjp1ic0 += -4.55552 * in[j+5][i+5];
outjp1ic0 += -4.55552 * in[j+6][i+4];
outjp1ic0 += in[j+5][i+4] * 8.10655;
out[j+1][i] = outjp1ic0;
outjp2ic0 = 3.18622 * in[j+2][i];
outjp2ic0 += 3.18622 * in[j+2][i+8];
outjp2ic0 += 3.18622 * in[j+10][i];
outjp2ic0 += 3.18622 * in[j+10][i+8];
outjp2ic0 += 4.5339 * in[j+2][i+1];
outjp2ic0 += 4.5339 * in[j+2][i+7];
outjp2ic0 += 4.5339 * in[j+3][i];
outjp2ic0 += 4.5339 * in[j+3][i+8];
outjp2ic0 += 4.5339 * in[j+9][i];
outjp2ic0 += 4.5339 * in[j+9][i+8];
outjp2ic0 += 4.5339 * in[j+10][i+1];
outjp2ic0 += 4.5339 * in[j+10][i+7];
outjp2ic0 += -0.000357 * in[j+2][i+2];
outjp2ic0 += -0.000357 * in[j+2][i+6];
outjp2ic0 += -0.000357 * in[j+4][i];
outjp2ic0 += -0.000357 * in[j+4][i+8];
outjp2ic0 += -0.000357 * in[j+8][i];
outjp2ic0 += -0.000357 * in[j+8][i+8];
outjp2ic0 += -0.000357 * in[j+10][i+2];
outjp2ic0 += -0.000357 * in[j+10][i+6];
outjp2ic0 += 0.002856 * in[j+2][i+3];
outjp2ic0 += 0.002856 * in[j+2][i+5];
outjp2ic0 += 0.002856 * in[j+5][i];
outjp2ic0 += 0.002856 * in[j+5][i+8];
outjp2ic0 += 0.002856 * in[j+7][i];
outjp2ic0 += 0.002856 * in[j+7][i+8];
outjp2ic0 += 0.002856 * in[j+10][i+3];
outjp2ic0 += 0.002856 * in[j+10][i+5];
outjp2ic0 += -0.00508225 * in[j+2][i+4];
outjp2ic0 += -0.00508225 * in[j+6][i+8];
outjp2ic0 += -0.00508225 * in[j+6][i];
outjp2ic0 += -0.00508225 * in[j+10][i+4];
outjp2ic0 += 0.00064516 * in[j+3][i+1];
outjp2ic0 += 0.00064516 * in[j+3][i+7];
outjp2ic0 += 0.00064516 * in[j+9][i+1];
outjp2ic0 += 0.00064516 * in[j+9][i+7];
outjp2ic0 += -0.00508 * in[j+3][i+2];
outjp2ic0 += -0.00508 * in[j+3][i+6];
outjp2ic0 += -0.00508 * in[j+4][i+1];
outjp2ic0 += -0.00508 * in[j+4][i+7];
outjp2ic0 += -0.00508 * in[j+8][i+1];
outjp2ic0 += -0.00508 * in[j+8][i+7];
outjp2ic0 += -0.00508 * in[j+9][i+2];
outjp2ic0 += -0.00508 * in[j+9][i+6];
outjp2ic0 += 0.04064 * in[j+3][i+3];
outjp2ic0 += 0.04064 * in[j+3][i+5];
outjp2ic0 += 0.04064 * in[j+5][i+1];
outjp2ic0 += 0.04064 * in[j+5][i+7];
outjp2ic0 += 0.04064 * in[j+7][i+1];
outjp2ic0 += 0.04064 * in[j+7][i+7];
outjp2ic0 += 0.04064 * in[j+9][i+3];
outjp2ic0 += 0.04064 * in[j+9][i+5];
outjp2ic0 += -0.0723189 * in[j+3][i+4];
outjp2ic0 += -0.0723189 * in[j+6][i+1];
outjp2ic0 += -0.0723189 * in[j+6][i+7];
outjp2ic0 += -0.0723189 * in[j+9][i+4];
outjp2ic0 += 0.04 * in[j+4][i+2];
outjp2ic0 += 0.04 * in[j+4][i+6];
outjp2ic0 += 0.04 * in[j+8][i+2];
outjp2ic0 += 0.04 * in[j+8][i+6];
outjp2ic0 += -0.32 * in[j+4][i+3];
outjp2ic0 += -0.32 * in[j+4][i+5];
outjp2ic0 += -0.32 * in[j+5][i+2];
outjp2ic0 += -0.32 * in[j+5][i+6];
outjp2ic0 += -0.32 * in[j+7][i+2];
outjp2ic0 += -0.32 * in[j+7][i+6];
outjp2ic0 += -0.32 * in[j+8][i+3];
outjp2ic0 += -0.32 * in[j+8][i+5];
outjp2ic0 += 0.56944 * in[j+4][i+4];
outjp2ic0 += 0.56944 * in[j+6][i+2];
outjp2ic0 += 0.56944 * in[j+6][i+6];
outjp2ic0 += 0.56944 * in[j+8][i+4];
outjp2ic0 += 2.56 * in[j+5][i+3];
outjp2ic0 += 2.56 * in[j+5][i+5];
outjp2ic0 += 2.56 * in[j+7][i+3];
outjp2ic0 += 2.56 * in[j+7][i+5];
outjp2ic0 += -4.55552 * in[j+5][i+4];
outjp2ic0 += -4.55552 * in[j+6][i+3];
outjp2ic0 += -4.55552 * in[j+6][i+5];
outjp2ic0 += -4.55552 * in[j+7][i+4];
outjp2ic0 += in[j+6][i+4] * 8.10655;
out[j+2][i] = outjp2ic0;
outjp3ic0 = 3.18622 * in[j+3][i];
outjp3ic0 += 3.18622 * in[j+3][i+8];
outjp3ic0 += 3.18622 * in[j+11][i];
outjp3ic0 += 3.18622 * in[j+11][i+8];
outjp3ic0 += 4.5339 * in[j+3][i+1];
outjp3ic0 += 4.5339 * in[j+3][i+7];
outjp3ic0 += 4.5339 * in[j+4][i];
outjp3ic0 += 4.5339 * in[j+4][i+8];
outjp3ic0 += 4.5339 * in[j+10][i];
outjp3ic0 += 4.5339 * in[j+10][i+8];
outjp3ic0 += 4.5339 * in[j+11][i+1];
outjp3ic0 += 4.5339 * in[j+11][i+7];
outjp3ic0 += -0.000357 * in[j+3][i+2];
outjp3ic0 += -0.000357 * in[j+3][i+6];
outjp3ic0 += -0.000357 * in[j+5][i];
outjp3ic0 += -0.000357 * in[j+5][i+8];
outjp3ic0 += -0.000357 * in[j+9][i];
outjp3ic0 += -0.000357 * in[j+9][i+8];
outjp3ic0 += -0.000357 * in[j+11][i+2];
outjp3ic0 += -0.000357 * in[j+11][i+6];
outjp3ic0 += 0.002856 * in[j+3][i+3];
outjp3ic0 += 0.002856 * in[j+3][i+5];
outjp3ic0 += 0.002856 * in[j+6][i];
outjp3ic0 += 0.002856 * in[j+6][i+8];
outjp3ic0 += 0.002856 * in[j+8][i];
outjp3ic0 += 0.002856 * in[j+8][i+8];
outjp3ic0 += 0.002856 * in[j+11][i+3];
outjp3ic0 += 0.002856 * in[j+11][i+5];
outjp3ic0 += -0.00508225 * in[j+3][i+4];
outjp3ic0 += -0.00508225 * in[j+7][i+8];
outjp3ic0 += -0.00508225 * in[j+7][i];
outjp3ic0 += -0.00508225 * in[j+11][i+4];
outjp3ic0 += 0.00064516 * in[j+4][i+1];
outjp3ic0 += 0.00064516 * in[j+4][i+7];
outjp3ic0 += 0.00064516 * in[j+10][i+1];
outjp3ic0 += 0.00064516 * in[j+10][i+7];
outjp3ic0 += -0.00508 * in[j+4][i+2];
outjp3ic0 += -0.00508 * in[j+4][i+6];
outjp3ic0 += -0.00508 * in[j+5][i+1];
outjp3ic0 += -0.00508 * in[j+5][i+7];
outjp3ic0 += -0.00508 * in[j+9][i+1];
outjp3ic0 += -0.00508 * in[j+9][i+7];
outjp3ic0 += -0.00508 * in[j+10][i+2];
outjp3ic0 += -0.00508 * in[j+10][i+6];
outjp3ic0 += 0.04064 * in[j+4][i+3];
outjp3ic0 += 0.04064 * in[j+4][i+5];
outjp3ic0 += 0.04064 * in[j+6][i+1];
outjp3ic0 += 0.04064 * in[j+6][i+7];
outjp3ic0 += 0.04064 * in[j+8][i+1];
outjp3ic0 += 0.04064 * in[j+8][i+7];
outjp3ic0 += 0.04064 * in[j+10][i+3];
outjp3ic0 += 0.04064 * in[j+10][i+5];
outjp3ic0 += -0.0723189 * in[j+4][i+4];
outjp3ic0 += -0.0723189 * in[j+7][i+1];
outjp3ic0 += -0.0723189 * in[j+7][i+7];
outjp3ic0 += -0.0723189 * in[j+10][i+4];
outjp3ic0 += 0.04 * in[j+5][i+2];
outjp3ic0 += 0.04 * in[j+5][i+6];
outjp3ic0 += 0.04 * in[j+9][i+2];
outjp3ic0 += 0.04 * in[j+9][i+6];
outjp3ic0 += -0.32 * in[j+5][i+3];
outjp3ic0 += -0.32 * in[j+5][i+5];
outjp3ic0 += -0.32 * in[j+6][i+2];
outjp3ic0 += -0.32 * in[j+6][i+6];
outjp3ic0 += -0.32 * in[j+8][i+2];
outjp3ic0 += -0.32 * in[j+8][i+6];
outjp3ic0 += -0.32 * in[j+9][i+3];
outjp3ic0 += -0.32 * in[j+9][i+5];
outjp3ic0 += 0.56944 * in[j+5][i+4];
outjp3ic0 += 0.56944 * in[j+7][i+2];
outjp3ic0 += 0.56944 * in[j+7][i+6];
outjp3ic0 += 0.56944 * in[j+9][i+4];
outjp3ic0 += 2.56 * in[j+6][i+3];
outjp3ic0 += 2.56 * in[j+6][i+5];
outjp3ic0 += 2.56 * in[j+8][i+3];
outjp3ic0 += 2.56 * in[j+8][i+5];
outjp3ic0 += -4.55552 * in[j+6][i+4];
outjp3ic0 += -4.55552 * in[j+7][i+3];
outjp3ic0 += -4.55552 * in[j+7][i+5];
outjp3ic0 += -4.55552 * in[j+8][i+4];
outjp3ic0 += in[j+7][i+4] * 8.10655;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
hipMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
double *out;
hipMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
hipFree (in);
hipFree (out);
} | .text
.file "reordered-d.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__j2d81ptPdS_i # -- Begin function _Z22__device_stub__j2d81ptPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__j2d81ptPdS_i,@function
_Z22__device_stub__j2d81ptPdS_i: # @_Z22__device_stub__j2d81ptPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__j2d81ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d81ptPdS_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
imulq %rbx, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit23
movl %ebp, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %bpl
cmovel %eax, %ecx
movl %ebp, %eax
shrl $5, %eax
leal 1(%rax), %edi
testb $31, %bpl
cmovel %eax, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7j2d81ptPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z7j2d81ptPdS_i,@object # @_Z7j2d81ptPdS_i
.section .rodata,"a",@progbits
.globl _Z7j2d81ptPdS_i
.p2align 3, 0x0
_Z7j2d81ptPdS_i:
.quad _Z22__device_stub__j2d81ptPdS_i
.size _Z7j2d81ptPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for in\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for out\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7j2d81ptPdS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__j2d81ptPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7j2d81ptPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001513c6_00000000-6_reordered-d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.type _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d81ptPdS_iPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7j2d81ptPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.globl _Z7j2d81ptPdS_i
.type _Z7j2d81ptPdS_i, @function
_Z7j2d81ptPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7j2d81ptPdS_i, .-_Z7j2d81ptPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for in\n"
.align 8
.LC2:
.string "Failed to allocate device memory for out\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, 24(%rsp)
testb $31, %bpl
jne .L16
movl %ebp, %eax
shrl $5, %eax
.L17:
movl %ebp, %edx
shrl $4, %edx
.L19:
movl %edx, 28(%rsp)
movl %eax, 32(%rsp)
movl $16, 16(%rsp)
movl $8, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %eax
shrl $5, %eax
addl $1, %eax
testb $15, %bpl
je .L17
movl %ebp, %edx
shrl $4, %edx
addl $1, %edx
jmp .L19
.L23:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC3:
.string "_Z7j2d81ptPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7j2d81ptPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reordered-d.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__j2d81ptPdS_i # -- Begin function _Z22__device_stub__j2d81ptPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__j2d81ptPdS_i,@function
_Z22__device_stub__j2d81ptPdS_i: # @_Z22__device_stub__j2d81ptPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__j2d81ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d81ptPdS_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
imulq %rbx, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit23
movl %ebp, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %bpl
cmovel %eax, %ecx
movl %ebp, %eax
shrl $5, %eax
leal 1(%rax), %edi
testb $31, %bpl
cmovel %eax, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7j2d81ptPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z7j2d81ptPdS_i,@object # @_Z7j2d81ptPdS_i
.section .rodata,"a",@progbits
.globl _Z7j2d81ptPdS_i
.p2align 3, 0x0
_Z7j2d81ptPdS_i:
.quad _Z22__device_stub__j2d81ptPdS_i
.size _Z7j2d81ptPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for in\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for out\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7j2d81ptPdS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__j2d81ptPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7j2d81ptPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float sigmoid(float x) {
return 1.0f / (1 + __expf(-x));
}
__global__ void updateBiasKernel_sigmoid(float* dZ, float* b, int cols, int row, float learning_rate){
int bid = blockIdx.x;
extern __shared__ float _share[];
//float * _max = _share;
float * _sum = _share;
float* sp = dZ + cols * bid;
_sum[threadIdx.x] = 0.0;
for(int id = threadIdx.x ; id < cols; id += blockDim.x){
// int id = tid + threadIdx.x;
//if(id < cols){
_sum[threadIdx.x] += sp[id];
//}
}
__syncthreads();
int len = blockDim.x;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
b[bid] -= learning_rate * (_sum[0]/cols);
} | code for sm_80
Function : _Z24updateBiasKernel_sigmoidPfS_iif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ STS [R10.X4], RZ ; /* 0x000000ff0a007388 */
/* 0x0011e20000004800 */
/*0060*/ ISETP.GE.AND P0, PT, R10.reuse, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x040fe20003f06270 */
/*0070*/ IMAD.SHL.U32 R4, R10, 0x4, RZ ; /* 0x000000040a047824 */
/* 0x000fd800078e00ff */
/*0080*/ @P0 BRA 0x190 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x180 ; /* 0x000000e000017945 */
/* 0x003fe20003800000 */
/*00a0*/ IMAD R5, R0, c[0x0][0x170], RZ ; /* 0x00005c0000057a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fca00078e000a */
/*00d0*/ SHF.R.S32.HI R2, RZ, 0x1f, R8 ; /* 0x0000001fff027819 */
/* 0x000fe40000011408 */
/*00e0*/ IADD3 R3, P0, R5, R8, RZ ; /* 0x0000000805037210 */
/* 0x000fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R12, R5, R2, 0x1, P0 ; /* 0x00000002050c7211 */
/* 0x000fe400000f0eff */
/*0100*/ LEA R2, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R3, R3, c[0x0][0x164], R12, 0x2, P0 ; /* 0x0000590003037a11 */
/* 0x000fcc00000f140c */
/*0120*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe20003f06270 */
/*0150*/ FADD R6, R3, R6 ; /* 0x0000000603067221 */
/* 0x004fd80000000000 */
/*0160*/ @!P0 BRA 0xd0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ STS [R10.X4], R6 ; /* 0x000000060a007388 */
/* 0x0001e40000004800 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*01c0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05270 */
/*01d0*/ @!P0 BRA 0x2d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fca00078e00ff */
/*01f0*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fe20000011402 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f06070 */
/*0220*/ @!P0 LEA R3, R2.reuse, 0x2, 0x1 ; /* 0x0000000202038811 */
/* 0x040fe400078e08ff */
/*0230*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P0 LOP3.LUT R3, R3, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc03038812 */
/* 0x000fe400078ec0ff */
/*0250*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0260*/ @!P0 LDS R5, [R10.X4] ; /* 0x000000000a058984 */
/* 0x000fe40000004800 */
/*0270*/ @!P0 IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104038824 */
/* 0x000fca00078e0203 */
/*0280*/ @!P0 LDS R6, [R3] ; /* 0x0000000003068984 */
/* 0x000e240000000800 */
/*0290*/ @!P0 FADD R5, R5, R6 ; /* 0x0000000605058221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P0 STS [R10.X4], R5 ; /* 0x000000050a008388 */
/* 0x0001e20000004800 */
/*02b0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05270 */
/*02c0*/ @P0 BRA 0x1f0 ; /* 0xffffff2000000947 */
/* 0x001fea000383ffff */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ I2F R3, c[0x0][0x170] ; /* 0x00005c0000037b06 */
/* 0x000e300000201400 */
/*02f0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e220000001000 */
/*0300*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000800 */
/*0310*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*0320*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fe40000000002 */
/*0330*/ FCHK P0, R4, R3 ; /* 0x0000000304007302 */
/* 0x002e240000000000 */
/*0340*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*0350*/ FFMA R6, -R3, R2, R4 ; /* 0x0000000203067223 */
/* 0x000fc80000000104 */
/*0360*/ FFMA R5, R5, R6, R2 ; /* 0x0000000605057223 */
/* 0x000fe20000000002 */
/*0370*/ @!P0 BRA 0x3a0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0380*/ MOV R2, 0x3a0 ; /* 0x000003a000027802 */
/* 0x000fe40000000f00 */
/*0390*/ CALL.REL.NOINC 0x400 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*03a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*03c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R5, -R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a23 */
/* 0x004fca0000000100 */
/*03e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ SHF.R.U32.HI R6, RZ, 0x17, R3.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011603 */
/*0410*/ IMAD.MOV.U32 R7, RZ, RZ, R4.reuse ; /* 0x000000ffff077224 */
/* 0x100fe200078e0004 */
/*0420*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fe20000011604 */
/*0430*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0440*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0450*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0460*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0480*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0490*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*04a0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*04b0*/ @!P0 BRA 0x630 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*04d0*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*04e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*04f0*/ @P0 BRA 0xa10 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0500*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0510*/ @!P0 BRA 0x9f0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0520*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0530*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0540*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0550*/ @!P1 BRA !P2, 0x9f0 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0560*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0570*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0580*/ @P1 BRA 0x9d0 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0590*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*05a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*05b0*/ @P0 BRA 0x9a0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*05d0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*05e0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*05f0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0600*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0610*/ @!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003089823 */
/* 0x000fe200000000ff */
/*0620*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0630*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe400078eb8ff */
/*0640*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0650*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0660*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0670*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0680*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0690*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*06a0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*06b0*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*06c0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*06d0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*06e0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*06f0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0700*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*0710*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0720*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0730*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0740*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0750*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0770*/ @!P0 BRA 0x980 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0790*/ @P0 BRA 0x950 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*07b0*/ @P0 BRA 0xa20 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*07d0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*07e0*/ @!P0 BRA 0xa20 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*07f0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0800*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0810*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0820*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0830*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0840*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0850*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0860*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0870*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0880*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0890*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*08a0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*08b0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*08c0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*08d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*08e0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*08f0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0900*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0910*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0920*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0930*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0940*/ BRA 0xa20 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0960*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0970*/ BRA 0xa20 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0980*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe200078e0203 */
/*0990*/ BRA 0xa20 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09a0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*09b0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*09c0*/ BRA 0xa20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*09e0*/ BRA 0xa20 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09f0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ FADD.FTZ R3, R4, R3 ; /* 0x0000000304037221 */
/* 0x000fc80000010000 */
/*0a20*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0a30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0a40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff5b002007950 */
/* 0x000fea0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float sigmoid(float x) {
return 1.0f / (1 + __expf(-x));
}
__global__ void updateBiasKernel_sigmoid(float* dZ, float* b, int cols, int row, float learning_rate){
int bid = blockIdx.x;
extern __shared__ float _share[];
//float * _max = _share;
float * _sum = _share;
float* sp = dZ + cols * bid;
_sum[threadIdx.x] = 0.0;
for(int id = threadIdx.x ; id < cols; id += blockDim.x){
// int id = tid + threadIdx.x;
//if(id < cols){
_sum[threadIdx.x] += sp[id];
//}
}
__syncthreads();
int len = blockDim.x;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
b[bid] -= learning_rate * (_sum[0]/cols);
} | .file "tmpxft_0012c702_00000000-6_updateBiasKernel_sigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidf
.type _Z7sigmoidf, @function
_Z7sigmoidf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7sigmoidf, .-_Z7sigmoidf
.globl _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif
.type _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif, @function
_Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24updateBiasKernel_sigmoidPfS_iif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif, .-_Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif
.globl _Z24updateBiasKernel_sigmoidPfS_iif
.type _Z24updateBiasKernel_sigmoidPfS_iif, @function
_Z24updateBiasKernel_sigmoidPfS_iif:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z24updateBiasKernel_sigmoidPfS_iif, .-_Z24updateBiasKernel_sigmoidPfS_iif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24updateBiasKernel_sigmoidPfS_iif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24updateBiasKernel_sigmoidPfS_iif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float sigmoid(float x) {
return 1.0f / (1 + __expf(-x));
}
__global__ void updateBiasKernel_sigmoid(float* dZ, float* b, int cols, int row, float learning_rate){
int bid = blockIdx.x;
extern __shared__ float _share[];
//float * _max = _share;
float * _sum = _share;
float* sp = dZ + cols * bid;
_sum[threadIdx.x] = 0.0;
for(int id = threadIdx.x ; id < cols; id += blockDim.x){
// int id = tid + threadIdx.x;
//if(id < cols){
_sum[threadIdx.x] += sp[id];
//}
}
__syncthreads();
int len = blockDim.x;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
b[bid] -= learning_rate * (_sum[0]/cols);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float sigmoid(float x) {
return 1.0f / (1 + __expf(-x));
}
__global__ void updateBiasKernel_sigmoid(float* dZ, float* b, int cols, int row, float learning_rate){
int bid = blockIdx.x;
extern __shared__ float _share[];
//float * _max = _share;
float * _sum = _share;
float* sp = dZ + cols * bid;
_sum[threadIdx.x] = 0.0;
for(int id = threadIdx.x ; id < cols; id += blockDim.x){
// int id = tid + threadIdx.x;
//if(id < cols){
_sum[threadIdx.x] += sp[id];
//}
}
__syncthreads();
int len = blockDim.x;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
b[bid] -= learning_rate * (_sum[0]/cols);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float sigmoid(float x) {
return 1.0f / (1 + __expf(-x));
}
__global__ void updateBiasKernel_sigmoid(float* dZ, float* b, int cols, int row, float learning_rate){
int bid = blockIdx.x;
extern __shared__ float _share[];
//float * _max = _share;
float * _sum = _share;
float* sp = dZ + cols * bid;
_sum[threadIdx.x] = 0.0;
for(int id = threadIdx.x ; id < cols; id += blockDim.x){
// int id = tid + threadIdx.x;
//if(id < cols){
_sum[threadIdx.x] += sp[id];
//}
}
__syncthreads();
int len = blockDim.x;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
b[bid] -= learning_rate * (_sum[0]/cols);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24updateBiasKernel_sigmoidPfS_iif
.globl _Z24updateBiasKernel_sigmoidPfS_iif
.p2align 8
.type _Z24updateBiasKernel_sigmoidPfS_iif,@function
_Z24updateBiasKernel_sigmoidPfS_iif:
s_load_b32 s4, s[0:1], 0x10
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, s15
s_mov_b32 s5, 0
s_mov_b32 s3, exec_lo
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x2c
ds_load_b32 v4, v3
s_mul_i32 s8, s2, s4
v_mov_b32_e32 v1, v0
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_and_b32 s8, s10, 0xffff
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v4, v2, v4 :: v_dual_add_nc_u32 v1, s8, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
ds_store_b32 v3, v4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s5, s3, 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_9
v_lshl_add_u32 v1, v0, 2, 0
s_and_b32 s3, 0xffff, s3
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lg_u32 s3, 1
s_cbranch_scc0 .LBB0_9
.LBB0_7:
s_lshr_b32 s5, s3, 1
s_add_i32 s3, s3, 1
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_lshr_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, s3, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
ds_store_b32 v3, v2
s_branch .LBB0_6
.LBB0_9:
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2
v_cvt_f32_i32_e32 v3, s4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_dual_mov_b32 v0, 0 :: v_dual_fmac_f32 v5, v6, v5
global_load_b32 v1, v0, s[0:1]
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v2, v4, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v1, -v2, s5, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24updateBiasKernel_sigmoidPfS_iif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24updateBiasKernel_sigmoidPfS_iif, .Lfunc_end0-_Z24updateBiasKernel_sigmoidPfS_iif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24updateBiasKernel_sigmoidPfS_iif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24updateBiasKernel_sigmoidPfS_iif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float sigmoid(float x) {
return 1.0f / (1 + __expf(-x));
}
__global__ void updateBiasKernel_sigmoid(float* dZ, float* b, int cols, int row, float learning_rate){
int bid = blockIdx.x;
extern __shared__ float _share[];
//float * _max = _share;
float * _sum = _share;
float* sp = dZ + cols * bid;
_sum[threadIdx.x] = 0.0;
for(int id = threadIdx.x ; id < cols; id += blockDim.x){
// int id = tid + threadIdx.x;
//if(id < cols){
_sum[threadIdx.x] += sp[id];
//}
}
__syncthreads();
int len = blockDim.x;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
b[bid] -= learning_rate * (_sum[0]/cols);
} | .text
.file "updateBiasKernel_sigmoid.hip"
.globl _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif # -- Begin function _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.p2align 4, 0x90
.type _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif,@function
_Z39__device_stub__updateBiasKernel_sigmoidPfS_iif: # @_Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24updateBiasKernel_sigmoidPfS_iif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif, .Lfunc_end0-_Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24updateBiasKernel_sigmoidPfS_iif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24updateBiasKernel_sigmoidPfS_iif,@object # @_Z24updateBiasKernel_sigmoidPfS_iif
.section .rodata,"a",@progbits
.globl _Z24updateBiasKernel_sigmoidPfS_iif
.p2align 3, 0x0
_Z24updateBiasKernel_sigmoidPfS_iif:
.quad _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.size _Z24updateBiasKernel_sigmoidPfS_iif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24updateBiasKernel_sigmoidPfS_iif"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24updateBiasKernel_sigmoidPfS_iif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24updateBiasKernel_sigmoidPfS_iif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ STS [R10.X4], RZ ; /* 0x000000ff0a007388 */
/* 0x0011e20000004800 */
/*0060*/ ISETP.GE.AND P0, PT, R10.reuse, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x040fe20003f06270 */
/*0070*/ IMAD.SHL.U32 R4, R10, 0x4, RZ ; /* 0x000000040a047824 */
/* 0x000fd800078e00ff */
/*0080*/ @P0 BRA 0x190 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x180 ; /* 0x000000e000017945 */
/* 0x003fe20003800000 */
/*00a0*/ IMAD R5, R0, c[0x0][0x170], RZ ; /* 0x00005c0000057a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fca00078e000a */
/*00d0*/ SHF.R.S32.HI R2, RZ, 0x1f, R8 ; /* 0x0000001fff027819 */
/* 0x000fe40000011408 */
/*00e0*/ IADD3 R3, P0, R5, R8, RZ ; /* 0x0000000805037210 */
/* 0x000fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R12, R5, R2, 0x1, P0 ; /* 0x00000002050c7211 */
/* 0x000fe400000f0eff */
/*0100*/ LEA R2, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R3, R3, c[0x0][0x164], R12, 0x2, P0 ; /* 0x0000590003037a11 */
/* 0x000fcc00000f140c */
/*0120*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe20003f06270 */
/*0150*/ FADD R6, R3, R6 ; /* 0x0000000603067221 */
/* 0x004fd80000000000 */
/*0160*/ @!P0 BRA 0xd0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ STS [R10.X4], R6 ; /* 0x000000060a007388 */
/* 0x0001e40000004800 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*01c0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05270 */
/*01d0*/ @!P0 BRA 0x2d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fca00078e00ff */
/*01f0*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fe20000011402 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f06070 */
/*0220*/ @!P0 LEA R3, R2.reuse, 0x2, 0x1 ; /* 0x0000000202038811 */
/* 0x040fe400078e08ff */
/*0230*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P0 LOP3.LUT R3, R3, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc03038812 */
/* 0x000fe400078ec0ff */
/*0250*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0260*/ @!P0 LDS R5, [R10.X4] ; /* 0x000000000a058984 */
/* 0x000fe40000004800 */
/*0270*/ @!P0 IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104038824 */
/* 0x000fca00078e0203 */
/*0280*/ @!P0 LDS R6, [R3] ; /* 0x0000000003068984 */
/* 0x000e240000000800 */
/*0290*/ @!P0 FADD R5, R5, R6 ; /* 0x0000000605058221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P0 STS [R10.X4], R5 ; /* 0x000000050a008388 */
/* 0x0001e20000004800 */
/*02b0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05270 */
/*02c0*/ @P0 BRA 0x1f0 ; /* 0xffffff2000000947 */
/* 0x001fea000383ffff */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ I2F R3, c[0x0][0x170] ; /* 0x00005c0000037b06 */
/* 0x000e300000201400 */
/*02f0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e220000001000 */
/*0300*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000800 */
/*0310*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*0320*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fe40000000002 */
/*0330*/ FCHK P0, R4, R3 ; /* 0x0000000304007302 */
/* 0x002e240000000000 */
/*0340*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*0350*/ FFMA R6, -R3, R2, R4 ; /* 0x0000000203067223 */
/* 0x000fc80000000104 */
/*0360*/ FFMA R5, R5, R6, R2 ; /* 0x0000000605057223 */
/* 0x000fe20000000002 */
/*0370*/ @!P0 BRA 0x3a0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0380*/ MOV R2, 0x3a0 ; /* 0x000003a000027802 */
/* 0x000fe40000000f00 */
/*0390*/ CALL.REL.NOINC 0x400 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*03a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*03c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R5, -R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a23 */
/* 0x004fca0000000100 */
/*03e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ SHF.R.U32.HI R6, RZ, 0x17, R3.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011603 */
/*0410*/ IMAD.MOV.U32 R7, RZ, RZ, R4.reuse ; /* 0x000000ffff077224 */
/* 0x100fe200078e0004 */
/*0420*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fe20000011604 */
/*0430*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0440*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0450*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0460*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0480*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0490*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*04a0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*04b0*/ @!P0 BRA 0x630 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*04d0*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*04e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*04f0*/ @P0 BRA 0xa10 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0500*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0510*/ @!P0 BRA 0x9f0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0520*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0530*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0540*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0550*/ @!P1 BRA !P2, 0x9f0 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0560*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0570*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0580*/ @P1 BRA 0x9d0 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0590*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*05a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*05b0*/ @P0 BRA 0x9a0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*05d0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*05e0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*05f0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0600*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0610*/ @!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003089823 */
/* 0x000fe200000000ff */
/*0620*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0630*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe400078eb8ff */
/*0640*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0650*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0660*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0670*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0680*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0690*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*06a0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*06b0*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*06c0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*06d0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*06e0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*06f0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0700*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*0710*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0720*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0730*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0740*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0750*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0770*/ @!P0 BRA 0x980 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0790*/ @P0 BRA 0x950 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*07b0*/ @P0 BRA 0xa20 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*07d0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*07e0*/ @!P0 BRA 0xa20 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*07f0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0800*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0810*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0820*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0830*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0840*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0850*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0860*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0870*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0880*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0890*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*08a0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*08b0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*08c0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*08d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*08e0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*08f0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0900*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0910*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0920*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0930*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0940*/ BRA 0xa20 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0960*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0970*/ BRA 0xa20 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0980*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe200078e0203 */
/*0990*/ BRA 0xa20 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09a0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*09b0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*09c0*/ BRA 0xa20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*09e0*/ BRA 0xa20 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09f0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ FADD.FTZ R3, R4, R3 ; /* 0x0000000304037221 */
/* 0x000fc80000010000 */
/*0a20*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0a30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0a40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff5b002007950 */
/* 0x000fea0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24updateBiasKernel_sigmoidPfS_iif
.globl _Z24updateBiasKernel_sigmoidPfS_iif
.p2align 8
.type _Z24updateBiasKernel_sigmoidPfS_iif,@function
_Z24updateBiasKernel_sigmoidPfS_iif:
s_load_b32 s4, s[0:1], 0x10
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, s15
s_mov_b32 s5, 0
s_mov_b32 s3, exec_lo
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x2c
ds_load_b32 v4, v3
s_mul_i32 s8, s2, s4
v_mov_b32_e32 v1, v0
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_and_b32 s8, s10, 0xffff
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v4, v2, v4 :: v_dual_add_nc_u32 v1, s8, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
ds_store_b32 v3, v4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s5, s3, 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_9
v_lshl_add_u32 v1, v0, 2, 0
s_and_b32 s3, 0xffff, s3
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lg_u32 s3, 1
s_cbranch_scc0 .LBB0_9
.LBB0_7:
s_lshr_b32 s5, s3, 1
s_add_i32 s3, s3, 1
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_lshr_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, s3, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
ds_store_b32 v3, v2
s_branch .LBB0_6
.LBB0_9:
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2
v_cvt_f32_i32_e32 v3, s4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_dual_mov_b32 v0, 0 :: v_dual_fmac_f32 v5, v6, v5
global_load_b32 v1, v0, s[0:1]
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v2, v4, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v1, -v2, s5, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24updateBiasKernel_sigmoidPfS_iif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24updateBiasKernel_sigmoidPfS_iif, .Lfunc_end0-_Z24updateBiasKernel_sigmoidPfS_iif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24updateBiasKernel_sigmoidPfS_iif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24updateBiasKernel_sigmoidPfS_iif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c702_00000000-6_updateBiasKernel_sigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidf
.type _Z7sigmoidf, @function
_Z7sigmoidf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7sigmoidf, .-_Z7sigmoidf
.globl _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif
.type _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif, @function
_Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24updateBiasKernel_sigmoidPfS_iif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif, .-_Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif
.globl _Z24updateBiasKernel_sigmoidPfS_iif
.type _Z24updateBiasKernel_sigmoidPfS_iif, @function
_Z24updateBiasKernel_sigmoidPfS_iif:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24updateBiasKernel_sigmoidPfS_iifPfS_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z24updateBiasKernel_sigmoidPfS_iif, .-_Z24updateBiasKernel_sigmoidPfS_iif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24updateBiasKernel_sigmoidPfS_iif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24updateBiasKernel_sigmoidPfS_iif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "updateBiasKernel_sigmoid.hip"
.globl _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif # -- Begin function _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.p2align 4, 0x90
.type _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif,@function
_Z39__device_stub__updateBiasKernel_sigmoidPfS_iif: # @_Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24updateBiasKernel_sigmoidPfS_iif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif, .Lfunc_end0-_Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24updateBiasKernel_sigmoidPfS_iif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24updateBiasKernel_sigmoidPfS_iif,@object # @_Z24updateBiasKernel_sigmoidPfS_iif
.section .rodata,"a",@progbits
.globl _Z24updateBiasKernel_sigmoidPfS_iif
.p2align 3, 0x0
_Z24updateBiasKernel_sigmoidPfS_iif:
.quad _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.size _Z24updateBiasKernel_sigmoidPfS_iif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24updateBiasKernel_sigmoidPfS_iif"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__updateBiasKernel_sigmoidPfS_iif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24updateBiasKernel_sigmoidPfS_iif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void nmfcpy(double *mat, double *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if (row < m && col < n)
mat[row*n+col] = matcp[row*n+col];
} | code for sm_80
Function : _Z6nmfcpyPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0100*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void nmfcpy(double *mat, double *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if (row < m && col < n)
mat[row*n+col] = matcp[row*n+col];
} | .file "tmpxft_000de4a8_00000000-6_nmfcpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii
.type _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii, @function
_Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6nmfcpyPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii, .-_Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii
.globl _Z6nmfcpyPdS_ii
.type _Z6nmfcpyPdS_ii, @function
_Z6nmfcpyPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6nmfcpyPdS_ii, .-_Z6nmfcpyPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6nmfcpyPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6nmfcpyPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void nmfcpy(double *mat, double *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if (row < m && col < n)
mat[row*n+col] = matcp[row*n+col];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfcpy(double *mat, double *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if (row < m && col < n)
mat[row*n+col] = matcp[row*n+col];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfcpy(double *mat, double *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if (row < m && col < n)
mat[row*n+col] = matcp[row*n+col];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6nmfcpyPdS_ii
.globl _Z6nmfcpyPdS_ii
.p2align 8
.type _Z6nmfcpyPdS_ii,@function
_Z6nmfcpyPdS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6nmfcpyPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6nmfcpyPdS_ii, .Lfunc_end0-_Z6nmfcpyPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6nmfcpyPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6nmfcpyPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfcpy(double *mat, double *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if (row < m && col < n)
mat[row*n+col] = matcp[row*n+col];
} | .text
.file "nmfcpy.hip"
.globl _Z21__device_stub__nmfcpyPdS_ii # -- Begin function _Z21__device_stub__nmfcpyPdS_ii
.p2align 4, 0x90
.type _Z21__device_stub__nmfcpyPdS_ii,@function
_Z21__device_stub__nmfcpyPdS_ii: # @_Z21__device_stub__nmfcpyPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6nmfcpyPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__nmfcpyPdS_ii, .Lfunc_end0-_Z21__device_stub__nmfcpyPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6nmfcpyPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6nmfcpyPdS_ii,@object # @_Z6nmfcpyPdS_ii
.section .rodata,"a",@progbits
.globl _Z6nmfcpyPdS_ii
.p2align 3, 0x0
_Z6nmfcpyPdS_ii:
.quad _Z21__device_stub__nmfcpyPdS_ii
.size _Z6nmfcpyPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6nmfcpyPdS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__nmfcpyPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6nmfcpyPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6nmfcpyPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0100*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6nmfcpyPdS_ii
.globl _Z6nmfcpyPdS_ii
.p2align 8
.type _Z6nmfcpyPdS_ii,@function
_Z6nmfcpyPdS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6nmfcpyPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6nmfcpyPdS_ii, .Lfunc_end0-_Z6nmfcpyPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6nmfcpyPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6nmfcpyPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de4a8_00000000-6_nmfcpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii
.type _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii, @function
_Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6nmfcpyPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii, .-_Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii
.globl _Z6nmfcpyPdS_ii
.type _Z6nmfcpyPdS_ii, @function
_Z6nmfcpyPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6nmfcpyPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6nmfcpyPdS_ii, .-_Z6nmfcpyPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6nmfcpyPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6nmfcpyPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nmfcpy.hip"
.globl _Z21__device_stub__nmfcpyPdS_ii # -- Begin function _Z21__device_stub__nmfcpyPdS_ii
.p2align 4, 0x90
.type _Z21__device_stub__nmfcpyPdS_ii,@function
_Z21__device_stub__nmfcpyPdS_ii: # @_Z21__device_stub__nmfcpyPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6nmfcpyPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__nmfcpyPdS_ii, .Lfunc_end0-_Z21__device_stub__nmfcpyPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6nmfcpyPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6nmfcpyPdS_ii,@object # @_Z6nmfcpyPdS_ii
.section .rodata,"a",@progbits
.globl _Z6nmfcpyPdS_ii
.p2align 3, 0x0
_Z6nmfcpyPdS_ii:
.quad _Z21__device_stub__nmfcpyPdS_ii
.size _Z6nmfcpyPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6nmfcpyPdS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__nmfcpyPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6nmfcpyPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // to avoid highlight problems
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdlib.h> // imported for rand() which generates a number between 0 & RAND_MAX
#include <time.h> // imported for the time() function and also the clock function
#include <limits> // for a large value
#include <cmath> // for exponentiation
using namespace std;
__global__ void FindClosestPoint(float3 *points, int *closestPoint, const int numberPoints)
{
// used to identify the thread that is currently running
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// now find the closest point to each point
// 'i' represents the current point that we are finding the closest point to!
int distanceBetweenPoints = 9999999, tempDistance = 0;
for (int j = 0; j < numberPoints; j++)
if (idx != j) // dont check the distance between the point and itself
{
tempDistance = pow((points[idx].x - points[j].x), 2) + pow((points[idx].y - points[j].y), 2);
if (tempDistance < distanceBetweenPoints)
{
distanceBetweenPoints = tempDistance;
closestPoint[idx] = j;
}
}
}
int main()
{
srand(time(NULL)); // used to initialize the seed for the random number generator
const int numberPoints = 1000;
clock_t startTime, endTime;
float3 *points = new float3[numberPoints];
float3 *pointsDeviceCopy;
int *closestPointDevice, *closestPoint = new int[numberPoints];
// initialize the points with random numbers
for (int i = 0; i < numberPoints; i++)
{
points[i].x = rand() % 1000;
points[i].y = rand() % 1000;
points[i].z = rand() % 1000;
}
// print the points initialized
for (int i = 0; i < numberPoints; i++)
cout << points[i].x << "\t" << points[i].y << "\t" << points[i].z << endl;
cout << endl;
// initialize memory in the GPU for calculation
if (cudaMalloc(&pointsDeviceCopy, sizeof(float3) * numberPoints) != cudaSuccess)
{
cout << "Couldn't initialize memory in the GPU for pointsDeviceCopy" << endl;
delete[] points;
delete[] closestPoint;
return 0;
}
if (cudaMalloc(&closestPointDevice, sizeof(int) * numberPoints) != cudaSuccess)
{
cout << "Couldn't initialize memory in the GPU for closestPointDevice" << endl;
cudaFree(pointsDeviceCopy);
delete[] points;
delete[] closestPoint;
return 0;
}
if (cudaMemcpy(pointsDeviceCopy, points, sizeof(float3) * numberPoints, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "Could not copy points to pointsDeviceCopy" << endl;
cudaFree(pointsDeviceCopy);
cudaFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
// now find the distance between all points
startTime = clock();
// since a block can have upto 1024 elements, we can use a single block
FindClosestPoint<<<1, numberPoints>>>(pointsDeviceCopy, closestPointDevice, numberPoints);
if (cudaMemcpy(closestPoint, closestPointDevice, sizeof(int) * numberPoints, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "Could not get the output!";
cudaFree(pointsDeviceCopy);
cudaFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
endTime = clock() - startTime;
delete[] points;
delete[] closestPoint;
cudaFree(closestPointDevice);
cudaFree(pointsDeviceCopy);
cout << "Time it took was " << ((float)endTime / CLOCKS_PER_SEC) << endl;
return 0;
} | code for sm_80
Function : _Z16FindClosestPointP6float3Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0xc ; /* 0x0000000cff077424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0080*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fe400078e0204 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x98967f ; /* 0x0098967fff037424 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.MOV R0, RZ, RZ, -R4 ; /* 0x000000ffff007224 */
/* 0x000fca00078e0a04 */
/*00f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0100*/ BSSY B0, 0x5d0 ; /* 0x000004c000007945 */
/* 0x000fd80003800000 */
/*0110*/ @!P0 BRA 0x5c0 ; /* 0x000004a000008947 */
/* 0x001fea0003800000 */
/*0120*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x000ea2000c1e1900 */
/*0140*/ BSSY B1, 0x1d0 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*0150*/ MOV R34, 0x1c0 ; /* 0x000001c000227802 */
/* 0x000fe20000000f00 */
/*0160*/ FADD R12, -R12, R5 ; /* 0x000000050c0c7221 */
/* 0x004fc80000000100 */
/*0170*/ F2F.F64.F32 R10, R12 ; /* 0x0000000c000a7310 */
/* 0x000e240000201800 */
/*0180*/ DADD R14, -RZ, |R10| ; /* 0x00000000ff0e7229 */
/* 0x001e14000000050a */
/*0190*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x001fe400078e000e */
/*01a0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000f */
/*01b0*/ CALL.REL.NOINC 0x640 ; /* 0x0000048000007944 */
/* 0x000fea0003c00000 */
/*01c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01d0*/ DADD R14, R10, 2 ; /* 0x400000000a0e7429 */
/* 0x000ea20000000000 */
/*01e0*/ FSETP.NEU.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fe20003f0d000 */
/*01f0*/ BSSY B1, 0x310 ; /* 0x0000011000017945 */
/* 0x000ff00003800000 */
/*0200*/ LOP3.LUT R14, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f0e7812 */
/* 0x004fe200078ec0ff */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, R21 ; /* 0x000000ffff0f7224 */
/* 0x002fc600078e0015 */
/*0220*/ ISETP.NE.AND P1, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fe20003f25270 */
/*0230*/ IMAD.MOV.U32 R14, RZ, RZ, R20 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0014 */
/*0240*/ @!P0 CS2R R14, SRZ ; /* 0x00000000000e8805 */
/* 0x000fd6000001ff00 */
/*0250*/ @P1 BRA 0x300 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0260*/ DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e5c0003f0c200 */
/*0270*/ @P0 BRA 0x2f0 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0290*/ LOP3.LUT R10, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b0a7812 */
/* 0x000fc800078ec0ff */
/*02a0*/ ISETP.NE.OR P0, PT, R10, 0x7ff00000, P0 ; /* 0x7ff000000a00780c */
/* 0x000fda0000705670 */
/*02b0*/ @P0 BRA 0x300 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0f7424 */
/* 0x000fe200078e00ff */
/*02e0*/ BRA 0x300 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*02f0*/ DADD R14, R10, 2 ; /* 0x400000000a0e7429 */
/* 0x00028c0000000000 */
/*0300*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R5, [R8.64+0x4] ; /* 0x0000040408057981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R10, [R6.64+0x4] ; /* 0x00000404060a7981 */
/* 0x002ee2000c1e1900 */
/*0330*/ FSETP.NEU.AND P0, PT, R12, 1, PT ; /* 0x3f8000000c00780b */
/* 0x000fe20003f0d000 */
/*0340*/ BSSY B1, 0x3e0 ; /* 0x0000009000017945 */
/* 0x000fe20003800000 */
/*0350*/ MOV R34, 0x3d0 ; /* 0x000003d000227802 */
/* 0x000fc40000000f00 */
/*0360*/ FSEL R12, R14, RZ, P0 ; /* 0x000000ff0e0c7208 */
/* 0x004fe40000000000 */
/*0370*/ FSEL R13, R15, 1.875, P0 ; /* 0x3ff000000f0d7808 */
/* 0x000fe20000000000 */
/*0380*/ FADD R5, -R5, R10 ; /* 0x0000000a05057221 */
/* 0x008fc80000000100 */
/*0390*/ F2F.F64.F32 R10, R5 ; /* 0x00000005000a7310 */
/* 0x000e640000201800 */
/*03a0*/ DADD R16, -RZ, |R10| ; /* 0x00000000ff107229 */
/* 0x003e14000000050a */
/*03b0*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x001fe400078e0010 */
/*03c0*/ CALL.REL.NOINC 0x640 ; /* 0x0000027000007944 */
/* 0x000fea0003c00000 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ DADD R14, R10, 2 ; /* 0x400000000a0e7429 */
/* 0x000ea20000000000 */
/*03f0*/ FSETP.NEU.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fe20003f0d000 */
/*0400*/ BSSY B1, 0x520 ; /* 0x0000011000017945 */
/* 0x000ff00003800000 */
/*0410*/ LOP3.LUT R14, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f0e7812 */
/* 0x004fe200078ec0ff */
/*0420*/ IMAD.MOV.U32 R15, RZ, RZ, R21 ; /* 0x000000ffff0f7224 */
/* 0x002fc600078e0015 */
/*0430*/ ISETP.NE.AND P1, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fe20003f25270 */
/*0440*/ IMAD.MOV.U32 R14, RZ, RZ, R20 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0014 */
/*0450*/ @!P0 CS2R R14, SRZ ; /* 0x00000000000e8805 */
/* 0x000fd6000001ff00 */
/*0460*/ @P1 BRA 0x510 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0470*/ DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e5c0003f0c200 */
/*0480*/ @P0 BRA 0x500 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0490*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*04a0*/ LOP3.LUT R10, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b0a7812 */
/* 0x000fc800078ec0ff */
/*04b0*/ ISETP.NE.OR P0, PT, R10, 0x7ff00000, P0 ; /* 0x7ff000000a00780c */
/* 0x000fda0000705670 */
/*04c0*/ @P0 BRA 0x510 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*04e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0f7424 */
/* 0x000fe200078e00ff */
/*04f0*/ BRA 0x510 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0500*/ DADD R14, R10, 2 ; /* 0x400000000a0e7429 */
/* 0x00028c0000000000 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0520*/ FSETP.NEU.AND P0, PT, R5, 1, PT ; /* 0x3f8000000500780b */
/* 0x000fc80003f0d000 */
/*0530*/ FSEL R10, R14, RZ, P0 ; /* 0x000000ff0e0a7208 */
/* 0x006fe40000000000 */
/*0540*/ FSEL R11, R15, 1.875, P0 ; /* 0x3ff000000f0b7808 */
/* 0x000fcc0000000000 */
/*0550*/ DADD R12, R12, R10 ; /* 0x000000000c0c7229 */
/* 0x000e54000000000a */
/*0560*/ F2I.F64.TRUNC R12, R12 ; /* 0x0000000c000c7311 */
/* 0x002e64000030d100 */
/*0570*/ ISETP.GE.AND P0, PT, R12, R3, PT ; /* 0x000000030c00720c */
/* 0x002fda0003f06270 */
/*0580*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b8424 */
/* 0x000fe400078e00ff */
/*0590*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff038224 */
/* 0x000fe400078e000c */
/*05a0*/ @!P0 IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a8625 */
/* 0x000fca00078e020b */
/*05b0*/ @!P0 STG.E [R10.64], R2 ; /* 0x000000020a008986 */
/* 0x0003e4000c101904 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x002fe40007ffe0ff */
/*05e0*/ IADD3 R8, P1, R8, 0xc, RZ ; /* 0x0000000c08087810 */
/* 0x000fe40007f3e0ff */
/*05f0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06270 */
/*0600*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0620*/ @!P0 BRA 0xf0 ; /* 0xfffffac000008947 */
/* 0x000fea000383ffff */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ SHF.R.U32.HI R35, RZ, 0x14, R17.reuse ; /* 0x00000014ff237819 */
/* 0x100fe20000011611 */
/*0650*/ IMAD.MOV.U32 R14, RZ, RZ, R18 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0012 */
/*0660*/ IMAD.MOV.U32 R15, RZ, RZ, R17.reuse ; /* 0x000000ffff0f7224 */
/* 0x100fe200078e0011 */
/*0670*/ ISETP.NE.AND P0, PT, R35, RZ, PT ; /* 0x000000ff2300720c */
/* 0x000fe20003f05270 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, R17 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0011 */
/*0690*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff147424 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff157424 */
/* 0x000fcc00078e00ff */
/*06c0*/ @!P0 DMUL R14, R14, 1.80143985094819840000e+16 ; /* 0x435000000e0e8828 */
/* 0x000e140000000000 */
/*06d0*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, R15 ; /* 0x000000ffff108224 */
/* 0x001fe200078e000f */
/*06e0*/ @!P0 LEA.HI R35, R15, 0xffffffca, RZ, 0xc ; /* 0xffffffca0f238811 */
/* 0x000fe200078f60ff */
/*06f0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff128224 */
/* 0x000fe400078e000e */
/*0700*/ IMAD.MOV.U32 R15, RZ, RZ, 0x43300000 ; /* 0x43300000ff0f7424 */
/* 0x000fe200078e00ff */
/*0710*/ LOP3.LUT R16, R16, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff10107812 */
/* 0x000fe400078ec0ff */
/*0720*/ IADD3 R14, R35, -0x3ff, RZ ; /* 0xfffffc01230e7810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LOP3.LUT R19, R16, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000010137812 */
/* 0x000fc800078efcff */
/*0740*/ ISETP.GE.U32.AND P1, PT, R19, 0x3ff6a09f, PT ; /* 0x3ff6a09f1300780c */
/* 0x000fda0003f26070 */
/*0750*/ @P1 IADD3 R17, R19, -0x100000, RZ ; /* 0xfff0000013111810 */
/* 0x000fe40007ffe0ff */
/*0760*/ @P1 IADD3 R14, R35, -0x3fe, RZ ; /* 0xfffffc02230e1810 */
/* 0x000fc60007ffe0ff */
/*0770*/ @P1 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff131224 */
/* 0x000fe200078e0011 */
/*0780*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000e0e7812 */
/* 0x000fca00078e3cff */
/*0790*/ DADD R22, R18, 1 ; /* 0x3ff0000012167429 */
/* 0x000e080000000000 */
/*07a0*/ DADD R18, R18, -1 ; /* 0xbff0000012127429 */
/* 0x000fe40000000000 */
/*07b0*/ MUFU.RCP64H R25, R23 ; /* 0x0000001700197308 */
/* 0x001e240000001800 */
/*07c0*/ DFMA R16, -R22, R24, 1 ; /* 0x3ff000001610742b */
/* 0x001e0c0000000118 */
/*07d0*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*07e0*/ DFMA R24, R24, R16, R24 ; /* 0x000000101818722b */
/* 0x001e0c0000000018 */
/*07f0*/ DMUL R16, R24, R18 ; /* 0x0000001218107228 */
/* 0x001e0c0000000000 */
/*0800*/ DFMA R16, R24, R18, R16 ; /* 0x000000121810722b */
/* 0x001e0c0000000010 */
/*0810*/ DMUL R28, R16, R16 ; /* 0x00000010101c7228 */
/* 0x001e080000000000 */
/*0820*/ DMUL R26, R16, R16 ; /* 0x00000010101a7228 */
/* 0x000fc80000000000 */
/*0830*/ DFMA R20, R28, R20, c[0x2][0x0] ; /* 0x008000001c14762b */
/* 0x001e0c0000000014 */
/*0840*/ DFMA R22, R28, R20, c[0x2][0x8] ; /* 0x008002001c16762b */
/* 0x001e080000000014 */
/*0850*/ DADD R20, R18, -R16 ; /* 0x0000000012147229 */
/* 0x000e480000000810 */
/*0860*/ DFMA R22, R28, R22, c[0x2][0x10] ; /* 0x008004001c16762b */
/* 0x001e080000000016 */
/*0870*/ DADD R20, R20, R20 ; /* 0x0000000014147229 */
/* 0x002e480000000014 */
/*0880*/ DFMA R22, R28, R22, c[0x2][0x18] ; /* 0x008006001c16762b */
/* 0x001e080000000016 */
/*0890*/ DFMA R20, R18, -R16, R20 ; /* 0x800000101214722b */
/* 0x002e480000000014 */
/*08a0*/ DFMA R22, R28, R22, c[0x2][0x20] ; /* 0x008008001c16762b */
/* 0x001e080000000016 */
/*08b0*/ DMUL R20, R24, R20 ; /* 0x0000001418147228 */
/* 0x002fc80000000000 */
/*08c0*/ DFMA R22, R28, R22, c[0x2][0x28] ; /* 0x00800a001c16762b */
/* 0x001e0c0000000016 */
/*08d0*/ DFMA R18, R28, R22, c[0x2][0x30] ; /* 0x00800c001c12762b */
/* 0x001e220000000016 */
/*08e0*/ IADD3 R31, R21, 0x100000, RZ ; /* 0x00100000151f7810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R30, RZ, RZ, R20 ; /* 0x000000ffff1e7224 */
/* 0x000fc800078e0014 */
/*0900*/ DADD R24, -R18, c[0x2][0x30] ; /* 0x00800c0012187629 */
/* 0x001e0c0000000100 */
/*0910*/ DFMA R24, R28, R22, R24 ; /* 0x000000161c18722b */
/* 0x001e080000000018 */
/*0920*/ DFMA R28, R16, R16, -R26 ; /* 0x00000010101c722b */
/* 0x000e48000000081a */
/*0930*/ DMUL R22, R16, R26 ; /* 0x0000001a10167228 */
/* 0x000e880000000000 */
/*0940*/ DADD R24, RZ, R24 ; /* 0x00000000ff187229 */
/* 0x001e080000000018 */
/*0950*/ DFMA R30, R16, R30, R28 ; /* 0x0000001e101e722b */
/* 0x002fc8000000001c */
/*0960*/ DFMA R28, R16, R26, -R22 ; /* 0x0000001a101c722b */
/* 0x004e480000000816 */
/*0970*/ DADD R24, R24, c[0x2][0x38] ; /* 0x00800e0018187629 */
/* 0x001e080000000000 */
/*0980*/ DFMA R28, R20, R26, R28 ; /* 0x0000001a141c722b */
/* 0x002e48000000001c */
/*0990*/ DADD R26, R18, R24 ; /* 0x00000000121a7229 */
/* 0x001e080000000018 */
/*09a0*/ DFMA R28, R16, R30, R28 ; /* 0x0000001e101c722b */
/* 0x002fc8000000001c */
/*09b0*/ DMUL R30, R26, R22 ; /* 0x000000161a1e7228 */
/* 0x001e080000000000 */
/*09c0*/ DADD R18, R18, -R26 ; /* 0x0000000012127229 */
/* 0x000e48000000081a */
/*09d0*/ DFMA R32, R26, R22, -R30 ; /* 0x000000161a20722b */
/* 0x001e08000000081e */
/*09e0*/ DADD R18, R24, R18 ; /* 0x0000000018127229 */
/* 0x002fc80000000012 */
/*09f0*/ DFMA R28, R26, R28, R32 ; /* 0x0000001c1a1c722b */
/* 0x001e0c0000000020 */
/*0a00*/ DFMA R28, R18, R22, R28 ; /* 0x00000016121c722b */
/* 0x001e0c000000001c */
/*0a10*/ DADD R22, R30, R28 ; /* 0x000000001e167229 */
/* 0x001e0c000000001c */
/*0a20*/ DADD R18, R16, R22 ; /* 0x0000000010127229 */
/* 0x001e080000000016 */
/*0a30*/ DADD R30, R30, -R22 ; /* 0x000000001e1e7229 */
/* 0x000e480000000816 */
/*0a40*/ DADD R16, R16, -R18 ; /* 0x0000000010107229 */
/* 0x001e080000000812 */
/*0a50*/ DADD R30, R28, R30 ; /* 0x000000001c1e7229 */
/* 0x002fc8000000001e */
/*0a60*/ DADD R16, R22, R16 ; /* 0x0000000016107229 */
/* 0x001e0c0000000010 */
/*0a70*/ DADD R16, R30, R16 ; /* 0x000000001e107229 */
/* 0x001e0c0000000010 */
/*0a80*/ DADD R22, R20, R16 ; /* 0x0000000014167229 */
/* 0x001e080000000010 */
/*0a90*/ DADD R16, R14, c[0x2][0x40] ; /* 0x008010000e107629 */
/* 0x000fc80000000000 */
/*0aa0*/ DADD R20, R18, R22 ; /* 0x0000000012147229 */
/* 0x001e0c0000000016 */
/*0ab0*/ DFMA R14, R16, c[0x2][0x48], R20 ; /* 0x00801200100e7a2b */
/* 0x001e080000000014 */
/*0ac0*/ DADD R24, R18, -R20 ; /* 0x0000000012187229 */
/* 0x000e480000000814 */
/*0ad0*/ DFMA R18, -R16, c[0x2][0x48], R14 ; /* 0x0080120010127a2b */
/* 0x001e08000000010e */
/*0ae0*/ DADD R24, R22, R24 ; /* 0x0000000016187229 */
/* 0x002fc80000000018 */
/*0af0*/ DADD R18, -R20, R18 ; /* 0x0000000014127229 */
/* 0x001e0c0000000112 */
/*0b00*/ DADD R18, R24, -R18 ; /* 0x0000000018127229 */
/* 0x0010640000000812 */
/*0b10*/ IMAD.MOV.U32 R24, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff187424 */
/* 0x001fe400078e00ff */
/*0b20*/ IMAD.MOV.U32 R25, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff197424 */
/* 0x000fe400078e00ff */
/*0b30*/ DFMA R18, R16, c[0x2][0x50], R18 ; /* 0x0080140010127a2b */
/* 0x002e0c0000000012 */
/*0b40*/ DADD R16, R14, R18 ; /* 0x000000000e107229 */
/* 0x001e0c0000000012 */
/*0b50*/ DADD R14, R14, -R16 ; /* 0x000000000e0e7229 */
/* 0x001e080000000810 */
/*0b60*/ DMUL R26, R16, 2 ; /* 0x40000000101a7828 */
/* 0x000e480000000000 */
/*0b70*/ DADD R14, R18, R14 ; /* 0x00000000120e7229 */
/* 0x0011e4000000000e */
/*0b80*/ IMAD.MOV.U32 R18, RZ, RZ, 0x652b82fe ; /* 0x652b82feff127424 */
/* 0x001fe400078e00ff */
/*0b90*/ DFMA R16, R16, 2, -R26 ; /* 0x400000001010782b */
/* 0x002e22000000081a */
/*0ba0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff137424 */
/* 0x000fca00078e00ff */
/*0bb0*/ DFMA R14, R14, 2, R16 ; /* 0x400000000e0e782b */
/* 0x001e0c0000000010 */
/*0bc0*/ DADD R16, R26, R14 ; /* 0x000000001a107229 */
/* 0x001e0c000000000e */
/*0bd0*/ DFMA R18, R16, R18, 6.75539944105574400000e+15 ; /* 0x433800001012742b */
/* 0x001e080000000012 */
/*0be0*/ FSETP.GEU.AND P0, PT, |R17|, 4.1917929649353027344, PT ; /* 0x4086232b1100780b */
/* 0x000fe40003f0e200 */
/*0bf0*/ DADD R20, R18, -6.75539944105574400000e+15 ; /* 0xc338000012147429 */
/* 0x001e0c0000000000 */
/*0c00*/ DFMA R22, R20, c[0x2][0x58], R16 ; /* 0x0080160014167a2b */
/* 0x001e0c0000000010 */
/*0c10*/ DFMA R22, R20, c[0x2][0x60], R22 ; /* 0x0080180014167a2b */
/* 0x001e0c0000000016 */
/*0c20*/ DFMA R24, R22, R24, c[0x2][0x68] ; /* 0x00801a001618762b */
/* 0x001e0c0000000018 */
/*0c30*/ DFMA R24, R22, R24, c[0x2][0x70] ; /* 0x00801c001618762b */
/* 0x001e0c0000000018 */
/*0c40*/ DFMA R24, R22, R24, c[0x2][0x78] ; /* 0x00801e001618762b */
/* 0x001e0c0000000018 */
/*0c50*/ DFMA R24, R22, R24, c[0x2][0x80] ; /* 0x008020001618762b */
/* 0x001e0c0000000018 */
/*0c60*/ DFMA R24, R22, R24, c[0x2][0x88] ; /* 0x008022001618762b */
/* 0x001e0c0000000018 */
/*0c70*/ DFMA R24, R22, R24, c[0x2][0x90] ; /* 0x008024001618762b */
/* 0x001e0c0000000018 */
/*0c80*/ DFMA R24, R22, R24, c[0x2][0x98] ; /* 0x008026001618762b */
/* 0x001e0c0000000018 */
/*0c90*/ DFMA R24, R22, R24, c[0x2][0xa0] ; /* 0x008028001618762b */
/* 0x001e0c0000000018 */
/*0ca0*/ DFMA R24, R22, R24, c[0x2][0xa8] ; /* 0x00802a001618762b */
/* 0x001e0c0000000018 */
/*0cb0*/ DFMA R24, R22, R24, 1 ; /* 0x3ff000001618742b */
/* 0x001e0c0000000018 */
/*0cc0*/ DFMA R22, R22, R24, 1 ; /* 0x3ff000001616742b */
/* 0x001e140000000018 */
/*0cd0*/ IMAD R21, R18, 0x100000, R23 ; /* 0x0010000012157824 */
/* 0x001fe400078e0217 */
/*0ce0*/ IMAD.MOV.U32 R20, RZ, RZ, R22 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0016 */
/*0cf0*/ @!P0 BRA 0xdc0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0d00*/ FSETP.GEU.AND P1, PT, |R17|, 4.2275390625, PT ; /* 0x408748001100780b */
/* 0x000fe20003f2e200 */
/*0d10*/ DADD R20, R16, +INF ; /* 0x7ff0000010147429 */
/* 0x000fc80000000000 */
/*0d20*/ DSETP.GEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000722a */
/* 0x000e0c0003f0e000 */
/*0d30*/ FSEL R20, R20, RZ, P0 ; /* 0x000000ff14147208 */
/* 0x001fe40000000000 */
/*0d40*/ @!P1 LEA.HI R19, R18, R18, RZ, 0x1 ; /* 0x0000001212139211 */
/* 0x000fe400078f08ff */
/*0d50*/ FSEL R21, R21, RZ, P0 ; /* 0x000000ff15157208 */
/* 0x000fe40000000000 */
/*0d60*/ @!P1 SHF.R.S32.HI R19, RZ, 0x1, R19 ; /* 0x00000001ff139819 */
/* 0x000fca0000011413 */
/*0d70*/ @!P1 IMAD.IADD R18, R18, 0x1, -R19 ; /* 0x0000000112129824 */
/* 0x000fe400078e0a13 */
/*0d80*/ @!P1 IMAD R23, R19, 0x100000, R23 ; /* 0x0010000013179824 */
/* 0x000fc600078e0217 */
/*0d90*/ @!P1 LEA R19, R18, 0x3ff00000, 0x14 ; /* 0x3ff0000012139811 */
/* 0x000fe200078ea0ff */
/*0da0*/ @!P1 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff129224 */
/* 0x000fcc00078e00ff */
/*0db0*/ @!P1 DMUL R20, R22, R18 ; /* 0x0000001216149228 */
/* 0x0000540000000000 */
/*0dc0*/ LOP3.LUT R18, R21, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff15127812 */
/* 0x003fe200078ec0ff */
/*0dd0*/ DADD R16, R26, -R16 ; /* 0x000000001a107229 */
/* 0x000e220000000810 */
/*0de0*/ IMAD.MOV.U32 R35, RZ, RZ, 0x0 ; /* 0x00000000ff237424 */
/* 0x000fe400078e00ff */
/*0df0*/ ISETP.NE.AND P0, PT, R18, 0x7ff00000, PT ; /* 0x7ff000001200780c */
/* 0x000fc60003f05270 */
/*0e00*/ DADD R16, R14, R16 ; /* 0x000000000e107229 */
/* 0x001e220000000010 */
/*0e10*/ ISETP.EQ.AND P0, PT, R20, RZ, !P0 ; /* 0x000000ff1400720c */
/* 0x000fda0004702270 */
/*0e20*/ @!P0 DFMA R20, R16, R20, R20 ; /* 0x000000141014822b */
/* 0x0010620000000014 */
/*0e30*/ RET.REL.NODEC R34 0x0 ; /* 0xfffff1c022007950 */
/* 0x000ff40003c3ffff */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // to avoid highlight problems
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdlib.h> // imported for rand() which generates a number between 0 & RAND_MAX
#include <time.h> // imported for the time() function and also the clock function
#include <limits> // for a large value
#include <cmath> // for exponentiation
using namespace std;
__global__ void FindClosestPoint(float3 *points, int *closestPoint, const int numberPoints)
{
// used to identify the thread that is currently running
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// now find the closest point to each point
// 'i' represents the current point that we are finding the closest point to!
int distanceBetweenPoints = 9999999, tempDistance = 0;
for (int j = 0; j < numberPoints; j++)
if (idx != j) // dont check the distance between the point and itself
{
tempDistance = pow((points[idx].x - points[j].x), 2) + pow((points[idx].y - points[j].y), 2);
if (tempDistance < distanceBetweenPoints)
{
distanceBetweenPoints = tempDistance;
closestPoint[idx] = j;
}
}
}
int main()
{
srand(time(NULL)); // used to initialize the seed for the random number generator
const int numberPoints = 1000;
clock_t startTime, endTime;
float3 *points = new float3[numberPoints];
float3 *pointsDeviceCopy;
int *closestPointDevice, *closestPoint = new int[numberPoints];
// initialize the points with random numbers
for (int i = 0; i < numberPoints; i++)
{
points[i].x = rand() % 1000;
points[i].y = rand() % 1000;
points[i].z = rand() % 1000;
}
// print the points initialized
for (int i = 0; i < numberPoints; i++)
cout << points[i].x << "\t" << points[i].y << "\t" << points[i].z << endl;
cout << endl;
// initialize memory in the GPU for calculation
if (cudaMalloc(&pointsDeviceCopy, sizeof(float3) * numberPoints) != cudaSuccess)
{
cout << "Couldn't initialize memory in the GPU for pointsDeviceCopy" << endl;
delete[] points;
delete[] closestPoint;
return 0;
}
if (cudaMalloc(&closestPointDevice, sizeof(int) * numberPoints) != cudaSuccess)
{
cout << "Couldn't initialize memory in the GPU for closestPointDevice" << endl;
cudaFree(pointsDeviceCopy);
delete[] points;
delete[] closestPoint;
return 0;
}
if (cudaMemcpy(pointsDeviceCopy, points, sizeof(float3) * numberPoints, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "Could not copy points to pointsDeviceCopy" << endl;
cudaFree(pointsDeviceCopy);
cudaFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
// now find the distance between all points
startTime = clock();
// since a block can have upto 1024 elements, we can use a single block
FindClosestPoint<<<1, numberPoints>>>(pointsDeviceCopy, closestPointDevice, numberPoints);
if (cudaMemcpy(closestPoint, closestPointDevice, sizeof(int) * numberPoints, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "Could not get the output!";
cudaFree(pointsDeviceCopy);
cudaFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
endTime = clock() - startTime;
delete[] points;
delete[] closestPoint;
cudaFree(closestPointDevice);
cudaFree(pointsDeviceCopy);
cout << "Time it took was " << ((float)endTime / CLOCKS_PER_SEC) << endl;
return 0;
} | .file "tmpxft_000dabec_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
.type _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii, @function
_Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16FindClosestPointP6float3Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii, .-_Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
.globl _Z16FindClosestPointP6float3Pii
.type _Z16FindClosestPointP6float3Pii, @function
_Z16FindClosestPointP6float3Pii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z16FindClosestPointP6float3Pii, .-_Z16FindClosestPointP6float3Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Couldn't initialize memory in the GPU for pointsDeviceCopy"
.align 8
.LC2:
.string "Couldn't initialize memory in the GPU for closestPointDevice"
.align 8
.LC3:
.string "Could not copy points to pointsDeviceCopy"
.section .rodata.str1.1
.LC4:
.string "Could not get the output!"
.LC5:
.string "Time it took was "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $12000, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movl $4000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %rbp, %rbx
leaq 12000(%rbp), %r13
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 8(%rbp)
addq $12, %rbp
cmpq %r13, %rbp
jne .L12
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r14
jmp .L17
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
call _ZSt16__throw_bad_castv@PLT
.L28:
call __stack_chk_fail@PLT
.L15:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbx
cmpq %r13, %rbx
je .L29
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L30
cmpb $0, 56(%r12)
je .L15
movzbl 67(%r12), %esi
jmp .L16
.L29:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
movl $12000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movl $12000, %edx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
call clock@PLT
movq %rax, %rbx
movl $1000, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L22:
movl $2, %ecx
movl $4000, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
call clock@PLT
subq %rbx, %rax
movq %rax, %rbp
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssq %rbp, %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L31:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
jmp .L19
.L33:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
jmp .L19
.L34:
movl $1000, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
jmp .L22
.L35:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
jmp .L19
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z16FindClosestPointP6float3Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16FindClosestPointP6float3Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // to avoid highlight problems
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdlib.h> // imported for rand() which generates a number between 0 & RAND_MAX
#include <time.h> // imported for the time() function and also the clock function
#include <limits> // for a large value
#include <cmath> // for exponentiation
using namespace std;
__global__ void FindClosestPoint(float3 *points, int *closestPoint, const int numberPoints)
{
// used to identify the thread that is currently running
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// now find the closest point to each point
// 'i' represents the current point that we are finding the closest point to!
int distanceBetweenPoints = 9999999, tempDistance = 0;
for (int j = 0; j < numberPoints; j++)
if (idx != j) // dont check the distance between the point and itself
{
tempDistance = pow((points[idx].x - points[j].x), 2) + pow((points[idx].y - points[j].y), 2);
if (tempDistance < distanceBetweenPoints)
{
distanceBetweenPoints = tempDistance;
closestPoint[idx] = j;
}
}
}
int main()
{
srand(time(NULL)); // used to initialize the seed for the random number generator
const int numberPoints = 1000;
clock_t startTime, endTime;
float3 *points = new float3[numberPoints];
float3 *pointsDeviceCopy;
int *closestPointDevice, *closestPoint = new int[numberPoints];
// initialize the points with random numbers
for (int i = 0; i < numberPoints; i++)
{
points[i].x = rand() % 1000;
points[i].y = rand() % 1000;
points[i].z = rand() % 1000;
}
// print the points initialized
for (int i = 0; i < numberPoints; i++)
cout << points[i].x << "\t" << points[i].y << "\t" << points[i].z << endl;
cout << endl;
// initialize memory in the GPU for calculation
if (cudaMalloc(&pointsDeviceCopy, sizeof(float3) * numberPoints) != cudaSuccess)
{
cout << "Couldn't initialize memory in the GPU for pointsDeviceCopy" << endl;
delete[] points;
delete[] closestPoint;
return 0;
}
if (cudaMalloc(&closestPointDevice, sizeof(int) * numberPoints) != cudaSuccess)
{
cout << "Couldn't initialize memory in the GPU for closestPointDevice" << endl;
cudaFree(pointsDeviceCopy);
delete[] points;
delete[] closestPoint;
return 0;
}
if (cudaMemcpy(pointsDeviceCopy, points, sizeof(float3) * numberPoints, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "Could not copy points to pointsDeviceCopy" << endl;
cudaFree(pointsDeviceCopy);
cudaFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
// now find the distance between all points
startTime = clock();
// since a block can have upto 1024 elements, we can use a single block
FindClosestPoint<<<1, numberPoints>>>(pointsDeviceCopy, closestPointDevice, numberPoints);
if (cudaMemcpy(closestPoint, closestPointDevice, sizeof(int) * numberPoints, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "Could not get the output!";
cudaFree(pointsDeviceCopy);
cudaFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
endTime = clock() - startTime;
delete[] points;
delete[] closestPoint;
cudaFree(closestPointDevice);
cudaFree(pointsDeviceCopy);
cout << "Time it took was " << ((float)endTime / CLOCKS_PER_SEC) << endl;
return 0;
} | // to avoid highlight problems
#include "hip/hip_runtime.h"
#include <iostream>
#include <stdlib.h> // imported for rand() which generates a number between 0 & RAND_MAX
#include <time.h> // imported for the time() function and also the clock function
#include <limits> // for a large value
#include <cmath> // for exponentiation
using namespace std;
__global__ void FindClosestPoint(float3 *points, int *closestPoint, const int numberPoints)
{
// used to identify the thread that is currently running
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// now find the closest point to each point
// 'i' represents the current point that we are finding the closest point to!
int distanceBetweenPoints = 9999999, tempDistance = 0;
for (int j = 0; j < numberPoints; j++)
if (idx != j) // dont check the distance between the point and itself
{
tempDistance = pow((points[idx].x - points[j].x), 2) + pow((points[idx].y - points[j].y), 2);
if (tempDistance < distanceBetweenPoints)
{
distanceBetweenPoints = tempDistance;
closestPoint[idx] = j;
}
}
}
int main()
{
srand(time(NULL)); // used to initialize the seed for the random number generator
const int numberPoints = 1000;
clock_t startTime, endTime;
float3 *points = new float3[numberPoints];
float3 *pointsDeviceCopy;
int *closestPointDevice, *closestPoint = new int[numberPoints];
// initialize the points with random numbers
for (int i = 0; i < numberPoints; i++)
{
points[i].x = rand() % 1000;
points[i].y = rand() % 1000;
points[i].z = rand() % 1000;
}
// print the points initialized
for (int i = 0; i < numberPoints; i++)
cout << points[i].x << "\t" << points[i].y << "\t" << points[i].z << endl;
cout << endl;
// initialize memory in the GPU for calculation
if (hipMalloc(&pointsDeviceCopy, sizeof(float3) * numberPoints) != hipSuccess)
{
cout << "Couldn't initialize memory in the GPU for pointsDeviceCopy" << endl;
delete[] points;
delete[] closestPoint;
return 0;
}
if (hipMalloc(&closestPointDevice, sizeof(int) * numberPoints) != hipSuccess)
{
cout << "Couldn't initialize memory in the GPU for closestPointDevice" << endl;
hipFree(pointsDeviceCopy);
delete[] points;
delete[] closestPoint;
return 0;
}
if (hipMemcpy(pointsDeviceCopy, points, sizeof(float3) * numberPoints, hipMemcpyHostToDevice) != hipSuccess)
{
cout << "Could not copy points to pointsDeviceCopy" << endl;
hipFree(pointsDeviceCopy);
hipFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
// now find the distance between all points
startTime = clock();
// since a block can have upto 1024 elements, we can use a single block
FindClosestPoint<<<1, numberPoints>>>(pointsDeviceCopy, closestPointDevice, numberPoints);
if (hipMemcpy(closestPoint, closestPointDevice, sizeof(int) * numberPoints, hipMemcpyDeviceToHost) != hipSuccess)
{
cout << "Could not get the output!";
hipFree(pointsDeviceCopy);
hipFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
endTime = clock() - startTime;
delete[] points;
delete[] closestPoint;
hipFree(closestPointDevice);
hipFree(pointsDeviceCopy);
cout << "Time it took was " << ((float)endTime / CLOCKS_PER_SEC) << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // to avoid highlight problems
#include "hip/hip_runtime.h"
#include <iostream>
#include <stdlib.h> // imported for rand() which generates a number between 0 & RAND_MAX
#include <time.h> // imported for the time() function and also the clock function
#include <limits> // for a large value
#include <cmath> // for exponentiation
using namespace std;
__global__ void FindClosestPoint(float3 *points, int *closestPoint, const int numberPoints)
{
// used to identify the thread that is currently running
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// now find the closest point to each point
// 'i' represents the current point that we are finding the closest point to!
int distanceBetweenPoints = 9999999, tempDistance = 0;
for (int j = 0; j < numberPoints; j++)
if (idx != j) // dont check the distance between the point and itself
{
tempDistance = pow((points[idx].x - points[j].x), 2) + pow((points[idx].y - points[j].y), 2);
if (tempDistance < distanceBetweenPoints)
{
distanceBetweenPoints = tempDistance;
closestPoint[idx] = j;
}
}
}
int main()
{
srand(time(NULL)); // used to initialize the seed for the random number generator
const int numberPoints = 1000;
clock_t startTime, endTime;
float3 *points = new float3[numberPoints];
float3 *pointsDeviceCopy;
int *closestPointDevice, *closestPoint = new int[numberPoints];
// initialize the points with random numbers
for (int i = 0; i < numberPoints; i++)
{
points[i].x = rand() % 1000;
points[i].y = rand() % 1000;
points[i].z = rand() % 1000;
}
// print the points initialized
for (int i = 0; i < numberPoints; i++)
cout << points[i].x << "\t" << points[i].y << "\t" << points[i].z << endl;
cout << endl;
// initialize memory in the GPU for calculation
if (hipMalloc(&pointsDeviceCopy, sizeof(float3) * numberPoints) != hipSuccess)
{
cout << "Couldn't initialize memory in the GPU for pointsDeviceCopy" << endl;
delete[] points;
delete[] closestPoint;
return 0;
}
if (hipMalloc(&closestPointDevice, sizeof(int) * numberPoints) != hipSuccess)
{
cout << "Couldn't initialize memory in the GPU for closestPointDevice" << endl;
hipFree(pointsDeviceCopy);
delete[] points;
delete[] closestPoint;
return 0;
}
if (hipMemcpy(pointsDeviceCopy, points, sizeof(float3) * numberPoints, hipMemcpyHostToDevice) != hipSuccess)
{
cout << "Could not copy points to pointsDeviceCopy" << endl;
hipFree(pointsDeviceCopy);
hipFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
// now find the distance between all points
startTime = clock();
// since a block can have upto 1024 elements, we can use a single block
FindClosestPoint<<<1, numberPoints>>>(pointsDeviceCopy, closestPointDevice, numberPoints);
if (hipMemcpy(closestPoint, closestPointDevice, sizeof(int) * numberPoints, hipMemcpyDeviceToHost) != hipSuccess)
{
cout << "Could not get the output!";
hipFree(pointsDeviceCopy);
hipFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
endTime = clock() - startTime;
delete[] points;
delete[] closestPoint;
hipFree(closestPointDevice);
hipFree(pointsDeviceCopy);
cout << "Time it took was " << ((float)endTime / CLOCKS_PER_SEC) << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.globl _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.p2align 8
.type _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii,@function
_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[8:11], s[0:1], 0x0
v_mov_b32_e32 v6, 0
s_mov_b32 s1, 0
s_mov_b32 s5, 0x3e76c4e1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_add_u32 s2, s8, 4
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v0, 0x98967f
s_addc_u32 s3, s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_mad_i64_i32 v[2:3], null, v1, 12, s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s1, s1, 1
s_add_u32 s2, s2, 12
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, s1
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e64 s1, v1
s_cbranch_execz .LBB0_3
global_load_b64 v[7:8], v[2:3], off
s_clause 0x1
global_load_b32 v9, v6, s[2:3] offset:-4
global_load_b32 v10, v6, s[2:3]
s_waitcnt vmcnt(0)
v_dual_sub_f32 v7, v7, v9 :: v_dual_sub_f32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e64 v9, |v7|
v_frexp_mant_f32_e64 v10, |v8|
v_frexp_exp_i32_f32_e32 v24, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v9
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v10
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, 0, 1, s0
v_ldexp_f32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v10, v10, v12
v_dual_add_f32 v11, 1.0, v9 :: v_dual_add_f32 v12, 1.0, v10
v_dual_add_f32 v15, -1.0, v9 :: v_dual_add_f32 v16, -1.0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v13, v11
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v17, v15, v13 :: v_dual_mul_f32 v18, v16, v14
v_add_f32_e32 v19, -1.0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v21, -1.0, v12 :: v_dual_mul_f32 v20, v11, v17
v_dual_mul_f32 v22, v12, v18 :: v_dual_sub_f32 v9, v9, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v10, v21
v_fma_f32 v11, v17, v11, -v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v18, v12, -v22
v_dual_fmac_f32 v11, v17, v9 :: v_dual_fmac_f32 v12, v18, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v9, v20, v11 :: v_dual_add_f32 v10, v22, v12
v_dual_sub_f32 v19, v15, v9 :: v_dual_sub_f32 v20, v9, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v22, v10, v22
v_sub_f32_e32 v21, v16, v10
v_dual_sub_f32 v15, v15, v19 :: v_dual_sub_f32 v12, v22, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v20, v11
v_sub_f32_e32 v9, v15, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v11, v9
v_add_f32_e32 v9, v19, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v13, v9
v_add_f32_e32 v11, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v16, v21 :: v_dual_mul_f32 v15, v11, v11
v_sub_f32_e32 v10, v16, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v12, v10
v_add_f32_e32 v10, v21, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v14, v10
v_add_f32_e32 v12, v18, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v14, v12, v18 :: v_dual_sub_f32 v13, v11, v17
v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v9, v9, v13
v_fma_f32 v14, v11, v11, -v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v18, v10, v10 :: v_dual_mul_f32 v13, v12, v12
v_add_f32_e32 v16, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, v12, v12, -v13
v_dual_fmac_f32 v14, v11, v16 :: v_dual_fmac_f32 v17, v12, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v18, v13, v17
v_dual_add_f32 v16, v15, v14 :: v_dual_sub_f32 v13, v18, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v19, s5, v16, 0x3e91f4c4 :: v_dual_fmaak_f32 v20, s5, v18, 0x3e91f4c4
v_sub_f32_e32 v15, v16, v15
v_sub_f32_e32 v13, v17, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v19, v16, v19, 0x3ecccdef :: v_dual_fmaak_f32 v20, v18, v20, 0x3ecccdef
v_sub_f32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v21, v16, v19 :: v_dual_mul_f32 v22, v18, v20
v_fma_f32 v15, v16, v19, -v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, v18, v20, -v22
v_fmac_f32_e32 v15, v14, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v17, v13, v20
v_mul_f32_e32 v20, v11, v16
v_frexp_exp_i32_f32_e32 v19, v7
v_add_f32_e32 v23, v21, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v27, v16, v11, -v20
v_add_f32_e32 v28, 0x3f2aaaaa, v23
v_add_f32_e32 v26, v22, v17
v_sub_f32_e32 v21, v23, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v27, v16, v9
v_ldexp_f32 v9, v9, 1
v_sub_f32_e32 v22, v26, v22
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v30, 0x3f2aaaaa, v26 :: v_dual_sub_f32 v15, v15, v21
v_add_f32_e32 v21, 0xbf2aaaaa, v28
v_dual_fmac_f32 v27, v14, v11 :: v_dual_sub_f32 v16, v17, v22
v_mul_f32_e32 v25, v12, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f32_e32 v17, 0xbf2aaaaa, v30
v_add_f32_e32 v15, 0x31739010, v15
v_dual_sub_f32 v21, v23, v21 :: v_dual_add_f32 v14, 0x31739010, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v29, v18, v12, -v25
v_sub_f32_e32 v16, v26, v17
v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v19, vcc_lo
v_ldexp_f32 v11, v11, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v29, v18, v10
v_subrev_co_ci_u32_e64 v18, vcc_lo, 0, v24, s0
v_ldexp_f32 v10, v10, 1
v_cmp_neq_f32_e64 s0, 0x7f800000, |v7|
v_fmac_f32_e32 v29, v13, v12
v_add_f32_e32 v13, v14, v16
v_ldexp_f32 v12, v12, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v19, v30, v13
v_dual_add_f32 v15, v15, v21 :: v_dual_sub_f32 v24, v30, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v16, v28, v15 :: v_dual_add_f32 v21, v25, v29
v_sub_f32_e32 v22, v28, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v26, v21, v19
v_add_f32_e32 v13, v13, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v15, v15, v22
v_fma_f32 v24, v21, v19, -v26
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v24, v21, v13
v_add_f32_e32 v14, v20, v27
v_cvt_f32_i32_e32 v13, v18
v_mul_f32_e32 v23, v14, v16
v_sub_f32_e32 v20, v14, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v22, v14, v16, -v23
v_sub_f32_e32 v20, v27, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v22, v14, v15
v_cvt_f32_i32_e32 v14, v17
v_fmac_f32_e32 v22, v20, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v16, 0x3f317218, v14 :: v_dual_sub_f32 v25, v21, v25
v_sub_f32_e32 v15, v29, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v24, v15, v19
v_fma_f32 v19, v14, 0x3f317218, -v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v18, v26, v24 :: v_dual_fmac_f32 v19, 0xb102e308, v14
v_sub_f32_e32 v25, v18, v26
v_add_f32_e32 v15, v23, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v21, v15, v23
v_sub_f32_e32 v21, v22, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v22, v24, v25
v_dual_add_f32 v20, v11, v15 :: v_dual_add_f32 v9, v9, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v10, v22
v_add_f32_e32 v23, v12, v18
v_dual_sub_f32 v12, v23, v12 :: v_dual_mul_f32 v17, 0x3f317218, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v18, v12
v_dual_add_f32 v10, v10, v12 :: v_dual_sub_f32 v11, v20, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v14, v23, v10
v_sub_f32_e32 v11, v15, v11
v_fma_f32 v15, v13, 0x3f317218, -v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v9, v11
v_add_f32_e32 v11, v16, v19
v_add_f32_e32 v12, v20, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v16, v11, v16
v_add_f32_e32 v18, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v22, v18, v11 :: v_dual_fmac_f32 v15, 0xb102e308, v13
v_dual_sub_f32 v16, v19, v16 :: v_dual_sub_f32 v23, v14, v23
v_sub_f32_e32 v19, v12, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v12, v12, v22
v_sub_f32_e32 v10, v10, v23
v_add_f32_e32 v13, v17, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v21, v13, v14
v_sub_f32_e32 v17, v13, v17
v_sub_f32_e32 v20, v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_sub_f32_e32 v15, v15, v17
v_sub_f32_e32 v17, v18, v22
v_sub_f32_e32 v9, v9, v19
v_sub_f32_e32 v19, v21, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v14, v14, v20 :: v_dual_sub_f32 v11, v11, v17
v_dual_add_f32 v11, v12, v11 :: v_dual_add_f32 v12, v15, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v13, v13, v19
v_add_f32_e32 v13, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v12, v13
v_add_f32_e32 v17, v16, v9
v_dual_sub_f32 v14, v17, v16 :: v_dual_sub_f32 v19, v12, v15
v_add_f32_e32 v11, v17, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v17, v17, v14 :: v_dual_sub_f32 v12, v12, v19
v_add_f32_e32 v20, v18, v11
v_sub_f32_e32 v10, v10, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v16, v16, v17
v_dual_sub_f32 v12, v15, v12 :: v_dual_sub_f32 v9, v9, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v14, v21, v13 :: v_dual_sub_f32 v17, v20, v18
v_add_f32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v9, v16
v_sub_f32_e32 v15, v14, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v13, v15
v_add_f32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v14, v10
v_sub_f32_e32 v14, v12, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v11, v11, v17
v_mul_f32_e32 v17, 0, v12
v_add_f32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, 2.0, v10
v_add_f32_e32 v11, v20, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v13, v11, v20 :: v_dual_mul_f32 v16, 0, v11
v_sub_f32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v13, v12, v12 :: v_dual_fmac_f32 v16, 2.0, v9
v_fma_f32 v9, v12, 2.0, -v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v17
v_dual_add_f32 v12, v13, v9 :: v_dual_add_f32 v15, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v11, v11, 2.0, -v15
v_cmp_class_f32_e64 vcc_lo, v15, 0x204
v_add_f32_e32 v10, v11, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v15, v10
v_cndmask_b32_e32 v14, v11, v15, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v13, 0x204
v_cndmask_b32_e32 v16, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v14
v_dual_sub_f32 v12, v12, v13 :: v_dual_sub_f32 v11, v11, v15
v_cndmask_b32_e64 v17, 0, 0x37000000, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v16
v_dual_sub_f32 v10, v10, v11 :: v_dual_sub_f32 v9, v9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v19, v14, v17
v_cndmask_b32_e64 v18, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v14|
v_dual_mul_f32 v21, 0x3fb8aa3b, v19 :: v_dual_sub_f32 v20, v16, v18
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v16|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v23, v19, 0x3fb8aa3b, -v21
v_mul_f32_e32 v22, 0x3fb8aa3b, v20
v_rndne_f32_e32 v24, v21
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v19
v_fmac_f32_e32 v23, 0x32a5705f, v19
v_fma_f32 v25, v20, 0x3fb8aa3b, -v22
v_rndne_f32_e32 v26, v22
v_sub_f32_e32 v21, v21, v24
v_cvt_i32_f32_e32 v11, v24
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v10, v17, v10 :: v_dual_fmac_f32 v25, 0x32a5705f, v20
v_dual_sub_f32 v22, v22, v26 :: v_dual_add_f32 v21, v21, v23
v_cvt_i32_f32_e32 v12, v26
v_add_f32_e32 v9, v18, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v22, v22, v25
v_exp_f32_e32 v15, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_exp_f32_e32 v13, v22
s_waitcnt_depctr 0xfff
v_ldexp_f32 v11, v15, v11
v_ldexp_f32 v12, v13, v12
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v19
v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v10, v11, v10, v11
v_cndmask_b32_e32 v12, 0x7f800000, v12, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
v_fma_f32 v9, v12, v9, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v12
v_cndmask_b32_e64 v10, 0x7f800000, |v10|, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, v9, v12, vcc_lo
v_cmp_neq_f32_e64 s0, 0x7f800000, |v8|
v_cmp_neq_f32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v9, 0x7f800000, |v9|, s0
v_cndmask_b32_e32 v7, 0, v10, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v8
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, 0, v9, vcc_lo
v_add_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v7, v7
v_cmpx_gt_i32_e64 v0, v7
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v8, s1
v_mov_b32_e32 v0, v7
global_store_b32 v[4:5], v8, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, .Lfunc_end0-_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // to avoid highlight problems
#include "hip/hip_runtime.h"
#include <iostream>
#include <stdlib.h> // imported for rand() which generates a number between 0 & RAND_MAX
#include <time.h> // imported for the time() function and also the clock function
#include <limits> // for a large value
#include <cmath> // for exponentiation
using namespace std;
__global__ void FindClosestPoint(float3 *points, int *closestPoint, const int numberPoints)
{
// used to identify the thread that is currently running
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// now find the closest point to each point
// 'i' represents the current point that we are finding the closest point to!
int distanceBetweenPoints = 9999999, tempDistance = 0;
for (int j = 0; j < numberPoints; j++)
if (idx != j) // dont check the distance between the point and itself
{
tempDistance = pow((points[idx].x - points[j].x), 2) + pow((points[idx].y - points[j].y), 2);
if (tempDistance < distanceBetweenPoints)
{
distanceBetweenPoints = tempDistance;
closestPoint[idx] = j;
}
}
}
int main()
{
srand(time(NULL)); // used to initialize the seed for the random number generator
const int numberPoints = 1000;
clock_t startTime, endTime;
float3 *points = new float3[numberPoints];
float3 *pointsDeviceCopy;
int *closestPointDevice, *closestPoint = new int[numberPoints];
// initialize the points with random numbers
for (int i = 0; i < numberPoints; i++)
{
points[i].x = rand() % 1000;
points[i].y = rand() % 1000;
points[i].z = rand() % 1000;
}
// print the points initialized
for (int i = 0; i < numberPoints; i++)
cout << points[i].x << "\t" << points[i].y << "\t" << points[i].z << endl;
cout << endl;
// initialize memory in the GPU for calculation
if (hipMalloc(&pointsDeviceCopy, sizeof(float3) * numberPoints) != hipSuccess)
{
cout << "Couldn't initialize memory in the GPU for pointsDeviceCopy" << endl;
delete[] points;
delete[] closestPoint;
return 0;
}
if (hipMalloc(&closestPointDevice, sizeof(int) * numberPoints) != hipSuccess)
{
cout << "Couldn't initialize memory in the GPU for closestPointDevice" << endl;
hipFree(pointsDeviceCopy);
delete[] points;
delete[] closestPoint;
return 0;
}
if (hipMemcpy(pointsDeviceCopy, points, sizeof(float3) * numberPoints, hipMemcpyHostToDevice) != hipSuccess)
{
cout << "Could not copy points to pointsDeviceCopy" << endl;
hipFree(pointsDeviceCopy);
hipFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
// now find the distance between all points
startTime = clock();
// since a block can have upto 1024 elements, we can use a single block
FindClosestPoint<<<1, numberPoints>>>(pointsDeviceCopy, closestPointDevice, numberPoints);
if (hipMemcpy(closestPoint, closestPointDevice, sizeof(int) * numberPoints, hipMemcpyDeviceToHost) != hipSuccess)
{
cout << "Could not get the output!";
hipFree(pointsDeviceCopy);
hipFree(closestPointDevice);
delete[] points;
delete[] closestPoint;
return 0;
}
endTime = clock() - startTime;
delete[] points;
delete[] closestPoint;
hipFree(closestPointDevice);
hipFree(pointsDeviceCopy);
cout << "Time it took was " << ((float)endTime / CLOCKS_PER_SEC) << endl;
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii # -- Begin function _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.p2align 4, 0x90
.type _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii,@function
_Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii: # @_Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii, .Lfunc_end0-_Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $12000, %edi # imm = 0x2EE0
callq _Znam
movq %rax, %r14
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %rbx
movl $8, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, -8(%r14,%r15)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, -4(%r14,%r15)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15)
addq $12, %r15
cmpq $12008, %r15 # imm = 0x2EE8
jne .LBB1_1
# %bb.2: # %.preheader.preheader
movl $8, %r12d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_3 Depth=1
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $12, %r12
cmpq $12008, %r12 # imm = 0x2EE8
je .LBB1_6
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss -8(%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -4(%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_39
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r15)
je .LBB1_14
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_15
.LBB1_6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_9
# %bb.8:
movzbl 67(%r15), %eax
jmp .LBB1_10
.LBB1_9:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movl $12000, %esi # imm = 0x2EE0
callq hipMalloc
testl %eax, %eax
je .LBB1_18
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%r15)
je .LBB1_16
# %bb.13:
movzbl 67(%r15), %eax
jmp .LBB1_17
.LBB1_18:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
testl %eax, %eax
je .LBB1_24
# %bb.19:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r15)
je .LBB1_22
# %bb.21:
movzbl 67(%r15), %eax
jmp .LBB1_23
.LBB1_16:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_36
.LBB1_24:
movq (%rsp), %rdi
movl $12000, %edx # imm = 0x2EE0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_30
# %bb.25:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%r15)
je .LBB1_28
# %bb.27:
movzbl 67(%r15), %eax
jmp .LBB1_29
.LBB1_22:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
jmp .LBB1_35
.LBB1_30:
callq clock
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 999(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $1000, %edx # imm = 0x3E8
callq _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.LBB1_32:
movq 8(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_37
# %bb.33:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_34
.LBB1_28:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_34:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
.LBB1_35:
callq hipFree
.LBB1_36:
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
.LBB1_38:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_37:
.cfi_def_cfa_offset 64
callq clock
movq %rax, %r12
subq %r15, %r12
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2ss %r12, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_38
.LBB1_39:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii,@object # @_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.section .rodata,"a",@progbits
.globl _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.p2align 3, 0x0
_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii:
.quad _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.size _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\t"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Couldn't initialize memory in the GPU for pointsDeviceCopy"
.size .L.str.1, 59
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Couldn't initialize memory in the GPU for closestPointDevice"
.size .L.str.2, 61
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Could not copy points to pointsDeviceCopy"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Could not get the output!"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time it took was "
.size .L.str.5, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dabec_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
.type _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii, @function
_Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16FindClosestPointP6float3Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii, .-_Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
.globl _Z16FindClosestPointP6float3Pii
.type _Z16FindClosestPointP6float3Pii, @function
_Z16FindClosestPointP6float3Pii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z16FindClosestPointP6float3Pii, .-_Z16FindClosestPointP6float3Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Couldn't initialize memory in the GPU for pointsDeviceCopy"
.align 8
.LC2:
.string "Couldn't initialize memory in the GPU for closestPointDevice"
.align 8
.LC3:
.string "Could not copy points to pointsDeviceCopy"
.section .rodata.str1.1
.LC4:
.string "Could not get the output!"
.LC5:
.string "Time it took was "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $12000, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movl $4000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %rbp, %rbx
leaq 12000(%rbp), %r13
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 8(%rbp)
addq $12, %rbp
cmpq %r13, %rbp
jne .L12
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r14
jmp .L17
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
call _ZSt16__throw_bad_castv@PLT
.L28:
call __stack_chk_fail@PLT
.L15:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbx
cmpq %r13, %rbx
je .L29
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L30
cmpb $0, 56(%r12)
je .L15
movzbl 67(%r12), %esi
jmp .L16
.L29:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
movl $12000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movl $12000, %edx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
call clock@PLT
movq %rax, %rbx
movl $1000, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L22:
movl $2, %ecx
movl $4000, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
call clock@PLT
subq %rbx, %rax
movq %rax, %rbp
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssq %rbp, %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L31:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
jmp .L19
.L33:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
jmp .L19
.L34:
movl $1000, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z16FindClosestPointP6float3PiiP6float3Pii
jmp .L22
.L35:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
jmp .L19
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z16FindClosestPointP6float3Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16FindClosestPointP6float3Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii # -- Begin function _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.p2align 4, 0x90
.type _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii,@function
_Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii: # @_Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii, .Lfunc_end0-_Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $12000, %edi # imm = 0x2EE0
callq _Znam
movq %rax, %r14
movl $4000, %edi # imm = 0xFA0
callq _Znam
movq %rax, %rbx
movl $8, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, -8(%r14,%r15)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, -4(%r14,%r15)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15)
addq $12, %r15
cmpq $12008, %r15 # imm = 0x2EE8
jne .LBB1_1
# %bb.2: # %.preheader.preheader
movl $8, %r12d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_3 Depth=1
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $12, %r12
cmpq $12008, %r12 # imm = 0x2EE8
je .LBB1_6
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss -8(%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -4(%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_39
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r15)
je .LBB1_14
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_15
.LBB1_6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_9
# %bb.8:
movzbl 67(%r15), %eax
jmp .LBB1_10
.LBB1_9:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movl $12000, %esi # imm = 0x2EE0
callq hipMalloc
testl %eax, %eax
je .LBB1_18
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%r15)
je .LBB1_16
# %bb.13:
movzbl 67(%r15), %eax
jmp .LBB1_17
.LBB1_18:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
testl %eax, %eax
je .LBB1_24
# %bb.19:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r15)
je .LBB1_22
# %bb.21:
movzbl 67(%r15), %eax
jmp .LBB1_23
.LBB1_16:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_36
.LBB1_24:
movq (%rsp), %rdi
movl $12000, %edx # imm = 0x2EE0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_30
# %bb.25:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_39
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%r15)
je .LBB1_28
# %bb.27:
movzbl 67(%r15), %eax
jmp .LBB1_29
.LBB1_22:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
jmp .LBB1_35
.LBB1_30:
callq clock
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 999(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $1000, %edx # imm = 0x3E8
callq _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.LBB1_32:
movq 8(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_37
# %bb.33:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_34
.LBB1_28:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_34:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
.LBB1_35:
callq hipFree
.LBB1_36:
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
.LBB1_38:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_37:
.cfi_def_cfa_offset 64
callq clock
movq %rax, %r12
subq %r15, %r12
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2ss %r12, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_38
.LBB1_39:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii,@object # @_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.section .rodata,"a",@progbits
.globl _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.p2align 3, 0x0
_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii:
.quad _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.size _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\t"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Couldn't initialize memory in the GPU for pointsDeviceCopy"
.size .L.str.1, 59
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Couldn't initialize memory in the GPU for closestPointDevice"
.size .L.str.2, 61
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Could not copy points to pointsDeviceCopy"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Could not get the output!"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time it took was "
.size .L.str.5, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__FindClosestPointP15HIP_vector_typeIfLj3EEPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16FindClosestPointP15HIP_vector_typeIfLj3EEPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// problem parameters
const double a = 1.;
const double b = 1.;
const int nx = 1024; //number of node points along y
const int ny = 1024; //number of node points along x
//convergence parameters
double tol = 1e-4;
int iter_max = 1000;
double sol_ref(double x, double y)
{
return sin(M_PI*x)*exp(-M_PI*y);
}
void discretisation(double *x, double *y)
{
double dx = a/nx; // spatial step along x
double dy = b/ny; // spatial step along y
for (int i=0; i<=nx; i++)
{
x[i] = i*dx;
y[i] = i*dy;
}
}
void boundary(double *T, double *x, double *y)
{
/*Boundary conditions along the x axis for all processes */
for ( int i=0; i<=nx; i++)
{
T[i*nx] = sol_ref(x[i], y[0]);
T[i*ny+ny] = sol_ref(x[i], y[ny]);
}
/*Boundary conditions along the y axis for all processes */
for ( int j=0; j<=ny; j++)
{
T[j] = sol_ref(x[0], y[j]);
T[nx*ny+j] = sol_ref(x[nx], y[j]);
}
}
void laplace2d(double *T, double *Tnew, double *error)
{
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
Tnew[j*nx + i] = 0.25 * ( T[j*nx + (i+1)] + T[j*nx + (i-1)] + T[(j-1)*nx + i] + T[(j+1)*nx + i] );
*error = fmax(*error, fabs(Tnew[j*nx + i] - T[j*nx + i]));
}
}
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
T[j*nx + i] = Tnew[j*nx + i];
}
}
}
int main(int argc,char **argv)
{
double tol = 1e-4;
int iter = 0;
double error;
double *T = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *Tnew = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *x = (double*) malloc(nx * sizeof(double));
double *y = (double*) malloc(ny * sizeof(double));
if(!x || !y || !T || !Tnew ) return 0;
discretisation(x, y);
boundary(T, x, y);
while (iter < iter_max )
{
error = 0.0;
laplace2d(T, Tnew, &error);
if (iter % 100 == 0 ) printf("%d, %0.6f\n", iter, error);
if (error < tol) break;
iter++;
}
free(T);
free(Tnew);
free(x);
free(y);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// problem parameters
const double a = 1.;
const double b = 1.;
const int nx = 1024; //number of node points along y
const int ny = 1024; //number of node points along x
//convergence parameters
double tol = 1e-4;
int iter_max = 1000;
double sol_ref(double x, double y)
{
return sin(M_PI*x)*exp(-M_PI*y);
}
void discretisation(double *x, double *y)
{
double dx = a/nx; // spatial step along x
double dy = b/ny; // spatial step along y
for (int i=0; i<=nx; i++)
{
x[i] = i*dx;
y[i] = i*dy;
}
}
void boundary(double *T, double *x, double *y)
{
/*Boundary conditions along the x axis for all processes */
for ( int i=0; i<=nx; i++)
{
T[i*nx] = sol_ref(x[i], y[0]);
T[i*ny+ny] = sol_ref(x[i], y[ny]);
}
/*Boundary conditions along the y axis for all processes */
for ( int j=0; j<=ny; j++)
{
T[j] = sol_ref(x[0], y[j]);
T[nx*ny+j] = sol_ref(x[nx], y[j]);
}
}
void laplace2d(double *T, double *Tnew, double *error)
{
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
Tnew[j*nx + i] = 0.25 * ( T[j*nx + (i+1)] + T[j*nx + (i-1)] + T[(j-1)*nx + i] + T[(j+1)*nx + i] );
*error = fmax(*error, fabs(Tnew[j*nx + i] - T[j*nx + i]));
}
}
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
T[j*nx + i] = Tnew[j*nx + i];
}
}
}
int main(int argc,char **argv)
{
double tol = 1e-4;
int iter = 0;
double error;
double *T = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *Tnew = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *x = (double*) malloc(nx * sizeof(double));
double *y = (double*) malloc(ny * sizeof(double));
if(!x || !y || !T || !Tnew ) return 0;
discretisation(x, y);
boundary(T, x, y);
while (iter < iter_max )
{
error = 0.0;
laplace2d(T, Tnew, &error);
if (iter % 100 == 0 ) printf("%d, %0.6f\n", iter, error);
if (error < tol) break;
iter++;
}
free(T);
free(Tnew);
free(x);
free(y);
return 0;
} | .file "tmpxft_0018a530_00000000-6_laplace2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sol_refdd
.type _Z7sol_refdd, @function
_Z7sol_refdd:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm1, 8(%rsp)
mulsd .LC0(%rip), %xmm0
call sin@PLT
movsd %xmm0, (%rsp)
movsd 8(%rsp), %xmm2
mulsd .LC1(%rip), %xmm2
movapd %xmm2, %xmm0
call exp@PLT
mulsd (%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7sol_refdd, .-_Z7sol_refdd
.globl _Z14discretisationPdS_
.type _Z14discretisationPdS_, @function
_Z14discretisationPdS_:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %eax
movsd .LC2(%rip), %xmm1
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
movsd %xmm0, (%rsi,%rax,8)
addq $1, %rax
cmpq $1025, %rax
jne .L6
ret
.cfi_endproc
.LFE2058:
.size _Z14discretisationPdS_, .-_Z14discretisationPdS_
.globl _Z8boundaryPdS_S_
.type _Z8boundaryPdS_S_, @function
_Z8boundaryPdS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %rbp
movq %rsi, %r12
movq %rdi, %rbx
leaq 8396800(%rdi), %r15
.L9:
movsd (%r12), %xmm0
movsd 0(%rbp), %xmm1
call _Z7sol_refdd
movsd %xmm0, (%rbx)
movsd (%r12), %xmm0
movsd 8192(%rbp), %xmm1
call _Z7sol_refdd
movsd %xmm0, 8192(%rbx)
addq $8, %r12
addq $8192, %rbx
cmpq %r15, %rbx
jne .L9
movl $0, %ebx
.L10:
movsd (%r14), %xmm0
movsd 0(%rbp,%rbx), %xmm1
call _Z7sol_refdd
movsd %xmm0, 0(%r13,%rbx)
movsd 8192(%r14), %xmm0
movsd 0(%rbp,%rbx), %xmm1
call _Z7sol_refdd
movsd %xmm0, 8388608(%r13,%rbx)
addq $8, %rbx
cmpq $8200, %rbx
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8boundaryPdS_S_, .-_Z8boundaryPdS_S_
.globl _Z9laplace2dPdS_S_
.type _Z9laplace2dPdS_S_, @function
_Z9laplace2dPdS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movq %rsi, %r15
movq %rdx, %r12
leaq 8200(%rsi), %rax
movq %rax, (%rsp)
leaq 16376(%rdi), %r13
movl $1024, 12(%rsp)
.L15:
addl $1024, 12(%rsp)
leaq -8184(%r13), %rbx
movq (%rsp), %rbp
.L16:
movsd 16(%rbx), %xmm0
addsd (%rbx), %xmm0
addsd -8184(%rbx), %xmm0
addsd 8200(%rbx), %xmm0
mulsd .LC3(%rip), %xmm0
movsd %xmm0, 0(%rbp)
subsd 8(%rbx), %xmm0
andpd .LC4(%rip), %xmm0
movsd (%r12), %xmm1
call fmax@PLT
movsd %xmm0, (%r12)
addq $8, %rbx
addq $8, %rbp
cmpq %r13, %rbx
jne .L16
addq $8192, (%rsp)
addq $8192, %r13
cmpl $1048576, 12(%rsp)
jne .L15
movl $16384, %edx
.L17:
leaq -8184(%rdx), %rax
.L18:
movsd (%r15,%rax), %xmm0
movsd %xmm0, (%r14,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L18
addq $8192, %rdx
cmpq $8396800, %rdx
jne .L17
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9laplace2dPdS_S_, .-_Z9laplace2dPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "%d, %0.6f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $8405000, %edi
call malloc@PLT
movq %rax, %rbp
movl $8405000, %edi
call malloc@PLT
movq %rax, %r12
movl $8192, %edi
call malloc@PLT
movq %rax, %r15
movl $8192, %edi
call malloc@PLT
testq %r15, %r15
je .L25
movq %rax, %r14
testq %rax, %rax
je .L25
testq %rbp, %rbp
je .L25
testq %r12, %r12
je .L25
movq %rax, %rsi
movq %r15, %rdi
call _Z14discretisationPdS_
movq %r14, %rdx
movq %r15, %rsi
movq %rbp, %rdi
call _Z8boundaryPdS_S_
cmpl $0, iter_max(%rip)
jle .L26
movl $0, %ebx
movq %rsp, %r13
jmp .L28
.L27:
movsd .LC7(%rip), %xmm1
comisd (%rsp), %xmm1
ja .L26
addl $1, %ebx
cmpl %ebx, iter_max(%rip)
jle .L26
.L28:
movq $0x000000000, (%rsp)
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z9laplace2dPdS_S_
movslq %ebx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %ebx
jne .L27
movsd (%rsp), %xmm0
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L27
.L26:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
.L25:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl iter_max
.data
.align 4
.type iter_max, @object
.size iter_max, 4
iter_max:
.long 1000
.globl tol
.align 8
.type tol, @object
.size tol, 8
tol:
.long -350469331
.long 1058682594
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1074340347
.align 8
.LC1:
.long 1413754136
.long -1073143301
.align 8
.LC2:
.long 0
.long 1062207488
.align 8
.LC3:
.long 0
.long 1070596096
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC7:
.long -350469331
.long 1058682594
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// problem parameters
const double a = 1.;
const double b = 1.;
const int nx = 1024; //number of node points along y
const int ny = 1024; //number of node points along x
//convergence parameters
double tol = 1e-4;
int iter_max = 1000;
double sol_ref(double x, double y)
{
return sin(M_PI*x)*exp(-M_PI*y);
}
void discretisation(double *x, double *y)
{
double dx = a/nx; // spatial step along x
double dy = b/ny; // spatial step along y
for (int i=0; i<=nx; i++)
{
x[i] = i*dx;
y[i] = i*dy;
}
}
void boundary(double *T, double *x, double *y)
{
/*Boundary conditions along the x axis for all processes */
for ( int i=0; i<=nx; i++)
{
T[i*nx] = sol_ref(x[i], y[0]);
T[i*ny+ny] = sol_ref(x[i], y[ny]);
}
/*Boundary conditions along the y axis for all processes */
for ( int j=0; j<=ny; j++)
{
T[j] = sol_ref(x[0], y[j]);
T[nx*ny+j] = sol_ref(x[nx], y[j]);
}
}
void laplace2d(double *T, double *Tnew, double *error)
{
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
Tnew[j*nx + i] = 0.25 * ( T[j*nx + (i+1)] + T[j*nx + (i-1)] + T[(j-1)*nx + i] + T[(j+1)*nx + i] );
*error = fmax(*error, fabs(Tnew[j*nx + i] - T[j*nx + i]));
}
}
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
T[j*nx + i] = Tnew[j*nx + i];
}
}
}
int main(int argc,char **argv)
{
double tol = 1e-4;
int iter = 0;
double error;
double *T = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *Tnew = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *x = (double*) malloc(nx * sizeof(double));
double *y = (double*) malloc(ny * sizeof(double));
if(!x || !y || !T || !Tnew ) return 0;
discretisation(x, y);
boundary(T, x, y);
while (iter < iter_max )
{
error = 0.0;
laplace2d(T, Tnew, &error);
if (iter % 100 == 0 ) printf("%d, %0.6f\n", iter, error);
if (error < tol) break;
iter++;
}
free(T);
free(Tnew);
free(x);
free(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// problem parameters
const double a = 1.;
const double b = 1.;
const int nx = 1024; //number of node points along y
const int ny = 1024; //number of node points along x
//convergence parameters
double tol = 1e-4;
int iter_max = 1000;
double sol_ref(double x, double y)
{
return sin(M_PI*x)*exp(-M_PI*y);
}
void discretisation(double *x, double *y)
{
double dx = a/nx; // spatial step along x
double dy = b/ny; // spatial step along y
for (int i=0; i<=nx; i++)
{
x[i] = i*dx;
y[i] = i*dy;
}
}
void boundary(double *T, double *x, double *y)
{
/*Boundary conditions along the x axis for all processes */
for ( int i=0; i<=nx; i++)
{
T[i*nx] = sol_ref(x[i], y[0]);
T[i*ny+ny] = sol_ref(x[i], y[ny]);
}
/*Boundary conditions along the y axis for all processes */
for ( int j=0; j<=ny; j++)
{
T[j] = sol_ref(x[0], y[j]);
T[nx*ny+j] = sol_ref(x[nx], y[j]);
}
}
void laplace2d(double *T, double *Tnew, double *error)
{
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
Tnew[j*nx + i] = 0.25 * ( T[j*nx + (i+1)] + T[j*nx + (i-1)] + T[(j-1)*nx + i] + T[(j+1)*nx + i] );
*error = fmax(*error, fabs(Tnew[j*nx + i] - T[j*nx + i]));
}
}
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
T[j*nx + i] = Tnew[j*nx + i];
}
}
}
int main(int argc,char **argv)
{
double tol = 1e-4;
int iter = 0;
double error;
double *T = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *Tnew = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *x = (double*) malloc(nx * sizeof(double));
double *y = (double*) malloc(ny * sizeof(double));
if(!x || !y || !T || !Tnew ) return 0;
discretisation(x, y);
boundary(T, x, y);
while (iter < iter_max )
{
error = 0.0;
laplace2d(T, Tnew, &error);
if (iter % 100 == 0 ) printf("%d, %0.6f\n", iter, error);
if (error < tol) break;
iter++;
}
free(T);
free(Tnew);
free(x);
free(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// problem parameters
const double a = 1.;
const double b = 1.;
const int nx = 1024; //number of node points along y
const int ny = 1024; //number of node points along x
//convergence parameters
double tol = 1e-4;
int iter_max = 1000;
double sol_ref(double x, double y)
{
return sin(M_PI*x)*exp(-M_PI*y);
}
void discretisation(double *x, double *y)
{
double dx = a/nx; // spatial step along x
double dy = b/ny; // spatial step along y
for (int i=0; i<=nx; i++)
{
x[i] = i*dx;
y[i] = i*dy;
}
}
void boundary(double *T, double *x, double *y)
{
/*Boundary conditions along the x axis for all processes */
for ( int i=0; i<=nx; i++)
{
T[i*nx] = sol_ref(x[i], y[0]);
T[i*ny+ny] = sol_ref(x[i], y[ny]);
}
/*Boundary conditions along the y axis for all processes */
for ( int j=0; j<=ny; j++)
{
T[j] = sol_ref(x[0], y[j]);
T[nx*ny+j] = sol_ref(x[nx], y[j]);
}
}
void laplace2d(double *T, double *Tnew, double *error)
{
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
Tnew[j*nx + i] = 0.25 * ( T[j*nx + (i+1)] + T[j*nx + (i-1)] + T[(j-1)*nx + i] + T[(j+1)*nx + i] );
*error = fmax(*error, fabs(Tnew[j*nx + i] - T[j*nx + i]));
}
}
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
T[j*nx + i] = Tnew[j*nx + i];
}
}
}
int main(int argc,char **argv)
{
double tol = 1e-4;
int iter = 0;
double error;
double *T = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *Tnew = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *x = (double*) malloc(nx * sizeof(double));
double *y = (double*) malloc(ny * sizeof(double));
if(!x || !y || !T || !Tnew ) return 0;
discretisation(x, y);
boundary(T, x, y);
while (iter < iter_max )
{
error = 0.0;
laplace2d(T, Tnew, &error);
if (iter % 100 == 0 ) printf("%d, %0.6f\n", iter, error);
if (error < tol) break;
iter++;
}
free(T);
free(Tnew);
free(x);
free(y);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// problem parameters
const double a = 1.;
const double b = 1.;
const int nx = 1024; //number of node points along y
const int ny = 1024; //number of node points along x
//convergence parameters
double tol = 1e-4;
int iter_max = 1000;
double sol_ref(double x, double y)
{
return sin(M_PI*x)*exp(-M_PI*y);
}
void discretisation(double *x, double *y)
{
double dx = a/nx; // spatial step along x
double dy = b/ny; // spatial step along y
for (int i=0; i<=nx; i++)
{
x[i] = i*dx;
y[i] = i*dy;
}
}
void boundary(double *T, double *x, double *y)
{
/*Boundary conditions along the x axis for all processes */
for ( int i=0; i<=nx; i++)
{
T[i*nx] = sol_ref(x[i], y[0]);
T[i*ny+ny] = sol_ref(x[i], y[ny]);
}
/*Boundary conditions along the y axis for all processes */
for ( int j=0; j<=ny; j++)
{
T[j] = sol_ref(x[0], y[j]);
T[nx*ny+j] = sol_ref(x[nx], y[j]);
}
}
void laplace2d(double *T, double *Tnew, double *error)
{
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
Tnew[j*nx + i] = 0.25 * ( T[j*nx + (i+1)] + T[j*nx + (i-1)] + T[(j-1)*nx + i] + T[(j+1)*nx + i] );
*error = fmax(*error, fabs(Tnew[j*nx + i] - T[j*nx + i]));
}
}
for( int j = 1; j <= nx-1; j++)
{
for( int i = 1; i <= ny-1; i++)
{
T[j*nx + i] = Tnew[j*nx + i];
}
}
}
int main(int argc,char **argv)
{
double tol = 1e-4;
int iter = 0;
double error;
double *T = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *Tnew = (double*) malloc(sizeof(double) * (nx+1) * (ny+1));
double *x = (double*) malloc(nx * sizeof(double));
double *y = (double*) malloc(ny * sizeof(double));
if(!x || !y || !T || !Tnew ) return 0;
discretisation(x, y);
boundary(T, x, y);
while (iter < iter_max )
{
error = 0.0;
laplace2d(T, Tnew, &error);
if (iter % 100 == 0 ) printf("%d, %0.6f\n", iter, error);
if (error < tol) break;
iter++;
}
free(T);
free(Tnew);
free(x);
free(y);
return 0;
} | .text
.file "laplace2d.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7sol_refdd
.LCPI0_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI0_1:
.quad 0xc00921fb54442d18 # double -3.1415926535897931
.text
.globl _Z7sol_refdd
.p2align 4, 0x90
.type _Z7sol_refdd,@function
_Z7sol_refdd: # @_Z7sol_refdd
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm1, 16(%rsp) # 8-byte Spill
mulsd .LCPI0_0(%rip), %xmm0
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI0_1(%rip), %xmm0
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7sol_refdd, .Lfunc_end0-_Z7sol_refdd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14discretisationPdS_
.LCPI1_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z14discretisationPdS_
.p2align 4, 0x90
.type _Z14discretisationPdS_,@function
_Z14discretisationPdS_: # @_Z14discretisationPdS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%rdi,%rax,8)
movsd %xmm1, (%rsi,%rax,8)
incq %rax
cmpq $1025, %rax # imm = 0x401
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z14discretisationPdS_, .Lfunc_end1-_Z14discretisationPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8boundaryPdS_S_
.LCPI2_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_1:
.quad 0xc00921fb54442d18 # double -3.1415926535897931
.text
.globl _Z8boundaryPdS_S_
.p2align 4, 0x90
.type _Z8boundaryPdS_S_,@function
_Z8boundaryPdS_S_: # @_Z8boundaryPdS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 8192(%rdi), %r12
xorl %r13d, %r13d
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movsd (%rbx), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm2, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, -8192(%r12)
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
mulsd .LCPI2_0(%rip), %xmm0
movsd 8192(%rbx), %xmm1 # xmm1 = mem[0],zero
mulsd .LCPI2_1(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r12)
incq %r13
addq $8192, %r12 # imm = 0x2000
cmpq $1025, %r13 # imm = 0x401
jne .LBB2_1
# %bb.2: # %.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movsd (%rbx,%r12,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm2, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r15,%r12,8)
movsd 8192(%r14), %xmm0 # xmm0 = mem[0],zero
mulsd .LCPI2_0(%rip), %xmm0
movsd (%rbx,%r12,8), %xmm1 # xmm1 = mem[0],zero
mulsd .LCPI2_1(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8388608(%r15,%r12,8)
incq %r12
cmpq $1025, %r12 # imm = 0x401
jne .LBB2_3
# %bb.4:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8boundaryPdS_S_, .Lfunc_end2-_Z8boundaryPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9laplace2dPdS_S_
.LCPI3_0:
.quad 0x3fd0000000000000 # double 0.25
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z9laplace2dPdS_S_
.p2align 4, 0x90
.type _Z9laplace2dPdS_S_,@function
_Z9laplace2dPdS_S_: # @_Z9laplace2dPdS_S_
.cfi_startproc
# %bb.0:
leaq 16392(%rdi), %rax
leaq 8200(%rsi), %rcx
movl $1, %r8d
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI3_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB3_1: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movq $-1023, %r9 # imm = 0xFC01
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%r9,8), %xmm2 # xmm2 = mem[0],zero
addsd -16(%rax,%r9,8), %xmm2
addsd -8200(%rax,%r9,8), %xmm2
addsd 8184(%rax,%r9,8), %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, 8184(%rcx,%r9,8)
movsd (%rdx), %xmm3 # xmm3 = mem[0],zero
subsd -8(%rax,%r9,8), %xmm2
andpd %xmm1, %xmm2
movapd %xmm3, %xmm4
cmpunordsd %xmm3, %xmm4
movapd %xmm4, %xmm5
andpd %xmm2, %xmm5
maxsd %xmm3, %xmm2
andnpd %xmm2, %xmm4
orpd %xmm5, %xmm4
movlpd %xmm4, (%rdx)
incq %r9
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r8
addq $8192, %rax # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %r8 # imm = 0x400
jne .LBB3_1
# %bb.4: # %.preheader.preheader
addq $8200, %rdi # imm = 0x2008
addq $8200, %rsi # imm = 0x2008
movl $1, %eax
.p2align 4, 0x90
.LBB3_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdi,%rcx,8)
incq %rcx
cmpq $1023, %rcx # imm = 0x3FF
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
incq %rax
addq $8192, %rdi # imm = 0x2000
addq $8192, %rsi # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB3_5
# %bb.8:
retq
.Lfunc_end3:
.size _Z9laplace2dPdS_S_, .Lfunc_end3-_Z9laplace2dPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI4_1:
.quad 0x3fd0000000000000 # double 0.25
.LCPI4_3:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %rbx
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
movl $8192, %edi # imm = 0x2000
callq malloc
testq %r14, %r14
je .LBB4_19
# %bb.1:
testq %rbx, %rbx
je .LBB4_19
# %bb.2:
testq %r15, %r15
je .LBB4_19
# %bb.3:
movq %rax, %r12
testq %rax, %rax
je .LBB4_19
# %bb.4: # %.preheader.preheader
movq %r14, 8(%rsp) # 8-byte Spill
xorl %eax, %eax
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB4_5: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rax,8)
movsd %xmm1, (%r12,%rax,8)
incq %rax
cmpq $1025, %rax # imm = 0x401
jne .LBB4_5
# %bb.6: # %_Z14discretisationPdS_.exit
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq _Z8boundaryPdS_S_
cmpl $0, iter_max(%rip)
jle .LBB4_18
# %bb.7: # %.preheader40.i.preheader.lr.ph
movq 16(%rsp), %rbx # 8-byte Reload
leaq 16392(%rbx), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq 8(%rsp), %r14 # 8-byte Reload
addq $8200, %r14 # imm = 0x2008
addq $8200, %rbx # imm = 0x2008
xorl %r13d, %r13d
movsd .LCPI4_1(%rip), %xmm3 # xmm3 = mem[0],zero
movapd .LCPI4_2(%rip), %xmm4 # xmm4 = [NaN,NaN]
.p2align 4, 0x90
.LBB4_9: # %.preheader40.i.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
# Child Loop BB4_11 Depth 3
# Child Loop BB4_14 Depth 2
movl $1, %eax
xorpd %xmm5, %xmm5
movq %r14, %rcx
movq 32(%rsp), %rdx # 8-byte Reload
.p2align 4, 0x90
.LBB4_10: # %.preheader40.i
# Parent Loop BB4_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_11 Depth 3
movq $-1023, %rsi # imm = 0xFC01
movapd %xmm5, %xmm0
.p2align 4, 0x90
.LBB4_11: # Parent Loop BB4_9 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
addsd -16(%rdx,%rsi,8), %xmm1
addsd -8200(%rdx,%rsi,8), %xmm1
addsd 8184(%rdx,%rsi,8), %xmm1
mulsd %xmm3, %xmm1
movsd %xmm1, 8184(%rcx,%rsi,8)
subsd -8(%rdx,%rsi,8), %xmm1
andpd %xmm4, %xmm1
cmpunordsd %xmm0, %xmm0
movapd %xmm0, %xmm2
andpd %xmm1, %xmm2
maxsd %xmm5, %xmm1
andnpd %xmm1, %xmm0
orpd %xmm2, %xmm0
movapd %xmm0, %xmm5
incq %rsi
jne .LBB4_11
# %bb.12: # in Loop: Header=BB4_10 Depth=2
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB4_10
# %bb.13: # %.preheader.i.preheader
# in Loop: Header=BB4_9 Depth=1
movsd %xmm5, 24(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_14: # %.preheader.i
# Parent Loop BB4_9 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%rbx,%rbp), %rdi
leaq (%r14,%rbp), %rsi
movl $8184, %edx # imm = 0x1FF8
callq memcpy@PLT
addq $8192, %rbp # imm = 0x2000
cmpq $8380416, %rbp # imm = 0x7FE000
jne .LBB4_14
# %bb.15: # %_Z9laplace2dPdS_S_.exit
# in Loop: Header=BB4_9 Depth=1
imull $-1030792151, %r13d, %eax # imm = 0xC28F5C29
rorl $2, %eax
cmpl $42949672, %eax # imm = 0x28F5C28
ja .LBB4_17
# %bb.16: # in Loop: Header=BB4_9 Depth=1
movl $.L.str, %edi
movl %r13d, %esi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
.LBB4_17: # in Loop: Header=BB4_9 Depth=1
movsd .LCPI4_3(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd .LCPI4_1(%rip), %xmm3 # xmm3 = mem[0],zero
movapd .LCPI4_2(%rip), %xmm4 # xmm4 = [NaN,NaN]
ja .LBB4_18
# %bb.8: # in Loop: Header=BB4_9 Depth=1
incl %r13d
cmpl iter_max(%rip), %r13d
jl .LBB4_9
.LBB4_18: # %._crit_edge
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
.LBB4_19:
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.type tol,@object # @tol
.data
.globl tol
.p2align 3, 0x0
tol:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.size tol, 8
.type iter_max,@object # @iter_max
.globl iter_max
.p2align 2, 0x0
iter_max:
.long 1000 # 0x3e8
.size iter_max, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, %0.6f\n"
.size .L.str, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018a530_00000000-6_laplace2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sol_refdd
.type _Z7sol_refdd, @function
_Z7sol_refdd:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm1, 8(%rsp)
mulsd .LC0(%rip), %xmm0
call sin@PLT
movsd %xmm0, (%rsp)
movsd 8(%rsp), %xmm2
mulsd .LC1(%rip), %xmm2
movapd %xmm2, %xmm0
call exp@PLT
mulsd (%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7sol_refdd, .-_Z7sol_refdd
.globl _Z14discretisationPdS_
.type _Z14discretisationPdS_, @function
_Z14discretisationPdS_:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %eax
movsd .LC2(%rip), %xmm1
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
movsd %xmm0, (%rsi,%rax,8)
addq $1, %rax
cmpq $1025, %rax
jne .L6
ret
.cfi_endproc
.LFE2058:
.size _Z14discretisationPdS_, .-_Z14discretisationPdS_
.globl _Z8boundaryPdS_S_
.type _Z8boundaryPdS_S_, @function
_Z8boundaryPdS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %rbp
movq %rsi, %r12
movq %rdi, %rbx
leaq 8396800(%rdi), %r15
.L9:
movsd (%r12), %xmm0
movsd 0(%rbp), %xmm1
call _Z7sol_refdd
movsd %xmm0, (%rbx)
movsd (%r12), %xmm0
movsd 8192(%rbp), %xmm1
call _Z7sol_refdd
movsd %xmm0, 8192(%rbx)
addq $8, %r12
addq $8192, %rbx
cmpq %r15, %rbx
jne .L9
movl $0, %ebx
.L10:
movsd (%r14), %xmm0
movsd 0(%rbp,%rbx), %xmm1
call _Z7sol_refdd
movsd %xmm0, 0(%r13,%rbx)
movsd 8192(%r14), %xmm0
movsd 0(%rbp,%rbx), %xmm1
call _Z7sol_refdd
movsd %xmm0, 8388608(%r13,%rbx)
addq $8, %rbx
cmpq $8200, %rbx
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8boundaryPdS_S_, .-_Z8boundaryPdS_S_
.globl _Z9laplace2dPdS_S_
.type _Z9laplace2dPdS_S_, @function
_Z9laplace2dPdS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movq %rsi, %r15
movq %rdx, %r12
leaq 8200(%rsi), %rax
movq %rax, (%rsp)
leaq 16376(%rdi), %r13
movl $1024, 12(%rsp)
.L15:
addl $1024, 12(%rsp)
leaq -8184(%r13), %rbx
movq (%rsp), %rbp
.L16:
movsd 16(%rbx), %xmm0
addsd (%rbx), %xmm0
addsd -8184(%rbx), %xmm0
addsd 8200(%rbx), %xmm0
mulsd .LC3(%rip), %xmm0
movsd %xmm0, 0(%rbp)
subsd 8(%rbx), %xmm0
andpd .LC4(%rip), %xmm0
movsd (%r12), %xmm1
call fmax@PLT
movsd %xmm0, (%r12)
addq $8, %rbx
addq $8, %rbp
cmpq %r13, %rbx
jne .L16
addq $8192, (%rsp)
addq $8192, %r13
cmpl $1048576, 12(%rsp)
jne .L15
movl $16384, %edx
.L17:
leaq -8184(%rdx), %rax
.L18:
movsd (%r15,%rax), %xmm0
movsd %xmm0, (%r14,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L18
addq $8192, %rdx
cmpq $8396800, %rdx
jne .L17
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9laplace2dPdS_S_, .-_Z9laplace2dPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "%d, %0.6f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $8405000, %edi
call malloc@PLT
movq %rax, %rbp
movl $8405000, %edi
call malloc@PLT
movq %rax, %r12
movl $8192, %edi
call malloc@PLT
movq %rax, %r15
movl $8192, %edi
call malloc@PLT
testq %r15, %r15
je .L25
movq %rax, %r14
testq %rax, %rax
je .L25
testq %rbp, %rbp
je .L25
testq %r12, %r12
je .L25
movq %rax, %rsi
movq %r15, %rdi
call _Z14discretisationPdS_
movq %r14, %rdx
movq %r15, %rsi
movq %rbp, %rdi
call _Z8boundaryPdS_S_
cmpl $0, iter_max(%rip)
jle .L26
movl $0, %ebx
movq %rsp, %r13
jmp .L28
.L27:
movsd .LC7(%rip), %xmm1
comisd (%rsp), %xmm1
ja .L26
addl $1, %ebx
cmpl %ebx, iter_max(%rip)
jle .L26
.L28:
movq $0x000000000, (%rsp)
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z9laplace2dPdS_S_
movslq %ebx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %ebx
jne .L27
movsd (%rsp), %xmm0
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L27
.L26:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
.L25:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl iter_max
.data
.align 4
.type iter_max, @object
.size iter_max, 4
iter_max:
.long 1000
.globl tol
.align 8
.type tol, @object
.size tol, 8
tol:
.long -350469331
.long 1058682594
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1074340347
.align 8
.LC1:
.long 1413754136
.long -1073143301
.align 8
.LC2:
.long 0
.long 1062207488
.align 8
.LC3:
.long 0
.long 1070596096
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC7:
.long -350469331
.long 1058682594
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "laplace2d.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7sol_refdd
.LCPI0_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI0_1:
.quad 0xc00921fb54442d18 # double -3.1415926535897931
.text
.globl _Z7sol_refdd
.p2align 4, 0x90
.type _Z7sol_refdd,@function
_Z7sol_refdd: # @_Z7sol_refdd
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm1, 16(%rsp) # 8-byte Spill
mulsd .LCPI0_0(%rip), %xmm0
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI0_1(%rip), %xmm0
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7sol_refdd, .Lfunc_end0-_Z7sol_refdd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14discretisationPdS_
.LCPI1_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z14discretisationPdS_
.p2align 4, 0x90
.type _Z14discretisationPdS_,@function
_Z14discretisationPdS_: # @_Z14discretisationPdS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%rdi,%rax,8)
movsd %xmm1, (%rsi,%rax,8)
incq %rax
cmpq $1025, %rax # imm = 0x401
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z14discretisationPdS_, .Lfunc_end1-_Z14discretisationPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8boundaryPdS_S_
.LCPI2_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_1:
.quad 0xc00921fb54442d18 # double -3.1415926535897931
.text
.globl _Z8boundaryPdS_S_
.p2align 4, 0x90
.type _Z8boundaryPdS_S_,@function
_Z8boundaryPdS_S_: # @_Z8boundaryPdS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 8192(%rdi), %r12
xorl %r13d, %r13d
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movsd (%rbx), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm2, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, -8192(%r12)
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
mulsd .LCPI2_0(%rip), %xmm0
movsd 8192(%rbx), %xmm1 # xmm1 = mem[0],zero
mulsd .LCPI2_1(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r12)
incq %r13
addq $8192, %r12 # imm = 0x2000
cmpq $1025, %r13 # imm = 0x401
jne .LBB2_1
# %bb.2: # %.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
movsd (%rbx,%r12,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm2, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r15,%r12,8)
movsd 8192(%r14), %xmm0 # xmm0 = mem[0],zero
mulsd .LCPI2_0(%rip), %xmm0
movsd (%rbx,%r12,8), %xmm1 # xmm1 = mem[0],zero
mulsd .LCPI2_1(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq exp
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8388608(%r15,%r12,8)
incq %r12
cmpq $1025, %r12 # imm = 0x401
jne .LBB2_3
# %bb.4:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8boundaryPdS_S_, .Lfunc_end2-_Z8boundaryPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9laplace2dPdS_S_
.LCPI3_0:
.quad 0x3fd0000000000000 # double 0.25
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z9laplace2dPdS_S_
.p2align 4, 0x90
.type _Z9laplace2dPdS_S_,@function
_Z9laplace2dPdS_S_: # @_Z9laplace2dPdS_S_
.cfi_startproc
# %bb.0:
leaq 16392(%rdi), %rax
leaq 8200(%rsi), %rcx
movl $1, %r8d
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI3_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB3_1: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movq $-1023, %r9 # imm = 0xFC01
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%r9,8), %xmm2 # xmm2 = mem[0],zero
addsd -16(%rax,%r9,8), %xmm2
addsd -8200(%rax,%r9,8), %xmm2
addsd 8184(%rax,%r9,8), %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, 8184(%rcx,%r9,8)
movsd (%rdx), %xmm3 # xmm3 = mem[0],zero
subsd -8(%rax,%r9,8), %xmm2
andpd %xmm1, %xmm2
movapd %xmm3, %xmm4
cmpunordsd %xmm3, %xmm4
movapd %xmm4, %xmm5
andpd %xmm2, %xmm5
maxsd %xmm3, %xmm2
andnpd %xmm2, %xmm4
orpd %xmm5, %xmm4
movlpd %xmm4, (%rdx)
incq %r9
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r8
addq $8192, %rax # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %r8 # imm = 0x400
jne .LBB3_1
# %bb.4: # %.preheader.preheader
addq $8200, %rdi # imm = 0x2008
addq $8200, %rsi # imm = 0x2008
movl $1, %eax
.p2align 4, 0x90
.LBB3_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdi,%rcx,8)
incq %rcx
cmpq $1023, %rcx # imm = 0x3FF
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
incq %rax
addq $8192, %rdi # imm = 0x2000
addq $8192, %rsi # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB3_5
# %bb.8:
retq
.Lfunc_end3:
.size _Z9laplace2dPdS_S_, .Lfunc_end3-_Z9laplace2dPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI4_1:
.quad 0x3fd0000000000000 # double 0.25
.LCPI4_3:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %rbx
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
movl $8192, %edi # imm = 0x2000
callq malloc
testq %r14, %r14
je .LBB4_19
# %bb.1:
testq %rbx, %rbx
je .LBB4_19
# %bb.2:
testq %r15, %r15
je .LBB4_19
# %bb.3:
movq %rax, %r12
testq %rax, %rax
je .LBB4_19
# %bb.4: # %.preheader.preheader
movq %r14, 8(%rsp) # 8-byte Spill
xorl %eax, %eax
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB4_5: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rax,8)
movsd %xmm1, (%r12,%rax,8)
incq %rax
cmpq $1025, %rax # imm = 0x401
jne .LBB4_5
# %bb.6: # %_Z14discretisationPdS_.exit
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq _Z8boundaryPdS_S_
cmpl $0, iter_max(%rip)
jle .LBB4_18
# %bb.7: # %.preheader40.i.preheader.lr.ph
movq 16(%rsp), %rbx # 8-byte Reload
leaq 16392(%rbx), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq 8(%rsp), %r14 # 8-byte Reload
addq $8200, %r14 # imm = 0x2008
addq $8200, %rbx # imm = 0x2008
xorl %r13d, %r13d
movsd .LCPI4_1(%rip), %xmm3 # xmm3 = mem[0],zero
movapd .LCPI4_2(%rip), %xmm4 # xmm4 = [NaN,NaN]
.p2align 4, 0x90
.LBB4_9: # %.preheader40.i.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
# Child Loop BB4_11 Depth 3
# Child Loop BB4_14 Depth 2
movl $1, %eax
xorpd %xmm5, %xmm5
movq %r14, %rcx
movq 32(%rsp), %rdx # 8-byte Reload
.p2align 4, 0x90
.LBB4_10: # %.preheader40.i
# Parent Loop BB4_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_11 Depth 3
movq $-1023, %rsi # imm = 0xFC01
movapd %xmm5, %xmm0
.p2align 4, 0x90
.LBB4_11: # Parent Loop BB4_9 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
addsd -16(%rdx,%rsi,8), %xmm1
addsd -8200(%rdx,%rsi,8), %xmm1
addsd 8184(%rdx,%rsi,8), %xmm1
mulsd %xmm3, %xmm1
movsd %xmm1, 8184(%rcx,%rsi,8)
subsd -8(%rdx,%rsi,8), %xmm1
andpd %xmm4, %xmm1
cmpunordsd %xmm0, %xmm0
movapd %xmm0, %xmm2
andpd %xmm1, %xmm2
maxsd %xmm5, %xmm1
andnpd %xmm1, %xmm0
orpd %xmm2, %xmm0
movapd %xmm0, %xmm5
incq %rsi
jne .LBB4_11
# %bb.12: # in Loop: Header=BB4_10 Depth=2
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB4_10
# %bb.13: # %.preheader.i.preheader
# in Loop: Header=BB4_9 Depth=1
movsd %xmm5, 24(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_14: # %.preheader.i
# Parent Loop BB4_9 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%rbx,%rbp), %rdi
leaq (%r14,%rbp), %rsi
movl $8184, %edx # imm = 0x1FF8
callq memcpy@PLT
addq $8192, %rbp # imm = 0x2000
cmpq $8380416, %rbp # imm = 0x7FE000
jne .LBB4_14
# %bb.15: # %_Z9laplace2dPdS_S_.exit
# in Loop: Header=BB4_9 Depth=1
imull $-1030792151, %r13d, %eax # imm = 0xC28F5C29
rorl $2, %eax
cmpl $42949672, %eax # imm = 0x28F5C28
ja .LBB4_17
# %bb.16: # in Loop: Header=BB4_9 Depth=1
movl $.L.str, %edi
movl %r13d, %esi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
.LBB4_17: # in Loop: Header=BB4_9 Depth=1
movsd .LCPI4_3(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd .LCPI4_1(%rip), %xmm3 # xmm3 = mem[0],zero
movapd .LCPI4_2(%rip), %xmm4 # xmm4 = [NaN,NaN]
ja .LBB4_18
# %bb.8: # in Loop: Header=BB4_9 Depth=1
incl %r13d
cmpl iter_max(%rip), %r13d
jl .LBB4_9
.LBB4_18: # %._crit_edge
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
.LBB4_19:
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.type tol,@object # @tol
.data
.globl tol
.p2align 3, 0x0
tol:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.size tol, 8
.type iter_max,@object # @iter_max
.globl iter_max
.p2align 2, 0x0
iter_max:
.long 1000 # 0x3e8
.size iter_max, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, %0.6f\n"
.size .L.str, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
int blockSize;
int gridSize;
__global__ void gameOfLife(int *indata, int *outdata, int width, int height)
{
__shared__ int sdata[256];
int tSize=width*height;
int x, y, x0,x1,y0,y1, n;
int bid, cid, tid;
tid = threadIdx.x;
bid = blockIdx.x;
for(cid = blockIdx.x*blockDim.x+tid; cid < tSize; cid += gridDim.x*blockDim.x){
if(tid<width){
x=(cid) % width; // x position
y=(cid) / width; // y position
x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too
x1=(x+1) % width; // one right x positional value
y0=(y-1+height) % height; // one row up y positional value
y1=(y+1) % height; // one row below y positional value
n=indata[y1*width+x0]+indata[y*width+x0]+indata[y0+x0]+indata[y0*width+x]+indata[y0*width+x1]+indata[y*width+x1]+indata[y1*width+x1]+indata[y1*width+x]; // no. of alive neighbor cells
if(n==3 || (n==2 && indata[cid])) // life created or sustains
{
sdata[tid]=1;
//outdata[cid]=1;
}
else // life destroyed or stay died
{
sdata[tid]=0;
//outdata[cid]=0;
}
__syncthreads();
outdata[cid]=sdata[tid];
}
}
}
int main(int argc, char **argv)
{
if(argc ^ 4){
printf("Usage: ./gol seed height width iteration\n");
exit(1);
}
clock_t sTime=clock();
int width= atoi(argv[3]);
int height=atoi(argv[2]);
int dsize=width*height;
int iteration=atoi(argv[3]);
int i, j;
int *data;
int *d_indata, *d_outdata, *temp;
// allocate memory for data in host
data=(int *)malloc(dsize*sizeof(int));
// allocate memory for data in device
cudaMalloc(&d_indata, dsize*sizeof(int));
cudaMalloc(&d_outdata, dsize*sizeof(int));
srand(atoi(argv[0])); // test seed
// initialize data in host as randomly 0 or 1
for(i=0;i<dsize;i++)
{
data[i]=rand()%2;
}
// copy initialized data to gpu device
cudaMemcpy( d_indata, data, dsize, cudaMemcpyHostToDevice );
for(i=0;i<iteration;i++)
{
// call kernel
gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height);
// synchronize between thread blocks
cudaDeviceSynchronize();
// swap d_indata and d_outdata for next iteration
temp=d_indata;
d_indata=d_outdata;
d_outdata=temp;
}
// copy data back from device to host memory
cudaMemcpy( data, d_indata, dsize, cudaMemcpyDeviceToHost);
// diplay cell status in console
printf("\n board status # \n");
for(i=0;i<height;i++)
{
for(j=0;j<width;j++)
{
printf(" %d",data[i*width+j]);
}
printf("\n");
}
// free memory allocated
cudaFree(d_indata);
cudaFree(d_outdata);
free(data);
clock_t eTime=clock();
printf("time taken = %ld",eTime-sTime);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z10gameOfLifePiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26270 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*00a0*/ @P1 BRA 0x8f0 ; /* 0x0000084000001947 */
/* 0x001fea0003800000 */
/*00b0*/ IABS R3, c[0x0][0x170] ; /* 0x00005c0000037a13 */
/* 0x000fe20000000000 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0d7435 */
/* 0x000fe400000001ff */
/*00e0*/ I2F.RP R4, R3 ; /* 0x0000000300047306 */
/* 0x000e300000209400 */
/*00f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R11, R4, 0xffffffe, RZ ; /* 0x0ffffffe040b7810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e24000021f000 */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R11 ; /* 0x000000ffff067224 */
/* 0x001fc800078e0a0b */
/*0130*/ IMAD R5, R6, R3, RZ ; /* 0x0000000306057224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R10, R11, R5, R10 ; /* 0x000000050b0a7227 */
/* 0x000fe200078e000a */
/*0160*/ IABS R5, c[0x0][0x174] ; /* 0x00005d0000057a13 */
/* 0x000fc80000000000 */
/*0170*/ I2F.RP R7, R5 ; /* 0x0000000500077306 */
/* 0x000e220000209400 */
/*0180*/ IMAD.HI.U32 R4, R10, R6, RZ ; /* 0x000000060a047227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R8, RZ, RZ, -R4 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a04 */
/*01a0*/ IMAD R6, R3, R8, R6 ; /* 0x0000000803067224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe20003f44070 */
/*01c0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e180000001000 */
/*01d0*/ @!P2 IADD3 R6, R6, -R3.reuse, RZ ; /* 0x800000030606a210 */
/* 0x080fe40007ffe0ff */
/*01e0*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R6, R2, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0002067a12 */
/* 0x000fe400078e3cff */
/*0210*/ IADD3 R8, R7, 0xffffffe, RZ ; /* 0x0ffffffe07087810 */
/* 0x001fe40007ffe0ff */
/*0220*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc40003f66270 */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*0240*/ LOP3.LUT R7, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff077a12 */
/* 0x000fc800078e33ff */
/*0250*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc600078e00ff */
/*0280*/ @!P3 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04b224 */
/* 0x000fca00078e0a04 */
/*0290*/ SEL R4, R7, R4, !P0 ; /* 0x0000000407047207 */
/* 0x000fe20004000000 */
/*02a0*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc600078e0a09 */
/*02b0*/ IADD3 R21, R4, 0x1, RZ ; /* 0x0000000104157810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV R11, RZ, RZ, -R4 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0a04 */
/*02d0*/ IABS R20, R21 ; /* 0x0000001500147213 */
/* 0x000fe20000000000 */
/*02e0*/ IMAD R6, R11, c[0x0][0x170], R2 ; /* 0x00005c000b067a24 */
/* 0x000fe400078e0202 */
/*02f0*/ IMAD R11, R12, R5, RZ ; /* 0x000000050c0b7224 */
/* 0x000fc600078e02ff */
/*0300*/ IADD3 R17, R6.reuse, c[0x0][0x170], -R13 ; /* 0x00005c0006117a10 */
/* 0x040fe20007ffe80d */
/*0310*/ IMAD.HI.U32 R11, R9, R11, R8 ; /* 0x0000000b090b7227 */
/* 0x000fe200078e0008 */
/*0320*/ IADD3 R19, R6, 0x1, RZ ; /* 0x0000000106137810 */
/* 0x000fe40007ffe0ff */
/*0330*/ IADD3 R8, R4, c[0x0][0x174], -R13 ; /* 0x00005d0004087a10 */
/* 0x000fe40007ffe80d */
/*0340*/ IABS R13, R17 ; /* 0x00000011000d7213 */
/* 0x000fe40000000000 */
/*0350*/ IABS R15, R19 ; /* 0x00000013000f7213 */
/* 0x000fe40000000000 */
/*0360*/ IABS R18, R8 ; /* 0x0000000800127213 */
/* 0x000fe20000000000 */
/*0370*/ IMAD.HI.U32 R9, R10, R13, RZ ; /* 0x0000000d0a097227 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.HI.U32 R10, R10, R15, RZ ; /* 0x0000000f0a0a7227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.HI.U32 R12, R11, R18, RZ ; /* 0x000000120b0c7227 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.MOV R14, RZ, RZ, -R9 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a09 */
/*03b0*/ IADD3 R9, -R12, RZ, RZ ; /* 0x000000ff0c097210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD.MOV R16, RZ, RZ, -R10 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a0a */
/*03d0*/ IMAD R10, R3.reuse, R14, R13 ; /* 0x0000000e030a7224 */
/* 0x040fe400078e020d */
/*03e0*/ IMAD R12, R3, R16, R15 ; /* 0x00000010030c7224 */
/* 0x000fe400078e020f */
/*03f0*/ IMAD.HI.U32 R11, R11, R20, RZ ; /* 0x000000140b0b7227 */
/* 0x000fe200078e00ff */
/*0400*/ ISETP.GT.U32.AND P3, PT, R3.reuse, R10, PT ; /* 0x0000000a0300720c */
/* 0x040fe40003f64070 */
/*0410*/ ISETP.GT.U32.AND P4, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe20003f84070 */
/*0420*/ IMAD R14, R5, R9, R18 ; /* 0x00000009050e7224 */
/* 0x000fc400078e0212 */
/*0430*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0a0b */
/*0440*/ ISETP.GT.U32.AND P5, PT, R5.reuse, R14, PT ; /* 0x0000000e0500720c */
/* 0x040fe20003fa4070 */
/*0450*/ IMAD R16, R5, R11, R20 ; /* 0x0000000b05107224 */
/* 0x000fc800078e0214 */
/*0460*/ @!P3 IMAD.IADD R10, R10, 0x1, -R3.reuse ; /* 0x000000010a0ab824 */
/* 0x100fe200078e0a03 */
/*0470*/ ISETP.GT.U32.AND P2, PT, R5, R16, PT ; /* 0x000000100500720c */
/* 0x000fe20003f44070 */
/*0480*/ @!P4 IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0cc824 */
/* 0x000fc600078e0a03 */
/*0490*/ ISETP.GT.U32.AND P4, PT, R3.reuse, R10, PT ; /* 0x0000000a0300720c */
/* 0x040fe40003f84070 */
/*04a0*/ ISETP.GT.U32.AND P6, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe40003fc4070 */
/*04b0*/ @!P5 IADD3 R14, R14, -R5, RZ ; /* 0x800000050e0ed210 */
/* 0x000fc80007ffe0ff */
/*04c0*/ ISETP.GT.U32.AND P5, PT, R5, R14, PT ; /* 0x0000000e0500720c */
/* 0x000fe20003fa4070 */
/*04d0*/ @!P2 IMAD.IADD R16, R16, 0x1, -R5 ; /* 0x000000011010a824 */
/* 0x000fe200078e0a05 */
/*04e0*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f46270 */
/*04f0*/ @!P4 IMAD.IADD R10, R10, 0x1, -R3.reuse ; /* 0x000000010a0ac824 */
/* 0x100fe200078e0a03 */
/*0500*/ ISETP.GT.U32.AND P3, PT, R5, R16, PT ; /* 0x000000100500720c */
/* 0x000fe20003f64070 */
/*0510*/ @!P6 IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0ce824 */
/* 0x000fe200078e0a03 */
/*0520*/ ISETP.GE.AND P4, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f86270 */
/*0530*/ ISETP.GE.AND P6, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003fc6270 */
/*0540*/ LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff037a12 */
/* 0x000fe400078e33ff */
/*0550*/ @!P5 IADD3 R14, R14, -R5, RZ ; /* 0x800000050e0ed210 */
/* 0x000fe40007ffe0ff */
/*0560*/ ISETP.GE.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc60003fa6270 */
/*0570*/ @!P3 IMAD.IADD R16, R16, 0x1, -R5 ; /* 0x000000011010b824 */
/* 0x000fe200078e0a05 */
/*0580*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f65270 */
/*0590*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe400078e0a0e */
/*05a0*/ @!P4 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff10c224 */
/* 0x000fe200078e0a10 */
/*05b0*/ @!P6 IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0ae210 */
/* 0x000fe40007ffe1ff */
/*05c0*/ SEL R5, R3.reuse, R14, !P3 ; /* 0x0000000e03057207 */
/* 0x040fe40005800000 */
/*05d0*/ SEL R9, R3, R16, !P3 ; /* 0x0000001003097207 */
/* 0x000fe20005800000 */
/*05e0*/ @!P5 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cd224 */
/* 0x000fe200078e0a0c */
/*05f0*/ SEL R10, R7, R10, !P0 ; /* 0x0000000a070a7207 */
/* 0x000fe20004000000 */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0610*/ SEL R7, R7, R12, !P0 ; /* 0x0000000c07077207 */
/* 0x000fe20004000000 */
/*0620*/ IMAD R14, R4, c[0x0][0x170], R10.reuse ; /* 0x00005c00040e7a24 */
/* 0x100fe400078e020a */
/*0630*/ IMAD R8, R9, c[0x0][0x170], R10 ; /* 0x00005c0009087a24 */
/* 0x000fe400078e020a */
/*0640*/ IMAD.IADD R10, R10, 0x1, R5 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0205 */
/*0650*/ IMAD R12, R5.reuse, c[0x0][0x170], R6 ; /* 0x00005c00050c7a24 */
/* 0x040fe400078e0206 */
/*0660*/ IMAD R18, R4, c[0x0][0x170], R7.reuse ; /* 0x00005c0004127a24 */
/* 0x100fe400078e0207 */
/*0670*/ IMAD R16, R5, c[0x0][0x170], R7 ; /* 0x00005c0005107a24 */
/* 0x000fc400078e0207 */
/*0680*/ IMAD R6, R9, c[0x0][0x170], R6 ; /* 0x00005c0009067a24 */
/* 0x000fe400078e0206 */
/*0690*/ IMAD.WIDE R4, R8, R3, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0203 */
/*06a0*/ IMAD R20, R9, c[0x0][0x170], R7 ; /* 0x00005c0009147a24 */
/* 0x000fe400078e0207 */
/*06b0*/ IMAD.WIDE R8, R10, R3.reuse, c[0x0][0x160] ; /* 0x000058000a087625 */
/* 0x080fe200078e0203 */
/*06c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea6000c1e1900 */
/*06d0*/ IMAD.WIDE R14, R14, R3.reuse, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x080fe400078e0203 */
/*06e0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ IMAD.WIDE R10, R12, R3, c[0x0][0x160] ; /* 0x000058000c0a7625 */
/* 0x000fc400078e0203 */
/*0700*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x000ea4000c1e1900 */
/*0710*/ IMAD.WIDE R12, R16, R3.reuse, c[0x0][0x160] ; /* 0x00005800100c7625 */
/* 0x080fe400078e0203 */
/*0720*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ee4000c1e1900 */
/*0730*/ IMAD.WIDE R16, R18, R3.reuse, c[0x0][0x160] ; /* 0x0000580012107625 */
/* 0x080fe400078e0203 */
/*0740*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ee4000c1e1900 */
/*0750*/ IMAD.WIDE R18, R20, R3, c[0x0][0x160] ; /* 0x0000580014127625 */
/* 0x000fc400078e0203 */
/*0760*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000f24000c1e1900 */
/*0770*/ IMAD.WIDE R20, R6, R3, c[0x0][0x160] ; /* 0x0000580006147625 */
/* 0x000fe400078e0203 */
/*0780*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000f62000c1e1900 */
/*07a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*07b0*/ IADD3 R4, R8, R7, R4 ; /* 0x0000000708047210 */
/* 0x004fc80007ffe004 */
/*07c0*/ IADD3 R4, R12, R4, R11 ; /* 0x000000040c047210 */
/* 0x008fc80007ffe00b */
/*07d0*/ IADD3 R4, R18, R4, R17 ; /* 0x0000000412047210 */
/* 0x010fc80007ffe011 */
/*07e0*/ IADD3 R4, R4, R21, RZ ; /* 0x0000001504047210 */
/* 0x020fc80007ffe0ff */
/*07f0*/ ISETP.NE.AND P2, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f45270 */
/*0800*/ @!P2 BRA 0x880 ; /* 0x000000700000a947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fda0003f05270 */
/*0820*/ @P0 BRA 0x870 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0203 */
/*0840*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0850*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fe20003f05270 */
/*0860*/ BRA 0x880 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0880*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe20004000000 */
/*0890*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*08a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc600078e0203 */
/*08b0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x000fe80000004800 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*08e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0011e4000c101906 */
/*08f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff037624 */
/* 0x000fc800078e00ff */
/*0900*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x000fca00078e0202 */
/*0910*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*0920*/ @!P0 BRA 0xa0 ; /* 0xfffff77000008947 */
/* 0x000fea000383ffff */
/*0930*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
int blockSize;
int gridSize;
__global__ void gameOfLife(int *indata, int *outdata, int width, int height)
{
__shared__ int sdata[256];
int tSize=width*height;
int x, y, x0,x1,y0,y1, n;
int bid, cid, tid;
tid = threadIdx.x;
bid = blockIdx.x;
for(cid = blockIdx.x*blockDim.x+tid; cid < tSize; cid += gridDim.x*blockDim.x){
if(tid<width){
x=(cid) % width; // x position
y=(cid) / width; // y position
x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too
x1=(x+1) % width; // one right x positional value
y0=(y-1+height) % height; // one row up y positional value
y1=(y+1) % height; // one row below y positional value
n=indata[y1*width+x0]+indata[y*width+x0]+indata[y0+x0]+indata[y0*width+x]+indata[y0*width+x1]+indata[y*width+x1]+indata[y1*width+x1]+indata[y1*width+x]; // no. of alive neighbor cells
if(n==3 || (n==2 && indata[cid])) // life created or sustains
{
sdata[tid]=1;
//outdata[cid]=1;
}
else // life destroyed or stay died
{
sdata[tid]=0;
//outdata[cid]=0;
}
__syncthreads();
outdata[cid]=sdata[tid];
}
}
}
int main(int argc, char **argv)
{
if(argc ^ 4){
printf("Usage: ./gol seed height width iteration\n");
exit(1);
}
clock_t sTime=clock();
int width= atoi(argv[3]);
int height=atoi(argv[2]);
int dsize=width*height;
int iteration=atoi(argv[3]);
int i, j;
int *data;
int *d_indata, *d_outdata, *temp;
// allocate memory for data in host
data=(int *)malloc(dsize*sizeof(int));
// allocate memory for data in device
cudaMalloc(&d_indata, dsize*sizeof(int));
cudaMalloc(&d_outdata, dsize*sizeof(int));
srand(atoi(argv[0])); // test seed
// initialize data in host as randomly 0 or 1
for(i=0;i<dsize;i++)
{
data[i]=rand()%2;
}
// copy initialized data to gpu device
cudaMemcpy( d_indata, data, dsize, cudaMemcpyHostToDevice );
for(i=0;i<iteration;i++)
{
// call kernel
gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height);
// synchronize between thread blocks
cudaDeviceSynchronize();
// swap d_indata and d_outdata for next iteration
temp=d_indata;
d_indata=d_outdata;
d_outdata=temp;
}
// copy data back from device to host memory
cudaMemcpy( data, d_indata, dsize, cudaMemcpyDeviceToHost);
// diplay cell status in console
printf("\n board status # \n");
for(i=0;i<height;i++)
{
for(j=0;j<width;j++)
{
printf(" %d",data[i*width+j]);
}
printf("\n");
}
// free memory allocated
cudaFree(d_indata);
cudaFree(d_outdata);
free(data);
clock_t eTime=clock();
printf("time taken = %ld",eTime-sTime);
cudaDeviceReset();
return 0;
} | .file "tmpxft_0001fb29_00000000-6_gol.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
.type _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, @function
_Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10gameOfLifePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, .-_Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
.globl _Z10gameOfLifePiS_ii
.type _Z10gameOfLifePiS_ii, @function
_Z10gameOfLifePiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10gameOfLifePiS_ii, .-_Z10gameOfLifePiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: ./gol seed height width iteration\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n board status # \n"
.LC2:
.string " %d"
.LC3:
.string "\n"
.LC4:
.string "time taken = %ld"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $4, %edi
jne .L29
movq %rsi, %r12
call clock@PLT
movq %rax, 40(%rsp)
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 16(%rsp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, 12(%rsp)
movl %eax, %ebx
imull %r13d, %ebx
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl %eax, %ebp
movl %ebx, 20(%rsp)
movslq %ebx, %r14
leaq 0(,%r14,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq (%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call srand@PLT
cmpl $0, 20(%rsp)
jle .L13
movq %r15, %r12
addq %r15, %rbx
.L14:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%r12)
addq $4, %r12
cmpq %rbx, %r12
jne .L14
.L13:
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 24(%rsp)
jle .L15
movl $0, %ebx
movl 16(%rsp), %r12d
jmp .L17
.L29:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
call cudaDeviceSynchronize@PLT
movq 48(%rsp), %rax
movq 56(%rsp), %rdx
movq %rdx, 48(%rsp)
movq %rax, 56(%rsp)
addl $1, %ebx
cmpl %ebp, %ebx
je .L15
.L17:
movl blockSize(%rip), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl gridSize(%rip), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movl 12(%rsp), %ecx
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
jmp .L16
.L15:
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L18
movl %r13d, 20(%rsp)
movl $0, %r14d
movl $0, %r12d
leal -1(%r13), %eax
movl %eax, 24(%rsp)
leaq 4(%r15), %rax
movq %rax, 32(%rsp)
leaq .LC2(%rip), %r13
jmp .L19
.L21:
movslq %r14d, %rdx
leaq (%r15,%rdx,4), %rbx
movl 24(%rsp), %eax
addq %rdx, %rax
movq 32(%rsp), %rcx
leaq (%rcx,%rax,4), %rbp
.L20:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
movl 20(%rsp), %eax
addl %eax, %r14d
movl 12(%rsp), %eax
cmpl %eax, %r12d
je .L18
.L19:
cmpl $0, 16(%rsp)
jg .L21
jmp .L22
.L18:
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
call clock@PLT
movq 40(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10gameOfLifePiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gameOfLifePiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl gridSize
.bss
.align 4
.type gridSize, @object
.size gridSize, 4
gridSize:
.zero 4
.globl blockSize
.align 4
.type blockSize, @object
.size blockSize, 4
blockSize:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
int blockSize;
int gridSize;
__global__ void gameOfLife(int *indata, int *outdata, int width, int height)
{
__shared__ int sdata[256];
int tSize=width*height;
int x, y, x0,x1,y0,y1, n;
int bid, cid, tid;
tid = threadIdx.x;
bid = blockIdx.x;
for(cid = blockIdx.x*blockDim.x+tid; cid < tSize; cid += gridDim.x*blockDim.x){
if(tid<width){
x=(cid) % width; // x position
y=(cid) / width; // y position
x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too
x1=(x+1) % width; // one right x positional value
y0=(y-1+height) % height; // one row up y positional value
y1=(y+1) % height; // one row below y positional value
n=indata[y1*width+x0]+indata[y*width+x0]+indata[y0+x0]+indata[y0*width+x]+indata[y0*width+x1]+indata[y*width+x1]+indata[y1*width+x1]+indata[y1*width+x]; // no. of alive neighbor cells
if(n==3 || (n==2 && indata[cid])) // life created or sustains
{
sdata[tid]=1;
//outdata[cid]=1;
}
else // life destroyed or stay died
{
sdata[tid]=0;
//outdata[cid]=0;
}
__syncthreads();
outdata[cid]=sdata[tid];
}
}
}
int main(int argc, char **argv)
{
if(argc ^ 4){
printf("Usage: ./gol seed height width iteration\n");
exit(1);
}
clock_t sTime=clock();
int width= atoi(argv[3]);
int height=atoi(argv[2]);
int dsize=width*height;
int iteration=atoi(argv[3]);
int i, j;
int *data;
int *d_indata, *d_outdata, *temp;
// allocate memory for data in host
data=(int *)malloc(dsize*sizeof(int));
// allocate memory for data in device
cudaMalloc(&d_indata, dsize*sizeof(int));
cudaMalloc(&d_outdata, dsize*sizeof(int));
srand(atoi(argv[0])); // test seed
// initialize data in host as randomly 0 or 1
for(i=0;i<dsize;i++)
{
data[i]=rand()%2;
}
// copy initialized data to gpu device
cudaMemcpy( d_indata, data, dsize, cudaMemcpyHostToDevice );
for(i=0;i<iteration;i++)
{
// call kernel
gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height);
// synchronize between thread blocks
cudaDeviceSynchronize();
// swap d_indata and d_outdata for next iteration
temp=d_indata;
d_indata=d_outdata;
d_outdata=temp;
}
// copy data back from device to host memory
cudaMemcpy( data, d_indata, dsize, cudaMemcpyDeviceToHost);
// diplay cell status in console
printf("\n board status # \n");
for(i=0;i<height;i++)
{
for(j=0;j<width;j++)
{
printf(" %d",data[i*width+j]);
}
printf("\n");
}
// free memory allocated
cudaFree(d_indata);
cudaFree(d_outdata);
free(data);
clock_t eTime=clock();
printf("time taken = %ld",eTime-sTime);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
int blockSize;
int gridSize;
__global__ void gameOfLife(int *indata, int *outdata, int width, int height)
{
__shared__ int sdata[256];
int tSize=width*height;
int x, y, x0,x1,y0,y1, n;
int bid, cid, tid;
tid = threadIdx.x;
bid = blockIdx.x;
for(cid = blockIdx.x*blockDim.x+tid; cid < tSize; cid += gridDim.x*blockDim.x){
if(tid<width){
x=(cid) % width; // x position
y=(cid) / width; // y position
x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too
x1=(x+1) % width; // one right x positional value
y0=(y-1+height) % height; // one row up y positional value
y1=(y+1) % height; // one row below y positional value
n=indata[y1*width+x0]+indata[y*width+x0]+indata[y0+x0]+indata[y0*width+x]+indata[y0*width+x1]+indata[y*width+x1]+indata[y1*width+x1]+indata[y1*width+x]; // no. of alive neighbor cells
if(n==3 || (n==2 && indata[cid])) // life created or sustains
{
sdata[tid]=1;
//outdata[cid]=1;
}
else // life destroyed or stay died
{
sdata[tid]=0;
//outdata[cid]=0;
}
__syncthreads();
outdata[cid]=sdata[tid];
}
}
}
int main(int argc, char **argv)
{
if(argc ^ 4){
printf("Usage: ./gol seed height width iteration\n");
exit(1);
}
clock_t sTime=clock();
int width= atoi(argv[3]);
int height=atoi(argv[2]);
int dsize=width*height;
int iteration=atoi(argv[3]);
int i, j;
int *data;
int *d_indata, *d_outdata, *temp;
// allocate memory for data in host
data=(int *)malloc(dsize*sizeof(int));
// allocate memory for data in device
hipMalloc(&d_indata, dsize*sizeof(int));
hipMalloc(&d_outdata, dsize*sizeof(int));
srand(atoi(argv[0])); // test seed
// initialize data in host as randomly 0 or 1
for(i=0;i<dsize;i++)
{
data[i]=rand()%2;
}
// copy initialized data to gpu device
hipMemcpy( d_indata, data, dsize, hipMemcpyHostToDevice );
for(i=0;i<iteration;i++)
{
// call kernel
gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height);
// synchronize between thread blocks
hipDeviceSynchronize();
// swap d_indata and d_outdata for next iteration
temp=d_indata;
d_indata=d_outdata;
d_outdata=temp;
}
// copy data back from device to host memory
hipMemcpy( data, d_indata, dsize, hipMemcpyDeviceToHost);
// diplay cell status in console
printf("\n board status # \n");
for(i=0;i<height;i++)
{
for(j=0;j<width;j++)
{
printf(" %d",data[i*width+j]);
}
printf("\n");
}
// free memory allocated
hipFree(d_indata);
hipFree(d_outdata);
free(data);
clock_t eTime=clock();
printf("time taken = %ld",eTime-sTime);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
int blockSize;
int gridSize;
__global__ void gameOfLife(int *indata, int *outdata, int width, int height)
{
__shared__ int sdata[256];
int tSize=width*height;
int x, y, x0,x1,y0,y1, n;
int bid, cid, tid;
tid = threadIdx.x;
bid = blockIdx.x;
for(cid = blockIdx.x*blockDim.x+tid; cid < tSize; cid += gridDim.x*blockDim.x){
if(tid<width){
x=(cid) % width; // x position
y=(cid) / width; // y position
x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too
x1=(x+1) % width; // one right x positional value
y0=(y-1+height) % height; // one row up y positional value
y1=(y+1) % height; // one row below y positional value
n=indata[y1*width+x0]+indata[y*width+x0]+indata[y0+x0]+indata[y0*width+x]+indata[y0*width+x1]+indata[y*width+x1]+indata[y1*width+x1]+indata[y1*width+x]; // no. of alive neighbor cells
if(n==3 || (n==2 && indata[cid])) // life created or sustains
{
sdata[tid]=1;
//outdata[cid]=1;
}
else // life destroyed or stay died
{
sdata[tid]=0;
//outdata[cid]=0;
}
__syncthreads();
outdata[cid]=sdata[tid];
}
}
}
int main(int argc, char **argv)
{
if(argc ^ 4){
printf("Usage: ./gol seed height width iteration\n");
exit(1);
}
clock_t sTime=clock();
int width= atoi(argv[3]);
int height=atoi(argv[2]);
int dsize=width*height;
int iteration=atoi(argv[3]);
int i, j;
int *data;
int *d_indata, *d_outdata, *temp;
// allocate memory for data in host
data=(int *)malloc(dsize*sizeof(int));
// allocate memory for data in device
hipMalloc(&d_indata, dsize*sizeof(int));
hipMalloc(&d_outdata, dsize*sizeof(int));
srand(atoi(argv[0])); // test seed
// initialize data in host as randomly 0 or 1
for(i=0;i<dsize;i++)
{
data[i]=rand()%2;
}
// copy initialized data to gpu device
hipMemcpy( d_indata, data, dsize, hipMemcpyHostToDevice );
for(i=0;i<iteration;i++)
{
// call kernel
gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height);
// synchronize between thread blocks
hipDeviceSynchronize();
// swap d_indata and d_outdata for next iteration
temp=d_indata;
d_indata=d_outdata;
d_outdata=temp;
}
// copy data back from device to host memory
hipMemcpy( data, d_indata, dsize, hipMemcpyDeviceToHost);
// diplay cell status in console
printf("\n board status # \n");
for(i=0;i<height;i++)
{
for(j=0;j<width;j++)
{
printf(" %d",data[i*width+j]);
}
printf("\n");
}
// free memory allocated
hipFree(d_indata);
hipFree(d_outdata);
free(data);
clock_t eTime=clock();
printf("time taken = %ld",eTime-sTime);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gameOfLifePiS_ii
.globl _Z10gameOfLifePiS_ii
.p2align 8
.type _Z10gameOfLifePiS_ii,@function
_Z10gameOfLifePiS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s6, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_15
s_ashr_i32 s9, s2, 31
s_ashr_i32 s6, s3, 31
s_add_i32 s7, s2, s9
s_add_i32 s11, s3, s6
s_xor_b32 s10, s7, s9
s_xor_b32 s11, s11, s6
v_cvt_f32_u32_e32 v2, s10
v_cvt_f32_u32_e32 v3, s11
s_load_b32 s13, s[4:5], 0x0
s_sub_i32 s4, 0, s10
s_sub_i32 s5, 0, s11
v_rcp_iflag_f32_e32 v2, v2
v_rcp_iflag_f32_e32 v3, v3
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_dual_mov_b32 v9, 1 :: v_dual_lshlrev_b32 v0, 2, v0
s_add_i32 s3, s3, -1
s_sub_i32 s14, 0, s2
v_mov_b32_e32 v12, 0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v3, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
v_mul_lo_u32 v4, s4, v2
v_mul_lo_u32 v5, s5, v3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, v4
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v2, v4
v_add_nc_u32_e32 v11, v3, v5
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s8, v1
s_or_b32 s13, s0, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_15
.LBB0_4:
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s17, 0
s_mov_b32 s16, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v2
v_xor_b32_e32 v14, s9, v2
v_xor_b32_e32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v10
v_mul_lo_u32 v5, v4, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s10, v3
v_cmp_le_u32_e64 s0, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cndmask_b32_e64 v3, v3, v6, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e64 s0, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v4, v5, s0
v_xor_b32_e32 v13, v2, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v14, v13
v_sub_nc_u32_e32 v5, v13, v14
v_mad_u64_u32 v[2:3], null, s2, v4, s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, s14, v5
v_mul_lo_u32 v15, v5, s2
v_add_nc_u32_e32 v6, s3, v5
v_add_nc_u32_e32 v5, 1, v5
v_add3_u32 v4, v1, v2, -1
v_ashrrev_i32_e32 v18, 31, v6
v_add3_u32 v3, v1, v3, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v16, 31, v5
v_ashrrev_i32_e32 v19, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v4, v6, v18
v_ashrrev_i32_e32 v17, 31, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v5, v5, v16
v_add_nc_u32_e32 v2, v19, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v20, v4, v18
v_sub_nc_u32_e32 v3, v17, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v23, v5, v16
v_add3_u32 v2, v1, v2, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v3, v1, v3, 1
v_mad_u64_u32 v[7:8], null, v23, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v22, v2, v19
v_xor_b32_e32 v21, v3, v17
v_mad_u64_u32 v[2:3], null, v20, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[5:6], null, v22, v10, 0
v_mul_lo_u32 v2, v8, s11
v_mad_u64_u32 v[4:5], null, v21, v10, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v3, v3, s11
v_mul_lo_u32 v4, v6, s10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v2, v23, v2
v_mul_lo_u32 v5, v5, s10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v20, v3
v_subrev_nc_u32_e32 v6, s11, v2
v_cmp_le_u32_e64 s0, s11, v2
v_sub_nc_u32_e32 v4, v22, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v8, s11, v3
v_sub_nc_u32_e32 v5, v21, v5
v_cndmask_b32_e64 v2, v2, v6, s0
v_cmp_le_u32_e64 s0, s11, v3
v_subrev_nc_u32_e32 v7, s10, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v20, s10, v5
v_subrev_nc_u32_e32 v6, s11, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_cmp_le_u32_e64 s0, s10, v4
v_cndmask_b32_e64 v4, v4, v7, s0
v_cmp_le_u32_e64 s0, s10, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s11, v3
v_subrev_nc_u32_e32 v8, s10, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v20, s0
v_cmp_le_u32_e64 s0, s11, v2
v_cndmask_b32_e64 v2, v2, v6, s0
v_cmp_le_u32_e64 s0, s11, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s10, v5
v_xor_b32_e32 v21, v2, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v7, s0
v_cmp_le_u32_e64 s0, s10, v4
v_xor_b32_e32 v2, v3, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v8, s0
v_cmp_le_u32_e64 s0, s10, v5
v_sub_nc_u32_e32 v23, v2, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v19
v_cndmask_b32_e64 v3, v5, v6, s0
v_sub_nc_u32_e32 v5, v21, v16
v_add_nc_u32_e32 v6, v2, v14
v_add_nc_u32_e32 v21, v21, v14
v_sub_nc_u32_e32 v7, v4, v19
v_xor_b32_e32 v3, v3, v17
v_mul_lo_u32 v22, v5, s2
v_sub_nc_u32_e32 v5, v6, v13
v_sub_nc_u32_e32 v13, v21, v13
v_add_nc_u32_e32 v2, v15, v7
v_sub_nc_u32_e32 v4, v3, v17
s_delay_alu instid0(VALU_DEP_4)
v_sub_nc_u32_e32 v6, v5, v18
v_add_nc_u32_e32 v5, v23, v7
v_add_nc_u32_e32 v7, v22, v7
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v14, v4, v15
v_mad_u64_u32 v[17:18], null, s2, v6, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
v_mad_u64_u32 v[19:20], null, v23, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v7, s0, s4, v7
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
v_add_co_u32 v5, s0, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
v_add_co_u32 v17, s0, s4, v17
v_add_co_ci_u32_e64 v18, s0, s5, v18, s0
s_clause 0x3
global_load_b32 v8, v[7:8], off
global_load_b32 v21, v[2:3], off
global_load_b32 v23, v[5:6], off
global_load_b32 v17, v[17:18], off
v_sub_nc_u32_e32 v3, v13, v16
v_add_nc_u32_e32 v2, v22, v4
v_ashrrev_i32_e32 v20, 31, v19
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, s2, v3, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[19:20]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[14:15]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, s0, s4, v4
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
v_add_co_u32 v13, s0, s4, v13
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_clause 0x3
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[13:14], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v6, v21, v8
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v23, v17
s_waitcnt vmcnt(2)
v_add3_u32 v4, v6, v4, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v3
v_cmpx_lt_i32_e32 2, v2
s_xor_b32 s1, exec_lo, s1
v_cmp_eq_u32_e64 s0, 3, v2
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s17, s0, exec_lo
s_and_not1_saveexec_b32 s18, s1
s_cbranch_execz .LBB0_11
s_mov_b32 s20, -1
s_mov_b32 s1, s17
s_mov_b32 s19, exec_lo
v_cmpx_eq_u32_e32 2, v2
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_b32 s21, s17, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 0, v2
v_cmp_eq_u32_e64 s1, 0, v2
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_or_not1_b32 s20, s1, exec_lo
s_or_b32 s1, s21, s0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s0, s16, exec_lo
s_and_b32 s16, s20, exec_lo
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s1, s1, exec_lo
s_or_b32 s16, s0, s16
s_or_b32 s17, s17, s1
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s0, s17
s_cbranch_execz .LBB0_13
s_and_not1_b32 s16, s16, exec_lo
ds_store_b32 v0, v9
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s16
s_cbranch_execz .LBB0_2
ds_store_b32 v0, v12
s_branch .LBB0_2
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gameOfLifePiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gameOfLifePiS_ii, .Lfunc_end0-_Z10gameOfLifePiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gameOfLifePiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z10gameOfLifePiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
int blockSize;
int gridSize;
__global__ void gameOfLife(int *indata, int *outdata, int width, int height)
{
__shared__ int sdata[256];
int tSize=width*height;
int x, y, x0,x1,y0,y1, n;
int bid, cid, tid;
tid = threadIdx.x;
bid = blockIdx.x;
for(cid = blockIdx.x*blockDim.x+tid; cid < tSize; cid += gridDim.x*blockDim.x){
if(tid<width){
x=(cid) % width; // x position
y=(cid) / width; // y position
x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too
x1=(x+1) % width; // one right x positional value
y0=(y-1+height) % height; // one row up y positional value
y1=(y+1) % height; // one row below y positional value
n=indata[y1*width+x0]+indata[y*width+x0]+indata[y0+x0]+indata[y0*width+x]+indata[y0*width+x1]+indata[y*width+x1]+indata[y1*width+x1]+indata[y1*width+x]; // no. of alive neighbor cells
if(n==3 || (n==2 && indata[cid])) // life created or sustains
{
sdata[tid]=1;
//outdata[cid]=1;
}
else // life destroyed or stay died
{
sdata[tid]=0;
//outdata[cid]=0;
}
__syncthreads();
outdata[cid]=sdata[tid];
}
}
}
int main(int argc, char **argv)
{
if(argc ^ 4){
printf("Usage: ./gol seed height width iteration\n");
exit(1);
}
clock_t sTime=clock();
int width= atoi(argv[3]);
int height=atoi(argv[2]);
int dsize=width*height;
int iteration=atoi(argv[3]);
int i, j;
int *data;
int *d_indata, *d_outdata, *temp;
// allocate memory for data in host
data=(int *)malloc(dsize*sizeof(int));
// allocate memory for data in device
hipMalloc(&d_indata, dsize*sizeof(int));
hipMalloc(&d_outdata, dsize*sizeof(int));
srand(atoi(argv[0])); // test seed
// initialize data in host as randomly 0 or 1
for(i=0;i<dsize;i++)
{
data[i]=rand()%2;
}
// copy initialized data to gpu device
hipMemcpy( d_indata, data, dsize, hipMemcpyHostToDevice );
for(i=0;i<iteration;i++)
{
// call kernel
gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height);
// synchronize between thread blocks
hipDeviceSynchronize();
// swap d_indata and d_outdata for next iteration
temp=d_indata;
d_indata=d_outdata;
d_outdata=temp;
}
// copy data back from device to host memory
hipMemcpy( data, d_indata, dsize, hipMemcpyDeviceToHost);
// diplay cell status in console
printf("\n board status # \n");
for(i=0;i<height;i++)
{
for(j=0;j<width;j++)
{
printf(" %d",data[i*width+j]);
}
printf("\n");
}
// free memory allocated
hipFree(d_indata);
hipFree(d_outdata);
free(data);
clock_t eTime=clock();
printf("time taken = %ld",eTime-sTime);
hipDeviceReset();
return 0;
} | .text
.file "gol.hip"
.globl _Z25__device_stub__gameOfLifePiS_ii # -- Begin function _Z25__device_stub__gameOfLifePiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__gameOfLifePiS_ii,@function
_Z25__device_stub__gameOfLifePiS_ii: # @_Z25__device_stub__gameOfLifePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10gameOfLifePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__gameOfLifePiS_ii, .Lfunc_end0-_Z25__device_stub__gameOfLifePiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB1_16
# %bb.1:
movq %rsi, %rbx
callq clock
movq %rax, 40(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %ebp
imull %r14d, %ebp
movq %rbx, (%rsp) # 8-byte Spill
movslq %ebp, %rbx
leaq (,%rbx,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq (%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq srand
movq %rbx, (%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %ebp, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq %r13, %rbx
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq 8(%rsp), %rdi
movq %r15, %rsi
movq (%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB1_9
# %bb.5: # %.lr.ph50
movabsq $4294967296, %r13 # imm = 0x100000000
leaq 112(%rsp), %rbx
movl %r14d, %ebp
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
decl %ebp
je .LBB1_9
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl gridSize(%rip), %edi
movl blockSize(%rip), %edx
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r14d, 28(%rsp)
movl %r12d, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10gameOfLifePiS_ii, %edi
movq %rbx, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_8
.LBB1_9: # %._crit_edge51
movq 8(%rsp), %rsi
movq %r15, 32(%rsp) # 8-byte Spill
movq %r15, %rdi
movq (%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB1_15
# %bb.10: # %.preheader.lr.ph
movl %r12d, %eax
movq %rax, (%rsp) # 8-byte Spill
movl %r14d, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # %._crit_edge54
# in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
movq %rbx, %r14
addl %r14d, %ebp
cmpq (%rsp), %r13 # 8-byte Folded Reload
je .LBB1_15
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movq %r14, %rbx
testl %r14d, %r14d
jle .LBB1_14
# %bb.12: # %.lr.ph53
# in Loop: Header=BB1_11 Depth=1
movl %ebp, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB1_13
jmp .LBB1_14
.LBB1_15: # %._crit_edge56
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi # 8-byte Reload
callq free
callq clock
subq 40(%rsp), %rax # 8-byte Folded Reload
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 208
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gameOfLifePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type blockSize,@object # @blockSize
.bss
.globl blockSize
.p2align 2, 0x0
blockSize:
.long 0 # 0x0
.size blockSize, 4
.type gridSize,@object # @gridSize
.globl gridSize
.p2align 2, 0x0
gridSize:
.long 0 # 0x0
.size gridSize, 4
.type _Z10gameOfLifePiS_ii,@object # @_Z10gameOfLifePiS_ii
.section .rodata,"a",@progbits
.globl _Z10gameOfLifePiS_ii
.p2align 3, 0x0
_Z10gameOfLifePiS_ii:
.quad _Z25__device_stub__gameOfLifePiS_ii
.size _Z10gameOfLifePiS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " %d"
.size .L.str.2, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time taken = %ld"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gameOfLifePiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n board status # "
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: ./gol seed height width iteration"
.size .Lstr.1, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gameOfLifePiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gameOfLifePiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10gameOfLifePiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26270 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*00a0*/ @P1 BRA 0x8f0 ; /* 0x0000084000001947 */
/* 0x001fea0003800000 */
/*00b0*/ IABS R3, c[0x0][0x170] ; /* 0x00005c0000037a13 */
/* 0x000fe20000000000 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0d7435 */
/* 0x000fe400000001ff */
/*00e0*/ I2F.RP R4, R3 ; /* 0x0000000300047306 */
/* 0x000e300000209400 */
/*00f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R11, R4, 0xffffffe, RZ ; /* 0x0ffffffe040b7810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e24000021f000 */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R11 ; /* 0x000000ffff067224 */
/* 0x001fc800078e0a0b */
/*0130*/ IMAD R5, R6, R3, RZ ; /* 0x0000000306057224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R10, R11, R5, R10 ; /* 0x000000050b0a7227 */
/* 0x000fe200078e000a */
/*0160*/ IABS R5, c[0x0][0x174] ; /* 0x00005d0000057a13 */
/* 0x000fc80000000000 */
/*0170*/ I2F.RP R7, R5 ; /* 0x0000000500077306 */
/* 0x000e220000209400 */
/*0180*/ IMAD.HI.U32 R4, R10, R6, RZ ; /* 0x000000060a047227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R8, RZ, RZ, -R4 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a04 */
/*01a0*/ IMAD R6, R3, R8, R6 ; /* 0x0000000803067224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe20003f44070 */
/*01c0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e180000001000 */
/*01d0*/ @!P2 IADD3 R6, R6, -R3.reuse, RZ ; /* 0x800000030606a210 */
/* 0x080fe40007ffe0ff */
/*01e0*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R6, R2, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0002067a12 */
/* 0x000fe400078e3cff */
/*0210*/ IADD3 R8, R7, 0xffffffe, RZ ; /* 0x0ffffffe07087810 */
/* 0x001fe40007ffe0ff */
/*0220*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc40003f66270 */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*0240*/ LOP3.LUT R7, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff077a12 */
/* 0x000fc800078e33ff */
/*0250*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc600078e00ff */
/*0280*/ @!P3 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04b224 */
/* 0x000fca00078e0a04 */
/*0290*/ SEL R4, R7, R4, !P0 ; /* 0x0000000407047207 */
/* 0x000fe20004000000 */
/*02a0*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc600078e0a09 */
/*02b0*/ IADD3 R21, R4, 0x1, RZ ; /* 0x0000000104157810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV R11, RZ, RZ, -R4 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0a04 */
/*02d0*/ IABS R20, R21 ; /* 0x0000001500147213 */
/* 0x000fe20000000000 */
/*02e0*/ IMAD R6, R11, c[0x0][0x170], R2 ; /* 0x00005c000b067a24 */
/* 0x000fe400078e0202 */
/*02f0*/ IMAD R11, R12, R5, RZ ; /* 0x000000050c0b7224 */
/* 0x000fc600078e02ff */
/*0300*/ IADD3 R17, R6.reuse, c[0x0][0x170], -R13 ; /* 0x00005c0006117a10 */
/* 0x040fe20007ffe80d */
/*0310*/ IMAD.HI.U32 R11, R9, R11, R8 ; /* 0x0000000b090b7227 */
/* 0x000fe200078e0008 */
/*0320*/ IADD3 R19, R6, 0x1, RZ ; /* 0x0000000106137810 */
/* 0x000fe40007ffe0ff */
/*0330*/ IADD3 R8, R4, c[0x0][0x174], -R13 ; /* 0x00005d0004087a10 */
/* 0x000fe40007ffe80d */
/*0340*/ IABS R13, R17 ; /* 0x00000011000d7213 */
/* 0x000fe40000000000 */
/*0350*/ IABS R15, R19 ; /* 0x00000013000f7213 */
/* 0x000fe40000000000 */
/*0360*/ IABS R18, R8 ; /* 0x0000000800127213 */
/* 0x000fe20000000000 */
/*0370*/ IMAD.HI.U32 R9, R10, R13, RZ ; /* 0x0000000d0a097227 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.HI.U32 R10, R10, R15, RZ ; /* 0x0000000f0a0a7227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.HI.U32 R12, R11, R18, RZ ; /* 0x000000120b0c7227 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.MOV R14, RZ, RZ, -R9 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a09 */
/*03b0*/ IADD3 R9, -R12, RZ, RZ ; /* 0x000000ff0c097210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD.MOV R16, RZ, RZ, -R10 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a0a */
/*03d0*/ IMAD R10, R3.reuse, R14, R13 ; /* 0x0000000e030a7224 */
/* 0x040fe400078e020d */
/*03e0*/ IMAD R12, R3, R16, R15 ; /* 0x00000010030c7224 */
/* 0x000fe400078e020f */
/*03f0*/ IMAD.HI.U32 R11, R11, R20, RZ ; /* 0x000000140b0b7227 */
/* 0x000fe200078e00ff */
/*0400*/ ISETP.GT.U32.AND P3, PT, R3.reuse, R10, PT ; /* 0x0000000a0300720c */
/* 0x040fe40003f64070 */
/*0410*/ ISETP.GT.U32.AND P4, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe20003f84070 */
/*0420*/ IMAD R14, R5, R9, R18 ; /* 0x00000009050e7224 */
/* 0x000fc400078e0212 */
/*0430*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0a0b */
/*0440*/ ISETP.GT.U32.AND P5, PT, R5.reuse, R14, PT ; /* 0x0000000e0500720c */
/* 0x040fe20003fa4070 */
/*0450*/ IMAD R16, R5, R11, R20 ; /* 0x0000000b05107224 */
/* 0x000fc800078e0214 */
/*0460*/ @!P3 IMAD.IADD R10, R10, 0x1, -R3.reuse ; /* 0x000000010a0ab824 */
/* 0x100fe200078e0a03 */
/*0470*/ ISETP.GT.U32.AND P2, PT, R5, R16, PT ; /* 0x000000100500720c */
/* 0x000fe20003f44070 */
/*0480*/ @!P4 IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0cc824 */
/* 0x000fc600078e0a03 */
/*0490*/ ISETP.GT.U32.AND P4, PT, R3.reuse, R10, PT ; /* 0x0000000a0300720c */
/* 0x040fe40003f84070 */
/*04a0*/ ISETP.GT.U32.AND P6, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe40003fc4070 */
/*04b0*/ @!P5 IADD3 R14, R14, -R5, RZ ; /* 0x800000050e0ed210 */
/* 0x000fc80007ffe0ff */
/*04c0*/ ISETP.GT.U32.AND P5, PT, R5, R14, PT ; /* 0x0000000e0500720c */
/* 0x000fe20003fa4070 */
/*04d0*/ @!P2 IMAD.IADD R16, R16, 0x1, -R5 ; /* 0x000000011010a824 */
/* 0x000fe200078e0a05 */
/*04e0*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f46270 */
/*04f0*/ @!P4 IMAD.IADD R10, R10, 0x1, -R3.reuse ; /* 0x000000010a0ac824 */
/* 0x100fe200078e0a03 */
/*0500*/ ISETP.GT.U32.AND P3, PT, R5, R16, PT ; /* 0x000000100500720c */
/* 0x000fe20003f64070 */
/*0510*/ @!P6 IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0ce824 */
/* 0x000fe200078e0a03 */
/*0520*/ ISETP.GE.AND P4, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f86270 */
/*0530*/ ISETP.GE.AND P6, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003fc6270 */
/*0540*/ LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff037a12 */
/* 0x000fe400078e33ff */
/*0550*/ @!P5 IADD3 R14, R14, -R5, RZ ; /* 0x800000050e0ed210 */
/* 0x000fe40007ffe0ff */
/*0560*/ ISETP.GE.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc60003fa6270 */
/*0570*/ @!P3 IMAD.IADD R16, R16, 0x1, -R5 ; /* 0x000000011010b824 */
/* 0x000fe200078e0a05 */
/*0580*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f65270 */
/*0590*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe400078e0a0e */
/*05a0*/ @!P4 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff10c224 */
/* 0x000fe200078e0a10 */
/*05b0*/ @!P6 IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0ae210 */
/* 0x000fe40007ffe1ff */
/*05c0*/ SEL R5, R3.reuse, R14, !P3 ; /* 0x0000000e03057207 */
/* 0x040fe40005800000 */
/*05d0*/ SEL R9, R3, R16, !P3 ; /* 0x0000001003097207 */
/* 0x000fe20005800000 */
/*05e0*/ @!P5 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cd224 */
/* 0x000fe200078e0a0c */
/*05f0*/ SEL R10, R7, R10, !P0 ; /* 0x0000000a070a7207 */
/* 0x000fe20004000000 */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0610*/ SEL R7, R7, R12, !P0 ; /* 0x0000000c07077207 */
/* 0x000fe20004000000 */
/*0620*/ IMAD R14, R4, c[0x0][0x170], R10.reuse ; /* 0x00005c00040e7a24 */
/* 0x100fe400078e020a */
/*0630*/ IMAD R8, R9, c[0x0][0x170], R10 ; /* 0x00005c0009087a24 */
/* 0x000fe400078e020a */
/*0640*/ IMAD.IADD R10, R10, 0x1, R5 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0205 */
/*0650*/ IMAD R12, R5.reuse, c[0x0][0x170], R6 ; /* 0x00005c00050c7a24 */
/* 0x040fe400078e0206 */
/*0660*/ IMAD R18, R4, c[0x0][0x170], R7.reuse ; /* 0x00005c0004127a24 */
/* 0x100fe400078e0207 */
/*0670*/ IMAD R16, R5, c[0x0][0x170], R7 ; /* 0x00005c0005107a24 */
/* 0x000fc400078e0207 */
/*0680*/ IMAD R6, R9, c[0x0][0x170], R6 ; /* 0x00005c0009067a24 */
/* 0x000fe400078e0206 */
/*0690*/ IMAD.WIDE R4, R8, R3, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0203 */
/*06a0*/ IMAD R20, R9, c[0x0][0x170], R7 ; /* 0x00005c0009147a24 */
/* 0x000fe400078e0207 */
/*06b0*/ IMAD.WIDE R8, R10, R3.reuse, c[0x0][0x160] ; /* 0x000058000a087625 */
/* 0x080fe200078e0203 */
/*06c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea6000c1e1900 */
/*06d0*/ IMAD.WIDE R14, R14, R3.reuse, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x080fe400078e0203 */
/*06e0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ IMAD.WIDE R10, R12, R3, c[0x0][0x160] ; /* 0x000058000c0a7625 */
/* 0x000fc400078e0203 */
/*0700*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x000ea4000c1e1900 */
/*0710*/ IMAD.WIDE R12, R16, R3.reuse, c[0x0][0x160] ; /* 0x00005800100c7625 */
/* 0x080fe400078e0203 */
/*0720*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ee4000c1e1900 */
/*0730*/ IMAD.WIDE R16, R18, R3.reuse, c[0x0][0x160] ; /* 0x0000580012107625 */
/* 0x080fe400078e0203 */
/*0740*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ee4000c1e1900 */
/*0750*/ IMAD.WIDE R18, R20, R3, c[0x0][0x160] ; /* 0x0000580014127625 */
/* 0x000fc400078e0203 */
/*0760*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000f24000c1e1900 */
/*0770*/ IMAD.WIDE R20, R6, R3, c[0x0][0x160] ; /* 0x0000580006147625 */
/* 0x000fe400078e0203 */
/*0780*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000f62000c1e1900 */
/*07a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*07b0*/ IADD3 R4, R8, R7, R4 ; /* 0x0000000708047210 */
/* 0x004fc80007ffe004 */
/*07c0*/ IADD3 R4, R12, R4, R11 ; /* 0x000000040c047210 */
/* 0x008fc80007ffe00b */
/*07d0*/ IADD3 R4, R18, R4, R17 ; /* 0x0000000412047210 */
/* 0x010fc80007ffe011 */
/*07e0*/ IADD3 R4, R4, R21, RZ ; /* 0x0000001504047210 */
/* 0x020fc80007ffe0ff */
/*07f0*/ ISETP.NE.AND P2, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f45270 */
/*0800*/ @!P2 BRA 0x880 ; /* 0x000000700000a947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fda0003f05270 */
/*0820*/ @P0 BRA 0x870 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0203 */
/*0840*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0850*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fe20003f05270 */
/*0860*/ BRA 0x880 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0880*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe20004000000 */
/*0890*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*08a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc600078e0203 */
/*08b0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x000fe80000004800 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*08e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0011e4000c101906 */
/*08f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff037624 */
/* 0x000fc800078e00ff */
/*0900*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x000fca00078e0202 */
/*0910*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*0920*/ @!P0 BRA 0xa0 ; /* 0xfffff77000008947 */
/* 0x000fea000383ffff */
/*0930*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gameOfLifePiS_ii
.globl _Z10gameOfLifePiS_ii
.p2align 8
.type _Z10gameOfLifePiS_ii,@function
_Z10gameOfLifePiS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s6, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_15
s_ashr_i32 s9, s2, 31
s_ashr_i32 s6, s3, 31
s_add_i32 s7, s2, s9
s_add_i32 s11, s3, s6
s_xor_b32 s10, s7, s9
s_xor_b32 s11, s11, s6
v_cvt_f32_u32_e32 v2, s10
v_cvt_f32_u32_e32 v3, s11
s_load_b32 s13, s[4:5], 0x0
s_sub_i32 s4, 0, s10
s_sub_i32 s5, 0, s11
v_rcp_iflag_f32_e32 v2, v2
v_rcp_iflag_f32_e32 v3, v3
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_dual_mov_b32 v9, 1 :: v_dual_lshlrev_b32 v0, 2, v0
s_add_i32 s3, s3, -1
s_sub_i32 s14, 0, s2
v_mov_b32_e32 v12, 0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v3, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
v_mul_lo_u32 v4, s4, v2
v_mul_lo_u32 v5, s5, v3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, v4
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v2, v4
v_add_nc_u32_e32 v11, v3, v5
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s8, v1
s_or_b32 s13, s0, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_15
.LBB0_4:
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s17, 0
s_mov_b32 s16, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v2
v_xor_b32_e32 v14, s9, v2
v_xor_b32_e32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v10
v_mul_lo_u32 v5, v4, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s10, v3
v_cmp_le_u32_e64 s0, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cndmask_b32_e64 v3, v3, v6, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e64 s0, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v4, v5, s0
v_xor_b32_e32 v13, v2, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v14, v13
v_sub_nc_u32_e32 v5, v13, v14
v_mad_u64_u32 v[2:3], null, s2, v4, s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, s14, v5
v_mul_lo_u32 v15, v5, s2
v_add_nc_u32_e32 v6, s3, v5
v_add_nc_u32_e32 v5, 1, v5
v_add3_u32 v4, v1, v2, -1
v_ashrrev_i32_e32 v18, 31, v6
v_add3_u32 v3, v1, v3, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v16, 31, v5
v_ashrrev_i32_e32 v19, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v4, v6, v18
v_ashrrev_i32_e32 v17, 31, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v5, v5, v16
v_add_nc_u32_e32 v2, v19, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v20, v4, v18
v_sub_nc_u32_e32 v3, v17, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v23, v5, v16
v_add3_u32 v2, v1, v2, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v3, v1, v3, 1
v_mad_u64_u32 v[7:8], null, v23, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v22, v2, v19
v_xor_b32_e32 v21, v3, v17
v_mad_u64_u32 v[2:3], null, v20, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[5:6], null, v22, v10, 0
v_mul_lo_u32 v2, v8, s11
v_mad_u64_u32 v[4:5], null, v21, v10, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v3, v3, s11
v_mul_lo_u32 v4, v6, s10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v2, v23, v2
v_mul_lo_u32 v5, v5, s10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v20, v3
v_subrev_nc_u32_e32 v6, s11, v2
v_cmp_le_u32_e64 s0, s11, v2
v_sub_nc_u32_e32 v4, v22, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v8, s11, v3
v_sub_nc_u32_e32 v5, v21, v5
v_cndmask_b32_e64 v2, v2, v6, s0
v_cmp_le_u32_e64 s0, s11, v3
v_subrev_nc_u32_e32 v7, s10, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v20, s10, v5
v_subrev_nc_u32_e32 v6, s11, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_cmp_le_u32_e64 s0, s10, v4
v_cndmask_b32_e64 v4, v4, v7, s0
v_cmp_le_u32_e64 s0, s10, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s11, v3
v_subrev_nc_u32_e32 v8, s10, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v20, s0
v_cmp_le_u32_e64 s0, s11, v2
v_cndmask_b32_e64 v2, v2, v6, s0
v_cmp_le_u32_e64 s0, s11, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s10, v5
v_xor_b32_e32 v21, v2, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v7, s0
v_cmp_le_u32_e64 s0, s10, v4
v_xor_b32_e32 v2, v3, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v8, s0
v_cmp_le_u32_e64 s0, s10, v5
v_sub_nc_u32_e32 v23, v2, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v19
v_cndmask_b32_e64 v3, v5, v6, s0
v_sub_nc_u32_e32 v5, v21, v16
v_add_nc_u32_e32 v6, v2, v14
v_add_nc_u32_e32 v21, v21, v14
v_sub_nc_u32_e32 v7, v4, v19
v_xor_b32_e32 v3, v3, v17
v_mul_lo_u32 v22, v5, s2
v_sub_nc_u32_e32 v5, v6, v13
v_sub_nc_u32_e32 v13, v21, v13
v_add_nc_u32_e32 v2, v15, v7
v_sub_nc_u32_e32 v4, v3, v17
s_delay_alu instid0(VALU_DEP_4)
v_sub_nc_u32_e32 v6, v5, v18
v_add_nc_u32_e32 v5, v23, v7
v_add_nc_u32_e32 v7, v22, v7
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v14, v4, v15
v_mad_u64_u32 v[17:18], null, s2, v6, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
v_mad_u64_u32 v[19:20], null, v23, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v7, s0, s4, v7
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
v_add_co_u32 v5, s0, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
v_add_co_u32 v17, s0, s4, v17
v_add_co_ci_u32_e64 v18, s0, s5, v18, s0
s_clause 0x3
global_load_b32 v8, v[7:8], off
global_load_b32 v21, v[2:3], off
global_load_b32 v23, v[5:6], off
global_load_b32 v17, v[17:18], off
v_sub_nc_u32_e32 v3, v13, v16
v_add_nc_u32_e32 v2, v22, v4
v_ashrrev_i32_e32 v20, 31, v19
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, s2, v3, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[19:20]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[14:15]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, s0, s4, v4
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
v_add_co_u32 v13, s0, s4, v13
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_clause 0x3
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[13:14], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v6, v21, v8
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v23, v17
s_waitcnt vmcnt(2)
v_add3_u32 v4, v6, v4, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v3
v_cmpx_lt_i32_e32 2, v2
s_xor_b32 s1, exec_lo, s1
v_cmp_eq_u32_e64 s0, 3, v2
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s17, s0, exec_lo
s_and_not1_saveexec_b32 s18, s1
s_cbranch_execz .LBB0_11
s_mov_b32 s20, -1
s_mov_b32 s1, s17
s_mov_b32 s19, exec_lo
v_cmpx_eq_u32_e32 2, v2
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_b32 s21, s17, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 0, v2
v_cmp_eq_u32_e64 s1, 0, v2
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_or_not1_b32 s20, s1, exec_lo
s_or_b32 s1, s21, s0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s0, s16, exec_lo
s_and_b32 s16, s20, exec_lo
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s1, s1, exec_lo
s_or_b32 s16, s0, s16
s_or_b32 s17, s17, s1
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s0, s17
s_cbranch_execz .LBB0_13
s_and_not1_b32 s16, s16, exec_lo
ds_store_b32 v0, v9
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s16
s_cbranch_execz .LBB0_2
ds_store_b32 v0, v12
s_branch .LBB0_2
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gameOfLifePiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gameOfLifePiS_ii, .Lfunc_end0-_Z10gameOfLifePiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gameOfLifePiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z10gameOfLifePiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001fb29_00000000-6_gol.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
.type _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, @function
_Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10gameOfLifePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, .-_Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
.globl _Z10gameOfLifePiS_ii
.type _Z10gameOfLifePiS_ii, @function
_Z10gameOfLifePiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10gameOfLifePiS_ii, .-_Z10gameOfLifePiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: ./gol seed height width iteration\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n board status # \n"
.LC2:
.string " %d"
.LC3:
.string "\n"
.LC4:
.string "time taken = %ld"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $4, %edi
jne .L29
movq %rsi, %r12
call clock@PLT
movq %rax, 40(%rsp)
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 16(%rsp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, 12(%rsp)
movl %eax, %ebx
imull %r13d, %ebx
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl %eax, %ebp
movl %ebx, 20(%rsp)
movslq %ebx, %r14
leaq 0(,%r14,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq (%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call srand@PLT
cmpl $0, 20(%rsp)
jle .L13
movq %r15, %r12
addq %r15, %rbx
.L14:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%r12)
addq $4, %r12
cmpq %rbx, %r12
jne .L14
.L13:
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 24(%rsp)
jle .L15
movl $0, %ebx
movl 16(%rsp), %r12d
jmp .L17
.L29:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
call cudaDeviceSynchronize@PLT
movq 48(%rsp), %rax
movq 56(%rsp), %rdx
movq %rdx, 48(%rsp)
movq %rax, 56(%rsp)
addl $1, %ebx
cmpl %ebp, %ebx
je .L15
.L17:
movl blockSize(%rip), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl gridSize(%rip), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movl 12(%rsp), %ecx
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii
jmp .L16
.L15:
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L18
movl %r13d, 20(%rsp)
movl $0, %r14d
movl $0, %r12d
leal -1(%r13), %eax
movl %eax, 24(%rsp)
leaq 4(%r15), %rax
movq %rax, 32(%rsp)
leaq .LC2(%rip), %r13
jmp .L19
.L21:
movslq %r14d, %rdx
leaq (%r15,%rdx,4), %rbx
movl 24(%rsp), %eax
addq %rdx, %rax
movq 32(%rsp), %rcx
leaq (%rcx,%rax,4), %rbp
.L20:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
movl 20(%rsp), %eax
addl %eax, %r14d
movl 12(%rsp), %eax
cmpl %eax, %r12d
je .L18
.L19:
cmpl $0, 16(%rsp)
jg .L21
jmp .L22
.L18:
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
call clock@PLT
movq 40(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10gameOfLifePiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gameOfLifePiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl gridSize
.bss
.align 4
.type gridSize, @object
.size gridSize, 4
gridSize:
.zero 4
.globl blockSize
.align 4
.type blockSize, @object
.size blockSize, 4
blockSize:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gol.hip"
.globl _Z25__device_stub__gameOfLifePiS_ii # -- Begin function _Z25__device_stub__gameOfLifePiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__gameOfLifePiS_ii,@function
_Z25__device_stub__gameOfLifePiS_ii: # @_Z25__device_stub__gameOfLifePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10gameOfLifePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__gameOfLifePiS_ii, .Lfunc_end0-_Z25__device_stub__gameOfLifePiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB1_16
# %bb.1:
movq %rsi, %rbx
callq clock
movq %rax, 40(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %ebp
imull %r14d, %ebp
movq %rbx, (%rsp) # 8-byte Spill
movslq %ebp, %rbx
leaq (,%rbx,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq (%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq srand
movq %rbx, (%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %ebp, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq %r13, %rbx
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq 8(%rsp), %rdi
movq %r15, %rsi
movq (%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB1_9
# %bb.5: # %.lr.ph50
movabsq $4294967296, %r13 # imm = 0x100000000
leaq 112(%rsp), %rbx
movl %r14d, %ebp
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
decl %ebp
je .LBB1_9
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl gridSize(%rip), %edi
movl blockSize(%rip), %edx
orq %r13, %rdi
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r14d, 28(%rsp)
movl %r12d, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10gameOfLifePiS_ii, %edi
movq %rbx, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_8
.LBB1_9: # %._crit_edge51
movq 8(%rsp), %rsi
movq %r15, 32(%rsp) # 8-byte Spill
movq %r15, %rdi
movq (%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB1_15
# %bb.10: # %.preheader.lr.ph
movl %r12d, %eax
movq %rax, (%rsp) # 8-byte Spill
movl %r14d, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # %._crit_edge54
# in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
movq %rbx, %r14
addl %r14d, %ebp
cmpq (%rsp), %r13 # 8-byte Folded Reload
je .LBB1_15
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movq %r14, %rbx
testl %r14d, %r14d
jle .LBB1_14
# %bb.12: # %.lr.ph53
# in Loop: Header=BB1_11 Depth=1
movl %ebp, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB1_13
jmp .LBB1_14
.LBB1_15: # %._crit_edge56
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi # 8-byte Reload
callq free
callq clock
subq 40(%rsp), %rax # 8-byte Folded Reload
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 208
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gameOfLifePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type blockSize,@object # @blockSize
.bss
.globl blockSize
.p2align 2, 0x0
blockSize:
.long 0 # 0x0
.size blockSize, 4
.type gridSize,@object # @gridSize
.globl gridSize
.p2align 2, 0x0
gridSize:
.long 0 # 0x0
.size gridSize, 4
.type _Z10gameOfLifePiS_ii,@object # @_Z10gameOfLifePiS_ii
.section .rodata,"a",@progbits
.globl _Z10gameOfLifePiS_ii
.p2align 3, 0x0
_Z10gameOfLifePiS_ii:
.quad _Z25__device_stub__gameOfLifePiS_ii
.size _Z10gameOfLifePiS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " %d"
.size .L.str.2, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time taken = %ld"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gameOfLifePiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n board status # "
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: ./gol seed height width iteration"
.size .Lstr.1, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gameOfLifePiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gameOfLifePiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void min(int* U, int* d, int* outDel, int* minOutEdges, size_t gSize, int useD) {
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
int pos1 = 2*globalThreadId;
int pos2 = 2*globalThreadId + 1;
int val1, val2;
if(pos1 < gSize) {
val1 = minOutEdges[pos1] + (useD ? d[pos1] : 0);
if(pos2 < gSize) {
val2 = minOutEdges[pos2] + (useD ? d[pos2] : 0);
val1 = val1 <= 0 ? INT_MAX : val1;
val2 = val2 <= 0 ? INT_MAX : val2;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
val2 = U[pos2] ? val2 : INT_MAX;
}
if(val1 > val2) {
outDel[globalThreadId] = val2;
}
else{
outDel[globalThreadId] = val1;
}
}
else {
val1 = val1 <= 0 ? INT_MAX : val1;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
}
outDel[globalThreadId] = val1;
}
}
} | code for sm_80
Function : _Z3minPiS_S_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD.SHL.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007824 */
/* 0x000fca00078e00ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x184], PT, P0 ; /* 0x0000610003007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe20003f25270 */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R5, R0, 0x2, R3 ; /* 0x0000000200057819 */
/* 0x000fe20000010203 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ IADD3 R6, P0, R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R7, R5, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0005077a10 */
/* 0x000fc600007fe4ff */
/*0100*/ @P1 IADD3 R8, P2, R4, c[0x0][0x168], RZ ; /* 0x00005a0004081a10 */
/* 0x000fe40007f5e0ff */
/*0110*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea4000c1e1900 */
/*0120*/ @P1 IADD3.X R9, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005091a10 */
/* 0x000fca00017fe4ff */
/*0130*/ @P1 LDG.E R10, [R8.64] ; /* 0x00000004080a1981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0160*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fc80000011400 */
/*0170*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x184], PT, P0 ; /* 0x000061000b007a0c */
/* 0x000fe20003f06100 */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R4, P2, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc80007f5e0ff */
/*01a0*/ IADD3.X R5, R5, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590005057a10 */
/* 0x000fe200017fe4ff */
/*01b0*/ IMAD.IADD R12, R3, 0x1, R10 ; /* 0x00000001030c7824 */
/* 0x004fe400078e020a */
/*01c0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e020d */
/*01d0*/ @!P0 BRA 0x260 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f06270 */
/*01f0*/ SEL R7, R12, 0x7fffffff, P0 ; /* 0x7fffffff0c077807 */
/* 0x000fe20000000000 */
/*0200*/ @!P1 BRA 0x240 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0220*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fc80003f05270 */
/*0230*/ SEL R7, R7, 0x7fffffff, P0 ; /* 0x7fffffff07077807 */
/* 0x000fca0000000000 */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ @P1 LEA R8, P0, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0000081a11 */
/* 0x040fe200078010ff */
/*0270*/ LDG.E R6, [R6.64+0x4] ; /* 0x0000040406067981 */
/* 0x000ea6000c1e1900 */
/*0280*/ @P1 LEA.HI.X R9, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000091a11 */
/* 0x000fe200000f140b */
/*0290*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*02a0*/ @P1 LDG.E R0, [R4.64] ; /* 0x0000000404001981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ @P1 LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a1981 */
/* 0x000f28000c1e1900 */
/*02c0*/ @P1 LDG.E R11, [R8.64] ; /* 0x00000004080b1981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ ISETP.GE.AND P4, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f86270 */
/*02e0*/ SEL R13, R12, 0x7fffffff, P4 ; /* 0x7fffffff0c0d7807 */
/* 0x000fe20002000000 */
/*02f0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x004fe200078e020b */
/*0300*/ @P1 ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000120c */
/* 0x008fc80003f45270 */
/*0310*/ ISETP.GE.AND P0, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00780c */
/* 0x040fe40003f06270 */
/*0320*/ @P1 ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00120c */
/* 0x010fe40003f65270 */
/*0330*/ SEL R11, R11, 0x7fffffff, P0 ; /* 0x7fffffff0b0b7807 */
/* 0x000fe40000000000 */
/*0340*/ @P1 SEL R13, R13, 0x7fffffff, P2 ; /* 0x7fffffff0d0d1807 */
/* 0x000fe40001000000 */
/*0350*/ @P1 SEL R11, R11, 0x7fffffff, P3 ; /* 0x7fffffff0b0b1807 */
/* 0x000fc80001800000 */
/*0360*/ ISETP.GT.AND P0, PT, R13, R11, PT ; /* 0x0000000b0d00720c */
/* 0x000fda0003f04270 */
/*0370*/ @!P0 STG.E [R2.64], R13 ; /* 0x0000000d02008986 */
/* 0x0001e2000c101904 */
/*0380*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void min(int* U, int* d, int* outDel, int* minOutEdges, size_t gSize, int useD) {
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
int pos1 = 2*globalThreadId;
int pos2 = 2*globalThreadId + 1;
int val1, val2;
if(pos1 < gSize) {
val1 = minOutEdges[pos1] + (useD ? d[pos1] : 0);
if(pos2 < gSize) {
val2 = minOutEdges[pos2] + (useD ? d[pos2] : 0);
val1 = val1 <= 0 ? INT_MAX : val1;
val2 = val2 <= 0 ? INT_MAX : val2;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
val2 = U[pos2] ? val2 : INT_MAX;
}
if(val1 > val2) {
outDel[globalThreadId] = val2;
}
else{
outDel[globalThreadId] = val1;
}
}
else {
val1 = val1 <= 0 ? INT_MAX : val1;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
}
outDel[globalThreadId] = val1;
}
}
} | .file "tmpxft_0007c799_00000000-6_min.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi
.type _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi, @function
_Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3minPiS_S_S_mi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi, .-_Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi
.globl _Z3minPiS_S_S_mi
.type _Z3minPiS_S_S_mi, @function
_Z3minPiS_S_S_mi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3minPiS_S_S_mi, .-_Z3minPiS_S_S_mi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3minPiS_S_S_mi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPiS_S_S_mi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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