Datasets:
Sarim-Hash
/
cuda_amd

Dataset card Data Studio Files
xet
Community
1
system
stringclasses
7 values
input
stringlengths
10
94.5k
output
stringlengths
14
55.5k
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000fd71c_00000000-6_kernel_calculate_vertex_V.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf .type _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf, @function _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z25kernel_calculate_vertex_VP6float3Pf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf, .-_Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf .globl _Z25kernel_calculate_vertex_VP6float3Pf .type _Z25kernel_calculate_vertex_VP6float3Pf, @function _Z25kernel_calculate_vertex_VP6float3Pf: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z25kernel_calculate_vertex_VP6float3Pf, .-_Z25kernel_calculate_vertex_VP6float3Pf .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z25kernel_calculate_vertex_VP6float3Pf" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "d_L" .LC2: .string "d_dx" .LC3: .string "d_dt" .LC4: .string "d_mass" .LC5: .string "d_g" .LC6: .string "d_t" .LC7: .string "d_scaling" .LC8: .string "d_current_scene" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z25kernel_calculate_vertex_VP6float3Pf(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL3d_L(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL4d_dx(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZL4d_dt(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL6d_mass(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZL3d_g(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZL3d_t(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL9d_scaling(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _ZL15d_current_scene(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL15d_current_scene .comm _ZL15d_current_scene,4,4 .local _ZL9d_scaling .comm _ZL9d_scaling,4,4 .local _ZL3d_t .comm _ZL3d_t,4,4 .local _ZL3d_g .comm _ZL3d_g,4,4 .local _ZL6d_mass .comm _ZL6d_mass,4,4 .local _ZL4d_dt .comm _ZL4d_dt,4,4 .local _ZL4d_dx .comm _ZL4d_dx,4,4 .local _ZL3d_L .comm _ZL3d_L,4,4 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "kernel_calculate_vertex_V.hip" .globl _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf # -- Begin function _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .p2align 4, 0x90 .type _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf,@function _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf: # @_Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, .Lfunc_end0-_Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rbx subq $32, %rsp .cfi_adjust_cfa_offset 32 xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction addq $32, %rsp .cfi_adjust_cfa_offset -32 movl $d_L, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_dx, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_dt, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_mass, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_g, %esi movl $.L__unnamed_6, %edx movl $.L__unnamed_6, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_t, %esi movl $.L__unnamed_7, %edx movl $.L__unnamed_7, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_scaling, %esi movl $.L__unnamed_8, %edx movl $.L__unnamed_8, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $d_current_scene, %esi movl $.L__unnamed_9, %edx movl $.L__unnamed_9, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $__hip_module_dtor, %edi popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type d_L,@object # @d_L .local d_L .comm d_L,4,4 .type d_dx,@object # @d_dx .local d_dx .comm d_dx,4,4 .type d_dt,@object # @d_dt .local d_dt .comm d_dt,4,4 .type d_mass,@object # @d_mass .local d_mass .comm d_mass,4,4 .type d_g,@object # @d_g .local d_g .comm d_g,4,4 .type d_t,@object # @d_t .local d_t .comm d_t,4,4 .type d_scaling,@object # @d_scaling .local d_scaling .comm d_scaling,4,4 .type d_current_scene,@object # @d_current_scene .local d_current_scene .comm d_current_scene,4,4 .type _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf,@object # @_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .section .rodata,"a",@progbits .globl _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .p2align 3, 0x0 _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf: .quad _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .size _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf" .size .L__unnamed_1, 57 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "d_L" .size .L__unnamed_2, 4 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "d_dx" .size .L__unnamed_3, 5 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "d_dt" .size .L__unnamed_4, 5 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "d_mass" .size .L__unnamed_5, 7 .type .L__unnamed_6,@object # @5 .L__unnamed_6: .asciz "d_g" .size .L__unnamed_6, 4 .type .L__unnamed_7,@object # @6 .L__unnamed_7: .asciz "d_t" .size .L__unnamed_7, 4 .type .L__unnamed_8,@object # @7 .L__unnamed_8: .asciz "d_scaling" .size .L__unnamed_8, 10 .type .L__unnamed_9,@object # @8 .L__unnamed_9: .asciz "d_current_scene" .size .L__unnamed_9, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym d_L .addrsig_sym d_dx .addrsig_sym d_dt .addrsig_sym d_mass .addrsig_sym d_g .addrsig_sym d_t .addrsig_sym d_scaling .addrsig_sym d_current_scene .addrsig_sym _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <iostream> #include <ctime> //#define MAX_NUMBER 32768 // 32 * 1024 //#define MAX_NUMBER 65536 // 64 * 1024 //#define MAX_NUMBER 131072 // 128 * 1024 #define MAX_NUMBER (1024 * 1024 * 16) // 128 * 1024 typedef int cuda_int; typedef int cpu_int; const int device = 0; // 在Matebook 14上只有一个MX250 int deviceNum; int maxBlockNumX; int maxBlockNumY; int maxBlockNumZ; int maxThdPerBlock; cudaDeviceProp deviceProp; cuda_int *dev_a = NULL; cuda_int *dev_b = NULL; cuda_int *dev_c = NULL; cpu_int a[MAX_NUMBER]; cpu_int b[MAX_NUMBER]; cpu_int c[MAX_NUMBER]; cudaError_t cudaEnvInit() { cudaError_t cudaStatus; int value; /* 在硬件平台上选择一个支持cuda的设备 */ cudaStatus = cudaGetDeviceCount(&deviceNum); cudaStatus = cudaGetDeviceProperties(&deviceProp, 0); cudaStatus = cudaSetDevice(device); if (cudaStatus != cudaSuccess) { std::cout << "cudaSetDevice failed!" << std::endl; return cudaStatus; } cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimX, device);\ maxBlockNumX = value; cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimY, device); maxBlockNumY = value; cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimZ, device); maxBlockNumZ = value; cudaStatus = cudaMalloc((void **)&dev_a, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_a failed!" << std::endl; return cudaStatus; } cudaStatus = cudaMalloc((void **)&dev_b, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_b failed!" << std::endl; cudaFree(dev_a); return cudaStatus; } cudaStatus = cudaMalloc((void **)&dev_c, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_c failed!" << std::endl; cudaFree(dev_a); cudaFree(dev_b); return cudaStatus; } maxThdPerBlock = deviceProp.maxThreadsPerBlock; return cudaSuccess; } void cudaRelaseApp() { cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c); } void cudaShowDevInfo() { std::cout << "CUDA device number: " << deviceNum << std::endl; std::cout << "CUDA device name: " << deviceProp.name << std::endl; std::cout << "CUDA device is " << (deviceProp.integrated == 1 ? "integrated" : "discreted") << std::endl; std::cout << "Multiprocessor number: " << deviceProp.multiProcessorCount << std::endl; std::cout << "register number of each Multiprocessor: " << deviceProp.regsPerMultiprocessor << std::endl; std::cout << "Global L1 cache supported: " << (deviceProp.globalL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "Local L1 cache supported: " << (deviceProp.localL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "L2 cache size: " << deviceProp.l2CacheSize << std::endl; std::cout << "warp size: " << deviceProp.warpSize << std::endl; std::cout << "Max threads dimension: " << deviceProp.maxThreadsDim << std::endl; std::cout << "Max threads per block: " << deviceProp.maxThreadsPerBlock << std::endl; std::cout << "Max threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << std::endl; std::cout << "registers per block: " << deviceProp.regsPerBlock << std::endl; std::cout << "Global memory available on device: " << (double)deviceProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl; std::cout << "Max X blocks: " << maxBlockNumX << std::endl; std::cout << "Max Y blocks: " << maxBlockNumY << std::endl; std::cout << "Max Z blocks: " << maxBlockNumZ << std::endl; std::cout << "Max threads per block: " << maxThdPerBlock << std::endl; std::cout << "Clock rate: " << (double)deviceProp.clockRate / 1024 / 1024 << " GHz" << std::endl; } __global__ void kernel(int *C, const int *A, const int *B) { int i = blockIdx.x * blockDim.x + threadIdx.x; C[i] = (A[i] + B[i]) * (A[i] - B[i]); C[i] = 2 * (C[i] + i) / i; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; } int main() { for (int i = 0; i < MAX_NUMBER; i++) { a[i] = 2; b[i] = 1; } clock_t start_t, end_t; cudaError_t res; res = cudaEnvInit(); if (res != cudaSuccess) return 0; cudaShowDevInfo(); res = cudaMemcpy(dev_a, a, sizeof(cpu_int) * MAX_NUMBER, cudaMemcpyHostToDevice); if (res != cudaSuccess) std::cout << "cudaMemcpy a failed!" << std::endl; res = cudaMemcpy(dev_b, b, sizeof(cpu_int) * MAX_NUMBER, cudaMemcpyHostToDevice); if (res != cudaSuccess) std::cout << "cudaMemcpy b failed!" << std::endl; int usedBlockNum = maxBlockNumZ; int usedThdPerBlock = maxThdPerBlock / 2; int iter_lenth = usedBlockNum * usedThdPerBlock; int iter_times = (MAX_NUMBER % iter_lenth == 0 ? MAX_NUMBER / iter_lenth : (MAX_NUMBER + iter_lenth) / iter_lenth); std::cout << "iter_lenth: " << iter_lenth << std::endl; std::cout << "iter_times: " << iter_times << std::endl; start_t = clock(); for (int i = 0; i < iter_times; i++) { kernel<<<usedBlockNum, usedThdPerBlock>>>(dev_c + iter_lenth * i, dev_a + iter_lenth * i, dev_b + iter_lenth * i); res = cudaGetLastError(); if (res != cudaSuccess) std::cout << "GetLastError failed!" << std::endl; res = cudaDeviceSynchronize(); if (res != cudaSuccess) std::cout << "DeviceSynchronize failed!" << std::endl; if (i == iter_times - 1) { int copy_len = (MAX_NUMBER % iter_lenth == 0 ? iter_lenth : MAX_NUMBER % iter_lenth); res = cudaMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * copy_len, cudaMemcpyDeviceToHost); } else res = cudaMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * iter_lenth, cudaMemcpyDeviceToHost); if (res != cudaSuccess) std::cout << "cudaMemcpy c failed!" << std::endl; } end_t = clock(); std::cout << "GPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; start_t = clock(); for (int i = 1; i < MAX_NUMBER; i++) { c[i] = (a[i] + b[i]) * (a[i] - b[i]); c[i] = 2 * (c[i] + i) / i; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; } end_t = clock(); std::cout << "CPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; cudaRelaseApp(); for (int i = 0; i < 100; i++) std::cout << c[i] << ' '; std::cout << std::endl; system("pause"); return 0; }
code for sm_80 Function : _Z6kernelPiPKiS1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */ /* 0x001fc800078e0200 */ /*0060*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */ /* 0x000fc800078e0206 */ /*0070*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */ /* 0x000fe200078e0206 */ /*0080*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea8000c1e1900 */ /*0090*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */ /* 0x000ea2000c1e1900 */ /*00a0*/ IABS R12, R7 ; /* 0x00000007000c7213 */ /* 0x000fc80000000000 */ /*00b0*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */ /* 0x000e300000209400 */ /*00c0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x001e240000001000 */ /*00d0*/ IADD3 R9, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a097810 */ /* 0x001fcc0007ffe0ff */ /*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */ /* 0x000e22000021f000 */ /*00f0*/ IMAD.IADD R8, R0.reuse, 0x1, R11.reuse ; /* 0x0000000100087824 */ /* 0x144fe400078e020b */ /*0100*/ IMAD.IADD R0, R0, 0x1, -R11 ; /* 0x0000000100007824 */ /* 0x000fe400078e0a0b */ /*0110*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */ /* 0x001fe400078e0a09 */ /*0120*/ IMAD R0, R8, R0, R7 ; /* 0x0000000008007224 */ /* 0x000fe200078e0207 */ /*0130*/ IABS R8, R7 ; /* 0x0000000700087213 */ /* 0x000fe20000000000 */ /*0140*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */ /* 0x000fe400078e02ff */ /*0150*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */ /* 0x000fc400078e00ff */ /*0160*/ IMAD.MOV R13, RZ, RZ, -R8 ; /* 0x000000ffff0d7224 */ /* 0x000fe400078e0a08 */ /*0170*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x000fe200078e00ff */ /*0180*/ IABS R10, R0 ; /* 0x00000000000a7213 */ /* 0x000fe40000000000 */ /*0190*/ LOP3.LUT R0, R0, R7, RZ, 0x3c, !PT ; /* 0x0000000700007212 */ /* 0x000fe200078e3cff */ /*01a0*/ IMAD.HI.U32 R8, R9, R11, R8 ; /* 0x0000000b09087227 */ /* 0x000fc600078e0008 */ /*01b0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe20003f26270 */ /*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R10 ; /* 0x000000ffff097224 */ /* 0x000fe400078e000a */ /*01d0*/ IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a7224 */ /* 0x000fe400078e000d */ /*01e0*/ IMAD.HI.U32 R8, R8, R9, RZ ; /* 0x0000000908087227 */ /* 0x000fc800078e00ff */ /*01f0*/ IMAD R9, R8, R10, R9 ; /* 0x0000000a08097224 */ /* 0x000fca00078e0209 */ /*0200*/ ISETP.GT.U32.AND P2, PT, R12, R9, PT ; /* 0x000000090c00720c */ /* 0x000fda0003f44070 */ /*0210*/ @!P2 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x000000010909a824 */ /* 0x000fe200078e0a0c */ /*0220*/ @!P2 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808a810 */ /* 0x000fe40007ffe0ff */ /*0230*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fe40003f45270 */ /*0240*/ ISETP.GE.U32.AND P0, PT, R9, R12, PT ; /* 0x0000000c0900720c */ /* 0x000fda0003f06070 */ /*0250*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */ /* 0x000fca0007ffe0ff */ /*0260*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */ /* 0x000fe200078e0a08 */ /*0270*/ @!P2 LOP3.LUT R8, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff08a212 */ /* 0x000fe200078e33ff */ /*0280*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */ /* 0x000fc800078e0206 */ /*0290*/ IMAD R9, R8, R8, RZ ; /* 0x0000000808097224 */ /* 0x000fca00078e02ff */ /*02a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe8000c101904 */ /*02b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea8000c1e1900 */ /*02c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */ /* 0x000ea4000c1e1900 */ /*02d0*/ IADD3 R11, R8, R0, R9 ; /* 0x00000000080b7210 */ /* 0x004fca0007ffe009 */ /*02e0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*02f0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea2000c1e1900 */ /*0300*/ IABS R14, R11 ; /* 0x0000000b000e7213 */ /* 0x000fe40000000000 */ /*0310*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*0320*/ IABS R16, R0.reuse ; /* 0x0000000000107213 */ /* 0x080fe40000000000 */ /*0330*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*0340*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fc800078e3cff */ /*0350*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*0360*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*0370*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fe20007ffe0ff */ /*0380*/ IMAD.MOV R10, RZ, RZ, -R16 ; /* 0x000000ffff0a7224 */ /* 0x000fca00078e0a10 */ /*0390*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*03b0*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*03c0*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fe400078e02ff */ /*03d0*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e000e */ /*03e0*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*03f0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */ /* 0x000fc800078e00ff */ /*0400*/ IMAD R8, R9, R10, R12 ; /* 0x0000000a09087224 */ /* 0x000fca00078e020c */ /*0410*/ ISETP.GT.U32.AND P2, PT, R13, R8, PT ; /* 0x000000080d00720c */ /* 0x000fda0003f44070 */ /*0420*/ @!P2 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x000000010808a824 */ /* 0x000fe200078e0a0d */ /*0430*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*0440*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*0450*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */ /* 0x000fda0003f06070 */ /*0460*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*0470*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */ /* 0x000fc800078e0009 */ /*0480*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */ /* 0x000fe200078e0a0b */ /*0490*/ @!P2 LOP3.LUT R11, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff0ba212 */ /* 0x000fca00078e33ff */ /*04a0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*04b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ea2000c1e1900 */ /*04c0*/ IABS R14, R11 ; /* 0x0000000b000e7213 */ /* 0x000fe40000000000 */ /*04d0*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*04e0*/ IABS R16, R0.reuse ; /* 0x0000000000107213 */ /* 0x080fe40000000000 */ /*04f0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*0500*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fc800078e3cff */ /*0510*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*0520*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*0530*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fe20007ffe0ff */ /*0540*/ IMAD.MOV R10, RZ, RZ, -R16 ; /* 0x000000ffff0a7224 */ /* 0x000fca00078e0a10 */ /*0550*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*0560*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*0570*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*0580*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fe400078e02ff */ /*0590*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e000e */ /*05a0*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*05b0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */ /* 0x000fc800078e00ff */ /*05c0*/ IMAD R8, R9, R10, R12 ; /* 0x0000000a09087224 */ /* 0x000fca00078e020c */ /*05d0*/ ISETP.GT.U32.AND P2, PT, R13, R8, PT ; /* 0x000000080d00720c */ /* 0x000fda0003f44070 */ /*05e0*/ @!P2 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x000000010808a824 */ /* 0x000fe200078e0a0d */ /*05f0*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*0600*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*0610*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */ /* 0x000fda0003f06070 */ /*0620*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*0630*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */ /* 0x000fe200078e0a09 */ /*0640*/ @!P2 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff09a212 */ /* 0x000fca00078e33ff */ /*0650*/ IMAD R9, R9, R9, RZ ; /* 0x0000000909097224 */ /* 0x000fca00078e02ff */ /*0660*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe8000c101904 */ /*0670*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea8000c1e1900 */ /*0680*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */ /* 0x000ea4000c1e1900 */ /*0690*/ IADD3 R11, R8, R0, R9 ; /* 0x00000000080b7210 */ /* 0x004fca0007ffe009 */ /*06a0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*06b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea2000c1e1900 */ /*06c0*/ IABS R14, R11 ; /* 0x0000000b000e7213 */ /* 0x000fe40000000000 */ /*06d0*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*06e0*/ IABS R16, R0.reuse ; /* 0x0000000000107213 */ /* 0x080fe40000000000 */ /*06f0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*0700*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fc800078e3cff */ /*0710*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*0720*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*0730*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fe20007ffe0ff */ /*0740*/ IMAD.MOV R10, RZ, RZ, -R16 ; /* 0x000000ffff0a7224 */ /* 0x000fca00078e0a10 */ /*0750*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*0760*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*0770*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*0780*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fe400078e02ff */ /*0790*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e000e */ /*07a0*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*07b0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */ /* 0x000fc800078e00ff */ /*07c0*/ IMAD R8, R9, R10, R12 ; /* 0x0000000a09087224 */ /* 0x000fca00078e020c */ /*07d0*/ ISETP.GT.U32.AND P2, PT, R13, R8, PT ; /* 0x000000080d00720c */ /* 0x000fda0003f44070 */ /*07e0*/ @!P2 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x000000010808a824 */ /* 0x000fe200078e0a0d */ /*07f0*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*0800*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*0810*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */ /* 0x000fda0003f06070 */ /*0820*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*0830*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */ /* 0x000fc800078e0009 */ /*0840*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */ /* 0x000fe200078e0a0b */ /*0850*/ @!P2 LOP3.LUT R11, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff0ba212 */ /* 0x000fca00078e33ff */ /*0860*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*0870*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ea2000c1e1900 */ /*0880*/ IABS R14, R11 ; /* 0x0000000b000e7213 */ /* 0x000fe40000000000 */ /*0890*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*08a0*/ IABS R16, R0.reuse ; /* 0x0000000000107213 */ /* 0x080fe40000000000 */ /*08b0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*08c0*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fc800078e3cff */ /*08d0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*08e0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*08f0*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fe20007ffe0ff */ /*0900*/ IMAD.MOV R10, RZ, RZ, -R16 ; /* 0x000000ffff0a7224 */ /* 0x000fca00078e0a10 */ /*0910*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*0920*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*0930*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*0940*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fe400078e02ff */ /*0950*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e000e */ /*0960*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*0970*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */ /* 0x000fc800078e00ff */ /*0980*/ IMAD R8, R9, R10, R12 ; /* 0x0000000a09087224 */ /* 0x000fca00078e020c */ /*0990*/ ISETP.GT.U32.AND P2, PT, R13, R8, PT ; /* 0x000000080d00720c */ /* 0x000fda0003f44070 */ /*09a0*/ @!P2 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x000000010808a824 */ /* 0x000fe200078e0a0d */ /*09b0*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*09c0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*09d0*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */ /* 0x000fda0003f06070 */ /*09e0*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*09f0*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */ /* 0x000fe200078e0a09 */ /*0a00*/ @!P2 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff09a212 */ /* 0x000fca00078e33ff */ /*0a10*/ IMAD R9, R9, R9, RZ ; /* 0x0000000909097224 */ /* 0x000fca00078e02ff */ /*0a20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe8000c101904 */ /*0a30*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea8000c1e1900 */ /*0a40*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */ /* 0x000ea4000c1e1900 */ /*0a50*/ IADD3 R11, R8, R0, R9 ; /* 0x00000000080b7210 */ /* 0x004fca0007ffe009 */ /*0a60*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*0a70*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea2000c1e1900 */ /*0a80*/ IABS R14, R11 ; /* 0x0000000b000e7213 */ /* 0x000fe40000000000 */ /*0a90*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*0aa0*/ IABS R16, R0.reuse ; /* 0x0000000000107213 */ /* 0x080fe40000000000 */ /*0ab0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*0ac0*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fc800078e3cff */ /*0ad0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*0ae0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*0af0*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fe20007ffe0ff */ /*0b00*/ IMAD.MOV R10, RZ, RZ, -R16 ; /* 0x000000ffff0a7224 */ /* 0x000fca00078e0a10 */ /*0b10*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*0b20*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*0b30*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*0b40*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fe400078e02ff */ /*0b50*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e000e */ /*0b60*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*0b70*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */ /* 0x000fc800078e00ff */ /*0b80*/ IMAD R8, R9, R10, R12 ; /* 0x0000000a09087224 */ /* 0x000fca00078e020c */ /*0b90*/ ISETP.GT.U32.AND P2, PT, R13, R8, PT ; /* 0x000000080d00720c */ /* 0x000fda0003f44070 */ /*0ba0*/ @!P2 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x000000010808a824 */ /* 0x000fe200078e0a0d */ /*0bb0*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*0bc0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*0bd0*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */ /* 0x000fda0003f06070 */ /*0be0*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*0bf0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */ /* 0x000fc800078e0009 */ /*0c00*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */ /* 0x000fe200078e0a0b */ /*0c10*/ @!P2 LOP3.LUT R11, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff0ba212 */ /* 0x000fca00078e33ff */ /*0c20*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*0c30*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ea2000c1e1900 */ /*0c40*/ IABS R14, R11 ; /* 0x0000000b000e7213 */ /* 0x000fe40000000000 */ /*0c50*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*0c60*/ IABS R16, R0.reuse ; /* 0x0000000000107213 */ /* 0x080fe40000000000 */ /*0c70*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*0c80*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fc800078e3cff */ /*0c90*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*0ca0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*0cb0*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fe20007ffe0ff */ /*0cc0*/ IMAD.MOV R10, RZ, RZ, -R16 ; /* 0x000000ffff0a7224 */ /* 0x000fca00078e0a10 */ /*0cd0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*0ce0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*0cf0*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*0d00*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fe400078e02ff */ /*0d10*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e000e */ /*0d20*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*0d30*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */ /* 0x000fc800078e00ff */ /*0d40*/ IMAD R8, R9, R10, R12 ; /* 0x0000000a09087224 */ /* 0x000fca00078e020c */ /*0d50*/ ISETP.GT.U32.AND P2, PT, R13, R8, PT ; /* 0x000000080d00720c */ /* 0x000fda0003f44070 */ /*0d60*/ @!P2 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x000000010808a824 */ /* 0x000fe200078e0a0d */ /*0d70*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*0d80*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*0d90*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */ /* 0x000fda0003f06070 */ /*0da0*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*0db0*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */ /* 0x000fe200078e0a09 */ /*0dc0*/ @!P2 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff09a212 */ /* 0x000fca00078e33ff */ /*0dd0*/ IMAD R9, R9, R9, RZ ; /* 0x0000000909097224 */ /* 0x000fca00078e02ff */ /*0de0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe8000c101904 */ /*0df0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea8000c1e1900 */ /*0e00*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */ /* 0x000ea4000c1e1900 */ /*0e10*/ IADD3 R11, R8, R0, R9 ; /* 0x00000000080b7210 */ /* 0x004fca0007ffe009 */ /*0e20*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0001e8000c101904 */ /*0e30*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x0002a4000c1e1900 */ /*0e40*/ IABS R4, R11 ; /* 0x0000000b00047213 */ /* 0x002fe40000000000 */ /*0e50*/ IABS R13, R0.reuse ; /* 0x00000000000d7213 */ /* 0x084fe40000000000 */ /*0e60*/ IABS R5, R0 ; /* 0x0000000000057213 */ /* 0x000fc40000000000 */ /*0e70*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */ /* 0x000e620000209400 */ /*0e80*/ LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0b7212 */ /* 0x001fe400078e3cff */ /*0e90*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */ /* 0x000fe400078e0a05 */ /*0ea0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */ /* 0x000fc60003f26270 */ /*0eb0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x002e240000001000 */ /*0ec0*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */ /* 0x001fcc0007ffe0ff */ /*0ed0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */ /* 0x000064000021f000 */ /*0ee0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x001fe400078e00ff */ /*0ef0*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */ /* 0x002fc800078e0a09 */ /*0f00*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */ /* 0x000fc800078e02ff */ /*0f10*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */ /* 0x000fcc00078e0008 */ /*0f20*/ IMAD.HI.U32 R9, R9, R4, RZ ; /* 0x0000000409097227 */ /* 0x000fc800078e00ff */ /*0f30*/ IMAD R4, R9, R5, R4 ; /* 0x0000000509047224 */ /* 0x000fca00078e0204 */ /*0f40*/ ISETP.GT.U32.AND P2, PT, R13, R4, PT ; /* 0x000000040d00720c */ /* 0x000fda0003f44070 */ /*0f50*/ @!P2 IMAD.IADD R4, R4, 0x1, -R13 ; /* 0x000000010404a824 */ /* 0x000fe200078e0a0d */ /*0f60*/ @!P2 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909a810 */ /* 0x000fe40007ffe0ff */ /*0f70*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f45270 */ /*0f80*/ ISETP.GE.U32.AND P0, PT, R4, R13, PT ; /* 0x0000000d0400720c */ /* 0x000fda0003f06070 */ /*0f90*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */ /* 0x000fca0007ffe0ff */ /*0fa0*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */ /* 0x000fe200078e0a09 */ /*0fb0*/ @!P2 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff09a212 */ /* 0x000fca00078e33ff */ /*0fc0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x0001e8000c101904 */ /*0fd0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0fe0*/ IABS R10, R9 ; /* 0x00000009000a7213 */ /* 0x000fe40000000000 */ /*0ff0*/ IABS R11, R2.reuse ; /* 0x00000002000b7213 */ /* 0x084fe40000000000 */ /*1000*/ IABS R3, R2.reuse ; /* 0x0000000200037213 */ /* 0x080fe40000000000 */ /*1010*/ I2F.RP R0, R11 ; /* 0x0000000b00007306 */ /* 0x000e620000209400 */ /*1020*/ LOP3.LUT R9, R9, R2, RZ, 0x3c, !PT ; /* 0x0000000209097212 */ /* 0x001fc800078e3cff */ /*1030*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */ /* 0x000fc60003f26270 */ /*1040*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */ /* 0x002e240000001000 */ /*1050*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */ /* 0x001fe20007ffe0ff */ /*1060*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */ /* 0x000fca00078e0a03 */ /*1070*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */ /* 0x000064000021f000 */ /*1080*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x001fe400078e00ff */ /*1090*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */ /* 0x002fc800078e0a05 */ /*10a0*/ IMAD R13, R8, R11, RZ ; /* 0x0000000b080d7224 */ /* 0x000fe400078e02ff */ /*10b0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */ /* 0x000fe400078e000a */ /*10c0*/ IMAD.HI.U32 R5, R5, R13, R4 ; /* 0x0000000d05057227 */ /* 0x000fcc00078e0004 */ /*10d0*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */ /* 0x000fc800078e00ff */ /*10e0*/ IMAD R0, R5, R0, R8 ; /* 0x0000000005007224 */ /* 0x000fca00078e0208 */ /*10f0*/ ISETP.GT.U32.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */ /* 0x000fda0003f44070 */ /*1100*/ @!P2 IMAD.IADD R0, R0, 0x1, -R11 ; /* 0x000000010000a824 */ /* 0x000fe200078e0a0b */ /*1110*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */ /* 0x000fe40007ffe0ff */ /*1120*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fe40003f45270 */ /*1130*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */ /* 0x000fda0003f06070 */ /*1140*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */ /* 0x000fca0007ffe0ff */ /*1150*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */ /* 0x000fe200078e0a05 */ /*1160*/ @!P2 LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff05a212 */ /* 0x000fca00078e33ff */ /*1170*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */ /* 0x000fe2000c101904 */ /*1180*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*1190*/ BRA 0x1190; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*11a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*11b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*11c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*11d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*11e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*11f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*1270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <iostream> #include <ctime> //#define MAX_NUMBER 32768 // 32 * 1024 //#define MAX_NUMBER 65536 // 64 * 1024 //#define MAX_NUMBER 131072 // 128 * 1024 #define MAX_NUMBER (1024 * 1024 * 16) // 128 * 1024 typedef int cuda_int; typedef int cpu_int; const int device = 0; // 在Matebook 14上只有一个MX250 int deviceNum; int maxBlockNumX; int maxBlockNumY; int maxBlockNumZ; int maxThdPerBlock; cudaDeviceProp deviceProp; cuda_int *dev_a = NULL; cuda_int *dev_b = NULL; cuda_int *dev_c = NULL; cpu_int a[MAX_NUMBER]; cpu_int b[MAX_NUMBER]; cpu_int c[MAX_NUMBER]; cudaError_t cudaEnvInit() { cudaError_t cudaStatus; int value; /* 在硬件平台上选择一个支持cuda的设备 */ cudaStatus = cudaGetDeviceCount(&deviceNum); cudaStatus = cudaGetDeviceProperties(&deviceProp, 0); cudaStatus = cudaSetDevice(device); if (cudaStatus != cudaSuccess) { std::cout << "cudaSetDevice failed!" << std::endl; return cudaStatus; } cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimX, device);\ maxBlockNumX = value; cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimY, device); maxBlockNumY = value; cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimZ, device); maxBlockNumZ = value; cudaStatus = cudaMalloc((void **)&dev_a, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_a failed!" << std::endl; return cudaStatus; } cudaStatus = cudaMalloc((void **)&dev_b, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_b failed!" << std::endl; cudaFree(dev_a); return cudaStatus; } cudaStatus = cudaMalloc((void **)&dev_c, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_c failed!" << std::endl; cudaFree(dev_a); cudaFree(dev_b); return cudaStatus; } maxThdPerBlock = deviceProp.maxThreadsPerBlock; return cudaSuccess; } void cudaRelaseApp() { cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c); } void cudaShowDevInfo() { std::cout << "CUDA device number: " << deviceNum << std::endl; std::cout << "CUDA device name: " << deviceProp.name << std::endl; std::cout << "CUDA device is " << (deviceProp.integrated == 1 ? "integrated" : "discreted") << std::endl; std::cout << "Multiprocessor number: " << deviceProp.multiProcessorCount << std::endl; std::cout << "register number of each Multiprocessor: " << deviceProp.regsPerMultiprocessor << std::endl; std::cout << "Global L1 cache supported: " << (deviceProp.globalL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "Local L1 cache supported: " << (deviceProp.localL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "L2 cache size: " << deviceProp.l2CacheSize << std::endl; std::cout << "warp size: " << deviceProp.warpSize << std::endl; std::cout << "Max threads dimension: " << deviceProp.maxThreadsDim << std::endl; std::cout << "Max threads per block: " << deviceProp.maxThreadsPerBlock << std::endl; std::cout << "Max threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << std::endl; std::cout << "registers per block: " << deviceProp.regsPerBlock << std::endl; std::cout << "Global memory available on device: " << (double)deviceProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl; std::cout << "Max X blocks: " << maxBlockNumX << std::endl; std::cout << "Max Y blocks: " << maxBlockNumY << std::endl; std::cout << "Max Z blocks: " << maxBlockNumZ << std::endl; std::cout << "Max threads per block: " << maxThdPerBlock << std::endl; std::cout << "Clock rate: " << (double)deviceProp.clockRate / 1024 / 1024 << " GHz" << std::endl; } __global__ void kernel(int *C, const int *A, const int *B) { int i = blockIdx.x * blockDim.x + threadIdx.x; C[i] = (A[i] + B[i]) * (A[i] - B[i]); C[i] = 2 * (C[i] + i) / i; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; } int main() { for (int i = 0; i < MAX_NUMBER; i++) { a[i] = 2; b[i] = 1; } clock_t start_t, end_t; cudaError_t res; res = cudaEnvInit(); if (res != cudaSuccess) return 0; cudaShowDevInfo(); res = cudaMemcpy(dev_a, a, sizeof(cpu_int) * MAX_NUMBER, cudaMemcpyHostToDevice); if (res != cudaSuccess) std::cout << "cudaMemcpy a failed!" << std::endl; res = cudaMemcpy(dev_b, b, sizeof(cpu_int) * MAX_NUMBER, cudaMemcpyHostToDevice); if (res != cudaSuccess) std::cout << "cudaMemcpy b failed!" << std::endl; int usedBlockNum = maxBlockNumZ; int usedThdPerBlock = maxThdPerBlock / 2; int iter_lenth = usedBlockNum * usedThdPerBlock; int iter_times = (MAX_NUMBER % iter_lenth == 0 ? MAX_NUMBER / iter_lenth : (MAX_NUMBER + iter_lenth) / iter_lenth); std::cout << "iter_lenth: " << iter_lenth << std::endl; std::cout << "iter_times: " << iter_times << std::endl; start_t = clock(); for (int i = 0; i < iter_times; i++) { kernel<<<usedBlockNum, usedThdPerBlock>>>(dev_c + iter_lenth * i, dev_a + iter_lenth * i, dev_b + iter_lenth * i); res = cudaGetLastError(); if (res != cudaSuccess) std::cout << "GetLastError failed!" << std::endl; res = cudaDeviceSynchronize(); if (res != cudaSuccess) std::cout << "DeviceSynchronize failed!" << std::endl; if (i == iter_times - 1) { int copy_len = (MAX_NUMBER % iter_lenth == 0 ? iter_lenth : MAX_NUMBER % iter_lenth); res = cudaMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * copy_len, cudaMemcpyDeviceToHost); } else res = cudaMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * iter_lenth, cudaMemcpyDeviceToHost); if (res != cudaSuccess) std::cout << "cudaMemcpy c failed!" << std::endl; } end_t = clock(); std::cout << "GPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; start_t = clock(); for (int i = 1; i < MAX_NUMBER; i++) { c[i] = (a[i] + b[i]) * (a[i] - b[i]); c[i] = 2 * (c[i] + i) / i; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; } end_t = clock(); std::cout << "CPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; cudaRelaseApp(); for (int i = 0; i < 100; i++) std::cout << c[i] << ' '; std::cout << std::endl; system("pause"); return 0; }
.file "tmpxft_000ce9bb_00000000-6_GPUvsCPU.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3675: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3675: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "cudaSetDevice failed!" .LC1: .string "cudaMalloc dev_a failed!" .LC2: .string "cudaMalloc dev_b failed!" .LC3: .string "cudaMalloc dev_c failed!" .text .globl _Z11cudaEnvInitv .type _Z11cudaEnvInitv, @function _Z11cudaEnvInitv: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $24, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax leaq deviceNum(%rip), %rdi call cudaGetDeviceCount@PLT movl $0, %esi leaq deviceProp(%rip), %rdi call cudaGetDeviceProperties_v2@PLT movl $0, %edi call cudaSetDevice@PLT testl %eax, %eax jne .L27 leaq 4(%rsp), %rbx movl $0, %edx movl $2, %esi movq %rbx, %rdi call cudaDeviceGetAttribute@PLT movl 4(%rsp), %eax movl %eax, maxBlockNumX(%rip) movl $0, %edx movl $3, %esi movq %rbx, %rdi call cudaDeviceGetAttribute@PLT movl 4(%rsp), %eax movl %eax, maxBlockNumY(%rip) movl $0, %edx movl $4, %esi movq %rbx, %rdi call cudaDeviceGetAttribute@PLT movl 4(%rsp), %eax movl %eax, maxBlockNumZ(%rip) movl $67108864, %esi leaq dev_a(%rip), %rdi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L28 movl $67108864, %esi leaq dev_b(%rip), %rdi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L29 movl $67108864, %esi leaq dev_c(%rip), %rdi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L30 movl 320+deviceProp(%rip), %eax movl %eax, maxThdPerBlock(%rip) jmp .L3 .L27: movl %eax, %ebx movl $21, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %rbp testq %rbp, %rbp je .L31 cmpb $0, 56(%rbp) je .L7 movzbl 67(%rbp), %esi .L8: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT .L3: movq 8(%rsp), %rax subq %fs:40, %rax jne .L32 movl %ebx, %eax addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state movq 8(%rsp), %rax subq %fs:40, %rax jne .L33 call _ZSt16__throw_bad_castv@PLT .L33: call __stack_chk_fail@PLT .L7: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L8 .L28: movl $24, %edx leaq .LC1(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %rbp testq %rbp, %rbp je .L34 cmpb $0, 56(%rbp) je .L13 movzbl 67(%rbp), %esi .L14: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT jmp .L3 .L34: movq 8(%rsp), %rax subq %fs:40, %rax jne .L35 call _ZSt16__throw_bad_castv@PLT .L35: call __stack_chk_fail@PLT .L13: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L14 .L29: movl $24, %edx leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %rbp testq %rbp, %rbp je .L36 cmpb $0, 56(%rbp) je .L18 movzbl 67(%rbp), %esi .L19: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movq dev_a(%rip), %rdi call cudaFree@PLT jmp .L3 .L36: movq 8(%rsp), %rax subq %fs:40, %rax jne .L37 call _ZSt16__throw_bad_castv@PLT .L37: call __stack_chk_fail@PLT .L18: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L19 .L30: movl $24, %edx leaq .LC3(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %rbp testq %rbp, %rbp je .L38 cmpb $0, 56(%rbp) je .L23 movzbl 67(%rbp), %esi .L24: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movq dev_a(%rip), %rdi call cudaFree@PLT movq dev_b(%rip), %rdi call cudaFree@PLT jmp .L3 .L38: movq 8(%rsp), %rax subq %fs:40, %rax jne .L39 call _ZSt16__throw_bad_castv@PLT .L39: call __stack_chk_fail@PLT .L23: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L24 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size _Z11cudaEnvInitv, .-_Z11cudaEnvInitv .globl _Z13cudaRelaseAppv .type _Z13cudaRelaseAppv, @function _Z13cudaRelaseAppv: .LFB3670: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq dev_a(%rip), %rdi call cudaFree@PLT movq dev_b(%rip), %rdi call cudaFree@PLT movq dev_c(%rip), %rdi call cudaFree@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3670: .size _Z13cudaRelaseAppv, .-_Z13cudaRelaseAppv .section .rodata.str1.1 .LC4: .string "integrated" .LC5: .string "discreted" .LC6: .string "Yes" .LC7: .string "No" .LC8: .string "CUDA device number: " .LC9: .string "CUDA device name: " .LC10: .string "CUDA device is " .LC11: .string "Multiprocessor number: " .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC12: .string "register number of each Multiprocessor: " .section .rodata.str1.1 .LC13: .string "Global L1 cache supported: " .LC14: .string "Local L1 cache supported: " .LC15: .string "L2 cache size: " .LC16: .string "warp size: " .LC17: .string "Max threads dimension: " .LC18: .string "Max threads per block: " .section .rodata.str1.8 .align 8 .LC19: .string "Max threads per multiprocessor: " .section .rodata.str1.1 .LC20: .string "registers per block: " .section .rodata.str1.8 .align 8 .LC21: .string "Global memory available on device: " .section .rodata.str1.1 .LC23: .string "MB" .LC24: .string "Max X blocks: " .LC25: .string "Max Y blocks: " .LC26: .string "Max Z blocks: " .LC27: .string "Clock rate: " .LC28: .string " GHz" .text .globl _Z15cudaShowDevInfov .type _Z15cudaShowDevInfov, @function _Z15cudaShowDevInfov: .LFB3671: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movl $20, %edx leaq .LC8(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl deviceNum(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L109 cmpb $0, 56(%rbp) je .L44 movzbl 67(%rbp), %esi .L45: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $18, %edx leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT leaq deviceProp(%rip), %rbp movq %rbp, %rdi call strlen@PLT movq %rax, %rdx movq %rbp, %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L110 cmpb $0, 56(%rbx) je .L47 movzbl 67(%rbx), %esi .L48: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $15, %edx leaq .LC10(%rip), %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT cmpl $1, 396+deviceProp(%rip) leaq .LC5(%rip), %rbx leaq .LC4(%rip), %rax cmove %rax, %rbx movq %rbx, %rdi call strlen@PLT movq %rax, %rdx movq %rbx, %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L111 cmpb $0, 56(%rbx) je .L51 movzbl 67(%rbx), %esi .L52: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $23, %edx leaq .LC11(%rip), %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 388+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L112 cmpb $0, 56(%rbp) je .L54 movzbl 67(%rbp), %esi .L55: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $40, %edx leaq .LC12(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 648+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L113 cmpb $0, 56(%rbp) je .L57 movzbl 67(%rbp), %esi .L58: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $27, %edx leaq .LC13(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT cmpl $1, 632+deviceProp(%rip) leaq .LC7(%rip), %rbx leaq .LC6(%rip), %rax cmove %rax, %rbx movq %rbx, %rdi call strlen@PLT movq %rax, %rdx movq %rbx, %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L114 cmpb $0, 56(%rbx) je .L61 movzbl 67(%rbx), %esi .L62: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $26, %edx leaq .LC14(%rip), %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT cmpl $1, 636+deviceProp(%rip) leaq .LC7(%rip), %rbx leaq .LC6(%rip), %rax cmove %rax, %rbx movq %rbx, %rdi call strlen@PLT movq %rax, %rdx movq %rbx, %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L115 cmpb $0, 56(%rbx) je .L65 movzbl 67(%rbx), %esi .L66: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $15, %edx leaq .LC15(%rip), %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 616+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L116 cmpb $0, 56(%rbp) je .L68 movzbl 67(%rbp), %esi .L69: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $11, %edx leaq .LC16(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 308+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L117 cmpb $0, 56(%rbp) je .L71 movzbl 67(%rbp), %esi .L72: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $23, %edx leaq .LC17(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT leaq 324+deviceProp(%rip), %rsi movq %rbx, %rdi call _ZNSo9_M_insertIPKvEERSoT_@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L118 cmpb $0, 56(%rbp) je .L74 movzbl 67(%rbp), %esi .L75: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $23, %edx leaq .LC18(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 320+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L119 cmpb $0, 56(%rbp) je .L77 movzbl 67(%rbp), %esi .L78: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $32, %edx leaq .LC19(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 624+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L120 cmpb $0, 56(%rbp) je .L80 movzbl 67(%rbp), %esi .L81: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $21, %edx leaq .LC20(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 304+deviceProp(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L121 cmpb $0, 56(%rbp) je .L83 movzbl 67(%rbp), %esi .L84: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $35, %edx leaq .LC21(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq 288+deviceProp(%rip), %rax testq %rax, %rax js .L85 pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 .L86: movsd .LC22(%rip), %xmm1 mulsd %xmm1, %xmm0 mulsd %xmm1, %xmm0 leaq _ZSt4cout(%rip), %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $2, %edx leaq .LC23(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L122 cmpb $0, 56(%rbp) je .L88 movzbl 67(%rbp), %esi .L89: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $14, %edx leaq .LC24(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl maxBlockNumX(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L123 cmpb $0, 56(%rbp) je .L91 movzbl 67(%rbp), %esi .L92: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $14, %edx leaq .LC25(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl maxBlockNumY(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L124 cmpb $0, 56(%rbp) je .L94 movzbl 67(%rbp), %esi .L95: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $14, %edx leaq .LC26(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl maxBlockNumZ(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L125 cmpb $0, 56(%rbp) je .L97 movzbl 67(%rbp), %esi .L98: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $23, %edx leaq .LC18(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl maxThdPerBlock(%rip), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L126 cmpb $0, 56(%rbp) je .L100 movzbl 67(%rbp), %esi .L101: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $12, %edx leaq .LC27(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT pxor %xmm0, %xmm0 cvtsi2sdl 348+deviceProp(%rip), %xmm0 movsd .LC22(%rip), %xmm1 mulsd %xmm1, %xmm0 mulsd %xmm1, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $4, %edx leaq .LC28(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L127 cmpb $0, 56(%rbp) je .L103 movzbl 67(%rbp), %esi .L104: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L109: .cfi_restore_state call _ZSt16__throw_bad_castv@PLT .L44: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L45 .L110: call _ZSt16__throw_bad_castv@PLT .L47: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L48 .L111: call _ZSt16__throw_bad_castv@PLT .L51: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L52 .L112: call _ZSt16__throw_bad_castv@PLT .L54: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L55 .L113: call _ZSt16__throw_bad_castv@PLT .L57: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L58 .L114: call _ZSt16__throw_bad_castv@PLT .L61: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L62 .L115: call _ZSt16__throw_bad_castv@PLT .L65: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L66 .L116: call _ZSt16__throw_bad_castv@PLT .L68: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L69 .L117: call _ZSt16__throw_bad_castv@PLT .L71: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L72 .L118: call _ZSt16__throw_bad_castv@PLT .L74: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L75 .L119: call _ZSt16__throw_bad_castv@PLT .L77: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L78 .L120: call _ZSt16__throw_bad_castv@PLT .L80: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L81 .L121: call _ZSt16__throw_bad_castv@PLT .L83: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L84 .L85: movq %rax, %rdx shrq %rdx andl $1, %eax orq %rax, %rdx pxor %xmm0, %xmm0 cvtsi2sdq %rdx, %xmm0 addsd %xmm0, %xmm0 jmp .L86 .L122: call _ZSt16__throw_bad_castv@PLT .L88: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L89 .L123: call _ZSt16__throw_bad_castv@PLT .L91: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L92 .L124: call _ZSt16__throw_bad_castv@PLT .L94: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L95 .L125: call _ZSt16__throw_bad_castv@PLT .L97: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L98 .L126: call _ZSt16__throw_bad_castv@PLT .L100: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L101 .L127: call _ZSt16__throw_bad_castv@PLT .L103: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L104 .cfi_endproc .LFE3671: .size _Z15cudaShowDevInfov, .-_Z15cudaShowDevInfov .globl _Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_ .type _Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_, @function _Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_: .LFB3697: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L132 .L128: movq 120(%rsp), %rax subq %fs:40, %rax jne .L133 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L132: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6kernelPiPKiS1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L128 .L133: call __stack_chk_fail@PLT .cfi_endproc .LFE3697: .size _Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_, .-_Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_ .globl _Z6kernelPiPKiS1_ .type _Z6kernelPiPKiS1_, @function _Z6kernelPiPKiS1_: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _Z6kernelPiPKiS1_, .-_Z6kernelPiPKiS1_ .section .rodata.str1.1 .LC29: .string "cudaMemcpy a failed!" .LC30: .string "cudaMemcpy b failed!" .LC31: .string "iter_lenth: " .LC32: .string "iter_times: " .LC33: .string "GetLastError failed!" .LC34: .string "DeviceSynchronize failed!" .LC35: .string "cudaMemcpy c failed!" .LC36: .string "GPU used time: " .LC39: .string "ms" .LC40: .string "CPU used time: " .LC41: .string "pause" .text .globl main .type main, @function main: .LFB3672: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq a(%rip), %rcx leaq b(%rip), %rdx .L137: movl $2, (%rcx,%rax) movl $1, (%rdx,%rax) addq $4, %rax cmpq $67108864, %rax jne .L137 call _Z11cudaEnvInitv movl %eax, %ebx testl %eax, %eax je .L161 .L138: movq 56(%rsp), %rax subq %fs:40, %rax jne .L162 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L161: .cfi_restore_state call _Z15cudaShowDevInfov movl $1, %ecx movl $67108864, %edx leaq a(%rip), %rsi movq dev_a(%rip), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L163 .L139: movl $1, %ecx movl $67108864, %edx leaq b(%rip), %rsi movq dev_b(%rip), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L164 .L140: movl maxBlockNumZ(%rip), %r13d movl maxThdPerBlock(%rip), %eax movl $2, %ecx cltd idivl %ecx movl %eax, 4(%rsp) imull %r13d, %eax movl %eax, %r12d movl $16777216, %eax movl $0, %edx idivl %r12d movl %edx, %r14d movl %eax, %ebp testl %edx, %edx je .L142 leal 16777216(%r12), %eax cltd idivl %r12d movl %eax, %ebp .L142: leaq .LC31(%rip), %rsi leaq _ZSt4cout(%rip), %r15 movq %r15, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %r12d, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC32(%rip), %rsi movq %r15, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebp, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT call clock@PLT movq %rax, 24(%rsp) testl %ebp, %ebp jle .L143 movslq %r12d, %rax salq $2, %rax movq %rax, 8(%rsp) testl %r14d, %r14d movl %r14d, %eax cmove %r12d, %eax cltq salq $2, %rax movq %rax, 16(%rsp) movl $0, %r14d leaq c(%rip), %r15 jmp .L150 .L163: leaq .LC29(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L139 .L164: leaq .LC30(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L140 .L166: movslq %ebx, %rdi salq $2, %rdi movq %rdi, %rdx addq dev_b(%rip), %rdx movq %rdi, %rsi addq dev_a(%rip), %rsi addq dev_c(%rip), %rdi call _Z31__device_stub__Z6kernelPiPKiS1_PiPKiS1_ jmp .L144 .L167: leaq .LC33(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L145 .L168: leaq .LC34(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L146 .L169: movslq %ebx, %rax salq $2, %rax movq %rax, %rsi addq dev_c(%rip), %rsi leaq (%rax,%r15), %rdi movl $2, %ecx movq 16(%rsp), %rdx call cudaMemcpy@PLT .L148: testl %eax, %eax jne .L165 .L149: addl $1, %r14d addl %r12d, %ebx cmpl %r14d, %ebp je .L143 .L150: movl 4(%rsp), %eax movl %eax, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl %r13d, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L166 .L144: call cudaGetLastError@PLT testl %eax, %eax jne .L167 .L145: call cudaDeviceSynchronize@PLT testl %eax, %eax jne .L168 .L146: leal -1(%rbp), %eax cmpl %r14d, %eax je .L169 movslq %ebx, %rdi salq $2, %rdi movq %rdi, %rsi addq dev_c(%rip), %rsi addq %r15, %rdi movl $2, %ecx movq 8(%rsp), %rdx call cudaMemcpy@PLT jmp .L148 .L165: leaq .LC35(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L149 .L143: call clock@PLT movq %rax, %rbx leaq .LC36(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq 24(%rsp), %rax subq %rax, %rbx pxor %xmm0, %xmm0 cvtsi2sdq %rbx, %xmm0 mulsd .LC37(%rip), %xmm0 divsd .LC38(%rip), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC39(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT call clock@PLT movq %rax, %rbx movl $1, %esi leaq a(%rip), %r9 leaq b(%rip), %r8 leaq c(%rip), %rdi .L151: movl (%r9,%rsi,4), %ecx movl (%r8,%rsi,4), %r10d leal (%rcx,%r10), %eax movl %ecx, %edx subl %r10d, %edx imull %edx, %eax addl %esi, %eax addl %eax, %eax cltd idivl %esi imull %eax, %eax addl %ecx, %eax addl %r10d, %eax cltd idivl %ecx cltd idivl %ecx imull %eax, %eax addl %ecx, %eax addl %r10d, %eax cltd idivl %ecx cltd idivl %ecx imull %eax, %eax addl %ecx, %eax addl %r10d, %eax cltd idivl %ecx cltd idivl %ecx imull %eax, %eax addl %ecx, %eax addl %r10d, %eax cltd idivl %ecx cltd idivl %ecx movl %eax, (%rdi,%rsi,4) addq $1, %rsi cmpq $16777216, %rsi jne .L151 call clock@PLT movq %rax, %rbp leaq .LC40(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi subq %rbx, %rbp pxor %xmm0, %xmm0 cvtsi2sdq %rbp, %xmm0 mulsd .LC37(%rip), %xmm0 divsd .LC38(%rip), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC39(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT call _Z13cudaRelaseAppv leaq c(%rip), %rbx leaq 400(%rbx), %r12 leaq _ZSt4cout(%rip), %rbp jmp .L154 .L152: movl $32, %esi call _ZNSo3putEc@PLT .L153: addq $4, %rbx cmpq %r12, %rbx je .L170 .L154: movl (%rbx), %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movb $32, 44(%rsp) movq (%rax), %rax movq -24(%rax), %rax cmpq $0, 16(%rdi,%rax) je .L152 leaq 44(%rsp), %rsi movl $1, %edx call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L153 .L170: leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC41(%rip), %rdi call system@PLT jmp .L138 .L162: call __stack_chk_fail@PLT .cfi_endproc .LFE3672: .size main, .-main .section .rodata.str1.1 .LC42: .string "_Z6kernelPiPKiS1_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3700: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC42(%rip), %rdx movq %rdx, %rcx leaq _Z6kernelPiPKiS1_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3700: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl c .bss .align 32 .type c, @object .size c, 67108864 c: .zero 67108864 .globl b .align 32 .type b, @object .size b, 67108864 b: .zero 67108864 .globl a .align 32 .type a, @object .size a, 67108864 a: .zero 67108864 .globl dev_c .align 8 .type dev_c, @object .size dev_c, 8 dev_c: .zero 8 .globl dev_b .align 8 .type dev_b, @object .size dev_b, 8 dev_b: .zero 8 .globl dev_a .align 8 .type dev_a, @object .size dev_a, 8 dev_a: .zero 8 .globl deviceProp .align 32 .type deviceProp, @object .size deviceProp, 1032 deviceProp: .zero 1032 .globl maxThdPerBlock .align 4 .type maxThdPerBlock, @object .size maxThdPerBlock, 4 maxThdPerBlock: .zero 4 .globl maxBlockNumZ .align 4 .type maxBlockNumZ, @object .size maxBlockNumZ, 4 maxBlockNumZ: .zero 4 .globl maxBlockNumY .align 4 .type maxBlockNumY, @object .size maxBlockNumY, 4 maxBlockNumY: .zero 4 .globl maxBlockNumX .align 4 .type maxBlockNumX, @object .size maxBlockNumX, 4 maxBlockNumX: .zero 4 .globl deviceNum .align 4 .type deviceNum, @object .size deviceNum, 4 deviceNum: .zero 4 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC22: .long 0 .long 1062207488 .align 8 .LC37: .long 0 .long 1083129856 .align 8 .LC38: .long 0 .long 1093567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <iostream> #include <ctime> //#define MAX_NUMBER 32768 // 32 * 1024 //#define MAX_NUMBER 65536 // 64 * 1024 //#define MAX_NUMBER 131072 // 128 * 1024 #define MAX_NUMBER (1024 * 1024 * 16) // 128 * 1024 typedef int cuda_int; typedef int cpu_int; const int device = 0; // 在Matebook 14上只有一个MX250 int deviceNum; int maxBlockNumX; int maxBlockNumY; int maxBlockNumZ; int maxThdPerBlock; cudaDeviceProp deviceProp; cuda_int *dev_a = NULL; cuda_int *dev_b = NULL; cuda_int *dev_c = NULL; cpu_int a[MAX_NUMBER]; cpu_int b[MAX_NUMBER]; cpu_int c[MAX_NUMBER]; cudaError_t cudaEnvInit() { cudaError_t cudaStatus; int value; /* 在硬件平台上选择一个支持cuda的设备 */ cudaStatus = cudaGetDeviceCount(&deviceNum); cudaStatus = cudaGetDeviceProperties(&deviceProp, 0); cudaStatus = cudaSetDevice(device); if (cudaStatus != cudaSuccess) { std::cout << "cudaSetDevice failed!" << std::endl; return cudaStatus; } cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimX, device);\ maxBlockNumX = value; cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimY, device); maxBlockNumY = value; cudaStatus = cudaDeviceGetAttribute(&value, cudaDevAttrMaxBlockDimZ, device); maxBlockNumZ = value; cudaStatus = cudaMalloc((void **)&dev_a, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_a failed!" << std::endl; return cudaStatus; } cudaStatus = cudaMalloc((void **)&dev_b, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_b failed!" << std::endl; cudaFree(dev_a); return cudaStatus; } cudaStatus = cudaMalloc((void **)&dev_c, MAX_NUMBER * sizeof(int)); if (cudaStatus != cudaSuccess) { std::cout << "cudaMalloc dev_c failed!" << std::endl; cudaFree(dev_a); cudaFree(dev_b); return cudaStatus; } maxThdPerBlock = deviceProp.maxThreadsPerBlock; return cudaSuccess; } void cudaRelaseApp() { cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c); } void cudaShowDevInfo() { std::cout << "CUDA device number: " << deviceNum << std::endl; std::cout << "CUDA device name: " << deviceProp.name << std::endl; std::cout << "CUDA device is " << (deviceProp.integrated == 1 ? "integrated" : "discreted") << std::endl; std::cout << "Multiprocessor number: " << deviceProp.multiProcessorCount << std::endl; std::cout << "register number of each Multiprocessor: " << deviceProp.regsPerMultiprocessor << std::endl; std::cout << "Global L1 cache supported: " << (deviceProp.globalL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "Local L1 cache supported: " << (deviceProp.localL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "L2 cache size: " << deviceProp.l2CacheSize << std::endl; std::cout << "warp size: " << deviceProp.warpSize << std::endl; std::cout << "Max threads dimension: " << deviceProp.maxThreadsDim << std::endl; std::cout << "Max threads per block: " << deviceProp.maxThreadsPerBlock << std::endl; std::cout << "Max threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << std::endl; std::cout << "registers per block: " << deviceProp.regsPerBlock << std::endl; std::cout << "Global memory available on device: " << (double)deviceProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl; std::cout << "Max X blocks: " << maxBlockNumX << std::endl; std::cout << "Max Y blocks: " << maxBlockNumY << std::endl; std::cout << "Max Z blocks: " << maxBlockNumZ << std::endl; std::cout << "Max threads per block: " << maxThdPerBlock << std::endl; std::cout << "Clock rate: " << (double)deviceProp.clockRate / 1024 / 1024 << " GHz" << std::endl; } __global__ void kernel(int *C, const int *A, const int *B) { int i = blockIdx.x * blockDim.x + threadIdx.x; C[i] = (A[i] + B[i]) * (A[i] - B[i]); C[i] = 2 * (C[i] + i) / i; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; } int main() { for (int i = 0; i < MAX_NUMBER; i++) { a[i] = 2; b[i] = 1; } clock_t start_t, end_t; cudaError_t res; res = cudaEnvInit(); if (res != cudaSuccess) return 0; cudaShowDevInfo(); res = cudaMemcpy(dev_a, a, sizeof(cpu_int) * MAX_NUMBER, cudaMemcpyHostToDevice); if (res != cudaSuccess) std::cout << "cudaMemcpy a failed!" << std::endl; res = cudaMemcpy(dev_b, b, sizeof(cpu_int) * MAX_NUMBER, cudaMemcpyHostToDevice); if (res != cudaSuccess) std::cout << "cudaMemcpy b failed!" << std::endl; int usedBlockNum = maxBlockNumZ; int usedThdPerBlock = maxThdPerBlock / 2; int iter_lenth = usedBlockNum * usedThdPerBlock; int iter_times = (MAX_NUMBER % iter_lenth == 0 ? MAX_NUMBER / iter_lenth : (MAX_NUMBER + iter_lenth) / iter_lenth); std::cout << "iter_lenth: " << iter_lenth << std::endl; std::cout << "iter_times: " << iter_times << std::endl; start_t = clock(); for (int i = 0; i < iter_times; i++) { kernel<<<usedBlockNum, usedThdPerBlock>>>(dev_c + iter_lenth * i, dev_a + iter_lenth * i, dev_b + iter_lenth * i); res = cudaGetLastError(); if (res != cudaSuccess) std::cout << "GetLastError failed!" << std::endl; res = cudaDeviceSynchronize(); if (res != cudaSuccess) std::cout << "DeviceSynchronize failed!" << std::endl; if (i == iter_times - 1) { int copy_len = (MAX_NUMBER % iter_lenth == 0 ? iter_lenth : MAX_NUMBER % iter_lenth); res = cudaMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * copy_len, cudaMemcpyDeviceToHost); } else res = cudaMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * iter_lenth, cudaMemcpyDeviceToHost); if (res != cudaSuccess) std::cout << "cudaMemcpy c failed!" << std::endl; } end_t = clock(); std::cout << "GPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; start_t = clock(); for (int i = 1; i < MAX_NUMBER; i++) { c[i] = (a[i] + b[i]) * (a[i] - b[i]); c[i] = 2 * (c[i] + i) / i; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; } end_t = clock(); std::cout << "CPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; cudaRelaseApp(); for (int i = 0; i < 100; i++) std::cout << c[i] << ' '; std::cout << std::endl; system("pause"); return 0; }
#include "hip/hip_runtime.h" #include <stdio.h> #include <iostream> #include <ctime> //#define MAX_NUMBER 32768 // 32 * 1024 //#define MAX_NUMBER 65536 // 64 * 1024 //#define MAX_NUMBER 131072 // 128 * 1024 #define MAX_NUMBER (1024 * 1024 * 16) // 128 * 1024 typedef int cuda_int; typedef int cpu_int; const int device = 0; // 在Matebook 14上只有一个MX250 int deviceNum; int maxBlockNumX; int maxBlockNumY; int maxBlockNumZ; int maxThdPerBlock; hipDeviceProp_t deviceProp; cuda_int *dev_a = NULL; cuda_int *dev_b = NULL; cuda_int *dev_c = NULL; cpu_int a[MAX_NUMBER]; cpu_int b[MAX_NUMBER]; cpu_int c[MAX_NUMBER]; hipError_t cudaEnvInit() { hipError_t cudaStatus; int value; /* 在硬件平台上选择一个支持cuda的设备 */ cudaStatus = hipGetDeviceCount(&deviceNum); cudaStatus = hipGetDeviceProperties(&deviceProp, 0); cudaStatus = hipSetDevice(device); if (cudaStatus != hipSuccess) { std::cout << "hipSetDevice failed!" << std::endl; return cudaStatus; } cudaStatus = hipDeviceGetAttribute(&value, hipDeviceAttributeMaxBlockDimX, device);\ maxBlockNumX = value; cudaStatus = hipDeviceGetAttribute(&value, hipDeviceAttributeMaxBlockDimY, device); maxBlockNumY = value; cudaStatus = hipDeviceGetAttribute(&value, hipDeviceAttributeMaxBlockDimZ, device); maxBlockNumZ = value; cudaStatus = hipMalloc((void **)&dev_a, MAX_NUMBER * sizeof(int)); if (cudaStatus != hipSuccess) { std::cout << "hipMalloc dev_a failed!" << std::endl; return cudaStatus; } cudaStatus = hipMalloc((void **)&dev_b, MAX_NUMBER * sizeof(int)); if (cudaStatus != hipSuccess) { std::cout << "hipMalloc dev_b failed!" << std::endl; hipFree(dev_a); return cudaStatus; } cudaStatus = hipMalloc((void **)&dev_c, MAX_NUMBER * sizeof(int)); if (cudaStatus != hipSuccess) { std::cout << "hipMalloc dev_c failed!" << std::endl; hipFree(dev_a); hipFree(dev_b); return cudaStatus; } maxThdPerBlock = deviceProp.maxThreadsPerBlock; return hipSuccess; } void cudaRelaseApp() { hipFree(dev_a); hipFree(dev_b); hipFree(dev_c); } void cudaShowDevInfo() { std::cout << "CUDA device number: " << deviceNum << std::endl; std::cout << "CUDA device name: " << deviceProp.name << std::endl; std::cout << "CUDA device is " << (deviceProp.integrated == 1 ? "integrated" : "discreted") << std::endl; std::cout << "Multiprocessor number: " << deviceProp.multiProcessorCount << std::endl; std::cout << "register number of each Multiprocessor: " << deviceProp.regsPerMultiprocessor << std::endl; std::cout << "Global L1 cache supported: " << (deviceProp.globalL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "Local L1 cache supported: " << (deviceProp.localL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "L2 cache size: " << deviceProp.l2CacheSize << std::endl; std::cout << "warp size: " << deviceProp.warpSize << std::endl; std::cout << "Max threads dimension: " << deviceProp.maxThreadsDim << std::endl; std::cout << "Max threads per block: " << deviceProp.maxThreadsPerBlock << std::endl; std::cout << "Max threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << std::endl; std::cout << "registers per block: " << deviceProp.regsPerBlock << std::endl; std::cout << "Global memory available on device: " << (double)deviceProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl; std::cout << "Max X blocks: " << maxBlockNumX << std::endl; std::cout << "Max Y blocks: " << maxBlockNumY << std::endl; std::cout << "Max Z blocks: " << maxBlockNumZ << std::endl; std::cout << "Max threads per block: " << maxThdPerBlock << std::endl; std::cout << "Clock rate: " << (double)deviceProp.clockRate / 1024 / 1024 << " GHz" << std::endl; } __global__ void kernel(int *C, const int *A, const int *B) { int i = blockIdx.x * blockDim.x + threadIdx.x; C[i] = (A[i] + B[i]) * (A[i] - B[i]); C[i] = 2 * (C[i] + i) / i; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; } int main() { for (int i = 0; i < MAX_NUMBER; i++) { a[i] = 2; b[i] = 1; } clock_t start_t, end_t; hipError_t res; res = cudaEnvInit(); if (res != hipSuccess) return 0; cudaShowDevInfo(); res = hipMemcpy(dev_a, a, sizeof(cpu_int) * MAX_NUMBER, hipMemcpyHostToDevice); if (res != hipSuccess) std::cout << "hipMemcpy a failed!" << std::endl; res = hipMemcpy(dev_b, b, sizeof(cpu_int) * MAX_NUMBER, hipMemcpyHostToDevice); if (res != hipSuccess) std::cout << "hipMemcpy b failed!" << std::endl; int usedBlockNum = maxBlockNumZ; int usedThdPerBlock = maxThdPerBlock / 2; int iter_lenth = usedBlockNum * usedThdPerBlock; int iter_times = (MAX_NUMBER % iter_lenth == 0 ? MAX_NUMBER / iter_lenth : (MAX_NUMBER + iter_lenth) / iter_lenth); std::cout << "iter_lenth: " << iter_lenth << std::endl; std::cout << "iter_times: " << iter_times << std::endl; start_t = clock(); for (int i = 0; i < iter_times; i++) { kernel<<<usedBlockNum, usedThdPerBlock>>>(dev_c + iter_lenth * i, dev_a + iter_lenth * i, dev_b + iter_lenth * i); res = hipGetLastError(); if (res != hipSuccess) std::cout << "GetLastError failed!" << std::endl; res = hipDeviceSynchronize(); if (res != hipSuccess) std::cout << "DeviceSynchronize failed!" << std::endl; if (i == iter_times - 1) { int copy_len = (MAX_NUMBER % iter_lenth == 0 ? iter_lenth : MAX_NUMBER % iter_lenth); res = hipMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * copy_len, hipMemcpyDeviceToHost); } else res = hipMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * iter_lenth, hipMemcpyDeviceToHost); if (res != hipSuccess) std::cout << "hipMemcpy c failed!" << std::endl; } end_t = clock(); std::cout << "GPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; start_t = clock(); for (int i = 1; i < MAX_NUMBER; i++) { c[i] = (a[i] + b[i]) * (a[i] - b[i]); c[i] = 2 * (c[i] + i) / i; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; } end_t = clock(); std::cout << "CPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; cudaRelaseApp(); for (int i = 0; i < 100; i++) std::cout << c[i] << ' '; std::cout << std::endl; system("pause"); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include "hip/hip_runtime.h" #include <stdio.h> #include <iostream> #include <ctime> //#define MAX_NUMBER 32768 // 32 * 1024 //#define MAX_NUMBER 65536 // 64 * 1024 //#define MAX_NUMBER 131072 // 128 * 1024 #define MAX_NUMBER (1024 * 1024 * 16) // 128 * 1024 typedef int cuda_int; typedef int cpu_int; const int device = 0; // 在Matebook 14上只有一个MX250 int deviceNum; int maxBlockNumX; int maxBlockNumY; int maxBlockNumZ; int maxThdPerBlock; hipDeviceProp_t deviceProp; cuda_int *dev_a = NULL; cuda_int *dev_b = NULL; cuda_int *dev_c = NULL; cpu_int a[MAX_NUMBER]; cpu_int b[MAX_NUMBER]; cpu_int c[MAX_NUMBER]; hipError_t cudaEnvInit() { hipError_t cudaStatus; int value; /* 在硬件平台上选择一个支持cuda的设备 */ cudaStatus = hipGetDeviceCount(&deviceNum); cudaStatus = hipGetDeviceProperties(&deviceProp, 0); cudaStatus = hipSetDevice(device); if (cudaStatus != hipSuccess) { std::cout << "hipSetDevice failed!" << std::endl; return cudaStatus; } cudaStatus = hipDeviceGetAttribute(&value, hipDeviceAttributeMaxBlockDimX, device);\ maxBlockNumX = value; cudaStatus = hipDeviceGetAttribute(&value, hipDeviceAttributeMaxBlockDimY, device); maxBlockNumY = value; cudaStatus = hipDeviceGetAttribute(&value, hipDeviceAttributeMaxBlockDimZ, device); maxBlockNumZ = value; cudaStatus = hipMalloc((void **)&dev_a, MAX_NUMBER * sizeof(int)); if (cudaStatus != hipSuccess) { std::cout << "hipMalloc dev_a failed!" << std::endl; return cudaStatus; } cudaStatus = hipMalloc((void **)&dev_b, MAX_NUMBER * sizeof(int)); if (cudaStatus != hipSuccess) { std::cout << "hipMalloc dev_b failed!" << std::endl; hipFree(dev_a); return cudaStatus; } cudaStatus = hipMalloc((void **)&dev_c, MAX_NUMBER * sizeof(int)); if (cudaStatus != hipSuccess) { std::cout << "hipMalloc dev_c failed!" << std::endl; hipFree(dev_a); hipFree(dev_b); return cudaStatus; } maxThdPerBlock = deviceProp.maxThreadsPerBlock; return hipSuccess; } void cudaRelaseApp() { hipFree(dev_a); hipFree(dev_b); hipFree(dev_c); } void cudaShowDevInfo() { std::cout << "CUDA device number: " << deviceNum << std::endl; std::cout << "CUDA device name: " << deviceProp.name << std::endl; std::cout << "CUDA device is " << (deviceProp.integrated == 1 ? "integrated" : "discreted") << std::endl; std::cout << "Multiprocessor number: " << deviceProp.multiProcessorCount << std::endl; std::cout << "register number of each Multiprocessor: " << deviceProp.regsPerMultiprocessor << std::endl; std::cout << "Global L1 cache supported: " << (deviceProp.globalL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "Local L1 cache supported: " << (deviceProp.localL1CacheSupported == 1 ? "Yes" : "No") << std::endl; std::cout << "L2 cache size: " << deviceProp.l2CacheSize << std::endl; std::cout << "warp size: " << deviceProp.warpSize << std::endl; std::cout << "Max threads dimension: " << deviceProp.maxThreadsDim << std::endl; std::cout << "Max threads per block: " << deviceProp.maxThreadsPerBlock << std::endl; std::cout << "Max threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << std::endl; std::cout << "registers per block: " << deviceProp.regsPerBlock << std::endl; std::cout << "Global memory available on device: " << (double)deviceProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl; std::cout << "Max X blocks: " << maxBlockNumX << std::endl; std::cout << "Max Y blocks: " << maxBlockNumY << std::endl; std::cout << "Max Z blocks: " << maxBlockNumZ << std::endl; std::cout << "Max threads per block: " << maxThdPerBlock << std::endl; std::cout << "Clock rate: " << (double)deviceProp.clockRate / 1024 / 1024 << " GHz" << std::endl; } __global__ void kernel(int *C, const int *A, const int *B) { int i = blockIdx.x * blockDim.x + threadIdx.x; C[i] = (A[i] + B[i]) * (A[i] - B[i]); C[i] = 2 * (C[i] + i) / i; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; C[i] = C[i] * C[i]; C[i] = C[i] + A[i] + B[i]; C[i] = C[i] / A[i]; C[i] = C[i] / B[i]; } int main() { for (int i = 0; i < MAX_NUMBER; i++) { a[i] = 2; b[i] = 1; } clock_t start_t, end_t; hipError_t res; res = cudaEnvInit(); if (res != hipSuccess) return 0; cudaShowDevInfo(); res = hipMemcpy(dev_a, a, sizeof(cpu_int) * MAX_NUMBER, hipMemcpyHostToDevice); if (res != hipSuccess) std::cout << "hipMemcpy a failed!" << std::endl; res = hipMemcpy(dev_b, b, sizeof(cpu_int) * MAX_NUMBER, hipMemcpyHostToDevice); if (res != hipSuccess) std::cout << "hipMemcpy b failed!" << std::endl; int usedBlockNum = maxBlockNumZ; int usedThdPerBlock = maxThdPerBlock / 2; int iter_lenth = usedBlockNum * usedThdPerBlock; int iter_times = (MAX_NUMBER % iter_lenth == 0 ? MAX_NUMBER / iter_lenth : (MAX_NUMBER + iter_lenth) / iter_lenth); std::cout << "iter_lenth: " << iter_lenth << std::endl; std::cout << "iter_times: " << iter_times << std::endl; start_t = clock(); for (int i = 0; i < iter_times; i++) { kernel<<<usedBlockNum, usedThdPerBlock>>>(dev_c + iter_lenth * i, dev_a + iter_lenth * i, dev_b + iter_lenth * i); res = hipGetLastError(); if (res != hipSuccess) std::cout << "GetLastError failed!" << std::endl; res = hipDeviceSynchronize(); if (res != hipSuccess) std::cout << "DeviceSynchronize failed!" << std::endl; if (i == iter_times - 1) { int copy_len = (MAX_NUMBER % iter_lenth == 0 ? iter_lenth : MAX_NUMBER % iter_lenth); res = hipMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * copy_len, hipMemcpyDeviceToHost); } else res = hipMemcpy(c + iter_lenth * i, dev_c + iter_lenth * i, sizeof(cpu_int) * iter_lenth, hipMemcpyDeviceToHost); if (res != hipSuccess) std::cout << "hipMemcpy c failed!" << std::endl; } end_t = clock(); std::cout << "GPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; start_t = clock(); for (int i = 1; i < MAX_NUMBER; i++) { c[i] = (a[i] + b[i]) * (a[i] - b[i]); c[i] = 2 * (c[i] + i) / i; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; c[i] = c[i] * c[i]; c[i] = c[i] + a[i] + b[i]; c[i] = c[i] / a[i]; c[i] = c[i] / a[i]; } end_t = clock(); std::cout << "CPU used time: " << (double)(end_t - start_t) * 1000 / CLOCKS_PER_SEC << "ms" << std::endl; cudaRelaseApp(); for (int i = 0; i < 100; i++) std::cout << c[i] << ' '; std::cout << std::endl; system("pause"); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6kernelPiPKiS1_ .globl _Z6kernelPiPKiS1_ .p2align 8 .type _Z6kernelPiPKiS1_,@function _Z6kernelPiPKiS1_: s_clause 0x2 s_load_b32 s2, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 v_ashrrev_i32_e32 v10, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_nc_u32_e32 v9, v1, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v11, v9, v10 v_add_co_u32 v4, vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v6, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo global_load_b32 v0, v[4:5], off global_load_b32 v8, v[6:7], off v_cvt_f32_u32_e32 v9, v11 v_sub_nc_u32_e32 v13, 0, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_rcp_iflag_f32_e32 v9, v9 s_waitcnt vmcnt(0) s_waitcnt_depctr 0xfff v_dual_mul_f32 v9, 0x4f7ffffe, v9 :: v_dual_add_nc_u32 v12, v8, v0 v_sub_nc_u32_e32 v0, v0, v8 v_cvt_u32_f32_e32 v14, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[8:9], null, v12, v0, v[1:2] v_mul_lo_u32 v0, v13, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v1, 1, v8 v_bfe_i32 v8, v8, 30, 1 v_mul_hi_u32 v0, v14, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v1, v1, v8 v_add_nc_u32_e32 v0, v14, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v1, v1, v8 v_xor_b32_e32 v8, v8, v10 v_mul_hi_u32 v0, v1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v9, v0, v11 v_sub_nc_u32_e32 v1, v1, v9 v_add_nc_u32_e32 v9, 1, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v12, v1, v11 v_cmp_ge_u32_e32 vcc_lo, v1, v11 v_dual_cndmask_b32 v0, v0, v9 :: v_dual_cndmask_b32 v1, v1, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v9, 1, v0 v_cmp_ge_u32_e32 vcc_lo, v1, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v0, v0, v9, vcc_lo v_xor_b32_e32 v0, v0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v0, v0, v8 v_mul_lo_u32 v8, v0, v0 v_add_co_u32 v0, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo global_store_b32 v[0:1], v8, off global_load_b32 v2, v[4:5], off global_load_b32 v3, v[6:7], off s_waitcnt vmcnt(0) v_add3_u32 v2, v2, v8, v3 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off v_ashrrev_i32_e32 v11, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v11 v_xor_b32_e32 v2, v2, v11 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v8 v_xor_b32_e32 v3, v3, v8 v_xor_b32_e32 v8, v11, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v9, v3 v_sub_nc_u32_e32 v10, 0, v3 v_rcp_iflag_f32_e32 v9, v9 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 v_mul_lo_u32 v10, v10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v9, v2, v9 v_mul_lo_u32 v10, v9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v10 v_add_nc_u32_e32 v10, 1, v9 v_sub_nc_u32_e32 v12, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v2, v2, v12 v_add_nc_u32_e32 v10, 1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v9, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v8 v_sub_nc_u32_e32 v2, v2, v8 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[6:7], off v_ashrrev_i32_e32 v11, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v11 v_xor_b32_e32 v2, v2, v11 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v8 v_xor_b32_e32 v3, v3, v8 v_xor_b32_e32 v8, v11, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v9, v3 v_sub_nc_u32_e32 v10, 0, v3 v_rcp_iflag_f32_e32 v9, v9 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 v_mul_lo_u32 v10, v10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v9, v2, v9 v_mul_lo_u32 v10, v9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v10 v_add_nc_u32_e32 v10, 1, v9 v_sub_nc_u32_e32 v12, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v2, v2, v12 v_add_nc_u32_e32 v10, 1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v9, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v8 v_sub_nc_u32_e32 v2, v2, v8 s_delay_alu instid0(VALU_DEP_1) v_mul_lo_u32 v2, v2, v2 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off global_load_b32 v8, v[6:7], off s_waitcnt vmcnt(0) v_add3_u32 v2, v3, v2, v8 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off v_ashrrev_i32_e32 v11, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v11 v_xor_b32_e32 v2, v2, v11 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v8 v_xor_b32_e32 v3, v3, v8 v_xor_b32_e32 v8, v11, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v9, v3 v_sub_nc_u32_e32 v10, 0, v3 v_rcp_iflag_f32_e32 v9, v9 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 v_mul_lo_u32 v10, v10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v9, v2, v9 v_mul_lo_u32 v10, v9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v10 v_add_nc_u32_e32 v10, 1, v9 v_sub_nc_u32_e32 v12, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v2, v2, v12 v_add_nc_u32_e32 v10, 1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v9, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v8 v_sub_nc_u32_e32 v2, v2, v8 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[6:7], off v_ashrrev_i32_e32 v11, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v11 v_xor_b32_e32 v2, v2, v11 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v8 v_xor_b32_e32 v3, v3, v8 v_xor_b32_e32 v8, v11, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v9, v3 v_sub_nc_u32_e32 v10, 0, v3 v_rcp_iflag_f32_e32 v9, v9 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 v_mul_lo_u32 v10, v10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v9, v2, v9 v_mul_lo_u32 v10, v9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v10 v_add_nc_u32_e32 v10, 1, v9 v_sub_nc_u32_e32 v12, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v2, v2, v12 v_add_nc_u32_e32 v10, 1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v9, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v8 v_sub_nc_u32_e32 v2, v2, v8 s_delay_alu instid0(VALU_DEP_1) v_mul_lo_u32 v2, v2, v2 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off global_load_b32 v8, v[6:7], off s_waitcnt vmcnt(0) v_add3_u32 v2, v3, v2, v8 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off v_ashrrev_i32_e32 v11, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v11 v_xor_b32_e32 v2, v2, v11 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v8 v_xor_b32_e32 v3, v3, v8 v_xor_b32_e32 v8, v11, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v9, v3 v_sub_nc_u32_e32 v10, 0, v3 v_rcp_iflag_f32_e32 v9, v9 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 v_mul_lo_u32 v10, v10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v9, v2, v9 v_mul_lo_u32 v10, v9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v10 v_add_nc_u32_e32 v10, 1, v9 v_sub_nc_u32_e32 v12, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v2, v2, v12 v_add_nc_u32_e32 v10, 1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v9, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v8 v_sub_nc_u32_e32 v2, v2, v8 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[6:7], off v_ashrrev_i32_e32 v11, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v11 v_xor_b32_e32 v2, v2, v11 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v8 v_xor_b32_e32 v3, v3, v8 v_xor_b32_e32 v8, v11, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v9, v3 v_sub_nc_u32_e32 v10, 0, v3 v_rcp_iflag_f32_e32 v9, v9 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 v_mul_lo_u32 v10, v10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v9, v2, v9 v_mul_lo_u32 v10, v9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v10 v_add_nc_u32_e32 v10, 1, v9 v_sub_nc_u32_e32 v12, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v2, v2, v12 v_add_nc_u32_e32 v10, 1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v9, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v8 v_sub_nc_u32_e32 v2, v2, v8 s_delay_alu instid0(VALU_DEP_1) v_mul_lo_u32 v2, v2, v2 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off global_load_b32 v8, v[6:7], off s_waitcnt vmcnt(0) v_add3_u32 v2, v3, v2, v8 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[4:5], off v_ashrrev_i32_e32 v9, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v9 v_xor_b32_e32 v2, v2, v9 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v4 v_xor_b32_e32 v3, v3, v4 v_xor_b32_e32 v4, v9, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v5, v3 v_sub_nc_u32_e32 v8, 0, v3 v_rcp_iflag_f32_e32 v5, v5 s_waitcnt_depctr 0xfff v_mul_f32_e32 v5, 0x4f7ffffe, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v5, v5 v_mul_lo_u32 v8, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v8, v5, v8 v_add_nc_u32_e32 v5, v5, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v5, v2, v5 v_mul_lo_u32 v8, v5, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v8 v_add_nc_u32_e32 v8, 1, v5 v_sub_nc_u32_e32 v10, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v2, v2, v10 v_add_nc_u32_e32 v8, 1, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v5, v8, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v4 v_sub_nc_u32_e32 v2, v2, v4 global_store_b32 v[0:1], v2, off global_load_b32 v3, v[6:7], off v_ashrrev_i32_e32 v7, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v7 v_xor_b32_e32 v2, v2, v7 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v3, v4 v_xor_b32_e32 v3, v3, v4 v_xor_b32_e32 v4, v7, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v5, v3 v_sub_nc_u32_e32 v6, 0, v3 v_rcp_iflag_f32_e32 v5, v5 s_waitcnt_depctr 0xfff v_mul_f32_e32 v5, 0x4f7ffffe, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v5, v5 v_mul_lo_u32 v6, v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v6, v5, v6 v_add_nc_u32_e32 v5, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v5, v2, v5 v_mul_lo_u32 v6, v5, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v2, v6 v_add_nc_u32_e32 v6, 1, v5 v_sub_nc_u32_e32 v8, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v2, v2, v8 v_add_nc_u32_e32 v6, 1, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_u32_e32 vcc_lo, v2, v3 v_cndmask_b32_e32 v2, v5, v6, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v4 v_sub_nc_u32_e32 v2, v2, v4 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6kernelPiPKiS1_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 15 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6kernelPiPKiS1_, .Lfunc_end0-_Z6kernelPiPKiS1_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6kernelPiPKiS1_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6kernelPiPKiS1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 15 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <iostream> #include <fstream> #include <vector> #include <utility> #include <cstring> #include <stdlib.h> #include <cuda.h> using namespace std; int main(){ ifstream in; in.open("enc_mat"); int r; in >> r; vector<pair<bool,vector<int> > > encmat(r); for(int i = 0; i<r; i++){ in >> encmat[i].first; int size; in >> size; vector<int> v(size); for(int j=0;j<size;j++){ in >> v[j]; } encmat[i].second = v; v.clear(); } int masksize = (r%8>0 ? r/8+1 : r/8); unsigned char* mask = (unsigned char*)malloc(masksize*sizeof(unsigned char)); memset(mask,0,masksize); for(int i=0;i<r;i++){ bool flag = encmat[i].first; vector<int> v = encmat[i].second; int count = 0; for(int j=0; j<v.size(); j++){ if(flag){ for(int k=count;k<count+v[j];k++){ mask[k/8] |= (0x80 >> k%8); } count+=v[j]; flag=0; } else{ count += v[j]; flag=1; } } } for(int i=0;i<masksize;i++) printf("%d\n",mask[i]); return 0; }
code for sm_80
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <iostream> #include <fstream> #include <vector> #include <utility> #include <cstring> #include <stdlib.h> #include <cuda.h> using namespace std; int main(){ ifstream in; in.open("enc_mat"); int r; in >> r; vector<pair<bool,vector<int> > > encmat(r); for(int i = 0; i<r; i++){ in >> encmat[i].first; int size; in >> size; vector<int> v(size); for(int j=0;j<size;j++){ in >> v[j]; } encmat[i].second = v; v.clear(); } int masksize = (r%8>0 ? r/8+1 : r/8); unsigned char* mask = (unsigned char*)malloc(masksize*sizeof(unsigned char)); memset(mask,0,masksize); for(int i=0;i<r;i++){ bool flag = encmat[i].first; vector<int> v = encmat[i].second; int count = 0; for(int j=0; j<v.size(); j++){ if(flag){ for(int k=count;k<count+v[j];k++){ mask[k/8] |= (0x80 >> k%8); } count+=v[j]; flag=0; } else{ count += v[j]; flag=1; } } } for(int i=0;i<masksize;i++) printf("%d\n",mask[i]); return 0; }
.file "tmpxft_000b5fc0_00000000-6_gpufold.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4170: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4170: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4193: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4193: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,"axG",@progbits,_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED5Ev,comdat .align 2 .weak _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .type _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev, @function _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev: .LFB4527: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %r12 movq 8(%rdi), %rbp movq (%rdi), %rbx cmpq %rbx, %rbp jne .L8 .L6: movq (%r12), %rdi testq %rdi, %rdi je .L5 movq 16(%r12), %rsi subq %rdi, %rsi call _ZdlPvm@PLT .L5: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state addq $32, %rbx cmpq %rbx, %rbp je .L6 .L8: movq 8(%rbx), %rdi testq %rdi, %rdi je .L7 movq 24(%rbx), %rsi subq %rdi, %rsi call _ZdlPvm@PLT jmp .L7 .cfi_endproc .LFE4527: .size _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev, .-_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .weak _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev .set _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev,_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .section .text._ZNSt6vectorIiSaIiEEaSERKS1_,"axG",@progbits,_ZNSt6vectorIiSaIiEEaSERKS1_,comdat .align 2 .weak _ZNSt6vectorIiSaIiEEaSERKS1_ .type _ZNSt6vectorIiSaIiEEaSERKS1_, @function _ZNSt6vectorIiSaIiEEaSERKS1_: .LFB4544: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx cmpq %rdi, %rsi je .L13 movq %rsi, %r12 movq (%rsi), %r13 movq 8(%rsi), %rbp subq %r13, %rbp movq (%rdi), %rdi movq 16(%rbx), %rax subq %rdi, %rax cmpq %rbp, %rax jb .L26 movq 8(%rbx), %rdx subq %rdi, %rdx cmpq %rbp, %rdx jb .L20 cmpq $4, %rbp jle .L21 movq %rbp, %rdx movq %r13, %rsi call memmove@PLT jmp .L19 .L26: movabsq $9223372036854775804, %rax cmpq %rbp, %rax jb .L27 movq %rbp, %rdi call _Znwm@PLT movq %rax, %r12 cmpq $4, %rbp jle .L16 movq %rbp, %rdx movq %r13, %rsi movq %rax, %rdi call memmove@PLT .L17: movq (%rbx), %rdi testq %rdi, %rdi je .L18 movq 16(%rbx), %rsi subq %rdi, %rsi call _ZdlPvm@PLT .L18: movq %r12, (%rbx) addq %rbp, %r12 movq %r12, 16(%rbx) .L19: addq (%rbx), %rbp movq %rbp, 8(%rbx) .L13: movq %rbx, %rax addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L27: .cfi_restore_state call _ZSt28__throw_bad_array_new_lengthv@PLT .L16: movl 0(%r13), %eax movl %eax, (%r12) jmp .L17 .L21: jne .L19 movl 0(%r13), %eax movl %eax, (%rdi) jmp .L19 .L20: cmpq $4, %rdx jle .L22 movq %r13, %rsi call memmove@PLT .L23: movq 8(%rbx), %rdi movq %rdi, %rsi subq (%rbx), %rsi addq (%r12), %rsi movq 8(%r12), %rdx subq %rsi, %rdx cmpq $4, %rdx jle .L24 call memmove@PLT jmp .L19 .L22: jne .L23 movl 0(%r13), %eax movl %eax, (%rdi) jmp .L23 .L24: jne .L19 movl (%rsi), %eax movl %eax, (%rdi) jmp .L19 .cfi_endproc .LFE4544: .size _ZNSt6vectorIiSaIiEEaSERKS1_, .-_ZNSt6vectorIiSaIiEEaSERKS1_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "enc_mat" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "cannot create std::vector larger than max_size()" .section .rodata.str1.1 .LC2: .string "%d\n" .text .globl main .type main, @function main: .LFB4163: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4163 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $648, %rsp .cfi_def_cfa_offset 704 movq %fs:40, %rax movq %rax, 632(%rsp) xorl %eax, %eax leaq 112(%rsp), %rbx movq %rbx, %rdi .LEHB0: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT .LEHE0: movl $8, %edx leaq .LC0(%rip), %rsi movq %rbx, %rdi .LEHB1: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT leaq 40(%rsp), %rsi movq %rbx, %rdi call _ZNSirsERi@PLT movslq 40(%rsp), %rdx movq %rdx, %rax shrq $58, %rax jne .L86 movq $0, 56(%rsp) movq $0, 64(%rsp) testq %rdx, %rdx je .L31 movq %rdx, %rbx salq $5, %rbx movq %rbx, %rdi call _Znwm@PLT jmp .L87 .L86: movq 632(%rsp), %rax subq %fs:40, %rax jne .L88 leaq .LC1(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE1: .L73: endbr64 movq %rax, %rbx jmp .L64 .L88: call __stack_chk_fail@PLT .L87: movq %rax, 8(%rsp) movq %rax, 48(%rsp) leaq (%rax,%rbx), %rdx movq %rdx, 64(%rsp) .L32: movb $0, (%rax) movq $0, 8(%rax) movq $0, 16(%rax) movq $0, 24(%rax) addq $32, %rax cmpq %rdx, %rax jne .L32 .L66: movq %rdx, 56(%rsp) movl 40(%rsp), %ecx testl %ecx, %ecx jle .L33 movq 8(%rsp), %r13 movl $0, %r14d jmp .L42 .L94: leaq 44(%rsp), %rsi leaq 112(%rsp), %rdi .LEHB2: call _ZNSirsERi@PLT movslq 44(%rsp), %rbx movabsq $2305843009213693951, %rax cmpq %rbx, %rax jb .L89 movq $0, 88(%rsp) movq $0, 96(%rsp) testq %rbx, %rbx je .L36 leaq 0(,%rbx,4), %r15 movq %r15, %rdi call _Znwm@PLT jmp .L90 .L89: movq 632(%rsp), %rax subq %fs:40, %rax jne .L91 leaq .LC1(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE2: .L91: call __stack_chk_fail@PLT .L90: movq %rax, %rbp movq %rax, 80(%rsp) leaq (%rax,%r15), %rdx movq %rdx, 96(%rsp) movl $0, (%rax) leaq 4(%rax), %rax cmpq $1, %rbx je .L69 cmpq %rax, %rdx je .L70 .L38: movl $0, (%rax) addq $4, %rax cmpq %rax, %rdx jne .L38 jmp .L37 .L69: movq %rax, %rdx jmp .L37 .L70: movq %rax, %rdx jmp .L37 .L92: addq $1, %rbx cmpl %ebx, 44(%rsp) jle .L39 .L40: leaq 0(%rbp,%rbx,4), %rsi movq %r12, %rdi .LEHB3: call _ZNSirsERi@PLT jmp .L92 .L39: leaq 80(%rsp), %rsi leaq 8(%r13), %rdi call _ZNSt6vectorIiSaIiEEaSERKS1_ .LEHE3: testq %rbp, %rbp je .L41 movq %r15, %rsi movq %rbp, %rdi call _ZdlPvm@PLT .L41: addl $1, %r14d movl 40(%rsp), %ecx addq $32, %r13 cmpl %r14d, %ecx jle .L93 .L42: leaq 112(%rsp), %rdi movq %r13, %rsi .LEHB4: call _ZNSi10_M_extractIbEERSiRT_@PLT jmp .L94 .L93: movl $8, %esi movl %ecx, %eax cltd idivl %esi testl %edx, %edx jle .L33 movl %ecx, %eax cltd idivl %esi addl $1, %eax movl %eax, 20(%rsp) movslq %eax, %r15 movq %r15, 24(%rsp) movq %r15, %rdi call malloc@PLT movq %rax, %rbx movq %r15, %rcx movq %r15, %rdx movl $0, %esi movq %rax, %rdi call __memset_chk@PLT cmpl $0, 40(%rsp) jle .L44 .L43: movq 8(%rsp), %r14 movl $0, %r15d jmp .L58 .L33: movl $8, %esi movl %ecx, %eax cltd idivl %esi movl %eax, 20(%rsp) movslq %eax, %r15 movq %r15, 24(%rsp) movq %r15, %rdi call malloc@PLT movq %rax, %rbx movq %r15, %rcx movq %r15, %rdx movl $0, %esi movq %rax, %rdi call __memset_chk@PLT cmpl $0, 40(%rsp) jg .L43 .L45: cmpl $0, 20(%rsp) jle .L59 .L44: movq %rbx, %rbp movq 24(%rsp), %rax addq %rax, %rbx leaq .LC2(%rip), %r12 jmp .L60 .L98: movq 632(%rsp), %rax subq %fs:40, %rax jne .L95 call _ZSt28__throw_bad_array_new_lengthv@PLT .L75: endbr64 movq %rax, %rbx jmp .L63 .L95: call __stack_chk_fail@PLT .L99: movq %rax, %r13 .L46: movq 8(%r12), %rsi movq 16(%r12), %r12 subq %rsi, %r12 cmpq $4, %r12 jle .L49 movq %r12, %rdx movq %r13, %rdi call memmove@PLT .L50: sarq $2, %r12 .L67: movl $0, %esi movl $0, %edx movl $128, %r8d movl $0, %r9d jmp .L56 .L71: movl $0, %r13d jmp .L46 .L49: je .L96 testq %r12, %r12 jne .L97 .L52: testq %r13, %r13 je .L57 movq 8(%rsp), %rsi movq %r13, %rdi call _ZdlPvm@PLT .L57: addl $1, %r15d addq $32, %r14 cmpl %r15d, 40(%rsp) jle .L45 .L58: movq %r14, %r12 movzbl (%r14), %ebp movq 16(%r14), %rax subq 8(%r14), %rax movq %rax, 8(%rsp) je .L71 movabsq $9223372036854775804, %rdi cmpq %rax, %rdi jb .L98 movq 8(%rsp), %rdi call _Znwm@PLT jmp .L99 .L96: movl (%rsi), %eax movl %eax, 0(%r13) jmp .L50 .L97: sarq $2, %r12 jmp .L67 .L53: addl 0(%r13,%rsi,4), %edx movl $1, %ebp .L54: addq $1, %rsi cmpq %r12, %rsi jnb .L52 .L56: testb %bpl, %bpl je .L53 movl %edx, %edi addl 0(%r13,%rsi,4), %edi cmpl %edi, %edx jge .L72 .L55: leal 7(%rdx), %eax testl %edx, %edx cmovns %edx, %eax sarl $3, %eax cltq movl %edx, %ecx andl $7, %ecx movl %r8d, %r10d sarl %cl, %r10d orb %r10b, (%rbx,%rax) addl $1, %edx cmpl %edi, %edx jne .L55 movl %edi, %edx movl %r9d, %ebp jmp .L54 .L72: movl %edi, %edx movl $0, %ebp jmp .L54 .L100: addq $1, %rbp cmpq %rbp, %rbx je .L59 .L60: movzbl 0(%rbp), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .LEHE4: jmp .L100 .L59: leaq 48(%rsp), %rdi call _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev leaq 112(%rsp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT movq 632(%rsp), %rax subq %fs:40, %rax jne .L101 movl $0, %eax addq $648, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L74: .cfi_restore_state endbr64 movq %rax, %rbx testq %rbp, %rbp je .L63 movq %r15, %rsi movq %rbp, %rdi call _ZdlPvm@PLT .L63: leaq 48(%rsp), %rdi call _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev .L64: leaq 112(%rsp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT movq 632(%rsp), %rax subq %fs:40, %rax je .L65 call __stack_chk_fail@PLT .L65: movq %rbx, %rdi .LEHB5: call _Unwind_Resume@PLT .LEHE5: .L36: movq $0, 80(%rsp) movq $0, 96(%rsp) movq %rbx, %r15 movl $0, %ebp movl $0, %edx .L37: movq %rdx, 88(%rsp) cmpl $0, 44(%rsp) jle .L39 movl $0, %ebx leaq 112(%rsp), %r12 jmp .L40 .L31: movq $0, 48(%rsp) movq $0, 64(%rsp) movq $0, 8(%rsp) movl $0, %edx jmp .L66 .L101: call __stack_chk_fail@PLT .cfi_endproc .LFE4163: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA4163: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4163-.LLSDACSB4163 .LLSDACSB4163: .uleb128 .LEHB0-.LFB4163 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB4163 .uleb128 .LEHE1-.LEHB1 .uleb128 .L73-.LFB4163 .uleb128 0 .uleb128 .LEHB2-.LFB4163 .uleb128 .LEHE2-.LEHB2 .uleb128 .L75-.LFB4163 .uleb128 0 .uleb128 .LEHB3-.LFB4163 .uleb128 .LEHE3-.LEHB3 .uleb128 .L74-.LFB4163 .uleb128 0 .uleb128 .LEHB4-.LFB4163 .uleb128 .LEHE4-.LEHB4 .uleb128 .L75-.LFB4163 .uleb128 0 .uleb128 .LEHB5-.LFB4163 .uleb128 .LEHE5-.LEHB5 .uleb128 0 .uleb128 0 .LLSDACSE4163: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <iostream> #include <fstream> #include <vector> #include <utility> #include <cstring> #include <stdlib.h> #include <cuda.h> using namespace std; int main(){ ifstream in; in.open("enc_mat"); int r; in >> r; vector<pair<bool,vector<int> > > encmat(r); for(int i = 0; i<r; i++){ in >> encmat[i].first; int size; in >> size; vector<int> v(size); for(int j=0;j<size;j++){ in >> v[j]; } encmat[i].second = v; v.clear(); } int masksize = (r%8>0 ? r/8+1 : r/8); unsigned char* mask = (unsigned char*)malloc(masksize*sizeof(unsigned char)); memset(mask,0,masksize); for(int i=0;i<r;i++){ bool flag = encmat[i].first; vector<int> v = encmat[i].second; int count = 0; for(int j=0; j<v.size(); j++){ if(flag){ for(int k=count;k<count+v[j];k++){ mask[k/8] |= (0x80 >> k%8); } count+=v[j]; flag=0; } else{ count += v[j]; flag=1; } } } for(int i=0;i<masksize;i++) printf("%d\n",mask[i]); return 0; }
#include <stdio.h> #include <iostream> #include <fstream> #include <vector> #include <utility> #include <cstring> #include <stdlib.h> #include <hip/hip_runtime.h> using namespace std; int main(){ ifstream in; in.open("enc_mat"); int r; in >> r; vector<pair<bool,vector<int> > > encmat(r); for(int i = 0; i<r; i++){ in >> encmat[i].first; int size; in >> size; vector<int> v(size); for(int j=0;j<size;j++){ in >> v[j]; } encmat[i].second = v; v.clear(); } int masksize = (r%8>0 ? r/8+1 : r/8); unsigned char* mask = (unsigned char*)malloc(masksize*sizeof(unsigned char)); memset(mask,0,masksize); for(int i=0;i<r;i++){ bool flag = encmat[i].first; vector<int> v = encmat[i].second; int count = 0; for(int j=0; j<v.size(); j++){ if(flag){ for(int k=count;k<count+v[j];k++){ mask[k/8] |= (0x80 >> k%8); } count+=v[j]; flag=0; } else{ count += v[j]; flag=1; } } } for(int i=0;i<masksize;i++) printf("%d\n",mask[i]); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <stdio.h> #include <iostream> #include <fstream> #include <vector> #include <utility> #include <cstring> #include <stdlib.h> #include <hip/hip_runtime.h> using namespace std; int main(){ ifstream in; in.open("enc_mat"); int r; in >> r; vector<pair<bool,vector<int> > > encmat(r); for(int i = 0; i<r; i++){ in >> encmat[i].first; int size; in >> size; vector<int> v(size); for(int j=0;j<size;j++){ in >> v[j]; } encmat[i].second = v; v.clear(); } int masksize = (r%8>0 ? r/8+1 : r/8); unsigned char* mask = (unsigned char*)malloc(masksize*sizeof(unsigned char)); memset(mask,0,masksize); for(int i=0;i<r;i++){ bool flag = encmat[i].first; vector<int> v = encmat[i].second; int count = 0; for(int j=0; j<v.size(); j++){ if(flag){ for(int k=count;k<count+v[j];k++){ mask[k/8] |= (0x80 >> k%8); } count+=v[j]; flag=0; } else{ count += v[j]; flag=1; } } } for(int i=0;i<masksize;i++) printf("%d\n",mask[i]); return 0; }
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <stdio.h> #include <iostream> #include <fstream> #include <vector> #include <utility> #include <cstring> #include <stdlib.h> #include <hip/hip_runtime.h> using namespace std; int main(){ ifstream in; in.open("enc_mat"); int r; in >> r; vector<pair<bool,vector<int> > > encmat(r); for(int i = 0; i<r; i++){ in >> encmat[i].first; int size; in >> size; vector<int> v(size); for(int j=0;j<size;j++){ in >> v[j]; } encmat[i].second = v; v.clear(); } int masksize = (r%8>0 ? r/8+1 : r/8); unsigned char* mask = (unsigned char*)malloc(masksize*sizeof(unsigned char)); memset(mask,0,masksize); for(int i=0;i<r;i++){ bool flag = encmat[i].first; vector<int> v = encmat[i].second; int count = 0; for(int j=0; j<v.size(); j++){ if(flag){ for(int k=count;k<count+v[j];k++){ mask[k/8] |= (0x80 >> k%8); } count+=v[j]; flag=0; } else{ count += v[j]; flag=1; } } } for(int i=0;i<masksize;i++) printf("%d\n",mask[i]); return 0; }
.text .file "gpufold.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI0_0: .zero 16 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $616, %rsp # imm = 0x268 .cfi_def_cfa_offset 672 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 96(%rsp), %rbx movq %rbx, %rdi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev leaq 112(%rsp), %rdi .Ltmp0: movl $.L.str, %esi movl $8, %edx callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode .Ltmp1: # %bb.1: # %.noexc movq 96(%rsp), %rcx addq -24(%rcx), %rbx xorl %esi, %esi testq %rax, %rax jne .LBB0_3 # %bb.2: movl 32(%rbx), %esi orl $4, %esi .LBB0_3: # %.invoke .Ltmp2: movq %rbx, %rdi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .Ltmp3: # %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit .Ltmp5: leaq 96(%rsp), %rdi leaq 8(%rsp), %rsi callq _ZNSirsERi .Ltmp6: # %bb.5: movslq 8(%rsp), %rbx testq %rbx, %rbx js .LBB0_75 # %bb.6: # %_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EE17_S_check_init_lenEmRKS4_.exit.i xorps %xmm0, %xmm0 movaps %xmm0, 16(%rsp) movq $0, 32(%rsp) testl %ebx, %ebx je .LBB0_8 # %bb.7: # %_ZNSt16allocator_traitsISaISt4pairIbSt6vectorIiSaIiEEEEE8allocateERS5_m.exit.i.i.i.i movq %rbx, %rdi shlq $5, %rdi .Ltmp8: callq _Znwm .Ltmp9: jmp .LBB0_9 .LBB0_8: xorl %eax, %eax .LBB0_9: # %_ZNSt12_Vector_baseISt4pairIbSt6vectorIiSaIiEEESaIS4_EEC2EmRKS5_.exit.i movq %rbx, %rcx shlq $5, %rcx addq %rax, %rcx movq %rax, 16(%rsp) movq %rax, 24(%rsp) movq %rcx, 32(%rsp) testl %ebx, %ebx je .LBB0_12 # %bb.10: # %.lr.ph.i.i.i.i.i.preheader xorps %xmm0, %xmm0 .p2align 4, 0x90 .LBB0_11: # %.lr.ph.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movb $0, (%rax) movups %xmm0, 8(%rax) movq $0, 24(%rax) addq $32, %rax decq %rbx jne .LBB0_11 .LBB0_12: # %_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EEC2EmRKS4_.exit movq %rax, 24(%rsp) movl 8(%rsp), %eax testl %eax, %eax jle .LBB0_35 # %bb.13: # %.lr.ph110 xorl %r12d, %r12d leaq 96(%rsp), %rbx leaq 48(%rsp), %r15 jmp .LBB0_15 .p2align 4, 0x90 .LBB0_14: # %_ZNSt6vectorIiSaIiEED2Ev.exit # in Loop: Header=BB0_15 Depth=1 incq %r12 movslq 8(%rsp), %rax cmpq %rax, %r12 jge .LBB0_35 .LBB0_15: # =>This Loop Header: Depth=1 # Child Loop BB0_28 Depth 2 movq %r12, %r13 shlq $5, %r13 movq 16(%rsp), %rsi addq %r13, %rsi .Ltmp10: movq %rbx, %rdi callq _ZNSi10_M_extractIbEERSiRT_ .Ltmp11: # %bb.16: # %_ZNSirsERb.exit # in Loop: Header=BB0_15 Depth=1 .Ltmp13: movq %rbx, %rdi leaq 12(%rsp), %rsi callq _ZNSirsERi .Ltmp14: # %bb.17: # in Loop: Header=BB0_15 Depth=1 movslq 12(%rsp), %rbp testq %rbp, %rbp js .LBB0_73 # %bb.18: # %_ZNSt6vectorIiSaIiEE17_S_check_init_lenEmRKS0_.exit.i # in Loop: Header=BB0_15 Depth=1 xorps %xmm0, %xmm0 movaps %xmm0, 48(%rsp) movq $0, 64(%rsp) testl %ebp, %ebp je .LBB0_20 # %bb.19: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i # in Loop: Header=BB0_15 Depth=1 leaq (,%rbp,4), %rdi .Ltmp16: callq _Znwm .Ltmp17: jmp .LBB0_21 .p2align 4, 0x90 .LBB0_20: # in Loop: Header=BB0_15 Depth=1 xorl %eax, %eax .LBB0_21: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i # in Loop: Header=BB0_15 Depth=1 movq %rax, 48(%rsp) movq %rax, 56(%rsp) leaq (%rax,%rbp,4), %r14 movq %r14, 64(%rsp) testl %ebp, %ebp je .LBB0_24 # %bb.22: # in Loop: Header=BB0_15 Depth=1 movl $0, (%rax) addq $4, %rax cmpl $1, %ebp jne .LBB0_25 .LBB0_24: # in Loop: Header=BB0_15 Depth=1 movq %rax, %r14 jmp .LBB0_26 .p2align 4, 0x90 .LBB0_25: # %_ZSt6fill_nIPimiET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i # in Loop: Header=BB0_15 Depth=1 leaq -4(,%rbp,4), %rdx movq %rax, %rdi xorl %esi, %esi callq memset@PLT .LBB0_26: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit # in Loop: Header=BB0_15 Depth=1 movq %r14, 56(%rsp) cmpl $0, 12(%rsp) jle .LBB0_30 # %bb.27: # %.lr.ph.preheader # in Loop: Header=BB0_15 Depth=1 xorl %ebp, %ebp xorl %r14d, %r14d .p2align 4, 0x90 .LBB0_28: # %.lr.ph # Parent Loop BB0_15 Depth=1 # => This Inner Loop Header: Depth=2 movq 48(%rsp), %rsi addq %rbp, %rsi .Ltmp19: movq %rbx, %rdi callq _ZNSirsERi .Ltmp20: # %bb.29: # in Loop: Header=BB0_28 Depth=2 incq %r14 movslq 12(%rsp), %rax addq $4, %rbp cmpq %rax, %r14 jl .LBB0_28 .LBB0_30: # %._crit_edge # in Loop: Header=BB0_15 Depth=1 movq 16(%rsp), %rax leaq (%rax,%r13), %rdi addq $8, %rdi .Ltmp22: movq %r15, %rsi callq _ZNSt6vectorIiSaIiEEaSERKS1_ .Ltmp23: # %bb.31: # in Loop: Header=BB0_15 Depth=1 movq 48(%rsp), %rdi cmpq %rdi, 56(%rsp) je .LBB0_33 # %bb.32: # in Loop: Header=BB0_15 Depth=1 movq %rdi, 56(%rsp) .LBB0_33: # %_ZNSt6vectorIiSaIiEE5clearEv.exit # in Loop: Header=BB0_15 Depth=1 testq %rdi, %rdi je .LBB0_14 # %bb.34: # in Loop: Header=BB0_15 Depth=1 callq _ZdlPv jmp .LBB0_14 .LBB0_35: # %._crit_edge111 xorl %edx, %edx testl $-2147483641, %eax # imm = 0x80000007 setg %dl leal 7(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx sarl $3, %ecx addl %ecx, %edx movl %edx, 84(%rsp) # 4-byte Spill movslq %edx, %r14 movq %r14, %rdi callq malloc movq %rax, %rbx movq %rax, %rdi xorl %esi, %esi movq %r14, %rdx callq memset@PLT cmpl $0, 8(%rsp) jle .LBB0_57 # %bb.36: # %.lr.ph122.preheader xorl %r13d, %r13d jmp .LBB0_38 .p2align 4, 0x90 .LBB0_37: # %_ZNSt6vectorIiSaIiEED2Ev.exit82 # in Loop: Header=BB0_38 Depth=1 incq %r13 movslq 8(%rsp), %rax cmpq %rax, %r13 jge .LBB0_57 .LBB0_38: # %.lr.ph122 # =>This Loop Header: Depth=1 # Child Loop BB0_49 Depth 2 # Child Loop BB0_52 Depth 3 movq 16(%rsp), %r15 movq %r13, %r12 shlq $5, %r12 movzbl (%r15,%r12), %ebp movq 16(%r15,%r12), %rdi subq 8(%r15,%r12), %rdi movq %r13, 88(%rsp) # 8-byte Spill je .LBB0_42 # %bb.39: # in Loop: Header=BB0_38 Depth=1 movq %rdi, %rax sarq $2, %rax movq %rax, %rcx shrq $61, %rcx jne .LBB0_68 # %bb.40: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i76 # in Loop: Header=BB0_38 Depth=1 .Ltmp25: callq _Znwm .Ltmp26: # %bb.41: # in Loop: Header=BB0_38 Depth=1 movq %rax, %r14 jmp .LBB0_43 .p2align 4, 0x90 .LBB0_42: # in Loop: Header=BB0_38 Depth=1 xorl %r14d, %r14d .LBB0_43: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i77 # in Loop: Header=BB0_38 Depth=1 leaq (%r15,%r12), %rax addq $8, %rax movq (%rax), %r12 movq 8(%rax), %r13 movq %r13, %r15 subq %r12, %r15 cmpq $5, %r15 jl .LBB0_55 # %bb.44: # in Loop: Header=BB0_38 Depth=1 movq %r14, %rdi movq %r12, %rsi movq %r15, %rdx callq memmove@PLT .LBB0_45: # %_ZNSt6vectorIiSaIiEEC2ERKS1_.exit # in Loop: Header=BB0_38 Depth=1 cmpq %r12, %r13 movq 88(%rsp), %r13 # 8-byte Reload je .LBB0_53 # %bb.46: # %.lr.ph118.preheader # in Loop: Header=BB0_38 Depth=1 sarq $2, %r15 cmpq $1, %r15 adcq $0, %r15 xorl %eax, %eax xorl %edx, %edx jmp .LBB0_49 .p2align 4, 0x90 .LBB0_47: # in Loop: Header=BB0_49 Depth=2 xorl %ebp, %ebp .LBB0_48: # %.loopexit # in Loop: Header=BB0_49 Depth=2 addl (%r14,%rax,4), %edx incq %rax cmpq %r15, %rax je .LBB0_53 .LBB0_49: # %.lr.ph118 # Parent Loop BB0_38 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_52 Depth 3 testb $1, %bpl movb $1, %bpl je .LBB0_48 # %bb.50: # %.preheader91 # in Loop: Header=BB0_49 Depth=2 movl (%r14,%rax,4), %esi testl %esi, %esi jle .LBB0_47 # %bb.51: # %.lr.ph113.preheader # in Loop: Header=BB0_49 Depth=2 addl %edx, %esi movl %edx, %edi .p2align 4, 0x90 .LBB0_52: # %.lr.ph113 # Parent Loop BB0_38 Depth=1 # Parent Loop BB0_49 Depth=2 # => This Inner Loop Header: Depth=3 movl %edi, %ecx andb $7, %cl movl $128, %r8d shrl %cl, %r8d leal 7(%rdi), %ecx testl %edi, %edi cmovnsl %edi, %ecx sarl $3, %ecx movslq %ecx, %rcx orb %r8b, (%rbx,%rcx) incl %edi cmpl %esi, %edi jl .LBB0_52 jmp .LBB0_47 .p2align 4, 0x90 .LBB0_53: # %._crit_edge119 # in Loop: Header=BB0_38 Depth=1 testq %r14, %r14 je .LBB0_37 # %bb.54: # in Loop: Header=BB0_38 Depth=1 movq %r14, %rdi callq _ZdlPv jmp .LBB0_37 .LBB0_55: # in Loop: Header=BB0_38 Depth=1 cmpq $4, %r15 jne .LBB0_45 # %bb.56: # in Loop: Header=BB0_38 Depth=1 movl (%r12), %eax movl %eax, (%r14) jmp .LBB0_45 .LBB0_57: # %.preheader movl 84(%rsp), %eax # 4-byte Reload testl %eax, %eax jle .LBB0_60 # %bb.58: # %.lr.ph124.preheader movl %eax, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_59: # %.lr.ph124 # =>This Inner Loop Header: Depth=1 movzbl (%rbx,%r15), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB0_59 .LBB0_60: # %._crit_edge125 movq 16(%rsp), %rbx movq 24(%rsp), %r14 jmp .LBB0_62 .p2align 4, 0x90 .LBB0_61: # %_ZSt8_DestroyISt4pairIbSt6vectorIiSaIiEEEEvPT_.exit.i.i.i.i # in Loop: Header=BB0_62 Depth=1 addq $32, %rbx .LBB0_62: # %._crit_edge125 # =>This Inner Loop Header: Depth=1 cmpq %r14, %rbx je .LBB0_65 # %bb.63: # %.lr.ph.i.i.i.i # in Loop: Header=BB0_62 Depth=1 movq 8(%rbx), %rdi testq %rdi, %rdi je .LBB0_61 # %bb.64: # in Loop: Header=BB0_62 Depth=1 callq _ZdlPv jmp .LBB0_61 .LBB0_65: # %_ZSt8_DestroyIPSt4pairIbSt6vectorIiSaIiEEES4_EvT_S6_RSaIT0_E.exit.i movq 16(%rsp), %rdi testq %rdi, %rdi je .LBB0_67 # %bb.66: callq _ZdlPv .LBB0_67: # %_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev.exit leaq 96(%rsp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq 352(%rsp), %rdi callq _ZNSt8ios_baseD2Ev xorl %eax, %eax addq $616, %rsp # imm = 0x268 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB0_68: .cfi_def_cfa_offset 672 shrq $62, %rax je .LBB0_71 # %bb.69: # %.noexc.i.i .Ltmp30: callq _ZSt28__throw_bad_array_new_lengthv .Ltmp31: # %bb.70: # %.noexc78 .LBB0_71: # %.noexc4.i.i .Ltmp28: callq _ZSt17__throw_bad_allocv .Ltmp29: # %bb.72: # %.noexc79 .LBB0_73: .Ltmp33: movl $.L.str.2, %edi callq _ZSt20__throw_length_errorPKc .Ltmp34: # %bb.74: # %.noexc71 .LBB0_75: .Ltmp36: movl $.L.str.2, %edi callq _ZSt20__throw_length_errorPKc .Ltmp37: # %bb.76: # %.noexc67 .LBB0_77: .Ltmp7: movq %rax, %rbx jmp .LBB0_92 .LBB0_78: .Ltmp38: movq %rax, %rbx jmp .LBB0_92 .LBB0_79: .Ltmp4: movq %rax, %rbx jmp .LBB0_92 .LBB0_80: # %.loopexit92 .Ltmp27: jmp .LBB0_90 .LBB0_81: # %.loopexit93 .Ltmp18: jmp .LBB0_90 .LBB0_82: .Ltmp24: jmp .LBB0_87 .LBB0_83: .Ltmp12: jmp .LBB0_90 .LBB0_84: .Ltmp15: jmp .LBB0_90 .LBB0_85: # %.loopexit.split-lp94 .Ltmp35: jmp .LBB0_90 .LBB0_86: .Ltmp21: .LBB0_87: movq %rax, %rbx movq 48(%rsp), %rdi testq %rdi, %rdi je .LBB0_91 # %bb.88: callq _ZdlPv jmp .LBB0_91 .LBB0_89: # %.loopexit.split-lp .Ltmp32: .LBB0_90: movq %rax, %rbx .LBB0_91: leaq 16(%rsp), %rdi callq _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .LBB0_92: leaq 96(%rsp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq 352(%rsp), %rdi callq _ZNSt8ios_baseD2Ev movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table0: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3 .uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4 .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6 .uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7 .byte 0 # On action: cleanup .uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9 .uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38 .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11 .uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12 .byte 0 # On action: cleanup .uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14 .uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15 .byte 0 # On action: cleanup .uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp19-.Ltmp17 # Call between .Ltmp17 and .Ltmp19 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20 .uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21 .byte 0 # On action: cleanup .uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23 .uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24 .byte 0 # On action: cleanup .uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp25-.Ltmp23 # Call between .Ltmp23 and .Ltmp25 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26 .uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27 .byte 0 # On action: cleanup .uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp30-.Ltmp26 # Call between .Ltmp26 and .Ltmp30 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp29-.Ltmp30 # Call between .Ltmp30 and .Ltmp29 .uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32 .byte 0 # On action: cleanup .uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34 .uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35 .byte 0 # On action: cleanup .uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37 .uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38 .byte 0 # On action: cleanup .uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Lfunc_end0-.Ltmp37 # Call between .Ltmp37 and .Lfunc_end0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .section .text._ZNSt6vectorIiSaIiEEaSERKS1_,"axG",@progbits,_ZNSt6vectorIiSaIiEEaSERKS1_,comdat .weak _ZNSt6vectorIiSaIiEEaSERKS1_ # -- Begin function _ZNSt6vectorIiSaIiEEaSERKS1_ .p2align 4, 0x90 .type _ZNSt6vectorIiSaIiEEaSERKS1_,@function _ZNSt6vectorIiSaIiEEaSERKS1_: # @_ZNSt6vectorIiSaIiEEaSERKS1_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx cmpq %rdi, %rsi je .LBB1_17 # %bb.1: movq (%rsi), %r12 movq 8(%rsi), %r14 subq %r12, %r14 movq (%rbx), %r15 movq 16(%rbx), %rax subq %r15, %rax cmpq %rax, %r14 jbe .LBB1_8 # %bb.2: movq %r14, %rax sarq $2, %rax movq %rax, %rcx shrq $61, %rcx jne .LBB1_18 # %bb.3: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i movq %r14, %rdi callq _Znwm movq %rax, %r13 cmpq $5, %r14 jl .LBB1_20 # %bb.4: movq %r13, %rdi movq %r12, %rsi movq %r14, %rdx callq memcpy@PLT .LBB1_5: # %_ZNSt6vectorIiSaIiEE20_M_allocate_and_copyIN9__gnu_cxx17__normal_iteratorIPKiS1_EEEEPimT_S9_.exit testq %r15, %r15 je .LBB1_7 # %bb.6: movq %r15, %rdi callq _ZdlPv .LBB1_7: # %_ZNSt12_Vector_baseIiSaIiEE13_M_deallocateEPim.exit movq %r13, (%rbx) addq %r14, %r13 movq %r13, 16(%rbx) jmp .LBB1_16 .LBB1_8: movq 8(%rbx), %rdx subq %r15, %rdx cmpq %r14, %rdx jae .LBB1_13 # %bb.9: movq %rsi, %r13 cmpq $5, %rdx jl .LBB1_22 # %bb.10: movq %r15, %rdi movq %r12, %rsi callq memmove@PLT .LBB1_11: # %_ZSt4copyIPiS0_ET0_T_S2_S1_.exit movq 8(%rbx), %rdi movq %rdi, %rsi subq (%rbx), %rsi addq (%r13), %rsi movq 8(%r13), %rdx subq %rsi, %rdx cmpq $5, %rdx jge .LBB1_15 # %bb.24: cmpq $4, %rdx jne .LBB1_16 # %bb.25: movl (%rsi), %eax movl %eax, (%rdi) jmp .LBB1_16 .LBB1_13: cmpq $5, %r14 jl .LBB1_26 # %bb.14: movq %r15, %rdi movq %r12, %rsi movq %r14, %rdx .LBB1_15: # %_ZSt4copyIN9__gnu_cxx17__normal_iteratorIPKiSt6vectorIiSaIiEEEENS1_IPiS6_EEET0_T_SB_SA_.exit callq memmove@PLT .LBB1_16: # %_ZSt4copyIN9__gnu_cxx17__normal_iteratorIPKiSt6vectorIiSaIiEEEENS1_IPiS6_EEET0_T_SB_SA_.exit addq (%rbx), %r14 movq %r14, 8(%rbx) .LBB1_17: movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_18: .cfi_def_cfa_offset 48 shrq $62, %rax je .LBB1_28 # %bb.19: callq _ZSt28__throw_bad_array_new_lengthv .LBB1_20: cmpq $4, %r14 jne .LBB1_5 # %bb.21: movl (%r12), %eax movl %eax, (%r13) jmp .LBB1_5 .LBB1_22: cmpq $4, %rdx jne .LBB1_11 # %bb.23: movl (%r12), %eax movl %eax, (%r15) jmp .LBB1_11 .LBB1_26: cmpq $4, %r14 jne .LBB1_16 # %bb.27: movl (%r12), %eax movl %eax, (%r15) jmp .LBB1_16 .LBB1_28: callq _ZSt17__throw_bad_allocv .Lfunc_end1: .size _ZNSt6vectorIiSaIiEEaSERKS1_, .Lfunc_end1-_ZNSt6vectorIiSaIiEEaSERKS1_ .cfi_endproc # -- End function .section .text._ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,"axG",@progbits,_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,comdat .weak _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev # -- Begin function _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .p2align 4, 0x90 .type _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,@function _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev: # @_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movq (%rdi), %r14 movq 8(%rdi), %r15 jmp .LBB2_1 .p2align 4, 0x90 .LBB2_4: # %_ZSt8_DestroyISt4pairIbSt6vectorIiSaIiEEEEvPT_.exit.i.i.i # in Loop: Header=BB2_1 Depth=1 addq $32, %r14 .LBB2_1: # =>This Inner Loop Header: Depth=1 cmpq %r15, %r14 je .LBB2_5 # %bb.2: # %.lr.ph.i.i.i # in Loop: Header=BB2_1 Depth=1 movq 8(%r14), %rdi testq %rdi, %rdi je .LBB2_4 # %bb.3: # in Loop: Header=BB2_1 Depth=1 callq _ZdlPv jmp .LBB2_4 .LBB2_5: # %_ZSt8_DestroyIPSt4pairIbSt6vectorIiSaIiEEES4_EvT_S6_RSaIT0_E.exit movq (%rbx), %rdi testq %rdi, %rdi je .LBB2_6 # %bb.7: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 jmp _ZdlPv # TAILCALL .LBB2_6: # %_ZNSt12_Vector_baseISt4pairIbSt6vectorIiSaIiEEESaIS4_EED2Ev.exit .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev, .Lfunc_end2-_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "enc_mat" .size .L.str, 8 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%d\n" .size .L.str.1, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "cannot create std::vector larger than max_size()" .size .L.str.2, 49 .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __gxx_personality_v0 .addrsig_sym _Unwind_Resume .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000b5fc0_00000000-6_gpufold.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4170: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4170: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4193: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4193: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,"axG",@progbits,_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED5Ev,comdat .align 2 .weak _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .type _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev, @function _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev: .LFB4527: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %r12 movq 8(%rdi), %rbp movq (%rdi), %rbx cmpq %rbx, %rbp jne .L8 .L6: movq (%r12), %rdi testq %rdi, %rdi je .L5 movq 16(%r12), %rsi subq %rdi, %rsi call _ZdlPvm@PLT .L5: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state addq $32, %rbx cmpq %rbx, %rbp je .L6 .L8: movq 8(%rbx), %rdi testq %rdi, %rdi je .L7 movq 24(%rbx), %rsi subq %rdi, %rsi call _ZdlPvm@PLT jmp .L7 .cfi_endproc .LFE4527: .size _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev, .-_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .weak _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev .set _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev,_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .section .text._ZNSt6vectorIiSaIiEEaSERKS1_,"axG",@progbits,_ZNSt6vectorIiSaIiEEaSERKS1_,comdat .align 2 .weak _ZNSt6vectorIiSaIiEEaSERKS1_ .type _ZNSt6vectorIiSaIiEEaSERKS1_, @function _ZNSt6vectorIiSaIiEEaSERKS1_: .LFB4544: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx cmpq %rdi, %rsi je .L13 movq %rsi, %r12 movq (%rsi), %r13 movq 8(%rsi), %rbp subq %r13, %rbp movq (%rdi), %rdi movq 16(%rbx), %rax subq %rdi, %rax cmpq %rbp, %rax jb .L26 movq 8(%rbx), %rdx subq %rdi, %rdx cmpq %rbp, %rdx jb .L20 cmpq $4, %rbp jle .L21 movq %rbp, %rdx movq %r13, %rsi call memmove@PLT jmp .L19 .L26: movabsq $9223372036854775804, %rax cmpq %rbp, %rax jb .L27 movq %rbp, %rdi call _Znwm@PLT movq %rax, %r12 cmpq $4, %rbp jle .L16 movq %rbp, %rdx movq %r13, %rsi movq %rax, %rdi call memmove@PLT .L17: movq (%rbx), %rdi testq %rdi, %rdi je .L18 movq 16(%rbx), %rsi subq %rdi, %rsi call _ZdlPvm@PLT .L18: movq %r12, (%rbx) addq %rbp, %r12 movq %r12, 16(%rbx) .L19: addq (%rbx), %rbp movq %rbp, 8(%rbx) .L13: movq %rbx, %rax addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L27: .cfi_restore_state call _ZSt28__throw_bad_array_new_lengthv@PLT .L16: movl 0(%r13), %eax movl %eax, (%r12) jmp .L17 .L21: jne .L19 movl 0(%r13), %eax movl %eax, (%rdi) jmp .L19 .L20: cmpq $4, %rdx jle .L22 movq %r13, %rsi call memmove@PLT .L23: movq 8(%rbx), %rdi movq %rdi, %rsi subq (%rbx), %rsi addq (%r12), %rsi movq 8(%r12), %rdx subq %rsi, %rdx cmpq $4, %rdx jle .L24 call memmove@PLT jmp .L19 .L22: jne .L23 movl 0(%r13), %eax movl %eax, (%rdi) jmp .L23 .L24: jne .L19 movl (%rsi), %eax movl %eax, (%rdi) jmp .L19 .cfi_endproc .LFE4544: .size _ZNSt6vectorIiSaIiEEaSERKS1_, .-_ZNSt6vectorIiSaIiEEaSERKS1_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "enc_mat" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "cannot create std::vector larger than max_size()" .section .rodata.str1.1 .LC2: .string "%d\n" .text .globl main .type main, @function main: .LFB4163: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4163 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $648, %rsp .cfi_def_cfa_offset 704 movq %fs:40, %rax movq %rax, 632(%rsp) xorl %eax, %eax leaq 112(%rsp), %rbx movq %rbx, %rdi .LEHB0: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT .LEHE0: movl $8, %edx leaq .LC0(%rip), %rsi movq %rbx, %rdi .LEHB1: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT leaq 40(%rsp), %rsi movq %rbx, %rdi call _ZNSirsERi@PLT movslq 40(%rsp), %rdx movq %rdx, %rax shrq $58, %rax jne .L86 movq $0, 56(%rsp) movq $0, 64(%rsp) testq %rdx, %rdx je .L31 movq %rdx, %rbx salq $5, %rbx movq %rbx, %rdi call _Znwm@PLT jmp .L87 .L86: movq 632(%rsp), %rax subq %fs:40, %rax jne .L88 leaq .LC1(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE1: .L73: endbr64 movq %rax, %rbx jmp .L64 .L88: call __stack_chk_fail@PLT .L87: movq %rax, 8(%rsp) movq %rax, 48(%rsp) leaq (%rax,%rbx), %rdx movq %rdx, 64(%rsp) .L32: movb $0, (%rax) movq $0, 8(%rax) movq $0, 16(%rax) movq $0, 24(%rax) addq $32, %rax cmpq %rdx, %rax jne .L32 .L66: movq %rdx, 56(%rsp) movl 40(%rsp), %ecx testl %ecx, %ecx jle .L33 movq 8(%rsp), %r13 movl $0, %r14d jmp .L42 .L94: leaq 44(%rsp), %rsi leaq 112(%rsp), %rdi .LEHB2: call _ZNSirsERi@PLT movslq 44(%rsp), %rbx movabsq $2305843009213693951, %rax cmpq %rbx, %rax jb .L89 movq $0, 88(%rsp) movq $0, 96(%rsp) testq %rbx, %rbx je .L36 leaq 0(,%rbx,4), %r15 movq %r15, %rdi call _Znwm@PLT jmp .L90 .L89: movq 632(%rsp), %rax subq %fs:40, %rax jne .L91 leaq .LC1(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE2: .L91: call __stack_chk_fail@PLT .L90: movq %rax, %rbp movq %rax, 80(%rsp) leaq (%rax,%r15), %rdx movq %rdx, 96(%rsp) movl $0, (%rax) leaq 4(%rax), %rax cmpq $1, %rbx je .L69 cmpq %rax, %rdx je .L70 .L38: movl $0, (%rax) addq $4, %rax cmpq %rax, %rdx jne .L38 jmp .L37 .L69: movq %rax, %rdx jmp .L37 .L70: movq %rax, %rdx jmp .L37 .L92: addq $1, %rbx cmpl %ebx, 44(%rsp) jle .L39 .L40: leaq 0(%rbp,%rbx,4), %rsi movq %r12, %rdi .LEHB3: call _ZNSirsERi@PLT jmp .L92 .L39: leaq 80(%rsp), %rsi leaq 8(%r13), %rdi call _ZNSt6vectorIiSaIiEEaSERKS1_ .LEHE3: testq %rbp, %rbp je .L41 movq %r15, %rsi movq %rbp, %rdi call _ZdlPvm@PLT .L41: addl $1, %r14d movl 40(%rsp), %ecx addq $32, %r13 cmpl %r14d, %ecx jle .L93 .L42: leaq 112(%rsp), %rdi movq %r13, %rsi .LEHB4: call _ZNSi10_M_extractIbEERSiRT_@PLT jmp .L94 .L93: movl $8, %esi movl %ecx, %eax cltd idivl %esi testl %edx, %edx jle .L33 movl %ecx, %eax cltd idivl %esi addl $1, %eax movl %eax, 20(%rsp) movslq %eax, %r15 movq %r15, 24(%rsp) movq %r15, %rdi call malloc@PLT movq %rax, %rbx movq %r15, %rcx movq %r15, %rdx movl $0, %esi movq %rax, %rdi call __memset_chk@PLT cmpl $0, 40(%rsp) jle .L44 .L43: movq 8(%rsp), %r14 movl $0, %r15d jmp .L58 .L33: movl $8, %esi movl %ecx, %eax cltd idivl %esi movl %eax, 20(%rsp) movslq %eax, %r15 movq %r15, 24(%rsp) movq %r15, %rdi call malloc@PLT movq %rax, %rbx movq %r15, %rcx movq %r15, %rdx movl $0, %esi movq %rax, %rdi call __memset_chk@PLT cmpl $0, 40(%rsp) jg .L43 .L45: cmpl $0, 20(%rsp) jle .L59 .L44: movq %rbx, %rbp movq 24(%rsp), %rax addq %rax, %rbx leaq .LC2(%rip), %r12 jmp .L60 .L98: movq 632(%rsp), %rax subq %fs:40, %rax jne .L95 call _ZSt28__throw_bad_array_new_lengthv@PLT .L75: endbr64 movq %rax, %rbx jmp .L63 .L95: call __stack_chk_fail@PLT .L99: movq %rax, %r13 .L46: movq 8(%r12), %rsi movq 16(%r12), %r12 subq %rsi, %r12 cmpq $4, %r12 jle .L49 movq %r12, %rdx movq %r13, %rdi call memmove@PLT .L50: sarq $2, %r12 .L67: movl $0, %esi movl $0, %edx movl $128, %r8d movl $0, %r9d jmp .L56 .L71: movl $0, %r13d jmp .L46 .L49: je .L96 testq %r12, %r12 jne .L97 .L52: testq %r13, %r13 je .L57 movq 8(%rsp), %rsi movq %r13, %rdi call _ZdlPvm@PLT .L57: addl $1, %r15d addq $32, %r14 cmpl %r15d, 40(%rsp) jle .L45 .L58: movq %r14, %r12 movzbl (%r14), %ebp movq 16(%r14), %rax subq 8(%r14), %rax movq %rax, 8(%rsp) je .L71 movabsq $9223372036854775804, %rdi cmpq %rax, %rdi jb .L98 movq 8(%rsp), %rdi call _Znwm@PLT jmp .L99 .L96: movl (%rsi), %eax movl %eax, 0(%r13) jmp .L50 .L97: sarq $2, %r12 jmp .L67 .L53: addl 0(%r13,%rsi,4), %edx movl $1, %ebp .L54: addq $1, %rsi cmpq %r12, %rsi jnb .L52 .L56: testb %bpl, %bpl je .L53 movl %edx, %edi addl 0(%r13,%rsi,4), %edi cmpl %edi, %edx jge .L72 .L55: leal 7(%rdx), %eax testl %edx, %edx cmovns %edx, %eax sarl $3, %eax cltq movl %edx, %ecx andl $7, %ecx movl %r8d, %r10d sarl %cl, %r10d orb %r10b, (%rbx,%rax) addl $1, %edx cmpl %edi, %edx jne .L55 movl %edi, %edx movl %r9d, %ebp jmp .L54 .L72: movl %edi, %edx movl $0, %ebp jmp .L54 .L100: addq $1, %rbp cmpq %rbp, %rbx je .L59 .L60: movzbl 0(%rbp), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .LEHE4: jmp .L100 .L59: leaq 48(%rsp), %rdi call _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev leaq 112(%rsp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT movq 632(%rsp), %rax subq %fs:40, %rax jne .L101 movl $0, %eax addq $648, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L74: .cfi_restore_state endbr64 movq %rax, %rbx testq %rbp, %rbp je .L63 movq %r15, %rsi movq %rbp, %rdi call _ZdlPvm@PLT .L63: leaq 48(%rsp), %rdi call _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED1Ev .L64: leaq 112(%rsp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT movq 632(%rsp), %rax subq %fs:40, %rax je .L65 call __stack_chk_fail@PLT .L65: movq %rbx, %rdi .LEHB5: call _Unwind_Resume@PLT .LEHE5: .L36: movq $0, 80(%rsp) movq $0, 96(%rsp) movq %rbx, %r15 movl $0, %ebp movl $0, %edx .L37: movq %rdx, 88(%rsp) cmpl $0, 44(%rsp) jle .L39 movl $0, %ebx leaq 112(%rsp), %r12 jmp .L40 .L31: movq $0, 48(%rsp) movq $0, 64(%rsp) movq $0, 8(%rsp) movl $0, %edx jmp .L66 .L101: call __stack_chk_fail@PLT .cfi_endproc .LFE4163: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA4163: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4163-.LLSDACSB4163 .LLSDACSB4163: .uleb128 .LEHB0-.LFB4163 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB4163 .uleb128 .LEHE1-.LEHB1 .uleb128 .L73-.LFB4163 .uleb128 0 .uleb128 .LEHB2-.LFB4163 .uleb128 .LEHE2-.LEHB2 .uleb128 .L75-.LFB4163 .uleb128 0 .uleb128 .LEHB3-.LFB4163 .uleb128 .LEHE3-.LEHB3 .uleb128 .L74-.LFB4163 .uleb128 0 .uleb128 .LEHB4-.LFB4163 .uleb128 .LEHE4-.LEHB4 .uleb128 .L75-.LFB4163 .uleb128 0 .uleb128 .LEHB5-.LFB4163 .uleb128 .LEHE5-.LEHB5 .uleb128 0 .uleb128 0 .LLSDACSE4163: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "gpufold.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI0_0: .zero 16 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $616, %rsp # imm = 0x268 .cfi_def_cfa_offset 672 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 96(%rsp), %rbx movq %rbx, %rdi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev leaq 112(%rsp), %rdi .Ltmp0: movl $.L.str, %esi movl $8, %edx callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode .Ltmp1: # %bb.1: # %.noexc movq 96(%rsp), %rcx addq -24(%rcx), %rbx xorl %esi, %esi testq %rax, %rax jne .LBB0_3 # %bb.2: movl 32(%rbx), %esi orl $4, %esi .LBB0_3: # %.invoke .Ltmp2: movq %rbx, %rdi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .Ltmp3: # %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit .Ltmp5: leaq 96(%rsp), %rdi leaq 8(%rsp), %rsi callq _ZNSirsERi .Ltmp6: # %bb.5: movslq 8(%rsp), %rbx testq %rbx, %rbx js .LBB0_75 # %bb.6: # %_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EE17_S_check_init_lenEmRKS4_.exit.i xorps %xmm0, %xmm0 movaps %xmm0, 16(%rsp) movq $0, 32(%rsp) testl %ebx, %ebx je .LBB0_8 # %bb.7: # %_ZNSt16allocator_traitsISaISt4pairIbSt6vectorIiSaIiEEEEE8allocateERS5_m.exit.i.i.i.i movq %rbx, %rdi shlq $5, %rdi .Ltmp8: callq _Znwm .Ltmp9: jmp .LBB0_9 .LBB0_8: xorl %eax, %eax .LBB0_9: # %_ZNSt12_Vector_baseISt4pairIbSt6vectorIiSaIiEEESaIS4_EEC2EmRKS5_.exit.i movq %rbx, %rcx shlq $5, %rcx addq %rax, %rcx movq %rax, 16(%rsp) movq %rax, 24(%rsp) movq %rcx, 32(%rsp) testl %ebx, %ebx je .LBB0_12 # %bb.10: # %.lr.ph.i.i.i.i.i.preheader xorps %xmm0, %xmm0 .p2align 4, 0x90 .LBB0_11: # %.lr.ph.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movb $0, (%rax) movups %xmm0, 8(%rax) movq $0, 24(%rax) addq $32, %rax decq %rbx jne .LBB0_11 .LBB0_12: # %_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EEC2EmRKS4_.exit movq %rax, 24(%rsp) movl 8(%rsp), %eax testl %eax, %eax jle .LBB0_35 # %bb.13: # %.lr.ph110 xorl %r12d, %r12d leaq 96(%rsp), %rbx leaq 48(%rsp), %r15 jmp .LBB0_15 .p2align 4, 0x90 .LBB0_14: # %_ZNSt6vectorIiSaIiEED2Ev.exit # in Loop: Header=BB0_15 Depth=1 incq %r12 movslq 8(%rsp), %rax cmpq %rax, %r12 jge .LBB0_35 .LBB0_15: # =>This Loop Header: Depth=1 # Child Loop BB0_28 Depth 2 movq %r12, %r13 shlq $5, %r13 movq 16(%rsp), %rsi addq %r13, %rsi .Ltmp10: movq %rbx, %rdi callq _ZNSi10_M_extractIbEERSiRT_ .Ltmp11: # %bb.16: # %_ZNSirsERb.exit # in Loop: Header=BB0_15 Depth=1 .Ltmp13: movq %rbx, %rdi leaq 12(%rsp), %rsi callq _ZNSirsERi .Ltmp14: # %bb.17: # in Loop: Header=BB0_15 Depth=1 movslq 12(%rsp), %rbp testq %rbp, %rbp js .LBB0_73 # %bb.18: # %_ZNSt6vectorIiSaIiEE17_S_check_init_lenEmRKS0_.exit.i # in Loop: Header=BB0_15 Depth=1 xorps %xmm0, %xmm0 movaps %xmm0, 48(%rsp) movq $0, 64(%rsp) testl %ebp, %ebp je .LBB0_20 # %bb.19: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i # in Loop: Header=BB0_15 Depth=1 leaq (,%rbp,4), %rdi .Ltmp16: callq _Znwm .Ltmp17: jmp .LBB0_21 .p2align 4, 0x90 .LBB0_20: # in Loop: Header=BB0_15 Depth=1 xorl %eax, %eax .LBB0_21: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i # in Loop: Header=BB0_15 Depth=1 movq %rax, 48(%rsp) movq %rax, 56(%rsp) leaq (%rax,%rbp,4), %r14 movq %r14, 64(%rsp) testl %ebp, %ebp je .LBB0_24 # %bb.22: # in Loop: Header=BB0_15 Depth=1 movl $0, (%rax) addq $4, %rax cmpl $1, %ebp jne .LBB0_25 .LBB0_24: # in Loop: Header=BB0_15 Depth=1 movq %rax, %r14 jmp .LBB0_26 .p2align 4, 0x90 .LBB0_25: # %_ZSt6fill_nIPimiET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i # in Loop: Header=BB0_15 Depth=1 leaq -4(,%rbp,4), %rdx movq %rax, %rdi xorl %esi, %esi callq memset@PLT .LBB0_26: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit # in Loop: Header=BB0_15 Depth=1 movq %r14, 56(%rsp) cmpl $0, 12(%rsp) jle .LBB0_30 # %bb.27: # %.lr.ph.preheader # in Loop: Header=BB0_15 Depth=1 xorl %ebp, %ebp xorl %r14d, %r14d .p2align 4, 0x90 .LBB0_28: # %.lr.ph # Parent Loop BB0_15 Depth=1 # => This Inner Loop Header: Depth=2 movq 48(%rsp), %rsi addq %rbp, %rsi .Ltmp19: movq %rbx, %rdi callq _ZNSirsERi .Ltmp20: # %bb.29: # in Loop: Header=BB0_28 Depth=2 incq %r14 movslq 12(%rsp), %rax addq $4, %rbp cmpq %rax, %r14 jl .LBB0_28 .LBB0_30: # %._crit_edge # in Loop: Header=BB0_15 Depth=1 movq 16(%rsp), %rax leaq (%rax,%r13), %rdi addq $8, %rdi .Ltmp22: movq %r15, %rsi callq _ZNSt6vectorIiSaIiEEaSERKS1_ .Ltmp23: # %bb.31: # in Loop: Header=BB0_15 Depth=1 movq 48(%rsp), %rdi cmpq %rdi, 56(%rsp) je .LBB0_33 # %bb.32: # in Loop: Header=BB0_15 Depth=1 movq %rdi, 56(%rsp) .LBB0_33: # %_ZNSt6vectorIiSaIiEE5clearEv.exit # in Loop: Header=BB0_15 Depth=1 testq %rdi, %rdi je .LBB0_14 # %bb.34: # in Loop: Header=BB0_15 Depth=1 callq _ZdlPv jmp .LBB0_14 .LBB0_35: # %._crit_edge111 xorl %edx, %edx testl $-2147483641, %eax # imm = 0x80000007 setg %dl leal 7(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx sarl $3, %ecx addl %ecx, %edx movl %edx, 84(%rsp) # 4-byte Spill movslq %edx, %r14 movq %r14, %rdi callq malloc movq %rax, %rbx movq %rax, %rdi xorl %esi, %esi movq %r14, %rdx callq memset@PLT cmpl $0, 8(%rsp) jle .LBB0_57 # %bb.36: # %.lr.ph122.preheader xorl %r13d, %r13d jmp .LBB0_38 .p2align 4, 0x90 .LBB0_37: # %_ZNSt6vectorIiSaIiEED2Ev.exit82 # in Loop: Header=BB0_38 Depth=1 incq %r13 movslq 8(%rsp), %rax cmpq %rax, %r13 jge .LBB0_57 .LBB0_38: # %.lr.ph122 # =>This Loop Header: Depth=1 # Child Loop BB0_49 Depth 2 # Child Loop BB0_52 Depth 3 movq 16(%rsp), %r15 movq %r13, %r12 shlq $5, %r12 movzbl (%r15,%r12), %ebp movq 16(%r15,%r12), %rdi subq 8(%r15,%r12), %rdi movq %r13, 88(%rsp) # 8-byte Spill je .LBB0_42 # %bb.39: # in Loop: Header=BB0_38 Depth=1 movq %rdi, %rax sarq $2, %rax movq %rax, %rcx shrq $61, %rcx jne .LBB0_68 # %bb.40: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i76 # in Loop: Header=BB0_38 Depth=1 .Ltmp25: callq _Znwm .Ltmp26: # %bb.41: # in Loop: Header=BB0_38 Depth=1 movq %rax, %r14 jmp .LBB0_43 .p2align 4, 0x90 .LBB0_42: # in Loop: Header=BB0_38 Depth=1 xorl %r14d, %r14d .LBB0_43: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i77 # in Loop: Header=BB0_38 Depth=1 leaq (%r15,%r12), %rax addq $8, %rax movq (%rax), %r12 movq 8(%rax), %r13 movq %r13, %r15 subq %r12, %r15 cmpq $5, %r15 jl .LBB0_55 # %bb.44: # in Loop: Header=BB0_38 Depth=1 movq %r14, %rdi movq %r12, %rsi movq %r15, %rdx callq memmove@PLT .LBB0_45: # %_ZNSt6vectorIiSaIiEEC2ERKS1_.exit # in Loop: Header=BB0_38 Depth=1 cmpq %r12, %r13 movq 88(%rsp), %r13 # 8-byte Reload je .LBB0_53 # %bb.46: # %.lr.ph118.preheader # in Loop: Header=BB0_38 Depth=1 sarq $2, %r15 cmpq $1, %r15 adcq $0, %r15 xorl %eax, %eax xorl %edx, %edx jmp .LBB0_49 .p2align 4, 0x90 .LBB0_47: # in Loop: Header=BB0_49 Depth=2 xorl %ebp, %ebp .LBB0_48: # %.loopexit # in Loop: Header=BB0_49 Depth=2 addl (%r14,%rax,4), %edx incq %rax cmpq %r15, %rax je .LBB0_53 .LBB0_49: # %.lr.ph118 # Parent Loop BB0_38 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_52 Depth 3 testb $1, %bpl movb $1, %bpl je .LBB0_48 # %bb.50: # %.preheader91 # in Loop: Header=BB0_49 Depth=2 movl (%r14,%rax,4), %esi testl %esi, %esi jle .LBB0_47 # %bb.51: # %.lr.ph113.preheader # in Loop: Header=BB0_49 Depth=2 addl %edx, %esi movl %edx, %edi .p2align 4, 0x90 .LBB0_52: # %.lr.ph113 # Parent Loop BB0_38 Depth=1 # Parent Loop BB0_49 Depth=2 # => This Inner Loop Header: Depth=3 movl %edi, %ecx andb $7, %cl movl $128, %r8d shrl %cl, %r8d leal 7(%rdi), %ecx testl %edi, %edi cmovnsl %edi, %ecx sarl $3, %ecx movslq %ecx, %rcx orb %r8b, (%rbx,%rcx) incl %edi cmpl %esi, %edi jl .LBB0_52 jmp .LBB0_47 .p2align 4, 0x90 .LBB0_53: # %._crit_edge119 # in Loop: Header=BB0_38 Depth=1 testq %r14, %r14 je .LBB0_37 # %bb.54: # in Loop: Header=BB0_38 Depth=1 movq %r14, %rdi callq _ZdlPv jmp .LBB0_37 .LBB0_55: # in Loop: Header=BB0_38 Depth=1 cmpq $4, %r15 jne .LBB0_45 # %bb.56: # in Loop: Header=BB0_38 Depth=1 movl (%r12), %eax movl %eax, (%r14) jmp .LBB0_45 .LBB0_57: # %.preheader movl 84(%rsp), %eax # 4-byte Reload testl %eax, %eax jle .LBB0_60 # %bb.58: # %.lr.ph124.preheader movl %eax, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_59: # %.lr.ph124 # =>This Inner Loop Header: Depth=1 movzbl (%rbx,%r15), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB0_59 .LBB0_60: # %._crit_edge125 movq 16(%rsp), %rbx movq 24(%rsp), %r14 jmp .LBB0_62 .p2align 4, 0x90 .LBB0_61: # %_ZSt8_DestroyISt4pairIbSt6vectorIiSaIiEEEEvPT_.exit.i.i.i.i # in Loop: Header=BB0_62 Depth=1 addq $32, %rbx .LBB0_62: # %._crit_edge125 # =>This Inner Loop Header: Depth=1 cmpq %r14, %rbx je .LBB0_65 # %bb.63: # %.lr.ph.i.i.i.i # in Loop: Header=BB0_62 Depth=1 movq 8(%rbx), %rdi testq %rdi, %rdi je .LBB0_61 # %bb.64: # in Loop: Header=BB0_62 Depth=1 callq _ZdlPv jmp .LBB0_61 .LBB0_65: # %_ZSt8_DestroyIPSt4pairIbSt6vectorIiSaIiEEES4_EvT_S6_RSaIT0_E.exit.i movq 16(%rsp), %rdi testq %rdi, %rdi je .LBB0_67 # %bb.66: callq _ZdlPv .LBB0_67: # %_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev.exit leaq 96(%rsp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq 352(%rsp), %rdi callq _ZNSt8ios_baseD2Ev xorl %eax, %eax addq $616, %rsp # imm = 0x268 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB0_68: .cfi_def_cfa_offset 672 shrq $62, %rax je .LBB0_71 # %bb.69: # %.noexc.i.i .Ltmp30: callq _ZSt28__throw_bad_array_new_lengthv .Ltmp31: # %bb.70: # %.noexc78 .LBB0_71: # %.noexc4.i.i .Ltmp28: callq _ZSt17__throw_bad_allocv .Ltmp29: # %bb.72: # %.noexc79 .LBB0_73: .Ltmp33: movl $.L.str.2, %edi callq _ZSt20__throw_length_errorPKc .Ltmp34: # %bb.74: # %.noexc71 .LBB0_75: .Ltmp36: movl $.L.str.2, %edi callq _ZSt20__throw_length_errorPKc .Ltmp37: # %bb.76: # %.noexc67 .LBB0_77: .Ltmp7: movq %rax, %rbx jmp .LBB0_92 .LBB0_78: .Ltmp38: movq %rax, %rbx jmp .LBB0_92 .LBB0_79: .Ltmp4: movq %rax, %rbx jmp .LBB0_92 .LBB0_80: # %.loopexit92 .Ltmp27: jmp .LBB0_90 .LBB0_81: # %.loopexit93 .Ltmp18: jmp .LBB0_90 .LBB0_82: .Ltmp24: jmp .LBB0_87 .LBB0_83: .Ltmp12: jmp .LBB0_90 .LBB0_84: .Ltmp15: jmp .LBB0_90 .LBB0_85: # %.loopexit.split-lp94 .Ltmp35: jmp .LBB0_90 .LBB0_86: .Ltmp21: .LBB0_87: movq %rax, %rbx movq 48(%rsp), %rdi testq %rdi, %rdi je .LBB0_91 # %bb.88: callq _ZdlPv jmp .LBB0_91 .LBB0_89: # %.loopexit.split-lp .Ltmp32: .LBB0_90: movq %rax, %rbx .LBB0_91: leaq 16(%rsp), %rdi callq _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .LBB0_92: leaq 96(%rsp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq 352(%rsp), %rdi callq _ZNSt8ios_baseD2Ev movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table0: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3 .uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4 .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6 .uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7 .byte 0 # On action: cleanup .uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9 .uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38 .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11 .uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12 .byte 0 # On action: cleanup .uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14 .uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15 .byte 0 # On action: cleanup .uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp19-.Ltmp17 # Call between .Ltmp17 and .Ltmp19 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20 .uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21 .byte 0 # On action: cleanup .uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23 .uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24 .byte 0 # On action: cleanup .uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp25-.Ltmp23 # Call between .Ltmp23 and .Ltmp25 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26 .uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27 .byte 0 # On action: cleanup .uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp30-.Ltmp26 # Call between .Ltmp26 and .Ltmp30 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp29-.Ltmp30 # Call between .Ltmp30 and .Ltmp29 .uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32 .byte 0 # On action: cleanup .uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34 .uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35 .byte 0 # On action: cleanup .uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37 .uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38 .byte 0 # On action: cleanup .uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Lfunc_end0-.Ltmp37 # Call between .Ltmp37 and .Lfunc_end0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .section .text._ZNSt6vectorIiSaIiEEaSERKS1_,"axG",@progbits,_ZNSt6vectorIiSaIiEEaSERKS1_,comdat .weak _ZNSt6vectorIiSaIiEEaSERKS1_ # -- Begin function _ZNSt6vectorIiSaIiEEaSERKS1_ .p2align 4, 0x90 .type _ZNSt6vectorIiSaIiEEaSERKS1_,@function _ZNSt6vectorIiSaIiEEaSERKS1_: # @_ZNSt6vectorIiSaIiEEaSERKS1_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx cmpq %rdi, %rsi je .LBB1_17 # %bb.1: movq (%rsi), %r12 movq 8(%rsi), %r14 subq %r12, %r14 movq (%rbx), %r15 movq 16(%rbx), %rax subq %r15, %rax cmpq %rax, %r14 jbe .LBB1_8 # %bb.2: movq %r14, %rax sarq $2, %rax movq %rax, %rcx shrq $61, %rcx jne .LBB1_18 # %bb.3: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i movq %r14, %rdi callq _Znwm movq %rax, %r13 cmpq $5, %r14 jl .LBB1_20 # %bb.4: movq %r13, %rdi movq %r12, %rsi movq %r14, %rdx callq memcpy@PLT .LBB1_5: # %_ZNSt6vectorIiSaIiEE20_M_allocate_and_copyIN9__gnu_cxx17__normal_iteratorIPKiS1_EEEEPimT_S9_.exit testq %r15, %r15 je .LBB1_7 # %bb.6: movq %r15, %rdi callq _ZdlPv .LBB1_7: # %_ZNSt12_Vector_baseIiSaIiEE13_M_deallocateEPim.exit movq %r13, (%rbx) addq %r14, %r13 movq %r13, 16(%rbx) jmp .LBB1_16 .LBB1_8: movq 8(%rbx), %rdx subq %r15, %rdx cmpq %r14, %rdx jae .LBB1_13 # %bb.9: movq %rsi, %r13 cmpq $5, %rdx jl .LBB1_22 # %bb.10: movq %r15, %rdi movq %r12, %rsi callq memmove@PLT .LBB1_11: # %_ZSt4copyIPiS0_ET0_T_S2_S1_.exit movq 8(%rbx), %rdi movq %rdi, %rsi subq (%rbx), %rsi addq (%r13), %rsi movq 8(%r13), %rdx subq %rsi, %rdx cmpq $5, %rdx jge .LBB1_15 # %bb.24: cmpq $4, %rdx jne .LBB1_16 # %bb.25: movl (%rsi), %eax movl %eax, (%rdi) jmp .LBB1_16 .LBB1_13: cmpq $5, %r14 jl .LBB1_26 # %bb.14: movq %r15, %rdi movq %r12, %rsi movq %r14, %rdx .LBB1_15: # %_ZSt4copyIN9__gnu_cxx17__normal_iteratorIPKiSt6vectorIiSaIiEEEENS1_IPiS6_EEET0_T_SB_SA_.exit callq memmove@PLT .LBB1_16: # %_ZSt4copyIN9__gnu_cxx17__normal_iteratorIPKiSt6vectorIiSaIiEEEENS1_IPiS6_EEET0_T_SB_SA_.exit addq (%rbx), %r14 movq %r14, 8(%rbx) .LBB1_17: movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_18: .cfi_def_cfa_offset 48 shrq $62, %rax je .LBB1_28 # %bb.19: callq _ZSt28__throw_bad_array_new_lengthv .LBB1_20: cmpq $4, %r14 jne .LBB1_5 # %bb.21: movl (%r12), %eax movl %eax, (%r13) jmp .LBB1_5 .LBB1_22: cmpq $4, %rdx jne .LBB1_11 # %bb.23: movl (%r12), %eax movl %eax, (%r15) jmp .LBB1_11 .LBB1_26: cmpq $4, %r14 jne .LBB1_16 # %bb.27: movl (%r12), %eax movl %eax, (%r15) jmp .LBB1_16 .LBB1_28: callq _ZSt17__throw_bad_allocv .Lfunc_end1: .size _ZNSt6vectorIiSaIiEEaSERKS1_, .Lfunc_end1-_ZNSt6vectorIiSaIiEEaSERKS1_ .cfi_endproc # -- End function .section .text._ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,"axG",@progbits,_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,comdat .weak _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev # -- Begin function _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .p2align 4, 0x90 .type _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev,@function _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev: # @_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movq (%rdi), %r14 movq 8(%rdi), %r15 jmp .LBB2_1 .p2align 4, 0x90 .LBB2_4: # %_ZSt8_DestroyISt4pairIbSt6vectorIiSaIiEEEEvPT_.exit.i.i.i # in Loop: Header=BB2_1 Depth=1 addq $32, %r14 .LBB2_1: # =>This Inner Loop Header: Depth=1 cmpq %r15, %r14 je .LBB2_5 # %bb.2: # %.lr.ph.i.i.i # in Loop: Header=BB2_1 Depth=1 movq 8(%r14), %rdi testq %rdi, %rdi je .LBB2_4 # %bb.3: # in Loop: Header=BB2_1 Depth=1 callq _ZdlPv jmp .LBB2_4 .LBB2_5: # %_ZSt8_DestroyIPSt4pairIbSt6vectorIiSaIiEEES4_EvT_S6_RSaIT0_E.exit movq (%rbx), %rdi testq %rdi, %rdi je .LBB2_6 # %bb.7: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 jmp _ZdlPv # TAILCALL .LBB2_6: # %_ZNSt12_Vector_baseISt4pairIbSt6vectorIiSaIiEEESaIS4_EED2Ev.exit .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev, .Lfunc_end2-_ZNSt6vectorISt4pairIbS_IiSaIiEEESaIS3_EED2Ev .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "enc_mat" .size .L.str, 8 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%d\n" .size .L.str.1, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "cannot create std::vector larger than max_size()" .size .L.str.2, 49 .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __gxx_personality_v0 .addrsig_sym _Unwind_Resume .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
/* ********************************************** * CS314 Principles of Programming Languages * * Spring 2020 * ********************************************** */ #include <stdio.h> #include <stdlib.h> __global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) { /*YOUR CODE HERE*/ int allThreads = blockDim.x * gridDim.x; int tid = blockIdx.x * blockDim.x + threadIdx.x; for(int i = tid; i < numEdges; i += allThreads){ if (src[i] != src[i+1]){ output[src[i]] = scanResult[i]; } } if(tid >= numEdges && allThreads !=0){ return; } }
code for sm_80 Function : _Z19collateSegments_gpuPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */ /* 0x001fca00078e0200 */ /*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0080*/ BSSY B0, 0x390 ; /* 0x0000030000007945 */ /* 0x000fe40003800000 */ /*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */ /* 0x000fc800078e02ff */ /*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */ /* 0x000e220000209000 */ /*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */ /* 0x000fe200078e0a00 */ /*00c0*/ ISETP.NE.U32.AND P2, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */ /* 0x040fe20003f45070 */ /*00d0*/ IMAD.IADD R2, R0, 0x1, R3 ; /* 0x0000000100027824 */ /* 0x000fca00078e0203 */ /*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */ /* 0x000fc800078e33ff */ /*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */ /* 0x000fe20007ffe000 */ /*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */ /* 0x001e240000001000 */ /*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */ /* 0x001fcc0007ffe0ff */ /*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */ /* 0x000064000021f000 */ /*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x001fe400078e00ff */ /*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */ /* 0x002fc800078e02ff */ /*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */ /* 0x000fcc00078e0004 */ /*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */ /* 0x000fc800078e00ff */ /*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */ /* 0x000fc800078e0a02 */ /*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */ /* 0x000fca00078e0207 */ /*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */ /* 0x000fda0003f06070 */ /*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */ /* 0x000fe40007ffe1ff */ /*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */ /* 0x000fe40007ffe0ff */ /*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */ /* 0x000fda0003f26070 */ /*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */ /* 0x000fe40007ffe0ff */ /*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */ /* 0x000fc800078e33ff */ /*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */ /* 0x040fe40007ffe0ff */ /*0200*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fe40003f06070 */ /*0210*/ LOP3.LUT P1, R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */ /* 0x000fda000782c0ff */ /*0220*/ @!P1 BRA 0x380 ; /* 0x0000015000009947 */ /* 0x000fea0003800000 */ /*0230*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */ /* 0x000fe400078e00ff */ /*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */ /* 0x000fe400078e0006 */ /*0250*/ IMAD.WIDE R4, R3, R10, c[0x0][0x160] ; /* 0x0000580003047625 */ /* 0x000fc800078e020a */ /*0260*/ IMAD.WIDE R6, R3, R10, c[0x0][0x168] ; /* 0x00005a0003067625 */ /* 0x000fe200078e020a */ /*0270*/ IADD3 R8, P1, R4, 0x4, RZ ; /* 0x0000000404087810 */ /* 0x000fca0007f3e0ff */ /*0280*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */ /* 0x000fc800008e0605 */ /*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */ /* 0x000fe200078e0008 */ /*02a0*/ MOV R11, R9 ; /* 0x00000009000b7202 */ /* 0x000fca0000000f00 */ /*02b0*/ LDG.E R5, [R10.64+-0x4] ; /* 0xfffffc040a057981 */ /* 0x000ea8000c1e1900 */ /*02c0*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */ /* 0x000ea4000c1e1900 */ /*02d0*/ ISETP.NE.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x004fda0003f25270 */ /*02e0*/ @P1 LDG.E R13, [R6.64] ; /* 0x00000004060d1981 */ /* 0x0000a2000c1e1900 */ /*02f0*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff041424 */ /* 0x000fe200078e00ff */ /*0300*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */ /* 0x000fe20007ffe0ff */ /*0310*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */ /* 0x000fc800078e020a */ /*0320*/ @P1 IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005041625 */ /* 0x000fc800078e0204 */ /*0330*/ IMAD.IADD R3, R0.reuse, 0x1, R3 ; /* 0x0000000100037824 */ /* 0x040fe400078e0203 */ /*0340*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */ /* 0x001fe200078e0206 */ /*0350*/ @P1 STG.E [R4.64], R13 ; /* 0x0000000d04001986 */ /* 0x0041e2000c101904 */ /*0360*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fda0003f25270 */ /*0370*/ @P1 BRA 0x290 ; /* 0xffffff1000001947 */ /* 0x001fea000383ffff */ /*0380*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0390*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*03a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fc800078e00ff */ /*03b0*/ IMAD.WIDE R8, R3, R2, c[0x0][0x160] ; /* 0x0000580003087625 */ /* 0x000fca00078e0202 */ /*03c0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */ /* 0x000ea8000c1e1900 */ /*03d0*/ LDG.E R4, [R8.64+0x4] ; /* 0x0000040408047981 */ /* 0x000ea4000c1e1900 */ /*03e0*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x004fe40003f05270 */ /*03f0*/ SHF.R.S32.HI R4, RZ, 0x1f, R3 ; /* 0x0000001fff047819 */ /* 0x000fd60000011403 */ /*0400*/ @P0 LEA R6, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003060a11 */ /* 0x000fc800078210ff */ /*0410*/ @P0 LEA.HI.X R7, R3, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b0003070a11 */ /* 0x000fca00008f1404 */ /*0420*/ @P0 LDG.E R15, [R6.64] ; /* 0x00000004060f0981 */ /* 0x000ea2000c1e1900 */ /*0430*/ @P0 IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005040625 */ /* 0x000fc800078e0202 */ /*0440*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */ /* 0x040fe200078e0208 */ /*0450*/ @P0 STG.E [R4.64], R15 ; /* 0x0000000f04000986 */ /* 0x0041e8000c101904 */ /*0460*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */ /* 0x000ea8000c1e1900 */ /*0470*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004040a0c7981 */ /* 0x000ea2000c1e1900 */ /*0480*/ IMAD.IADD R17, R0, 0x1, R3 ; /* 0x0000000100117824 */ /* 0x000fe200078e0203 */ /*0490*/ ISETP.NE.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720c */ /* 0x004fc80003f05270 */ /*04a0*/ SHF.R.S32.HI R12, RZ, 0x1f, R17 ; /* 0x0000001fff0c7819 */ /* 0x000fd20000011411 */ /*04b0*/ @P0 LEA R8, P1, R17, c[0x0][0x168], 0x2 ; /* 0x00005a0011080a11 */ /* 0x000fc800078210ff */ /*04c0*/ @P0 LEA.HI.X R9, R17, c[0x0][0x16c], R12, 0x2, P1 ; /* 0x00005b0011090a11 */ /* 0x000fca00008f140c */ /*04d0*/ @P0 LDG.E R3, [R8.64] ; /* 0x0000000408030981 */ /* 0x000ea2000c1e1900 */ /*04e0*/ @P0 IMAD.WIDE R6, R13, R2, c[0x0][0x170] ; /* 0x00005c000d060625 */ /* 0x000fc800078e0202 */ /*04f0*/ IMAD.WIDE R12, R0.reuse, 0x4, R10 ; /* 0x00000004000c7825 */ /* 0x040fe200078e020a */ /*0500*/ @P0 STG.E [R6.64], R3 ; /* 0x0000000306000986 */ /* 0x0043e8000c101904 */ /*0510*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */ /* 0x001ea8000c1e1900 */ /*0520*/ LDG.E R4, [R12.64+0x4] ; /* 0x000004040c047981 */ /* 0x000ea2000c1e1900 */ /*0530*/ IADD3 R17, R0, R17, RZ ; /* 0x0000001100117210 */ /* 0x000fc40007ffe0ff */ /*0540*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x004fe40003f05270 */ /*0550*/ SHF.R.S32.HI R4, RZ, 0x1f, R17 ; /* 0x0000001fff047819 */ /* 0x000fd60000011411 */ /*0560*/ @P0 LEA R10, P1, R17, c[0x0][0x168], 0x2 ; /* 0x00005a00110a0a11 */ /* 0x000fc800078210ff */ /*0570*/ @P0 LEA.HI.X R11, R17, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b00110b0a11 */ /* 0x000fcc00008f1404 */ /*0580*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b0981 */ /* 0x000ea2000c1e1900 */ /*0590*/ @P0 IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005040625 */ /* 0x000fc800078e0202 */ /*05a0*/ IMAD.WIDE R8, R0.reuse, 0x4, R12 ; /* 0x0000000400087825 */ /* 0x040fe200078e020c */ /*05b0*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */ /* 0x0041e8000c101904 */ /*05c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x002ea8000c1e1900 */ /*05d0*/ LDG.E R3, [R8.64+0x4] ; /* 0x0000040408037981 */ /* 0x000ea4000c1e1900 */ /*05e0*/ ISETP.NE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */ /* 0x004fe20003f05270 */ /*05f0*/ IMAD.IADD R3, R0, 0x1, R17 ; /* 0x0000000100037824 */ /* 0x000fca00078e0211 */ /*0600*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */ /* 0x000fce0000011403 */ /*0610*/ @P0 LEA R12, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a00030c0a11 */ /* 0x000fc800078210ff */ /*0620*/ @P0 LEA.HI.X R13, R3, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b00030d0a11 */ /* 0x000fcc00008f1406 */ /*0630*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */ /* 0x000ea2000c1e1900 */ /*0640*/ @P0 IMAD.WIDE R6, R7, R2, c[0x0][0x170] ; /* 0x00005c0007060625 */ /* 0x000fc800078e0202 */ /*0650*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */ /* 0x000fe200078e0203 */ /*0660*/ @P0 STG.E [R6.64], R13 ; /* 0x0000000d06000986 */ /* 0x0041e8000c101904 */ /*0670*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */ /* 0x000fda0003f06270 */ /*0680*/ @!P0 BRA 0x3a0 ; /* 0xfffffd1000008947 */ /* 0x001fea000383ffff */ /*0690*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*06b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0700*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0710*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0720*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0730*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0740*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0750*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0760*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0770*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
/* ********************************************** * CS314 Principles of Programming Languages * * Spring 2020 * ********************************************** */ #include <stdio.h> #include <stdlib.h> __global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) { /*YOUR CODE HERE*/ int allThreads = blockDim.x * gridDim.x; int tid = blockIdx.x * blockDim.x + threadIdx.x; for(int i = tid; i < numEdges; i += allThreads){ if (src[i] != src[i+1]){ output[src[i]] = scanResult[i]; } } if(tid >= numEdges && allThreads !=0){ return; } }
.file "tmpxft_00105df7_00000000-6_collateSegments.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2059: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i .type _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, @function _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i: .LFB2081: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2081: .size _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, .-_Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i .globl _Z19collateSegments_gpuPiS_S_i .type _Z19collateSegments_gpuPiS_S_i, @function _Z19collateSegments_gpuPiS_S_i: .LFB2082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2082: .size _Z19collateSegments_gpuPiS_S_i, .-_Z19collateSegments_gpuPiS_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z19collateSegments_gpuPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* ********************************************** * CS314 Principles of Programming Languages * * Spring 2020 * ********************************************** */ #include <stdio.h> #include <stdlib.h> __global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) { /*YOUR CODE HERE*/ int allThreads = blockDim.x * gridDim.x; int tid = blockIdx.x * blockDim.x + threadIdx.x; for(int i = tid; i < numEdges; i += allThreads){ if (src[i] != src[i+1]){ output[src[i]] = scanResult[i]; } } if(tid >= numEdges && allThreads !=0){ return; } }
/* ********************************************** * CS314 Principles of Programming Languages * * Spring 2020 * ********************************************** */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> __global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) { /*YOUR CODE HERE*/ int allThreads = blockDim.x * gridDim.x; int tid = blockIdx.x * blockDim.x + threadIdx.x; for(int i = tid; i < numEdges; i += allThreads){ if (src[i] != src[i+1]){ output[src[i]] = scanResult[i]; } } if(tid >= numEdges && allThreads !=0){ return; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/* ********************************************** * CS314 Principles of Programming Languages * * Spring 2020 * ********************************************** */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> __global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) { /*YOUR CODE HERE*/ int allThreads = blockDim.x * gridDim.x; int tid = blockIdx.x * blockDim.x + threadIdx.x; for(int i = tid; i < numEdges; i += allThreads){ if (src[i] != src[i+1]){ output[src[i]] = scanResult[i]; } } if(tid >= numEdges && allThreads !=0){ return; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19collateSegments_gpuPiS_S_i .globl _Z19collateSegments_gpuPiS_S_i .p2align 8 .type _Z19collateSegments_gpuPiS_S_i,@function _Z19collateSegments_gpuPiS_S_i: s_clause 0x1 s_load_b32 s4, s[0:1], 0x2c s_load_b32 s12, s[0:1], 0x18 s_add_u32 s2, s0, 32 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s12, v1 s_cbranch_execz .LBB0_5 s_load_b32 s9, s[2:3], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s8, s9, s8 s_ashr_i32 s9, s8, 31 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[10:11], s[8:9], 2 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v1, s8, v1 v_add_co_u32 v2, s0, v2, s10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v3, s0, s11, v3, s0 v_cmp_le_i32_e32 vcc_lo, s12, v1 s_or_b32 s1, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execz .LBB0_5 .LBB0_3: v_add_co_u32 v4, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo s_mov_b32 s0, exec_lo global_load_b64 v[4:5], v[4:5], off s_waitcnt vmcnt(0) v_cmpx_ne_u32_e64 v4, v5 s_cbranch_execz .LBB0_2 v_add_co_u32 v5, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo global_load_b32 v0, v[5:6], off v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[4:5] v_add_co_u32 v4, vcc_lo, s2, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[4:5], v0, off s_branch .LBB0_2 .LBB0_5: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19collateSegments_gpuPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z19collateSegments_gpuPiS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19collateSegments_gpuPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z19collateSegments_gpuPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/* ********************************************** * CS314 Principles of Programming Languages * * Spring 2020 * ********************************************** */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> __global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) { /*YOUR CODE HERE*/ int allThreads = blockDim.x * gridDim.x; int tid = blockIdx.x * blockDim.x + threadIdx.x; for(int i = tid; i < numEdges; i += allThreads){ if (src[i] != src[i+1]){ output[src[i]] = scanResult[i]; } } if(tid >= numEdges && allThreads !=0){ return; } }
.text .file "collateSegments.hip" .globl _Z34__device_stub__collateSegments_gpuPiS_S_i # -- Begin function _Z34__device_stub__collateSegments_gpuPiS_S_i .p2align 4, 0x90 .type _Z34__device_stub__collateSegments_gpuPiS_S_i,@function _Z34__device_stub__collateSegments_gpuPiS_S_i: # @_Z34__device_stub__collateSegments_gpuPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z19collateSegments_gpuPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z34__device_stub__collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z34__device_stub__collateSegments_gpuPiS_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19collateSegments_gpuPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z19collateSegments_gpuPiS_S_i,@object # @_Z19collateSegments_gpuPiS_S_i .section .rodata,"a",@progbits .globl _Z19collateSegments_gpuPiS_S_i .p2align 3, 0x0 _Z19collateSegments_gpuPiS_S_i: .quad _Z34__device_stub__collateSegments_gpuPiS_S_i .size _Z19collateSegments_gpuPiS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z19collateSegments_gpuPiS_S_i" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__collateSegments_gpuPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z19collateSegments_gpuPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z19collateSegments_gpuPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */ /* 0x001fca00078e0200 */ /*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0080*/ BSSY B0, 0x390 ; /* 0x0000030000007945 */ /* 0x000fe40003800000 */ /*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */ /* 0x000fc800078e02ff */ /*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */ /* 0x000e220000209000 */ /*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */ /* 0x000fe200078e0a00 */ /*00c0*/ ISETP.NE.U32.AND P2, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */ /* 0x040fe20003f45070 */ /*00d0*/ IMAD.IADD R2, R0, 0x1, R3 ; /* 0x0000000100027824 */ /* 0x000fca00078e0203 */ /*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */ /* 0x000fc800078e33ff */ /*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */ /* 0x000fe20007ffe000 */ /*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */ /* 0x001e240000001000 */ /*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */ /* 0x001fcc0007ffe0ff */ /*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */ /* 0x000064000021f000 */ /*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x001fe400078e00ff */ /*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */ /* 0x002fc800078e02ff */ /*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */ /* 0x000fcc00078e0004 */ /*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */ /* 0x000fc800078e00ff */ /*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */ /* 0x000fc800078e0a02 */ /*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */ /* 0x000fca00078e0207 */ /*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */ /* 0x000fda0003f06070 */ /*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */ /* 0x000fe40007ffe1ff */ /*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */ /* 0x000fe40007ffe0ff */ /*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */ /* 0x000fda0003f26070 */ /*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */ /* 0x000fe40007ffe0ff */ /*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */ /* 0x000fc800078e33ff */ /*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */ /* 0x040fe40007ffe0ff */ /*0200*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fe40003f06070 */ /*0210*/ LOP3.LUT P1, R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */ /* 0x000fda000782c0ff */ /*0220*/ @!P1 BRA 0x380 ; /* 0x0000015000009947 */ /* 0x000fea0003800000 */ /*0230*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */ /* 0x000fe400078e00ff */ /*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */ /* 0x000fe400078e0006 */ /*0250*/ IMAD.WIDE R4, R3, R10, c[0x0][0x160] ; /* 0x0000580003047625 */ /* 0x000fc800078e020a */ /*0260*/ IMAD.WIDE R6, R3, R10, c[0x0][0x168] ; /* 0x00005a0003067625 */ /* 0x000fe200078e020a */ /*0270*/ IADD3 R8, P1, R4, 0x4, RZ ; /* 0x0000000404087810 */ /* 0x000fca0007f3e0ff */ /*0280*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */ /* 0x000fc800008e0605 */ /*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */ /* 0x000fe200078e0008 */ /*02a0*/ MOV R11, R9 ; /* 0x00000009000b7202 */ /* 0x000fca0000000f00 */ /*02b0*/ LDG.E R5, [R10.64+-0x4] ; /* 0xfffffc040a057981 */ /* 0x000ea8000c1e1900 */ /*02c0*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */ /* 0x000ea4000c1e1900 */ /*02d0*/ ISETP.NE.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x004fda0003f25270 */ /*02e0*/ @P1 LDG.E R13, [R6.64] ; /* 0x00000004060d1981 */ /* 0x0000a2000c1e1900 */ /*02f0*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff041424 */ /* 0x000fe200078e00ff */ /*0300*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */ /* 0x000fe20007ffe0ff */ /*0310*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */ /* 0x000fc800078e020a */ /*0320*/ @P1 IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005041625 */ /* 0x000fc800078e0204 */ /*0330*/ IMAD.IADD R3, R0.reuse, 0x1, R3 ; /* 0x0000000100037824 */ /* 0x040fe400078e0203 */ /*0340*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */ /* 0x001fe200078e0206 */ /*0350*/ @P1 STG.E [R4.64], R13 ; /* 0x0000000d04001986 */ /* 0x0041e2000c101904 */ /*0360*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fda0003f25270 */ /*0370*/ @P1 BRA 0x290 ; /* 0xffffff1000001947 */ /* 0x001fea000383ffff */ /*0380*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0390*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*03a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fc800078e00ff */ /*03b0*/ IMAD.WIDE R8, R3, R2, c[0x0][0x160] ; /* 0x0000580003087625 */ /* 0x000fca00078e0202 */ /*03c0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */ /* 0x000ea8000c1e1900 */ /*03d0*/ LDG.E R4, [R8.64+0x4] ; /* 0x0000040408047981 */ /* 0x000ea4000c1e1900 */ /*03e0*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x004fe40003f05270 */ /*03f0*/ SHF.R.S32.HI R4, RZ, 0x1f, R3 ; /* 0x0000001fff047819 */ /* 0x000fd60000011403 */ /*0400*/ @P0 LEA R6, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003060a11 */ /* 0x000fc800078210ff */ /*0410*/ @P0 LEA.HI.X R7, R3, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b0003070a11 */ /* 0x000fca00008f1404 */ /*0420*/ @P0 LDG.E R15, [R6.64] ; /* 0x00000004060f0981 */ /* 0x000ea2000c1e1900 */ /*0430*/ @P0 IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005040625 */ /* 0x000fc800078e0202 */ /*0440*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */ /* 0x040fe200078e0208 */ /*0450*/ @P0 STG.E [R4.64], R15 ; /* 0x0000000f04000986 */ /* 0x0041e8000c101904 */ /*0460*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */ /* 0x000ea8000c1e1900 */ /*0470*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004040a0c7981 */ /* 0x000ea2000c1e1900 */ /*0480*/ IMAD.IADD R17, R0, 0x1, R3 ; /* 0x0000000100117824 */ /* 0x000fe200078e0203 */ /*0490*/ ISETP.NE.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720c */ /* 0x004fc80003f05270 */ /*04a0*/ SHF.R.S32.HI R12, RZ, 0x1f, R17 ; /* 0x0000001fff0c7819 */ /* 0x000fd20000011411 */ /*04b0*/ @P0 LEA R8, P1, R17, c[0x0][0x168], 0x2 ; /* 0x00005a0011080a11 */ /* 0x000fc800078210ff */ /*04c0*/ @P0 LEA.HI.X R9, R17, c[0x0][0x16c], R12, 0x2, P1 ; /* 0x00005b0011090a11 */ /* 0x000fca00008f140c */ /*04d0*/ @P0 LDG.E R3, [R8.64] ; /* 0x0000000408030981 */ /* 0x000ea2000c1e1900 */ /*04e0*/ @P0 IMAD.WIDE R6, R13, R2, c[0x0][0x170] ; /* 0x00005c000d060625 */ /* 0x000fc800078e0202 */ /*04f0*/ IMAD.WIDE R12, R0.reuse, 0x4, R10 ; /* 0x00000004000c7825 */ /* 0x040fe200078e020a */ /*0500*/ @P0 STG.E [R6.64], R3 ; /* 0x0000000306000986 */ /* 0x0043e8000c101904 */ /*0510*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */ /* 0x001ea8000c1e1900 */ /*0520*/ LDG.E R4, [R12.64+0x4] ; /* 0x000004040c047981 */ /* 0x000ea2000c1e1900 */ /*0530*/ IADD3 R17, R0, R17, RZ ; /* 0x0000001100117210 */ /* 0x000fc40007ffe0ff */ /*0540*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x004fe40003f05270 */ /*0550*/ SHF.R.S32.HI R4, RZ, 0x1f, R17 ; /* 0x0000001fff047819 */ /* 0x000fd60000011411 */ /*0560*/ @P0 LEA R10, P1, R17, c[0x0][0x168], 0x2 ; /* 0x00005a00110a0a11 */ /* 0x000fc800078210ff */ /*0570*/ @P0 LEA.HI.X R11, R17, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b00110b0a11 */ /* 0x000fcc00008f1404 */ /*0580*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b0981 */ /* 0x000ea2000c1e1900 */ /*0590*/ @P0 IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005040625 */ /* 0x000fc800078e0202 */ /*05a0*/ IMAD.WIDE R8, R0.reuse, 0x4, R12 ; /* 0x0000000400087825 */ /* 0x040fe200078e020c */ /*05b0*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */ /* 0x0041e8000c101904 */ /*05c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x002ea8000c1e1900 */ /*05d0*/ LDG.E R3, [R8.64+0x4] ; /* 0x0000040408037981 */ /* 0x000ea4000c1e1900 */ /*05e0*/ ISETP.NE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */ /* 0x004fe20003f05270 */ /*05f0*/ IMAD.IADD R3, R0, 0x1, R17 ; /* 0x0000000100037824 */ /* 0x000fca00078e0211 */ /*0600*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */ /* 0x000fce0000011403 */ /*0610*/ @P0 LEA R12, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a00030c0a11 */ /* 0x000fc800078210ff */ /*0620*/ @P0 LEA.HI.X R13, R3, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b00030d0a11 */ /* 0x000fcc00008f1406 */ /*0630*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */ /* 0x000ea2000c1e1900 */ /*0640*/ @P0 IMAD.WIDE R6, R7, R2, c[0x0][0x170] ; /* 0x00005c0007060625 */ /* 0x000fc800078e0202 */ /*0650*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */ /* 0x000fe200078e0203 */ /*0660*/ @P0 STG.E [R6.64], R13 ; /* 0x0000000d06000986 */ /* 0x0041e8000c101904 */ /*0670*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */ /* 0x000fda0003f06270 */ /*0680*/ @!P0 BRA 0x3a0 ; /* 0xfffffd1000008947 */ /* 0x001fea000383ffff */ /*0690*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*06b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0700*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0710*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0720*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0730*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0740*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0750*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0760*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0770*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19collateSegments_gpuPiS_S_i .globl _Z19collateSegments_gpuPiS_S_i .p2align 8 .type _Z19collateSegments_gpuPiS_S_i,@function _Z19collateSegments_gpuPiS_S_i: s_clause 0x1 s_load_b32 s4, s[0:1], 0x2c s_load_b32 s12, s[0:1], 0x18 s_add_u32 s2, s0, 32 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s12, v1 s_cbranch_execz .LBB0_5 s_load_b32 s9, s[2:3], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s8, s9, s8 s_ashr_i32 s9, s8, 31 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[10:11], s[8:9], 2 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v1, s8, v1 v_add_co_u32 v2, s0, v2, s10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v3, s0, s11, v3, s0 v_cmp_le_i32_e32 vcc_lo, s12, v1 s_or_b32 s1, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execz .LBB0_5 .LBB0_3: v_add_co_u32 v4, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo s_mov_b32 s0, exec_lo global_load_b64 v[4:5], v[4:5], off s_waitcnt vmcnt(0) v_cmpx_ne_u32_e64 v4, v5 s_cbranch_execz .LBB0_2 v_add_co_u32 v5, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo global_load_b32 v0, v[5:6], off v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[4:5] v_add_co_u32 v4, vcc_lo, s2, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[4:5], v0, off s_branch .LBB0_2 .LBB0_5: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19collateSegments_gpuPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z19collateSegments_gpuPiS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19collateSegments_gpuPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z19collateSegments_gpuPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00105df7_00000000-6_collateSegments.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2059: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i .type _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, @function _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i: .LFB2081: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2081: .size _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, .-_Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i .globl _Z19collateSegments_gpuPiS_S_i .type _Z19collateSegments_gpuPiS_S_i, @function _Z19collateSegments_gpuPiS_S_i: .LFB2082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2082: .size _Z19collateSegments_gpuPiS_S_i, .-_Z19collateSegments_gpuPiS_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z19collateSegments_gpuPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "collateSegments.hip" .globl _Z34__device_stub__collateSegments_gpuPiS_S_i # -- Begin function _Z34__device_stub__collateSegments_gpuPiS_S_i .p2align 4, 0x90 .type _Z34__device_stub__collateSegments_gpuPiS_S_i,@function _Z34__device_stub__collateSegments_gpuPiS_S_i: # @_Z34__device_stub__collateSegments_gpuPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z19collateSegments_gpuPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z34__device_stub__collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z34__device_stub__collateSegments_gpuPiS_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19collateSegments_gpuPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z19collateSegments_gpuPiS_S_i,@object # @_Z19collateSegments_gpuPiS_S_i .section .rodata,"a",@progbits .globl _Z19collateSegments_gpuPiS_S_i .p2align 3, 0x0 _Z19collateSegments_gpuPiS_S_i: .quad _Z34__device_stub__collateSegments_gpuPiS_S_i .size _Z19collateSegments_gpuPiS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z19collateSegments_gpuPiS_S_i" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__collateSegments_gpuPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z19collateSegments_gpuPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void set_chunk_data( int x, int y, double dx, double dy, double* cell_x, double* cell_y, double* cell_dx, double* cell_dy, double* vertex_x, double* vertex_y, double* volume, double* x_area, double* y_area) { const int gid = blockIdx.x*blockDim.x+threadIdx.x; if(gid < x) { cell_x[gid] = 0.5*(vertex_x[gid]+vertex_x[gid+1]); cell_dx[gid] = dx; } if(gid < y) { cell_y[gid] = 0.5*(vertex_y[gid]+vertex_y[gid+1]); cell_dy[gid] = dy; } if(gid < x*y) { volume[gid] = dx*dy; } if(gid < (x+1)*y) { x_area[gid] = dy; } if(gid < x*(y+1)) { y_area[gid] = dx; } }
code for sm_80 Function : _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */ /* 0x000fe40000000a00 */ /*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fe20000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0060*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fda0003f26270 */ /*0070*/ @!P1 MOV R11, 0x8 ; /* 0x00000008000b9802 */ /* 0x000fca0000000f00 */ /*0080*/ @!P1 IMAD.WIDE R4, R0, R11, c[0x0][0x198] ; /* 0x0000660000049625 */ /* 0x000fca00078e020b */ /*0090*/ @!P1 LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080804029981 */ /* 0x000ea8000c1e1b00 */ /*00a0*/ @!P1 LDG.E.64 R6, [R4.64] ; /* 0x0000000804069981 */ /* 0x000ea2000c1e1b00 */ /*00b0*/ ISETP.GE.AND P0, PT, R0.reuse, c[0x0][0x164], PT ; /* 0x0000590000007a0c */ /* 0x040fe20003f06270 */ /*00c0*/ @!P1 IMAD.WIDE R8, R0, R11, c[0x0][0x178] ; /* 0x00005e0000089625 */ /* 0x000fe200078e020b */ /*00d0*/ @!P1 MOV R16, c[0x0][0x168] ; /* 0x00005a0000109a02 */ /* 0x000fc60000000f00 */ /*00e0*/ @!P1 IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff119624 */ /* 0x000fe400078e00ff */ /*00f0*/ @!P1 IMAD.WIDE R10, R0, R11, c[0x0][0x188] ; /* 0x00006200000a9625 */ /* 0x000fe200078e020b */ /*0100*/ @!P1 DADD R6, R2, R6 ; /* 0x0000000002069229 */ /* 0x00404a0000000006 */ /*0110*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff038424 */ /* 0x001fe200078e00ff */ /*0120*/ @!P1 DMUL R6, R6, 0.5 ; /* 0x3fe0000006069828 */ /* 0x002e060000000000 */ /*0130*/ @!P0 IMAD.WIDE R12, R0, R3, c[0x0][0x1a0] ; /* 0x00006800000c8625 */ /* 0x000fc800078e0203 */ /*0140*/ @!P1 STG.E.64 [R8.64], R6 ; /* 0x0000000608009986 */ /* 0x0011e8000c101b08 */ /*0150*/ @!P1 STG.E.64 [R10.64], R16 ; /* 0x000000100a009986 */ /* 0x0003e8000c101b08 */ /*0160*/ @!P0 LDG.E.64 R4, [R12.64+0x8] ; /* 0x000008080c048981 */ /* 0x0004e8000c1e1b00 */ /*0170*/ @!P0 LDG.E.64 R14, [R12.64] ; /* 0x000000080c0e8981 */ /* 0x0004e2000c1e1b00 */ /*0180*/ UIMAD UR4, UR7, UR6, URZ ; /* 0x00000006070472a4 */ /* 0x000fe2000f8e023f */ /*0190*/ @!P0 IMAD.WIDE R6, R0, R3, c[0x0][0x180] ; /* 0x0000600000068625 */ /* 0x001fc600078e0203 */ /*01a0*/ UIADD3 UR5, UR4, UR7, URZ ; /* 0x0000000704057290 */ /* 0x000fe2000fffe03f */ /*01b0*/ @!P0 IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x190] ; /* 0x0000640000028625 */ /* 0x040fe200078e0203 */ /*01c0*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fe2000bf26270 */ /*01d0*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */ /* 0x000fc6000fffe03f */ /*01e0*/ ISETP.GE.AND P2, PT, R0, UR5, PT ; /* 0x0000000500007c0c */ /* 0x000fc6000bf46270 */ /*01f0*/ ISETP.GE.AND P3, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fcc000bf66270 */ /*0200*/ @!P1 MOV R18, c[0x0][0x168] ; /* 0x00005a0000129a02 */ /* 0x000fe20000000f00 */ /*0210*/ @!P1 IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b9424 */ /* 0x002fe200078e00ff */ /*0220*/ @!P1 MOV R19, c[0x0][0x16c] ; /* 0x00005b0000139a02 */ /* 0x000fe40000000f00 */ /*0230*/ @!P2 IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; /* 0x00000008ff0da424 */ /* 0x004fe200078e00ff */ /*0240*/ @!P2 MOV R16, c[0x0][0x170] ; /* 0x00005c000010aa02 */ /* 0x000fe20000000f00 */ /*0250*/ @!P1 IMAD.WIDE R10, R0.reuse, R11, c[0x0][0x1a8] ; /* 0x00006a00000a9625 */ /* 0x040fe200078e020b */ /*0260*/ @!P2 MOV R17, c[0x0][0x174] ; /* 0x00005d000011aa02 */ /* 0x000fe20000000f00 */ /*0270*/ @!P1 DMUL R8, R18, c[0x0][0x170] ; /* 0x00005c0012089a28 */ /* 0x000fe40000000000 */ /*0280*/ @!P2 IMAD.WIDE R12, R0, R13, c[0x0][0x1b0] ; /* 0x00006c00000ca625 */ /* 0x000fc400078e020d */ /*0290*/ @!P0 DADD R4, R4, R14 ; /* 0x0000000004048229 */ /* 0x008064000000000e */ /*02a0*/ @!P0 MOV R14, c[0x0][0x170] ; /* 0x00005c00000e8a02 */ /* 0x001fe40000000f00 */ /*02b0*/ @!P0 MOV R15, c[0x0][0x174] ; /* 0x00005d00000f8a02 */ /* 0x000fe40000000f00 */ /*02c0*/ @!P0 DMUL R4, R4, 0.5 ; /* 0x3fe0000004048828 */ /* 0x002e0e0000000000 */ /*02d0*/ @!P0 STG.E.64 [R6.64], R4 ; /* 0x0000000406008986 */ /* 0x0011e8000c101b08 */ /*02e0*/ @!P0 STG.E.64 [R2.64], R14 ; /* 0x0000000e02008986 */ /* 0x0001e8000c101b08 */ /*02f0*/ @!P1 STG.E.64 [R10.64], R8 ; /* 0x000000080a009986 */ /* 0x0001e8000c101b08 */ /*0300*/ @!P2 STG.E.64 [R12.64], R16 ; /* 0x000000100c00a986 */ /* 0x0001e2000c101b08 */ /*0310*/ @P3 EXIT ; /* 0x000000000000394d */ /* 0x000fea0003800000 */ /*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */ /* 0x001fe200078e00ff */ /*0330*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */ /* 0x000fc40000000f00 */ /*0340*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */ /* 0x000fe20000000f00 */ /*0350*/ IMAD.WIDE R2, R0, R3, c[0x0][0x1b8] ; /* 0x00006e0000027625 */ /* 0x000fca00078e0203 */ /*0360*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */ /* 0x000fe2000c101b08 */ /*0370*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0380*/ BRA 0x380; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0390*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0400*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0410*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0420*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0430*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0440*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0450*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0460*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0470*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void set_chunk_data( int x, int y, double dx, double dy, double* cell_x, double* cell_y, double* cell_dx, double* cell_dy, double* vertex_x, double* vertex_y, double* volume, double* x_area, double* y_area) { const int gid = blockIdx.x*blockDim.x+threadIdx.x; if(gid < x) { cell_x[gid] = 0.5*(vertex_x[gid]+vertex_x[gid+1]); cell_dx[gid] = dx; } if(gid < y) { cell_y[gid] = 0.5*(vertex_y[gid]+vertex_y[gid+1]); cell_dy[gid] = dy; } if(gid < x*y) { volume[gid] = dx*dy; } if(gid < (x+1)*y) { x_area[gid] = dy; } if(gid < x*(y+1)) { y_area[gid] = dx; } }
.file "tmpxft_000967ec_00000000-6_set_chunk_data.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_ .type _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_, @function _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_: .LFB2051: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movl %edi, 92(%rsp) movl %esi, 88(%rsp) movsd %xmm0, 80(%rsp) movsd %xmm1, 72(%rsp) movq %rdx, 64(%rsp) movq %rcx, 56(%rsp) movq %r8, 48(%rsp) movq %r9, 40(%rsp) movq 288(%rsp), %rax movq %rax, 32(%rsp) movq 296(%rsp), %rax movq %rax, 24(%rsp) movq 304(%rsp), %rax movq %rax, 16(%rsp) movq 312(%rsp), %rax movq %rax, 8(%rsp) movq 320(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 92(%rsp), %rax movq %rax, 160(%rsp) leaq 88(%rsp), %rax movq %rax, 168(%rsp) leaq 80(%rsp), %rax movq %rax, 176(%rsp) leaq 72(%rsp), %rax movq %rax, 184(%rsp) leaq 64(%rsp), %rax movq %rax, 192(%rsp) leaq 56(%rsp), %rax movq %rax, 200(%rsp) leaq 48(%rsp), %rax movq %rax, 208(%rsp) leaq 40(%rsp), %rax movq %rax, 216(%rsp) leaq 32(%rsp), %rax movq %rax, 224(%rsp) leaq 24(%rsp), %rax movq %rax, 232(%rsp) leaq 16(%rsp), %rax movq %rax, 240(%rsp) leaq 8(%rsp), %rax movq %rax, 248(%rsp) movq %rsp, %rax movq %rax, 256(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $1, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) leaq 104(%rsp), %rcx leaq 96(%rsp), %rdx leaq 124(%rsp), %rsi leaq 112(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 264(%rsp), %rax subq %fs:40, %rax jne .L8 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 104(%rsp) .cfi_def_cfa_offset 296 pushq 104(%rsp) .cfi_def_cfa_offset 304 leaq 176(%rsp), %r9 movq 140(%rsp), %rcx movl 148(%rsp), %r8d movq 128(%rsp), %rsi movl 136(%rsp), %edx leaq _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_, .-_Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_ .globl _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .type _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, @function _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_ addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, .-_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void set_chunk_data( int x, int y, double dx, double dy, double* cell_x, double* cell_y, double* cell_dx, double* cell_dy, double* vertex_x, double* vertex_y, double* volume, double* x_area, double* y_area) { const int gid = blockIdx.x*blockDim.x+threadIdx.x; if(gid < x) { cell_x[gid] = 0.5*(vertex_x[gid]+vertex_x[gid+1]); cell_dx[gid] = dx; } if(gid < y) { cell_y[gid] = 0.5*(vertex_y[gid]+vertex_y[gid+1]); cell_dy[gid] = dy; } if(gid < x*y) { volume[gid] = dx*dy; } if(gid < (x+1)*y) { x_area[gid] = dy; } if(gid < x*(y+1)) { y_area[gid] = dx; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void set_chunk_data( int x, int y, double dx, double dy, double* cell_x, double* cell_y, double* cell_dx, double* cell_dy, double* vertex_x, double* vertex_y, double* volume, double* x_area, double* y_area) { const int gid = blockIdx.x*blockDim.x+threadIdx.x; if(gid < x) { cell_x[gid] = 0.5*(vertex_x[gid]+vertex_x[gid+1]); cell_dx[gid] = dx; } if(gid < y) { cell_y[gid] = 0.5*(vertex_y[gid]+vertex_y[gid+1]); cell_dy[gid] = dy; } if(gid < x*y) { volume[gid] = dx*dy; } if(gid < (x+1)*y) { x_area[gid] = dy; } if(gid < x*(y+1)) { y_area[gid] = dx; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void set_chunk_data( int x, int y, double dx, double dy, double* cell_x, double* cell_y, double* cell_dx, double* cell_dy, double* vertex_x, double* vertex_y, double* volume, double* x_area, double* y_area) { const int gid = blockIdx.x*blockDim.x+threadIdx.x; if(gid < x) { cell_x[gid] = 0.5*(vertex_x[gid]+vertex_x[gid+1]); cell_dx[gid] = dx; } if(gid < y) { cell_y[gid] = 0.5*(vertex_y[gid]+vertex_y[gid+1]); cell_dy[gid] = dy; } if(gid < x*y) { volume[gid] = dx*dy; } if(gid < (x+1)*y) { x_area[gid] = dy; } if(gid < x*(y+1)) { y_area[gid] = dx; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .globl _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .p2align 8 .type _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_,@function _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: s_clause 0x2 s_load_b32 s4, s[0:1], 0x6c s_load_b32 s6, s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mov_b32 s4, exec_lo v_ashrrev_i32_e32 v2, 31, v1 v_cmpx_gt_i32_e64 s6, v1 s_cbranch_execz .LBB0_2 s_load_b64 s[8:9], s[0:1], 0x38 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s8, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s9, v8, vcc_lo global_load_b128 v[3:6], v[3:4], off s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x18 s_load_b64 s[10:11], s[0:1], 0x28 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s8, v7 v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo v_add_co_u32 v7, vcc_lo, s10, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo s_waitcnt vmcnt(0) v_add_f64 v[3:4], v[3:4], v[5:6] v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2 s_delay_alu instid0(VALU_DEP_2) v_mul_f64 v[3:4], v[3:4], 0.5 global_store_b64 v[9:10], v[3:4], off global_store_b64 v[7:8], v[5:6], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s4 s_clause 0x1 s_load_b32 s7, s[0:1], 0x4 s_load_b64 s[4:5], s[0:1], 0x10 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s7, v1 s_cbranch_execz .LBB0_4 s_load_b64 s[10:11], s[0:1], 0x40 v_lshlrev_b64 v[7:8], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s10, v7 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v8, vcc_lo global_load_b128 v[3:6], v[3:4], off s_clause 0x1 s_load_b64 s[10:11], s[0:1], 0x20 s_load_b64 s[12:13], s[0:1], 0x30 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s10, v7 v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo v_add_co_u32 v7, vcc_lo, s12, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo s_waitcnt vmcnt(0) v_add_f64 v[3:4], v[3:4], v[5:6] v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 s_delay_alu instid0(VALU_DEP_2) v_mul_f64 v[3:4], v[3:4], 0.5 global_store_b64 v[9:10], v[3:4], off global_store_b64 v[7:8], v[5:6], off .LBB0_4: s_or_b32 exec_lo, exec_lo, s8 s_mul_i32 s8, s7, s6 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s8, v1 s_and_saveexec_b32 s8, vcc_lo s_cbranch_execz .LBB0_6 v_mul_f64 v[3:4], s[2:3], s[4:5] s_load_b64 s[10:11], s[0:1], 0x48 v_lshlrev_b64 v[5:6], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s10, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo global_store_b64 v[5:6], v[3:4], off .LBB0_6: s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s8, s6, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s8, s8, s7 v_cmp_gt_i32_e32 vcc_lo, s8, v1 s_and_saveexec_b32 s8, vcc_lo s_cbranch_execz .LBB0_8 s_load_b64 s[10:11], s[0:1], 0x50 v_lshlrev_b64 v[3:4], 3, v[1:2] v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v3, vcc_lo, s10, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo global_store_b64 v[3:4], v[5:6], off .LBB0_8: s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s4, s7, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s4, s4, s6 v_cmp_gt_i32_e32 vcc_lo, s4, v1 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_10 s_load_b64 s[0:1], s[0:1], 0x58 v_lshlrev_b64 v[0:1], 3, v[1:2] v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b64 v[0:1], v[2:3], off .LBB0_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 352 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .offset: 96 .size: 4 .value_kind: hidden_block_count_x - .offset: 100 .size: 4 .value_kind: hidden_block_count_y - .offset: 104 .size: 4 .value_kind: hidden_block_count_z - .offset: 108 .size: 2 .value_kind: hidden_group_size_x - .offset: 110 .size: 2 .value_kind: hidden_group_size_y - .offset: 112 .size: 2 .value_kind: hidden_group_size_z - .offset: 114 .size: 2 .value_kind: hidden_remainder_x - .offset: 116 .size: 2 .value_kind: hidden_remainder_y - .offset: 118 .size: 2 .value_kind: hidden_remainder_z - .offset: 136 .size: 8 .value_kind: hidden_global_offset_x - .offset: 144 .size: 8 .value_kind: hidden_global_offset_y - .offset: 152 .size: 8 .value_kind: hidden_global_offset_z - .offset: 160 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 352 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void set_chunk_data( int x, int y, double dx, double dy, double* cell_x, double* cell_y, double* cell_dx, double* cell_dy, double* vertex_x, double* vertex_y, double* volume, double* x_area, double* y_area) { const int gid = blockIdx.x*blockDim.x+threadIdx.x; if(gid < x) { cell_x[gid] = 0.5*(vertex_x[gid]+vertex_x[gid+1]); cell_dx[gid] = dx; } if(gid < y) { cell_y[gid] = 0.5*(vertex_y[gid]+vertex_y[gid+1]); cell_dy[gid] = dy; } if(gid < x*y) { volume[gid] = dx*dy; } if(gid < (x+1)*y) { x_area[gid] = dy; } if(gid < x*(y+1)) { y_area[gid] = dx; } }
.text .file "set_chunk_data.hip" .globl _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ # -- Begin function _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .p2align 4, 0x90 .type _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_,@function _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: # @_Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .cfi_startproc # %bb.0: subq $216, %rsp .cfi_def_cfa_offset 224 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movsd %xmm0, 104(%rsp) movsd %xmm1, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 104(%rsp), %rax movq %rax, 128(%rsp) leaq 96(%rsp), %rax movq %rax, 136(%rsp) leaq 88(%rsp), %rax movq %rax, 144(%rsp) leaq 80(%rsp), %rax movq %rax, 152(%rsp) leaq 72(%rsp), %rax movq %rax, 160(%rsp) leaq 64(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 232(%rsp), %rax movq %rax, 184(%rsp) leaq 240(%rsp), %rax movq %rax, 192(%rsp) leaq 248(%rsp), %rax movq %rax, 200(%rsp) leaq 256(%rsp), %rax movq %rax, 208(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $232, %rsp .cfi_adjust_cfa_offset -232 retq .Lfunc_end0: .size _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_,@object # @_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .section .rodata,"a",@progbits .globl _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .p2align 3, 0x0 _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: .quad _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .size _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_" .size .L__unnamed_1, 41 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */ /* 0x000fe40000000a00 */ /*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fe20000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0060*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fda0003f26270 */ /*0070*/ @!P1 MOV R11, 0x8 ; /* 0x00000008000b9802 */ /* 0x000fca0000000f00 */ /*0080*/ @!P1 IMAD.WIDE R4, R0, R11, c[0x0][0x198] ; /* 0x0000660000049625 */ /* 0x000fca00078e020b */ /*0090*/ @!P1 LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080804029981 */ /* 0x000ea8000c1e1b00 */ /*00a0*/ @!P1 LDG.E.64 R6, [R4.64] ; /* 0x0000000804069981 */ /* 0x000ea2000c1e1b00 */ /*00b0*/ ISETP.GE.AND P0, PT, R0.reuse, c[0x0][0x164], PT ; /* 0x0000590000007a0c */ /* 0x040fe20003f06270 */ /*00c0*/ @!P1 IMAD.WIDE R8, R0, R11, c[0x0][0x178] ; /* 0x00005e0000089625 */ /* 0x000fe200078e020b */ /*00d0*/ @!P1 MOV R16, c[0x0][0x168] ; /* 0x00005a0000109a02 */ /* 0x000fc60000000f00 */ /*00e0*/ @!P1 IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff119624 */ /* 0x000fe400078e00ff */ /*00f0*/ @!P1 IMAD.WIDE R10, R0, R11, c[0x0][0x188] ; /* 0x00006200000a9625 */ /* 0x000fe200078e020b */ /*0100*/ @!P1 DADD R6, R2, R6 ; /* 0x0000000002069229 */ /* 0x00404a0000000006 */ /*0110*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff038424 */ /* 0x001fe200078e00ff */ /*0120*/ @!P1 DMUL R6, R6, 0.5 ; /* 0x3fe0000006069828 */ /* 0x002e060000000000 */ /*0130*/ @!P0 IMAD.WIDE R12, R0, R3, c[0x0][0x1a0] ; /* 0x00006800000c8625 */ /* 0x000fc800078e0203 */ /*0140*/ @!P1 STG.E.64 [R8.64], R6 ; /* 0x0000000608009986 */ /* 0x0011e8000c101b08 */ /*0150*/ @!P1 STG.E.64 [R10.64], R16 ; /* 0x000000100a009986 */ /* 0x0003e8000c101b08 */ /*0160*/ @!P0 LDG.E.64 R4, [R12.64+0x8] ; /* 0x000008080c048981 */ /* 0x0004e8000c1e1b00 */ /*0170*/ @!P0 LDG.E.64 R14, [R12.64] ; /* 0x000000080c0e8981 */ /* 0x0004e2000c1e1b00 */ /*0180*/ UIMAD UR4, UR7, UR6, URZ ; /* 0x00000006070472a4 */ /* 0x000fe2000f8e023f */ /*0190*/ @!P0 IMAD.WIDE R6, R0, R3, c[0x0][0x180] ; /* 0x0000600000068625 */ /* 0x001fc600078e0203 */ /*01a0*/ UIADD3 UR5, UR4, UR7, URZ ; /* 0x0000000704057290 */ /* 0x000fe2000fffe03f */ /*01b0*/ @!P0 IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x190] ; /* 0x0000640000028625 */ /* 0x040fe200078e0203 */ /*01c0*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fe2000bf26270 */ /*01d0*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */ /* 0x000fc6000fffe03f */ /*01e0*/ ISETP.GE.AND P2, PT, R0, UR5, PT ; /* 0x0000000500007c0c */ /* 0x000fc6000bf46270 */ /*01f0*/ ISETP.GE.AND P3, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fcc000bf66270 */ /*0200*/ @!P1 MOV R18, c[0x0][0x168] ; /* 0x00005a0000129a02 */ /* 0x000fe20000000f00 */ /*0210*/ @!P1 IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b9424 */ /* 0x002fe200078e00ff */ /*0220*/ @!P1 MOV R19, c[0x0][0x16c] ; /* 0x00005b0000139a02 */ /* 0x000fe40000000f00 */ /*0230*/ @!P2 IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; /* 0x00000008ff0da424 */ /* 0x004fe200078e00ff */ /*0240*/ @!P2 MOV R16, c[0x0][0x170] ; /* 0x00005c000010aa02 */ /* 0x000fe20000000f00 */ /*0250*/ @!P1 IMAD.WIDE R10, R0.reuse, R11, c[0x0][0x1a8] ; /* 0x00006a00000a9625 */ /* 0x040fe200078e020b */ /*0260*/ @!P2 MOV R17, c[0x0][0x174] ; /* 0x00005d000011aa02 */ /* 0x000fe20000000f00 */ /*0270*/ @!P1 DMUL R8, R18, c[0x0][0x170] ; /* 0x00005c0012089a28 */ /* 0x000fe40000000000 */ /*0280*/ @!P2 IMAD.WIDE R12, R0, R13, c[0x0][0x1b0] ; /* 0x00006c00000ca625 */ /* 0x000fc400078e020d */ /*0290*/ @!P0 DADD R4, R4, R14 ; /* 0x0000000004048229 */ /* 0x008064000000000e */ /*02a0*/ @!P0 MOV R14, c[0x0][0x170] ; /* 0x00005c00000e8a02 */ /* 0x001fe40000000f00 */ /*02b0*/ @!P0 MOV R15, c[0x0][0x174] ; /* 0x00005d00000f8a02 */ /* 0x000fe40000000f00 */ /*02c0*/ @!P0 DMUL R4, R4, 0.5 ; /* 0x3fe0000004048828 */ /* 0x002e0e0000000000 */ /*02d0*/ @!P0 STG.E.64 [R6.64], R4 ; /* 0x0000000406008986 */ /* 0x0011e8000c101b08 */ /*02e0*/ @!P0 STG.E.64 [R2.64], R14 ; /* 0x0000000e02008986 */ /* 0x0001e8000c101b08 */ /*02f0*/ @!P1 STG.E.64 [R10.64], R8 ; /* 0x000000080a009986 */ /* 0x0001e8000c101b08 */ /*0300*/ @!P2 STG.E.64 [R12.64], R16 ; /* 0x000000100c00a986 */ /* 0x0001e2000c101b08 */ /*0310*/ @P3 EXIT ; /* 0x000000000000394d */ /* 0x000fea0003800000 */ /*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */ /* 0x001fe200078e00ff */ /*0330*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */ /* 0x000fc40000000f00 */ /*0340*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */ /* 0x000fe20000000f00 */ /*0350*/ IMAD.WIDE R2, R0, R3, c[0x0][0x1b8] ; /* 0x00006e0000027625 */ /* 0x000fca00078e0203 */ /*0360*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */ /* 0x000fe2000c101b08 */ /*0370*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0380*/ BRA 0x380; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0390*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0400*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0410*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0420*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0430*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0440*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0450*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0460*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0470*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .globl _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .p2align 8 .type _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_,@function _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: s_clause 0x2 s_load_b32 s4, s[0:1], 0x6c s_load_b32 s6, s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mov_b32 s4, exec_lo v_ashrrev_i32_e32 v2, 31, v1 v_cmpx_gt_i32_e64 s6, v1 s_cbranch_execz .LBB0_2 s_load_b64 s[8:9], s[0:1], 0x38 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s8, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s9, v8, vcc_lo global_load_b128 v[3:6], v[3:4], off s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x18 s_load_b64 s[10:11], s[0:1], 0x28 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s8, v7 v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo v_add_co_u32 v7, vcc_lo, s10, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo s_waitcnt vmcnt(0) v_add_f64 v[3:4], v[3:4], v[5:6] v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2 s_delay_alu instid0(VALU_DEP_2) v_mul_f64 v[3:4], v[3:4], 0.5 global_store_b64 v[9:10], v[3:4], off global_store_b64 v[7:8], v[5:6], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s4 s_clause 0x1 s_load_b32 s7, s[0:1], 0x4 s_load_b64 s[4:5], s[0:1], 0x10 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s7, v1 s_cbranch_execz .LBB0_4 s_load_b64 s[10:11], s[0:1], 0x40 v_lshlrev_b64 v[7:8], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s10, v7 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v8, vcc_lo global_load_b128 v[3:6], v[3:4], off s_clause 0x1 s_load_b64 s[10:11], s[0:1], 0x20 s_load_b64 s[12:13], s[0:1], 0x30 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s10, v7 v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo v_add_co_u32 v7, vcc_lo, s12, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo s_waitcnt vmcnt(0) v_add_f64 v[3:4], v[3:4], v[5:6] v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 s_delay_alu instid0(VALU_DEP_2) v_mul_f64 v[3:4], v[3:4], 0.5 global_store_b64 v[9:10], v[3:4], off global_store_b64 v[7:8], v[5:6], off .LBB0_4: s_or_b32 exec_lo, exec_lo, s8 s_mul_i32 s8, s7, s6 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s8, v1 s_and_saveexec_b32 s8, vcc_lo s_cbranch_execz .LBB0_6 v_mul_f64 v[3:4], s[2:3], s[4:5] s_load_b64 s[10:11], s[0:1], 0x48 v_lshlrev_b64 v[5:6], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s10, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo global_store_b64 v[5:6], v[3:4], off .LBB0_6: s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s8, s6, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s8, s8, s7 v_cmp_gt_i32_e32 vcc_lo, s8, v1 s_and_saveexec_b32 s8, vcc_lo s_cbranch_execz .LBB0_8 s_load_b64 s[10:11], s[0:1], 0x50 v_lshlrev_b64 v[3:4], 3, v[1:2] v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v3, vcc_lo, s10, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo global_store_b64 v[3:4], v[5:6], off .LBB0_8: s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s4, s7, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s4, s4, s6 v_cmp_gt_i32_e32 vcc_lo, s4, v1 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_10 s_load_b64 s[0:1], s[0:1], 0x58 v_lshlrev_b64 v[0:1], 3, v[1:2] v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b64 v[0:1], v[2:3], off .LBB0_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 352 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .offset: 96 .size: 4 .value_kind: hidden_block_count_x - .offset: 100 .size: 4 .value_kind: hidden_block_count_y - .offset: 104 .size: 4 .value_kind: hidden_block_count_z - .offset: 108 .size: 2 .value_kind: hidden_group_size_x - .offset: 110 .size: 2 .value_kind: hidden_group_size_y - .offset: 112 .size: 2 .value_kind: hidden_group_size_z - .offset: 114 .size: 2 .value_kind: hidden_remainder_x - .offset: 116 .size: 2 .value_kind: hidden_remainder_y - .offset: 118 .size: 2 .value_kind: hidden_remainder_z - .offset: 136 .size: 8 .value_kind: hidden_global_offset_x - .offset: 144 .size: 8 .value_kind: hidden_global_offset_y - .offset: 152 .size: 8 .value_kind: hidden_global_offset_z - .offset: 160 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 352 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000967ec_00000000-6_set_chunk_data.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_ .type _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_, @function _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_: .LFB2051: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movl %edi, 92(%rsp) movl %esi, 88(%rsp) movsd %xmm0, 80(%rsp) movsd %xmm1, 72(%rsp) movq %rdx, 64(%rsp) movq %rcx, 56(%rsp) movq %r8, 48(%rsp) movq %r9, 40(%rsp) movq 288(%rsp), %rax movq %rax, 32(%rsp) movq 296(%rsp), %rax movq %rax, 24(%rsp) movq 304(%rsp), %rax movq %rax, 16(%rsp) movq 312(%rsp), %rax movq %rax, 8(%rsp) movq 320(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 92(%rsp), %rax movq %rax, 160(%rsp) leaq 88(%rsp), %rax movq %rax, 168(%rsp) leaq 80(%rsp), %rax movq %rax, 176(%rsp) leaq 72(%rsp), %rax movq %rax, 184(%rsp) leaq 64(%rsp), %rax movq %rax, 192(%rsp) leaq 56(%rsp), %rax movq %rax, 200(%rsp) leaq 48(%rsp), %rax movq %rax, 208(%rsp) leaq 40(%rsp), %rax movq %rax, 216(%rsp) leaq 32(%rsp), %rax movq %rax, 224(%rsp) leaq 24(%rsp), %rax movq %rax, 232(%rsp) leaq 16(%rsp), %rax movq %rax, 240(%rsp) leaq 8(%rsp), %rax movq %rax, 248(%rsp) movq %rsp, %rax movq %rax, 256(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $1, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) leaq 104(%rsp), %rcx leaq 96(%rsp), %rdx leaq 124(%rsp), %rsi leaq 112(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 264(%rsp), %rax subq %fs:40, %rax jne .L8 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 104(%rsp) .cfi_def_cfa_offset 296 pushq 104(%rsp) .cfi_def_cfa_offset 304 leaq 176(%rsp), %r9 movq 140(%rsp), %rcx movl 148(%rsp), %r8d movq 128(%rsp), %rsi movl 136(%rsp), %edx leaq _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_, .-_Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_ .globl _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .type _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, @function _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z54__device_stub__Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_iiddPdS_S_S_S_S_S_S_S_ addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, .-_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "set_chunk_data.hip" .globl _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ # -- Begin function _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .p2align 4, 0x90 .type _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_,@function _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: # @_Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .cfi_startproc # %bb.0: subq $216, %rsp .cfi_def_cfa_offset 224 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movsd %xmm0, 104(%rsp) movsd %xmm1, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 104(%rsp), %rax movq %rax, 128(%rsp) leaq 96(%rsp), %rax movq %rax, 136(%rsp) leaq 88(%rsp), %rax movq %rax, 144(%rsp) leaq 80(%rsp), %rax movq %rax, 152(%rsp) leaq 72(%rsp), %rax movq %rax, 160(%rsp) leaq 64(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 232(%rsp), %rax movq %rax, 184(%rsp) leaq 240(%rsp), %rax movq %rax, 192(%rsp) leaq 248(%rsp), %rax movq %rax, 200(%rsp) leaq 256(%rsp), %rax movq %rax, 208(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $232, %rsp .cfi_adjust_cfa_offset -232 retq .Lfunc_end0: .size _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_,@object # @_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .section .rodata,"a",@progbits .globl _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .p2align 3, 0x0 _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_: .quad _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .size _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_" .size .L__unnamed_1, 41 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14set_chunk_dataiiddPdS_S_S_S_S_S_S_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
// Author: Ulises Olivares // uolivares@unam.mx // Oct 22, 2020 #include<iostream> #include<stdio.h> #include<time.h> #include<cstdlib> #include<math.h> #include <unistd.h> #define n 99999999 // input/output 1D array size #define m 9999 //assume mask size as odd #define TILE_SIZE 1024 #define MAX_MASK_WIDTH 256 using namespace std; //Global variables long long int sizeN = n * sizeof(float); long long int sizeM = m * sizeof(float); float h_N[n] , h_M[m], h_P[n]; int threads = 1024; int blocks = ceil(float(n)/float(threads)); __constant__ float c_M[m]; // GPU timers using CUDA events float globalMemTimer = 0.0f, constantMemTimer = 0.0f, sharedMemTimer = 0.0f; // Method definition void generateRandom(float *h_a, int size); void parallelConvolution1D(); void parallelConvolutionConstant1D(); void parallelConvolutionTiled1D(); template <typename vec> void printVector(vec *V, int size); // Kernel definition __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width); __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width); __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width); int main(){ //init N and M with random numbers generateRandom(h_N, n); generateRandom(h_M, m); // Parallel convolution 1D kernel parallelConvolution1D(); // Parallel convolution 1D constant memory parallelConvolutionConstant1D(); // Parallel convolution 1D shared - constant memory parallelConvolutionTiled1D(); return 0; } __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*M[j]; } } P[i] = Pvalue; } __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("M[i]: %d ", c_M[i] ); //printf("thread: %d", i ); float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*c_M[j]; } } P[i] = Pvalue; } __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width) { int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("tid: %d ", i); __shared__ float N_ds[TILE_SIZE + MAX_MASK_WIDTH - 1]; int n1 = Mask_Width/2; int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x; if (threadIdx.x >= blockDim.x - n1) { N_ds[threadIdx.x - (blockDim.x - n1)] = (halo_index_left < 0) ? 0 : N[halo_index_left]; } N_ds[n1 + threadIdx.x] = N[blockIdx.x*blockDim.x + threadIdx.x]; int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x; if (threadIdx.x < n1) { N_ds[n1 + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? 0 : N[halo_index_right]; } __syncthreads(); float Pvalue = 0; for(int j = 0; j < Mask_Width; j++) { Pvalue += N_ds[threadIdx.x + j]*c_M[j]; } /*if(Pvalue!=0) printf("value: %f", Pvalue);*/ P[i] = Pvalue; //printf("tid %d Pvalue: %lf ", i, Pvalue ); } template <typename vec> void printVector(vec *V, int size){ for(int i = 0; i < size; i++){ cout<< V[i] << " "; } cout << endl; } void generateRandom(float *h_a, int size){ // Initialize seed srand(time(NULL)); for(int i=0; i<size; i++){ h_a[i] = float(rand() % 10 +1); } } void parallelConvolutionTiled1D() { float *d_N, *d_P; cudaMalloc((void **)&d_N, sizeN); cudaMalloc((void **)&d_P, sizeN); // copy data from host to device cudaMemcpy(d_N, h_N, sizeN, cudaMemcpyHostToDevice); // Trasfeer data to constant memory cudaMemcpyToSymbol(c_M, h_M, sizeM); // define timers cudaEvent_t start, stop; // events to take time cudaEventCreate(&start); cudaEventCreate(&stop); // start timer cudaEventRecord(start,0); //Launch kernel CUDAconvolution_1D_tiled<<<blocks, threads>>> (d_N, d_P, m, n); cudaEventRecord(stop,0); cudaEventSynchronize(stop); cudaEventElapsedTime(&sharedMemTimer, start, stop); cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Shared-Constant Mem) : " << sharedMemTimer << " ms, " << sharedMemTimer / 1000 << " secs" <<endl; cudaMemcpy(h_P, d_P, sizeN, cudaMemcpyDeviceToHost); //printVector(h_P, n); cudaFree(c_M); cudaFree(d_N); cudaFree(d_P); } void parallelConvolutionConstant1D(){ float *d_N, *d_P; cudaMalloc((void **)&d_N, sizeN); cudaMalloc((void **)&d_P, sizeN); // copy data from host to device cudaMemcpy(d_N, h_N, sizeN, cudaMemcpyHostToDevice); // Trasfeer data to constant memory cudaMemcpyToSymbol(c_M, h_M, sizeM); // define timers cudaEvent_t start, stop; // events to take time cudaEventCreate(&start); cudaEventCreate(&stop); // start timer cudaEventRecord(start,0); //Launch kernel CUDAConvolutionConstant1D<<<blocks, threads>>>(d_N, d_P, m, n); cudaEventRecord(stop,0); cudaEventSynchronize(stop); cudaEventElapsedTime(&constantMemTimer, start, stop); cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Constant Mem) : " << constantMemTimer << " ms, " << constantMemTimer / 1000 << " secs" <<endl; cudaMemcpy(h_P, d_P, sizeN, cudaMemcpyDeviceToHost); //cout<< "Resulting P vector (Constant)" << endl; //printVector(h_P, n); cudaFree(c_M); cudaFree(d_N); cudaFree(d_P); } void parallelConvolution1D(){ float *d_N, *d_M, *d_P; // Reservar memoria en device cudaMalloc((void **)&d_N, sizeN); cudaMalloc((void **)&d_M, sizeM); cudaMalloc((void **)&d_P, sizeN); // Transferir datos de host a device cudaMemcpy(d_N, h_N, sizeN, cudaMemcpyHostToDevice); cudaMemcpy(d_M, h_M, sizeM, cudaMemcpyHostToDevice); // define timers cudaEvent_t start, stop; // events to take time cudaEventCreate(&start); cudaEventCreate(&stop); // start timer cudaEventRecord(start,0); //Launch kernel CUDAConvolution1D<<<blocks, threads>>>(d_N, d_M, d_P, m, n); cudaEventRecord(stop,0); cudaEventSynchronize(stop); cudaEventElapsedTime(&globalMemTimer, start, stop); //cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Global Mem) : " << globalMemTimer << " ms, " << globalMemTimer / 1000 << " secs" <<endl; cudaMemcpy(h_P, d_P, sizeN, cudaMemcpyDeviceToHost); //cout<< "Resulting P vector (Global)" << endl; //printVector(h_P, n); //free(h_N); free(h_M); free(h_P); cudaFree(d_M); cudaFree(d_N); cudaFree(d_P); }
.file "tmpxft_000a3f2c_00000000-6_convolution_tiled.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3690: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3690: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z14generateRandomPfi .type _Z14generateRandomPfi, @function _Z14generateRandomPfi: .LFB3684: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %r12 movl %esi, %ebp movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT testl %ebp, %ebp jle .L3 movq %r12, %rbx movslq %ebp, %rbp leaq (%r12,%rbp,4), %rbp .L5: call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax addl $1, %eax pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 movss %xmm0, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L5 .L3: popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3684: .size _Z14generateRandomPfi, .-_Z14generateRandomPfi .globl _Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii .type _Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii, @function _Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii: .LFB3712: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L12 .L8: movq 136(%rsp), %rax subq %fs:40, %rax jne .L13 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z17CUDAConvolution1DPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L8 .L13: call __stack_chk_fail@PLT .cfi_endproc .LFE3712: .size _Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii, .-_Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii .globl _Z17CUDAConvolution1DPfS_S_ii .type _Z17CUDAConvolution1DPfS_S_ii, @function _Z17CUDAConvolution1DPfS_S_ii: .LFB3713: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3713: .size _Z17CUDAConvolution1DPfS_S_ii, .-_Z17CUDAConvolution1DPfS_S_ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Elapsed parallel 1D convolution (Global Mem) : " .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string " ms, " .LC3: .string " secs" .text .globl _Z21parallelConvolution1Dv .type _Z21parallelConvolution1Dv, @function _Z21parallelConvolution1Dv: .LFB3687: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $88, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi movq sizeN(%rip), %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq sizeM(%rip), %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq sizeN(%rip), %rsi call cudaMalloc@PLT movl $1, %ecx movq sizeN(%rip), %rdx leaq h_N(%rip), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq sizeM(%rip), %rdx leaq h_M(%rip), %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT leaq 32(%rsp), %rdi call cudaEventCreate@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT movl threads(%rip), %eax movl %eax, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl blocks(%rip), %eax movl %eax, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $0, %r9d movl $0, %r8d movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L24 .L17: movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movq 40(%rsp), %rdi call cudaEventSynchronize@PLT movq 40(%rsp), %rdx movq 32(%rsp), %rsi leaq globalMemTimer(%rip), %rdi call cudaEventElapsedTime@PLT movl $47, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT pxor %xmm0, %xmm0 cvtss2sd globalMemTimer(%rip), %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $5, %edx leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movss globalMemTimer(%rip), %xmm0 divss .LC2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $5, %edx leaq .LC3(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L25 cmpb $0, 56(%rbp) je .L20 movzbl 67(%rbp), %esi .L21: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $2, %ecx movq sizeN(%rip), %rdx movq 24(%rsp), %rsi leaq h_P(%rip), %rdi call cudaMemcpy@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L26 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state movl $99999999, %r8d movl $9999, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z43__device_stub__Z17CUDAConvolution1DPfS_S_iiPfS_S_ii jmp .L17 .L25: movq 72(%rsp), %rax subq %fs:40, %rax jne .L27 call _ZSt16__throw_bad_castv@PLT .L27: call __stack_chk_fail@PLT .L20: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L21 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE3687: .size _Z21parallelConvolution1Dv, .-_Z21parallelConvolution1Dv .globl _Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii .type _Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii, @function _Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii: .LFB3714: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L32 .L28: movq 136(%rsp), %rax subq %fs:40, %rax jne .L33 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z25CUDAConvolutionConstant1DPfS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L28 .L33: call __stack_chk_fail@PLT .cfi_endproc .LFE3714: .size _Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii, .-_Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii .globl _Z25CUDAConvolutionConstant1DPfS_ii .type _Z25CUDAConvolutionConstant1DPfS_ii, @function _Z25CUDAConvolutionConstant1DPfS_ii: .LFB3715: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3715: .size _Z25CUDAConvolutionConstant1DPfS_ii, .-_Z25CUDAConvolutionConstant1DPfS_ii .section .rodata.str1.8 .align 8 .LC4: .string "Elapsed parallel 1D convolution (Constant Mem) : " .text .globl _Z29parallelConvolutionConstant1Dv .type _Z29parallelConvolutionConstant1Dv, @function _Z29parallelConvolutionConstant1Dv: .LFB3686: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq %rsp, %rdi movq sizeN(%rip), %rsi call cudaMalloc@PLT leaq 8(%rsp), %rdi movq sizeN(%rip), %rsi call cudaMalloc@PLT movl $1, %ecx movq sizeN(%rip), %rdx leaq h_N(%rip), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %r8d movl $0, %ecx movq sizeM(%rip), %rdx leaq h_M(%rip), %rsi leaq _ZL3c_M(%rip), %rdi call cudaMemcpyToSymbol@PLT leaq 16(%rsp), %rdi call cudaEventCreate@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl threads(%rip), %eax movl %eax, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl blocks(%rip), %eax movl %eax, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L44 .L37: movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movq 24(%rsp), %rdi call cudaEventSynchronize@PLT movq 24(%rsp), %rdx movq 16(%rsp), %rsi leaq constantMemTimer(%rip), %rdi call cudaEventElapsedTime@PLT call cudaDeviceSynchronize@PLT movl $49, %edx leaq .LC4(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT pxor %xmm0, %xmm0 cvtss2sd constantMemTimer(%rip), %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $5, %edx leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movss constantMemTimer(%rip), %xmm0 divss .LC2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $5, %edx leaq .LC3(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L45 cmpb $0, 56(%rbp) je .L40 movzbl 67(%rbp), %esi .L41: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $2, %ecx movq sizeN(%rip), %rdx movq 8(%rsp), %rsi leaq h_P(%rip), %rdi call cudaMemcpy@PLT leaq _ZL3c_M(%rip), %rdi call cudaFree@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L46 addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L44: .cfi_restore_state movl $99999999, %ecx movl $9999, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z49__device_stub__Z25CUDAConvolutionConstant1DPfS_iiPfS_ii jmp .L37 .L45: movq 56(%rsp), %rax subq %fs:40, %rax jne .L47 call _ZSt16__throw_bad_castv@PLT .L47: call __stack_chk_fail@PLT .L40: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L41 .L46: call __stack_chk_fail@PLT .cfi_endproc .LFE3686: .size _Z29parallelConvolutionConstant1Dv, .-_Z29parallelConvolutionConstant1Dv .globl _Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii .type _Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii, @function _Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii: .LFB3716: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L52 .L48: movq 136(%rsp), %rax subq %fs:40, %rax jne .L53 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L52: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z24CUDAconvolution_1D_tiledPfS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L48 .L53: call __stack_chk_fail@PLT .cfi_endproc .LFE3716: .size _Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii, .-_Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii .globl _Z24CUDAconvolution_1D_tiledPfS_ii .type _Z24CUDAconvolution_1D_tiledPfS_ii, @function _Z24CUDAconvolution_1D_tiledPfS_ii: .LFB3717: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3717: .size _Z24CUDAconvolution_1D_tiledPfS_ii, .-_Z24CUDAconvolution_1D_tiledPfS_ii .section .rodata.str1.8 .align 8 .LC5: .string "Elapsed parallel 1D convolution (Shared-Constant Mem) : " .text .globl _Z26parallelConvolutionTiled1Dv .type _Z26parallelConvolutionTiled1Dv, @function _Z26parallelConvolutionTiled1Dv: .LFB3685: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq %rsp, %rdi movq sizeN(%rip), %rsi call cudaMalloc@PLT leaq 8(%rsp), %rdi movq sizeN(%rip), %rsi call cudaMalloc@PLT movl $1, %ecx movq sizeN(%rip), %rdx leaq h_N(%rip), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %r8d movl $0, %ecx movq sizeM(%rip), %rdx leaq h_M(%rip), %rsi leaq _ZL3c_M(%rip), %rdi call cudaMemcpyToSymbol@PLT leaq 16(%rsp), %rdi call cudaEventCreate@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl threads(%rip), %eax movl %eax, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl blocks(%rip), %eax movl %eax, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L64 .L57: movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movq 24(%rsp), %rdi call cudaEventSynchronize@PLT movq 24(%rsp), %rdx movq 16(%rsp), %rsi leaq sharedMemTimer(%rip), %rdi call cudaEventElapsedTime@PLT call cudaDeviceSynchronize@PLT movl $56, %edx leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT pxor %xmm0, %xmm0 cvtss2sd sharedMemTimer(%rip), %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $5, %edx leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movss sharedMemTimer(%rip), %xmm0 divss .LC2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $5, %edx leaq .LC3(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L65 cmpb $0, 56(%rbp) je .L60 movzbl 67(%rbp), %esi .L61: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $2, %ecx movq sizeN(%rip), %rdx movq 8(%rsp), %rsi leaq h_P(%rip), %rdi call cudaMemcpy@PLT leaq _ZL3c_M(%rip), %rdi call cudaFree@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L66 addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L64: .cfi_restore_state movl $99999999, %ecx movl $9999, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z48__device_stub__Z24CUDAconvolution_1D_tiledPfS_iiPfS_ii jmp .L57 .L65: movq 56(%rsp), %rax subq %fs:40, %rax jne .L67 call _ZSt16__throw_bad_castv@PLT .L67: call __stack_chk_fail@PLT .L60: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L61 .L66: call __stack_chk_fail@PLT .cfi_endproc .LFE3685: .size _Z26parallelConvolutionTiled1Dv, .-_Z26parallelConvolutionTiled1Dv .globl main .type main, @function main: .LFB3682: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl $99999999, %esi leaq h_N(%rip), %rdi call _Z14generateRandomPfi movl $9999, %esi leaq h_M(%rip), %rdi call _Z14generateRandomPfi call _Z21parallelConvolution1Dv call _Z29parallelConvolutionConstant1Dv call _Z26parallelConvolutionTiled1Dv movl $0, %eax addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3682: .size main, .-main .section .rodata.str1.8 .align 8 .LC6: .string "_Z24CUDAconvolution_1D_tiledPfS_ii" .align 8 .LC7: .string "_Z25CUDAConvolutionConstant1DPfS_ii" .section .rodata.str1.1 .LC8: .string "_Z17CUDAConvolution1DPfS_S_ii" .LC9: .string "c_M" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3719: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z24CUDAconvolution_1D_tiledPfS_ii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z25CUDAConvolutionConstant1DPfS_ii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z17CUDAConvolution1DPfS_S_ii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $39996, %r9d movl $0, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _ZL3c_M(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3719: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .text .type _GLOBAL__sub_I_sizeN, @function _GLOBAL__sub_I_sizeN: .LFB4349: .cfi_startproc endbr64 pxor %xmm1, %xmm1 cvtsi2ssl threads(%rip), %xmm1 movss .LC10(%rip), %xmm0 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC14(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC11(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L73 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC13(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L73: cvttss2sil %xmm3, %eax movl %eax, blocks(%rip) ret .cfi_endproc .LFE4349: .size _GLOBAL__sub_I_sizeN, .-_GLOBAL__sub_I_sizeN .section .init_array .align 8 .quad _GLOBAL__sub_I_sizeN .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl sharedMemTimer .bss .align 4 .type sharedMemTimer, @object .size sharedMemTimer, 4 sharedMemTimer: .zero 4 .globl constantMemTimer .align 4 .type constantMemTimer, @object .size constantMemTimer, 4 constantMemTimer: .zero 4 .globl globalMemTimer .align 4 .type globalMemTimer, @object .size globalMemTimer, 4 globalMemTimer: .zero 4 .local _ZL3c_M .comm _ZL3c_M,39996,32 .globl blocks .align 4 .type blocks, @object .size blocks, 4 blocks: .zero 4 .globl threads .data .align 4 .type threads, @object .size threads, 4 threads: .long 1024 .globl h_P .bss .align 32 .type h_P, @object .size h_P, 399999996 h_P: .zero 399999996 .globl h_M .align 32 .type h_M, @object .size h_M, 39996 h_M: .zero 39996 .globl h_N .align 32 .type h_N, @object .size h_N, 399999996 h_N: .zero 399999996 .globl sizeM .data .align 8 .type sizeM, @object .size sizeM, 8 sizeM: .quad 39996 .globl sizeN .align 8 .type sizeN, @object .size sizeN, 8 sizeN: .quad 399999996 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1148846080 .align 4 .LC10: .long 1287568416 .align 4 .LC11: .long 1258291200 .align 4 .LC13: .long 1065353216 .align 4 .LC14: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
// Author: Ulises Olivares // uolivares@unam.mx // Oct 22, 2020 #include<iostream> #include<stdio.h> #include<time.h> #include<cstdlib> #include<math.h> #include <unistd.h> #define n 99999999 // input/output 1D array size #define m 9999 //assume mask size as odd #define TILE_SIZE 1024 #define MAX_MASK_WIDTH 256 using namespace std; //Global variables long long int sizeN = n * sizeof(float); long long int sizeM = m * sizeof(float); float h_N[n] , h_M[m], h_P[n]; int threads = 1024; int blocks = ceil(float(n)/float(threads)); __constant__ float c_M[m]; // GPU timers using CUDA events float globalMemTimer = 0.0f, constantMemTimer = 0.0f, sharedMemTimer = 0.0f; // Method definition void generateRandom(float *h_a, int size); void parallelConvolution1D(); void parallelConvolutionConstant1D(); void parallelConvolutionTiled1D(); template <typename vec> void printVector(vec *V, int size); // Kernel definition __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width); __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width); __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width); int main(){ //init N and M with random numbers generateRandom(h_N, n); generateRandom(h_M, m); // Parallel convolution 1D kernel parallelConvolution1D(); // Parallel convolution 1D constant memory parallelConvolutionConstant1D(); // Parallel convolution 1D shared - constant memory parallelConvolutionTiled1D(); return 0; } __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*M[j]; } } P[i] = Pvalue; } __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("M[i]: %d ", c_M[i] ); //printf("thread: %d", i ); float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*c_M[j]; } } P[i] = Pvalue; } __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width) { int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("tid: %d ", i); __shared__ float N_ds[TILE_SIZE + MAX_MASK_WIDTH - 1]; int n1 = Mask_Width/2; int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x; if (threadIdx.x >= blockDim.x - n1) { N_ds[threadIdx.x - (blockDim.x - n1)] = (halo_index_left < 0) ? 0 : N[halo_index_left]; } N_ds[n1 + threadIdx.x] = N[blockIdx.x*blockDim.x + threadIdx.x]; int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x; if (threadIdx.x < n1) { N_ds[n1 + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? 0 : N[halo_index_right]; } __syncthreads(); float Pvalue = 0; for(int j = 0; j < Mask_Width; j++) { Pvalue += N_ds[threadIdx.x + j]*c_M[j]; } /*if(Pvalue!=0) printf("value: %f", Pvalue);*/ P[i] = Pvalue; //printf("tid %d Pvalue: %lf ", i, Pvalue ); } template <typename vec> void printVector(vec *V, int size){ for(int i = 0; i < size; i++){ cout<< V[i] << " "; } cout << endl; } void generateRandom(float *h_a, int size){ // Initialize seed srand(time(NULL)); for(int i=0; i<size; i++){ h_a[i] = float(rand() % 10 +1); } } void parallelConvolutionTiled1D() { float *d_N, *d_P; cudaMalloc((void **)&d_N, sizeN); cudaMalloc((void **)&d_P, sizeN); // copy data from host to device cudaMemcpy(d_N, h_N, sizeN, cudaMemcpyHostToDevice); // Trasfeer data to constant memory cudaMemcpyToSymbol(c_M, h_M, sizeM); // define timers cudaEvent_t start, stop; // events to take time cudaEventCreate(&start); cudaEventCreate(&stop); // start timer cudaEventRecord(start,0); //Launch kernel CUDAconvolution_1D_tiled<<<blocks, threads>>> (d_N, d_P, m, n); cudaEventRecord(stop,0); cudaEventSynchronize(stop); cudaEventElapsedTime(&sharedMemTimer, start, stop); cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Shared-Constant Mem) : " << sharedMemTimer << " ms, " << sharedMemTimer / 1000 << " secs" <<endl; cudaMemcpy(h_P, d_P, sizeN, cudaMemcpyDeviceToHost); //printVector(h_P, n); cudaFree(c_M); cudaFree(d_N); cudaFree(d_P); } void parallelConvolutionConstant1D(){ float *d_N, *d_P; cudaMalloc((void **)&d_N, sizeN); cudaMalloc((void **)&d_P, sizeN); // copy data from host to device cudaMemcpy(d_N, h_N, sizeN, cudaMemcpyHostToDevice); // Trasfeer data to constant memory cudaMemcpyToSymbol(c_M, h_M, sizeM); // define timers cudaEvent_t start, stop; // events to take time cudaEventCreate(&start); cudaEventCreate(&stop); // start timer cudaEventRecord(start,0); //Launch kernel CUDAConvolutionConstant1D<<<blocks, threads>>>(d_N, d_P, m, n); cudaEventRecord(stop,0); cudaEventSynchronize(stop); cudaEventElapsedTime(&constantMemTimer, start, stop); cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Constant Mem) : " << constantMemTimer << " ms, " << constantMemTimer / 1000 << " secs" <<endl; cudaMemcpy(h_P, d_P, sizeN, cudaMemcpyDeviceToHost); //cout<< "Resulting P vector (Constant)" << endl; //printVector(h_P, n); cudaFree(c_M); cudaFree(d_N); cudaFree(d_P); } void parallelConvolution1D(){ float *d_N, *d_M, *d_P; // Reservar memoria en device cudaMalloc((void **)&d_N, sizeN); cudaMalloc((void **)&d_M, sizeM); cudaMalloc((void **)&d_P, sizeN); // Transferir datos de host a device cudaMemcpy(d_N, h_N, sizeN, cudaMemcpyHostToDevice); cudaMemcpy(d_M, h_M, sizeM, cudaMemcpyHostToDevice); // define timers cudaEvent_t start, stop; // events to take time cudaEventCreate(&start); cudaEventCreate(&stop); // start timer cudaEventRecord(start,0); //Launch kernel CUDAConvolution1D<<<blocks, threads>>>(d_N, d_M, d_P, m, n); cudaEventRecord(stop,0); cudaEventSynchronize(stop); cudaEventElapsedTime(&globalMemTimer, start, stop); //cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Global Mem) : " << globalMemTimer << " ms, " << globalMemTimer / 1000 << " secs" <<endl; cudaMemcpy(h_P, d_P, sizeN, cudaMemcpyDeviceToHost); //cout<< "Resulting P vector (Global)" << endl; //printVector(h_P, n); //free(h_N); free(h_M); free(h_P); cudaFree(d_M); cudaFree(d_N); cudaFree(d_P); }
// Author: Ulises Olivares // uolivares@unam.mx // Oct 22, 2020 #include <hip/hip_runtime.h> #include<iostream> #include<stdio.h> #include<time.h> #include<cstdlib> #include<math.h> #include <unistd.h> #define n 99999999 // input/output 1D array size #define m 9999 //assume mask size as odd #define TILE_SIZE 1024 #define MAX_MASK_WIDTH 256 using namespace std; //Global variables long long int sizeN = n * sizeof(float); long long int sizeM = m * sizeof(float); float h_N[n] , h_M[m], h_P[n]; int threads = 1024; int blocks = ceil(float(n)/float(threads)); __constant__ float c_M[m]; // GPU timers using CUDA events float globalMemTimer = 0.0f, constantMemTimer = 0.0f, sharedMemTimer = 0.0f; // Method definition void generateRandom(float *h_a, int size); void parallelConvolution1D(); void parallelConvolutionConstant1D(); void parallelConvolutionTiled1D(); template <typename vec> void printVector(vec *V, int size); // Kernel definition __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width); __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width); __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width); int main(){ //init N and M with random numbers generateRandom(h_N, n); generateRandom(h_M, m); // Parallel convolution 1D kernel parallelConvolution1D(); // Parallel convolution 1D constant memory parallelConvolutionConstant1D(); // Parallel convolution 1D shared - constant memory parallelConvolutionTiled1D(); return 0; } __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*M[j]; } } P[i] = Pvalue; } __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("M[i]: %d ", c_M[i] ); //printf("thread: %d", i ); float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*c_M[j]; } } P[i] = Pvalue; } __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width) { int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("tid: %d ", i); __shared__ float N_ds[TILE_SIZE + MAX_MASK_WIDTH - 1]; int n1 = Mask_Width/2; int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x; if (threadIdx.x >= blockDim.x - n1) { N_ds[threadIdx.x - (blockDim.x - n1)] = (halo_index_left < 0) ? 0 : N[halo_index_left]; } N_ds[n1 + threadIdx.x] = N[blockIdx.x*blockDim.x + threadIdx.x]; int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x; if (threadIdx.x < n1) { N_ds[n1 + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? 0 : N[halo_index_right]; } __syncthreads(); float Pvalue = 0; for(int j = 0; j < Mask_Width; j++) { Pvalue += N_ds[threadIdx.x + j]*c_M[j]; } /*if(Pvalue!=0) printf("value: %f", Pvalue);*/ P[i] = Pvalue; //printf("tid %d Pvalue: %lf ", i, Pvalue ); } template <typename vec> void printVector(vec *V, int size){ for(int i = 0; i < size; i++){ cout<< V[i] << " "; } cout << endl; } void generateRandom(float *h_a, int size){ // Initialize seed srand(time(NULL)); for(int i=0; i<size; i++){ h_a[i] = float(rand() % 10 +1); } } void parallelConvolutionTiled1D() { float *d_N, *d_P; hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_P, sizeN); // copy data from host to device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); // Trasfeer data to constant memory hipMemcpyToSymbol(HIP_SYMBOL(c_M), h_M, sizeM); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAconvolution_1D_tiled<<<blocks, threads>>> (d_N, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&sharedMemTimer, start, stop); hipDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Shared-Constant Mem) : " << sharedMemTimer << " ms, " << sharedMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //printVector(h_P, n); hipFree(c_M); hipFree(d_N); hipFree(d_P); } void parallelConvolutionConstant1D(){ float *d_N, *d_P; hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_P, sizeN); // copy data from host to device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); // Trasfeer data to constant memory hipMemcpyToSymbol(HIP_SYMBOL(c_M), h_M, sizeM); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAConvolutionConstant1D<<<blocks, threads>>>(d_N, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&constantMemTimer, start, stop); hipDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Constant Mem) : " << constantMemTimer << " ms, " << constantMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //cout<< "Resulting P vector (Constant)" << endl; //printVector(h_P, n); hipFree(c_M); hipFree(d_N); hipFree(d_P); } void parallelConvolution1D(){ float *d_N, *d_M, *d_P; // Reservar memoria en device hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_M, sizeM); hipMalloc((void **)&d_P, sizeN); // Transferir datos de host a device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); hipMemcpy(d_M, h_M, sizeM, hipMemcpyHostToDevice); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAConvolution1D<<<blocks, threads>>>(d_N, d_M, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&globalMemTimer, start, stop); //cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Global Mem) : " << globalMemTimer << " ms, " << globalMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //cout<< "Resulting P vector (Global)" << endl; //printVector(h_P, n); //free(h_N); free(h_M); free(h_P); hipFree(d_M); hipFree(d_N); hipFree(d_P); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
// Author: Ulises Olivares // uolivares@unam.mx // Oct 22, 2020 #include <hip/hip_runtime.h> #include<iostream> #include<stdio.h> #include<time.h> #include<cstdlib> #include<math.h> #include <unistd.h> #define n 99999999 // input/output 1D array size #define m 9999 //assume mask size as odd #define TILE_SIZE 1024 #define MAX_MASK_WIDTH 256 using namespace std; //Global variables long long int sizeN = n * sizeof(float); long long int sizeM = m * sizeof(float); float h_N[n] , h_M[m], h_P[n]; int threads = 1024; int blocks = ceil(float(n)/float(threads)); __constant__ float c_M[m]; // GPU timers using CUDA events float globalMemTimer = 0.0f, constantMemTimer = 0.0f, sharedMemTimer = 0.0f; // Method definition void generateRandom(float *h_a, int size); void parallelConvolution1D(); void parallelConvolutionConstant1D(); void parallelConvolutionTiled1D(); template <typename vec> void printVector(vec *V, int size); // Kernel definition __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width); __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width); __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width); int main(){ //init N and M with random numbers generateRandom(h_N, n); generateRandom(h_M, m); // Parallel convolution 1D kernel parallelConvolution1D(); // Parallel convolution 1D constant memory parallelConvolutionConstant1D(); // Parallel convolution 1D shared - constant memory parallelConvolutionTiled1D(); return 0; } __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*M[j]; } } P[i] = Pvalue; } __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("M[i]: %d ", c_M[i] ); //printf("thread: %d", i ); float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*c_M[j]; } } P[i] = Pvalue; } __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width) { int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("tid: %d ", i); __shared__ float N_ds[TILE_SIZE + MAX_MASK_WIDTH - 1]; int n1 = Mask_Width/2; int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x; if (threadIdx.x >= blockDim.x - n1) { N_ds[threadIdx.x - (blockDim.x - n1)] = (halo_index_left < 0) ? 0 : N[halo_index_left]; } N_ds[n1 + threadIdx.x] = N[blockIdx.x*blockDim.x + threadIdx.x]; int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x; if (threadIdx.x < n1) { N_ds[n1 + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? 0 : N[halo_index_right]; } __syncthreads(); float Pvalue = 0; for(int j = 0; j < Mask_Width; j++) { Pvalue += N_ds[threadIdx.x + j]*c_M[j]; } /*if(Pvalue!=0) printf("value: %f", Pvalue);*/ P[i] = Pvalue; //printf("tid %d Pvalue: %lf ", i, Pvalue ); } template <typename vec> void printVector(vec *V, int size){ for(int i = 0; i < size; i++){ cout<< V[i] << " "; } cout << endl; } void generateRandom(float *h_a, int size){ // Initialize seed srand(time(NULL)); for(int i=0; i<size; i++){ h_a[i] = float(rand() % 10 +1); } } void parallelConvolutionTiled1D() { float *d_N, *d_P; hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_P, sizeN); // copy data from host to device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); // Trasfeer data to constant memory hipMemcpyToSymbol(HIP_SYMBOL(c_M), h_M, sizeM); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAconvolution_1D_tiled<<<blocks, threads>>> (d_N, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&sharedMemTimer, start, stop); hipDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Shared-Constant Mem) : " << sharedMemTimer << " ms, " << sharedMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //printVector(h_P, n); hipFree(c_M); hipFree(d_N); hipFree(d_P); } void parallelConvolutionConstant1D(){ float *d_N, *d_P; hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_P, sizeN); // copy data from host to device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); // Trasfeer data to constant memory hipMemcpyToSymbol(HIP_SYMBOL(c_M), h_M, sizeM); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAConvolutionConstant1D<<<blocks, threads>>>(d_N, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&constantMemTimer, start, stop); hipDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Constant Mem) : " << constantMemTimer << " ms, " << constantMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //cout<< "Resulting P vector (Constant)" << endl; //printVector(h_P, n); hipFree(c_M); hipFree(d_N); hipFree(d_P); } void parallelConvolution1D(){ float *d_N, *d_M, *d_P; // Reservar memoria en device hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_M, sizeM); hipMalloc((void **)&d_P, sizeN); // Transferir datos de host a device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); hipMemcpy(d_M, h_M, sizeM, hipMemcpyHostToDevice); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAConvolution1D<<<blocks, threads>>>(d_N, d_M, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&globalMemTimer, start, stop); //cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Global Mem) : " << globalMemTimer << " ms, " << globalMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //cout<< "Resulting P vector (Global)" << endl; //printVector(h_P, n); //free(h_N); free(h_M); free(h_P); hipFree(d_M); hipFree(d_N); hipFree(d_P); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z17CUDAConvolution1DPfS_S_ii .globl _Z17CUDAConvolution1DPfS_S_ii .p2align 8 .type _Z17CUDAConvolution1DPfS_S_ii,@function _Z17CUDAConvolution1DPfS_S_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_cmp_lt_i32 s3, 1 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_cbranch_scc1 .LBB0_5 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s8, s[0:1], 0x1c s_lshr_b32 s2, s3, 31 v_mov_b32_e32 v3, 0 s_add_i32 s2, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s2, s2, 1 v_subrev_nc_u32_e32 v2, s2, v1 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v0, v3 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 s_add_i32 s3, s3, -1 v_add_nc_u32_e32 v2, 1, v2 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_6 .LBB0_3: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v2 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e64 s2, s8, v2 s_and_b32 s9, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s2, s9 s_cbranch_execz .LBB0_2 v_lshlrev_b64 v[4:5], 2, v[2:3] s_load_b32 s9, s[6:7], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_b32 v4, v[4:5], off s_waitcnt vmcnt(0) lgkmcnt(0) v_fmac_f32_e32 v0, s9, v4 s_branch .LBB0_2 .LBB0_5: v_mov_b32_e32 v0, 0 .LBB0_6: s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z17CUDAConvolution1DPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z17CUDAConvolution1DPfS_S_ii, .Lfunc_end0-_Z17CUDAConvolution1DPfS_S_ii .section .AMDGPU.csdata,"",@progbits .text .protected _Z25CUDAConvolutionConstant1DPfS_ii .globl _Z25CUDAConvolutionConstant1DPfS_ii .p2align 8 .type _Z25CUDAConvolutionConstant1DPfS_ii,@function _Z25CUDAConvolutionConstant1DPfS_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_cmp_lt_i32 s3, 1 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_cbranch_scc1 .LBB1_5 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s8, s[0:1], 0x14 s_lshr_b32 s2, s3, 31 v_mov_b32_e32 v3, 0 s_add_i32 s2, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) s_ashr_i32 s2, s2, 1 s_getpc_b64 s[6:7] s_add_u32 s6, s6, c_M@rel32@lo+4 s_addc_u32 s7, s7, c_M@rel32@hi+12 v_subrev_nc_u32_e32 v2, s2, v1 v_mov_b32_e32 v0, v3 s_branch .LBB1_3 .p2align 6 .LBB1_2: s_or_b32 exec_lo, exec_lo, s2 s_add_i32 s3, s3, -1 v_add_nc_u32_e32 v2, 1, v2 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB1_6 .LBB1_3: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v2 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e64 s2, s8, v2 s_and_b32 s9, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s2, s9 s_cbranch_execz .LBB1_2 v_lshlrev_b64 v[4:5], 2, v[2:3] s_load_b32 s9, s[6:7], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_b32 v4, v[4:5], off s_waitcnt vmcnt(0) lgkmcnt(0) v_fmac_f32_e32 v0, s9, v4 s_branch .LBB1_2 .LBB1_5: v_mov_b32_e32 v0, 0 .LBB1_6: s_load_b64 s[0:1], s[0:1], 0x8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25CUDAConvolutionConstant1DPfS_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z25CUDAConvolutionConstant1DPfS_ii, .Lfunc_end1-_Z25CUDAConvolutionConstant1DPfS_ii .section .AMDGPU.csdata,"",@progbits .text .protected _Z24CUDAconvolution_1D_tiledPfS_ii .globl _Z24CUDAconvolution_1D_tiledPfS_ii .p2align 8 .type _Z24CUDAconvolution_1D_tiledPfS_ii,@function _Z24CUDAconvolution_1D_tiledPfS_ii: s_clause 0x2 s_load_b32 s4, s[0:1], 0x10 s_load_b32 s5, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_lshr_b32 s6, s4, 31 s_and_b32 s5, s5, 0xffff s_add_i32 s6, s4, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s6, s6, 1 s_sub_i32 s7, s5, s6 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_le_u32_e32 vcc_lo, s7, v0 s_and_saveexec_b32 s7, vcc_lo s_cbranch_execz .LBB2_4 s_add_i32 s8, s15, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s8, s5, v[0:1] v_mov_b32_e32 v2, 0 s_mov_b32 s8, exec_lo v_cmpx_lt_i32_e32 -1, v1 s_cbranch_execz .LBB2_3 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s2, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo global_load_b32 v2, v[1:2], off .LBB2_3: s_or_b32 exec_lo, exec_lo, s8 v_add_nc_u32_e32 v1, s6, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v1, s5, v1 v_lshlrev_b32_e32 v1, 2, v1 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 .LBB2_4: s_or_b32 exec_lo, exec_lo, s7 v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1] v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[1:2] v_add_co_u32 v3, vcc_lo, s2, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo global_load_b32 v3, v[3:4], off v_add_lshl_u32 v4, s6, v0, 2 s_waitcnt vmcnt(0) ds_store_b32 v4, v3 v_cmpx_gt_u32_e64 s6, v0 s_cbranch_execz .LBB2_8 s_load_b32 s8, s[0:1], 0x14 s_add_i32 s15, s15, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1] s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s8, v3 s_and_saveexec_b32 s8, vcc_lo s_cbranch_execz .LBB2_7 v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[3:4] v_add_co_u32 v2, vcc_lo, s2, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v2, v[2:3], off .LBB2_7: s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s5, s5, s6 s_delay_alu instid0(SALU_CYCLE_1) v_add_lshl_u32 v3, s5, v0, 2 s_waitcnt vmcnt(0) ds_store_b32 v3, v2 .LBB2_8: s_or_b32 exec_lo, exec_lo, s7 s_cmp_lt_i32 s4, 1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB2_11 v_lshlrev_b32_e32 v2, 2, v0 v_mov_b32_e32 v0, 0 s_getpc_b64 s[2:3] s_add_u32 s2, s2, c_M@rel32@lo+4 s_addc_u32 s3, s3, c_M@rel32@hi+12 .LBB2_10: ds_load_b32 v3, v2 s_load_b32 s5, s[2:3], 0x0 s_add_i32 s4, s4, -1 v_add_nc_u32_e32 v2, 4, v2 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmp_eq_u32 s4, 0 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v0, s5, v3 s_cbranch_scc0 .LBB2_10 s_branch .LBB2_12 .LBB2_11: v_mov_b32_e32 v0, 0 .LBB2_12: s_load_b64 s[0:1], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z24CUDAconvolution_1D_tiledPfS_ii .amdhsa_group_segment_fixed_size 5116 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z24CUDAconvolution_1D_tiledPfS_ii, .Lfunc_end2-_Z24CUDAconvolution_1D_tiledPfS_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected c_M .type c_M,@object .section .bss,"aw",@nobits .globl c_M .p2align 4, 0x0 c_M: .zero 39996 .size c_M, 39996 .type __hip_cuid_,@object .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym c_M .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z17CUDAConvolution1DPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z17CUDAConvolution1DPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25CUDAConvolutionConstant1DPfS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25CUDAConvolutionConstant1DPfS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 5116 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z24CUDAconvolution_1D_tiledPfS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z24CUDAconvolution_1D_tiledPfS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
// Author: Ulises Olivares // uolivares@unam.mx // Oct 22, 2020 #include <hip/hip_runtime.h> #include<iostream> #include<stdio.h> #include<time.h> #include<cstdlib> #include<math.h> #include <unistd.h> #define n 99999999 // input/output 1D array size #define m 9999 //assume mask size as odd #define TILE_SIZE 1024 #define MAX_MASK_WIDTH 256 using namespace std; //Global variables long long int sizeN = n * sizeof(float); long long int sizeM = m * sizeof(float); float h_N[n] , h_M[m], h_P[n]; int threads = 1024; int blocks = ceil(float(n)/float(threads)); __constant__ float c_M[m]; // GPU timers using CUDA events float globalMemTimer = 0.0f, constantMemTimer = 0.0f, sharedMemTimer = 0.0f; // Method definition void generateRandom(float *h_a, int size); void parallelConvolution1D(); void parallelConvolutionConstant1D(); void parallelConvolutionTiled1D(); template <typename vec> void printVector(vec *V, int size); // Kernel definition __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width); __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width); __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width); int main(){ //init N and M with random numbers generateRandom(h_N, n); generateRandom(h_M, m); // Parallel convolution 1D kernel parallelConvolution1D(); // Parallel convolution 1D constant memory parallelConvolutionConstant1D(); // Parallel convolution 1D shared - constant memory parallelConvolutionTiled1D(); return 0; } __global__ void CUDAConvolution1D(float *N, float *M, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*M[j]; } } P[i] = Pvalue; } __global__ void CUDAConvolutionConstant1D(float *N, float *P, int Mask_Width, int Width){ int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("M[i]: %d ", c_M[i] ); //printf("thread: %d", i ); float Pvalue = 0; int N_start_point = i - (Mask_Width/2); for (int j = 0; j < Mask_Width; j++) { if (N_start_point + j >= 0 && N_start_point + j < Width) { Pvalue += N[N_start_point + j]*c_M[j]; } } P[i] = Pvalue; } __global__ void CUDAconvolution_1D_tiled(float *N, float *P, int Mask_Width, int Width) { int i = blockIdx.x*blockDim.x + threadIdx.x; //printf("tid: %d ", i); __shared__ float N_ds[TILE_SIZE + MAX_MASK_WIDTH - 1]; int n1 = Mask_Width/2; int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x; if (threadIdx.x >= blockDim.x - n1) { N_ds[threadIdx.x - (blockDim.x - n1)] = (halo_index_left < 0) ? 0 : N[halo_index_left]; } N_ds[n1 + threadIdx.x] = N[blockIdx.x*blockDim.x + threadIdx.x]; int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x; if (threadIdx.x < n1) { N_ds[n1 + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? 0 : N[halo_index_right]; } __syncthreads(); float Pvalue = 0; for(int j = 0; j < Mask_Width; j++) { Pvalue += N_ds[threadIdx.x + j]*c_M[j]; } /*if(Pvalue!=0) printf("value: %f", Pvalue);*/ P[i] = Pvalue; //printf("tid %d Pvalue: %lf ", i, Pvalue ); } template <typename vec> void printVector(vec *V, int size){ for(int i = 0; i < size; i++){ cout<< V[i] << " "; } cout << endl; } void generateRandom(float *h_a, int size){ // Initialize seed srand(time(NULL)); for(int i=0; i<size; i++){ h_a[i] = float(rand() % 10 +1); } } void parallelConvolutionTiled1D() { float *d_N, *d_P; hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_P, sizeN); // copy data from host to device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); // Trasfeer data to constant memory hipMemcpyToSymbol(HIP_SYMBOL(c_M), h_M, sizeM); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAconvolution_1D_tiled<<<blocks, threads>>> (d_N, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&sharedMemTimer, start, stop); hipDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Shared-Constant Mem) : " << sharedMemTimer << " ms, " << sharedMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //printVector(h_P, n); hipFree(c_M); hipFree(d_N); hipFree(d_P); } void parallelConvolutionConstant1D(){ float *d_N, *d_P; hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_P, sizeN); // copy data from host to device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); // Trasfeer data to constant memory hipMemcpyToSymbol(HIP_SYMBOL(c_M), h_M, sizeM); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAConvolutionConstant1D<<<blocks, threads>>>(d_N, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&constantMemTimer, start, stop); hipDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Constant Mem) : " << constantMemTimer << " ms, " << constantMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //cout<< "Resulting P vector (Constant)" << endl; //printVector(h_P, n); hipFree(c_M); hipFree(d_N); hipFree(d_P); } void parallelConvolution1D(){ float *d_N, *d_M, *d_P; // Reservar memoria en device hipMalloc((void **)&d_N, sizeN); hipMalloc((void **)&d_M, sizeM); hipMalloc((void **)&d_P, sizeN); // Transferir datos de host a device hipMemcpy(d_N, h_N, sizeN, hipMemcpyHostToDevice); hipMemcpy(d_M, h_M, sizeM, hipMemcpyHostToDevice); // define timers hipEvent_t start, stop; // events to take time hipEventCreate(&start); hipEventCreate(&stop); // start timer hipEventRecord(start,0); //Launch kernel CUDAConvolution1D<<<blocks, threads>>>(d_N, d_M, d_P, m, n); hipEventRecord(stop,0); hipEventSynchronize(stop); hipEventElapsedTime(&globalMemTimer, start, stop); //cudaDeviceSynchronize(); cout<< "Elapsed parallel 1D convolution (Global Mem) : " << globalMemTimer << " ms, " << globalMemTimer / 1000 << " secs" <<endl; hipMemcpy(h_P, d_P, sizeN, hipMemcpyDeviceToHost); //cout<< "Resulting P vector (Global)" << endl; //printVector(h_P, n); //free(h_N); free(h_M); free(h_P); hipFree(d_M); hipFree(d_N); hipFree(d_P); }
.text .file "convolution_tiled.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 xorl %ebx, %ebx xorl %edi, %edi callq time movl %eax, %edi callq srand .p2align 4, 0x90 .LBB0_1: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, h_N(%rbx) addq $4, %rbx cmpq $399999996, %rbx # imm = 0x17D783FC jne .LBB0_1 # %bb.2: # %_Z14generateRandomPfi.exit xorl %edi, %edi callq time movl %eax, %edi callq srand movq $-39996, %rbx # imm = 0xFFFF63C4 .p2align 4, 0x90 .LBB0_3: # %.lr.ph.i1 # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, h_M+39996(%rbx) addq $4, %rbx jne .LBB0_3 # %bb.4: # %_Z14generateRandomPfi.exit5 callq _Z21parallelConvolution1Dv callq _Z29parallelConvolutionConstant1Dv callq _Z26parallelConvolutionTiled1Dv xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc # -- End function .globl _Z14generateRandomPfi # -- Begin function _Z14generateRandomPfi .p2align 4, 0x90 .type _Z14generateRandomPfi,@function _Z14generateRandomPfi: # @_Z14generateRandomPfi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %esi, %ebp movq %rdi, %rbx xorl %edi, %edi callq time movl %eax, %edi callq srand testl %ebp, %ebp jle .LBB1_3 # %bb.1: # %.lr.ph.preheader movl %ebp, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, (%rbx,%r15,4) incq %r15 cmpq %r15, %r14 jne .LBB1_2 .LBB1_3: # %._crit_edge addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z14generateRandomPfi, .Lfunc_end1-_Z14generateRandomPfi .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z21parallelConvolution1Dv .LCPI2_0: .long 0x447a0000 # float 1000 .text .globl _Z21parallelConvolution1Dv .p2align 4, 0x90 .type _Z21parallelConvolution1Dv,@function _Z21parallelConvolution1Dv: # @_Z21parallelConvolution1Dv .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $168, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq sizeN(%rip), %rsi leaq 32(%rsp), %rdi callq hipMalloc movq sizeM(%rip), %rsi leaq 24(%rsp), %rdi callq hipMalloc movq sizeN(%rip), %rsi leaq 16(%rsp), %rdi callq hipMalloc movq 32(%rsp), %rdi movq sizeN(%rip), %rdx movl $h_N, %esi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movq sizeM(%rip), %rdx movl $h_M, %esi movl $1, %ecx callq hipMemcpy leaq 48(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movq 48(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl blocks(%rip), %edi movl threads(%rip), %edx movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 120(%rsp) movq %rcx, 112(%rsp) movq %rdx, 104(%rsp) movl $9999, 44(%rsp) # imm = 0x270F movl $99999999, 40(%rsp) # imm = 0x5F5E0FF leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 44(%rsp), %rax movq %rax, 152(%rsp) leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z17CUDAConvolution1DPfS_S_ii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 48(%rsp), %rsi movq 8(%rsp), %rdx movl $globalMemTimer, %edi callq hipEventElapsedTime movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $47, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss globalMemTimer(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss globalMemTimer(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI2_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.2, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB2_7 # %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r14) je .LBB2_5 # %bb.4: movzbl 67(%r14), %eax jmp .LBB2_6 .LBB2_5: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rsi movq sizeN(%rip), %rdx movl $h_P, %edi movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree addq $168, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB2_7: .cfi_def_cfa_offset 192 callq _ZSt16__throw_bad_castv .Lfunc_end2: .size _Z21parallelConvolution1Dv, .Lfunc_end2-_Z21parallelConvolution1Dv .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z29parallelConvolutionConstant1Dv .LCPI3_0: .long 0x447a0000 # float 1000 .text .globl _Z29parallelConvolutionConstant1Dv .p2align 4, 0x90 .type _Z29parallelConvolutionConstant1Dv,@function _Z29parallelConvolutionConstant1Dv: # @_Z29parallelConvolutionConstant1Dv .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq sizeN(%rip), %rsi leaq 24(%rsp), %rdi callq hipMalloc movq sizeN(%rip), %rsi leaq 16(%rsp), %rdi callq hipMalloc movq 24(%rsp), %rdi movq sizeN(%rip), %rdx movl $h_N, %esi movl $1, %ecx callq hipMemcpy movq sizeM(%rip), %rdx movl $c_M, %edi movl $h_M, %esi xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol leaq 40(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movq 40(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl blocks(%rip), %edi movl threads(%rip), %edx movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movl $9999, 36(%rsp) # imm = 0x270F movl $99999999, 32(%rsp) # imm = 0x5F5E0FF leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z25CUDAConvolutionConstant1DPfS_ii, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_2: movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 40(%rsp), %rsi movq 8(%rsp), %rdx movl $constantMemTimer, %edi callq hipEventElapsedTime callq hipDeviceSynchronize movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $49, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss constantMemTimer(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss constantMemTimer(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI3_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.2, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB3_7 # %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r14) je .LBB3_5 # %bb.4: movzbl 67(%r14), %eax jmp .LBB3_6 .LBB3_5: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB3_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rsi movq sizeN(%rip), %rdx movl $h_P, %edi movl $2, %ecx callq hipMemcpy movl $c_M, %edi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB3_7: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end3: .size _Z29parallelConvolutionConstant1Dv, .Lfunc_end3-_Z29parallelConvolutionConstant1Dv .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z26parallelConvolutionTiled1Dv .LCPI4_0: .long 0x447a0000 # float 1000 .text .globl _Z26parallelConvolutionTiled1Dv .p2align 4, 0x90 .type _Z26parallelConvolutionTiled1Dv,@function _Z26parallelConvolutionTiled1Dv: # @_Z26parallelConvolutionTiled1Dv .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq sizeN(%rip), %rsi leaq 24(%rsp), %rdi callq hipMalloc movq sizeN(%rip), %rsi leaq 16(%rsp), %rdi callq hipMalloc movq 24(%rsp), %rdi movq sizeN(%rip), %rdx movl $h_N, %esi movl $1, %ecx callq hipMemcpy movq sizeM(%rip), %rdx movl $c_M, %edi movl $h_M, %esi xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol leaq 40(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movq 40(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl blocks(%rip), %edi movl threads(%rip), %edx movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movl $9999, 36(%rsp) # imm = 0x270F movl $99999999, 32(%rsp) # imm = 0x5F5E0FF leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z24CUDAconvolution_1D_tiledPfS_ii, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB4_2: movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 40(%rsp), %rsi movq 8(%rsp), %rdx movl $sharedMemTimer, %edi callq hipEventElapsedTime callq hipDeviceSynchronize movl $_ZSt4cout, %edi movl $.L.str, %esi movl $56, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss sharedMemTimer(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss sharedMemTimer(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI4_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.2, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB4_7 # %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r14) je .LBB4_5 # %bb.4: movzbl 67(%r14), %eax jmp .LBB4_6 .LBB4_5: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB4_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rsi movq sizeN(%rip), %rdx movl $h_P, %edi movl $2, %ecx callq hipMemcpy movl $c_M, %edi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB4_7: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end4: .size _Z26parallelConvolutionTiled1Dv, .Lfunc_end4-_Z26parallelConvolutionTiled1Dv .cfi_endproc # -- End function .globl _Z32__device_stub__CUDAConvolution1DPfS_S_ii # -- Begin function _Z32__device_stub__CUDAConvolution1DPfS_S_ii .p2align 4, 0x90 .type _Z32__device_stub__CUDAConvolution1DPfS_S_ii,@function _Z32__device_stub__CUDAConvolution1DPfS_S_ii: # @_Z32__device_stub__CUDAConvolution1DPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z17CUDAConvolution1DPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end5: .size _Z32__device_stub__CUDAConvolution1DPfS_S_ii, .Lfunc_end5-_Z32__device_stub__CUDAConvolution1DPfS_S_ii .cfi_endproc # -- End function .globl _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii # -- Begin function _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii .p2align 4, 0x90 .type _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii,@function _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii: # @_Z40__device_stub__CUDAConvolutionConstant1DPfS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z25CUDAConvolutionConstant1DPfS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end6: .size _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii, .Lfunc_end6-_Z40__device_stub__CUDAConvolutionConstant1DPfS_ii .cfi_endproc # -- End function .globl _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii # -- Begin function _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii .p2align 4, 0x90 .type _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii,@function _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii: # @_Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z24CUDAconvolution_1D_tiledPfS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end7: .size _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii, .Lfunc_end7-_Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _GLOBAL__sub_I_convolution_tiled.hip .LCPI8_0: .long 0x4cbebc20 # float 1.0E+8 .section .text.startup,"ax",@progbits .p2align 4, 0x90 .type _GLOBAL__sub_I_convolution_tiled.hip,@function _GLOBAL__sub_I_convolution_tiled.hip: # @_GLOBAL__sub_I_convolution_tiled.hip .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 cvtsi2ssl threads(%rip), %xmm1 movss .LCPI8_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %eax movl %eax, blocks(%rip) popq %rax .cfi_def_cfa_offset 8 retq .Lfunc_end8: .size _GLOBAL__sub_I_convolution_tiled.hip, .Lfunc_end8-_GLOBAL__sub_I_convolution_tiled.hip .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB9_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB9_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z17CUDAConvolution1DPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25CUDAConvolutionConstant1DPfS_ii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z24CUDAconvolution_1D_tiledPfS_ii, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $0, 8(%rsp) movl $1, (%rsp) movl $c_M, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movl $39996, %r9d # imm = 0x9C3C movq %rbx, %rdi xorl %r8d, %r8d callq __hipRegisterVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end9: .size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB10_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB10_2: retq .Lfunc_end10: .size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor .cfi_endproc # -- End function .type sizeN,@object # @sizeN .data .globl sizeN .p2align 3, 0x0 sizeN: .quad 399999996 # 0x17d783fc .size sizeN, 8 .type sizeM,@object # @sizeM .globl sizeM .p2align 3, 0x0 sizeM: .quad 39996 # 0x9c3c .size sizeM, 8 .type h_N,@object # @h_N .bss .globl h_N .p2align 4, 0x0 h_N: .zero 399999996 .size h_N, 399999996 .type h_M,@object # @h_M .globl h_M .p2align 4, 0x0 h_M: .zero 39996 .size h_M, 39996 .type h_P,@object # @h_P .globl h_P .p2align 4, 0x0 h_P: .zero 399999996 .size h_P, 399999996 .type threads,@object # @threads .data .globl threads .p2align 2, 0x0 threads: .long 1024 # 0x400 .size threads, 4 .type blocks,@object # @blocks .bss .globl blocks .p2align 2, 0x0 blocks: .long 0 # 0x0 .size blocks, 4 .type c_M,@object # @c_M .local c_M .comm c_M,39996,16 .type globalMemTimer,@object # @globalMemTimer .globl globalMemTimer .p2align 2, 0x0 globalMemTimer: .long 0x00000000 # float 0 .size globalMemTimer, 4 .type constantMemTimer,@object # @constantMemTimer .globl constantMemTimer .p2align 2, 0x0 constantMemTimer: .long 0x00000000 # float 0 .size constantMemTimer, 4 .type sharedMemTimer,@object # @sharedMemTimer .globl sharedMemTimer .p2align 2, 0x0 sharedMemTimer: .long 0x00000000 # float 0 .size sharedMemTimer, 4 .type _Z17CUDAConvolution1DPfS_S_ii,@object # @_Z17CUDAConvolution1DPfS_S_ii .section .rodata,"a",@progbits .globl _Z17CUDAConvolution1DPfS_S_ii .p2align 3, 0x0 _Z17CUDAConvolution1DPfS_S_ii: .quad _Z32__device_stub__CUDAConvolution1DPfS_S_ii .size _Z17CUDAConvolution1DPfS_S_ii, 8 .type _Z25CUDAConvolutionConstant1DPfS_ii,@object # @_Z25CUDAConvolutionConstant1DPfS_ii .globl _Z25CUDAConvolutionConstant1DPfS_ii .p2align 3, 0x0 _Z25CUDAConvolutionConstant1DPfS_ii: .quad _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii .size _Z25CUDAConvolutionConstant1DPfS_ii, 8 .type _Z24CUDAconvolution_1D_tiledPfS_ii,@object # @_Z24CUDAconvolution_1D_tiledPfS_ii .globl _Z24CUDAconvolution_1D_tiledPfS_ii .p2align 3, 0x0 _Z24CUDAconvolution_1D_tiledPfS_ii: .quad _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii .size _Z24CUDAconvolution_1D_tiledPfS_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Elapsed parallel 1D convolution (Shared-Constant Mem) : " .size .L.str, 57 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " ms, " .size .L.str.1, 6 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz " secs" .size .L.str.2, 6 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Elapsed parallel 1D convolution (Constant Mem) : " .size .L.str.3, 50 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Elapsed parallel 1D convolution (Global Mem) : " .size .L.str.4, 48 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z17CUDAConvolution1DPfS_S_ii" .size .L__unnamed_1, 30 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z25CUDAConvolutionConstant1DPfS_ii" .size .L__unnamed_2, 36 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z24CUDAconvolution_1D_tiledPfS_ii" .size .L__unnamed_3, 35 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "c_M" .size .L__unnamed_4, 4 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad _GLOBAL__sub_I_convolution_tiled.hip .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z32__device_stub__CUDAConvolution1DPfS_S_ii .addrsig_sym _Z40__device_stub__CUDAConvolutionConstant1DPfS_ii .addrsig_sym _Z39__device_stub__CUDAconvolution_1D_tiledPfS_ii .addrsig_sym _GLOBAL__sub_I_convolution_tiled.hip .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym h_N .addrsig_sym h_M .addrsig_sym h_P .addrsig_sym c_M .addrsig_sym globalMemTimer .addrsig_sym constantMemTimer .addrsig_sym sharedMemTimer .addrsig_sym _Z17CUDAConvolution1DPfS_S_ii .addrsig_sym _Z25CUDAConvolutionConstant1DPfS_ii .addrsig_sym _Z24CUDAconvolution_1D_tiledPfS_ii .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <math.h> #include <stdlib.h> #define err 0.00001 #define err2 0.000001 __device__ void f(float x, float *y) { // *y = exp(x)-5*pow(x,2); // slide *y = (pow(x, 2)*(2.1-0.5*x)/(pow(1-x, 2)*(1.1-0.5*x)))-13.616; // *y = tan(x) - x + 1; // 1.b // *y = 0.5*exp(x/3) - sin(x); // 1.c } __global__ void regula_falsi() { float x0,x1,x2,y0,y1,y2; // x0 = 0; x1 = 1; // slide x0 = -0.2; x1 = 1.2; // 1.a // x0 = 0; x1 = 3*M_PI; // 1.b // x0 = 0; x1 = 1; // 1.c printf("%10s %10s %10s %10s %10s %10s\n", "x0", "x1", "f(x0)", "f(x1)", "x2", "f(x2)"); do { f(x0, &y0); f(x1, &y1); x2=x1-((y1*(x1-x0))/(y1-y0)); f(x2, &y2); printf("%10.4f %10.4f %10.4f %10.4f %10.4f %10.4f\n", x0,x1,y0,y1,x2,y2); if(fabs(y2)<err2) { x0=x2; x1=x2; } else { if(y0*y2<0) x1=x2; else x0=x2; } } while(fabs(x0-x1)>err); printf("Hasil = %.5f\n",x2); } int main(int argc, char **argv) { regula_falsi<<<1, 1>>>(); cudaDeviceSynchronize(); return 0; }
.file "tmpxft_0019c267_00000000-6_regula-falsi.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z1ffPf .type _Z1ffPf, @function _Z1ffPf: .LFB2057: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z1ffPf, .-_Z1ffPf .globl _Z31__device_stub__Z12regula_falsivv .type _Z31__device_stub__Z12regula_falsivv, @function _Z31__device_stub__Z12regula_falsivv: .LFB2083: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 72(%rsp), %rax subq %fs:40, %rax jne .L10 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z12regula_falsiv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z31__device_stub__Z12regula_falsivv, .-_Z31__device_stub__Z12regula_falsivv .globl _Z12regula_falsiv .type _Z12regula_falsiv, @function _Z12regula_falsiv: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z12regula_falsivv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z12regula_falsiv, .-_Z12regula_falsiv .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L16 .L14: call cudaDeviceSynchronize@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state call _Z31__device_stub__Z12regula_falsivv jmp .L14 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12regula_falsiv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12regula_falsiv(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <math.h> #include <stdlib.h> #define err 0.00001 #define err2 0.000001 __device__ void f(float x, float *y) { // *y = exp(x)-5*pow(x,2); // slide *y = (pow(x, 2)*(2.1-0.5*x)/(pow(1-x, 2)*(1.1-0.5*x)))-13.616; // *y = tan(x) - x + 1; // 1.b // *y = 0.5*exp(x/3) - sin(x); // 1.c } __global__ void regula_falsi() { float x0,x1,x2,y0,y1,y2; // x0 = 0; x1 = 1; // slide x0 = -0.2; x1 = 1.2; // 1.a // x0 = 0; x1 = 3*M_PI; // 1.b // x0 = 0; x1 = 1; // 1.c printf("%10s %10s %10s %10s %10s %10s\n", "x0", "x1", "f(x0)", "f(x1)", "x2", "f(x2)"); do { f(x0, &y0); f(x1, &y1); x2=x1-((y1*(x1-x0))/(y1-y0)); f(x2, &y2); printf("%10.4f %10.4f %10.4f %10.4f %10.4f %10.4f\n", x0,x1,y0,y1,x2,y2); if(fabs(y2)<err2) { x0=x2; x1=x2; } else { if(y0*y2<0) x1=x2; else x0=x2; } } while(fabs(x0-x1)>err); printf("Hasil = %.5f\n",x2); } int main(int argc, char **argv) { regula_falsi<<<1, 1>>>(); cudaDeviceSynchronize(); return 0; }
#include <hip/hip_runtime.h> #include <stdio.h> #include <math.h> #include <stdlib.h> #define err 0.00001 #define err2 0.000001 __device__ void f(float x, float *y) { // *y = exp(x)-5*pow(x,2); // slide *y = (pow(x, 2)*(2.1-0.5*x)/(pow(1-x, 2)*(1.1-0.5*x)))-13.616; // *y = tan(x) - x + 1; // 1.b // *y = 0.5*exp(x/3) - sin(x); // 1.c } __global__ void regula_falsi() { float x0,x1,x2,y0,y1,y2; // x0 = 0; x1 = 1; // slide x0 = -0.2; x1 = 1.2; // 1.a // x0 = 0; x1 = 3*M_PI; // 1.b // x0 = 0; x1 = 1; // 1.c printf("%10s %10s %10s %10s %10s %10s\n", "x0", "x1", "f(x0)", "f(x1)", "x2", "f(x2)"); do { f(x0, &y0); f(x1, &y1); x2=x1-((y1*(x1-x0))/(y1-y0)); f(x2, &y2); printf("%10.4f %10.4f %10.4f %10.4f %10.4f %10.4f\n", x0,x1,y0,y1,x2,y2); if(fabs(y2)<err2) { x0=x2; x1=x2; } else { if(y0*y2<0) x1=x2; else x0=x2; } } while(fabs(x0-x1)>err); printf("Hasil = %.5f\n",x2); } int main(int argc, char **argv) { regula_falsi<<<1, 1>>>(); hipDeviceSynchronize(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <math.h> #include <stdlib.h> #define err 0.00001 #define err2 0.000001 __device__ void f(float x, float *y) { // *y = exp(x)-5*pow(x,2); // slide *y = (pow(x, 2)*(2.1-0.5*x)/(pow(1-x, 2)*(1.1-0.5*x)))-13.616; // *y = tan(x) - x + 1; // 1.b // *y = 0.5*exp(x/3) - sin(x); // 1.c } __global__ void regula_falsi() { float x0,x1,x2,y0,y1,y2; // x0 = 0; x1 = 1; // slide x0 = -0.2; x1 = 1.2; // 1.a // x0 = 0; x1 = 3*M_PI; // 1.b // x0 = 0; x1 = 1; // 1.c printf("%10s %10s %10s %10s %10s %10s\n", "x0", "x1", "f(x0)", "f(x1)", "x2", "f(x2)"); do { f(x0, &y0); f(x1, &y1); x2=x1-((y1*(x1-x0))/(y1-y0)); f(x2, &y2); printf("%10.4f %10.4f %10.4f %10.4f %10.4f %10.4f\n", x0,x1,y0,y1,x2,y2); if(fabs(y2)<err2) { x0=x2; x1=x2; } else { if(y0*y2<0) x1=x2; else x0=x2; } } while(fabs(x0-x1)>err); printf("Hasil = %.5f\n",x2); } int main(int argc, char **argv) { regula_falsi<<<1, 1>>>(); hipDeviceSynchronize(); return 0; }
.text .file "regula-falsi.hip" .globl _Z27__device_stub__regula_falsiv # -- Begin function _Z27__device_stub__regula_falsiv .p2align 4, 0x90 .type _Z27__device_stub__regula_falsiv,@function _Z27__device_stub__regula_falsiv: # @_Z27__device_stub__regula_falsiv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z12regula_falsiv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z27__device_stub__regula_falsiv, .Lfunc_end0-_Z27__device_stub__regula_falsiv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z12regula_falsiv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12regula_falsiv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z12regula_falsiv,@object # @_Z12regula_falsiv .section .rodata,"a",@progbits .globl _Z12regula_falsiv .p2align 3, 0x0 _Z12regula_falsiv: .quad _Z27__device_stub__regula_falsiv .size _Z12regula_falsiv, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12regula_falsiv" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__regula_falsiv .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12regula_falsiv .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0019c267_00000000-6_regula-falsi.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z1ffPf .type _Z1ffPf, @function _Z1ffPf: .LFB2057: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z1ffPf, .-_Z1ffPf .globl _Z31__device_stub__Z12regula_falsivv .type _Z31__device_stub__Z12regula_falsivv, @function _Z31__device_stub__Z12regula_falsivv: .LFB2083: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 72(%rsp), %rax subq %fs:40, %rax jne .L10 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z12regula_falsiv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z31__device_stub__Z12regula_falsivv, .-_Z31__device_stub__Z12regula_falsivv .globl _Z12regula_falsiv .type _Z12regula_falsiv, @function _Z12regula_falsiv: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z12regula_falsivv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z12regula_falsiv, .-_Z12regula_falsiv .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L16 .L14: call cudaDeviceSynchronize@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state call _Z31__device_stub__Z12regula_falsivv jmp .L14 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12regula_falsiv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12regula_falsiv(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "regula-falsi.hip" .globl _Z27__device_stub__regula_falsiv # -- Begin function _Z27__device_stub__regula_falsiv .p2align 4, 0x90 .type _Z27__device_stub__regula_falsiv,@function _Z27__device_stub__regula_falsiv: # @_Z27__device_stub__regula_falsiv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z12regula_falsiv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z27__device_stub__regula_falsiv, .Lfunc_end0-_Z27__device_stub__regula_falsiv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z12regula_falsiv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12regula_falsiv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z12regula_falsiv,@object # @_Z12regula_falsiv .section .rodata,"a",@progbits .globl _Z12regula_falsiv .p2align 3, 0x0 _Z12regula_falsiv: .quad _Z27__device_stub__regula_falsiv .size _Z12regula_falsiv, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12regula_falsiv" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__regula_falsiv .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12regula_falsiv .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void sigmoidKernel(float* input, float* output, int edge) { KERNEL_POSITION; output[position] = 1 / (1 + exp(-input[position])); }
code for sm_80 Function : _Z13sigmoidKernelPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fc800078e0203 */ /*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fcc00078e0205 */ /*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0080*/ HFMA2.MMA R7, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff077435 */ /* 0x000fe200000001ff */ /*0090*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */ /* 0x000fe200078e00ff */ /*00a0*/ BSSY B0, 0x1f0 ; /* 0x0000014000007945 */ /* 0x000fe60003800000 */ /*00b0*/ FFMA.SAT R4, -R2, R5, 0.5 ; /* 0x3f00000002047423 */ /* 0x004fca0000002105 */ /*00c0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */ /* 0x000fc80000004007 */ /*00d0*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */ /* 0x040fe40000000000 */ /*00e0*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */ /* 0x000fe400078e00ff */ /*00f0*/ FFMA R5, -R2, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b02057823 */ /* 0x000fc80000000905 */ /*0100*/ FFMA R5, -R2, 1.925963033500011079e-08, R5 ; /* 0x32a5706002057823 */ /* 0x000fcc0000000105 */ /*0110*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */ /* 0x000e240000000800 */ /*0120*/ FFMA R4, R4, R5, 1 ; /* 0x3f80000004047423 */ /* 0x001fca0000000005 */ /*0130*/ IADD3 R2, R4, 0x1800000, RZ ; /* 0x0180000004027810 */ /* 0x000fc80007ffe0ff */ /*0140*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */ /* 0x000fc800078ec0ff */ /*0150*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */ /* 0x000fda0003f04070 */ /*0160*/ @P0 BRA 0x1a0 ; /* 0x0000003000000947 */ /* 0x000fea0003800000 */ /*0170*/ MOV R2, 0x190 ; /* 0x0000019000027802 */ /* 0x000fe40000000f00 */ /*0180*/ CALL.REL.NOINC 0x230 ; /* 0x000000a000007944 */ /* 0x000fea0003c00000 */ /*0190*/ BRA 0x1e0 ; /* 0x0000004000007947 */ /* 0x000fea0003800000 */ /*01a0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */ /* 0x000e240000001000 */ /*01b0*/ FFMA R2, R4, R5, -1 ; /* 0xbf80000004027423 */ /* 0x001fc80000000005 */ /*01c0*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */ /* 0x000fc80000010100 */ /*01d0*/ FFMA R5, R5, R2, R5 ; /* 0x0000000205057223 */ /* 0x000fe40000000005 */ /*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fc800078e00ff */ /*0200*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0203 */ /*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe2000c101904 */ /*0220*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0230*/ SHF.L.U32 R3, R4, 0x1, RZ ; /* 0x0000000104037819 */ /* 0x000fe200000006ff */ /*0240*/ BSSY B1, 0x550 ; /* 0x0000030000017945 */ /* 0x000fe60003800000 */ /*0250*/ SHF.R.U32.HI R3, RZ, 0x18, R3 ; /* 0x00000018ff037819 */ /* 0x000fc80000011603 */ /*0260*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f05070 */ /*0270*/ @P0 BRA 0x320 ; /* 0x000000a000000947 */ /* 0x000fea0003800000 */ /*0280*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */ /* 0x000fca00078e00ff */ /*0290*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f05270 */ /*02a0*/ @P0 FFMA R5, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004050823 */ /* 0x000fe200000000ff */ /*02b0*/ @!P0 MUFU.RCP R3, R4 ; /* 0x0000000400038308 */ /* 0x000ff00000001000 */ /*02c0*/ @P0 MUFU.RCP R6, R5 ; /* 0x0000000500060308 */ /* 0x000e240000001000 */ /*02d0*/ @P0 FFMA R7, R5, R6, -1 ; /* 0xbf80000005070423 */ /* 0x001fc80000000006 */ /*02e0*/ @P0 FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07070221 */ /* 0x000fc80000010100 */ /*02f0*/ @P0 FFMA R7, R6, R7, R6 ; /* 0x0000000706070223 */ /* 0x000fc80000000006 */ /*0300*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */ /* 0x000fe200000000ff */ /*0310*/ BRA 0x540 ; /* 0x0000022000007947 */ /* 0x000fea0003800000 */ /*0320*/ IADD3 R5, R3, -0xfd, RZ ; /* 0xffffff0303057810 */ /* 0x000fc80007ffe0ff */ /*0330*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */ /* 0x000fda0003f04070 */ /*0340*/ @P0 BRA 0x530 ; /* 0x000001e000000947 */ /* 0x000fea0003800000 */ /*0350*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */ /* 0x000fe200078ec0ff */ /*0360*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */ /* 0x000fe200078e00ff */ /*0370*/ IADD3 R3, R3, -0xfc, RZ ; /* 0xffffff0403037810 */ /* 0x000fe40007ffe0ff */ /*0380*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */ /* 0x000fe400078efcff */ /*0390*/ SHF.L.U32 R11, R10, R5, RZ ; /* 0x000000050a0b7219 */ /* 0x000fe400000006ff */ /*03a0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */ /* 0x000e240000001000 */ /*03b0*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */ /* 0x001fc80000000007 */ /*03c0*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */ /* 0x000fc80000010100 */ /*03d0*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */ /* 0x1c0fe40000004007 */ /*03e0*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */ /* 0x000fc60000008007 */ /*03f0*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */ /* 0x040fe400078ec0ff */ /*0400*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */ /* 0x000fe40003f1d000 */ /*0410*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */ /* 0x000fe400078efcff */ /*0420*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */ /* 0x000fe40004000000 */ /*0430*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */ /* 0x000fe400078ec0ff */ /*0440*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */ /* 0x000fc40007ffe1ff */ /*0450*/ SHF.R.U32.HI R6, RZ, R5.reuse, R6 ; /* 0x00000005ff067219 */ /* 0x080fe40000011606 */ /*0460*/ LOP3.LUT P1, RZ, R7, R5, R8.reuse, 0xf8, !PT ; /* 0x0000000507ff7212 */ /* 0x100fe4000782f808 */ /*0470*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */ /* 0x040fe4000780c0ff */ /*0480*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */ /* 0x000fe4000784c0ff */ /*0490*/ SHF.R.U32.HI R3, RZ, R3, R8 ; /* 0x00000003ff037219 */ /* 0x000fe40000011608 */ /*04a0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40000703c20 */ /*04b0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */ /* 0x000fe4000782c0ff */ /*04c0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */ /* 0x000fca0004000000 */ /*04d0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */ /* 0x000fca00078e0a05 */ /*04e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f06270 */ /*04f0*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */ /* 0x000fca0007ffe0ff */ /*0500*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */ /* 0x000fca00078e00ff */ /*0510*/ LOP3.LUT R3, R3, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000003037812 */ /* 0x000fe200078ef804 */ /*0520*/ BRA 0x540 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*0530*/ MUFU.RCP R3, R4 ; /* 0x0000000400037308 */ /* 0x0000640000001000 */ /*0540*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0550*/ MOV R5, R3 ; /* 0x0000000300057202 */ /* 0x002fe20000000f00 */ /*0560*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */ /* 0x000fc800078e00ff */ /*0570*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa8002007950 */ /* 0x000fea0003c3ffff */ /*0580*/ BRA 0x580; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0590*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0600*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0610*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0620*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0630*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0640*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0650*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0660*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0670*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void sigmoidKernel(float* input, float* output, int edge) { KERNEL_POSITION; output[position] = 1 / (1 + exp(-input[position])); }
.file "tmpxft_000e4b3f_00000000-6_sigmoidKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i .type _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i, @function _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13sigmoidKernelPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i, .-_Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i .globl _Z13sigmoidKernelPfS_i .type _Z13sigmoidKernelPfS_i, @function _Z13sigmoidKernelPfS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z13sigmoidKernelPfS_i, .-_Z13sigmoidKernelPfS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z13sigmoidKernelPfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z13sigmoidKernelPfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void sigmoidKernel(float* input, float* output, int edge) { KERNEL_POSITION; output[position] = 1 / (1 + exp(-input[position])); }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void sigmoidKernel(float* input, float* output, int edge) { KERNEL_POSITION; output[position] = 1 / (1 + exp(-input[position])); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void sigmoidKernel(float* input, float* output, int edge) { KERNEL_POSITION; output[position] = 1 / (1 + exp(-input[position])); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13sigmoidKernelPfS_i .globl _Z13sigmoidKernelPfS_i .p2align 8 .type _Z13sigmoidKernelPfS_i,@function _Z13sigmoidKernelPfS_i: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_mul_f32_e32 v3, 0xbfb8aa3b, v2 v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2 v_fma_f32 v4, v2, 0xbfb8aa3b, -v3 v_rndne_f32_e32 v5, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5 v_add_f32_e32 v3, v3, v4 v_cvt_i32_f32_e32 v4, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_exp_f32_e32 v3, v3 s_waitcnt_depctr 0xfff v_ldexp_f32 v3, v3, v4 v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo v_add_f32_e32 v2, 1.0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v3, null, v2, v2, 1.0 v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0 v_rcp_f32_e32 v4, v3 s_waitcnt_depctr 0xfff v_fma_f32 v5, -v3, v4, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v4, v5, v4 v_mul_f32_e32 v5, v6, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v7, -v3, v5, v6 v_fmac_f32_e32 v5, v7, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v3, -v3, v5, v6 v_div_fmas_f32 v3, v3, v4, v5 v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_div_fixup_f32 v2, v3, v2, 1.0 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13sigmoidKernelPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13sigmoidKernelPfS_i, .Lfunc_end0-_Z13sigmoidKernelPfS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13sigmoidKernelPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13sigmoidKernelPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void sigmoidKernel(float* input, float* output, int edge) { KERNEL_POSITION; output[position] = 1 / (1 + exp(-input[position])); }
.text .file "sigmoidKernel.hip" .globl _Z28__device_stub__sigmoidKernelPfS_i # -- Begin function _Z28__device_stub__sigmoidKernelPfS_i .p2align 4, 0x90 .type _Z28__device_stub__sigmoidKernelPfS_i,@function _Z28__device_stub__sigmoidKernelPfS_i: # @_Z28__device_stub__sigmoidKernelPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13sigmoidKernelPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z28__device_stub__sigmoidKernelPfS_i, .Lfunc_end0-_Z28__device_stub__sigmoidKernelPfS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13sigmoidKernelPfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z13sigmoidKernelPfS_i,@object # @_Z13sigmoidKernelPfS_i .section .rodata,"a",@progbits .globl _Z13sigmoidKernelPfS_i .p2align 3, 0x0 _Z13sigmoidKernelPfS_i: .quad _Z28__device_stub__sigmoidKernelPfS_i .size _Z13sigmoidKernelPfS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13sigmoidKernelPfS_i" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__sigmoidKernelPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13sigmoidKernelPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z13sigmoidKernelPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fc800078e0203 */ /*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fcc00078e0205 */ /*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0080*/ HFMA2.MMA R7, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff077435 */ /* 0x000fe200000001ff */ /*0090*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */ /* 0x000fe200078e00ff */ /*00a0*/ BSSY B0, 0x1f0 ; /* 0x0000014000007945 */ /* 0x000fe60003800000 */ /*00b0*/ FFMA.SAT R4, -R2, R5, 0.5 ; /* 0x3f00000002047423 */ /* 0x004fca0000002105 */ /*00c0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */ /* 0x000fc80000004007 */ /*00d0*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */ /* 0x040fe40000000000 */ /*00e0*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */ /* 0x000fe400078e00ff */ /*00f0*/ FFMA R5, -R2, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b02057823 */ /* 0x000fc80000000905 */ /*0100*/ FFMA R5, -R2, 1.925963033500011079e-08, R5 ; /* 0x32a5706002057823 */ /* 0x000fcc0000000105 */ /*0110*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */ /* 0x000e240000000800 */ /*0120*/ FFMA R4, R4, R5, 1 ; /* 0x3f80000004047423 */ /* 0x001fca0000000005 */ /*0130*/ IADD3 R2, R4, 0x1800000, RZ ; /* 0x0180000004027810 */ /* 0x000fc80007ffe0ff */ /*0140*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */ /* 0x000fc800078ec0ff */ /*0150*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */ /* 0x000fda0003f04070 */ /*0160*/ @P0 BRA 0x1a0 ; /* 0x0000003000000947 */ /* 0x000fea0003800000 */ /*0170*/ MOV R2, 0x190 ; /* 0x0000019000027802 */ /* 0x000fe40000000f00 */ /*0180*/ CALL.REL.NOINC 0x230 ; /* 0x000000a000007944 */ /* 0x000fea0003c00000 */ /*0190*/ BRA 0x1e0 ; /* 0x0000004000007947 */ /* 0x000fea0003800000 */ /*01a0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */ /* 0x000e240000001000 */ /*01b0*/ FFMA R2, R4, R5, -1 ; /* 0xbf80000004027423 */ /* 0x001fc80000000005 */ /*01c0*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */ /* 0x000fc80000010100 */ /*01d0*/ FFMA R5, R5, R2, R5 ; /* 0x0000000205057223 */ /* 0x000fe40000000005 */ /*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fc800078e00ff */ /*0200*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0203 */ /*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe2000c101904 */ /*0220*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0230*/ SHF.L.U32 R3, R4, 0x1, RZ ; /* 0x0000000104037819 */ /* 0x000fe200000006ff */ /*0240*/ BSSY B1, 0x550 ; /* 0x0000030000017945 */ /* 0x000fe60003800000 */ /*0250*/ SHF.R.U32.HI R3, RZ, 0x18, R3 ; /* 0x00000018ff037819 */ /* 0x000fc80000011603 */ /*0260*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f05070 */ /*0270*/ @P0 BRA 0x320 ; /* 0x000000a000000947 */ /* 0x000fea0003800000 */ /*0280*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */ /* 0x000fca00078e00ff */ /*0290*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f05270 */ /*02a0*/ @P0 FFMA R5, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004050823 */ /* 0x000fe200000000ff */ /*02b0*/ @!P0 MUFU.RCP R3, R4 ; /* 0x0000000400038308 */ /* 0x000ff00000001000 */ /*02c0*/ @P0 MUFU.RCP R6, R5 ; /* 0x0000000500060308 */ /* 0x000e240000001000 */ /*02d0*/ @P0 FFMA R7, R5, R6, -1 ; /* 0xbf80000005070423 */ /* 0x001fc80000000006 */ /*02e0*/ @P0 FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07070221 */ /* 0x000fc80000010100 */ /*02f0*/ @P0 FFMA R7, R6, R7, R6 ; /* 0x0000000706070223 */ /* 0x000fc80000000006 */ /*0300*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */ /* 0x000fe200000000ff */ /*0310*/ BRA 0x540 ; /* 0x0000022000007947 */ /* 0x000fea0003800000 */ /*0320*/ IADD3 R5, R3, -0xfd, RZ ; /* 0xffffff0303057810 */ /* 0x000fc80007ffe0ff */ /*0330*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */ /* 0x000fda0003f04070 */ /*0340*/ @P0 BRA 0x530 ; /* 0x000001e000000947 */ /* 0x000fea0003800000 */ /*0350*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */ /* 0x000fe200078ec0ff */ /*0360*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */ /* 0x000fe200078e00ff */ /*0370*/ IADD3 R3, R3, -0xfc, RZ ; /* 0xffffff0403037810 */ /* 0x000fe40007ffe0ff */ /*0380*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */ /* 0x000fe400078efcff */ /*0390*/ SHF.L.U32 R11, R10, R5, RZ ; /* 0x000000050a0b7219 */ /* 0x000fe400000006ff */ /*03a0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */ /* 0x000e240000001000 */ /*03b0*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */ /* 0x001fc80000000007 */ /*03c0*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */ /* 0x000fc80000010100 */ /*03d0*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */ /* 0x1c0fe40000004007 */ /*03e0*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */ /* 0x000fc60000008007 */ /*03f0*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */ /* 0x040fe400078ec0ff */ /*0400*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */ /* 0x000fe40003f1d000 */ /*0410*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */ /* 0x000fe400078efcff */ /*0420*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */ /* 0x000fe40004000000 */ /*0430*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */ /* 0x000fe400078ec0ff */ /*0440*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */ /* 0x000fc40007ffe1ff */ /*0450*/ SHF.R.U32.HI R6, RZ, R5.reuse, R6 ; /* 0x00000005ff067219 */ /* 0x080fe40000011606 */ /*0460*/ LOP3.LUT P1, RZ, R7, R5, R8.reuse, 0xf8, !PT ; /* 0x0000000507ff7212 */ /* 0x100fe4000782f808 */ /*0470*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */ /* 0x040fe4000780c0ff */ /*0480*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */ /* 0x000fe4000784c0ff */ /*0490*/ SHF.R.U32.HI R3, RZ, R3, R8 ; /* 0x00000003ff037219 */ /* 0x000fe40000011608 */ /*04a0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40000703c20 */ /*04b0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */ /* 0x000fe4000782c0ff */ /*04c0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */ /* 0x000fca0004000000 */ /*04d0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */ /* 0x000fca00078e0a05 */ /*04e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f06270 */ /*04f0*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */ /* 0x000fca0007ffe0ff */ /*0500*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */ /* 0x000fca00078e00ff */ /*0510*/ LOP3.LUT R3, R3, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000003037812 */ /* 0x000fe200078ef804 */ /*0520*/ BRA 0x540 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*0530*/ MUFU.RCP R3, R4 ; /* 0x0000000400037308 */ /* 0x0000640000001000 */ /*0540*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0550*/ MOV R5, R3 ; /* 0x0000000300057202 */ /* 0x002fe20000000f00 */ /*0560*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */ /* 0x000fc800078e00ff */ /*0570*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa8002007950 */ /* 0x000fea0003c3ffff */ /*0580*/ BRA 0x580; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0590*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*05f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0600*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0610*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0620*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0630*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0640*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0650*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0660*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0670*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13sigmoidKernelPfS_i .globl _Z13sigmoidKernelPfS_i .p2align 8 .type _Z13sigmoidKernelPfS_i,@function _Z13sigmoidKernelPfS_i: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_mul_f32_e32 v3, 0xbfb8aa3b, v2 v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2 v_fma_f32 v4, v2, 0xbfb8aa3b, -v3 v_rndne_f32_e32 v5, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5 v_add_f32_e32 v3, v3, v4 v_cvt_i32_f32_e32 v4, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_exp_f32_e32 v3, v3 s_waitcnt_depctr 0xfff v_ldexp_f32 v3, v3, v4 v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo v_add_f32_e32 v2, 1.0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v3, null, v2, v2, 1.0 v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0 v_rcp_f32_e32 v4, v3 s_waitcnt_depctr 0xfff v_fma_f32 v5, -v3, v4, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v4, v5, v4 v_mul_f32_e32 v5, v6, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v7, -v3, v5, v6 v_fmac_f32_e32 v5, v7, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v3, -v3, v5, v6 v_div_fmas_f32 v3, v3, v4, v5 v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_div_fixup_f32 v2, v3, v2, 1.0 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13sigmoidKernelPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13sigmoidKernelPfS_i, .Lfunc_end0-_Z13sigmoidKernelPfS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13sigmoidKernelPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13sigmoidKernelPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000e4b3f_00000000-6_sigmoidKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i .type _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i, @function _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13sigmoidKernelPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i, .-_Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i .globl _Z13sigmoidKernelPfS_i .type _Z13sigmoidKernelPfS_i, @function _Z13sigmoidKernelPfS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z13sigmoidKernelPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z13sigmoidKernelPfS_i, .-_Z13sigmoidKernelPfS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z13sigmoidKernelPfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z13sigmoidKernelPfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "sigmoidKernel.hip" .globl _Z28__device_stub__sigmoidKernelPfS_i # -- Begin function _Z28__device_stub__sigmoidKernelPfS_i .p2align 4, 0x90 .type _Z28__device_stub__sigmoidKernelPfS_i,@function _Z28__device_stub__sigmoidKernelPfS_i: # @_Z28__device_stub__sigmoidKernelPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13sigmoidKernelPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z28__device_stub__sigmoidKernelPfS_i, .Lfunc_end0-_Z28__device_stub__sigmoidKernelPfS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13sigmoidKernelPfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z13sigmoidKernelPfS_i,@object # @_Z13sigmoidKernelPfS_i .section .rodata,"a",@progbits .globl _Z13sigmoidKernelPfS_i .p2align 3, 0x0 _Z13sigmoidKernelPfS_i: .quad _Z28__device_stub__sigmoidKernelPfS_i .size _Z13sigmoidKernelPfS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13sigmoidKernelPfS_i" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__sigmoidKernelPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13sigmoidKernelPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include<iostream> #include<cuda_runtime.h> int main(void) { cudaDeviceProp prop; int count; cudaGetDeviceCount(&count); for (int i = 0; i < count; i++) { cudaGetDeviceProperties(&prop, i); } return 0; }
code for sm_80
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include<iostream> #include<cuda_runtime.h> int main(void) { cudaDeviceProp prop; int count; cudaGetDeviceCount(&count); for (int i = 0; i < count; i++) { cudaGetDeviceProperties(&prop, i); } return 0; }
.file "tmpxft_000ddd1a_00000000-6_File1.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $1064, %rsp .cfi_def_cfa_offset 1088 movq %fs:40, %rax movq %rax, 1048(%rsp) xorl %eax, %eax leaq 12(%rsp), %rdi call cudaGetDeviceCount@PLT cmpl $0, 12(%rsp) jle .L4 movl $0, %ebx leaq 16(%rsp), %rbp .L5: movl %ebx, %esi movq %rbp, %rdi call cudaGetDeviceProperties_v2@PLT addl $1, %ebx cmpl %ebx, 12(%rsp) jg .L5 .L4: movq 1048(%rsp), %rax subq %fs:40, %rax jne .L9 movl $0, %eax addq $1064, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include<iostream> #include<cuda_runtime.h> int main(void) { cudaDeviceProp prop; int count; cudaGetDeviceCount(&count); for (int i = 0; i < count; i++) { cudaGetDeviceProperties(&prop, i); } return 0; }
#include<iostream> #include<hip/hip_runtime.h> int main(void) { hipDeviceProp_t prop; int count; hipGetDeviceCount(&count); for (int i = 0; i < count; i++) { hipGetDeviceProperties(&prop, i); } return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include<iostream> #include<hip/hip_runtime.h> int main(void) { hipDeviceProp_t prop; int count; hipGetDeviceCount(&count); for (int i = 0; i < count; i++) { hipGetDeviceProperties(&prop, i); } return 0; }
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include<iostream> #include<hip/hip_runtime.h> int main(void) { hipDeviceProp_t prop; int count; hipGetDeviceCount(&count); for (int i = 0; i < count; i++) { hipGetDeviceProperties(&prop, i); } return 0; }
.text .file "File1.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 1504 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 4(%rsp), %rdi callq hipGetDeviceCount cmpl $0, 4(%rsp) jle .LBB0_3 # %bb.1: # %.lr.ph.preheader xorl %ebx, %ebx leaq 8(%rsp), %r14 .p2align 4, 0x90 .LBB0_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl %ebx, %esi callq hipGetDevicePropertiesR0600 incl %ebx cmpl 4(%rsp), %ebx jl .LBB0_2 .LBB0_3: # %._crit_edge xorl %eax, %eax addq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000ddd1a_00000000-6_File1.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $1064, %rsp .cfi_def_cfa_offset 1088 movq %fs:40, %rax movq %rax, 1048(%rsp) xorl %eax, %eax leaq 12(%rsp), %rdi call cudaGetDeviceCount@PLT cmpl $0, 12(%rsp) jle .L4 movl $0, %ebx leaq 16(%rsp), %rbp .L5: movl %ebx, %esi movq %rbp, %rdi call cudaGetDeviceProperties_v2@PLT addl $1, %ebx cmpl %ebx, 12(%rsp) jg .L5 .L4: movq 1048(%rsp), %rax subq %fs:40, %rax jne .L9 movl $0, %eax addq $1064, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "File1.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 1504 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 4(%rsp), %rdi callq hipGetDeviceCount cmpl $0, 4(%rsp) jle .LBB0_3 # %bb.1: # %.lr.ph.preheader xorl %ebx, %ebx leaq 8(%rsp), %r14 .p2align 4, 0x90 .LBB0_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl %ebx, %esi callq hipGetDevicePropertiesR0600 incl %ebx cmpl 4(%rsp), %ebx jl .LBB0_2 .LBB0_3: # %._crit_edge xorl %eax, %eax addq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
/** * Copyright 2019 Matthew Oliver * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include <cstdint> __device__ __forceinline__ float clamp(const float f, const float a, const float b) { return fmaxf(a, fminf(f, b)); } __device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv) { // Get YCbCr values const float luma = static_cast<float>(yuv.x); const float chromaCb = static_cast<float>(yuv.y) - 128.0f; const float chromaCr = static_cast<float>(yuv.z) - 128.0f; // Convert to RGB using BT601 return make_float3( luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb); } struct Pixel2 { float3 m_pixels[2]; }; struct NV12Planes { uint8_t* m_plane1; uint8_t* m_plane2; }; template<typename T> struct RGBPlanes { T* m_plane1; T* m_plane2; T* m_plane3; }; __device__ __forceinline__ Pixel2 getNV12ToRGB( const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep) { // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved // There are 1 U+V sample for every 2x2 Y block // Y1 Y2 Y3 Y4 Y5 Y5 // Y7 Y8 Y9 Y10 Y11 Y12 // Y13 Y14 Y15 Y16 Y17 Y18 // Y19 Y20 Y21 Y22 Y23 Y24 // // U1 V1 U2 V2 U2 V3 // U4 V4 U5 V5 U6 V6 // // UV1 is used for Y1 Y2 Y7 Y8 // UV2 is used for Y3 Y4 Y9 Y10 // UV4 is used for Y13 Y14 Y19 Y20 // etc. // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows // To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4 // This replaces 2 Y loads at a time with 2 UV loads for each 2xY row uchar3 yuvi[2]; const uint32_t sourceOffset = y * sourceStep + x; yuvi[0].x = source.m_plane1[sourceOffset]; yuvi[1].x = source.m_plane1[sourceOffset + 1]; const uint32_t chromaOffset = y >> 1; const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x; const uint8_t chromaCb = source.m_plane2[chromaSourceOffset]; const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1]; // This doesn't perform any chroma interpolation, this feature would need to be added later if needed yuvi[0].y = chromaCb; yuvi[0].z = chromaCr; yuvi[1].y = chromaCb; yuvi[1].z = chromaCr; Pixel2 rgb; rgb.m_pixels[0] = YUVToRGB(yuvi[0]); rgb.m_pixels[1] = YUVToRGB(yuvi[1]); return rgb; } template<typename T> class UpPack { public: typedef float3 Type; }; template<> class UpPack<uint8_t> { public: typedef uchar3 Type; }; template<typename T> __device__ __forceinline__ T getRGB(const float3 pixel) { // Normalise float values return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f)); } template<> __device__ __forceinline__ uchar3 getRGB(const float3 pixel) { return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f)); } template<typename T> __device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep) { const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1); const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y; if (x >= width - 1 || y >= height) { return; } Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep); const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]); const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]); const uint32_t destOffset = y * destStep + x; dest.m_plane1[destOffset] = pixel1.x; dest.m_plane1[destOffset + 1] = pixel2.x; dest.m_plane2[destOffset] = pixel1.y; dest.m_plane2[destOffset + 1] = pixel2.y; dest.m_plane3[destOffset] = pixel1.z; dest.m_plane3[destOffset + 1] = pixel2.z; } extern "C" { __global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep) { convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep); } __global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep) { convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float)); } }
.file "tmpxft_0000b906_00000000-6_FFFRFormatConvert.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2035: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2035: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj .type _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj, @function _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj: .LFB2057: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %esi, 12(%rsp) movl %edx, 8(%rsp) movl %ecx, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movq %rdi, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %r8, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 168 pushq 24(%rsp) .cfi_def_cfa_offset 176 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq convertNV12ToRGB8P(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj, .-_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj .globl convertNV12ToRGB8P .type convertNV12ToRGB8P, @function convertNV12ToRGB8P: .LFB2058: .cfi_startproc endbr64 subq $24, %rsp .cfi_def_cfa_offset 32 movq %rdi, (%rsp) movq %rsi, 8(%rsp) movl %edx, %esi movl %ecx, %edx movl %r8d, %ecx movq %rsp, %rdi leaq 32(%rsp), %r8 call _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size convertNV12ToRGB8P, .-convertNV12ToRGB8P .globl _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj .type _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj, @function _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj: .LFB2059: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %esi, 12(%rsp) movl %edx, 8(%rsp) movl %ecx, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movq %rdi, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %r8, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 168 pushq 24(%rsp) .cfi_def_cfa_offset 176 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq convertNV12ToRGB32FP(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj, .-_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj .globl convertNV12ToRGB32FP .type convertNV12ToRGB32FP, @function convertNV12ToRGB32FP: .LFB2060: .cfi_startproc endbr64 subq $24, %rsp .cfi_def_cfa_offset 32 movq %rdi, (%rsp) movq %rsi, 8(%rsp) movl %edx, %esi movl %ecx, %edx movl %r8d, %ecx movq %rsp, %rdi leaq 32(%rsp), %r8 call _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size convertNV12ToRGB32FP, .-convertNV12ToRGB32FP .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "convertNV12ToRGB32FP" .LC1: .string "convertNV12ToRGB8P" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2062: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq convertNV12ToRGB32FP(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq convertNV12ToRGB8P(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/** * Copyright 2019 Matthew Oliver * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include <cstdint> __device__ __forceinline__ float clamp(const float f, const float a, const float b) { return fmaxf(a, fminf(f, b)); } __device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv) { // Get YCbCr values const float luma = static_cast<float>(yuv.x); const float chromaCb = static_cast<float>(yuv.y) - 128.0f; const float chromaCr = static_cast<float>(yuv.z) - 128.0f; // Convert to RGB using BT601 return make_float3( luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb); } struct Pixel2 { float3 m_pixels[2]; }; struct NV12Planes { uint8_t* m_plane1; uint8_t* m_plane2; }; template<typename T> struct RGBPlanes { T* m_plane1; T* m_plane2; T* m_plane3; }; __device__ __forceinline__ Pixel2 getNV12ToRGB( const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep) { // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved // There are 1 U+V sample for every 2x2 Y block // Y1 Y2 Y3 Y4 Y5 Y5 // Y7 Y8 Y9 Y10 Y11 Y12 // Y13 Y14 Y15 Y16 Y17 Y18 // Y19 Y20 Y21 Y22 Y23 Y24 // // U1 V1 U2 V2 U2 V3 // U4 V4 U5 V5 U6 V6 // // UV1 is used for Y1 Y2 Y7 Y8 // UV2 is used for Y3 Y4 Y9 Y10 // UV4 is used for Y13 Y14 Y19 Y20 // etc. // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows // To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4 // This replaces 2 Y loads at a time with 2 UV loads for each 2xY row uchar3 yuvi[2]; const uint32_t sourceOffset = y * sourceStep + x; yuvi[0].x = source.m_plane1[sourceOffset]; yuvi[1].x = source.m_plane1[sourceOffset + 1]; const uint32_t chromaOffset = y >> 1; const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x; const uint8_t chromaCb = source.m_plane2[chromaSourceOffset]; const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1]; // This doesn't perform any chroma interpolation, this feature would need to be added later if needed yuvi[0].y = chromaCb; yuvi[0].z = chromaCr; yuvi[1].y = chromaCb; yuvi[1].z = chromaCr; Pixel2 rgb; rgb.m_pixels[0] = YUVToRGB(yuvi[0]); rgb.m_pixels[1] = YUVToRGB(yuvi[1]); return rgb; } template<typename T> class UpPack { public: typedef float3 Type; }; template<> class UpPack<uint8_t> { public: typedef uchar3 Type; }; template<typename T> __device__ __forceinline__ T getRGB(const float3 pixel) { // Normalise float values return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f)); } template<> __device__ __forceinline__ uchar3 getRGB(const float3 pixel) { return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f)); } template<typename T> __device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep) { const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1); const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y; if (x >= width - 1 || y >= height) { return; } Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep); const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]); const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]); const uint32_t destOffset = y * destStep + x; dest.m_plane1[destOffset] = pixel1.x; dest.m_plane1[destOffset + 1] = pixel2.x; dest.m_plane2[destOffset] = pixel1.y; dest.m_plane2[destOffset + 1] = pixel2.y; dest.m_plane3[destOffset] = pixel1.z; dest.m_plane3[destOffset + 1] = pixel2.z; } extern "C" { __global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep) { convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep); } __global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep) { convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float)); } }
/** * Copyright 2019 Matthew Oliver * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include <hip/hip_runtime.h> #include <cstdint> __device__ __forceinline__ float clamp(const float f, const float a, const float b) { return fmaxf(a, fminf(f, b)); } __device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv) { // Get YCbCr values const float luma = static_cast<float>(yuv.x); const float chromaCb = static_cast<float>(yuv.y) - 128.0f; const float chromaCr = static_cast<float>(yuv.z) - 128.0f; // Convert to RGB using BT601 return make_float3( luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb); } struct Pixel2 { float3 m_pixels[2]; }; struct NV12Planes { uint8_t* m_plane1; uint8_t* m_plane2; }; template<typename T> struct RGBPlanes { T* m_plane1; T* m_plane2; T* m_plane3; }; __device__ __forceinline__ Pixel2 getNV12ToRGB( const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep) { // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved // There are 1 U+V sample for every 2x2 Y block // Y1 Y2 Y3 Y4 Y5 Y5 // Y7 Y8 Y9 Y10 Y11 Y12 // Y13 Y14 Y15 Y16 Y17 Y18 // Y19 Y20 Y21 Y22 Y23 Y24 // // U1 V1 U2 V2 U2 V3 // U4 V4 U5 V5 U6 V6 // // UV1 is used for Y1 Y2 Y7 Y8 // UV2 is used for Y3 Y4 Y9 Y10 // UV4 is used for Y13 Y14 Y19 Y20 // etc. // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows // To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4 // This replaces 2 Y loads at a time with 2 UV loads for each 2xY row uchar3 yuvi[2]; const uint32_t sourceOffset = y * sourceStep + x; yuvi[0].x = source.m_plane1[sourceOffset]; yuvi[1].x = source.m_plane1[sourceOffset + 1]; const uint32_t chromaOffset = y >> 1; const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x; const uint8_t chromaCb = source.m_plane2[chromaSourceOffset]; const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1]; // This doesn't perform any chroma interpolation, this feature would need to be added later if needed yuvi[0].y = chromaCb; yuvi[0].z = chromaCr; yuvi[1].y = chromaCb; yuvi[1].z = chromaCr; Pixel2 rgb; rgb.m_pixels[0] = YUVToRGB(yuvi[0]); rgb.m_pixels[1] = YUVToRGB(yuvi[1]); return rgb; } template<typename T> class UpPack { public: typedef float3 Type; }; template<> class UpPack<uint8_t> { public: typedef uchar3 Type; }; template<typename T> __device__ __forceinline__ T getRGB(const float3 pixel) { // Normalise float values return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f)); } template<> __device__ __forceinline__ uchar3 getRGB(const float3 pixel) { return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f)); } template<typename T> __device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep) { const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1); const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y; if (x >= width - 1 || y >= height) { return; } Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep); const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]); const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]); const uint32_t destOffset = y * destStep + x; dest.m_plane1[destOffset] = pixel1.x; dest.m_plane1[destOffset + 1] = pixel2.x; dest.m_plane2[destOffset] = pixel1.y; dest.m_plane2[destOffset + 1] = pixel2.y; dest.m_plane3[destOffset] = pixel1.z; dest.m_plane3[destOffset + 1] = pixel2.z; } extern "C" { __global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep) { convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep); } __global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep) { convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float)); } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/** * Copyright 2019 Matthew Oliver * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include <hip/hip_runtime.h> #include <cstdint> __device__ __forceinline__ float clamp(const float f, const float a, const float b) { return fmaxf(a, fminf(f, b)); } __device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv) { // Get YCbCr values const float luma = static_cast<float>(yuv.x); const float chromaCb = static_cast<float>(yuv.y) - 128.0f; const float chromaCr = static_cast<float>(yuv.z) - 128.0f; // Convert to RGB using BT601 return make_float3( luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb); } struct Pixel2 { float3 m_pixels[2]; }; struct NV12Planes { uint8_t* m_plane1; uint8_t* m_plane2; }; template<typename T> struct RGBPlanes { T* m_plane1; T* m_plane2; T* m_plane3; }; __device__ __forceinline__ Pixel2 getNV12ToRGB( const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep) { // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved // There are 1 U+V sample for every 2x2 Y block // Y1 Y2 Y3 Y4 Y5 Y5 // Y7 Y8 Y9 Y10 Y11 Y12 // Y13 Y14 Y15 Y16 Y17 Y18 // Y19 Y20 Y21 Y22 Y23 Y24 // // U1 V1 U2 V2 U2 V3 // U4 V4 U5 V5 U6 V6 // // UV1 is used for Y1 Y2 Y7 Y8 // UV2 is used for Y3 Y4 Y9 Y10 // UV4 is used for Y13 Y14 Y19 Y20 // etc. // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows // To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4 // This replaces 2 Y loads at a time with 2 UV loads for each 2xY row uchar3 yuvi[2]; const uint32_t sourceOffset = y * sourceStep + x; yuvi[0].x = source.m_plane1[sourceOffset]; yuvi[1].x = source.m_plane1[sourceOffset + 1]; const uint32_t chromaOffset = y >> 1; const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x; const uint8_t chromaCb = source.m_plane2[chromaSourceOffset]; const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1]; // This doesn't perform any chroma interpolation, this feature would need to be added later if needed yuvi[0].y = chromaCb; yuvi[0].z = chromaCr; yuvi[1].y = chromaCb; yuvi[1].z = chromaCr; Pixel2 rgb; rgb.m_pixels[0] = YUVToRGB(yuvi[0]); rgb.m_pixels[1] = YUVToRGB(yuvi[1]); return rgb; } template<typename T> class UpPack { public: typedef float3 Type; }; template<> class UpPack<uint8_t> { public: typedef uchar3 Type; }; template<typename T> __device__ __forceinline__ T getRGB(const float3 pixel) { // Normalise float values return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f)); } template<> __device__ __forceinline__ uchar3 getRGB(const float3 pixel) { return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f)); } template<typename T> __device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep) { const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1); const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y; if (x >= width - 1 || y >= height) { return; } Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep); const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]); const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]); const uint32_t destOffset = y * destStep + x; dest.m_plane1[destOffset] = pixel1.x; dest.m_plane1[destOffset + 1] = pixel2.x; dest.m_plane2[destOffset] = pixel1.y; dest.m_plane2[destOffset + 1] = pixel2.y; dest.m_plane3[destOffset] = pixel1.z; dest.m_plane3[destOffset + 1] = pixel2.z; } extern "C" { __global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep) { convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep); } __global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep) { convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float)); } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected convertNV12ToRGB8P .globl convertNV12ToRGB8P .p2align 8 .type convertNV12ToRGB8P,@function convertNV12ToRGB8P: s_clause 0x1 s_load_b32 s4, s[0:1], 0x4c s_load_b64 s[2:3], s[0:1], 0x14 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 s_delay_alu instid0(VALU_DEP_2) v_lshlrev_b32_e32 v3, 1, v1 s_waitcnt lgkmcnt(0) s_and_b32 s5, s4, 0xffff s_lshr_b32 s4, s4, 16 s_mul_i32 s14, s14, s5 v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3] v_lshl_add_u32 v1, s14, 1, v3 s_add_i32 s2, s2, -1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s2, v1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u32_e64 s2, s3, v0 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b32 s2, s[0:1], 0x10 s_load_b128 s[4:7], s[0:1], 0x0 v_lshrrev_b32_e32 v4, 1, v0 s_mov_b32 s3, 0x3ff23cbe s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v4, s2, v[1:2] v_add_nc_u32_e32 v5, 1, v2 v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2] s_mov_b32 s2, 0x61cffeb0 global_load_u8 v4, v5, s[6:7] v_add_nc_u32_e32 v5, 1, v3 s_clause 0x1 global_load_u8 v8, v3, s[4:5] global_load_u8 v9, v5, s[4:5] global_load_u8 v10, v2, s[6:7] s_waitcnt vmcnt(3) v_cvt_f32_ubyte0_e32 v2, v4 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v11, 0xc3000000, v2 s_waitcnt vmcnt(2) v_cvt_f64_u32_e32 v[2:3], v8 s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[6:7], v9 v_cvt_f64_f32_e32 v[4:5], v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3] v_fma_f64 v[4:5], v[4:5], s[2:3], v[6:7] s_clause 0x2 s_load_b32 s2, s[0:1], 0x38 s_load_b128 s[4:7], s[0:1], 0x20 s_load_b64 s[0:1], s[0:1], 0x30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f32_f64_e32 v6, v[2:3] v_cvt_f32_f64_e32 v4, v[4:5] s_waitcnt vmcnt(0) v_cvt_f32_ubyte0_e32 v5, v10 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2] v_cvt_f32_ubyte0_e32 v0, v8 v_cvt_f32_ubyte0_e32 v3, v9 v_add_f32_e32 v1, 0xc3000000, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fmamk_f32 v5, v1, 0xbeca0f91, v0 v_fmac_f32_e32 v0, 0x40020e17, v1 v_fmamk_f32 v7, v1, 0xbeca0f91, v3 v_fmac_f32_e32 v3, 0x40020e17, v1 v_add_nc_u32_e32 v1, 1, v2 v_fmac_f32_e32 v5, 0xbf14a234, v11 v_minmax_f32 v0, v0, 0x437f0000, 0 v_fmac_f32_e32 v7, 0xbf14a234, v11 v_minmax_f32 v3, v3, 0x437f0000, 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_minmax_f32 v5, v5, 0x437f0000, 0 v_cvt_i32_f32_e32 v0, v0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_minmax_f32 v7, v7, 0x437f0000, 0 v_cvt_i32_f32_e32 v3, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cvt_i32_f32_e32 v5, v5 v_cvt_i32_f32_e32 v7, v7 v_minmax_f32 v6, v6, 0x437f0000, 0 v_minmax_f32 v4, v4, 0x437f0000, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f32_e32 v6, v6 v_cvt_i32_f32_e32 v4, v4 s_clause 0x1 global_store_b8 v2, v6, s[4:5] global_store_b8 v1, v4, s[4:5] s_clause 0x1 global_store_b8 v2, v5, s[6:7] global_store_b8 v1, v7, s[6:7] s_clause 0x1 global_store_b8 v2, v0, s[0:1] global_store_b8 v1, v3, s[0:1] .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel convertNV12ToRGB8P .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size convertNV12ToRGB8P, .Lfunc_end0-convertNV12ToRGB8P .section .AMDGPU.csdata,"",@progbits .text .protected convertNV12ToRGB32FP .globl convertNV12ToRGB32FP .p2align 8 .type convertNV12ToRGB32FP,@function convertNV12ToRGB32FP: s_clause 0x1 s_load_b32 s4, s[0:1], 0x4c s_load_b64 s[2:3], s[0:1], 0x14 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 s_delay_alu instid0(VALU_DEP_2) v_lshlrev_b32_e32 v3, 1, v1 s_waitcnt lgkmcnt(0) s_and_b32 s5, s4, 0xffff s_lshr_b32 s4, s4, 16 s_mul_i32 s14, s14, s5 v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3] v_lshl_add_u32 v1, s14, 1, v3 s_add_i32 s2, s2, -1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s2, v1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u32_e64 s2, s3, v0 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_2 s_clause 0x1 s_load_b32 s2, s[0:1], 0x10 s_load_b128 s[4:7], s[0:1], 0x0 v_lshrrev_b32_e32 v4, 1, v0 s_mov_b32 s3, 0x3ff23cbe s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v4, s2, v[1:2] v_add_nc_u32_e32 v5, 1, v2 v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2] s_mov_b32 s2, 0x61cffeb0 global_load_u8 v4, v5, s[6:7] v_add_nc_u32_e32 v5, 1, v3 s_clause 0x1 global_load_u8 v14, v3, s[4:5] global_load_u8 v15, v5, s[4:5] global_load_u8 v12, v2, s[6:7] s_load_b32 s4, s[0:1], 0x38 s_waitcnt lgkmcnt(0) s_lshr_b32 s8, s4, 2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x20 s_load_b64 s[0:1], s[0:1], 0x30 s_waitcnt vmcnt(3) v_cvt_f32_ubyte0_e32 v2, v4 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v16, 0xc3000000, v2 s_waitcnt vmcnt(2) v_cvt_f64_u32_e32 v[2:3], v14 s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[6:7], v15 s_waitcnt vmcnt(0) v_cvt_f32_ubyte0_e32 v17, v12 v_cvt_f32_ubyte0_e32 v14, v14 v_cvt_f64_f32_e32 v[4:5], v16 v_cvt_f32_ubyte0_e32 v15, v15 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v17, 0xc3000000, v17 v_fmamk_f32 v20, v17, 0xbeca0f91, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v20, 0xbf14a234, v16 v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3] v_fma_f64 v[4:5], v[4:5], s[2:3], v[6:7] v_div_scale_f32 v28, s2, v20, 0x437f0000, v20 v_fmamk_f32 v21, v17, 0xbeca0f91, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fmac_f32_e32 v21, 0xbf14a234, v16 v_div_scale_f32 v16, null, 0x437f0000, 0x437f0000, v20 v_rcp_f32_e32 v24, v16 s_waitcnt_depctr 0xfff v_fma_f32 v31, -v16, v24, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v24, v31, v24 v_mul_f32_e32 v36, v28, v24 v_cvt_f32_f64_e32 v18, v[2:3] v_mad_u64_u32 v[6:7], null, v0, s8, v[1:2] v_mov_b32_e32 v7, 0 v_cvt_f32_f64_e32 v19, v[4:5] v_fma_f32 v43, -v16, v36, v28 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b64 v[0:1], 2, v[6:7] v_add_nc_u32_e32 v6, 1, v6 v_fmac_f32_e32 v36, v43, v24 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v8, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo v_lshlrev_b64 v[6:7], 2, v[6:7] v_add_co_u32 v10, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v12, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v13, vcc_lo, s5, v7, vcc_lo v_add_co_u32 v2, vcc_lo, s6, v6 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v6 v_div_scale_f32 v32, null, 0x437f0000, 0x437f0000, v18 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo v_div_scale_f32 v33, null, 0x437f0000, 0x437f0000, v19 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_rcp_f32_e32 v34, v32 v_div_scale_f32 v40, vcc_lo, v18, 0x437f0000, v18 v_fma_f32 v16, -v16, v36, v28 s_waitcnt_depctr 0xfff v_fma_f32 v37, -v32, v34, 1.0 v_dual_fmac_f32 v15, 0x40020e17, v17 :: v_dual_fmac_f32 v34, v37, v34 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_div_scale_f32 v7, null, 0x437f0000, 0x437f0000, v15 v_div_scale_f32 v26, s1, v15, 0x437f0000, v15 v_div_scale_f32 v37, s4, v19, 0x437f0000, v19 v_rcp_f32_e32 v23, v7 v_mul_f32_e32 v42, v40, v34 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f32 v45, -v32, v42, v40 s_waitcnt_depctr 0xfff v_fma_f32 v30, -v7, v23, 1.0 v_fmac_f32_e32 v14, 0x40020e17, v17 v_dual_fmac_f32 v42, v45, v34 :: v_dual_fmac_f32 v23, v30, v23 v_rcp_f32_e32 v30, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v6, null, 0x437f0000, 0x437f0000, v14 v_div_scale_f32 v25, s0, v14, 0x437f0000, v14 v_rcp_f32_e32 v17, v6 s_waitcnt_depctr 0xfff v_fma_f32 v39, -v33, v30, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_fmac_f32_e32 v30, v39, v30 v_div_scale_f32 v22, null, 0x437f0000, 0x437f0000, v21 v_fma_f32 v29, -v6, v17, 1.0 v_div_scale_f32 v31, s3, v21, 0x437f0000, v21 v_rcp_f32_e32 v27, v22 v_mul_f32_e32 v44, v37, v30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v17, v29, v17 v_mul_f32_e32 v35, v25, v17 s_waitcnt_depctr 0xfff v_fma_f32 v29, -v22, v27, 1.0 v_fma_f32 v38, -v6, v35, v25 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v27, v29, v27 v_mul_f32_e32 v29, v26, v23 v_mul_f32_e32 v39, v31, v27 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v41, -v7, v29, v26 v_fmac_f32_e32 v29, v41, v23 v_fma_f32 v41, -v33, v44, v37 v_fmac_f32_e32 v35, v38, v17 v_fma_f32 v38, -v22, v39, v31 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v7, -v7, v29, v26 v_fmac_f32_e32 v44, v41, v30 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_fma_f32 v6, -v6, v35, v25 v_fma_f32 v25, -v32, v42, v40 v_fmac_f32_e32 v39, v38, v27 v_fma_f32 v26, -v33, v44, v37 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_div_fmas_f32 v25, v25, v34, v42 s_mov_b32 vcc_lo, s2 v_fma_f32 v22, -v22, v39, v31 v_div_fmas_f32 v16, v16, v24, v36 s_mov_b32 vcc_lo, s0 v_div_fmas_f32 v6, v6, v17, v35 v_div_fixup_f32 v17, v25, 0x437f0000, v18 s_mov_b32 vcc_lo, s4 v_div_fixup_f32 v16, v16, 0x437f0000, v20 v_div_fmas_f32 v18, v26, v30, v44 s_mov_b32 vcc_lo, s3 v_div_fixup_f32 v6, v6, 0x437f0000, v14 v_div_fmas_f32 v20, v22, v27, v39 v_cmp_nlt_f32_e32 vcc_lo, 1.0, v17 v_div_fixup_f32 v18, v18, 0x437f0000, v19 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_div_fixup_f32 v20, v20, 0x437f0000, v21 v_cndmask_b32_e32 v14, 1.0, v17, vcc_lo s_mov_b32 vcc_lo, s1 v_div_fmas_f32 v7, v7, v23, v29 v_cmp_nlt_f32_e32 vcc_lo, 1.0, v16 v_div_fixup_f32 v7, v7, 0x437f0000, v15 v_cndmask_b32_e32 v19, 1.0, v16, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 1.0, v6 v_cndmask_b32_e32 v21, 1.0, v6, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v17 v_cndmask_b32_e32 v14, 0, v14, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 1.0, v18 v_cndmask_b32_e32 v15, 1.0, v18, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v16 v_cndmask_b32_e32 v16, 0, v19, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 1.0, v20 v_cndmask_b32_e32 v17, 1.0, v20, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v6 v_cndmask_b32_e32 v6, 0, v21, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 1.0, v7 v_cndmask_b32_e32 v19, 1.0, v7, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v18 v_cndmask_b32_e32 v15, 0, v15, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v20 v_cndmask_b32_e32 v17, 0, v17, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v7 v_cndmask_b32_e32 v7, 0, v19, vcc_lo s_clause 0x1 global_store_b32 v[8:9], v14, off global_store_b32 v[12:13], v15, off s_clause 0x1 global_store_b32 v[10:11], v16, off global_store_b32 v[2:3], v17, off s_clause 0x1 global_store_b32 v[0:1], v6, off global_store_b32 v[4:5], v7, off .LBB1_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel convertNV12ToRGB32FP .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 46 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size convertNV12ToRGB32FP, .Lfunc_end1-convertNV12ToRGB32FP .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 24 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: convertNV12ToRGB8P .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: convertNV12ToRGB8P.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 24 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: convertNV12ToRGB32FP .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: convertNV12ToRGB32FP.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 46 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/** * Copyright 2019 Matthew Oliver * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include <hip/hip_runtime.h> #include <cstdint> __device__ __forceinline__ float clamp(const float f, const float a, const float b) { return fmaxf(a, fminf(f, b)); } __device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv) { // Get YCbCr values const float luma = static_cast<float>(yuv.x); const float chromaCb = static_cast<float>(yuv.y) - 128.0f; const float chromaCr = static_cast<float>(yuv.z) - 128.0f; // Convert to RGB using BT601 return make_float3( luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb); } struct Pixel2 { float3 m_pixels[2]; }; struct NV12Planes { uint8_t* m_plane1; uint8_t* m_plane2; }; template<typename T> struct RGBPlanes { T* m_plane1; T* m_plane2; T* m_plane3; }; __device__ __forceinline__ Pixel2 getNV12ToRGB( const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep) { // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved // There are 1 U+V sample for every 2x2 Y block // Y1 Y2 Y3 Y4 Y5 Y5 // Y7 Y8 Y9 Y10 Y11 Y12 // Y13 Y14 Y15 Y16 Y17 Y18 // Y19 Y20 Y21 Y22 Y23 Y24 // // U1 V1 U2 V2 U2 V3 // U4 V4 U5 V5 U6 V6 // // UV1 is used for Y1 Y2 Y7 Y8 // UV2 is used for Y3 Y4 Y9 Y10 // UV4 is used for Y13 Y14 Y19 Y20 // etc. // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows // To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4 // This replaces 2 Y loads at a time with 2 UV loads for each 2xY row uchar3 yuvi[2]; const uint32_t sourceOffset = y * sourceStep + x; yuvi[0].x = source.m_plane1[sourceOffset]; yuvi[1].x = source.m_plane1[sourceOffset + 1]; const uint32_t chromaOffset = y >> 1; const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x; const uint8_t chromaCb = source.m_plane2[chromaSourceOffset]; const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1]; // This doesn't perform any chroma interpolation, this feature would need to be added later if needed yuvi[0].y = chromaCb; yuvi[0].z = chromaCr; yuvi[1].y = chromaCb; yuvi[1].z = chromaCr; Pixel2 rgb; rgb.m_pixels[0] = YUVToRGB(yuvi[0]); rgb.m_pixels[1] = YUVToRGB(yuvi[1]); return rgb; } template<typename T> class UpPack { public: typedef float3 Type; }; template<> class UpPack<uint8_t> { public: typedef uchar3 Type; }; template<typename T> __device__ __forceinline__ T getRGB(const float3 pixel) { // Normalise float values return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f)); } template<> __device__ __forceinline__ uchar3 getRGB(const float3 pixel) { return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f)); } template<typename T> __device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep) { const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1); const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y; if (x >= width - 1 || y >= height) { return; } Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep); const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]); const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]); const uint32_t destOffset = y * destStep + x; dest.m_plane1[destOffset] = pixel1.x; dest.m_plane1[destOffset + 1] = pixel2.x; dest.m_plane2[destOffset] = pixel1.y; dest.m_plane2[destOffset + 1] = pixel2.y; dest.m_plane3[destOffset] = pixel1.z; dest.m_plane3[destOffset + 1] = pixel2.z; } extern "C" { __global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep) { convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep); } __global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width, const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep) { convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float)); } }
.text .file "FFFRFormatConvert.hip" .globl __device_stub__convertNV12ToRGB8P # -- Begin function __device_stub__convertNV12ToRGB8P .p2align 4, 0x90 .type __device_stub__convertNV12ToRGB8P,@function __device_stub__convertNV12ToRGB8P: # @__device_stub__convertNV12ToRGB8P .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 64(%rsp) movq %rsi, 72(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 64(%rsp), %rax movq %rax, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 144(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $convertNV12ToRGB8P, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size __device_stub__convertNV12ToRGB8P, .Lfunc_end0-__device_stub__convertNV12ToRGB8P .cfi_endproc # -- End function .globl __device_stub__convertNV12ToRGB32FP # -- Begin function __device_stub__convertNV12ToRGB32FP .p2align 4, 0x90 .type __device_stub__convertNV12ToRGB32FP,@function __device_stub__convertNV12ToRGB32FP: # @__device_stub__convertNV12ToRGB32FP .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 64(%rsp) movq %rsi, 72(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 64(%rsp), %rax movq %rax, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 144(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $convertNV12ToRGB32FP, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end1: .size __device_stub__convertNV12ToRGB32FP, .Lfunc_end1-__device_stub__convertNV12ToRGB32FP .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $convertNV12ToRGB8P, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $convertNV12ToRGB32FP, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type convertNV12ToRGB8P,@object # @convertNV12ToRGB8P .section .rodata,"a",@progbits .globl convertNV12ToRGB8P .p2align 3, 0x0 convertNV12ToRGB8P: .quad __device_stub__convertNV12ToRGB8P .size convertNV12ToRGB8P, 8 .type convertNV12ToRGB32FP,@object # @convertNV12ToRGB32FP .globl convertNV12ToRGB32FP .p2align 3, 0x0 convertNV12ToRGB32FP: .quad __device_stub__convertNV12ToRGB32FP .size convertNV12ToRGB32FP, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "convertNV12ToRGB8P" .size .L__unnamed_1, 19 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "convertNV12ToRGB32FP" .size .L__unnamed_2, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__convertNV12ToRGB8P .addrsig_sym __device_stub__convertNV12ToRGB32FP .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym convertNV12ToRGB8P .addrsig_sym convertNV12ToRGB32FP .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0000b906_00000000-6_FFFRFormatConvert.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2035: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2035: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj .type _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj, @function _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj: .LFB2057: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %esi, 12(%rsp) movl %edx, 8(%rsp) movl %ecx, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movq %rdi, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %r8, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 168 pushq 24(%rsp) .cfi_def_cfa_offset 176 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq convertNV12ToRGB8P(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj, .-_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj .globl convertNV12ToRGB8P .type convertNV12ToRGB8P, @function convertNV12ToRGB8P: .LFB2058: .cfi_startproc endbr64 subq $24, %rsp .cfi_def_cfa_offset 32 movq %rdi, (%rsp) movq %rsi, 8(%rsp) movl %edx, %esi movl %ecx, %edx movl %r8d, %ecx movq %rsp, %rdi leaq 32(%rsp), %r8 call _Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size convertNV12ToRGB8P, .-convertNV12ToRGB8P .globl _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj .type _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj, @function _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj: .LFB2059: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %esi, 12(%rsp) movl %edx, 8(%rsp) movl %ecx, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movq %rdi, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %r8, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 168 pushq 24(%rsp) .cfi_def_cfa_offset 176 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq convertNV12ToRGB32FP(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj, .-_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj .globl convertNV12ToRGB32FP .type convertNV12ToRGB32FP, @function convertNV12ToRGB32FP: .LFB2060: .cfi_startproc endbr64 subq $24, %rsp .cfi_def_cfa_offset 32 movq %rdi, (%rsp) movq %rsi, 8(%rsp) movl %edx, %esi movl %ecx, %edx movl %r8d, %ecx movq %rsp, %rdi leaq 32(%rsp), %r8 call _Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size convertNV12ToRGB32FP, .-convertNV12ToRGB32FP .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "convertNV12ToRGB32FP" .LC1: .string "convertNV12ToRGB8P" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2062: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq convertNV12ToRGB32FP(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq convertNV12ToRGB8P(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "FFFRFormatConvert.hip" .globl __device_stub__convertNV12ToRGB8P # -- Begin function __device_stub__convertNV12ToRGB8P .p2align 4, 0x90 .type __device_stub__convertNV12ToRGB8P,@function __device_stub__convertNV12ToRGB8P: # @__device_stub__convertNV12ToRGB8P .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 64(%rsp) movq %rsi, 72(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 64(%rsp), %rax movq %rax, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 144(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $convertNV12ToRGB8P, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size __device_stub__convertNV12ToRGB8P, .Lfunc_end0-__device_stub__convertNV12ToRGB8P .cfi_endproc # -- End function .globl __device_stub__convertNV12ToRGB32FP # -- Begin function __device_stub__convertNV12ToRGB32FP .p2align 4, 0x90 .type __device_stub__convertNV12ToRGB32FP,@function __device_stub__convertNV12ToRGB32FP: # @__device_stub__convertNV12ToRGB32FP .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 64(%rsp) movq %rsi, 72(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 64(%rsp), %rax movq %rax, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 144(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $convertNV12ToRGB32FP, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end1: .size __device_stub__convertNV12ToRGB32FP, .Lfunc_end1-__device_stub__convertNV12ToRGB32FP .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $convertNV12ToRGB8P, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $convertNV12ToRGB32FP, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type convertNV12ToRGB8P,@object # @convertNV12ToRGB8P .section .rodata,"a",@progbits .globl convertNV12ToRGB8P .p2align 3, 0x0 convertNV12ToRGB8P: .quad __device_stub__convertNV12ToRGB8P .size convertNV12ToRGB8P, 8 .type convertNV12ToRGB32FP,@object # @convertNV12ToRGB32FP .globl convertNV12ToRGB32FP .p2align 3, 0x0 convertNV12ToRGB32FP: .quad __device_stub__convertNV12ToRGB32FP .size convertNV12ToRGB32FP, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "convertNV12ToRGB8P" .size .L__unnamed_1, 19 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "convertNV12ToRGB32FP" .size .L__unnamed_2, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__convertNV12ToRGB8P .addrsig_sym __device_stub__convertNV12ToRGB32FP .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym convertNV12ToRGB8P .addrsig_sym convertNV12ToRGB32FP .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#ifndef _GENSPARSEMAT_ #define _GENSPARSEMAT_ void GenSparseMat(int *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) { /* generate sparse representation conVec : input vector / flattened matrix sparseVec : sparse vector idxVec : every element is the starting index in sparseVec for ith row in matrix conVec nPostNeurons : number of non-zero elements in ith row */ int i, j, counter = 0, nPost; for(i = 0; i < rows; ++i) { nPost = 0; for(j = 0; j < clms; ++j) { if(conVec[i + clms * j]) { /* i --> j */ sparseVec[counter] = j; counter += 1; nPost += 1; } } nPostNeurons[i] = nPost; } idxVec[0] = 0; for(i = 1; i < rows; ++i) { idxVec[i] = idxVec[i-1] + nPostNeurons[i-1]; } } #endif
code for sm_80
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#ifndef _GENSPARSEMAT_ #define _GENSPARSEMAT_ void GenSparseMat(int *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) { /* generate sparse representation conVec : input vector / flattened matrix sparseVec : sparse vector idxVec : every element is the starting index in sparseVec for ith row in matrix conVec nPostNeurons : number of non-zero elements in ith row */ int i, j, counter = 0, nPost; for(i = 0; i < rows; ++i) { nPost = 0; for(j = 0; j < clms; ++j) { if(conVec[i + clms * j]) { /* i --> j */ sparseVec[counter] = j; counter += 1; nPost += 1; } } nPostNeurons[i] = nPost; } idxVec[0] = 0; for(i = 1; i < rows; ++i) { idxVec[i] = idxVec[i-1] + nPostNeurons[i-1]; } } #endif
.file "tmpxft_0016961c_00000000-6_GenSparseMat.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z12GenSparseMatPiiiS_S_S_ .type _Z12GenSparseMatPiiiS_S_S_, @function _Z12GenSparseMatPiiiS_S_S_: .LFB2027: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %r8, %r12 testl %esi, %esi jle .L4 movq %rdi, %r13 movl %esi, %ebp movl %edx, %edi movq %rcx, %rbx movslq %esi, %r14 movslq %edx, %r10 salq $2, %r10 movl $0, %r8d movl $0, %ecx jmp .L5 .L6: addl $1, %eax addq %r10, %rdx cmpl %eax, %edi je .L9 .L7: cmpl $0, (%rdx) je .L6 movslq %ecx, %r11 movl %eax, (%rbx,%r11,4) addl $1, %ecx addl $1, %esi jmp .L6 .L9: movl %esi, (%r9,%r8,4) addq $1, %r8 addq $4, %r13 cmpq %r14, %r8 je .L8 .L5: movq %r13, %rdx movl $0, %esi movl $0, %eax testl %edi, %edi jg .L7 jmp .L9 .L8: movl $0, (%r12) cmpl $1, %ebp jle .L3 leal -1(%rbp), %ecx movl $0, %eax .L11: movl (%r9,%rax,4), %edx addl (%r12,%rax,4), %edx movl %edx, 4(%r12,%rax,4) addq $1, %rax cmpq %rax, %rcx jne .L11 .L3: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L4: .cfi_restore_state movl $0, (%r8) jmp .L3 .cfi_endproc .LFE2027: .size _Z12GenSparseMatPiiiS_S_S_, .-_Z12GenSparseMatPiiiS_S_S_ .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#ifndef _GENSPARSEMAT_ #define _GENSPARSEMAT_ void GenSparseMat(int *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) { /* generate sparse representation conVec : input vector / flattened matrix sparseVec : sparse vector idxVec : every element is the starting index in sparseVec for ith row in matrix conVec nPostNeurons : number of non-zero elements in ith row */ int i, j, counter = 0, nPost; for(i = 0; i < rows; ++i) { nPost = 0; for(j = 0; j < clms; ++j) { if(conVec[i + clms * j]) { /* i --> j */ sparseVec[counter] = j; counter += 1; nPost += 1; } } nPostNeurons[i] = nPost; } idxVec[0] = 0; for(i = 1; i < rows; ++i) { idxVec[i] = idxVec[i-1] + nPostNeurons[i-1]; } } #endif
#ifndef _GENSPARSEMAT_ #define _GENSPARSEMAT_ void GenSparseMat(int *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) { /* generate sparse representation conVec : input vector / flattened matrix sparseVec : sparse vector idxVec : every element is the starting index in sparseVec for ith row in matrix conVec nPostNeurons : number of non-zero elements in ith row */ int i, j, counter = 0, nPost; for(i = 0; i < rows; ++i) { nPost = 0; for(j = 0; j < clms; ++j) { if(conVec[i + clms * j]) { /* i --> j */ sparseVec[counter] = j; counter += 1; nPost += 1; } } nPostNeurons[i] = nPost; } idxVec[0] = 0; for(i = 1; i < rows; ++i) { idxVec[i] = idxVec[i-1] + nPostNeurons[i-1]; } } #endif
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#ifndef _GENSPARSEMAT_ #define _GENSPARSEMAT_ void GenSparseMat(int *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) { /* generate sparse representation conVec : input vector / flattened matrix sparseVec : sparse vector idxVec : every element is the starting index in sparseVec for ith row in matrix conVec nPostNeurons : number of non-zero elements in ith row */ int i, j, counter = 0, nPost; for(i = 0; i < rows; ++i) { nPost = 0; for(j = 0; j < clms; ++j) { if(conVec[i + clms * j]) { /* i --> j */ sparseVec[counter] = j; counter += 1; nPost += 1; } } nPostNeurons[i] = nPost; } idxVec[0] = 0; for(i = 1; i < rows; ++i) { idxVec[i] = idxVec[i-1] + nPostNeurons[i-1]; } } #endif
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#ifndef _GENSPARSEMAT_ #define _GENSPARSEMAT_ void GenSparseMat(int *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) { /* generate sparse representation conVec : input vector / flattened matrix sparseVec : sparse vector idxVec : every element is the starting index in sparseVec for ith row in matrix conVec nPostNeurons : number of non-zero elements in ith row */ int i, j, counter = 0, nPost; for(i = 0; i < rows; ++i) { nPost = 0; for(j = 0; j < clms; ++j) { if(conVec[i + clms * j]) { /* i --> j */ sparseVec[counter] = j; counter += 1; nPost += 1; } } nPostNeurons[i] = nPost; } idxVec[0] = 0; for(i = 1; i < rows; ++i) { idxVec[i] = idxVec[i-1] + nPostNeurons[i-1]; } } #endif
.text .file "GenSparseMat.hip" .globl _Z12GenSparseMatPiiiS_S_S_ # -- Begin function _Z12GenSparseMatPiiiS_S_S_ .p2align 4, 0x90 .type _Z12GenSparseMatPiiiS_S_S_,@function _Z12GenSparseMatPiiiS_S_S_: # @_Z12GenSparseMatPiiiS_S_S_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %esi, %eax testl %esi, %esi jle .LBB0_9 # %bb.1: # %.preheader.lr.ph movslq %edx, %r10 movl %r10d, %r11d shlq $2, %r10 xorl %ebx, %ebx xorl %r14d, %r14d jmp .LBB0_2 .p2align 4, 0x90 .LBB0_3: # in Loop: Header=BB0_2 Depth=1 xorl %ebp, %ebp .LBB0_8: # %._crit_edge # in Loop: Header=BB0_2 Depth=1 movl %ebp, (%r9,%rbx,4) incq %rbx addq $4, %rdi cmpq %rax, %rbx je .LBB0_9 .LBB0_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB0_5 Depth 2 testl %edx, %edx jle .LBB0_3 # %bb.4: # %.lr.ph.preheader # in Loop: Header=BB0_2 Depth=1 xorl %r15d, %r15d movq %rdi, %r12 xorl %ebp, %ebp jmp .LBB0_5 .p2align 4, 0x90 .LBB0_7: # in Loop: Header=BB0_5 Depth=2 incq %r15 addq %r10, %r12 cmpq %r15, %r11 je .LBB0_8 .LBB0_5: # %.lr.ph # Parent Loop BB0_2 Depth=1 # => This Inner Loop Header: Depth=2 cmpl $0, (%r12) je .LBB0_7 # %bb.6: # in Loop: Header=BB0_5 Depth=2 movslq %r14d, %r14 movl %r15d, (%rcx,%r14,4) incl %r14d incl %ebp jmp .LBB0_7 .LBB0_9: # %._crit_edge40 movl $0, (%r8) cmpl $2, %esi jl .LBB0_12 # %bb.10: # %.lr.ph43.preheader movl (%r8), %ecx decq %rax xorl %edx, %edx .p2align 4, 0x90 .LBB0_11: # %.lr.ph43 # =>This Inner Loop Header: Depth=1 addl (%r9,%rdx,4), %ecx movl %ecx, 4(%r8,%rdx,4) incq %rdx cmpq %rdx, %rax jne .LBB0_11 .LBB0_12: # %._crit_edge44 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z12GenSparseMatPiiiS_S_S_, .Lfunc_end0-_Z12GenSparseMatPiiiS_S_S_ .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0016961c_00000000-6_GenSparseMat.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z12GenSparseMatPiiiS_S_S_ .type _Z12GenSparseMatPiiiS_S_S_, @function _Z12GenSparseMatPiiiS_S_S_: .LFB2027: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %r8, %r12 testl %esi, %esi jle .L4 movq %rdi, %r13 movl %esi, %ebp movl %edx, %edi movq %rcx, %rbx movslq %esi, %r14 movslq %edx, %r10 salq $2, %r10 movl $0, %r8d movl $0, %ecx jmp .L5 .L6: addl $1, %eax addq %r10, %rdx cmpl %eax, %edi je .L9 .L7: cmpl $0, (%rdx) je .L6 movslq %ecx, %r11 movl %eax, (%rbx,%r11,4) addl $1, %ecx addl $1, %esi jmp .L6 .L9: movl %esi, (%r9,%r8,4) addq $1, %r8 addq $4, %r13 cmpq %r14, %r8 je .L8 .L5: movq %r13, %rdx movl $0, %esi movl $0, %eax testl %edi, %edi jg .L7 jmp .L9 .L8: movl $0, (%r12) cmpl $1, %ebp jle .L3 leal -1(%rbp), %ecx movl $0, %eax .L11: movl (%r9,%rax,4), %edx addl (%r12,%rax,4), %edx movl %edx, 4(%r12,%rax,4) addq $1, %rax cmpq %rax, %rcx jne .L11 .L3: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L4: .cfi_restore_state movl $0, (%r8) jmp .L3 .cfi_endproc .LFE2027: .size _Z12GenSparseMatPiiiS_S_S_, .-_Z12GenSparseMatPiiiS_S_S_ .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "GenSparseMat.hip" .globl _Z12GenSparseMatPiiiS_S_S_ # -- Begin function _Z12GenSparseMatPiiiS_S_S_ .p2align 4, 0x90 .type _Z12GenSparseMatPiiiS_S_S_,@function _Z12GenSparseMatPiiiS_S_S_: # @_Z12GenSparseMatPiiiS_S_S_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %esi, %eax testl %esi, %esi jle .LBB0_9 # %bb.1: # %.preheader.lr.ph movslq %edx, %r10 movl %r10d, %r11d shlq $2, %r10 xorl %ebx, %ebx xorl %r14d, %r14d jmp .LBB0_2 .p2align 4, 0x90 .LBB0_3: # in Loop: Header=BB0_2 Depth=1 xorl %ebp, %ebp .LBB0_8: # %._crit_edge # in Loop: Header=BB0_2 Depth=1 movl %ebp, (%r9,%rbx,4) incq %rbx addq $4, %rdi cmpq %rax, %rbx je .LBB0_9 .LBB0_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB0_5 Depth 2 testl %edx, %edx jle .LBB0_3 # %bb.4: # %.lr.ph.preheader # in Loop: Header=BB0_2 Depth=1 xorl %r15d, %r15d movq %rdi, %r12 xorl %ebp, %ebp jmp .LBB0_5 .p2align 4, 0x90 .LBB0_7: # in Loop: Header=BB0_5 Depth=2 incq %r15 addq %r10, %r12 cmpq %r15, %r11 je .LBB0_8 .LBB0_5: # %.lr.ph # Parent Loop BB0_2 Depth=1 # => This Inner Loop Header: Depth=2 cmpl $0, (%r12) je .LBB0_7 # %bb.6: # in Loop: Header=BB0_5 Depth=2 movslq %r14d, %r14 movl %r15d, (%rcx,%r14,4) incl %r14d incl %ebp jmp .LBB0_7 .LBB0_9: # %._crit_edge40 movl $0, (%r8) cmpl $2, %esi jl .LBB0_12 # %bb.10: # %.lr.ph43.preheader movl (%r8), %ecx decq %rax xorl %edx, %edx .p2align 4, 0x90 .LBB0_11: # %.lr.ph43 # =>This Inner Loop Header: Depth=1 addl (%r9,%rdx,4), %ecx movl %ecx, 4(%r8,%rdx,4) incq %rdx cmpq %rdx, %rax jne .LBB0_11 .LBB0_12: # %._crit_edge44 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z12GenSparseMatPiiiS_S_S_, .Lfunc_end0-_Z12GenSparseMatPiiiS_S_S_ .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <stdlib.h> #include <cstring> #include <time.h> __global__ void memtransf(int * arr) { int gid = blockIdx.x * blockDim.x + threadIdx.x; printf("tid : %d, gid : %d, value : %d\n", threadIdx.x, gid, arr[gid]); } int main() { int shape = 128; int size = shape * sizeof(int); int * h_arr; h_arr = (int *)malloc(size); for(int i=0; i<shape;i++) { h_arr[i]=(int)(rand() & 0xff); } int * d_arr; cudaMalloc((void**)&d_arr, size); cudaMemcpy(d_arr, h_arr, size, cudaMemcpyHostToDevice); dim3 block(64); dim3 grid(2); memtransf<<<grid, block>>>(d_arr); cudaDeviceSynchronize(); cudaFree(d_arr); free(h_arr); cudaDeviceReset(); return 0; }
code for sm_80 Function : _Z9memtransfPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */ /* 0x000fe20007ffe0ff */ /*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */ /* 0x000e240000002100 */ /*0060*/ IMAD R11, R11, c[0x0][0x0], R10 ; /* 0x000000000b0b7a24 */ /* 0x001fc800078e020a */ /*0070*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */ /* 0x000fcc00078e0202 */ /*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x000fe20000000f00 */ /*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */ /* 0x000fe200078e00ff */ /*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */ /* 0x000fe20007f1e0ff */ /*00c0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */ /* 0x0001e20000100a00 */ /*00d0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */ /* 0x0000620000000a00 */ /*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */ /* 0x000fe400078e00ff */ /*00f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */ /* 0x000fe200000e06ff */ /*0100*/ STL [R1+0x8], R2 ; /* 0x0000080201007387 */ /* 0x0041e80000100800 */ /*0110*/ LEPC R2 ; /* 0x000000000002734e */ /* 0x003fc60000000000 */ /*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */ /* 0x000fe40000000f00 */ /*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */ /* 0x000fc40000000f00 */ /*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */ /* 0x000fe40000000f00 */ /*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x000fe40000000f00 */ /*0160*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */ /* 0x000fc8000791e102 */ /*0170*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */ /* 0x000fc800007e2503 */ /*0180*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */ /* 0x000fea0003c00000 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <stdlib.h> #include <cstring> #include <time.h> __global__ void memtransf(int * arr) { int gid = blockIdx.x * blockDim.x + threadIdx.x; printf("tid : %d, gid : %d, value : %d\n", threadIdx.x, gid, arr[gid]); } int main() { int shape = 128; int size = shape * sizeof(int); int * h_arr; h_arr = (int *)malloc(size); for(int i=0; i<shape;i++) { h_arr[i]=(int)(rand() & 0xff); } int * d_arr; cudaMalloc((void**)&d_arr, size); cudaMemcpy(d_arr, h_arr, size, cudaMemcpyHostToDevice); dim3 block(64); dim3 grid(2); memtransf<<<grid, block>>>(d_arr); cudaDeviceSynchronize(); cudaFree(d_arr); free(h_arr); cudaDeviceReset(); return 0; }
.file "tmpxft_0016ffb0_00000000-6_memtrans.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z28__device_stub__Z9memtransfPiPi .type _Z28__device_stub__Z9memtransfPiPi, @function _Z28__device_stub__Z9memtransfPiPi: .LFB2082: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9memtransfPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z28__device_stub__Z9memtransfPiPi, .-_Z28__device_stub__Z9memtransfPiPi .globl _Z9memtransfPi .type _Z9memtransfPi, @function _Z9memtransfPi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z9memtransfPiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z9memtransfPi, .-_Z9memtransfPi .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $512, %edi call malloc@PLT movq %rax, %r12 movq %rax, %rbx leaq 512(%rax), %rbp .L12: call rand@PLT movzbl %al, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L12 leaq 8(%rsp), %rdi movl $512, %esi call cudaMalloc@PLT movl $1, %ecx movl $512, %edx movq %r12, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $64, 16(%rsp) movl $1, 20(%rsp) movl $2, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 16(%rsp), %rdx movl $1, %ecx movq 28(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L13: call cudaDeviceSynchronize@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call free@PLT call cudaDeviceReset@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movq 8(%rsp), %rdi call _Z28__device_stub__Z9memtransfPiPi jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z9memtransfPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z9memtransfPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <stdlib.h> #include <cstring> #include <time.h> __global__ void memtransf(int * arr) { int gid = blockIdx.x * blockDim.x + threadIdx.x; printf("tid : %d, gid : %d, value : %d\n", threadIdx.x, gid, arr[gid]); } int main() { int shape = 128; int size = shape * sizeof(int); int * h_arr; h_arr = (int *)malloc(size); for(int i=0; i<shape;i++) { h_arr[i]=(int)(rand() & 0xff); } int * d_arr; cudaMalloc((void**)&d_arr, size); cudaMemcpy(d_arr, h_arr, size, cudaMemcpyHostToDevice); dim3 block(64); dim3 grid(2); memtransf<<<grid, block>>>(d_arr); cudaDeviceSynchronize(); cudaFree(d_arr); free(h_arr); cudaDeviceReset(); return 0; }
#include "hip/hip_runtime.h" #include <stdio.h> #include <stdlib.h> #include <cstring> #include <time.h> __global__ void memtransf(int * arr) { int gid = blockIdx.x * blockDim.x + threadIdx.x; printf("tid : %d, gid : %d, value : %d\n", threadIdx.x, gid, arr[gid]); } int main() { int shape = 128; int size = shape * sizeof(int); int * h_arr; h_arr = (int *)malloc(size); for(int i=0; i<shape;i++) { h_arr[i]=(int)(rand() & 0xff); } int * d_arr; hipMalloc((void**)&d_arr, size); hipMemcpy(d_arr, h_arr, size, hipMemcpyHostToDevice); dim3 block(64); dim3 grid(2); memtransf<<<grid, block>>>(d_arr); hipDeviceSynchronize(); hipFree(d_arr); free(h_arr); hipDeviceReset(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include "hip/hip_runtime.h" #include <stdio.h> #include <stdlib.h> #include <cstring> #include <time.h> __global__ void memtransf(int * arr) { int gid = blockIdx.x * blockDim.x + threadIdx.x; printf("tid : %d, gid : %d, value : %d\n", threadIdx.x, gid, arr[gid]); } int main() { int shape = 128; int size = shape * sizeof(int); int * h_arr; h_arr = (int *)malloc(size); for(int i=0; i<shape;i++) { h_arr[i]=(int)(rand() & 0xff); } int * d_arr; hipMalloc((void**)&d_arr, size); hipMemcpy(d_arr, h_arr, size, hipMemcpyHostToDevice); dim3 block(64); dim3 grid(2); memtransf<<<grid, block>>>(d_arr); hipDeviceSynchronize(); hipFree(d_arr); free(h_arr); hipDeviceReset(); return 0; }
.text .file "memtrans.hip" .globl _Z24__device_stub__memtransfPi # -- Begin function _Z24__device_stub__memtransfPi .p2align 4, 0x90 .type _Z24__device_stub__memtransfPi,@function _Z24__device_stub__memtransfPi: # @_Z24__device_stub__memtransfPi .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z9memtransfPi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size _Z24__device_stub__memtransfPi, .Lfunc_end0-_Z24__device_stub__memtransfPi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $512, %edi # imm = 0x200 callq malloc movq %rax, %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand movzbl %al, %eax movl %eax, (%rbx,%r14,4) incq %r14 cmpq $128, %r14 jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $512, %esi # imm = 0x200 callq hipMalloc movq 8(%rsp), %rdi movl $512, %edx # imm = 0x200 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967298, %rdi # imm = 0x100000002 leaq 62(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 16(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z9memtransfPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free callq hipDeviceReset xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9memtransfPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9memtransfPi,@object # @_Z9memtransfPi .section .rodata,"a",@progbits .globl _Z9memtransfPi .p2align 3, 0x0 _Z9memtransfPi: .quad _Z24__device_stub__memtransfPi .size _Z9memtransfPi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9memtransfPi" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__memtransfPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9memtransfPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0016ffb0_00000000-6_memtrans.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z28__device_stub__Z9memtransfPiPi .type _Z28__device_stub__Z9memtransfPiPi, @function _Z28__device_stub__Z9memtransfPiPi: .LFB2082: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9memtransfPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z28__device_stub__Z9memtransfPiPi, .-_Z28__device_stub__Z9memtransfPiPi .globl _Z9memtransfPi .type _Z9memtransfPi, @function _Z9memtransfPi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z9memtransfPiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z9memtransfPi, .-_Z9memtransfPi .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $512, %edi call malloc@PLT movq %rax, %r12 movq %rax, %rbx leaq 512(%rax), %rbp .L12: call rand@PLT movzbl %al, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L12 leaq 8(%rsp), %rdi movl $512, %esi call cudaMalloc@PLT movl $1, %ecx movl $512, %edx movq %r12, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $64, 16(%rsp) movl $1, 20(%rsp) movl $2, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 16(%rsp), %rdx movl $1, %ecx movq 28(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L13: call cudaDeviceSynchronize@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call free@PLT call cudaDeviceReset@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movq 8(%rsp), %rdi call _Z28__device_stub__Z9memtransfPiPi jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z9memtransfPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z9memtransfPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "memtrans.hip" .globl _Z24__device_stub__memtransfPi # -- Begin function _Z24__device_stub__memtransfPi .p2align 4, 0x90 .type _Z24__device_stub__memtransfPi,@function _Z24__device_stub__memtransfPi: # @_Z24__device_stub__memtransfPi .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z9memtransfPi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size _Z24__device_stub__memtransfPi, .Lfunc_end0-_Z24__device_stub__memtransfPi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $512, %edi # imm = 0x200 callq malloc movq %rax, %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand movzbl %al, %eax movl %eax, (%rbx,%r14,4) incq %r14 cmpq $128, %r14 jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $512, %esi # imm = 0x200 callq hipMalloc movq 8(%rsp), %rdi movl $512, %edx # imm = 0x200 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967298, %rdi # imm = 0x100000002 leaq 62(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 16(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z9memtransfPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free callq hipDeviceReset xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9memtransfPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9memtransfPi,@object # @_Z9memtransfPi .section .rodata,"a",@progbits .globl _Z9memtransfPi .p2align 3, 0x0 _Z9memtransfPi: .quad _Z24__device_stub__memtransfPi .size _Z9memtransfPi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9memtransfPi" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__memtransfPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9memtransfPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <bits/stdc++.h> using namespace std; const int MAXX = 1e8; __constant__ int4 avg_dev[32]; __constant__ double cov_inv_dev[32][3][3]; __constant__ double dets_dev[32]; #define CSC(call) \ do { \ cudaError_t res = call; \ if (res != cudaSuccess) { \ fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \ __FILE__, __LINE__, cudaGetErrorString(res)); \ exit(0); \ } \ } while(0) struct pnt { int x, y; }; __global__ void kernel(uchar4 *data, int w, int h, int nc) { int idx = blockDim.x * blockIdx.x + threadIdx.x; int idy = blockDim.y * blockIdx.y + threadIdx.y; int offsetx = blockDim.x * gridDim.x; int offsety = blockDim.y * gridDim.y; int x, y, i, j, k; uchar4 ps; for (y = idy; y < h; y += offsety) { for (x = idx; x < w; x += offsetx) { ps = data[y * w + x]; double mx = -MAXX; int idx = -1; for (i = 0; i < nc; ++i) { int diff[3]; diff[0] = ps.x - avg_dev[i].x; diff[1] = ps.y - avg_dev[i].y; diff[2] = ps.z - avg_dev[i].z; double tmp[3]; for (j = 0; j < 3; ++j) { tmp[j] = 0; for (k = 0; k < 3; ++k) { tmp[j] += (diff[k] * cov_inv_dev[i][k][j]); } } double ans = 0; for (j = 0; j < 3; ++j) { ans += (tmp[j] * diff[j]); } ans = -ans - log(abs(dets_dev[i])); if (ans > mx) { mx = ans; idx = i; } } data[y * w + x].w = idx; } } } int main() { int w, h; char inputFile[256], outputFile[256]; cin >> inputFile >> outputFile; FILE *fp = fopen(inputFile, "rb"); fread(&w, sizeof(int), 1, fp); fread(&h, sizeof(int), 1, fp); uchar4 *data = (uchar4 *) malloc(sizeof(uchar4) * w * h); fread(data, sizeof(uchar4), w * h, fp); fclose(fp); int nc, np; cin >> nc; vector<vector<pnt>> classes(nc); int4 avg[32]; double cov[32][3][3]; double cov_inv[32][3][3]; double dets[32]; for (int i = 0; i < nc; ++i) { cin >> np; classes[i].resize(np); // input + counting averages long long xx = 0, yy = 0, zz = 0; for (int j = 0; j < np; ++j) { cin >> classes[i][j].x >> classes[i][j].y; uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; xx += ps.x; yy += ps.y; zz += ps.z; } xx /= np; avg[i].x = xx; yy /= np; avg[i].y = yy; zz /= np; avg[i].z = zz; cout << avg[i].x << " " << avg[i].y << " " << avg[i].z << "\n"; // counting cov for (int j = 0; j < np; ++j) { uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; int diff[3]; diff[0] = ps.x - avg[i].x; diff[1] = ps.y - avg[i].y; diff[2] = ps.z - avg[i].z; for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] += diff[k] * diff[m]; } } } for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] /= (np - 1); } } // counting cov_inverse + determinants double det = cov[i][0][0] * (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) - cov[i][0][1] * (cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) + cov[i][0][2] * (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]); cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / det; cov_inv[i][1][0] = -(cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) / det; cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / det; cov_inv[i][0][1] = -(cov[i][0][1] * cov[i][2][2] - cov[i][2][1] * cov[i][0][2]) / det; cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][2][0] * cov[i][0][2]) / det; cov_inv[i][2][1] = -(cov[i][0][0] * cov[i][2][1] - cov[i][2][0] * cov[i][0][1]) / det; cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][1][1] * cov[i][0][2]) / det; cov_inv[i][1][2] = -(cov[i][0][0] * cov[i][1][2] - cov[i][1][0] * cov[i][0][2]) / det; cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / det; dets[i] = det; } uchar4 *dev_data; CSC(cudaMalloc(&dev_data, sizeof(uchar4) * w * h)); CSC(cudaMemcpy(dev_data, data, sizeof(uchar4) * w * h, cudaMemcpyHostToDevice)); CSC(cudaMemcpyToSymbol(avg_dev, avg, sizeof(double) * 32 * 3)); CSC(cudaMemcpyToSymbol(cov_inv_dev, cov_inv, sizeof(double) * 32 * 3 * 3)); CSC(cudaMemcpyToSymbol(dets_dev, dets, sizeof(double) * 32)); cudaEvent_t start, stop; float time; cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0); kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc); cudaEventRecord(stop, 0); cudaEventSynchronize(stop); cudaEventElapsedTime(&time, start, stop); fprintf(stderr, "%.2f\n", time); cudaEventDestroy(stop); cudaEventDestroy(start); CSC(cudaMemcpy(data, dev_data, sizeof(uchar4) * h * w, cudaMemcpyDeviceToHost)); fp = fopen(outputFile, "wb"); fwrite(&w, sizeof(int), 1, fp); fwrite(&h, sizeof(int), 1, fp); fwrite(data, sizeof(uchar4), w * h, fp); fclose(fp); cudaFree(dev_data); free(data); return 0; }
code for sm_80 Function : _Z6kernelP6uchar4iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */ /* 0x000e280000002600 */ /*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */ /* 0x000e240000002200 */ /*0030*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */ /* 0x001fe400078e0203 */ /*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e260000002500 */ /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */ /* 0x000fda0003f06270 */ /*0060*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */ /* 0x000fe200078e00ff */ /*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */ /* 0x000e620000002100 */ /*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*00a0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */ /* 0x000fc800078e02ff */ /*00b0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */ /* 0x000ea20000209000 */ /*00c0*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */ /* 0x000fe200078e0a00 */ /*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fcc0003f45070 */ /*00e0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */ /* 0x004ea20000001000 */ /*00f0*/ IMAD R3, R3, c[0x0][0x0], R8 ; /* 0x0000000003037a24 */ /* 0x003fca00078e0208 */ /*0100*/ IADD3 R5, R3, R0, RZ ; /* 0x0000000003057210 */ /* 0x000fc80007ffe0ff */ /*0110*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */ /* 0x000fc800078e33ff */ /*0120*/ IADD3 R9, R9, c[0x0][0x168], R0 ; /* 0x00005a0009097a10 */ /* 0x000fe40007ffe000 */ /*0130*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */ /* 0x004fc80007ffe0ff */ /*0140*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */ /* 0x000064000021f000 */ /*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x001fe400078e00ff */ /*0160*/ IMAD R11, R11, R7, RZ ; /* 0x000000070b0b7224 */ /* 0x002fc800078e02ff */ /*0170*/ IMAD.HI.U32 R2, R7, R11, R6 ; /* 0x0000000b07027227 */ /* 0x000fe200078e0006 */ /*0180*/ IADD3 R7, R0, R5, RZ ; /* 0x0000000500077210 */ /* 0x000fca0007ffe0ff */ /*0190*/ IMAD.HI.U32 R2, R2, R9, RZ ; /* 0x0000000902027227 */ /* 0x000fc800078e00ff */ /*01a0*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */ /* 0x000fc800078e0a02 */ /*01b0*/ IMAD R9, R0, R6, R9 ; /* 0x0000000600097224 */ /* 0x000fca00078e0209 */ /*01c0*/ ISETP.GE.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */ /* 0x000fda0003f06070 */ /*01d0*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */ /* 0x000fe200078e0a00 */ /*01e0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */ /* 0x000fc80007ffe0ff */ /*01f0*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */ /* 0x000fda0003f26070 */ /*0200*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */ /* 0x000fe40007ffe0ff */ /*0210*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */ /* 0x000fc800078e33ff */ /*0220*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */ /* 0x000fc80007ffe0ff */ /*0230*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */ /* 0x000fe400078ec0ff */ /*0240*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */ /* 0x000fe20003f06270 */ /*0250*/ BSSY B0, 0xd00 ; /* 0x00000aa000007945 */ /* 0x000fd80003800000 */ /*0260*/ @P0 BRA 0xcf0 ; /* 0x00000a8000000947 */ /* 0x002fea0003800000 */ /*0270*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */ /* 0x000fda0003f01270 */ /*0280*/ @P0 BRA 0x530 ; /* 0x000002a000000947 */ /* 0x000fea0003800000 */ /*0290*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe20003f25270 */ /*02a0*/ BSSY B1, 0x400 ; /* 0x0000015000017945 */ /* 0x000fe20003800000 */ /*02b0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fe20003f06070 */ /*02c0*/ IMAD.MOV.U32 R17, RZ, RZ, R3 ; /* 0x000000ffff117224 */ /* 0x000fd400078e0003 */ /*02d0*/ @!P1 BRA 0x3f0 ; /* 0x0000011000009947 */ /* 0x000fea0003800000 */ /*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */ /* 0x000fe200078e00ff */ /*02f0*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */ /* 0x000fe20003f25270 */ /*0300*/ IMAD R8, R4, c[0x0][0x168], R3 ; /* 0x00005a0004087a24 */ /* 0x000fe200078e0203 */ /*0310*/ MOV R17, R5 ; /* 0x0000000500117202 */ /* 0x000fe20000000f00 */ /*0320*/ IMAD.MOV.U32 R12, RZ, RZ, 0xff ; /* 0x000000ffff0c7424 */ /* 0x000fe400078e00ff */ /*0330*/ IMAD.WIDE R8, R8, R11, c[0x0][0x160] ; /* 0x0000580008087625 */ /* 0x000fca00078e020b */ /*0340*/ STG.E.U8 [R8.64+0x3], R12 ; /* 0x0000030c08007986 */ /* 0x0001e6000c101104 */ /*0350*/ @!P1 BRA 0x3f0 ; /* 0x0000009000009947 */ /* 0x000fea0003800000 */ /*0360*/ ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600780c */ /* 0x000fe20003f25270 */ /*0370*/ IMAD R8, R4, c[0x0][0x168], R5 ; /* 0x00005a0004087a24 */ /* 0x001fe400078e0205 */ /*0380*/ IMAD.MOV.U32 R17, RZ, RZ, R7 ; /* 0x000000ffff117224 */ /* 0x000fe400078e0007 */ /*0390*/ IMAD.WIDE R8, R8, R11, c[0x0][0x160] ; /* 0x0000580008087625 */ /* 0x000fca00078e020b */ /*03a0*/ STG.E.U8 [R8.64+0x3], R12 ; /* 0x0000030c08007986 */ /* 0x0001e6000c101104 */ /*03b0*/ @P1 IMAD R10, R4, c[0x0][0x168], R7.reuse ; /* 0x00005a00040a1a24 */ /* 0x100fe400078e0207 */ /*03c0*/ @P1 IMAD.IADD R17, R0, 0x1, R7 ; /* 0x0000000100111824 */ /* 0x000fe400078e0207 */ /*03d0*/ @P1 IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a1625 */ /* 0x000fca00078e020b */ /*03e0*/ @P1 STG.E.U8 [R10.64+0x3], R12 ; /* 0x0000030c0a001986 */ /* 0x0001e4000c101104 */ /*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0400*/ BSSY B1, 0x520 ; /* 0x0000011000017945 */ /* 0x000fe20003800000 */ /*0410*/ @!P0 BRA 0x510 ; /* 0x000000f000008947 */ /* 0x000fea0003800000 */ /*0420*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */ /* 0x000fe200000001ff */ /*0430*/ IMAD.MOV.U32 R16, RZ, RZ, 0xff ; /* 0x000000ffff107424 */ /* 0x000fca00078e00ff */ /*0440*/ IMAD R8, R4, c[0x0][0x168], R17 ; /* 0x00005a0004087a24 */ /* 0x001fe200078e0211 */ /*0450*/ IADD3 R17, R0, R17, R0 ; /* 0x0000001100117210 */ /* 0x000fc60007ffe000 */ /*0460*/ IMAD.WIDE R8, R8, R19, c[0x0][0x160] ; /* 0x0000580008087625 */ /* 0x000fe200078e0213 */ /*0470*/ IADD3 R17, R0, R17, R0 ; /* 0x0000001100117210 */ /* 0x000fc80007ffe000 */ /*0480*/ STG.E.U8 [R8.64+0x3], R16 ; /* 0x0000031008007986 */ /* 0x0001e2000c101104 */ /*0490*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */ /* 0x000fe200078e0208 */ /*04a0*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */ /* 0x000fc80003f06270 */ /*04b0*/ STG.E.U8 [R10.64+0x3], R16 ; /* 0x000003100a007986 */ /* 0x0001e2000c101104 */ /*04c0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */ /* 0x000fca00078e020a */ /*04d0*/ STG.E.U8 [R12.64+0x3], R16 ; /* 0x000003100c007986 */ /* 0x0001e2000c101104 */ /*04e0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */ /* 0x000fca00078e020c */ /*04f0*/ STG.E.U8 [R14.64+0x3], R16 ; /* 0x000003100e007986 */ /* 0x0001e2000c101104 */ /*0500*/ @!P0 BRA 0x440 ; /* 0xffffff3000008947 */ /* 0x000fea000383ffff */ /*0510*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0520*/ BRA 0xcf0 ; /* 0x000007c000007947 */ /* 0x000fea0003800000 */ /*0530*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */ /* 0x000fe400078e0003 */ /*0540*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */ /* 0x000fe400078e00ff */ /*0550*/ IMAD R14, R4, c[0x0][0x168], R9 ; /* 0x00005a00040e7a24 */ /* 0x000fc800078e0209 */ /*0560*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */ /* 0x000fcc00078e020f */ /*0570*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000ea2000c1e1900 */ /*0580*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */ /* 0x002fe200000001ff */ /*0590*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */ /* 0x000fe200078e00ff */ /*05a0*/ MOV R11, 0xffffffff ; /* 0xffffffff000b7802 */ /* 0x000fe20000000f00 */ /*05b0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */ /* 0x000fe400078e00ff */ /*05c0*/ IMAD.MOV.U32 R26, RZ, RZ, 0xb00 ; /* 0x00000b00ff1a7424 */ /* 0x000fe400078e00ff */ /*05d0*/ IMAD.MOV.U32 R27, RZ, RZ, 0x200 ; /* 0x00000200ff1b7424 */ /* 0x000fe400078e00ff */ /*05e0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x3e68287c ; /* 0xc197d784ff0d7424 */ /* 0x000fe200078e00ff */ /*05f0*/ PRMT R28, R14, 0x7770, RZ ; /* 0x000077700e1c7816 */ /* 0x004fc400000000ff */ /*0600*/ PRMT R29, R14.reuse, 0x7771, RZ ; /* 0x000077710e1d7816 */ /* 0x040fe400000000ff */ /*0610*/ PRMT R30, R14, 0x7772, RZ ; /* 0x000077720e1e7816 */ /* 0x001fe400000000ff */ /*0620*/ LDC.64 R14, c[0x3][R10] ; /* 0x00c000000a0e7b82 */ /* 0x001e300000000a00 */ /*0630*/ LDC.64 R18, c[0x3][R27] ; /* 0x00c000001b127b82 */ /* 0x000e700000000a00 */ /*0640*/ LDC.64 R24, c[0x3][R27+0x18] ; /* 0x00c006001b187b82 */ /* 0x000ea20000000a00 */ /*0650*/ IMAD.IADD R14, R28, 0x1, -R14 ; /* 0x000000011c0e7824 */ /* 0x001fce00078e0a0e */ /*0660*/ LDC R31, c[0x3][R10+0x8] ; /* 0x00c002000a1f7b82 */ /* 0x000e220000000800 */ /*0670*/ IMAD.IADD R32, R29, 0x1, -R15 ; /* 0x000000011d207824 */ /* 0x000fe200078e0a0f */ /*0680*/ I2F.F64 R20, R14 ; /* 0x0000000e00147312 */ /* 0x000e6c0000201c00 */ /*0690*/ LDC.64 R16, c[0x3][R27+0x8] ; /* 0x00c002001b107b82 */ /* 0x000ee40000000a00 */ /*06a0*/ I2F.F64 R32, R32 ; /* 0x0000002000207312 */ /* 0x000eac0000201c00 */ /*06b0*/ LDC.64 R22, c[0x3][R27+0x20] ; /* 0x00c008001b167b82 */ /* 0x000f220000000a00 */ /*06c0*/ DFMA R18, R20, R18, RZ ; /* 0x000000121412722b */ /* 0x002e8e00000000ff */ /*06d0*/ LDC.64 R34, c[0x3][R27+0x30] ; /* 0x00c00c001b227b82 */ /* 0x000e620000000a00 */ /*06e0*/ DFMA R24, R32, R24, R18 ; /* 0x000000182018722b */ /* 0x0041e40000000012 */ /*06f0*/ IADD3 R18, R30, -R31, RZ ; /* 0x8000001f1e127210 */ /* 0x001fe20007ffe0ff */ /*0700*/ IMAD.MOV.U32 R31, RZ, RZ, -0x3ff ; /* 0xfffffc01ff1f7424 */ /* 0x000fe200078e00ff */ /*0710*/ DFMA R16, R20, R16, RZ ; /* 0x000000101410722b */ /* 0x008f0600000000ff */ /*0720*/ LDC.64 R14, c[0x3][R27+0x38] ; /* 0x00c00e001b0e7b82 */ /* 0x000e220000000a00 */ /*0730*/ I2F.F64 R18, R18 ; /* 0x0000001200127312 */ /* 0x000e640000201c00 */ /*0740*/ DFMA R22, R32, R22, R16 ; /* 0x000000162016722b */ /* 0x01040a0000000010 */ /*0750*/ LDC.64 R16, c[0x3][R26] ; /* 0x00c000001a107b82 */ /* 0x004ea20000000a00 */ /*0760*/ DFMA R34, R18, R34, R24 ; /* 0x000000221222722b */ /* 0x0022ce0000000018 */ /*0770*/ LDC.64 R24, c[0x3][R27+0x10] ; /* 0x00c004001b187b82 */ /* 0x002e620000000a00 */ /*0780*/ DFMA R14, R18, R14, R22 ; /* 0x0000000e120e722b */ /* 0x0011ce0000000016 */ /*0790*/ LDC.64 R22, c[0x3][R27+0x28] ; /* 0x00c00a001b167b82 */ /* 0x001e220000000a00 */ /*07a0*/ DFMA R34, R20, R34, RZ ; /* 0x000000221422722b */ /* 0x008ec800000000ff */ /*07b0*/ DADD R16, -RZ, |R16| ; /* 0x00000000ff107229 */ /* 0x004e880000000510 */ /*07c0*/ DFMA R14, R32, R14, R34 ; /* 0x0000000e200e722b */ /* 0x008fcc0000000022 */ /*07d0*/ ISETP.GT.AND P0, PT, R17, 0xfffff, PT ; /* 0x000fffff1100780c */ /* 0x004fe20003f04270 */ /*07e0*/ DFMA R20, R20, R24, RZ ; /* 0x000000181414722b */ /* 0x00222400000000ff */ /*07f0*/ LDC.64 R24, c[0x3][R27+0x40] ; /* 0x00c010001b187b82 */ /* 0x002e680000000a00 */ /*0800*/ DFMA R22, R32, R22, R20 ; /* 0x000000162016722b */ /* 0x0010640000000014 */ /*0810*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */ /* 0x001fe400078e0010 */ /*0820*/ IMAD.MOV.U32 R21, RZ, RZ, R17 ; /* 0x000000ffff157224 */ /* 0x000fc400078e0011 */ /*0830*/ IMAD.MOV.U32 R32, RZ, RZ, R17 ; /* 0x000000ffff207224 */ /* 0x000fe400078e0011 */ /*0840*/ @!P0 IMAD.MOV.U32 R31, RZ, RZ, -0x435 ; /* 0xfffffbcbff1f8424 */ /* 0x000fe400078e00ff */ /*0850*/ @!P0 DMUL R20, R20, 1.80143985094819840000e+16 ; /* 0x4350000014148828 */ /* 0x000e080000000000 */ /*0860*/ DFMA R24, R18, R24, R22 ; /* 0x000000181218722b */ /* 0x002e4c0000000016 */ /*0870*/ @!P0 MOV R32, R21 ; /* 0x0000001500208202 */ /* 0x001fe40000000f00 */ /*0880*/ @!P0 MOV R16, R20 ; /* 0x0000001400108202 */ /* 0x000fe40000000f00 */ /*0890*/ IADD3 R17, R32, -0x1, RZ ; /* 0xffffffff20117810 */ /* 0x000fe20007ffe0ff */ /*08a0*/ DFMA R14, R18, R24, R14 ; /* 0x00000018120e722b */ /* 0x002046000000000e */ /*08b0*/ ISETP.GE.U32.AND P1, PT, R17, 0x7fefffff, PT ; /* 0x7fefffff1100780c */ /* 0x000fda0003f26070 */ /*08c0*/ @!P1 BRA 0x940 ; /* 0x0000007000009947 */ /* 0x000fea0003800000 */ /*08d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */ /* 0x003fe200078e00ff */ /*08e0*/ FSETP.NEU.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720b */ /* 0x000fe20003f0d000 */ /*08f0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff117424 */ /* 0x000fcc00078e00ff */ /*0900*/ DFMA R16, R20, R16, +INF ; /* 0x7ff000001410742b */ /* 0x000e140000000010 */ /*0910*/ FSEL R16, R16, RZ, P0 ; /* 0x000000ff10107208 */ /* 0x001fe40000000000 */ /*0920*/ FSEL R17, R17, -QNAN , P0 ; /* 0xfff0000011117808 */ /* 0x000fe20000000000 */ /*0930*/ BRA 0xbd0 ; /* 0x0000029000007947 */ /* 0x000fea0003800000 */ /*0940*/ LOP3.LUT R17, R32.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff20117812 */ /* 0x043fe200078ec0ff */ /*0950*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */ /* 0x000fe200078e00ff */ /*0960*/ LEA.HI R31, R32, R31, RZ, 0xc ; /* 0x0000001f201f7211 */ /* 0x000fe400078f60ff */ /*0970*/ LOP3.LUT R17, R17, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000011117812 */ /* 0x000fc800078efcff */ /*0980*/ ISETP.GE.AND P0, PT, R17, 0x3ff6a09f, PT ; /* 0x3ff6a09f1100780c */ /* 0x000fda0003f06270 */ /*0990*/ @P0 IADD3 R19, R17, -0x100000, RZ ; /* 0xfff0000011130810 */ /* 0x000fe40007ffe0ff */ /*09a0*/ @P0 IADD3 R31, R31, 0x1, RZ ; /* 0x000000011f1f0810 */ /* 0x000fe40007ffe0ff */ /*09b0*/ @P0 MOV R17, R19 ; /* 0x0000001300110202 */ /* 0x000fcc0000000f00 */ /*09c0*/ DADD R24, R16, 1 ; /* 0x3ff0000010187429 */ /* 0x000e080000000000 */ /*09d0*/ DADD R16, R16, -1 ; /* 0xbff0000010107429 */ /* 0x000fe40000000000 */ /*09e0*/ MUFU.RCP64H R19, R25 ; /* 0x0000001900137308 */ /* 0x001e240000001800 */ /*09f0*/ DFMA R22, -R24, R18, 1 ; /* 0x3ff000001816742b */ /* 0x0010640000000112 */ /*0a00*/ IMAD.MOV.U32 R24, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff187424 */ /* 0x001fe200078e00ff */ /*0a10*/ MOV R25, 0x3eb1380b ; /* 0x3eb1380b00197802 */ /* 0x000fc60000000f00 */ /*0a20*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */ /* 0x002e0c0000000016 */ /*0a30*/ DFMA R22, R18, R22, R18 ; /* 0x000000161216722b */ /* 0x001e0c0000000012 */ /*0a40*/ DMUL R20, R22, R16 ; /* 0x0000001016147228 */ /* 0x001e0c0000000000 */ /*0a50*/ DFMA R20, R22, R16, R20 ; /* 0x000000101614722b */ /* 0x001e0c0000000014 */ /*0a60*/ DADD R18, R16, -R20 ; /* 0x0000000010127229 */ /* 0x001e0c0000000814 */ /*0a70*/ DADD R18, R18, R18 ; /* 0x0000000012127229 */ /* 0x001e0c0000000012 */ /*0a80*/ DFMA R18, R16, -R20, R18 ; /* 0x800000141012722b */ /* 0x001e080000000012 */ /*0a90*/ DMUL R16, R20, R20 ; /* 0x0000001414107228 */ /* 0x000e480000000000 */ /*0aa0*/ DMUL R18, R22, R18 ; /* 0x0000001216127228 */ /* 0x001fc80000000000 */ /*0ab0*/ DFMA R24, R16, R24, c[0x2][0x0] ; /* 0x008000001018762b */ /* 0x002e0c0000000018 */ /*0ac0*/ DFMA R24, R16, R24, c[0x2][0x8] ; /* 0x008002001018762b */ /* 0x001e0c0000000018 */ /*0ad0*/ DFMA R24, R16, R24, c[0x2][0x10] ; /* 0x008004001018762b */ /* 0x001e0c0000000018 */ /*0ae0*/ DFMA R24, R16, R24, c[0x2][0x18] ; /* 0x008006001018762b */ /* 0x001e0c0000000018 */ /*0af0*/ DFMA R32, R16, R24, c[0x2][0x20] ; /* 0x008008001020762b */ /* 0x0010640000000018 */ /*0b00*/ LOP3.LUT R24, R31, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000001f187812 */ /* 0x001fe200078e3cff */ /*0b10*/ IMAD.MOV.U32 R25, RZ, RZ, 0x43300000 ; /* 0x43300000ff197424 */ /* 0x000fc600078e00ff */ /*0b20*/ DFMA R32, R16, R32, c[0x2][0x28] ; /* 0x00800a001020762b */ /* 0x002e080000000020 */ /*0b30*/ DADD R24, R24, c[0x2][0x38] ; /* 0x00800e0018187629 */ /* 0x000e480000000000 */ /*0b40*/ DFMA R32, R16, R32, c[0x2][0x30] ; /* 0x00800c001020762b */ /* 0x001e080000000020 */ /*0b50*/ DFMA R22, R24, c[0x2][0x40], R20 ; /* 0x0080100018167a2b */ /* 0x002e480000000014 */ /*0b60*/ DMUL R32, R16, R32 ; /* 0x0000002010207228 */ /* 0x001e080000000000 */ /*0b70*/ DFMA R16, -R24, c[0x2][0x40], R22 ; /* 0x0080100018107a2b */ /* 0x002e480000000116 */ /*0b80*/ DFMA R18, R20, R32, R18 ; /* 0x000000201412722b */ /* 0x001fc80000000012 */ /*0b90*/ DADD R16, -R20, R16 ; /* 0x0000000014107229 */ /* 0x002e0c0000000110 */ /*0ba0*/ DADD R16, R18, -R16 ; /* 0x0000000012107229 */ /* 0x001e0c0000000810 */ /*0bb0*/ DFMA R16, R24, c[0x2][0x48], R16 ; /* 0x0080120018107a2b */ /* 0x001e0c0000000010 */ /*0bc0*/ DADD R16, R22, R16 ; /* 0x0000000016107229 */ /* 0x00104c0000000010 */ /*0bd0*/ DADD R14, -R14, -R16 ; /* 0x000000000e0e7229 */ /* 0x002e620000000910 */ /*0be0*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */ /* 0x000fe40007ffe0ff */ /*0bf0*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */ /* 0x000fe40007ffe0ff */ /*0c00*/ IADD3 R27, R27, 0x48, RZ ; /* 0x000000481b1b7810 */ /* 0x000fe20007ffe0ff */ /*0c10*/ DSETP.GT.AND P0, PT, R14, R12, PT ; /* 0x0000000c0e00722a */ /* 0x002e4c0003f04000 */ /*0c20*/ SEL R11, R8.reuse, R11, P0 ; /* 0x0000000b080b7207 */ /* 0x042fe40000000000 */ /*0c30*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */ /* 0x000fe40007ffe0ff */ /*0c40*/ FSEL R12, R14, R12, P0 ; /* 0x0000000c0e0c7208 */ /* 0x000fe40000000000 */ /*0c50*/ ISETP.GE.AND P1, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */ /* 0x000fe40003f26270 */ /*0c60*/ FSEL R13, R15, R13, P0 ; /* 0x0000000d0f0d7208 */ /* 0x000fd60000000000 */ /*0c70*/ @!P1 BRA 0x620 ; /* 0xfffff9a000009947 */ /* 0x000fea000383ffff */ /*0c80*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */ /* 0x000fe400078e00ff */ /*0c90*/ IMAD R12, R4, c[0x0][0x168], R9 ; /* 0x00005a00040c7a24 */ /* 0x000fe200078e0209 */ /*0ca0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */ /* 0x000fc60007ffe0ff */ /*0cb0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */ /* 0x000fe200078e020d */ /*0cc0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */ /* 0x000fc80003f06270 */ /*0cd0*/ STG.E.U8 [R12.64+0x3], R11 ; /* 0x0000030b0c007986 */ /* 0x0003f2000c101104 */ /*0ce0*/ @!P0 BRA 0x540 ; /* 0xfffff85000008947 */ /* 0x000fea000383ffff */ /*0cf0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0d00*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff097624 */ /* 0x001fc800078e00ff */ /*0d10*/ IMAD R4, R9, c[0x0][0x10], R4 ; /* 0x0000040009047a24 */ /* 0x000fca00078e0204 */ /*0d20*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */ /* 0x000fda0003f06270 */ /*0d30*/ @!P0 BRA 0x240 ; /* 0xfffff50000008947 */ /* 0x000fea000383ffff */ /*0d40*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0d60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0d70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0d80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0d90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0da0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0db0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0dc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0dd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0de0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0df0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <bits/stdc++.h> using namespace std; const int MAXX = 1e8; __constant__ int4 avg_dev[32]; __constant__ double cov_inv_dev[32][3][3]; __constant__ double dets_dev[32]; #define CSC(call) \ do { \ cudaError_t res = call; \ if (res != cudaSuccess) { \ fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \ __FILE__, __LINE__, cudaGetErrorString(res)); \ exit(0); \ } \ } while(0) struct pnt { int x, y; }; __global__ void kernel(uchar4 *data, int w, int h, int nc) { int idx = blockDim.x * blockIdx.x + threadIdx.x; int idy = blockDim.y * blockIdx.y + threadIdx.y; int offsetx = blockDim.x * gridDim.x; int offsety = blockDim.y * gridDim.y; int x, y, i, j, k; uchar4 ps; for (y = idy; y < h; y += offsety) { for (x = idx; x < w; x += offsetx) { ps = data[y * w + x]; double mx = -MAXX; int idx = -1; for (i = 0; i < nc; ++i) { int diff[3]; diff[0] = ps.x - avg_dev[i].x; diff[1] = ps.y - avg_dev[i].y; diff[2] = ps.z - avg_dev[i].z; double tmp[3]; for (j = 0; j < 3; ++j) { tmp[j] = 0; for (k = 0; k < 3; ++k) { tmp[j] += (diff[k] * cov_inv_dev[i][k][j]); } } double ans = 0; for (j = 0; j < 3; ++j) { ans += (tmp[j] * diff[j]); } ans = -ans - log(abs(dets_dev[i])); if (ans > mx) { mx = ans; idx = i; } } data[y * w + x].w = idx; } } } int main() { int w, h; char inputFile[256], outputFile[256]; cin >> inputFile >> outputFile; FILE *fp = fopen(inputFile, "rb"); fread(&w, sizeof(int), 1, fp); fread(&h, sizeof(int), 1, fp); uchar4 *data = (uchar4 *) malloc(sizeof(uchar4) * w * h); fread(data, sizeof(uchar4), w * h, fp); fclose(fp); int nc, np; cin >> nc; vector<vector<pnt>> classes(nc); int4 avg[32]; double cov[32][3][3]; double cov_inv[32][3][3]; double dets[32]; for (int i = 0; i < nc; ++i) { cin >> np; classes[i].resize(np); // input + counting averages long long xx = 0, yy = 0, zz = 0; for (int j = 0; j < np; ++j) { cin >> classes[i][j].x >> classes[i][j].y; uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; xx += ps.x; yy += ps.y; zz += ps.z; } xx /= np; avg[i].x = xx; yy /= np; avg[i].y = yy; zz /= np; avg[i].z = zz; cout << avg[i].x << " " << avg[i].y << " " << avg[i].z << "\n"; // counting cov for (int j = 0; j < np; ++j) { uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; int diff[3]; diff[0] = ps.x - avg[i].x; diff[1] = ps.y - avg[i].y; diff[2] = ps.z - avg[i].z; for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] += diff[k] * diff[m]; } } } for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] /= (np - 1); } } // counting cov_inverse + determinants double det = cov[i][0][0] * (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) - cov[i][0][1] * (cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) + cov[i][0][2] * (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]); cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / det; cov_inv[i][1][0] = -(cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) / det; cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / det; cov_inv[i][0][1] = -(cov[i][0][1] * cov[i][2][2] - cov[i][2][1] * cov[i][0][2]) / det; cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][2][0] * cov[i][0][2]) / det; cov_inv[i][2][1] = -(cov[i][0][0] * cov[i][2][1] - cov[i][2][0] * cov[i][0][1]) / det; cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][1][1] * cov[i][0][2]) / det; cov_inv[i][1][2] = -(cov[i][0][0] * cov[i][1][2] - cov[i][1][0] * cov[i][0][2]) / det; cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / det; dets[i] = det; } uchar4 *dev_data; CSC(cudaMalloc(&dev_data, sizeof(uchar4) * w * h)); CSC(cudaMemcpy(dev_data, data, sizeof(uchar4) * w * h, cudaMemcpyHostToDevice)); CSC(cudaMemcpyToSymbol(avg_dev, avg, sizeof(double) * 32 * 3)); CSC(cudaMemcpyToSymbol(cov_inv_dev, cov_inv, sizeof(double) * 32 * 3 * 3)); CSC(cudaMemcpyToSymbol(dets_dev, dets, sizeof(double) * 32)); cudaEvent_t start, stop; float time; cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0); kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc); cudaEventRecord(stop, 0); cudaEventSynchronize(stop); cudaEventElapsedTime(&time, start, stop); fprintf(stderr, "%.2f\n", time); cudaEventDestroy(stop); cudaEventDestroy(start); CSC(cudaMemcpy(data, dev_data, sizeof(uchar4) * h * w, cudaMemcpyDeviceToHost)); fp = fopen(outputFile, "wb"); fwrite(&w, sizeof(int), 1, fp); fwrite(&h, sizeof(int), 1, fp); fwrite(data, sizeof(uchar4), w * h, fp); fclose(fp); cudaFree(dev_data); free(data); return 0; }
.file "tmpxft_00180323_00000000-6_main.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB10862: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10862: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii .type _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii, @function _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii: .LFB10884: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6kernelP6uchar4iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE10884: .size _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii, .-_Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii .globl _Z6kernelP6uchar4iii .type _Z6kernelP6uchar4iii, @function _Z6kernelP6uchar4iii: .LFB10885: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10885: .size _Z6kernelP6uchar4iii, .-_Z6kernelP6uchar4iii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6kernelP6uchar4iii" .LC1: .string "avg_dev" .LC2: .string "cov_inv_dev" .LC3: .string "dets_dev" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB10887: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6kernelP6uchar4iii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $512, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL7avg_dev(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL11cov_inv_dev(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $256, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZL8dets_dev(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10887: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_,"axG",@progbits,_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_,comdat .weak _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_ .type _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_, @function _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_: .LFB11566: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx movabsq $9223372036854775807, %rdx call _ZSt17__istream_extractRSiPcl@PLT movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE11566: .size _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_, .-_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_ .section .text._ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED5Ev,comdat .align 2 .weak _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev .type _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev, @function _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev: .LFB11577: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %r12 movq 8(%rdi), %rbp movq (%rdi), %rbx cmpq %rbx, %rbp jne .L18 .L16: movq (%r12), %rdi testq %rdi, %rdi je .L15 movq 16(%r12), %rsi subq %rdi, %rsi call _ZdlPvm@PLT .L15: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state addq $24, %rbx cmpq %rbx, %rbp je .L16 .L18: movq (%rbx), %rdi testq %rdi, %rdi je .L17 movq 16(%rbx), %rsi subq %rdi, %rsi call _ZdlPvm@PLT jmp .L17 .cfi_endproc .LFE11577: .size _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev, .-_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev .weak _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED1Ev .set _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED1Ev,_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev .section .rodata._ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm.str1.1,"aMS",@progbits,1 .LC4: .string "vector::_M_default_append" .section .text._ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm,comdat .align 2 .weak _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm .type _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm, @function _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm: .LFB12017: .cfi_startproc endbr64 testq %rsi, %rsi je .L36 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbp movq %rsi, %rbx movq 8(%rdi), %rdx movq (%rdi), %r15 movq %rdx, %r14 subq %r15, %r14 movq %r14, %r13 sarq $3, %r13 movabsq $1152921504606846975, %rax subq %r13, %rax movq %rax, %rcx movq 16(%rdi), %rax subq %rdx, %rax sarq $3, %rax cmpq %rsi, %rax jb .L24 movl $0, (%rdx) movl $0, 4(%rdx) leaq 8(%rdx), %rdi subq $1, %rbx je .L25 leaq (%rdi,%rbx,8), %rsi movq %rdi, %rax .L26: movq (%rdx), %rcx movq %rcx, (%rax) addq $8, %rax cmpq %rax, %rsi jne .L26 subq %rdx, %rsi leaq -8(%rdi,%rsi), %rdi .L25: movq %rdi, 8(%rbp) .L22: addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state cmpq %rsi, %rcx jb .L39 cmpq %r13, %rsi movq %r13, %rax cmovnb %rsi, %rax addq %r13, %rax movabsq $1152921504606846975, %rdx cmpq %rdx, %rax cmova %rdx, %rax salq $3, %rax movq %rax, 8(%rsp) movq %rax, %rdi call _Znwm@PLT movq %rax, %r12 leaq (%rax,%r14), %rdx movl $0, (%rdx) movl $0, 4(%rdx) movq %rbx, %rcx subq $1, %rcx je .L28 leaq 8(%rdx), %rax leaq (%rax,%rcx,8), %rsi .L29: movq (%rdx), %rcx movq %rcx, (%rax) addq $8, %rax cmpq %rax, %rsi jne .L29 .L28: testq %r14, %r14 jg .L40 testq %r15, %r15 je .L32 movq 16(%rbp), %rsi subq %r15, %rsi jmp .L31 .L39: leaq .LC4(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L40: movq %r14, %rdx movq %r15, %rsi movq %r12, %rdi call memmove@PLT movq 16(%rbp), %rsi subq %r15, %rsi .L31: movq %r15, %rdi call _ZdlPvm@PLT .L32: movq %r12, 0(%rbp) addq %r13, %rbx leaq (%r12,%rbx,8), %rax movq %rax, 8(%rbp) movq 8(%rsp), %rax addq %rax, %r12 movq %r12, 16(%rbp) jmp .L22 .L36: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 .cfi_restore 15 ret .cfi_endproc .LFE12017: .size _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm, .-_ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm .section .rodata.str1.1 .LC5: .string "rb" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC6: .string "cannot create std::vector larger than max_size()" .section .rodata.str1.1 .LC7: .string " " .LC8: .string "\n" .section .rodata.str1.8 .align 8 .LC10: .string "/home/ubuntu/Datasets/stackv2/train-structured/ArtDu/PGP/master/labs/lab3/main.cu" .section .rodata.str1.1 .LC11: .string "ERROR in %s:%d. Message: %s\n" .LC12: .string "%.2f\n" .LC13: .string "wb" .text .globl main .type main, @function main: .LFB10859: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA10859 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $4096, %rsp .cfi_def_cfa_offset 4152 orq $0, (%rsp) subq $1976, %rsp .cfi_def_cfa_offset 6128 movq %fs:40, %rax movq %rax, 6056(%rsp) xorl %eax, %eax leaq 5536(%rsp), %rbx movq %rbx, %rsi leaq _ZSt3cin(%rip), %r12 movq %r12, %rdi .LEHB0: call _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_ movq %rax, %rdi leaq 5792(%rsp), %rsi call _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_ leaq .LC5(%rip), %rsi movq %rbx, %rdi call fopen@PLT movq %rax, %rbx leaq 48(%rsp), %rdi movq %rax, %r8 movl $1, %ecx movl $4, %edx movl $4, %esi call __fread_chk@PLT leaq 52(%rsp), %rdi movq %rbx, %r8 movl $1, %ecx movl $4, %edx movl $4, %esi call __fread_chk@PLT movslq 48(%rsp), %rbp movslq 52(%rsp), %rax imulq %rax, %rbp leaq 0(,%rbp,4), %r13 movq %r13, %rdi call malloc@PLT movq %rax, %r14 movq %rbx, %r8 movq %rbp, %rcx movl $4, %edx movq %r13, %rsi movq %rax, %rdi call __fread_chk@PLT movq %rbx, %rdi call fclose@PLT leaq 56(%rsp), %rsi movq %r12, %rdi call _ZNSirsERi@PLT movslq 56(%rsp), %rax movabsq $384307168202282325, %rdx cmpq %rax, %rdx jb .L81 testq %rax, %rax je .L44 leaq (%rax,%rax,2), %rcx leaq 0(,%rcx,8), %rbx movq %rbx, %rdi call _Znwm@PLT movq %rax, 112(%rsp) leaq (%rax,%rbx), %rcx movq %rcx, 128(%rsp) movq %rax, %rdx .L45: movq $0, (%rdx) movq $0, 8(%rdx) movq $0, 16(%rdx) addq $24, %rdx cmpq %rcx, %rdx jne .L45 .L69: movq %rcx, 120(%rsp) cmpl $0, 56(%rsp) jle .L46 leaq 928(%rsp), %r13 leaq 3232(%rsp), %rcx movq %rcx, 32(%rsp) leaq 416(%rsp), %rcx movq %rcx, 40(%rsp) movq %rax, 16(%rsp) movq $0, 24(%rsp) jmp .L59 .L81: movq 6056(%rsp), %rax subq %fs:40, %rax jne .L82 leaq .LC6(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE0: .L82: call __stack_chk_fail@PLT .L86: movq 16(%rsp), %rax movq %rax, %r12 movslq 60(%rsp), %rsi movq 8(%rax), %rdx movq (%rax), %rcx movq %rdx, %rax subq %rcx, %rax sarq $3, %rax cmpq %rsi, %rax jb .L83 cmpq %rax, %rsi jnb .L48 leaq (%rcx,%rsi,8), %rax cmpq %rax, %rdx je .L48 movq %rax, 8(%r12) .L48: movl 60(%rsp), %eax testl %eax, %eax jle .L71 movl $0, %ebp movq $0, 8(%rsp) movl $0, %r15d movq $0, (%rsp) jmp .L50 .L83: subq %rax, %rsi movq %r12, %rdi .LEHB1: call _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm jmp .L48 .L84: movq %rax, %rdi movq %rbx, %rsi addq (%r12), %rsi addq $4, %rsi call _ZNSirsERi@PLT addq (%r12), %rbx movl 4(%rbx), %eax imull 48(%rsp), %eax addl (%rbx), %eax cltq leaq (%r14,%rax,4), %rax movzbl (%rax), %edx addq %rdx, (%rsp) movzbl 1(%rax), %edx addq %rdx, %r15 movzbl 2(%rax), %eax addq %rax, 8(%rsp) movl 60(%rsp), %eax addq $1, %rbp cmpl %ebp, %eax jle .L49 .L50: leaq 0(,%rbp,8), %rbx movq %rbx, %rsi addq (%r12), %rsi leaq _ZSt3cin(%rip), %rdi call _ZNSirsERi@PLT jmp .L84 .L71: movq $0, 8(%rsp) movl $0, %r15d movq $0, (%rsp) .L49: movslq %eax, %rcx movq (%rsp), %rax cqto idivq %rcx movl %eax, %esi movq 40(%rsp), %rdi movq %rdi, %rbx movl %eax, (%rdi) movq %r15, %rax cqto idivq %rcx movl %eax, 4(%rdi) movq 8(%rsp), %rax cqto idivq %rcx movl %eax, 8(%rdi) leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT movq %rax, %rbp movl $1, %edx leaq .LC7(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 4(%rbx), %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rbp movl $1, %edx leaq .LC7(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 8(%rbx), %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx leaq .LC8(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 60(%rsp), %eax testl %eax, %eax jle .L51 movl 48(%rsp), %r10d movl (%rbx), %r8d movl 4(%rbx), %ecx movl 8(%rbx), %ebp movq (%r12), %rdx movslq %eax, %rsi leaq (%rdx,%rsi,8), %rbx leaq 148(%rsp), %r11 leaq 160(%rsp), %rdi movl %r8d, 8(%rsp) movl %eax, %esi jmp .L55 .L54: movl %r9d, %r10d movq (%rsp), %rdx addq $8, %rdx cmpq %rbx, %rdx je .L85 .L55: movl %r10d, %eax imull 4(%rdx), %eax addl (%rdx), %eax cltq leaq (%r14,%rax,4), %rax movzbl (%rax), %r9d movl 8(%rsp), %r15d subl %r15d, %r9d movl %r9d, 148(%rsp) movzbl 1(%rax), %r9d subl %ecx, %r9d movl %r9d, 152(%rsp) movzbl 2(%rax), %eax subl %ebp, %eax movl %eax, 156(%rsp) movq %r13, %r15 movq %r11, %r12 movl %r10d, %r9d movq %rdx, (%rsp) .L52: movl (%r12), %r10d movq %r11, %r8 movq %r15, %rax .L53: movl %r10d, %edx imull (%r8), %edx pxor %xmm0, %xmm0 cvtsi2sdl %edx, %xmm0 addsd (%rax), %xmm0 movsd %xmm0, (%rax) addq $8, %rax addq $4, %r8 cmpq %rdi, %r8 jne .L53 addq $4, %r12 addq $24, %r15 cmpq %rdi, %r12 jne .L52 jmp .L54 .L85: movl %esi, %eax .L51: movq %r13, %rsi subl $1, %eax pxor %xmm1, %xmm1 cvtsi2sdl %eax, %xmm1 leaq 72(%r13), %rcx .L56: movq %rsi, %rax movl $3, %edx .L57: movsd (%rax), %xmm0 divsd %xmm1, %xmm0 movsd %xmm0, (%rax) addq $8, %rax subl $1, %edx jne .L57 addq $24, %rsi cmpq %rcx, %rsi jne .L56 movsd 0(%r13), %xmm3 movsd 32(%r13), %xmm8 movsd 64(%r13), %xmm4 movsd 56(%r13), %xmm2 movsd 40(%r13), %xmm1 movapd %xmm8, %xmm12 mulsd %xmm4, %xmm12 movapd %xmm2, %xmm0 mulsd %xmm1, %xmm0 subsd %xmm0, %xmm12 movsd 8(%r13), %xmm5 movsd 24(%r13), %xmm7 movsd 48(%r13), %xmm10 movapd %xmm4, %xmm6 mulsd %xmm7, %xmm6 movapd %xmm1, %xmm0 mulsd %xmm10, %xmm0 subsd %xmm0, %xmm6 movsd 16(%r13), %xmm9 movapd %xmm2, %xmm11 mulsd %xmm7, %xmm11 movapd %xmm8, %xmm0 mulsd %xmm10, %xmm0 subsd %xmm0, %xmm11 movapd %xmm3, %xmm0 mulsd %xmm12, %xmm0 movapd %xmm5, %xmm13 mulsd %xmm6, %xmm13 subsd %xmm13, %xmm0 movapd %xmm9, %xmm13 mulsd %xmm11, %xmm13 addsd %xmm13, %xmm0 divsd %xmm0, %xmm12 movq 32(%rsp), %rax movsd %xmm12, (%rax) xorpd .LC9(%rip), %xmm6 divsd %xmm0, %xmm6 movsd %xmm6, 24(%rax) divsd %xmm0, %xmm11 movsd %xmm11, 48(%rax) movapd %xmm4, %xmm6 mulsd %xmm5, %xmm6 movapd %xmm2, %xmm11 mulsd %xmm9, %xmm11 subsd %xmm11, %xmm6 xorpd .LC9(%rip), %xmm6 divsd %xmm0, %xmm6 movsd %xmm6, 8(%rax) mulsd %xmm3, %xmm4 movapd %xmm10, %xmm6 mulsd %xmm9, %xmm6 subsd %xmm6, %xmm4 divsd %xmm0, %xmm4 movsd %xmm4, 32(%rax) mulsd %xmm3, %xmm2 movapd %xmm10, %xmm4 mulsd %xmm5, %xmm4 subsd %xmm4, %xmm2 xorpd .LC9(%rip), %xmm2 divsd %xmm0, %xmm2 movsd %xmm2, 56(%rax) movapd %xmm1, %xmm2 mulsd %xmm5, %xmm2 movapd %xmm8, %xmm4 mulsd %xmm9, %xmm4 subsd %xmm4, %xmm2 divsd %xmm0, %xmm2 movsd %xmm2, 16(%rax) mulsd %xmm3, %xmm1 movapd %xmm9, %xmm2 mulsd %xmm7, %xmm2 subsd %xmm2, %xmm1 xorpd .LC9(%rip), %xmm1 divsd %xmm0, %xmm1 movsd %xmm1, 40(%rax) mulsd %xmm8, %xmm3 mulsd %xmm7, %xmm5 subsd %xmm5, %xmm3 divsd %xmm0, %xmm3 movsd %xmm3, 64(%rax) movq 24(%rsp), %rbx movsd %xmm0, 160(%rsp,%rbx,8) addq $1, %rbx movq %rbx, 24(%rsp) addq $72, %rax movq %rax, 32(%rsp) addq $16, 40(%rsp) addq $24, 16(%rsp) cmpl %ebx, 56(%rsp) jle .L46 movq %rcx, %r13 .L59: leaq 60(%rsp), %rsi leaq _ZSt3cin(%rip), %rdi call _ZNSirsERi@PLT jmp .L86 .L46: movslq 48(%rsp), %rsi movslq 52(%rsp), %rax imulq %rax, %rsi salq $2, %rsi leaq 64(%rsp), %rdi call cudaMalloc@PLT movl %eax, %edi testl %eax, %eax je .L60 call cudaGetErrorString@PLT movq %rax, %r9 movl $158, %r8d leaq .LC10(%rip), %rcx leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $0, %edi call exit@PLT .L60: movslq 48(%rsp), %rdx movslq 52(%rsp), %rax imulq %rax, %rdx salq $2, %rdx movl $1, %ecx movq %r14, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi testl %eax, %eax je .L61 call cudaGetErrorString@PLT movq %rax, %r9 movl $159, %r8d leaq .LC10(%rip), %rcx leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $0, %edi call exit@PLT .L61: leaq 416(%rsp), %rsi movl $1, %r8d movl $0, %ecx movl $768, %edx leaq _ZL7avg_dev(%rip), %rdi call cudaMemcpyToSymbol@PLT movl %eax, %edi testl %eax, %eax je .L62 call cudaGetErrorString@PLT movq %rax, %r9 movl $161, %r8d leaq .LC10(%rip), %rcx leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $0, %edi call exit@PLT .L62: leaq 3232(%rsp), %rsi movl $1, %r8d movl $0, %ecx movl $2304, %edx leaq _ZL11cov_inv_dev(%rip), %rdi call cudaMemcpyToSymbol@PLT movl %eax, %edi testl %eax, %eax je .L63 call cudaGetErrorString@PLT movq %rax, %r9 movl $162, %r8d leaq .LC10(%rip), %rcx leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $0, %edi call exit@PLT .L63: leaq 160(%rsp), %rsi movl $1, %r8d movl $0, %ecx movl $256, %edx leaq _ZL8dets_dev(%rip), %rdi call cudaMemcpyToSymbol@PLT movl %eax, %edi testl %eax, %eax je .L64 call cudaGetErrorString@PLT movq %rax, %r9 movl $163, %r8d leaq .LC10(%rip), %rcx leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $0, %edi call exit@PLT .L64: leaq 72(%rsp), %rdi call cudaEventCreate@PLT leaq 80(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 72(%rsp), %rdi call cudaEventRecord@PLT movl $16, 100(%rsp) movl $16, 104(%rsp) movl $1, 108(%rsp) movl $16, 88(%rsp) movl $16, 92(%rsp) movl $0, %r9d movl $0, %r8d movq 100(%rsp), %rdx movl $1, %ecx movq 88(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L65 movl 56(%rsp), %ecx movl 52(%rsp), %edx movl 48(%rsp), %esi movq 64(%rsp), %rdi call _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii .L65: movl $0, %esi movq 80(%rsp), %rdi call cudaEventRecord@PLT movq 80(%rsp), %rdi call cudaEventSynchronize@PLT leaq 100(%rsp), %rdi movq 80(%rsp), %rdx movq 72(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 100(%rsp), %xmm0 leaq .LC12(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $1, %eax call __fprintf_chk@PLT movq 80(%rsp), %rdi call cudaEventDestroy@PLT movq 72(%rsp), %rdi call cudaEventDestroy@PLT movslq 52(%rsp), %rdx movslq 48(%rsp), %rax imulq %rax, %rdx salq $2, %rdx movl $2, %ecx movq 64(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl %eax, %edi testl %eax, %eax je .L66 call cudaGetErrorString@PLT movq %rax, %r9 movl $180, %r8d leaq .LC10(%rip), %rcx leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $0, %edi call exit@PLT .L66: leaq 5792(%rsp), %rdi leaq .LC13(%rip), %rsi call fopen@PLT movq %rax, %rbx leaq 48(%rsp), %rdi movq %rax, %rcx movl $1, %edx movl $4, %esi call fwrite@PLT leaq 52(%rsp), %rdi movq %rbx, %rcx movl $1, %edx movl $4, %esi call fwrite@PLT movl 48(%rsp), %edx imull 52(%rsp), %edx movslq %edx, %rdx movq %rbx, %rcx movl $4, %esi movq %r14, %rdi call fwrite@PLT movq %rbx, %rdi call fclose@PLT movq 64(%rsp), %rdi call cudaFree@PLT .LEHE1: movq %r14, %rdi call free@PLT leaq 112(%rsp), %rdi call _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED1Ev movq 6056(%rsp), %rax subq %fs:40, %rax jne .L87 movl $0, %eax addq $6072, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L73: .cfi_restore_state endbr64 movq %rax, %rbx leaq 112(%rsp), %rdi call _ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED1Ev movq 6056(%rsp), %rax subq %fs:40, %rax je .L68 call __stack_chk_fail@PLT .L68: movq %rbx, %rdi .LEHB2: call _Unwind_Resume@PLT .LEHE2: .L44: movq $0, 112(%rsp) movq $0, 128(%rsp) movl $0, %eax movl $0, %ecx jmp .L69 .L87: call __stack_chk_fail@PLT .cfi_endproc .LFE10859: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA10859: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE10859-.LLSDACSB10859 .LLSDACSB10859: .uleb128 .LEHB0-.LFB10859 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB10859 .uleb128 .LEHE1-.LEHB1 .uleb128 .L73-.LFB10859 .uleb128 0 .uleb128 .LEHB2-.LFB10859 .uleb128 .LEHE2-.LEHB2 .uleb128 0 .uleb128 0 .LLSDACSE10859: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL8dets_dev .comm _ZL8dets_dev,256,32 .local _ZL11cov_inv_dev .comm _ZL11cov_inv_dev,2304,32 .local _ZL7avg_dev .comm _ZL7avg_dev,512,32 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC9: .long 0 .long -2147483648 .long 0 .long 0 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <bits/stdc++.h> using namespace std; const int MAXX = 1e8; __constant__ int4 avg_dev[32]; __constant__ double cov_inv_dev[32][3][3]; __constant__ double dets_dev[32]; #define CSC(call) \ do { \ cudaError_t res = call; \ if (res != cudaSuccess) { \ fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \ __FILE__, __LINE__, cudaGetErrorString(res)); \ exit(0); \ } \ } while(0) struct pnt { int x, y; }; __global__ void kernel(uchar4 *data, int w, int h, int nc) { int idx = blockDim.x * blockIdx.x + threadIdx.x; int idy = blockDim.y * blockIdx.y + threadIdx.y; int offsetx = blockDim.x * gridDim.x; int offsety = blockDim.y * gridDim.y; int x, y, i, j, k; uchar4 ps; for (y = idy; y < h; y += offsety) { for (x = idx; x < w; x += offsetx) { ps = data[y * w + x]; double mx = -MAXX; int idx = -1; for (i = 0; i < nc; ++i) { int diff[3]; diff[0] = ps.x - avg_dev[i].x; diff[1] = ps.y - avg_dev[i].y; diff[2] = ps.z - avg_dev[i].z; double tmp[3]; for (j = 0; j < 3; ++j) { tmp[j] = 0; for (k = 0; k < 3; ++k) { tmp[j] += (diff[k] * cov_inv_dev[i][k][j]); } } double ans = 0; for (j = 0; j < 3; ++j) { ans += (tmp[j] * diff[j]); } ans = -ans - log(abs(dets_dev[i])); if (ans > mx) { mx = ans; idx = i; } } data[y * w + x].w = idx; } } } int main() { int w, h; char inputFile[256], outputFile[256]; cin >> inputFile >> outputFile; FILE *fp = fopen(inputFile, "rb"); fread(&w, sizeof(int), 1, fp); fread(&h, sizeof(int), 1, fp); uchar4 *data = (uchar4 *) malloc(sizeof(uchar4) * w * h); fread(data, sizeof(uchar4), w * h, fp); fclose(fp); int nc, np; cin >> nc; vector<vector<pnt>> classes(nc); int4 avg[32]; double cov[32][3][3]; double cov_inv[32][3][3]; double dets[32]; for (int i = 0; i < nc; ++i) { cin >> np; classes[i].resize(np); // input + counting averages long long xx = 0, yy = 0, zz = 0; for (int j = 0; j < np; ++j) { cin >> classes[i][j].x >> classes[i][j].y; uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; xx += ps.x; yy += ps.y; zz += ps.z; } xx /= np; avg[i].x = xx; yy /= np; avg[i].y = yy; zz /= np; avg[i].z = zz; cout << avg[i].x << " " << avg[i].y << " " << avg[i].z << "\n"; // counting cov for (int j = 0; j < np; ++j) { uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; int diff[3]; diff[0] = ps.x - avg[i].x; diff[1] = ps.y - avg[i].y; diff[2] = ps.z - avg[i].z; for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] += diff[k] * diff[m]; } } } for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] /= (np - 1); } } // counting cov_inverse + determinants double det = cov[i][0][0] * (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) - cov[i][0][1] * (cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) + cov[i][0][2] * (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]); cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / det; cov_inv[i][1][0] = -(cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) / det; cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / det; cov_inv[i][0][1] = -(cov[i][0][1] * cov[i][2][2] - cov[i][2][1] * cov[i][0][2]) / det; cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][2][0] * cov[i][0][2]) / det; cov_inv[i][2][1] = -(cov[i][0][0] * cov[i][2][1] - cov[i][2][0] * cov[i][0][1]) / det; cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][1][1] * cov[i][0][2]) / det; cov_inv[i][1][2] = -(cov[i][0][0] * cov[i][1][2] - cov[i][1][0] * cov[i][0][2]) / det; cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / det; dets[i] = det; } uchar4 *dev_data; CSC(cudaMalloc(&dev_data, sizeof(uchar4) * w * h)); CSC(cudaMemcpy(dev_data, data, sizeof(uchar4) * w * h, cudaMemcpyHostToDevice)); CSC(cudaMemcpyToSymbol(avg_dev, avg, sizeof(double) * 32 * 3)); CSC(cudaMemcpyToSymbol(cov_inv_dev, cov_inv, sizeof(double) * 32 * 3 * 3)); CSC(cudaMemcpyToSymbol(dets_dev, dets, sizeof(double) * 32)); cudaEvent_t start, stop; float time; cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0); kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc); cudaEventRecord(stop, 0); cudaEventSynchronize(stop); cudaEventElapsedTime(&time, start, stop); fprintf(stderr, "%.2f\n", time); cudaEventDestroy(stop); cudaEventDestroy(start); CSC(cudaMemcpy(data, dev_data, sizeof(uchar4) * h * w, cudaMemcpyDeviceToHost)); fp = fopen(outputFile, "wb"); fwrite(&w, sizeof(int), 1, fp); fwrite(&h, sizeof(int), 1, fp); fwrite(data, sizeof(uchar4), w * h, fp); fclose(fp); cudaFree(dev_data); free(data); return 0; }
#include <hip/hip_runtime.h> #include <bits/stdc++.h> using namespace std; const int MAXX = 1e8; __constant__ int4 avg_dev[32]; __constant__ double cov_inv_dev[32][3][3]; __constant__ double dets_dev[32]; #define CSC(call) \ do { \ hipError_t res = call; \ if (res != hipSuccess) { \ fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \ __FILE__, __LINE__, hipGetErrorString(res)); \ exit(0); \ } \ } while(0) struct pnt { int x, y; }; __global__ void kernel(uchar4 *data, int w, int h, int nc) { int idx = blockDim.x * blockIdx.x + threadIdx.x; int idy = blockDim.y * blockIdx.y + threadIdx.y; int offsetx = blockDim.x * gridDim.x; int offsety = blockDim.y * gridDim.y; int x, y, i, j, k; uchar4 ps; for (y = idy; y < h; y += offsety) { for (x = idx; x < w; x += offsetx) { ps = data[y * w + x]; double mx = -MAXX; int idx = -1; for (i = 0; i < nc; ++i) { int diff[3]; diff[0] = ps.x - avg_dev[i].x; diff[1] = ps.y - avg_dev[i].y; diff[2] = ps.z - avg_dev[i].z; double tmp[3]; for (j = 0; j < 3; ++j) { tmp[j] = 0; for (k = 0; k < 3; ++k) { tmp[j] += (diff[k] * cov_inv_dev[i][k][j]); } } double ans = 0; for (j = 0; j < 3; ++j) { ans += (tmp[j] * diff[j]); } ans = -ans - log(abs(dets_dev[i])); if (ans > mx) { mx = ans; idx = i; } } data[y * w + x].w = idx; } } } int main() { int w, h; char inputFile[256], outputFile[256]; cin >> inputFile >> outputFile; FILE *fp = fopen(inputFile, "rb"); fread(&w, sizeof(int), 1, fp); fread(&h, sizeof(int), 1, fp); uchar4 *data = (uchar4 *) malloc(sizeof(uchar4) * w * h); fread(data, sizeof(uchar4), w * h, fp); fclose(fp); int nc, np; cin >> nc; vector<vector<pnt>> classes(nc); int4 avg[32]; double cov[32][3][3]; double cov_inv[32][3][3]; double dets[32]; for (int i = 0; i < nc; ++i) { cin >> np; classes[i].resize(np); // input + counting averages long long xx = 0, yy = 0, zz = 0; for (int j = 0; j < np; ++j) { cin >> classes[i][j].x >> classes[i][j].y; uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; xx += ps.x; yy += ps.y; zz += ps.z; } xx /= np; avg[i].x = xx; yy /= np; avg[i].y = yy; zz /= np; avg[i].z = zz; cout << avg[i].x << " " << avg[i].y << " " << avg[i].z << "\n"; // counting cov for (int j = 0; j < np; ++j) { uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; int diff[3]; diff[0] = ps.x - avg[i].x; diff[1] = ps.y - avg[i].y; diff[2] = ps.z - avg[i].z; for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] += diff[k] * diff[m]; } } } for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] /= (np - 1); } } // counting cov_inverse + determinants double det = cov[i][0][0] * (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) - cov[i][0][1] * (cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) + cov[i][0][2] * (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]); cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / det; cov_inv[i][1][0] = -(cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) / det; cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / det; cov_inv[i][0][1] = -(cov[i][0][1] * cov[i][2][2] - cov[i][2][1] * cov[i][0][2]) / det; cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][2][0] * cov[i][0][2]) / det; cov_inv[i][2][1] = -(cov[i][0][0] * cov[i][2][1] - cov[i][2][0] * cov[i][0][1]) / det; cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][1][1] * cov[i][0][2]) / det; cov_inv[i][1][2] = -(cov[i][0][0] * cov[i][1][2] - cov[i][1][0] * cov[i][0][2]) / det; cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / det; dets[i] = det; } uchar4 *dev_data; CSC(hipMalloc(&dev_data, sizeof(uchar4) * w * h)); CSC(hipMemcpy(dev_data, data, sizeof(uchar4) * w * h, hipMemcpyHostToDevice)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(avg_dev), avg, sizeof(double) * 32 * 3)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(cov_inv_dev), cov_inv, sizeof(double) * 32 * 3 * 3)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(dets_dev), dets, sizeof(double) * 32)); hipEvent_t start, stop; float time; hipEventCreate(&start); hipEventCreate(&stop); hipEventRecord(start, 0); kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc); hipEventRecord(stop, 0); hipEventSynchronize(stop); hipEventElapsedTime(&time, start, stop); fprintf(stderr, "%.2f\n", time); hipEventDestroy(stop); hipEventDestroy(start); CSC(hipMemcpy(data, dev_data, sizeof(uchar4) * h * w, hipMemcpyDeviceToHost)); fp = fopen(outputFile, "wb"); fwrite(&w, sizeof(int), 1, fp); fwrite(&h, sizeof(int), 1, fp); fwrite(data, sizeof(uchar4), w * h, fp); fclose(fp); hipFree(dev_data); free(data); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <bits/stdc++.h> using namespace std; const int MAXX = 1e8; __constant__ int4 avg_dev[32]; __constant__ double cov_inv_dev[32][3][3]; __constant__ double dets_dev[32]; #define CSC(call) \ do { \ hipError_t res = call; \ if (res != hipSuccess) { \ fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \ __FILE__, __LINE__, hipGetErrorString(res)); \ exit(0); \ } \ } while(0) struct pnt { int x, y; }; __global__ void kernel(uchar4 *data, int w, int h, int nc) { int idx = blockDim.x * blockIdx.x + threadIdx.x; int idy = blockDim.y * blockIdx.y + threadIdx.y; int offsetx = blockDim.x * gridDim.x; int offsety = blockDim.y * gridDim.y; int x, y, i, j, k; uchar4 ps; for (y = idy; y < h; y += offsety) { for (x = idx; x < w; x += offsetx) { ps = data[y * w + x]; double mx = -MAXX; int idx = -1; for (i = 0; i < nc; ++i) { int diff[3]; diff[0] = ps.x - avg_dev[i].x; diff[1] = ps.y - avg_dev[i].y; diff[2] = ps.z - avg_dev[i].z; double tmp[3]; for (j = 0; j < 3; ++j) { tmp[j] = 0; for (k = 0; k < 3; ++k) { tmp[j] += (diff[k] * cov_inv_dev[i][k][j]); } } double ans = 0; for (j = 0; j < 3; ++j) { ans += (tmp[j] * diff[j]); } ans = -ans - log(abs(dets_dev[i])); if (ans > mx) { mx = ans; idx = i; } } data[y * w + x].w = idx; } } } int main() { int w, h; char inputFile[256], outputFile[256]; cin >> inputFile >> outputFile; FILE *fp = fopen(inputFile, "rb"); fread(&w, sizeof(int), 1, fp); fread(&h, sizeof(int), 1, fp); uchar4 *data = (uchar4 *) malloc(sizeof(uchar4) * w * h); fread(data, sizeof(uchar4), w * h, fp); fclose(fp); int nc, np; cin >> nc; vector<vector<pnt>> classes(nc); int4 avg[32]; double cov[32][3][3]; double cov_inv[32][3][3]; double dets[32]; for (int i = 0; i < nc; ++i) { cin >> np; classes[i].resize(np); // input + counting averages long long xx = 0, yy = 0, zz = 0; for (int j = 0; j < np; ++j) { cin >> classes[i][j].x >> classes[i][j].y; uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; xx += ps.x; yy += ps.y; zz += ps.z; } xx /= np; avg[i].x = xx; yy /= np; avg[i].y = yy; zz /= np; avg[i].z = zz; cout << avg[i].x << " " << avg[i].y << " " << avg[i].z << "\n"; // counting cov for (int j = 0; j < np; ++j) { uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; int diff[3]; diff[0] = ps.x - avg[i].x; diff[1] = ps.y - avg[i].y; diff[2] = ps.z - avg[i].z; for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] += diff[k] * diff[m]; } } } for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] /= (np - 1); } } // counting cov_inverse + determinants double det = cov[i][0][0] * (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) - cov[i][0][1] * (cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) + cov[i][0][2] * (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]); cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / det; cov_inv[i][1][0] = -(cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) / det; cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / det; cov_inv[i][0][1] = -(cov[i][0][1] * cov[i][2][2] - cov[i][2][1] * cov[i][0][2]) / det; cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][2][0] * cov[i][0][2]) / det; cov_inv[i][2][1] = -(cov[i][0][0] * cov[i][2][1] - cov[i][2][0] * cov[i][0][1]) / det; cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][1][1] * cov[i][0][2]) / det; cov_inv[i][1][2] = -(cov[i][0][0] * cov[i][1][2] - cov[i][1][0] * cov[i][0][2]) / det; cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / det; dets[i] = det; } uchar4 *dev_data; CSC(hipMalloc(&dev_data, sizeof(uchar4) * w * h)); CSC(hipMemcpy(dev_data, data, sizeof(uchar4) * w * h, hipMemcpyHostToDevice)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(avg_dev), avg, sizeof(double) * 32 * 3)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(cov_inv_dev), cov_inv, sizeof(double) * 32 * 3 * 3)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(dets_dev), dets, sizeof(double) * 32)); hipEvent_t start, stop; float time; hipEventCreate(&start); hipEventCreate(&stop); hipEventRecord(start, 0); kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc); hipEventRecord(stop, 0); hipEventSynchronize(stop); hipEventElapsedTime(&time, start, stop); fprintf(stderr, "%.2f\n", time); hipEventDestroy(stop); hipEventDestroy(start); CSC(hipMemcpy(data, dev_data, sizeof(uchar4) * h * w, hipMemcpyDeviceToHost)); fp = fopen(outputFile, "wb"); fwrite(&w, sizeof(int), 1, fp); fwrite(&h, sizeof(int), 1, fp); fwrite(data, sizeof(uchar4), w * h, fp); fclose(fp); hipFree(dev_data); free(data); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6kernelP15HIP_vector_typeIhLj4EEiii .globl _Z6kernelP15HIP_vector_typeIhLj4EEiii .p2align 8 .type _Z6kernelP15HIP_vector_typeIhLj4EEiii,@function _Z6kernelP15HIP_vector_typeIhLj4EEiii: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b32 s33, s[0:1], 0xc v_bfe_u32 v1, v0, 10, 10 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_lshr_b32 s6, s4, 16 s_mov_b32 s4, exec_lo v_mad_u64_u32 v[6:7], null, s15, s6, v[1:2] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s33, v6 s_cbranch_execz .LBB0_17 s_clause 0x1 s_load_b32 s22, s[2:3], 0xc s_load_b64 s[2:3], s[2:3], 0x0 s_clause 0x2 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s38, s[0:1], 0x8 s_load_b32 s39, s[0:1], 0x10 v_and_b32_e32 v0, 0x3ff, v0 s_mov_b32 s7, 0 s_mov_b32 s9, 0x3fe55555 s_mov_b32 s8, 0x55555555 s_mov_b32 s11, 0x3fc38538 s_mov_b32 s10, 0x6b47b09a s_mov_b32 s13, 0x3fc3ab76 s_mov_b32 s12, 0xbf559e2b s_mov_b32 s17, 0x3fc7474d s_mov_b32 s16, 0xd7f4df2e s_mov_b32 s19, 0x3fcc71c0 s_mov_b32 s18, 0x16291751 s_mov_b32 s21, 0x3fd24924 s_mov_b32 s20, 0x9b27acf1 s_mov_b32 s15, 0x3fd99999 s_waitcnt lgkmcnt(0) s_and_b32 s0, s22, 0xffff s_mov_b32 s22, 0x55555780 v_mad_u64_u32 v[7:8], null, s14, s0, v[0:1] s_mul_i32 s41, s2, s0 s_cmp_gt_i32 s39, 0 s_mov_b32 s14, 0x998ef7b6 s_mul_i32 s40, s3, s6 s_cselect_b32 s42, -1, 0 s_mov_b32 s25, 0x3fe62e42 s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_i32_e64 s0, s38, v7 s_mov_b32 s24, 0xfefa39ef s_mov_b32 s27, 0x3c7abc9e s_mov_b32 s26, 0x3b39803f s_mov_b32 s43, 0 s_branch .LBB0_4 .LBB0_2: s_or_b32 exec_lo, exec_lo, s45 .LBB0_3: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s44 v_add_nc_u32_e32 v6, s40, v6 v_cmp_le_i32_e32 vcc_lo, s33, v6 s_or_b32 s43, vcc_lo, s43 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s43 s_cbranch_execz .LBB0_17 .LBB0_4: s_and_saveexec_b32 s44, s0 s_cbranch_execz .LBB0_3 v_mul_lo_u32 v14, v6, s38 v_mov_b32_e32 v15, v7 s_mov_b32 s45, 0 s_branch .LBB0_8 .LBB0_6: v_mov_b32_e32 v16, -1 .LBB0_7: v_add_nc_u32_e32 v15, s41, v15 global_store_b8 v[8:9], v16, off offset:3 v_cmp_le_i32_e32 vcc_lo, s38, v15 s_or_b32 s45, vcc_lo, s45 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s45 s_cbranch_execz .LBB0_2 .LBB0_8: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v8, v15, v14 v_ashrrev_i32_e32 v9, 31, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[8:9] v_add_co_u32 v8, vcc_lo, s4, v8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo s_and_not1_b32 vcc_lo, exec_lo, s42 s_cbranch_vccnz .LBB0_6 s_clause 0x2 global_load_u8 v17, v[8:9], off offset:2 global_load_u8 v18, v[8:9], off offset:1 global_load_u8 v19, v[8:9], off v_mov_b32_e32 v10, 0 v_dual_mov_b32 v11, 0xc197d784 :: v_dual_mov_b32 v16, -1 s_mov_b32 s6, 0 s_getpc_b64 s[28:29] s_add_u32 s28, s28, cov_inv_dev@rel32@lo+4 s_addc_u32 s29, s29, cov_inv_dev@rel32@hi+12 .LBB0_10: s_getpc_b64 s[2:3] s_add_u32 s2, s2, avg_dev@rel32@lo+4 s_addc_u32 s3, s3, avg_dev@rel32@hi+12 s_lshl_b64 s[30:31], s[6:7], 4 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s2, s30, s2 s_addc_u32 s3, s31, s3 s_getpc_b64 s[34:35] s_add_u32 s34, s34, avg_dev@rel32@lo+8 s_addc_u32 s35, s35, avg_dev@rel32@hi+16 s_add_u32 s34, s30, s34 s_addc_u32 s35, s31, s35 s_getpc_b64 s[36:37] s_add_u32 s36, s36, avg_dev@rel32@lo+12 s_addc_u32 s37, s37, avg_dev@rel32@hi+20 s_add_u32 s30, s30, s36 s_addc_u32 s31, s31, s37 s_clause 0x2 s_load_b32 s1, s[2:3], 0x0 s_load_b32 s2, s[34:35], 0x0 s_load_b32 s3, s[30:31], 0x0 s_mov_b64 s[30:31], s[28:29] s_waitcnt vmcnt(0) lgkmcnt(0) v_subrev_nc_u32_e32 v20, s1, v19 v_subrev_nc_u32_e32 v21, s2, v18 v_subrev_nc_u32_e32 v22, s3, v17 s_mov_b32 s3, 0 .LBB0_11: s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s3, 2 s_mov_b64 s[34:35], 0 s_cselect_b32 s1, -1, 0 s_cmp_eq_u32 s3, 1 v_cndmask_b32_e64 v5, v5, 0, s1 v_cndmask_b32_e64 v4, v4, 0, s1 s_cselect_b32 s1, -1, 0 s_cmp_eq_u32 s3, 0 v_cndmask_b32_e64 v3, v3, 0, s1 v_cndmask_b32_e64 v2, v2, 0, s1 s_cselect_b32 s1, -1, 0 s_mov_b64 s[36:37], s[30:31] v_cndmask_b32_e64 v1, v1, 0, s1 v_cndmask_b32_e64 v0, v0, 0, s1 s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB0_12: s_cmp_eq_u32 s34, 1 s_load_b64 s[46:47], s[36:37], 0x0 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s34, 2 v_cndmask_b32_e32 v12, v20, v21, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s3, 1 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e32 v12, v12, v22, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s3, 2 v_cndmask_b32_e32 v23, v1, v3, vcc_lo v_cndmask_b32_e32 v25, v0, v2, vcc_lo v_cvt_f64_i32_e32 v[12:13], v12 s_cselect_b32 s1, -1, 0 s_cmp_eq_u32 s3, 0 v_cndmask_b32_e64 v24, v23, v5, s1 v_cndmask_b32_e64 v23, v25, v4, s1 s_cselect_b32 s2, -1, 0 s_add_u32 s34, s34, 1 s_addc_u32 s35, s35, 0 s_add_u32 s36, s36, 24 s_addc_u32 s37, s37, 0 s_cmp_lg_u32 s34, 3 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], s[46:47], v[12:13], v[23:24] v_cndmask_b32_e32 v2, v2, v12, vcc_lo s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e64 v5, v5, v13, s1 v_cndmask_b32_e64 v4, v4, v12, s1 v_cndmask_b32_e32 v3, v3, v13, vcc_lo v_cndmask_b32_e64 v1, v1, v13, s2 v_cndmask_b32_e64 v0, v0, v12, s2 s_cbranch_scc1 .LBB0_12 s_set_inst_prefetch_distance 0x2 s_add_i32 s3, s3, 1 s_add_u32 s30, s30, 8 s_addc_u32 s31, s31, 0 s_cmp_lg_u32 s3, 3 s_cbranch_scc1 .LBB0_11 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_mov_b64 s[2:3], 0 .p2align 6 .LBB0_15: s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s2, 1 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s2, 2 v_cndmask_b32_e32 v23, v1, v3, vcc_lo v_cndmask_b32_e32 v25, v20, v21, vcc_lo s_cselect_b32 s1, -1, 0 s_add_u32 s2, s2, 1 s_addc_u32 s3, s3, 0 v_cndmask_b32_e64 v24, v23, v5, s1 v_cndmask_b32_e64 v23, v25, v22, s1 s_cmp_lg_u32 s2, 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f64_i32_e32 v[25:26], v23 v_cndmask_b32_e32 v23, v0, v2, vcc_lo v_cndmask_b32_e64 v23, v23, v4, s1 s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[12:13], v[23:24], v[25:26], v[12:13] s_cbranch_scc1 .LBB0_15 s_getpc_b64 s[2:3] s_add_u32 s2, s2, dets_dev@rel32@lo+4 s_addc_u32 s3, s3, dets_dev@rel32@hi+12 s_lshl_b64 s[30:31], s[6:7], 3 s_mov_b32 s23, s9 s_add_u32 s2, s30, s2 s_addc_u32 s3, s31, s3 s_load_b64 s[2:3], s[2:3], 0x0 s_waitcnt lgkmcnt(0) v_frexp_mant_f64_e64 v[20:21], |s[2:3]| v_cmp_class_f64_e64 s1, s[2:3], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[20:21] v_cndmask_b32_e64 v22, 0, 1, vcc_lo v_ldexp_f64 v[20:21], v[20:21], v22 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[20:21], 1.0 v_add_f64 v[28:29], v[20:21], -1.0 v_rcp_f64_e32 v[24:25], v[22:23] v_add_f64 v[30:31], v[22:23], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0 v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0 v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[26:27], v[28:29], v[24:25] v_mul_f64 v[32:33], v[22:23], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[26:27], v[22:23], -v[32:33] v_fma_f64 v[20:21], v[26:27], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[32:33], v[20:21] v_add_f64 v[30:31], v[28:29], -v[22:23] v_add_f64 v[32:33], v[22:23], -v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[28:29], v[28:29], -v[30:31] v_add_f64 v[20:21], v[32:33], -v[20:21] v_frexp_exp_i32_f64_e32 v32, s[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[28:29], -v[22:23] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[30:31], v[20:21] v_mul_f64 v[20:21], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[26:27], v[20:21] v_mul_f64 v[24:25], v[22:23], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[28:29], v[24:25], s[12:13], s[10:11] v_mul_f64 v[30:31], v[22:23], v[24:25] v_fma_f64 v[28:29], v[24:25], v[28:29], s[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[24:25], v[28:29], s[18:19] v_fma_f64 v[28:29], v[24:25], v[28:29], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[24:25], v[28:29], s[14:15] v_fma_f64 v[24:25], v[24:25], v[28:29], s[22:23] v_ldexp_f64 v[28:29], v[22:23], 1 v_add_f64 v[22:23], v[22:23], -v[26:27] s_and_b32 s23, s3, 0x7fffffff s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f64 v[24:25], v[30:31], v[24:25] v_subrev_co_ci_u32_e32 v30, vcc_lo, 0, v32, vcc_lo v_add_f64 v[20:21], v[20:21], -v[22:23] v_cmp_neq_f64_e64 vcc_lo, s[2:3], 0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cvt_f64_i32_e32 v[30:31], v30 v_add_f64 v[26:27], v[28:29], v[24:25] v_ldexp_f64 v[20:21], v[20:21], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[32:33], v[30:31], s[24:25] v_add_f64 v[22:23], v[26:27], -v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[28:29], v[30:31], s[24:25], -v[32:33] v_add_f64 v[22:23], v[24:25], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[30:31], s[26:27], v[28:29] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[32:33], v[24:25] v_add_f64 v[28:29], v[26:27], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[32:33], v[22:23], -v[32:33] v_add_f64 v[30:31], v[22:23], v[28:29] v_add_f64 v[26:27], v[28:29], -v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[24:25], -v[32:33] v_add_f64 v[34:35], v[30:31], -v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[26:27] v_add_f64 v[36:37], v[30:31], -v[34:35] v_add_f64 v[26:27], v[28:29], -v[34:35] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[28:29], v[24:25], v[20:21] v_add_f64 v[22:23], v[22:23], -v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[22:23], v[26:27], v[22:23] v_add_f64 v[26:27], v[28:29], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[28:29], v[22:23] v_add_f64 v[28:29], v[28:29], -v[26:27] v_add_f64 v[20:21], v[20:21], -v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[32:33], v[30:31], v[22:23] v_add_f64 v[24:25], v[24:25], -v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[26:27], v[32:33], -v[30:31] v_add_f64 v[20:21], v[20:21], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[32:33], v[20:21] v_cndmask_b32_e64 v20, v20, s2, s1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v21, v21, s23, s1 v_cndmask_b32_e32 v20, 0, v20, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v21, 0xfff00000, v21, vcc_lo v_add_f64 v[12:13], -v[12:13], -v[20:21] s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, v[12:13], v[10:11] v_dual_cndmask_b32 v11, v11, v13 :: v_dual_cndmask_b32 v10, v10, v12 v_cndmask_b32_e64 v16, v16, s6, vcc_lo s_add_i32 s6, s6, 1 s_add_u32 s28, s28, 0x48 s_addc_u32 s29, s29, 0 s_cmp_lg_u32 s6, s39 s_cbranch_scc1 .LBB0_10 s_branch .LBB0_7 .LBB0_17: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6kernelP15HIP_vector_typeIhLj4EEiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 38 .amdhsa_next_free_sgpr 48 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6kernelP15HIP_vector_typeIhLj4EEiii, .Lfunc_end0-_Z6kernelP15HIP_vector_typeIhLj4EEiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected avg_dev .type avg_dev,@object .section .bss,"aw",@nobits .globl avg_dev .p2align 4, 0x0 avg_dev: .zero 512 .size avg_dev, 512 .protected cov_inv_dev .type cov_inv_dev,@object .globl cov_inv_dev .p2align 4, 0x0 cov_inv_dev: .zero 2304 .size cov_inv_dev, 2304 .protected dets_dev .type dets_dev,@object .globl dets_dev .p2align 4, 0x0 dets_dev: .zero 256 .size dets_dev, 256 .type __hip_cuid_,@object .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym avg_dev .addrsig_sym cov_inv_dev .addrsig_sym dets_dev .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6kernelP15HIP_vector_typeIhLj4EEiii .private_segment_fixed_size: 0 .sgpr_count: 50 .sgpr_spill_count: 0 .symbol: _Z6kernelP15HIP_vector_typeIhLj4EEiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 38 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <bits/stdc++.h> using namespace std; const int MAXX = 1e8; __constant__ int4 avg_dev[32]; __constant__ double cov_inv_dev[32][3][3]; __constant__ double dets_dev[32]; #define CSC(call) \ do { \ hipError_t res = call; \ if (res != hipSuccess) { \ fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \ __FILE__, __LINE__, hipGetErrorString(res)); \ exit(0); \ } \ } while(0) struct pnt { int x, y; }; __global__ void kernel(uchar4 *data, int w, int h, int nc) { int idx = blockDim.x * blockIdx.x + threadIdx.x; int idy = blockDim.y * blockIdx.y + threadIdx.y; int offsetx = blockDim.x * gridDim.x; int offsety = blockDim.y * gridDim.y; int x, y, i, j, k; uchar4 ps; for (y = idy; y < h; y += offsety) { for (x = idx; x < w; x += offsetx) { ps = data[y * w + x]; double mx = -MAXX; int idx = -1; for (i = 0; i < nc; ++i) { int diff[3]; diff[0] = ps.x - avg_dev[i].x; diff[1] = ps.y - avg_dev[i].y; diff[2] = ps.z - avg_dev[i].z; double tmp[3]; for (j = 0; j < 3; ++j) { tmp[j] = 0; for (k = 0; k < 3; ++k) { tmp[j] += (diff[k] * cov_inv_dev[i][k][j]); } } double ans = 0; for (j = 0; j < 3; ++j) { ans += (tmp[j] * diff[j]); } ans = -ans - log(abs(dets_dev[i])); if (ans > mx) { mx = ans; idx = i; } } data[y * w + x].w = idx; } } } int main() { int w, h; char inputFile[256], outputFile[256]; cin >> inputFile >> outputFile; FILE *fp = fopen(inputFile, "rb"); fread(&w, sizeof(int), 1, fp); fread(&h, sizeof(int), 1, fp); uchar4 *data = (uchar4 *) malloc(sizeof(uchar4) * w * h); fread(data, sizeof(uchar4), w * h, fp); fclose(fp); int nc, np; cin >> nc; vector<vector<pnt>> classes(nc); int4 avg[32]; double cov[32][3][3]; double cov_inv[32][3][3]; double dets[32]; for (int i = 0; i < nc; ++i) { cin >> np; classes[i].resize(np); // input + counting averages long long xx = 0, yy = 0, zz = 0; for (int j = 0; j < np; ++j) { cin >> classes[i][j].x >> classes[i][j].y; uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; xx += ps.x; yy += ps.y; zz += ps.z; } xx /= np; avg[i].x = xx; yy /= np; avg[i].y = yy; zz /= np; avg[i].z = zz; cout << avg[i].x << " " << avg[i].y << " " << avg[i].z << "\n"; // counting cov for (int j = 0; j < np; ++j) { uchar4 ps = data[classes[i][j].y * w + classes[i][j].x]; int diff[3]; diff[0] = ps.x - avg[i].x; diff[1] = ps.y - avg[i].y; diff[2] = ps.z - avg[i].z; for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] += diff[k] * diff[m]; } } } for (int k = 0; k < 3; ++k) { for (int m = 0; m < 3; ++m) { cov[i][k][m] /= (np - 1); } } // counting cov_inverse + determinants double det = cov[i][0][0] * (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) - cov[i][0][1] * (cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) + cov[i][0][2] * (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]); cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / det; cov_inv[i][1][0] = -(cov[i][1][0] * cov[i][2][2] - cov[i][2][0] * cov[i][1][2]) / det; cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / det; cov_inv[i][0][1] = -(cov[i][0][1] * cov[i][2][2] - cov[i][2][1] * cov[i][0][2]) / det; cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][2][0] * cov[i][0][2]) / det; cov_inv[i][2][1] = -(cov[i][0][0] * cov[i][2][1] - cov[i][2][0] * cov[i][0][1]) / det; cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][1][1] * cov[i][0][2]) / det; cov_inv[i][1][2] = -(cov[i][0][0] * cov[i][1][2] - cov[i][1][0] * cov[i][0][2]) / det; cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / det; dets[i] = det; } uchar4 *dev_data; CSC(hipMalloc(&dev_data, sizeof(uchar4) * w * h)); CSC(hipMemcpy(dev_data, data, sizeof(uchar4) * w * h, hipMemcpyHostToDevice)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(avg_dev), avg, sizeof(double) * 32 * 3)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(cov_inv_dev), cov_inv, sizeof(double) * 32 * 3 * 3)); CSC(hipMemcpyToSymbol(HIP_SYMBOL(dets_dev), dets, sizeof(double) * 32)); hipEvent_t start, stop; float time; hipEventCreate(&start); hipEventCreate(&stop); hipEventRecord(start, 0); kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc); hipEventRecord(stop, 0); hipEventSynchronize(stop); hipEventElapsedTime(&time, start, stop); fprintf(stderr, "%.2f\n", time); hipEventDestroy(stop); hipEventDestroy(start); CSC(hipMemcpy(data, dev_data, sizeof(uchar4) * h * w, hipMemcpyDeviceToHost)); fp = fopen(outputFile, "wb"); fwrite(&w, sizeof(int), 1, fp); fwrite(&h, sizeof(int), 1, fp); fwrite(data, sizeof(uchar4), w * h, fp); fclose(fp); hipFree(dev_data); free(data); return 0; }
.text .file "main.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii # -- Begin function _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii .p2align 4, 0x90 .type _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii,@function _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii: # @_Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 20(%rsp), %rax movq %rax, 88(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) leaq 12(%rsp), %rax movq %rax, 104(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6kernelP15HIP_vector_typeIhLj4EEiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii, .Lfunc_end0-_Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .quad 0x8000000000000000 # double -0 .quad 0x8000000000000000 # double -0 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $6088, %rsp # imm = 0x17C8 .cfi_def_cfa_offset 6144 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 .cfi_escape 0x2e, 0x00 leaq 5824(%rsp), %rbx movl $_ZSt3cin, %edi movl $256, %edx # imm = 0x100 movq %rbx, %rsi callq _ZSt17__istream_extractRSiPcl .cfi_escape 0x2e, 0x00 leaq 960(%rsp), %rsi movl $_ZSt3cin, %edi movl $256, %edx # imm = 0x100 callq _ZSt17__istream_extractRSiPcl .cfi_escape 0x2e, 0x00 movl $.L.str, %esi movq %rbx, %rdi callq fopen movq %rax, %rbx .cfi_escape 0x2e, 0x00 movq %rsp, %rdi movl $4, %esi movl $1, %edx movq %rax, %rcx callq fread .cfi_escape 0x2e, 0x00 leaq 12(%rsp), %rdi movl $4, %esi movl $1, %edx movq %rbx, %rcx callq fread movslq (%rsp), %rax movslq 12(%rsp), %r14 imulq %rax, %r14 leaq (,%r14,4), %rdi .cfi_escape 0x2e, 0x00 callq malloc .cfi_escape 0x2e, 0x00 movl $4, %esi movq %rax, 16(%rsp) # 8-byte Spill movq %rax, %rdi movq %r14, %rdx movq %rbx, %rcx callq fread .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq fclose .cfi_escape 0x2e, 0x00 leaq 8(%rsp), %rsi movl $_ZSt3cin, %edi callq _ZNSirsERi movslq 8(%rsp), %rbx testq %rbx, %rbx js .LBB1_105 # %bb.1: # %_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EE17_S_check_init_lenEmRKS3_.exit.i testl %ebx, %ebx jne .LBB1_3 # %bb.2: xorl %r15d, %r15d jmp .LBB1_4 .LBB1_3: # %_ZNSt16allocator_traitsISaISt6vectorI3pntSaIS1_EEEE8allocateERS4_m.exit.i.i.i.i leaq (,%rbx,8), %rax leaq (%rax,%rax,2), %rdi .cfi_escape 0x2e, 0x00 callq _Znwm movq %rax, %r15 .LBB1_4: # %_ZNSt12_Vector_baseISt6vectorI3pntSaIS1_EESaIS3_EEC2EmRKS4_.exit.i movq %r15, 24(%rsp) # 8-byte Spill testl %ebx, %ebx je .LBB1_6 # %bb.5: # %.lr.ph.preheader.i.i.i.i.i shlq $3, %rbx leaq (%rbx,%rbx,2), %rbx .cfi_escape 0x2e, 0x00 movq %r15, %rdi xorl %esi, %esi movq %rbx, %rdx callq memset@PLT addq %r15, %rbx movq %rbx, 24(%rsp) # 8-byte Spill .LBB1_6: # %_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EEC2EmRKS3_.exit cmpl $0, 8(%rsp) jle .LBB1_34 # %bb.7: # %.lr.ph258 leaq 3520(%rsp), %r12 xorl %r14d, %r14d movq %r15, 48(%rsp) # 8-byte Spill .p2align 4, 0x90 .LBB1_8: # =>This Loop Header: Depth=1 # Child Loop BB1_41 Depth 2 # Child Loop BB1_24 Depth 2 # Child Loop BB1_25 Depth 3 # Child Loop BB1_26 Depth 4 # Child Loop BB1_30 Depth 2 # Child Loop BB1_31 Depth 3 .Ltmp0: .cfi_escape 0x2e, 0x00 movl $_ZSt3cin, %edi leaq 4(%rsp), %rsi callq _ZNSirsERi .Ltmp1: # %bb.9: # in Loop: Header=BB1_8 Depth=1 leaq (%r14,%r14,2), %rcx leaq (%r15,%rcx,8), %r13 movslq 4(%rsp), %rax movq (%r15,%rcx,8), %rdx movq 8(%r15,%rcx,8), %rcx movq %rcx, %rdi subq %rdx, %rdi sarq $3, %rdi movq %rax, %rsi subq %rdi, %rsi jbe .LBB1_11 # %bb.10: # in Loop: Header=BB1_8 Depth=1 .Ltmp2: .cfi_escape 0x2e, 0x00 movq %r13, %rdi callq _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm .Ltmp3: jmp .LBB1_14 .p2align 4, 0x90 .LBB1_11: # in Loop: Header=BB1_8 Depth=1 jae .LBB1_14 # %bb.12: # in Loop: Header=BB1_8 Depth=1 leaq (%rdx,%rax,8), %rax cmpq %rax, %rcx je .LBB1_14 # %bb.13: # in Loop: Header=BB1_8 Depth=1 movq %rax, 8(%r13) .p2align 4, 0x90 .LBB1_14: # %_ZNSt6vectorI3pntSaIS0_EE6resizeEm.exit # in Loop: Header=BB1_8 Depth=1 movq %r12, 120(%rsp) # 8-byte Spill movl 4(%rsp), %eax testl %eax, %eax jle .LBB1_15 # %bb.40: # %.lr.ph # in Loop: Header=BB1_8 Depth=1 movq %r14, 112(%rsp) # 8-byte Spill movslq (%rsp), %rax movq %rax, 128(%rsp) # 8-byte Spill movl $4, %r15d xorl %r14d, %r14d xorl %ebx, %ebx xorl %r12d, %r12d xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_41: # Parent Loop BB1_8 Depth=1 # => This Inner Loop Header: Depth=2 movq (%r13), %rax leaq (%rax,%r15), %rsi addq $-4, %rsi .Ltmp5: .cfi_escape 0x2e, 0x00 movl $_ZSt3cin, %edi callq _ZNSirsERi .Ltmp6: # %bb.42: # in Loop: Header=BB1_41 Depth=2 movq (%r13), %rsi addq %r15, %rsi .Ltmp7: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSirsERi .Ltmp8: # %bb.43: # in Loop: Header=BB1_41 Depth=2 movq (%r13), %rax movslq (%rax,%r15), %rcx imulq 128(%rsp), %rcx # 8-byte Folded Reload movslq -4(%rax,%r15), %rax addq %rcx, %rax movq 16(%rsp), %rdx # 8-byte Reload movzbl (%rdx,%rax,4), %ecx addq %rcx, %rbx movzbl 1(%rdx,%rax,4), %ecx addq %rcx, %r12 movzbl 2(%rdx,%rax,4), %eax addq %rax, %rbp incq %r14 movslq 4(%rsp), %rax addq $8, %r15 cmpq %rax, %r14 jl .LBB1_41 # %bb.44: # in Loop: Header=BB1_8 Depth=1 movq 112(%rsp), %r14 # 8-byte Reload jmp .LBB1_16 .p2align 4, 0x90 .LBB1_15: # in Loop: Header=BB1_8 Depth=1 xorl %ebp, %ebp xorl %r12d, %r12d xorl %ebx, %ebx .LBB1_16: # %._crit_edge # in Loop: Header=BB1_8 Depth=1 movslq %eax, %rcx movq %rbx, %rax cqto idivq %rcx movq %rax, %rsi movq %r14, %r15 shlq $4, %r14 movl %esi, 192(%rsp,%r14) movq %r12, %rax cqto idivq %rcx movl %eax, 196(%rsp,%r14) movq %rbp, %rax cqto idivq %rcx movl %eax, 200(%rsp,%r14) .Ltmp10: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi # kill: def $esi killed $esi killed $rsi callq _ZNSolsEi .Ltmp11: # %bb.17: # in Loop: Header=BB1_8 Depth=1 .Ltmp12: movq %rax, %rbx .cfi_escape 0x2e, 0x00 movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp13: # %bb.18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit # in Loop: Header=BB1_8 Depth=1 addq %rsp, %r14 addq $192, %r14 movl 4(%r14), %esi .Ltmp14: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZNSolsEi .Ltmp15: # %bb.19: # in Loop: Header=BB1_8 Depth=1 .Ltmp16: movq %rax, %rbx .cfi_escape 0x2e, 0x00 movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp17: # %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit202 # in Loop: Header=BB1_8 Depth=1 movl 8(%r14), %esi .Ltmp18: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZNSolsEi .Ltmp19: # %bb.21: # in Loop: Header=BB1_8 Depth=1 .Ltmp20: .cfi_escape 0x2e, 0x00 movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp21: # %bb.22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit204.preheader # in Loop: Header=BB1_8 Depth=1 movl 4(%rsp), %eax testl %eax, %eax movq 120(%rsp), %r12 # 8-byte Reload jle .LBB1_29 # %bb.23: # %.lr.ph253 # in Loop: Header=BB1_8 Depth=1 movslq (%rsp), %rcx movl (%r14), %edx movl 4(%r14), %esi movl 8(%r14), %edi xorl %r8d, %r8d .p2align 4, 0x90 .LBB1_24: # Parent Loop BB1_8 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_25 Depth 3 # Child Loop BB1_26 Depth 4 movq (%r13), %r9 movslq 4(%r9,%r8,8), %r10 imulq %rcx, %r10 movslq (%r9,%r8,8), %r9 addq %r10, %r9 movq 16(%rsp), %rbx # 8-byte Reload movzbl (%rbx,%r9,4), %r10d subl %edx, %r10d movzbl 1(%rbx,%r9,4), %r11d subl %esi, %r11d movzbl 2(%rbx,%r9,4), %r9d subl %edi, %r9d movl %r10d, 80(%rsp) movl %r11d, 84(%rsp) movl %r9d, 88(%rsp) movq %r12, %r9 xorl %r10d, %r10d .p2align 4, 0x90 .LBB1_25: # %.preheader # Parent Loop BB1_8 Depth=1 # Parent Loop BB1_24 Depth=2 # => This Loop Header: Depth=3 # Child Loop BB1_26 Depth 4 movl 80(%rsp,%r10,4), %r11d xorl %ebx, %ebx .p2align 4, 0x90 .LBB1_26: # Parent Loop BB1_8 Depth=1 # Parent Loop BB1_24 Depth=2 # Parent Loop BB1_25 Depth=3 # => This Inner Loop Header: Depth=4 movl 80(%rsp,%rbx,4), %ebp imull %r11d, %ebp xorps %xmm0, %xmm0 cvtsi2sd %ebp, %xmm0 addsd (%r9,%rbx,8), %xmm0 movsd %xmm0, (%r9,%rbx,8) incq %rbx cmpq $3, %rbx jne .LBB1_26 # %bb.27: # in Loop: Header=BB1_25 Depth=3 incq %r10 addq $24, %r9 cmpq $3, %r10 jne .LBB1_25 # %bb.28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit204 # in Loop: Header=BB1_24 Depth=2 incq %r8 cmpq %rax, %r8 jne .LBB1_24 .LBB1_29: # %.preheader237 # in Loop: Header=BB1_8 Depth=1 decl %eax xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 movq %r12, %rax xorl %ecx, %ecx movq %r15, %r14 movq 48(%rsp), %r15 # 8-byte Reload .p2align 4, 0x90 .LBB1_30: # %.preheader236 # Parent Loop BB1_8 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_31 Depth 3 xorl %edx, %edx .p2align 4, 0x90 .LBB1_31: # Parent Loop BB1_8 Depth=1 # Parent Loop BB1_30 Depth=2 # => This Inner Loop Header: Depth=3 movsd (%rax,%rdx,8), %xmm1 # xmm1 = mem[0],zero divsd %xmm0, %xmm1 movsd %xmm1, (%rax,%rdx,8) incq %rdx cmpq $3, %rdx jne .LBB1_31 # %bb.32: # in Loop: Header=BB1_30 Depth=2 incq %rcx addq $24, %rax cmpq $3, %rcx jne .LBB1_30 # %bb.33: # in Loop: Header=BB1_8 Depth=1 leaq (,%r14,8), %rax leaq (%rax,%rax,8), %rax movsd 3552(%rsp,%rax), %xmm3 # xmm3 = mem[0],zero movsd 3584(%rsp,%rax), %xmm7 # xmm7 = mem[0],zero movapd %xmm3, %xmm10 mulsd %xmm7, %xmm10 movsd 3576(%rsp,%rax), %xmm8 # xmm8 = mem[0],zero movsd 3560(%rsp,%rax), %xmm4 # xmm4 = mem[0],zero movapd %xmm8, %xmm0 mulsd %xmm4, %xmm0 subsd %xmm0, %xmm10 movsd 3520(%rsp,%rax), %xmm0 # xmm0 = mem[0],zero movsd 3528(%rsp,%rax), %xmm1 # xmm1 = mem[0],zero movapd %xmm0, %xmm11 mulsd %xmm10, %xmm11 movsd 3544(%rsp,%rax), %xmm2 # xmm2 = mem[0],zero movapd %xmm7, %xmm12 mulsd %xmm2, %xmm12 movsd 3568(%rsp,%rax), %xmm9 # xmm9 = mem[0],zero movapd %xmm4, %xmm5 mulsd %xmm9, %xmm5 subsd %xmm5, %xmm12 movapd %xmm1, %xmm5 mulsd %xmm12, %xmm5 subsd %xmm5, %xmm11 movsd 3536(%rsp,%rax), %xmm6 # xmm6 = mem[0],zero movapd %xmm8, %xmm13 mulsd %xmm2, %xmm13 movapd %xmm3, %xmm5 mulsd %xmm9, %xmm5 subsd %xmm5, %xmm13 movapd %xmm6, %xmm5 mulsd %xmm13, %xmm5 addsd %xmm11, %xmm5 divsd %xmm5, %xmm10 movsd %xmm10, 1216(%rsp,%rax) movapd .LCPI1_0(%rip), %xmm14 # xmm14 = [-0.0E+0,-0.0E+0] xorpd %xmm14, %xmm12 divsd %xmm5, %xmm12 movsd %xmm12, 1240(%rsp,%rax) divsd %xmm5, %xmm13 movsd %xmm13, 1264(%rsp,%rax) movapd %xmm0, %xmm10 mulsd %xmm7, %xmm10 mulsd %xmm1, %xmm7 movapd %xmm0, %xmm11 mulsd %xmm8, %xmm11 mulsd %xmm6, %xmm8 subsd %xmm8, %xmm7 xorpd %xmm14, %xmm7 divsd %xmm5, %xmm7 movsd %xmm7, 1224(%rsp,%rax) movapd %xmm1, %xmm7 mulsd %xmm9, %xmm7 mulsd %xmm6, %xmm9 subsd %xmm9, %xmm10 divsd %xmm5, %xmm10 movsd %xmm10, 1248(%rsp,%rax) subsd %xmm7, %xmm11 xorpd %xmm14, %xmm11 divsd %xmm5, %xmm11 movsd %xmm11, 1272(%rsp,%rax) movapd %xmm0, %xmm7 mulsd %xmm4, %xmm7 mulsd %xmm1, %xmm4 mulsd %xmm3, %xmm0 mulsd %xmm6, %xmm3 subsd %xmm3, %xmm4 divsd %xmm5, %xmm4 movsd %xmm4, 1232(%rsp,%rax) mulsd %xmm2, %xmm6 subsd %xmm6, %xmm7 xorpd %xmm14, %xmm7 divsd %xmm5, %xmm7 movsd %xmm7, 1256(%rsp,%rax) mulsd %xmm2, %xmm1 subsd %xmm1, %xmm0 divsd %xmm5, %xmm0 movsd %xmm0, 1280(%rsp,%rax) movsd %xmm5, 704(%rsp,%r14,8) incq %r14 movslq 8(%rsp), %rax addq $72, %r12 cmpq %rax, %r14 jl .LBB1_8 .LBB1_34: # %._crit_edge259 movl (%rsp), %ebx movslq %ebx, %rax movl 12(%rsp), %ebp movslq %ebp, %r12 imulq %rax, %r12 shlq $2, %r12 .Ltmp23: .cfi_escape 0x2e, 0x00 leaq 40(%rsp), %rdi movq %r12, %rsi callq hipMalloc .Ltmp24: # %bb.35: # %_ZL9hipMallocI15HIP_vector_typeIhLj4EEE10hipError_tPPT_m.exit testl %eax, %eax jne .LBB1_36 # %bb.49: movq 40(%rsp), %rdi .Ltmp28: .cfi_escape 0x2e, 0x00 movq 16(%rsp), %rsi # 8-byte Reload movq %r12, %rdx movl $1, %ecx callq hipMemcpy .Ltmp29: # %bb.50: testl %eax, %eax jne .LBB1_51 # %bb.54: .Ltmp33: .cfi_escape 0x2e, 0x00 leaq 192(%rsp), %rsi movl $avg_dev, %edi movl $768, %edx # imm = 0x300 xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol .Ltmp34: # %bb.55: # %_Z17hipMemcpyToSymbolIA32_15HIP_vector_typeIiLj4EEE10hipError_tRKT_PKvmm13hipMemcpyKind.exit testl %eax, %eax jne .LBB1_56 # %bb.59: .Ltmp38: .cfi_escape 0x2e, 0x00 leaq 1216(%rsp), %rsi movl $cov_inv_dev, %edi movl $2304, %edx # imm = 0x900 xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol .Ltmp39: # %bb.60: # %_Z17hipMemcpyToSymbolIA32_A3_A3_dE10hipError_tRKT_PKvmm13hipMemcpyKind.exit testl %eax, %eax jne .LBB1_61 # %bb.64: .Ltmp43: .cfi_escape 0x2e, 0x00 leaq 704(%rsp), %rsi movl $dets_dev, %edi movl $256, %edx # imm = 0x100 xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol .Ltmp44: # %bb.65: # %_Z17hipMemcpyToSymbolIA32_dE10hipError_tRKT_PKvmm13hipMemcpyKind.exit testl %eax, %eax jne .LBB1_66 # %bb.69: .Ltmp48: .cfi_escape 0x2e, 0x00 leaq 56(%rsp), %rdi callq hipEventCreate .Ltmp49: # %bb.70: .Ltmp50: .cfi_escape 0x2e, 0x00 leaq 32(%rsp), %rdi callq hipEventCreate .Ltmp51: # %bb.71: movq 56(%rsp), %rdi .Ltmp52: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp53: # %bb.72: .Ltmp54: .cfi_escape 0x2e, 0x00 movabsq $68719476752, %rdi # imm = 0x1000000010 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp55: # %bb.73: testl %eax, %eax jne .LBB1_76 # %bb.74: movq 40(%rsp), %rax movl 8(%rsp), %ecx movq %rax, 184(%rsp) movl %ebx, 76(%rsp) movl %ebp, 72(%rsp) movl %ecx, 68(%rsp) leaq 184(%rsp), %rax movq %rax, 80(%rsp) leaq 76(%rsp), %rax movq %rax, 88(%rsp) leaq 72(%rsp), %rax movq %rax, 96(%rsp) leaq 68(%rsp), %rax movq %rax, 104(%rsp) .Ltmp56: .cfi_escape 0x2e, 0x00 leaq 168(%rsp), %rdi leaq 152(%rsp), %rsi leaq 144(%rsp), %rdx leaq 136(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp57: # %bb.75: # %.noexc208 movq 168(%rsp), %rsi movl 176(%rsp), %edx movq 152(%rsp), %rcx movl 160(%rsp), %r8d .Ltmp58: .cfi_escape 0x2e, 0x10 leaq 80(%rsp), %r9 movl $_Z6kernelP15HIP_vector_typeIhLj4EEiii, %edi pushq 136(%rsp) .cfi_adjust_cfa_offset 8 pushq 152(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp59: .LBB1_76: movq 32(%rsp), %rdi .Ltmp60: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp61: # %bb.77: movq 32(%rsp), %rdi .Ltmp62: .cfi_escape 0x2e, 0x00 callq hipEventSynchronize .Ltmp63: # %bb.78: movq 56(%rsp), %rsi movq 32(%rsp), %rdx .Ltmp64: .cfi_escape 0x2e, 0x00 leaq 64(%rsp), %rdi callq hipEventElapsedTime .Ltmp65: # %bb.79: movq stderr(%rip), %rdi movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .cfi_escape 0x2e, 0x00 movl $.L.str.5, %esi movb $1, %al callq fprintf movq 32(%rsp), %rdi .Ltmp66: .cfi_escape 0x2e, 0x00 callq hipEventDestroy .Ltmp67: # %bb.80: movq 56(%rsp), %rdi .Ltmp68: .cfi_escape 0x2e, 0x00 callq hipEventDestroy .Ltmp69: # %bb.81: movq 40(%rsp), %rsi .Ltmp70: .cfi_escape 0x2e, 0x00 movq 16(%rsp), %rdi # 8-byte Reload movq %r12, %rdx movl $2, %ecx callq hipMemcpy .Ltmp71: # %bb.82: testl %eax, %eax jne .LBB1_83 # %bb.86: .cfi_escape 0x2e, 0x00 leaq 960(%rsp), %rdi movl $.L.str.6, %esi callq fopen movq %rax, %rbx .cfi_escape 0x2e, 0x00 movq %rsp, %rdi movl $4, %esi movl $1, %edx movq %rax, %rcx callq fwrite .cfi_escape 0x2e, 0x00 leaq 12(%rsp), %rdi movl $4, %esi movl $1, %edx movq %rbx, %rcx callq fwrite movslq (%rsp), %rax movslq 12(%rsp), %rdx imulq %rax, %rdx .cfi_escape 0x2e, 0x00 movl $4, %esi movq 16(%rsp), %rdi # 8-byte Reload movq %rbx, %rcx callq fwrite .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq fclose movq 40(%rsp), %rdi .Ltmp75: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp76: # %bb.87: .cfi_escape 0x2e, 0x00 movq 16(%rsp), %rdi # 8-byte Reload callq free cmpq 24(%rsp), %r15 # 8-byte Folded Reload je .LBB1_92 # %bb.88: # %.lr.ph.i.i.i.i.preheader movq %r15, %rbx jmp .LBB1_89 .p2align 4, 0x90 .LBB1_91: # %_ZSt8_DestroyISt6vectorI3pntSaIS1_EEEvPT_.exit.i.i.i.i # in Loop: Header=BB1_89 Depth=1 addq $24, %rbx cmpq 24(%rsp), %rbx # 8-byte Folded Reload je .LBB1_92 .LBB1_89: # %.lr.ph.i.i.i.i # =>This Inner Loop Header: Depth=1 movq (%rbx), %rdi testq %rdi, %rdi je .LBB1_91 # %bb.90: # in Loop: Header=BB1_89 Depth=1 .cfi_escape 0x2e, 0x00 callq _ZdlPv jmp .LBB1_91 .LBB1_92: # %_ZSt8_DestroyIPSt6vectorI3pntSaIS1_EES3_EvT_S5_RSaIT0_E.exit.i testq %r15, %r15 je .LBB1_94 # %bb.93: .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .LBB1_94: # %_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev.exit xorl %eax, %eax addq $6088, %rsp # imm = 0x17C8 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_105: # %.noexc .cfi_def_cfa_offset 6144 .cfi_escape 0x2e, 0x00 movl $.L.str.7, %edi callq _ZSt20__throw_length_errorPKc .LBB1_36: movq stderr(%rip), %rbx .Ltmp25: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp26: # %bb.37: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $.L.str.4, %edx movq %rbx, %rdi movl $160, %ecx jmp .LBB1_38 .LBB1_51: movq stderr(%rip), %rbx .Ltmp30: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp31: # %bb.52: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $.L.str.4, %edx movq %rbx, %rdi movl $161, %ecx jmp .LBB1_38 .LBB1_56: movq stderr(%rip), %rbx .Ltmp35: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp36: # %bb.57: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $.L.str.4, %edx movq %rbx, %rdi movl $163, %ecx jmp .LBB1_38 .LBB1_61: movq stderr(%rip), %rbx .Ltmp40: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp41: # %bb.62: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $.L.str.4, %edx movq %rbx, %rdi movl $164, %ecx jmp .LBB1_38 .LBB1_66: movq stderr(%rip), %rbx .Ltmp45: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp46: # %bb.67: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $.L.str.4, %edx movq %rbx, %rdi movl $165, %ecx .LBB1_38: movq %rax, %r8 xorl %eax, %eax callq fprintf .cfi_escape 0x2e, 0x00 xorl %edi, %edi callq exit .LBB1_83: movq stderr(%rip), %rbx .Ltmp72: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp73: # %bb.84: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $.L.str.4, %edx movq %rbx, %rdi movl $182, %ecx jmp .LBB1_38 .LBB1_85: .Ltmp74: jmp .LBB1_96 .LBB1_68: .Ltmp47: jmp .LBB1_96 .LBB1_63: .Ltmp42: jmp .LBB1_96 .LBB1_58: .Ltmp37: jmp .LBB1_96 .LBB1_53: .Ltmp32: jmp .LBB1_96 .LBB1_48: .Ltmp27: jmp .LBB1_96 .LBB1_95: .Ltmp77: jmp .LBB1_96 .LBB1_39: .Ltmp4: .LBB1_96: movq %rax, %rbx jmp .LBB1_97 .LBB1_47: .Ltmp22: jmp .LBB1_46 .LBB1_45: .Ltmp9: .LBB1_46: movq %rax, %rbx movq 48(%rsp), %r15 # 8-byte Reload .LBB1_97: cmpq 24(%rsp), %r15 # 8-byte Folded Reload jne .LBB1_98 .LBB1_102: # %_ZSt8_DestroyIPSt6vectorI3pntSaIS1_EES3_EvT_S5_RSaIT0_E.exit.i217 testq %r15, %r15 je .LBB1_104 # %bb.103: .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .LBB1_104: # %_ZNSt6vectorIS_I3pntSaIS0_EESaIS2_EED2Ev.exit219 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _Unwind_Resume@PLT .LBB1_98: # %.lr.ph.i.i.i.i212.preheader movq %r15, %r14 jmp .LBB1_99 .p2align 4, 0x90 .LBB1_101: # %_ZSt8_DestroyISt6vectorI3pntSaIS1_EEEvPT_.exit.i.i.i.i215 # in Loop: Header=BB1_99 Depth=1 addq $24, %r14 cmpq 24(%rsp), %r14 # 8-byte Folded Reload je .LBB1_102 .LBB1_99: # %.lr.ph.i.i.i.i212 # =>This Inner Loop Header: Depth=1 movq (%r14), %rdi testq %rdi, %rdi je .LBB1_101 # %bb.100: # in Loop: Header=BB1_99 Depth=1 .cfi_escape 0x2e, 0x00 callq _ZdlPv jmp .LBB1_101 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table1: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3 .uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4 .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8 .uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9 .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp21-.Ltmp10 # Call between .Ltmp10 and .Ltmp21 .uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22 .byte 0 # On action: cleanup .uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24 .uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27 .byte 0 # On action: cleanup .uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29 .uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32 .byte 0 # On action: cleanup .uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34 .uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37 .byte 0 # On action: cleanup .uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39 .uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42 .byte 0 # On action: cleanup .uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44 .uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47 .byte 0 # On action: cleanup .uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp69-.Ltmp48 # Call between .Ltmp48 and .Ltmp69 .uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77 .byte 0 # On action: cleanup .uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71 .uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74 .byte 0 # On action: cleanup .uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp76-.Ltmp75 # Call between .Ltmp75 and .Ltmp76 .uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77 .byte 0 # On action: cleanup .uleb128 .Ltmp76-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp25-.Ltmp76 # Call between .Ltmp76 and .Ltmp25 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26 .uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27 .byte 0 # On action: cleanup .uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31 .uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32 .byte 0 # On action: cleanup .uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36 .uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37 .byte 0 # On action: cleanup .uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41 .uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42 .byte 0 # On action: cleanup .uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 18 << .uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46 .uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47 .byte 0 # On action: cleanup .uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 19 << .uleb128 .Ltmp73-.Ltmp72 # Call between .Ltmp72 and .Ltmp73 .uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74 .byte 0 # On action: cleanup .uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 20 << .uleb128 .Lfunc_end1-.Ltmp73 # Call between .Ltmp73 and .Lfunc_end1 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .section .text._ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm,comdat .weak _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm # -- Begin function _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm .p2align 4, 0x90 .type _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm,@function _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm: # @_ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 testq %rsi, %rsi je .LBB2_19 # %bb.1: movq %rsi, %rbx movq 8(%rdi), %r14 movq 16(%rdi), %rax subq %r14, %rax sarq $3, %rax cmpq %rsi, %rax jae .LBB2_2 # %bb.7: movabsq $1152921504606846975, %rax # imm = 0xFFFFFFFFFFFFFFF movq (%rdi), %rcx movq %rcx, 16(%rsp) # 8-byte Spill subq %rcx, %r14 movq %r14, %r15 sarq $3, %r15 movq %r15, %rcx xorq %rax, %rcx cmpq %rbx, %rcx jb .LBB2_20 # %bb.8: # %_ZNKSt6vectorI3pntSaIS0_EE12_M_check_lenEmPKc.exit movq %rdi, 8(%rsp) # 8-byte Spill cmpq %rbx, %r15 movq %rbx, %rcx cmovaq %r15, %rcx leaq (%rcx,%r15), %r13 cmpq %rax, %r13 cmovaeq %rax, %r13 addq %r15, %rcx cmovbq %rax, %r13 testq %r13, %r13 je .LBB2_9 # %bb.10: leaq (,%r13,8), %rdi callq _Znwm movq %rax, %r12 jmp .LBB2_11 .LBB2_2: movq $0, (%r14) cmpq $1, %rbx jne .LBB2_4 # %bb.3: addq $8, %r14 movq %r14, %rax movq %r14, 8(%rdi) jmp .LBB2_19 .LBB2_4: leaq (%r14,%rbx,8), %rax shlq $3, %rbx movl $8, %ecx .p2align 4, 0x90 .LBB2_5: # %.lr.ph.i.i.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movq (%r14), %rdx movq %rdx, (%r14,%rcx) addq $8, %rcx cmpq %rcx, %rbx jne .LBB2_5 # %bb.6: # %_ZSt27__uninitialized_default_n_aIP3pntmS0_ET_S2_T0_RSaIT1_E.exit movq %rax, 8(%rdi) jmp .LBB2_19 .LBB2_9: xorl %r12d, %r12d .LBB2_11: # %_ZNSt12_Vector_baseI3pntSaIS0_EE11_M_allocateEm.exit leaq (%r12,%r15,8), %rbp movq $0, (%r12,%r15,8) cmpq $1, %rbx je .LBB2_14 # %bb.12: leaq (,%rbx,8), %rax movl $8, %ecx .p2align 4, 0x90 .LBB2_13: # %.lr.ph.i.i.i.i.i.i.i30 # =>This Inner Loop Header: Depth=1 movq (%rbp), %rdx movq %rdx, (%rbp,%rcx) addq $8, %rcx cmpq %rcx, %rax jne .LBB2_13 .LBB2_14: # %_ZSt27__uninitialized_default_n_aIP3pntmS0_ET_S2_T0_RSaIT1_E.exit34 testq %r14, %r14 movq 16(%rsp), %r15 # 8-byte Reload jle .LBB2_16 # %bb.15: movq %r12, %rdi movq %r15, %rsi movq %r14, %rdx callq memmove@PLT .LBB2_16: # %_ZNSt6vectorI3pntSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit testq %r15, %r15 je .LBB2_18 # %bb.17: movq %r15, %rdi callq _ZdlPv .LBB2_18: # %_ZNSt12_Vector_baseI3pntSaIS0_EE13_M_deallocateEPS0_m.exit37 movq 8(%rsp), %rax # 8-byte Reload movq %r12, (%rax) leaq (,%rbx,8), %rcx addq %rbp, %rcx movq %rcx, 8(%rax) leaq (%r12,%r13,8), %rcx movq %rcx, 16(%rax) .LBB2_19: addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_20: .cfi_def_cfa_offset 80 movl $.L.str.8, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end2: .size _ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm, .Lfunc_end2-_ZNSt6vectorI3pntSaIS0_EE17_M_default_appendEm .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx subq $32, %rsp .cfi_adjust_cfa_offset 32 xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6kernelP15HIP_vector_typeIhLj4EEiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction addq $32, %rsp .cfi_adjust_cfa_offset -32 movl $avg_dev, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movl $512, %r9d # imm = 0x200 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $cov_inv_dev, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movl $2304, %r9d # imm = 0x900 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $dets_dev, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movl $256, %r9d # imm = 0x100 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq __hipRegisterVar addq $16, %rsp .cfi_adjust_cfa_offset -16 movl $__hip_module_dtor, %edi popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type avg_dev,@object # @avg_dev .local avg_dev .comm avg_dev,512,16 .type cov_inv_dev,@object # @cov_inv_dev .local cov_inv_dev .comm cov_inv_dev,2304,16 .type dets_dev,@object # @dets_dev .local dets_dev .comm dets_dev,256,16 .type _Z6kernelP15HIP_vector_typeIhLj4EEiii,@object # @_Z6kernelP15HIP_vector_typeIhLj4EEiii .section .rodata,"a",@progbits .globl _Z6kernelP15HIP_vector_typeIhLj4EEiii .p2align 3, 0x0 _Z6kernelP15HIP_vector_typeIhLj4EEiii: .quad _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii .size _Z6kernelP15HIP_vector_typeIhLj4EEiii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "rb" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " " .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\n" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "ERROR in %s:%d. Message: %s\n" .size .L.str.3, 29 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ArtDu/PGP/master/labs/lab3/main.hip" .size .L.str.4, 93 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "%.2f\n" .size .L.str.5, 6 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "wb" .size .L.str.6, 3 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "cannot create std::vector larger than max_size()" .size .L.str.7, 49 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "vector::_M_default_append" .size .L.str.8, 26 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6kernelP15HIP_vector_typeIhLj4EEiii" .size .L__unnamed_1, 38 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "avg_dev" .size .L__unnamed_2, 8 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "cov_inv_dev" .size .L__unnamed_3, 12 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "dets_dev" .size .L__unnamed_4, 9 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__kernelP15HIP_vector_typeIhLj4EEiii .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym avg_dev .addrsig_sym cov_inv_dev .addrsig_sym dets_dev .addrsig_sym _Z6kernelP15HIP_vector_typeIhLj4EEiii .addrsig_sym _ZSt3cin .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
// // include files // #include <stdlib.h> #include <stdio.h> #include <string.h> #include <math.h> //#include <cutil_inline.h> #include "cuda_runtime.h" //#include "MyFirst_kernel.cu" __global__ void my_first_kernel(float *x) { // Uncomment line below and define integer "tid" as global index to vector "x" int tid = blockIdx.x * blockDim.x + threadIdx.x; // Uncomment line below and define x[tid] to be equal to the thread index x[tid] = (float)threadIdx.x; } // // main host code // int main(int argc, char **argv) { float *h_x, *d_x; int nblocks, nthreads, nsize, n; // set number of blocks, and threads per block nblocks = 2; nthreads = 16; nsize = nblocks*nthreads; // allocate memory for array h_x = (float *)malloc(nsize*sizeof(float)); cudaMalloc((void **)&d_x, nsize*sizeof(float)); // execute kernel my_first_kernel<<<nblocks,nthreads>>>(d_x); // copy results from device to host cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost); // print results for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]); // check results float sumcheck = 0.; float sumcheckcorrect = 0.; for (int i = 0; i < nblocks * nthreads; ++i) { sumcheck += h_x[i]; } for (int j=0; j<nthreads; ++j) { sumcheckcorrect += j; } sumcheckcorrect *= 2; if (fabs(sumcheck-sumcheckcorrect)<1e-6) { printf("PASSED!\n"); } else { printf("FAILED!\n"); } // free memory cudaFree(d_x); free(h_x); return 0; }
code for sm_80 Function : _Z15my_first_kernelPf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e620000002500 */ /*0050*/ I2F.U32 R5, R7 ; /* 0x0000000700057306 */ /* 0x001e220000201000 */ /*0060*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */ /* 0x002fca00078e0207 */ /*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fca00078e0203 */ /*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101904 */ /*0090*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
// // include files // #include <stdlib.h> #include <stdio.h> #include <string.h> #include <math.h> //#include <cutil_inline.h> #include "cuda_runtime.h" //#include "MyFirst_kernel.cu" __global__ void my_first_kernel(float *x) { // Uncomment line below and define integer "tid" as global index to vector "x" int tid = blockIdx.x * blockDim.x + threadIdx.x; // Uncomment line below and define x[tid] to be equal to the thread index x[tid] = (float)threadIdx.x; } // // main host code // int main(int argc, char **argv) { float *h_x, *d_x; int nblocks, nthreads, nsize, n; // set number of blocks, and threads per block nblocks = 2; nthreads = 16; nsize = nblocks*nthreads; // allocate memory for array h_x = (float *)malloc(nsize*sizeof(float)); cudaMalloc((void **)&d_x, nsize*sizeof(float)); // execute kernel my_first_kernel<<<nblocks,nthreads>>>(d_x); // copy results from device to host cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost); // print results for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]); // check results float sumcheck = 0.; float sumcheckcorrect = 0.; for (int i = 0; i < nblocks * nthreads; ++i) { sumcheck += h_x[i]; } for (int j=0; j<nthreads; ++j) { sumcheckcorrect += j; } sumcheckcorrect *= 2; if (fabs(sumcheck-sumcheckcorrect)<1e-6) { printf("PASSED!\n"); } else { printf("FAILED!\n"); } // free memory cudaFree(d_x); free(h_x); return 0; }
.file "tmpxft_000d0f9f_00000000-6_MyFirst.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z15my_first_kernelPfPf .type _Z35__device_stub__Z15my_first_kernelPfPf, @function _Z35__device_stub__Z15my_first_kernelPfPf: .LFB2082: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z15my_first_kernelPf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf .globl _Z15my_first_kernelPf .type _Z15my_first_kernelPf, @function _Z15my_first_kernelPf: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z15my_first_kernelPfPf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string " n, x = %d %f \n" .LC4: .string "PASSED!\n" .LC5: .string "FAILED!\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $128, %edi call malloc@PLT movq %rax, %rbp leaq 8(%rsp), %rdi movl $128, %esi call cudaMalloc@PLT movl $16, 28(%rsp) movl $1, 32(%rsp) movl $2, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L26 .L12: movl $2, %ecx movl $128, %edx movq 8(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl $0, %ebx leaq .LC1(%rip), %r12 .L13: pxor %xmm0, %xmm0 cvtss2sd 0(%rbp,%rbx,4), %xmm0 movl %ebx, %edx movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $32, %rbx jne .L13 movq %rbp, %rax leaq 128(%rbp), %rdx pxor %xmm0, %xmm0 .L14: addss (%rax), %xmm0 addq $4, %rax cmpq %rax, %rdx jne .L14 movl $0, %eax pxor %xmm1, %xmm1 .L15: pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 addss %xmm2, %xmm1 addl $1, %eax cmpl $16, %eax jne .L15 addss %xmm1, %xmm1 subss %xmm1, %xmm0 andps .LC2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movsd .LC3(%rip), %xmm1 comisd %xmm0, %xmm1 jbe .L24 leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L18: movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L27 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state movq 8(%rsp), %rdi call _Z35__device_stub__Z15my_first_kernelPfPf jmp .L12 .L24: leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L18 .L27: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z15my_first_kernelPf" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z15my_first_kernelPf(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC2: .long 2147483647 .long 0 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long -1598689907 .long 1051772663 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
// // include files // #include <stdlib.h> #include <stdio.h> #include <string.h> #include <math.h> //#include <cutil_inline.h> #include "cuda_runtime.h" //#include "MyFirst_kernel.cu" __global__ void my_first_kernel(float *x) { // Uncomment line below and define integer "tid" as global index to vector "x" int tid = blockIdx.x * blockDim.x + threadIdx.x; // Uncomment line below and define x[tid] to be equal to the thread index x[tid] = (float)threadIdx.x; } // // main host code // int main(int argc, char **argv) { float *h_x, *d_x; int nblocks, nthreads, nsize, n; // set number of blocks, and threads per block nblocks = 2; nthreads = 16; nsize = nblocks*nthreads; // allocate memory for array h_x = (float *)malloc(nsize*sizeof(float)); cudaMalloc((void **)&d_x, nsize*sizeof(float)); // execute kernel my_first_kernel<<<nblocks,nthreads>>>(d_x); // copy results from device to host cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost); // print results for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]); // check results float sumcheck = 0.; float sumcheckcorrect = 0.; for (int i = 0; i < nblocks * nthreads; ++i) { sumcheck += h_x[i]; } for (int j=0; j<nthreads; ++j) { sumcheckcorrect += j; } sumcheckcorrect *= 2; if (fabs(sumcheck-sumcheckcorrect)<1e-6) { printf("PASSED!\n"); } else { printf("FAILED!\n"); } // free memory cudaFree(d_x); free(h_x); return 0; }
// // include files // #include <stdlib.h> #include <stdio.h> #include <string.h> #include <math.h> //#include <cutil_inline.h> #include "hip/hip_runtime.h" //#include "MyFirst_kernel.cu" __global__ void my_first_kernel(float *x) { // Uncomment line below and define integer "tid" as global index to vector "x" int tid = blockIdx.x * blockDim.x + threadIdx.x; // Uncomment line below and define x[tid] to be equal to the thread index x[tid] = (float)threadIdx.x; } // // main host code // int main(int argc, char **argv) { float *h_x, *d_x; int nblocks, nthreads, nsize, n; // set number of blocks, and threads per block nblocks = 2; nthreads = 16; nsize = nblocks*nthreads; // allocate memory for array h_x = (float *)malloc(nsize*sizeof(float)); hipMalloc((void **)&d_x, nsize*sizeof(float)); // execute kernel my_first_kernel<<<nblocks,nthreads>>>(d_x); // copy results from device to host hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost); // print results for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]); // check results float sumcheck = 0.; float sumcheckcorrect = 0.; for (int i = 0; i < nblocks * nthreads; ++i) { sumcheck += h_x[i]; } for (int j=0; j<nthreads; ++j) { sumcheckcorrect += j; } sumcheckcorrect *= 2; if (fabs(sumcheck-sumcheckcorrect)<1e-6) { printf("PASSED!\n"); } else { printf("FAILED!\n"); } // free memory hipFree(d_x); free(h_x); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
// // include files // #include <stdlib.h> #include <stdio.h> #include <string.h> #include <math.h> //#include <cutil_inline.h> #include "hip/hip_runtime.h" //#include "MyFirst_kernel.cu" __global__ void my_first_kernel(float *x) { // Uncomment line below and define integer "tid" as global index to vector "x" int tid = blockIdx.x * blockDim.x + threadIdx.x; // Uncomment line below and define x[tid] to be equal to the thread index x[tid] = (float)threadIdx.x; } // // main host code // int main(int argc, char **argv) { float *h_x, *d_x; int nblocks, nthreads, nsize, n; // set number of blocks, and threads per block nblocks = 2; nthreads = 16; nsize = nblocks*nthreads; // allocate memory for array h_x = (float *)malloc(nsize*sizeof(float)); hipMalloc((void **)&d_x, nsize*sizeof(float)); // execute kernel my_first_kernel<<<nblocks,nthreads>>>(d_x); // copy results from device to host hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost); // print results for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]); // check results float sumcheck = 0.; float sumcheckcorrect = 0.; for (int i = 0; i < nblocks * nthreads; ++i) { sumcheck += h_x[i]; } for (int j=0; j<nthreads; ++j) { sumcheckcorrect += j; } sumcheckcorrect *= 2; if (fabs(sumcheck-sumcheckcorrect)<1e-6) { printf("PASSED!\n"); } else { printf("FAILED!\n"); } // free memory hipFree(d_x); free(h_x); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15my_first_kernelPf .globl _Z15my_first_kernelPf .p2align 8 .type _Z15my_first_kernelPf,@function _Z15my_first_kernelPf: s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 v_cvt_f32_u32_e32 v3, v0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v0, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo global_store_b32 v[0:1], v3, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15my_first_kernelPf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15my_first_kernelPf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15my_first_kernelPf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
// // include files // #include <stdlib.h> #include <stdio.h> #include <string.h> #include <math.h> //#include <cutil_inline.h> #include "hip/hip_runtime.h" //#include "MyFirst_kernel.cu" __global__ void my_first_kernel(float *x) { // Uncomment line below and define integer "tid" as global index to vector "x" int tid = blockIdx.x * blockDim.x + threadIdx.x; // Uncomment line below and define x[tid] to be equal to the thread index x[tid] = (float)threadIdx.x; } // // main host code // int main(int argc, char **argv) { float *h_x, *d_x; int nblocks, nthreads, nsize, n; // set number of blocks, and threads per block nblocks = 2; nthreads = 16; nsize = nblocks*nthreads; // allocate memory for array h_x = (float *)malloc(nsize*sizeof(float)); hipMalloc((void **)&d_x, nsize*sizeof(float)); // execute kernel my_first_kernel<<<nblocks,nthreads>>>(d_x); // copy results from device to host hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost); // print results for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]); // check results float sumcheck = 0.; float sumcheckcorrect = 0.; for (int i = 0; i < nblocks * nthreads; ++i) { sumcheck += h_x[i]; } for (int j=0; j<nthreads; ++j) { sumcheckcorrect += j; } sumcheckcorrect *= 2; if (fabs(sumcheck-sumcheckcorrect)<1e-6) { printf("PASSED!\n"); } else { printf("FAILED!\n"); } // free memory hipFree(d_x); free(h_x); return 0; }
.text .file "MyFirst.hip" .globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf .p2align 4, 0x90 .type _Z30__device_stub__my_first_kernelPf,@function _Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z15my_first_kernelPf, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_1: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $128, %edi callq malloc movq %rax, %rbx leaq 8(%rsp), %rdi movl $128, %esi callq hipMalloc movabsq $4294967298, %rdi # imm = 0x100000002 leaq 14(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 16(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z15my_first_kernelPf, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movl $128, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # =>This Inner Loop Header: Depth=1 movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movl %r14d, %esi movb $1, %al callq printf incq %r14 cmpq $32, %r14 jne .LBB1_3 # %bb.4: # %.preheader39.preheader xorps %xmm0, %xmm0 xorl %eax, %eax .p2align 4, 0x90 .LBB1_5: # %.preheader39 # =>This Inner Loop Header: Depth=1 addss (%rbx,%rax,4), %xmm0 incq %rax cmpq $32, %rax jne .LBB1_5 # %bb.6: # %.preheader.preheader xorps %xmm1, %xmm1 xorl %eax, %eax .p2align 4, 0x90 .LBB1_7: # %.preheader # =>This Inner Loop Header: Depth=1 xorps %xmm2, %xmm2 cvtsi2ss %eax, %xmm2 addss %xmm2, %xmm1 incl %eax cmpl $16, %eax jne .LBB1_7 # %bb.8: addss %xmm1, %xmm1 subss %xmm1, %xmm0 andps .LCPI1_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero ucomisd %xmm0, %xmm1 movl $.Lstr.1, %eax movl $.Lstr, %edi cmovaq %rax, %rdi callq puts@PLT movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15my_first_kernelPf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf .section .rodata,"a",@progbits .globl _Z15my_first_kernelPf .p2align 3, 0x0 _Z15my_first_kernelPf: .quad _Z30__device_stub__my_first_kernelPf .size _Z15my_first_kernelPf, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " n, x = %d %f \n" .size .L.str, 20 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15my_first_kernelPf" .size .L__unnamed_1, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "FAILED!" .size .Lstr, 8 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "PASSED!" .size .Lstr.1, 8 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__my_first_kernelPf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15my_first_kernelPf .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z15my_first_kernelPf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e620000002500 */ /*0050*/ I2F.U32 R5, R7 ; /* 0x0000000700057306 */ /* 0x001e220000201000 */ /*0060*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */ /* 0x002fca00078e0207 */ /*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fca00078e0203 */ /*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101904 */ /*0090*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15my_first_kernelPf .globl _Z15my_first_kernelPf .p2align 8 .type _Z15my_first_kernelPf,@function _Z15my_first_kernelPf: s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 v_cvt_f32_u32_e32 v3, v0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v0, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo global_store_b32 v[0:1], v3, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15my_first_kernelPf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15my_first_kernelPf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15my_first_kernelPf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000d0f9f_00000000-6_MyFirst.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z15my_first_kernelPfPf .type _Z35__device_stub__Z15my_first_kernelPfPf, @function _Z35__device_stub__Z15my_first_kernelPfPf: .LFB2082: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z15my_first_kernelPf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf .globl _Z15my_first_kernelPf .type _Z15my_first_kernelPf, @function _Z15my_first_kernelPf: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z15my_first_kernelPfPf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string " n, x = %d %f \n" .LC4: .string "PASSED!\n" .LC5: .string "FAILED!\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $128, %edi call malloc@PLT movq %rax, %rbp leaq 8(%rsp), %rdi movl $128, %esi call cudaMalloc@PLT movl $16, 28(%rsp) movl $1, 32(%rsp) movl $2, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L26 .L12: movl $2, %ecx movl $128, %edx movq 8(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl $0, %ebx leaq .LC1(%rip), %r12 .L13: pxor %xmm0, %xmm0 cvtss2sd 0(%rbp,%rbx,4), %xmm0 movl %ebx, %edx movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $32, %rbx jne .L13 movq %rbp, %rax leaq 128(%rbp), %rdx pxor %xmm0, %xmm0 .L14: addss (%rax), %xmm0 addq $4, %rax cmpq %rax, %rdx jne .L14 movl $0, %eax pxor %xmm1, %xmm1 .L15: pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 addss %xmm2, %xmm1 addl $1, %eax cmpl $16, %eax jne .L15 addss %xmm1, %xmm1 subss %xmm1, %xmm0 andps .LC2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movsd .LC3(%rip), %xmm1 comisd %xmm0, %xmm1 jbe .L24 leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L18: movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L27 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state movq 8(%rsp), %rdi call _Z35__device_stub__Z15my_first_kernelPfPf jmp .L12 .L24: leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L18 .L27: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z15my_first_kernelPf" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z15my_first_kernelPf(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC2: .long 2147483647 .long 0 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long -1598689907 .long 1051772663 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "MyFirst.hip" .globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf .p2align 4, 0x90 .type _Z30__device_stub__my_first_kernelPf,@function _Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z15my_first_kernelPf, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_1: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $128, %edi callq malloc movq %rax, %rbx leaq 8(%rsp), %rdi movl $128, %esi callq hipMalloc movabsq $4294967298, %rdi # imm = 0x100000002 leaq 14(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 16(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z15my_first_kernelPf, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movl $128, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # =>This Inner Loop Header: Depth=1 movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movl %r14d, %esi movb $1, %al callq printf incq %r14 cmpq $32, %r14 jne .LBB1_3 # %bb.4: # %.preheader39.preheader xorps %xmm0, %xmm0 xorl %eax, %eax .p2align 4, 0x90 .LBB1_5: # %.preheader39 # =>This Inner Loop Header: Depth=1 addss (%rbx,%rax,4), %xmm0 incq %rax cmpq $32, %rax jne .LBB1_5 # %bb.6: # %.preheader.preheader xorps %xmm1, %xmm1 xorl %eax, %eax .p2align 4, 0x90 .LBB1_7: # %.preheader # =>This Inner Loop Header: Depth=1 xorps %xmm2, %xmm2 cvtsi2ss %eax, %xmm2 addss %xmm2, %xmm1 incl %eax cmpl $16, %eax jne .LBB1_7 # %bb.8: addss %xmm1, %xmm1 subss %xmm1, %xmm0 andps .LCPI1_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero ucomisd %xmm0, %xmm1 movl $.Lstr.1, %eax movl $.Lstr, %edi cmovaq %rax, %rdi callq puts@PLT movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15my_first_kernelPf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf .section .rodata,"a",@progbits .globl _Z15my_first_kernelPf .p2align 3, 0x0 _Z15my_first_kernelPf: .quad _Z30__device_stub__my_first_kernelPf .size _Z15my_first_kernelPf, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " n, x = %d %f \n" .size .L.str, 20 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15my_first_kernelPf" .size .L__unnamed_1, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "FAILED!" .size .Lstr, 8 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "PASSED!" .size .Lstr.1, 8 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__my_first_kernelPf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15my_first_kernelPf .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00040c05_00000000-6_oFAST.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2065: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2065: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z8calcMaskPKiiiRtS1_ .type _Z8calcMaskPKiiiRtS1_, @function _Z8calcMaskPKiiiRtS1_: .LFB2059: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2059: .size _Z8calcMaskPKiiiRtS1_, .-_Z8calcMaskPKiiiRtS1_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "oFAST Module active!\n" .text .globl _Z20pipeline_print_oFASTv .type _Z20pipeline_print_oFASTv, @function _Z20pipeline_print_oFASTv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _Z20pipeline_print_oFASTv, .-_Z20pipeline_print_oFASTv .globl _Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_ .type _Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_, @function _Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_: .LFB2087: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movl %esi, 52(%rsp) movl %edx, 48(%rsp) movl %ecx, 44(%rsp) movq %r8, 32(%rsp) movl %r9d, 40(%rsp) movq 248(%rsp), %rax movq %rax, 24(%rsp) movq 256(%rsp), %rax movq %rax, 16(%rsp) movq 264(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 52(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rax movq %rax, 144(%rsp) leaq 44(%rsp), %rax movq %rax, 152(%rsp) leaq 32(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 240(%rsp), %rax movq %rax, 176(%rsp) leaq 24(%rsp), %rax movq %rax, 184(%rsp) leaq 16(%rsp), %rax movq %rax, 192(%rsp) leaq 8(%rsp), %rax movq %rax, 200(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 216(%rsp), %rax subq %fs:40, %rax jne .L12 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z13calcKeyPointsPhiiiPfiiPiS1_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_, .-_Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_ .globl _Z13calcKeyPointsPhiiiPfiiPiS1_S_ .type _Z13calcKeyPointsPhiiiPfiiPiS1_S_, @function _Z13calcKeyPointsPhiiiPfiiPiS1_S_: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pushq 40(%rsp) .cfi_def_cfa_offset 24 pushq 40(%rsp) .cfi_def_cfa_offset 32 pushq 40(%rsp) .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_ addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z13calcKeyPointsPhiiiPfiiPiS1_S_, .-_Z13calcKeyPointsPhiiiPfiiPiS1_S_ .globl _Z9gpu_oFASTPhiiiP6float4iiPiS2_ .type _Z9gpu_oFASTPhiiiP6float4iiPiS2_, @function _Z9gpu_oFASTPhiiiP6float4iiPiS2_: .LFB2061: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %rdi, 16(%rsp) movl %esi, %ebx movl %edx, %ebp movl %ecx, 28(%rsp) movq %r8, 8(%rsp) movl %r9d, %r13d movq 152(%rsp), %r14 movq 160(%rsp), %r15 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 56(%rsp) movl $1, 68(%rsp) leal 56(%rsi), %eax movl %esi, %edx addl $25, %edx cmovns %edx, %eax sarl $5, %eax movl %eax, 60(%rsp) leal 8(%rbp), %eax movl %ebp, %edx addl $1, %edx cmovns %edx, %eax sarl $3, %eax movl %eax, 64(%rsp) leaq 32(%rsp), %rdi movl $1, %edx movl $8129, %esi call cudaMallocManaged@PLT movl $0, %eax leaq _ZL7c_table(%rip), %rsi .L16: movzbl (%rsi,%rax), %ecx movq 32(%rsp), %rdx movb %cl, (%rdx,%rax) addq $1, %rax cmpq $8129, %rax jne .L16 movl %r13d, %r12d imull 144(%rsp), %r12d imull $100, %r12d, %esi movslq %esi, %rsi salq $2, %rsi leaq 40(%rsp), %rdi movl $1, %edx call cudaMallocManaged@PLT movl $32, 48(%rsp) movl $8, 52(%rsp) movl 56(%rsp), %ecx movl $0, %r9d movl $8129, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L25 .L17: call cudaDeviceSynchronize@PLT testl %r12d, %r12d jle .L15 movq 8(%rsp), %rsi movq 40(%rsp), %rax leaq 384(%rax), %rcx leal (%r12,%r12,2), %r8d sall $3, %r8d movl $0, %edi .L19: leaq -384(%rcx), %rax movq %rsi, %rdx .L20: movss 12(%rax), %xmm0 movss 8(%rax), %xmm1 movss 4(%rax), %xmm2 movss (%rax), %xmm3 movss %xmm3, (%rdx) movss %xmm2, 4(%rdx) movss %xmm1, 8(%rdx) movss %xmm0, 12(%rdx) addq $16, %rax addq $16, %rdx cmpq %rcx, %rax jne .L20 addq $384, %rsi addl $24, %edi addq $400, %rcx cmpl %r8d, %edi jne .L19 .L15: movq 72(%rsp), %rax subq %fs:40, %rax jne .L26 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state pushq 32(%rsp) .cfi_def_cfa_offset 152 pushq %r15 .cfi_def_cfa_offset 160 pushq %r14 .cfi_def_cfa_offset 168 movl 168(%rsp), %eax pushq %rax .cfi_def_cfa_offset 176 movl %r13d, %r9d movq 72(%rsp), %r8 movl 60(%rsp), %ecx movl %ebp, %edx movl %ebx, %esi movq 48(%rsp), %rdi call _Z47__device_stub__Z13calcKeyPointsPhiiiPfiiPiS1_S_PhiiiPfiiPiS1_S_ addq $32, %rsp .cfi_def_cfa_offset 144 jmp .L17 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z9gpu_oFASTPhiiiP6float4iiPiS2_, .-_Z9gpu_oFASTPhiiiP6float4iiPiS2_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_Z13calcKeyPointsPhiiiPfiiPiS1_S_" .section .rodata.str1.1 .LC2: .string "g_counter" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2090: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z13calcKeyPointsPhiiiPfiiPiS1_S_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL9g_counter(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL9g_counter .comm _ZL9g_counter,4,4 .section .rodata .align 32 .type _ZL7c_table, @object .size _ZL7c_table, 8129 _ZL7c_table: .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377\377\377\377\377\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377\377" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\360" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\300" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\200" .string "" .string "" .string "" .string "" .string "" .string "" .string "\377" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\300" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\200" .string "" .string "" .string "\360" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .string "\200" .ascii "\300\200\200\200\200\200\200\200\200\200\200\200\200\200\200" .ascii "\200\200\200\200\200\200\200\200\200\200\200\200\200\200\200" .ascii "\200\200\200\200\200\200\200\200\200\200\200\200\200\200\200" .ascii "\200\200\200\200\200\200\200\200\200\200\200\200\200\200\200" .ascii "\200\200\200\200\200\210\210\210\210\210\210\210\210\210\210" .ascii "\210\210\210\210\210\210\210\210\210\210\210\210\210\210\210" .ascii "\210\210\210\210\210\210\210\252\252\252\252\252\252\252\252" .ascii "\252\252\252\252\252\252\252\252\377\377\377\377\377\377\377" .ascii "\377\377\377\377\377\377\377\377\377" .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "oFAST.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include "cuda.h" #define max(x,y) ((x) > (y)? (x) : (y)) #define min(x,y) ((x) < (y)? (x) : (y)) #define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1) void check_error (const char* message) { cudaError_t error = cudaGetLastError (); if (error != cudaSuccess) { printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error)); exit(-1); } } __global__ void sw4 (double * uacc_in_0, double * uacc_in_1, double * uacc_in_2, double * __restrict__ u_in_0, double * __restrict__ u_in_1, double * __restrict__ u_in_2, double * __restrict__ mu_in, double * __restrict__ la_in, double * strx, double * stry, double * strz, int N) { //Determing the block's indices int blockdim_i= (int)(blockDim.x); int i0 = (int)(blockIdx.x)*(blockdim_i); int i = max (i0, 0) + (int)(threadIdx.x); int blockdim_j= (int)(blockDim.y); int j0 = (int)(blockIdx.y)*(blockdim_j); int j = max (j0, 0) + (int)(threadIdx.y); int blockdim_k= (int)(blockDim.z); int k0 = (int)(blockIdx.z)*(blockdim_k); int k = max (k0, 0) + (int)(threadIdx.z); // Assumptions int a1 = 1; double h = 3.7; double cof = 1e0 / ( h * h); double (*uacc_0)[304][304] = (double (*)[304][304])uacc_in_0; double (*uacc_1)[304][304] = (double (*)[304][304])uacc_in_1; double (*uacc_2)[304][304] = (double (*)[304][304])uacc_in_2; double (*u_0)[304][304] = (double (*)[304][304])u_in_0; double (*u_1)[304][304] = (double (*)[304][304])u_in_1; double (*u_2)[304][304] = (double (*)[304][304])u_in_2; double (*mu)[304][304] = (double (*)[304][304])mu_in; double (*la)[304][304] = (double (*)[304][304])la_in; double mux1, mux2, mux3, mux4, muy1, muy2, muy3, muy4, muz1, muz2, muz3, muz4; double r1, r2, r3; if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) { double muz4; double muz1; double muy4; double muy1; double mux4; double mux1; double muz3; double muz2; double muy3; double muy2; double mux3; double mux2; double _t_5_; double _t_7_; double _t_3_; double _t_9_; double _t_11_; double _t_10_; double _t_12_; double _t_13_; double _t_14_; double _t_0_; double _t_16_; double _t_15_; double _t_17_; double _t_18_; double _t_19_; double _t_4_; double _t_2_; double _t_6_; double _t_1_; double _t_8_; double r1; double _t_30_; double _t_31_; double _t_33_; double _t_29_; double _t_27_; double _t_26_; double _t_28_; double _t_32_; double _t_34_; double _t_20_; double _t_22_; double _t_21_; double _t_23_; double _t_24_; double _t_25_; double _t_36_; double _t_35_; double _t_52_; double _t_37_; double _t_54_; double _t_38_; double _t_39_; double r2; double _t_56_; double _t_58_; double _t_42_; double _t_41_; double _t_43_; double _t_44_; double _t_45_; double _t_40_; double _t_47_; double _t_46_; double _t_48_; double _t_49_; double _t_50_; double _t_53_; double _t_51_; double _t_55_; double _t_57_; double _t_59_; double r3; double _t_102_; double _t_100_; double _t_76_; double _t_74_; double _t_63_; double _t_61_; double _t_89_; double _t_87_; double _t_103_; double _t_77_; double _t_85_; double _t_111_; double _t_104_; double _t_80_; double _t_112_; double _t_83_; double _t_101_; double _t_78_; double _t_106_; double _t_86_; double _t_109_; double _t_75_; double _t_107_; double _t_81_; double _t_84_; double _t_105_; double _t_110_; double _t_108_; double _t_60_; double _t_79_; double _t_82_; double _t_64_; double _t_90_; double _t_72_; double _t_98_; double _t_65_; double _t_93_; double _t_73_; double _t_96_; double _t_62_; double _t_91_; double _t_67_; double _t_99_; double _t_88_; double _t_70_; double _t_68_; double _t_94_; double _t_92_; double _t_71_; double _t_97_; double _t_95_; double _t_66_; double _t_69_; double _t_129_; double _t_127_; double _t_155_; double _t_153_; double _t_116_; double _t_114_; double _t_142_; double _t_140_; double _t_117_; double _t_143_; double _t_125_; double _t_151_; double _t_118_; double _t_146_; double _t_126_; double _t_149_; double _t_115_; double _t_144_; double _t_120_; double _t_152_; double _t_141_; double _t_123_; double _t_121_; double _t_147_; double _t_145_; double _t_124_; double _t_150_; double _t_148_; double _t_113_; double _t_119_; double _t_122_; double _t_130_; double _t_156_; double _t_138_; double _t_164_; double _t_131_; double _t_159_; double _t_139_; double _t_128_; double _t_162_; double _t_157_; double _t_133_; double _t_165_; double _t_136_; double _t_154_; double _t_134_; double _t_160_; double _t_137_; double _t_158_; double _t_132_; double _t_163_; double _t_135_; double _t_161_; double _t_169_; double _t_182_; double _t_167_; double _t_180_; double _t_195_; double _t_208_; double _t_193_; double _t_206_; double _t_170_; double _t_183_; double _t_178_; double _t_191_; double _t_171_; double _t_186_; double _t_179_; double _t_168_; double _t_189_; double _t_184_; double _t_173_; double _t_192_; double _t_176_; double _t_181_; double _t_174_; double _t_187_; double _t_177_; double _t_185_; double _t_172_; double _t_190_; double _t_175_; double _t_166_; double _t_188_; double _t_196_; double _t_209_; double _t_204_; double _t_217_; double _t_197_; double _t_212_; double _t_205_; double _t_194_; double _t_215_; double _t_210_; double _t_199_; double _t_218_; double _t_207_; double _t_202_; double _t_200_; double _t_213_; double _t_211_; double _t_203_; double _t_198_; double _t_216_; double _t_201_; double _t_214_; double uacc_0kc0jc0ic0; double uacc_1kc0jc0ic0; double uacc_2kc0jc0ic0; muz4 = -3.0 / 4.0 * mu[k+2][j][i] * strz[k+2]; muz4 += mu[k+1][j][i] * strz[k+1]; muz4 -= 3.0 / 4.0 * mu[k][j][i] * strz[k]; muz1 = -3.0 / 4.0 * mu[k][j][i] * strz[k]; muz1 += mu[k-1][j][i] * strz[k-1]; muz1 -= 3.0 / 4.0 * mu[k-2][j][i] * strz[k-2]; muy4 = -3.0 / 4.0 * mu[k][j][i] * stry[j]; muy4 += mu[k][j+1][i] * stry[j+1]; muy4 -= 3.0 / 4.0 * mu[k][j+2][i] * stry[j+2]; muy1 = -3.0 / 4.0 * mu[k][j][i] * stry[j]; muy1 += mu[k][j-1][i] * stry[j-1]; muy1 -= 3.0 / 4.0 * mu[k][j-2][i] * stry[j-2]; mux4 = -3.0 / 4.0 * mu[k][j][i] * strx[i]; mux4 += mu[k][j][i+1] * strx[i+1]; mux4 -= 3.0 / 4.0 * mu[k][j][i+2] * strx[i+2]; mux1 = -3.0 / 4.0 * mu[k][j][i] * strx[i]; mux1 += mu[k][j][i-1] * strx[i-1]; mux1 -= 3.0 / 4.0 * mu[k][j][i-2] * strx[i-2]; muz3 = mu[k-1][j][i] * strz[k-1]; muz3 += mu[k+2][j][i] * strz[k+2]; muz3 += 3.0 * mu[k+1][j][i] * strz[k+1]; muz3 += 3.0 * mu[k][j][i] * strz[k]; muz2 = mu[k-2][j][i] * strz[k-2]; muz2 += mu[k+1][j][i] * strz[k+1]; muz2 += 3.0 * mu[k][j][i] * strz[k]; muz2 += 3.0 * mu[k-1][j][i] * strz[k-1]; muy3 = mu[k][j-1][i] * stry[j-1]; muy3 += mu[k][j+2][i] * stry[j+2]; muy3 += 3.0 * mu[k][j+1][i] * stry[j+1]; muy3 += 3.0 * mu[k][j][i] * stry[j]; muy2 = mu[k][j-2][i] * stry[j-2]; muy2 += mu[k][j+1][i] * stry[j+1]; muy2 += 3.0 * mu[k][j][i] * stry[j]; muy2 += 3.0 * mu[k][j-1][i] * stry[j-1]; mux3 = mu[k][j][i-1] * strx[i-1]; mux3 += mu[k][j][i+2] * strx[i+2]; mux3 += 3.0 * mu[k][j][i+1] * strx[i+1]; mux3 += 3.0 * mu[k][j][i] * strx[i]; mux2 = mu[k][j][i-2] * strx[i-2]; mux2 += mu[k][j][i+1] * strx[i+1]; mux2 += 3.0 * mu[k][j][i] * strx[i]; mux2 += 3.0 * mu[k][j][i-1] * strx[i-1]; _t_5_ = u_0[k][j][i-1]; _t_5_ -= u_0[k][j][i]; _t_7_ = -u_0[k][j][i]; _t_7_ += u_0[k][j][i+1]; _t_3_ = -u_0[k][j][i]; _t_3_ += u_0[k][j][i-2]; _t_9_ = -u_0[k][j][i]; _t_9_ += u_0[k][j][i+2]; _t_11_ = -u_0[k][j][i]; _t_11_ += u_0[k][j-2][i]; _t_10_ = muy1 * _t_11_; _t_12_ = -u_0[k][j][i]; _t_12_ += u_0[k][j-1][i]; _t_10_ += muy2 * _t_12_; _t_13_ = -u_0[k][j][i]; _t_13_ += u_0[k][j+1][i]; _t_10_ += muy3 * _t_13_; _t_14_ = -u_0[k][j][i]; _t_14_ += u_0[k][j+2][i]; _t_10_ += muy4 * _t_14_; _t_0_ = stry[j] * _t_10_; _t_16_ = -u_0[k][j][i]; _t_16_ += u_0[k-2][j][i]; _t_15_ = muz1 * _t_16_; _t_17_ = -u_0[k][j][i]; _t_17_ += u_0[k-1][j][i]; _t_15_ += muz2 * _t_17_; _t_18_ = -u_0[k][j][i]; _t_19_ = -u_0[k][j][i]; _t_18_ += u_0[k+1][j][i]; _t_15_ += muz3 * _t_18_; _t_19_ += u_0[k+2][j][i]; _t_15_ += muz4 * _t_19_; _t_0_ += strz[k] * _t_15_; _t_4_ = 2.0 * mux2; _t_2_ = 2.0 * mux1; _t_2_ -= 3.0 / 4.0 * la[k][j][i-2] * strx[i-2]; _t_4_ += la[k][j][i-2] * strx[i-2]; _t_2_ += la[k][j][i-1] * strx[i-1]; _t_4_ += 3.0 * la[k][j][i-1] * strx[i-1]; _t_6_ = la[k][j][i-1] * strx[i-1]; _t_6_ += 2.0 * mux3; _t_2_ -= 3.0 / 4.0 * la[k][j][i] * strx[i]; _t_4_ += 3.0 * la[k][j][i] * strx[i]; _t_6_ += 3.0 * la[k][j][i] * strx[i]; _t_1_ = _t_2_ * _t_3_; _t_8_ = -3.0 / 4.0 * la[k][j][i] * strx[i]; _t_8_ += 2.0 * mux4; _t_4_ += la[k][j][i+1] * strx[i+1]; _t_1_ += _t_4_ * _t_5_; _t_6_ += 3.0 * la[k][j][i+1] * strx[i+1]; _t_8_ += la[k][j][i+1] * strx[i+1]; _t_6_ += la[k][j][i+2] * strx[i+2]; _t_1_ += _t_6_ * _t_7_; _t_8_ -= 3.0 / 4.0 * la[k][j][i+2] * strx[i+2]; _t_1_ += _t_8_ * _t_9_; _t_0_ += strx[i] * _t_1_; r1 = 1.0 / 6.0 * _t_0_; _t_30_ = u_1[k][j-1][i]; _t_31_ = 3.0 * la[k][j][i] * stry[j]; _t_31_ += 2.0 * muy3; _t_33_ = -3.0 / 4.0 * la[k][j][i] * stry[j]; _t_33_ += 2.0 * muy4; _t_31_ += la[k][j+2][i] * stry[j+2]; _t_33_ -= 3.0 / 4.0 * la[k][j+2][i] * stry[j+2]; _t_29_ = 3.0 * la[k][j][i] * stry[j]; _t_29_ += 2.0 * muy2; _t_29_ += la[k][j+1][i] * stry[j+1]; _t_31_ += 3.0 * la[k][j+1][i] * stry[j+1]; _t_33_ += la[k][j+1][i] * stry[j+1]; _t_27_ = -3.0 / 4.0 * la[k][j][i] * stry[j]; _t_27_ += 2.0 * muy1; _t_27_ += la[k][j-1][i] * stry[j-1]; _t_29_ += 3.0 * la[k][j-1][i] * stry[j-1]; _t_31_ += la[k][j-1][i] * stry[j-1]; _t_27_ -= 3.0 / 4.0 * la[k][j-2][i] * stry[j-2]; _t_29_ += la[k][j-2][i] * stry[j-2]; _t_30_ -= u_1[k][j][i]; _t_26_ = _t_29_ * _t_30_; _t_28_ = -u_1[k][j][i]; _t_28_ += u_1[k][j-2][i]; _t_26_ += _t_27_ * _t_28_; _t_32_ = -u_1[k][j][i]; _t_32_ += u_1[k][j+1][i]; _t_26_ += _t_31_ * _t_32_; _t_34_ = -u_1[k][j][i]; _t_34_ += u_1[k][j+2][i]; _t_26_ += _t_33_ * _t_34_; _t_20_ = stry[j] * _t_26_; _t_22_ = -u_1[k][j][i]; _t_22_ += u_1[k][j][i-2]; _t_21_ = mux1 * _t_22_; _t_23_ = -u_1[k][j][i]; _t_23_ += u_1[k][j][i-1]; _t_21_ += mux2 * _t_23_; _t_24_ = -u_1[k][j][i]; _t_24_ += u_1[k][j][i+1]; _t_21_ += mux3 * _t_24_; _t_25_ = -u_1[k][j][i]; _t_25_ += u_1[k][j][i+2]; _t_21_ += mux4 * _t_25_; _t_20_ += strx[i] * _t_21_; _t_36_ = -u_1[k][j][i]; _t_36_ += u_1[k-2][j][i]; _t_35_ = muz1 * _t_36_; _t_52_ = -3.0 / 4.0 * la[k][j][i] * strz[k]; _t_52_ += 2.0 * muz1; _t_37_ = -u_1[k][j][i]; _t_37_ += u_1[k-1][j][i]; _t_35_ += muz2 * _t_37_; _t_54_ = 3.0 * la[k][j][i] * strz[k]; _t_54_ += 2.0 * muz2; _t_52_ -= 3.0 / 4.0 * la[k-2][j][i] * strz[k-2]; _t_54_ += la[k-2][j][i] * strz[k-2]; _t_38_ = -u_1[k][j][i]; _t_39_ = -u_1[k][j][i]; _t_38_ += u_1[k+1][j][i]; _t_35_ += muz3 * _t_38_; _t_39_ += u_1[k+2][j][i]; _t_35_ += muz4 * _t_39_; _t_20_ += strz[k] * _t_35_; r2 = 1.0 / 6.0 * _t_20_; _t_56_ = 3.0 * la[k][j][i] * strz[k]; _t_56_ += 2.0 * muz3; _t_58_ = -3.0 / 4.0 * la[k][j][i] * strz[k]; _t_58_ += 2.0 * muz4; _t_52_ += la[k-1][j][i] * strz[k-1]; _t_54_ += 3.0 * la[k-1][j][i] * strz[k-1]; _t_56_ += la[k-1][j][i] * strz[k-1]; _t_54_ += la[k+1][j][i] * strz[k+1]; _t_56_ += 3.0 * la[k+1][j][i] * strz[k+1]; _t_58_ += la[k+1][j][i] * strz[k+1]; _t_56_ += la[k+2][j][i] * strz[k+2]; _t_58_ -= 3.0 / 4.0 * la[k+2][j][i] * strz[k+2]; _t_42_ = u_2[k][j][i-2]; _t_42_ -= u_2[k][j][i]; _t_41_ = mux1 * _t_42_; _t_43_ = -u_2[k][j][i]; _t_43_ += u_2[k][j][i-1]; _t_41_ += mux2 * _t_43_; _t_44_ = -u_2[k][j][i]; _t_44_ += u_2[k][j][i+1]; _t_41_ += mux3 * _t_44_; _t_45_ = -u_2[k][j][i]; _t_45_ += u_2[k][j][i+2]; _t_41_ += mux4 * _t_45_; _t_40_ = strx[i] * _t_41_; _t_47_ = -u_2[k][j][i]; _t_47_ += u_2[k][j-2][i]; _t_46_ = muy1 * _t_47_; _t_48_ = -u_2[k][j][i]; _t_48_ += u_2[k][j-1][i]; _t_46_ += muy2 * _t_48_; _t_49_ = -u_2[k][j][i]; _t_49_ += u_2[k][j+1][i]; _t_46_ += muy3 * _t_49_; _t_50_ = -u_2[k][j][i]; _t_50_ += u_2[k][j+2][i]; _t_46_ += muy4 * _t_50_; _t_40_ += stry[j] * _t_46_; _t_53_ = -u_2[k][j][i]; _t_53_ += u_2[k-2][j][i]; _t_51_ = _t_52_ * _t_53_; _t_55_ = -u_2[k][j][i]; _t_55_ += u_2[k-1][j][i]; _t_51_ += _t_54_ * _t_55_; _t_57_ = -u_2[k][j][i]; _t_59_ = -u_2[k][j][i]; _t_57_ += u_2[k+1][j][i]; _t_51_ += _t_56_ * _t_57_; _t_59_ += u_2[k+2][j][i]; _t_51_ += _t_58_ * _t_59_; _t_40_ += strz[k] * _t_51_; r3 = 1.0 / 6.0 * _t_40_; _t_102_ = stry[j] * strz[k]; _t_100_ = _t_102_ * 1.0 / 144.0; _t_76_ = stry[j] * strz[k]; _t_74_ = _t_76_ * 1.0 / 144.0; _t_63_ = strx[i] * strz[k]; _t_61_ = _t_63_ * 1.0 / 144.0; _t_89_ = strx[i] * strz[k]; _t_87_ = _t_89_ * 1.0 / 144.0; _t_103_ = u_1[k-2][j-2][i]; _t_77_ = u_1[k-2][j-2][i]; _t_103_ -= u_1[k-2][j+2][i]; _t_85_ = u_1[k-2][j+2][i]; _t_77_ -= u_1[k+2][j-2][i]; _t_111_ = u_1[k+2][j-2][i]; _t_85_ -= u_1[k+2][j+2][i]; _t_111_ -= u_1[k+2][j+2][i]; _t_104_ = -u_1[k-2][j-1][i]; _t_80_ = u_1[k-2][j-1][i]; _t_80_ -= u_1[k+2][j-1][i]; _t_112_ = -u_1[k+2][j-1][i]; _t_104_ += u_1[k-2][j+1][i]; _t_103_ += 8.0 * _t_104_; _t_83_ = u_1[k-2][j+1][i]; _t_83_ -= u_1[k+2][j+1][i]; _t_112_ += u_1[k+2][j+1][i]; _t_111_ += 8.0 * _t_112_; _t_101_ = la[k-2][j][i] * _t_103_; _t_101_ -= la[k+2][j][i] * _t_111_; _t_78_ = -u_1[k-1][j-2][i]; _t_106_ = u_1[k-1][j-2][i]; _t_106_ -= u_1[k-1][j+2][i]; _t_86_ = -u_1[k-1][j+2][i]; _t_78_ += u_1[k+1][j-2][i]; _t_77_ += 8.0 * _t_78_; _t_109_ = u_1[k+1][j-2][i]; _t_86_ += u_1[k+1][j+2][i]; _t_85_ += 8.0 * _t_86_; _t_109_ -= u_1[k+1][j+2][i]; _t_75_ = mu[k][j-2][i] * _t_77_; _t_75_ -= mu[k][j+2][i] * _t_85_; _t_107_ = -u_1[k-1][j-1][i]; _t_81_ = -u_1[k-1][j-1][i]; _t_107_ += u_1[k-1][j+1][i]; _t_106_ += 8.0 * _t_107_; _t_84_ = -u_1[k-1][j+1][i]; _t_105_ = la[k-1][j][i] * _t_106_; _t_101_ -= 8.0 * _t_105_; _t_81_ += u_1[k+1][j-1][i]; _t_80_ += 8.0 * _t_81_; _t_110_ = -u_1[k+1][j-1][i]; _t_84_ += u_1[k+1][j+1][i]; _t_83_ += 8.0 * _t_84_; _t_110_ += u_1[k+1][j+1][i]; _t_109_ += 8.0 * _t_110_; _t_108_ = la[k+1][j][i] * _t_109_; _t_101_ += 8.0 * _t_108_; _t_60_ = _t_100_ * _t_101_; _t_79_ = mu[k][j-1][i] * _t_80_; _t_75_ -= 8.0 * _t_79_; _t_82_ = mu[k][j+1][i] * _t_83_; _t_75_ += 8.0 * _t_82_; _t_60_ += _t_74_ * _t_75_; _t_64_ = u_0[k-2][j][i-2]; _t_90_ = u_0[k-2][j][i-2]; _t_90_ -= u_0[k-2][j][i+2]; _t_72_ = u_0[k-2][j][i+2]; _t_64_ -= u_0[k+2][j][i-2]; _t_98_ = u_0[k+2][j][i-2]; _t_72_ -= u_0[k+2][j][i+2]; _t_98_ -= u_0[k+2][j][i+2]; _t_65_ = -u_0[k-1][j][i-2]; _t_93_ = u_0[k-1][j][i-2]; _t_93_ -= u_0[k-1][j][i+2]; _t_73_ = -u_0[k-1][j][i+2]; _t_65_ += u_0[k+1][j][i-2]; _t_64_ += 8.0 * _t_65_; _t_96_ = u_0[k+1][j][i-2]; _t_73_ += u_0[k+1][j][i+2]; _t_72_ += 8.0 * _t_73_; _t_96_ -= u_0[k+1][j][i+2]; _t_62_ = mu[k][j][i-2] * _t_64_; _t_62_ -= mu[k][j][i+2] * _t_72_; _t_91_ = -u_0[k-2][j][i-1]; _t_67_ = u_0[k-2][j][i-1]; _t_67_ -= u_0[k+2][j][i-1]; _t_99_ = -u_0[k+2][j][i-1]; _t_91_ += u_0[k-2][j][i+1]; _t_90_ += 8.0 * _t_91_; _t_88_ = la[k-2][j][i] * _t_90_; _t_70_ = u_0[k-2][j][i+1]; _t_70_ -= u_0[k+2][j][i+1]; _t_99_ += u_0[k+2][j][i+1]; _t_98_ += 8.0 * _t_99_; _t_88_ -= la[k+2][j][i] * _t_98_; _t_68_ = -u_0[k-1][j][i-1]; _t_94_ = -u_0[k-1][j][i-1]; _t_94_ += u_0[k-1][j][i+1]; _t_93_ += 8.0 * _t_94_; _t_92_ = la[k-1][j][i] * _t_93_; _t_88_ -= 8.0 * _t_92_; _t_71_ = -u_0[k-1][j][i+1]; _t_68_ += u_0[k+1][j][i-1]; _t_67_ += 8.0 * _t_68_; _t_97_ = -u_0[k+1][j][i-1]; _t_71_ += u_0[k+1][j][i+1]; _t_70_ += 8.0 * _t_71_; _t_97_ += u_0[k+1][j][i+1]; _t_96_ += 8.0 * _t_97_; _t_95_ = la[k+1][j][i] * _t_96_; _t_88_ += 8.0 * _t_95_; _t_60_ += _t_87_ * _t_88_; _t_66_ = mu[k][j][i-1] * _t_67_; _t_62_ -= 8.0 * _t_66_; _t_69_ = mu[k][j][i+1] * _t_70_; _t_62_ += 8.0 * _t_69_; _t_60_ += _t_61_ * _t_62_; r3 += _t_60_; _t_129_ = strx[i] * strz[k]; _t_127_ = _t_129_ * 1.0 / 144.0; _t_155_ = strx[i] * strz[k]; _t_153_ = _t_155_ * 1.0 / 144.0; _t_116_ = strx[i] * stry[j]; _t_114_ = _t_116_ * 1.0 / 144.0; _t_142_ = strx[i] * stry[j]; _t_140_ = _t_142_ * 1.0 / 144.0; _t_117_ = u_1[k][j-2][i-2]; _t_143_ = u_1[k][j-2][i-2]; _t_143_ -= u_1[k][j-2][i+2]; _t_125_ = u_1[k][j-2][i+2]; _t_117_ -= u_1[k][j+2][i-2]; _t_151_ = u_1[k][j+2][i-2]; _t_125_ -= u_1[k][j+2][i+2]; _t_151_ -= u_1[k][j+2][i+2]; _t_118_ = -u_1[k][j-1][i-2]; _t_146_ = u_1[k][j-1][i-2]; _t_146_ -= u_1[k][j-1][i+2]; _t_126_ = -u_1[k][j-1][i+2]; _t_118_ += u_1[k][j+1][i-2]; _t_117_ += 8.0 * _t_118_; _t_149_ = u_1[k][j+1][i-2]; _t_126_ += u_1[k][j+1][i+2]; _t_125_ += 8.0 * _t_126_; _t_149_ -= u_1[k][j+1][i+2]; _t_115_ = la[k][j][i-2] * _t_117_; _t_115_ -= la[k][j][i+2] * _t_125_; _t_144_ = -u_1[k][j-2][i-1]; _t_120_ = u_1[k][j-2][i-1]; _t_120_ -= u_1[k][j+2][i-1]; _t_152_ = -u_1[k][j+2][i-1]; _t_144_ += u_1[k][j-2][i+1]; _t_143_ += 8.0 * _t_144_; _t_141_ = mu[k][j-2][i] * _t_143_; _t_123_ = u_1[k][j-2][i+1]; _t_123_ -= u_1[k][j+2][i+1]; _t_152_ += u_1[k][j+2][i+1]; _t_151_ += 8.0 * _t_152_; _t_141_ -= mu[k][j+2][i] * _t_151_; _t_121_ = -u_1[k][j-1][i-1]; _t_147_ = -u_1[k][j-1][i-1]; _t_147_ += u_1[k][j-1][i+1]; _t_146_ += 8.0 * _t_147_; _t_145_ = mu[k][j-1][i] * _t_146_; _t_141_ -= 8.0 * _t_145_; _t_124_ = -u_1[k][j-1][i+1]; _t_121_ += u_1[k][j+1][i-1]; _t_120_ += 8.0 * _t_121_; _t_150_ = -u_1[k][j+1][i-1]; _t_124_ += u_1[k][j+1][i+1]; _t_123_ += 8.0 * _t_124_; _t_150_ += u_1[k][j+1][i+1]; _t_149_ += 8.0 * _t_150_; _t_148_ = mu[k][j+1][i] * _t_149_; _t_141_ += 8.0 * _t_148_; _t_113_ = _t_140_ * _t_141_; _t_119_ = la[k][j][i-1] * _t_120_; _t_115_ -= 8.0 * _t_119_; _t_122_ = la[k][j][i+1] * _t_123_; _t_115_ += 8.0 * _t_122_; _t_113_ += _t_114_ * _t_115_; _t_130_ = u_2[k-2][j][i-2]; _t_156_ = u_2[k-2][j][i-2]; _t_156_ -= u_2[k-2][j][i+2]; _t_138_ = u_2[k-2][j][i+2]; _t_130_ -= u_2[k+2][j][i-2]; _t_164_ = u_2[k+2][j][i-2]; _t_138_ -= u_2[k+2][j][i+2]; _t_164_ -= u_2[k+2][j][i+2]; _t_131_ = -u_2[k-1][j][i-2]; _t_159_ = u_2[k-1][j][i-2]; _t_159_ -= u_2[k-1][j][i+2]; _t_139_ = -u_2[k-1][j][i+2]; _t_131_ += u_2[k+1][j][i-2]; _t_130_ += 8.0 * _t_131_; _t_128_ = la[k][j][i-2] * _t_130_; _t_162_ = u_2[k+1][j][i-2]; _t_139_ += u_2[k+1][j][i+2]; _t_138_ += 8.0 * _t_139_; _t_128_ -= la[k][j][i+2] * _t_138_; _t_162_ -= u_2[k+1][j][i+2]; _t_157_ = -u_2[k-2][j][i-1]; _t_133_ = u_2[k-2][j][i-1]; _t_133_ -= u_2[k+2][j][i-1]; _t_165_ = -u_2[k+2][j][i-1]; _t_157_ += u_2[k-2][j][i+1]; _t_156_ += 8.0 * _t_157_; _t_136_ = u_2[k-2][j][i+1]; _t_136_ -= u_2[k+2][j][i+1]; _t_165_ += u_2[k+2][j][i+1]; _t_164_ += 8.0 * _t_165_; _t_154_ = mu[k-2][j][i] * _t_156_; _t_154_ -= mu[k+2][j][i] * _t_164_; _t_134_ = -u_2[k-1][j][i-1]; _t_160_ = -u_2[k-1][j][i-1]; _t_160_ += u_2[k-1][j][i+1]; _t_159_ += 8.0 * _t_160_; _t_137_ = -u_2[k-1][j][i+1]; _t_158_ = mu[k-1][j][i] * _t_159_; _t_154_ -= 8.0 * _t_158_; _t_134_ += u_2[k+1][j][i-1]; _t_133_ += 8.0 * _t_134_; _t_132_ = la[k][j][i-1] * _t_133_; _t_128_ -= 8.0 * _t_132_; _t_163_ = -u_2[k+1][j][i-1]; _t_137_ += u_2[k+1][j][i+1]; _t_136_ += 8.0 * _t_137_; _t_163_ += u_2[k+1][j][i+1]; _t_162_ += 8.0 * _t_163_; _t_135_ = la[k][j][i+1] * _t_136_; _t_128_ += 8.0 * _t_135_; _t_113_ += _t_127_ * _t_128_; _t_161_ = mu[k+1][j][i] * _t_162_; _t_154_ += 8.0 * _t_161_; _t_113_ += _t_153_ * _t_154_; r1 += _t_113_; _t_169_ = strx[i] * stry[j]; _t_182_ = strx[i] * stry[j]; _t_167_ = _t_169_ * 1.0 / 144.0; _t_180_ = _t_182_ * 1.0 / 144.0; _t_195_ = stry[j] * strz[k]; _t_208_ = stry[j] * strz[k]; _t_193_ = _t_195_ * 1.0 / 144.0; _t_206_ = _t_208_ * 1.0 / 144.0; _t_170_ = u_0[k][j-2][i-2]; _t_183_ = u_0[k][j-2][i-2]; _t_183_ -= u_0[k][j-2][i+2]; _t_178_ = u_0[k][j-2][i+2]; _t_170_ -= u_0[k][j+2][i-2]; _t_191_ = u_0[k][j+2][i-2]; _t_178_ -= u_0[k][j+2][i+2]; _t_191_ -= u_0[k][j+2][i+2]; _t_171_ = -u_0[k][j-1][i-2]; _t_186_ = u_0[k][j-1][i-2]; _t_186_ -= u_0[k][j-1][i+2]; _t_179_ = -u_0[k][j-1][i+2]; _t_171_ += u_0[k][j+1][i-2]; _t_170_ += 8.0 * _t_171_; _t_168_ = mu[k][j][i-2] * _t_170_; _t_189_ = u_0[k][j+1][i-2]; _t_179_ += u_0[k][j+1][i+2]; _t_178_ += 8.0 * _t_179_; _t_168_ -= mu[k][j][i+2] * _t_178_; _t_189_ -= u_0[k][j+1][i+2]; _t_184_ = -u_0[k][j-2][i-1]; _t_173_ = u_0[k][j-2][i-1]; _t_173_ -= u_0[k][j+2][i-1]; _t_192_ = -u_0[k][j+2][i-1]; _t_184_ += u_0[k][j-2][i+1]; _t_183_ += 8.0 * _t_184_; _t_176_ = u_0[k][j-2][i+1]; _t_176_ -= u_0[k][j+2][i+1]; _t_192_ += u_0[k][j+2][i+1]; _t_191_ += 8.0 * _t_192_; _t_181_ = la[k][j-2][i] * _t_183_; _t_181_ -= la[k][j+2][i] * _t_191_; _t_174_ = -u_0[k][j-1][i-1]; _t_187_ = -u_0[k][j-1][i-1]; _t_187_ += u_0[k][j-1][i+1]; _t_186_ += 8.0 * _t_187_; _t_177_ = -u_0[k][j-1][i+1]; _t_185_ = la[k][j-1][i] * _t_186_; _t_181_ -= 8.0 * _t_185_; _t_174_ += u_0[k][j+1][i-1]; _t_173_ += 8.0 * _t_174_; _t_172_ = mu[k][j][i-1] * _t_173_; _t_168_ -= 8.0 * _t_172_; _t_190_ = -u_0[k][j+1][i-1]; _t_177_ += u_0[k][j+1][i+1]; _t_176_ += 8.0 * _t_177_; _t_190_ += u_0[k][j+1][i+1]; _t_189_ += 8.0 * _t_190_; _t_175_ = mu[k][j][i+1] * _t_176_; _t_168_ += 8.0 * _t_175_; _t_166_ = _t_167_ * _t_168_; _t_188_ = la[k][j+1][i] * _t_189_; _t_181_ += 8.0 * _t_188_; _t_166_ += _t_180_ * _t_181_; _t_196_ = u_2[k-2][j-2][i]; _t_209_ = u_2[k-2][j-2][i]; _t_209_ -= u_2[k-2][j+2][i]; _t_204_ = u_2[k-2][j+2][i]; _t_196_ -= u_2[k+2][j-2][i]; _t_217_ = u_2[k+2][j-2][i]; _t_204_ -= u_2[k+2][j+2][i]; _t_217_ -= u_2[k+2][j+2][i]; _t_197_ = -u_2[k-1][j-2][i]; _t_212_ = u_2[k-1][j-2][i]; _t_212_ -= u_2[k-1][j+2][i]; _t_205_ = -u_2[k-1][j+2][i]; _t_197_ += u_2[k+1][j-2][i]; _t_196_ += 8.0 * _t_197_; _t_194_ = la[k][j-2][i] * _t_196_; _t_215_ = u_2[k+1][j-2][i]; _t_205_ += u_2[k+1][j+2][i]; _t_204_ += 8.0 * _t_205_; _t_194_ -= la[k][j+2][i] * _t_204_; _t_215_ -= u_2[k+1][j+2][i]; _t_210_ = -u_2[k-2][j-1][i]; _t_199_ = u_2[k-2][j-1][i]; _t_199_ -= u_2[k+2][j-1][i]; _t_218_ = -u_2[k+2][j-1][i]; _t_210_ += u_2[k-2][j+1][i]; _t_209_ += 8.0 * _t_210_; _t_207_ = mu[k-2][j][i] * _t_209_; _t_202_ = u_2[k-2][j+1][i]; _t_202_ -= u_2[k+2][j+1][i]; _t_218_ += u_2[k+2][j+1][i]; _t_217_ += 8.0 * _t_218_; _t_207_ -= mu[k+2][j][i] * _t_217_; _t_200_ = -u_2[k-1][j-1][i]; _t_213_ = -u_2[k-1][j-1][i]; _t_213_ += u_2[k-1][j+1][i]; _t_212_ += 8.0 * _t_213_; _t_211_ = mu[k-1][j][i] * _t_212_; _t_207_ -= 8.0 * _t_211_; _t_203_ = -u_2[k-1][j+1][i]; _t_200_ += u_2[k+1][j-1][i]; _t_199_ += 8.0 * _t_200_; _t_198_ = la[k][j-1][i] * _t_199_; _t_194_ -= 8.0 * _t_198_; _t_216_ = -u_2[k+1][j-1][i]; _t_203_ += u_2[k+1][j+1][i]; _t_202_ += 8.0 * _t_203_; _t_216_ += u_2[k+1][j+1][i]; _t_215_ += 8.0 * _t_216_; _t_201_ = la[k][j+1][i] * _t_202_; _t_194_ += 8.0 * _t_201_; _t_166_ += _t_193_ * _t_194_; _t_214_ = mu[k+1][j][i] * _t_215_; _t_207_ += 8.0 * _t_214_; _t_166_ += _t_206_ * _t_207_; r2 += _t_166_; uacc_0kc0jc0ic0 = a1 * uacc_0[k][j][i]; uacc_0kc0jc0ic0 += cof * r1; uacc_0[k][j][i] = uacc_0kc0jc0ic0; uacc_1kc0jc0ic0 = a1 * uacc_1[k][j][i]; uacc_1kc0jc0ic0 += cof * r2; uacc_1[k][j][i] = uacc_1kc0jc0ic0; uacc_2kc0jc0ic0 = a1 * uacc_2[k][j][i]; uacc_2kc0jc0ic0 += cof * r3; uacc_2[k][j][i] = uacc_2kc0jc0ic0; } } extern "C" void host_code (double *h_uacc_0, double *h_uacc_1, double *h_uacc_2, double *h_u_0, double *h_u_1, double *h_u_2, double *h_mu, double *h_la, double *h_strx, double *h_stry, double *h_strz, int N) { double *uacc_0; cudaMalloc (&uacc_0, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for uacc_0\n"); cudaMemcpy (uacc_0, h_uacc_0, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *uacc_1; cudaMalloc (&uacc_1, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for uacc_1\n"); cudaMemcpy (uacc_1, h_uacc_1, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *uacc_2; cudaMalloc (&uacc_2, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for uacc_2\n"); cudaMemcpy (uacc_2, h_uacc_2, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *u_0; cudaMalloc (&u_0, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for u_0\n"); cudaMemcpy (u_0, h_u_0, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *u_1; cudaMalloc (&u_1, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for u_1\n"); cudaMemcpy (u_1, h_u_1, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *u_2; cudaMalloc (&u_2, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for u_2\n"); cudaMemcpy (u_2, h_u_2, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *mu; cudaMalloc (&mu, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for mu\n"); cudaMemcpy (mu, h_mu, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *la; cudaMalloc (&la, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for la\n"); cudaMemcpy (la, h_la, sizeof(double)*N*N*N, cudaMemcpyHostToDevice); double *strx; cudaMalloc (&strx, sizeof(double)*N); check_error ("Failed to allocate device memory for strx\n"); cudaMemcpy (strx, h_strx, sizeof(double)*N, cudaMemcpyHostToDevice); double *stry; cudaMalloc (&stry, sizeof(double)*N); check_error ("Failed to allocate device memory for stry\n"); cudaMemcpy (stry, h_stry, sizeof(double)*N, cudaMemcpyHostToDevice); double *strz; cudaMalloc (&strz, sizeof(double)*N); check_error ("Failed to allocate device memory for strz\n"); cudaMemcpy (strz, h_strz, sizeof(double)*N, cudaMemcpyHostToDevice); dim3 blockconfig (16, 2, 2); dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z)); sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N); cudaMemcpy (h_uacc_0, uacc_0, sizeof(double)*N*N*N, cudaMemcpyDeviceToHost); cudaMemcpy (h_uacc_1, uacc_1, sizeof(double)*N*N*N, cudaMemcpyDeviceToHost); cudaMemcpy (h_uacc_2, uacc_2, sizeof(double)*N*N*N, cudaMemcpyDeviceToHost); cudaFree (uacc_0); cudaFree (uacc_1); cudaFree (uacc_2); cudaFree (u_0); cudaFree (u_1); cudaFree (u_2); cudaFree (mu); cudaFree (la); cudaFree (strx); cudaFree (stry); cudaFree (strz); }
.file "tmpxft_000b673e_00000000-6_reordered-k.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error : %s, %s\n" .text .globl _Z11check_errorPKc .type _Z11check_errorPKc, @function _Z11check_errorPKc: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L6 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $-1, %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z11check_errorPKc, .-_Z11check_errorPKc .globl _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i .type _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i: .LFB2083: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq 304(%rsp), %rax movq %rax, 16(%rsp) movq 312(%rsp), %rax movq %rax, 8(%rsp) movq 320(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 32(%rsp), %rax movq %rax, 168(%rsp) leaq 24(%rsp), %rax movq %rax, 176(%rsp) movq %rcx, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 184(%rsp) movq %r8, 64(%rsp) leaq 64(%rsp), %rax movq %rax, 192(%rsp) movq %r9, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 200(%rsp) movq 288(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 208(%rsp) movq 296(%rsp), %rax movq %rax, 88(%rsp) leaq 88(%rsp), %rax movq %rax, 216(%rsp) leaq 16(%rsp), %rax movq %rax, 224(%rsp) leaq 8(%rsp), %rax movq %rax, 232(%rsp) movq %rsp, %rax movq %rax, 240(%rsp) leaq 328(%rsp), %rax movq %rax, 248(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $1, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) leaq 104(%rsp), %rcx leaq 96(%rsp), %rdx leaq 124(%rsp), %rsi leaq 112(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 264(%rsp), %rax subq %fs:40, %rax jne .L12 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 104(%rsp) .cfi_def_cfa_offset 296 pushq 104(%rsp) .cfi_def_cfa_offset 304 leaq 176(%rsp), %r9 movq 140(%rsp), %rcx movl 148(%rsp), %r8d movq 128(%rsp), %rsi movl 136(%rsp), %edx leaq _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i .globl _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .type _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, @function _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, .-_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "Failed to allocate device memory for uacc_0\n" .align 8 .LC2: .string "Failed to allocate device memory for uacc_1\n" .align 8 .LC3: .string "Failed to allocate device memory for uacc_2\n" .align 8 .LC4: .string "Failed to allocate device memory for u_0\n" .align 8 .LC5: .string "Failed to allocate device memory for u_1\n" .align 8 .LC6: .string "Failed to allocate device memory for u_2\n" .align 8 .LC7: .string "Failed to allocate device memory for mu\n" .align 8 .LC8: .string "Failed to allocate device memory for la\n" .align 8 .LC9: .string "Failed to allocate device memory for strx\n" .align 8 .LC10: .string "Failed to allocate device memory for stry\n" .align 8 .LC11: .string "Failed to allocate device memory for strz\n" .text .globl host_code .type host_code, @function host_code: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $200, %rsp .cfi_def_cfa_offset 256 movq %rdi, (%rsp) movq %rsi, 8(%rsp) movq %rdx, 16(%rsp) movq %rcx, 24(%rsp) movq %r8, 32(%rsp) movq %r9, 40(%rsp) movq 256(%rsp), %r15 movq 264(%rsp), %r14 movq 272(%rsp), %r13 movq 280(%rsp), %rax movq %rax, 48(%rsp) movq 288(%rsp), %rbx movq %rbx, 56(%rsp) movl 296(%rsp), %r12d movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax movslq %r12d, %rbp movq %rbp, %rbx imulq %rbp, %rbx imulq %rbp, %rbx salq $3, %rbx leaq 72(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC1(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq (%rsp), %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT leaq 80(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC2(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 8(%rsp), %rsi movq 80(%rsp), %rdi call cudaMemcpy@PLT leaq 88(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 16(%rsp), %rsi movq 88(%rsp), %rdi call cudaMemcpy@PLT leaq 96(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC4(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq 96(%rsp), %rdi call cudaMemcpy@PLT leaq 104(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC5(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 32(%rsp), %rsi movq 104(%rsp), %rdi call cudaMemcpy@PLT leaq 112(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC6(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 40(%rsp), %rsi movq 112(%rsp), %rdi call cudaMemcpy@PLT leaq 120(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC7(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r15, %rsi movq 120(%rsp), %rdi call cudaMemcpy@PLT leaq 128(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC8(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 128(%rsp), %rdi call cudaMemcpy@PLT salq $3, %rbp leaq 136(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC9(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbp, %rdx movq %r13, %rsi movq 136(%rsp), %rdi call cudaMemcpy@PLT leaq 144(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC10(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbp, %rdx movq 48(%rsp), %rsi movq 144(%rsp), %rdi call cudaMemcpy@PLT leaq 152(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC11(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbp, %rdx movq 56(%rsp), %rsi movq 152(%rsp), %rdi call cudaMemcpy@PLT movl %r12d, %eax shrl %eax movl %eax, %esi addl $1, %esi testb $1, %r12b cmove %eax, %esi movl %r12d, %edx shrl $4, %edx movl %edx, %eax addl $1, %eax testb $15, %r12b cmove %edx, %eax movl %eax, 172(%rsp) movl %esi, 176(%rsp) movl $16, 160(%rsp) movl $2, 164(%rsp) movl $0, %r9d movl $0, %r8d movq 160(%rsp), %rdx movl $2, %ecx movq 172(%rsp), %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L20: movl $2, %ecx movq %rbx, %rdx movq 72(%rsp), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 80(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 88(%rsp), %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 80(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rdi call cudaFree@PLT movq 96(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rdi call cudaFree@PLT movq 112(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rdi call cudaFree@PLT movq 128(%rsp), %rdi call cudaFree@PLT movq 136(%rsp), %rdi call cudaFree@PLT movq 144(%rsp), %rdi call cudaFree@PLT movq 152(%rsp), %rdi call cudaFree@PLT movq 184(%rsp), %rax subq %fs:40, %rax jne .L24 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq %r12 .cfi_def_cfa_offset 264 pushq 160(%rsp) .cfi_def_cfa_offset 272 pushq 160(%rsp) .cfi_def_cfa_offset 280 pushq 160(%rsp) .cfi_def_cfa_offset 288 pushq 160(%rsp) .cfi_def_cfa_offset 296 pushq 160(%rsp) .cfi_def_cfa_offset 304 movq 160(%rsp), %r9 movq 152(%rsp), %r8 movq 144(%rsp), %rcx movq 136(%rsp), %rdx movq 128(%rsp), %rsi movq 120(%rsp), %rdi call _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i addq $48, %rsp .cfi_def_cfa_offset 256 jmp .L20 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size host_code, .-host_code .section .rodata.str1.1 .LC12: .string "_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <stdio.h> #include "hip/hip_runtime.h" #define max(x,y) ((x) > (y)? (x) : (y)) #define min(x,y) ((x) < (y)? (x) : (y)) #define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1) void check_error (const char* message) { hipError_t error = hipGetLastError (); if (error != hipSuccess) { printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error)); exit(-1); } } __global__ void sw4 (double * uacc_in_0, double * uacc_in_1, double * uacc_in_2, double * __restrict__ u_in_0, double * __restrict__ u_in_1, double * __restrict__ u_in_2, double * __restrict__ mu_in, double * __restrict__ la_in, double * strx, double * stry, double * strz, int N) { //Determing the block's indices int blockdim_i= (int)(blockDim.x); int i0 = (int)(blockIdx.x)*(blockdim_i); int i = max (i0, 0) + (int)(threadIdx.x); int blockdim_j= (int)(blockDim.y); int j0 = (int)(blockIdx.y)*(blockdim_j); int j = max (j0, 0) + (int)(threadIdx.y); int blockdim_k= (int)(blockDim.z); int k0 = (int)(blockIdx.z)*(blockdim_k); int k = max (k0, 0) + (int)(threadIdx.z); // Assumptions int a1 = 1; double h = 3.7; double cof = 1e0 / ( h * h); double (*uacc_0)[304][304] = (double (*)[304][304])uacc_in_0; double (*uacc_1)[304][304] = (double (*)[304][304])uacc_in_1; double (*uacc_2)[304][304] = (double (*)[304][304])uacc_in_2; double (*u_0)[304][304] = (double (*)[304][304])u_in_0; double (*u_1)[304][304] = (double (*)[304][304])u_in_1; double (*u_2)[304][304] = (double (*)[304][304])u_in_2; double (*mu)[304][304] = (double (*)[304][304])mu_in; double (*la)[304][304] = (double (*)[304][304])la_in; double mux1, mux2, mux3, mux4, muy1, muy2, muy3, muy4, muz1, muz2, muz3, muz4; double r1, r2, r3; if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) { double muz4; double muz1; double muy4; double muy1; double mux4; double mux1; double muz3; double muz2; double muy3; double muy2; double mux3; double mux2; double _t_5_; double _t_7_; double _t_3_; double _t_9_; double _t_11_; double _t_10_; double _t_12_; double _t_13_; double _t_14_; double _t_0_; double _t_16_; double _t_15_; double _t_17_; double _t_18_; double _t_19_; double _t_4_; double _t_2_; double _t_6_; double _t_1_; double _t_8_; double r1; double _t_30_; double _t_31_; double _t_33_; double _t_29_; double _t_27_; double _t_26_; double _t_28_; double _t_32_; double _t_34_; double _t_20_; double _t_22_; double _t_21_; double _t_23_; double _t_24_; double _t_25_; double _t_36_; double _t_35_; double _t_52_; double _t_37_; double _t_54_; double _t_38_; double _t_39_; double r2; double _t_56_; double _t_58_; double _t_42_; double _t_41_; double _t_43_; double _t_44_; double _t_45_; double _t_40_; double _t_47_; double _t_46_; double _t_48_; double _t_49_; double _t_50_; double _t_53_; double _t_51_; double _t_55_; double _t_57_; double _t_59_; double r3; double _t_102_; double _t_100_; double _t_76_; double _t_74_; double _t_63_; double _t_61_; double _t_89_; double _t_87_; double _t_103_; double _t_77_; double _t_85_; double _t_111_; double _t_104_; double _t_80_; double _t_112_; double _t_83_; double _t_101_; double _t_78_; double _t_106_; double _t_86_; double _t_109_; double _t_75_; double _t_107_; double _t_81_; double _t_84_; double _t_105_; double _t_110_; double _t_108_; double _t_60_; double _t_79_; double _t_82_; double _t_64_; double _t_90_; double _t_72_; double _t_98_; double _t_65_; double _t_93_; double _t_73_; double _t_96_; double _t_62_; double _t_91_; double _t_67_; double _t_99_; double _t_88_; double _t_70_; double _t_68_; double _t_94_; double _t_92_; double _t_71_; double _t_97_; double _t_95_; double _t_66_; double _t_69_; double _t_129_; double _t_127_; double _t_155_; double _t_153_; double _t_116_; double _t_114_; double _t_142_; double _t_140_; double _t_117_; double _t_143_; double _t_125_; double _t_151_; double _t_118_; double _t_146_; double _t_126_; double _t_149_; double _t_115_; double _t_144_; double _t_120_; double _t_152_; double _t_141_; double _t_123_; double _t_121_; double _t_147_; double _t_145_; double _t_124_; double _t_150_; double _t_148_; double _t_113_; double _t_119_; double _t_122_; double _t_130_; double _t_156_; double _t_138_; double _t_164_; double _t_131_; double _t_159_; double _t_139_; double _t_128_; double _t_162_; double _t_157_; double _t_133_; double _t_165_; double _t_136_; double _t_154_; double _t_134_; double _t_160_; double _t_137_; double _t_158_; double _t_132_; double _t_163_; double _t_135_; double _t_161_; double _t_169_; double _t_182_; double _t_167_; double _t_180_; double _t_195_; double _t_208_; double _t_193_; double _t_206_; double _t_170_; double _t_183_; double _t_178_; double _t_191_; double _t_171_; double _t_186_; double _t_179_; double _t_168_; double _t_189_; double _t_184_; double _t_173_; double _t_192_; double _t_176_; double _t_181_; double _t_174_; double _t_187_; double _t_177_; double _t_185_; double _t_172_; double _t_190_; double _t_175_; double _t_166_; double _t_188_; double _t_196_; double _t_209_; double _t_204_; double _t_217_; double _t_197_; double _t_212_; double _t_205_; double _t_194_; double _t_215_; double _t_210_; double _t_199_; double _t_218_; double _t_207_; double _t_202_; double _t_200_; double _t_213_; double _t_211_; double _t_203_; double _t_198_; double _t_216_; double _t_201_; double _t_214_; double uacc_0kc0jc0ic0; double uacc_1kc0jc0ic0; double uacc_2kc0jc0ic0; muz4 = -3.0 / 4.0 * mu[k+2][j][i] * strz[k+2]; muz4 += mu[k+1][j][i] * strz[k+1]; muz4 -= 3.0 / 4.0 * mu[k][j][i] * strz[k]; muz1 = -3.0 / 4.0 * mu[k][j][i] * strz[k]; muz1 += mu[k-1][j][i] * strz[k-1]; muz1 -= 3.0 / 4.0 * mu[k-2][j][i] * strz[k-2]; muy4 = -3.0 / 4.0 * mu[k][j][i] * stry[j]; muy4 += mu[k][j+1][i] * stry[j+1]; muy4 -= 3.0 / 4.0 * mu[k][j+2][i] * stry[j+2]; muy1 = -3.0 / 4.0 * mu[k][j][i] * stry[j]; muy1 += mu[k][j-1][i] * stry[j-1]; muy1 -= 3.0 / 4.0 * mu[k][j-2][i] * stry[j-2]; mux4 = -3.0 / 4.0 * mu[k][j][i] * strx[i]; mux4 += mu[k][j][i+1] * strx[i+1]; mux4 -= 3.0 / 4.0 * mu[k][j][i+2] * strx[i+2]; mux1 = -3.0 / 4.0 * mu[k][j][i] * strx[i]; mux1 += mu[k][j][i-1] * strx[i-1]; mux1 -= 3.0 / 4.0 * mu[k][j][i-2] * strx[i-2]; muz3 = mu[k-1][j][i] * strz[k-1]; muz3 += mu[k+2][j][i] * strz[k+2]; muz3 += 3.0 * mu[k+1][j][i] * strz[k+1]; muz3 += 3.0 * mu[k][j][i] * strz[k]; muz2 = mu[k-2][j][i] * strz[k-2]; muz2 += mu[k+1][j][i] * strz[k+1]; muz2 += 3.0 * mu[k][j][i] * strz[k]; muz2 += 3.0 * mu[k-1][j][i] * strz[k-1]; muy3 = mu[k][j-1][i] * stry[j-1]; muy3 += mu[k][j+2][i] * stry[j+2]; muy3 += 3.0 * mu[k][j+1][i] * stry[j+1]; muy3 += 3.0 * mu[k][j][i] * stry[j]; muy2 = mu[k][j-2][i] * stry[j-2]; muy2 += mu[k][j+1][i] * stry[j+1]; muy2 += 3.0 * mu[k][j][i] * stry[j]; muy2 += 3.0 * mu[k][j-1][i] * stry[j-1]; mux3 = mu[k][j][i-1] * strx[i-1]; mux3 += mu[k][j][i+2] * strx[i+2]; mux3 += 3.0 * mu[k][j][i+1] * strx[i+1]; mux3 += 3.0 * mu[k][j][i] * strx[i]; mux2 = mu[k][j][i-2] * strx[i-2]; mux2 += mu[k][j][i+1] * strx[i+1]; mux2 += 3.0 * mu[k][j][i] * strx[i]; mux2 += 3.0 * mu[k][j][i-1] * strx[i-1]; _t_5_ = u_0[k][j][i-1]; _t_5_ -= u_0[k][j][i]; _t_7_ = -u_0[k][j][i]; _t_7_ += u_0[k][j][i+1]; _t_3_ = -u_0[k][j][i]; _t_3_ += u_0[k][j][i-2]; _t_9_ = -u_0[k][j][i]; _t_9_ += u_0[k][j][i+2]; _t_11_ = -u_0[k][j][i]; _t_11_ += u_0[k][j-2][i]; _t_10_ = muy1 * _t_11_; _t_12_ = -u_0[k][j][i]; _t_12_ += u_0[k][j-1][i]; _t_10_ += muy2 * _t_12_; _t_13_ = -u_0[k][j][i]; _t_13_ += u_0[k][j+1][i]; _t_10_ += muy3 * _t_13_; _t_14_ = -u_0[k][j][i]; _t_14_ += u_0[k][j+2][i]; _t_10_ += muy4 * _t_14_; _t_0_ = stry[j] * _t_10_; _t_16_ = -u_0[k][j][i]; _t_16_ += u_0[k-2][j][i]; _t_15_ = muz1 * _t_16_; _t_17_ = -u_0[k][j][i]; _t_17_ += u_0[k-1][j][i]; _t_15_ += muz2 * _t_17_; _t_18_ = -u_0[k][j][i]; _t_19_ = -u_0[k][j][i]; _t_18_ += u_0[k+1][j][i]; _t_15_ += muz3 * _t_18_; _t_19_ += u_0[k+2][j][i]; _t_15_ += muz4 * _t_19_; _t_0_ += strz[k] * _t_15_; _t_4_ = 2.0 * mux2; _t_2_ = 2.0 * mux1; _t_2_ -= 3.0 / 4.0 * la[k][j][i-2] * strx[i-2]; _t_4_ += la[k][j][i-2] * strx[i-2]; _t_2_ += la[k][j][i-1] * strx[i-1]; _t_4_ += 3.0 * la[k][j][i-1] * strx[i-1]; _t_6_ = la[k][j][i-1] * strx[i-1]; _t_6_ += 2.0 * mux3; _t_2_ -= 3.0 / 4.0 * la[k][j][i] * strx[i]; _t_4_ += 3.0 * la[k][j][i] * strx[i]; _t_6_ += 3.0 * la[k][j][i] * strx[i]; _t_1_ = _t_2_ * _t_3_; _t_8_ = -3.0 / 4.0 * la[k][j][i] * strx[i]; _t_8_ += 2.0 * mux4; _t_4_ += la[k][j][i+1] * strx[i+1]; _t_1_ += _t_4_ * _t_5_; _t_6_ += 3.0 * la[k][j][i+1] * strx[i+1]; _t_8_ += la[k][j][i+1] * strx[i+1]; _t_6_ += la[k][j][i+2] * strx[i+2]; _t_1_ += _t_6_ * _t_7_; _t_8_ -= 3.0 / 4.0 * la[k][j][i+2] * strx[i+2]; _t_1_ += _t_8_ * _t_9_; _t_0_ += strx[i] * _t_1_; r1 = 1.0 / 6.0 * _t_0_; _t_30_ = u_1[k][j-1][i]; _t_31_ = 3.0 * la[k][j][i] * stry[j]; _t_31_ += 2.0 * muy3; _t_33_ = -3.0 / 4.0 * la[k][j][i] * stry[j]; _t_33_ += 2.0 * muy4; _t_31_ += la[k][j+2][i] * stry[j+2]; _t_33_ -= 3.0 / 4.0 * la[k][j+2][i] * stry[j+2]; _t_29_ = 3.0 * la[k][j][i] * stry[j]; _t_29_ += 2.0 * muy2; _t_29_ += la[k][j+1][i] * stry[j+1]; _t_31_ += 3.0 * la[k][j+1][i] * stry[j+1]; _t_33_ += la[k][j+1][i] * stry[j+1]; _t_27_ = -3.0 / 4.0 * la[k][j][i] * stry[j]; _t_27_ += 2.0 * muy1; _t_27_ += la[k][j-1][i] * stry[j-1]; _t_29_ += 3.0 * la[k][j-1][i] * stry[j-1]; _t_31_ += la[k][j-1][i] * stry[j-1]; _t_27_ -= 3.0 / 4.0 * la[k][j-2][i] * stry[j-2]; _t_29_ += la[k][j-2][i] * stry[j-2]; _t_30_ -= u_1[k][j][i]; _t_26_ = _t_29_ * _t_30_; _t_28_ = -u_1[k][j][i]; _t_28_ += u_1[k][j-2][i]; _t_26_ += _t_27_ * _t_28_; _t_32_ = -u_1[k][j][i]; _t_32_ += u_1[k][j+1][i]; _t_26_ += _t_31_ * _t_32_; _t_34_ = -u_1[k][j][i]; _t_34_ += u_1[k][j+2][i]; _t_26_ += _t_33_ * _t_34_; _t_20_ = stry[j] * _t_26_; _t_22_ = -u_1[k][j][i]; _t_22_ += u_1[k][j][i-2]; _t_21_ = mux1 * _t_22_; _t_23_ = -u_1[k][j][i]; _t_23_ += u_1[k][j][i-1]; _t_21_ += mux2 * _t_23_; _t_24_ = -u_1[k][j][i]; _t_24_ += u_1[k][j][i+1]; _t_21_ += mux3 * _t_24_; _t_25_ = -u_1[k][j][i]; _t_25_ += u_1[k][j][i+2]; _t_21_ += mux4 * _t_25_; _t_20_ += strx[i] * _t_21_; _t_36_ = -u_1[k][j][i]; _t_36_ += u_1[k-2][j][i]; _t_35_ = muz1 * _t_36_; _t_52_ = -3.0 / 4.0 * la[k][j][i] * strz[k]; _t_52_ += 2.0 * muz1; _t_37_ = -u_1[k][j][i]; _t_37_ += u_1[k-1][j][i]; _t_35_ += muz2 * _t_37_; _t_54_ = 3.0 * la[k][j][i] * strz[k]; _t_54_ += 2.0 * muz2; _t_52_ -= 3.0 / 4.0 * la[k-2][j][i] * strz[k-2]; _t_54_ += la[k-2][j][i] * strz[k-2]; _t_38_ = -u_1[k][j][i]; _t_39_ = -u_1[k][j][i]; _t_38_ += u_1[k+1][j][i]; _t_35_ += muz3 * _t_38_; _t_39_ += u_1[k+2][j][i]; _t_35_ += muz4 * _t_39_; _t_20_ += strz[k] * _t_35_; r2 = 1.0 / 6.0 * _t_20_; _t_56_ = 3.0 * la[k][j][i] * strz[k]; _t_56_ += 2.0 * muz3; _t_58_ = -3.0 / 4.0 * la[k][j][i] * strz[k]; _t_58_ += 2.0 * muz4; _t_52_ += la[k-1][j][i] * strz[k-1]; _t_54_ += 3.0 * la[k-1][j][i] * strz[k-1]; _t_56_ += la[k-1][j][i] * strz[k-1]; _t_54_ += la[k+1][j][i] * strz[k+1]; _t_56_ += 3.0 * la[k+1][j][i] * strz[k+1]; _t_58_ += la[k+1][j][i] * strz[k+1]; _t_56_ += la[k+2][j][i] * strz[k+2]; _t_58_ -= 3.0 / 4.0 * la[k+2][j][i] * strz[k+2]; _t_42_ = u_2[k][j][i-2]; _t_42_ -= u_2[k][j][i]; _t_41_ = mux1 * _t_42_; _t_43_ = -u_2[k][j][i]; _t_43_ += u_2[k][j][i-1]; _t_41_ += mux2 * _t_43_; _t_44_ = -u_2[k][j][i]; _t_44_ += u_2[k][j][i+1]; _t_41_ += mux3 * _t_44_; _t_45_ = -u_2[k][j][i]; _t_45_ += u_2[k][j][i+2]; _t_41_ += mux4 * _t_45_; _t_40_ = strx[i] * _t_41_; _t_47_ = -u_2[k][j][i]; _t_47_ += u_2[k][j-2][i]; _t_46_ = muy1 * _t_47_; _t_48_ = -u_2[k][j][i]; _t_48_ += u_2[k][j-1][i]; _t_46_ += muy2 * _t_48_; _t_49_ = -u_2[k][j][i]; _t_49_ += u_2[k][j+1][i]; _t_46_ += muy3 * _t_49_; _t_50_ = -u_2[k][j][i]; _t_50_ += u_2[k][j+2][i]; _t_46_ += muy4 * _t_50_; _t_40_ += stry[j] * _t_46_; _t_53_ = -u_2[k][j][i]; _t_53_ += u_2[k-2][j][i]; _t_51_ = _t_52_ * _t_53_; _t_55_ = -u_2[k][j][i]; _t_55_ += u_2[k-1][j][i]; _t_51_ += _t_54_ * _t_55_; _t_57_ = -u_2[k][j][i]; _t_59_ = -u_2[k][j][i]; _t_57_ += u_2[k+1][j][i]; _t_51_ += _t_56_ * _t_57_; _t_59_ += u_2[k+2][j][i]; _t_51_ += _t_58_ * _t_59_; _t_40_ += strz[k] * _t_51_; r3 = 1.0 / 6.0 * _t_40_; _t_102_ = stry[j] * strz[k]; _t_100_ = _t_102_ * 1.0 / 144.0; _t_76_ = stry[j] * strz[k]; _t_74_ = _t_76_ * 1.0 / 144.0; _t_63_ = strx[i] * strz[k]; _t_61_ = _t_63_ * 1.0 / 144.0; _t_89_ = strx[i] * strz[k]; _t_87_ = _t_89_ * 1.0 / 144.0; _t_103_ = u_1[k-2][j-2][i]; _t_77_ = u_1[k-2][j-2][i]; _t_103_ -= u_1[k-2][j+2][i]; _t_85_ = u_1[k-2][j+2][i]; _t_77_ -= u_1[k+2][j-2][i]; _t_111_ = u_1[k+2][j-2][i]; _t_85_ -= u_1[k+2][j+2][i]; _t_111_ -= u_1[k+2][j+2][i]; _t_104_ = -u_1[k-2][j-1][i]; _t_80_ = u_1[k-2][j-1][i]; _t_80_ -= u_1[k+2][j-1][i]; _t_112_ = -u_1[k+2][j-1][i]; _t_104_ += u_1[k-2][j+1][i]; _t_103_ += 8.0 * _t_104_; _t_83_ = u_1[k-2][j+1][i]; _t_83_ -= u_1[k+2][j+1][i]; _t_112_ += u_1[k+2][j+1][i]; _t_111_ += 8.0 * _t_112_; _t_101_ = la[k-2][j][i] * _t_103_; _t_101_ -= la[k+2][j][i] * _t_111_; _t_78_ = -u_1[k-1][j-2][i]; _t_106_ = u_1[k-1][j-2][i]; _t_106_ -= u_1[k-1][j+2][i]; _t_86_ = -u_1[k-1][j+2][i]; _t_78_ += u_1[k+1][j-2][i]; _t_77_ += 8.0 * _t_78_; _t_109_ = u_1[k+1][j-2][i]; _t_86_ += u_1[k+1][j+2][i]; _t_85_ += 8.0 * _t_86_; _t_109_ -= u_1[k+1][j+2][i]; _t_75_ = mu[k][j-2][i] * _t_77_; _t_75_ -= mu[k][j+2][i] * _t_85_; _t_107_ = -u_1[k-1][j-1][i]; _t_81_ = -u_1[k-1][j-1][i]; _t_107_ += u_1[k-1][j+1][i]; _t_106_ += 8.0 * _t_107_; _t_84_ = -u_1[k-1][j+1][i]; _t_105_ = la[k-1][j][i] * _t_106_; _t_101_ -= 8.0 * _t_105_; _t_81_ += u_1[k+1][j-1][i]; _t_80_ += 8.0 * _t_81_; _t_110_ = -u_1[k+1][j-1][i]; _t_84_ += u_1[k+1][j+1][i]; _t_83_ += 8.0 * _t_84_; _t_110_ += u_1[k+1][j+1][i]; _t_109_ += 8.0 * _t_110_; _t_108_ = la[k+1][j][i] * _t_109_; _t_101_ += 8.0 * _t_108_; _t_60_ = _t_100_ * _t_101_; _t_79_ = mu[k][j-1][i] * _t_80_; _t_75_ -= 8.0 * _t_79_; _t_82_ = mu[k][j+1][i] * _t_83_; _t_75_ += 8.0 * _t_82_; _t_60_ += _t_74_ * _t_75_; _t_64_ = u_0[k-2][j][i-2]; _t_90_ = u_0[k-2][j][i-2]; _t_90_ -= u_0[k-2][j][i+2]; _t_72_ = u_0[k-2][j][i+2]; _t_64_ -= u_0[k+2][j][i-2]; _t_98_ = u_0[k+2][j][i-2]; _t_72_ -= u_0[k+2][j][i+2]; _t_98_ -= u_0[k+2][j][i+2]; _t_65_ = -u_0[k-1][j][i-2]; _t_93_ = u_0[k-1][j][i-2]; _t_93_ -= u_0[k-1][j][i+2]; _t_73_ = -u_0[k-1][j][i+2]; _t_65_ += u_0[k+1][j][i-2]; _t_64_ += 8.0 * _t_65_; _t_96_ = u_0[k+1][j][i-2]; _t_73_ += u_0[k+1][j][i+2]; _t_72_ += 8.0 * _t_73_; _t_96_ -= u_0[k+1][j][i+2]; _t_62_ = mu[k][j][i-2] * _t_64_; _t_62_ -= mu[k][j][i+2] * _t_72_; _t_91_ = -u_0[k-2][j][i-1]; _t_67_ = u_0[k-2][j][i-1]; _t_67_ -= u_0[k+2][j][i-1]; _t_99_ = -u_0[k+2][j][i-1]; _t_91_ += u_0[k-2][j][i+1]; _t_90_ += 8.0 * _t_91_; _t_88_ = la[k-2][j][i] * _t_90_; _t_70_ = u_0[k-2][j][i+1]; _t_70_ -= u_0[k+2][j][i+1]; _t_99_ += u_0[k+2][j][i+1]; _t_98_ += 8.0 * _t_99_; _t_88_ -= la[k+2][j][i] * _t_98_; _t_68_ = -u_0[k-1][j][i-1]; _t_94_ = -u_0[k-1][j][i-1]; _t_94_ += u_0[k-1][j][i+1]; _t_93_ += 8.0 * _t_94_; _t_92_ = la[k-1][j][i] * _t_93_; _t_88_ -= 8.0 * _t_92_; _t_71_ = -u_0[k-1][j][i+1]; _t_68_ += u_0[k+1][j][i-1]; _t_67_ += 8.0 * _t_68_; _t_97_ = -u_0[k+1][j][i-1]; _t_71_ += u_0[k+1][j][i+1]; _t_70_ += 8.0 * _t_71_; _t_97_ += u_0[k+1][j][i+1]; _t_96_ += 8.0 * _t_97_; _t_95_ = la[k+1][j][i] * _t_96_; _t_88_ += 8.0 * _t_95_; _t_60_ += _t_87_ * _t_88_; _t_66_ = mu[k][j][i-1] * _t_67_; _t_62_ -= 8.0 * _t_66_; _t_69_ = mu[k][j][i+1] * _t_70_; _t_62_ += 8.0 * _t_69_; _t_60_ += _t_61_ * _t_62_; r3 += _t_60_; _t_129_ = strx[i] * strz[k]; _t_127_ = _t_129_ * 1.0 / 144.0; _t_155_ = strx[i] * strz[k]; _t_153_ = _t_155_ * 1.0 / 144.0; _t_116_ = strx[i] * stry[j]; _t_114_ = _t_116_ * 1.0 / 144.0; _t_142_ = strx[i] * stry[j]; _t_140_ = _t_142_ * 1.0 / 144.0; _t_117_ = u_1[k][j-2][i-2]; _t_143_ = u_1[k][j-2][i-2]; _t_143_ -= u_1[k][j-2][i+2]; _t_125_ = u_1[k][j-2][i+2]; _t_117_ -= u_1[k][j+2][i-2]; _t_151_ = u_1[k][j+2][i-2]; _t_125_ -= u_1[k][j+2][i+2]; _t_151_ -= u_1[k][j+2][i+2]; _t_118_ = -u_1[k][j-1][i-2]; _t_146_ = u_1[k][j-1][i-2]; _t_146_ -= u_1[k][j-1][i+2]; _t_126_ = -u_1[k][j-1][i+2]; _t_118_ += u_1[k][j+1][i-2]; _t_117_ += 8.0 * _t_118_; _t_149_ = u_1[k][j+1][i-2]; _t_126_ += u_1[k][j+1][i+2]; _t_125_ += 8.0 * _t_126_; _t_149_ -= u_1[k][j+1][i+2]; _t_115_ = la[k][j][i-2] * _t_117_; _t_115_ -= la[k][j][i+2] * _t_125_; _t_144_ = -u_1[k][j-2][i-1]; _t_120_ = u_1[k][j-2][i-1]; _t_120_ -= u_1[k][j+2][i-1]; _t_152_ = -u_1[k][j+2][i-1]; _t_144_ += u_1[k][j-2][i+1]; _t_143_ += 8.0 * _t_144_; _t_141_ = mu[k][j-2][i] * _t_143_; _t_123_ = u_1[k][j-2][i+1]; _t_123_ -= u_1[k][j+2][i+1]; _t_152_ += u_1[k][j+2][i+1]; _t_151_ += 8.0 * _t_152_; _t_141_ -= mu[k][j+2][i] * _t_151_; _t_121_ = -u_1[k][j-1][i-1]; _t_147_ = -u_1[k][j-1][i-1]; _t_147_ += u_1[k][j-1][i+1]; _t_146_ += 8.0 * _t_147_; _t_145_ = mu[k][j-1][i] * _t_146_; _t_141_ -= 8.0 * _t_145_; _t_124_ = -u_1[k][j-1][i+1]; _t_121_ += u_1[k][j+1][i-1]; _t_120_ += 8.0 * _t_121_; _t_150_ = -u_1[k][j+1][i-1]; _t_124_ += u_1[k][j+1][i+1]; _t_123_ += 8.0 * _t_124_; _t_150_ += u_1[k][j+1][i+1]; _t_149_ += 8.0 * _t_150_; _t_148_ = mu[k][j+1][i] * _t_149_; _t_141_ += 8.0 * _t_148_; _t_113_ = _t_140_ * _t_141_; _t_119_ = la[k][j][i-1] * _t_120_; _t_115_ -= 8.0 * _t_119_; _t_122_ = la[k][j][i+1] * _t_123_; _t_115_ += 8.0 * _t_122_; _t_113_ += _t_114_ * _t_115_; _t_130_ = u_2[k-2][j][i-2]; _t_156_ = u_2[k-2][j][i-2]; _t_156_ -= u_2[k-2][j][i+2]; _t_138_ = u_2[k-2][j][i+2]; _t_130_ -= u_2[k+2][j][i-2]; _t_164_ = u_2[k+2][j][i-2]; _t_138_ -= u_2[k+2][j][i+2]; _t_164_ -= u_2[k+2][j][i+2]; _t_131_ = -u_2[k-1][j][i-2]; _t_159_ = u_2[k-1][j][i-2]; _t_159_ -= u_2[k-1][j][i+2]; _t_139_ = -u_2[k-1][j][i+2]; _t_131_ += u_2[k+1][j][i-2]; _t_130_ += 8.0 * _t_131_; _t_128_ = la[k][j][i-2] * _t_130_; _t_162_ = u_2[k+1][j][i-2]; _t_139_ += u_2[k+1][j][i+2]; _t_138_ += 8.0 * _t_139_; _t_128_ -= la[k][j][i+2] * _t_138_; _t_162_ -= u_2[k+1][j][i+2]; _t_157_ = -u_2[k-2][j][i-1]; _t_133_ = u_2[k-2][j][i-1]; _t_133_ -= u_2[k+2][j][i-1]; _t_165_ = -u_2[k+2][j][i-1]; _t_157_ += u_2[k-2][j][i+1]; _t_156_ += 8.0 * _t_157_; _t_136_ = u_2[k-2][j][i+1]; _t_136_ -= u_2[k+2][j][i+1]; _t_165_ += u_2[k+2][j][i+1]; _t_164_ += 8.0 * _t_165_; _t_154_ = mu[k-2][j][i] * _t_156_; _t_154_ -= mu[k+2][j][i] * _t_164_; _t_134_ = -u_2[k-1][j][i-1]; _t_160_ = -u_2[k-1][j][i-1]; _t_160_ += u_2[k-1][j][i+1]; _t_159_ += 8.0 * _t_160_; _t_137_ = -u_2[k-1][j][i+1]; _t_158_ = mu[k-1][j][i] * _t_159_; _t_154_ -= 8.0 * _t_158_; _t_134_ += u_2[k+1][j][i-1]; _t_133_ += 8.0 * _t_134_; _t_132_ = la[k][j][i-1] * _t_133_; _t_128_ -= 8.0 * _t_132_; _t_163_ = -u_2[k+1][j][i-1]; _t_137_ += u_2[k+1][j][i+1]; _t_136_ += 8.0 * _t_137_; _t_163_ += u_2[k+1][j][i+1]; _t_162_ += 8.0 * _t_163_; _t_135_ = la[k][j][i+1] * _t_136_; _t_128_ += 8.0 * _t_135_; _t_113_ += _t_127_ * _t_128_; _t_161_ = mu[k+1][j][i] * _t_162_; _t_154_ += 8.0 * _t_161_; _t_113_ += _t_153_ * _t_154_; r1 += _t_113_; _t_169_ = strx[i] * stry[j]; _t_182_ = strx[i] * stry[j]; _t_167_ = _t_169_ * 1.0 / 144.0; _t_180_ = _t_182_ * 1.0 / 144.0; _t_195_ = stry[j] * strz[k]; _t_208_ = stry[j] * strz[k]; _t_193_ = _t_195_ * 1.0 / 144.0; _t_206_ = _t_208_ * 1.0 / 144.0; _t_170_ = u_0[k][j-2][i-2]; _t_183_ = u_0[k][j-2][i-2]; _t_183_ -= u_0[k][j-2][i+2]; _t_178_ = u_0[k][j-2][i+2]; _t_170_ -= u_0[k][j+2][i-2]; _t_191_ = u_0[k][j+2][i-2]; _t_178_ -= u_0[k][j+2][i+2]; _t_191_ -= u_0[k][j+2][i+2]; _t_171_ = -u_0[k][j-1][i-2]; _t_186_ = u_0[k][j-1][i-2]; _t_186_ -= u_0[k][j-1][i+2]; _t_179_ = -u_0[k][j-1][i+2]; _t_171_ += u_0[k][j+1][i-2]; _t_170_ += 8.0 * _t_171_; _t_168_ = mu[k][j][i-2] * _t_170_; _t_189_ = u_0[k][j+1][i-2]; _t_179_ += u_0[k][j+1][i+2]; _t_178_ += 8.0 * _t_179_; _t_168_ -= mu[k][j][i+2] * _t_178_; _t_189_ -= u_0[k][j+1][i+2]; _t_184_ = -u_0[k][j-2][i-1]; _t_173_ = u_0[k][j-2][i-1]; _t_173_ -= u_0[k][j+2][i-1]; _t_192_ = -u_0[k][j+2][i-1]; _t_184_ += u_0[k][j-2][i+1]; _t_183_ += 8.0 * _t_184_; _t_176_ = u_0[k][j-2][i+1]; _t_176_ -= u_0[k][j+2][i+1]; _t_192_ += u_0[k][j+2][i+1]; _t_191_ += 8.0 * _t_192_; _t_181_ = la[k][j-2][i] * _t_183_; _t_181_ -= la[k][j+2][i] * _t_191_; _t_174_ = -u_0[k][j-1][i-1]; _t_187_ = -u_0[k][j-1][i-1]; _t_187_ += u_0[k][j-1][i+1]; _t_186_ += 8.0 * _t_187_; _t_177_ = -u_0[k][j-1][i+1]; _t_185_ = la[k][j-1][i] * _t_186_; _t_181_ -= 8.0 * _t_185_; _t_174_ += u_0[k][j+1][i-1]; _t_173_ += 8.0 * _t_174_; _t_172_ = mu[k][j][i-1] * _t_173_; _t_168_ -= 8.0 * _t_172_; _t_190_ = -u_0[k][j+1][i-1]; _t_177_ += u_0[k][j+1][i+1]; _t_176_ += 8.0 * _t_177_; _t_190_ += u_0[k][j+1][i+1]; _t_189_ += 8.0 * _t_190_; _t_175_ = mu[k][j][i+1] * _t_176_; _t_168_ += 8.0 * _t_175_; _t_166_ = _t_167_ * _t_168_; _t_188_ = la[k][j+1][i] * _t_189_; _t_181_ += 8.0 * _t_188_; _t_166_ += _t_180_ * _t_181_; _t_196_ = u_2[k-2][j-2][i]; _t_209_ = u_2[k-2][j-2][i]; _t_209_ -= u_2[k-2][j+2][i]; _t_204_ = u_2[k-2][j+2][i]; _t_196_ -= u_2[k+2][j-2][i]; _t_217_ = u_2[k+2][j-2][i]; _t_204_ -= u_2[k+2][j+2][i]; _t_217_ -= u_2[k+2][j+2][i]; _t_197_ = -u_2[k-1][j-2][i]; _t_212_ = u_2[k-1][j-2][i]; _t_212_ -= u_2[k-1][j+2][i]; _t_205_ = -u_2[k-1][j+2][i]; _t_197_ += u_2[k+1][j-2][i]; _t_196_ += 8.0 * _t_197_; _t_194_ = la[k][j-2][i] * _t_196_; _t_215_ = u_2[k+1][j-2][i]; _t_205_ += u_2[k+1][j+2][i]; _t_204_ += 8.0 * _t_205_; _t_194_ -= la[k][j+2][i] * _t_204_; _t_215_ -= u_2[k+1][j+2][i]; _t_210_ = -u_2[k-2][j-1][i]; _t_199_ = u_2[k-2][j-1][i]; _t_199_ -= u_2[k+2][j-1][i]; _t_218_ = -u_2[k+2][j-1][i]; _t_210_ += u_2[k-2][j+1][i]; _t_209_ += 8.0 * _t_210_; _t_207_ = mu[k-2][j][i] * _t_209_; _t_202_ = u_2[k-2][j+1][i]; _t_202_ -= u_2[k+2][j+1][i]; _t_218_ += u_2[k+2][j+1][i]; _t_217_ += 8.0 * _t_218_; _t_207_ -= mu[k+2][j][i] * _t_217_; _t_200_ = -u_2[k-1][j-1][i]; _t_213_ = -u_2[k-1][j-1][i]; _t_213_ += u_2[k-1][j+1][i]; _t_212_ += 8.0 * _t_213_; _t_211_ = mu[k-1][j][i] * _t_212_; _t_207_ -= 8.0 * _t_211_; _t_203_ = -u_2[k-1][j+1][i]; _t_200_ += u_2[k+1][j-1][i]; _t_199_ += 8.0 * _t_200_; _t_198_ = la[k][j-1][i] * _t_199_; _t_194_ -= 8.0 * _t_198_; _t_216_ = -u_2[k+1][j-1][i]; _t_203_ += u_2[k+1][j+1][i]; _t_202_ += 8.0 * _t_203_; _t_216_ += u_2[k+1][j+1][i]; _t_215_ += 8.0 * _t_216_; _t_201_ = la[k][j+1][i] * _t_202_; _t_194_ += 8.0 * _t_201_; _t_166_ += _t_193_ * _t_194_; _t_214_ = mu[k+1][j][i] * _t_215_; _t_207_ += 8.0 * _t_214_; _t_166_ += _t_206_ * _t_207_; r2 += _t_166_; uacc_0kc0jc0ic0 = a1 * uacc_0[k][j][i]; uacc_0kc0jc0ic0 += cof * r1; uacc_0[k][j][i] = uacc_0kc0jc0ic0; uacc_1kc0jc0ic0 = a1 * uacc_1[k][j][i]; uacc_1kc0jc0ic0 += cof * r2; uacc_1[k][j][i] = uacc_1kc0jc0ic0; uacc_2kc0jc0ic0 = a1 * uacc_2[k][j][i]; uacc_2kc0jc0ic0 += cof * r3; uacc_2[k][j][i] = uacc_2kc0jc0ic0; } } extern "C" void host_code (double *h_uacc_0, double *h_uacc_1, double *h_uacc_2, double *h_u_0, double *h_u_1, double *h_u_2, double *h_mu, double *h_la, double *h_strx, double *h_stry, double *h_strz, int N) { double *uacc_0; hipMalloc (&uacc_0, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for uacc_0\n"); hipMemcpy (uacc_0, h_uacc_0, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *uacc_1; hipMalloc (&uacc_1, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for uacc_1\n"); hipMemcpy (uacc_1, h_uacc_1, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *uacc_2; hipMalloc (&uacc_2, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for uacc_2\n"); hipMemcpy (uacc_2, h_uacc_2, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *u_0; hipMalloc (&u_0, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for u_0\n"); hipMemcpy (u_0, h_u_0, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *u_1; hipMalloc (&u_1, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for u_1\n"); hipMemcpy (u_1, h_u_1, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *u_2; hipMalloc (&u_2, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for u_2\n"); hipMemcpy (u_2, h_u_2, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *mu; hipMalloc (&mu, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for mu\n"); hipMemcpy (mu, h_mu, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *la; hipMalloc (&la, sizeof(double)*N*N*N); check_error ("Failed to allocate device memory for la\n"); hipMemcpy (la, h_la, sizeof(double)*N*N*N, hipMemcpyHostToDevice); double *strx; hipMalloc (&strx, sizeof(double)*N); check_error ("Failed to allocate device memory for strx\n"); hipMemcpy (strx, h_strx, sizeof(double)*N, hipMemcpyHostToDevice); double *stry; hipMalloc (&stry, sizeof(double)*N); check_error ("Failed to allocate device memory for stry\n"); hipMemcpy (stry, h_stry, sizeof(double)*N, hipMemcpyHostToDevice); double *strz; hipMalloc (&strz, sizeof(double)*N); check_error ("Failed to allocate device memory for strz\n"); hipMemcpy (strz, h_strz, sizeof(double)*N, hipMemcpyHostToDevice); dim3 blockconfig (16, 2, 2); dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z)); sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N); hipMemcpy (h_uacc_0, uacc_0, sizeof(double)*N*N*N, hipMemcpyDeviceToHost); hipMemcpy (h_uacc_1, uacc_1, sizeof(double)*N*N*N, hipMemcpyDeviceToHost); hipMemcpy (h_uacc_2, uacc_2, sizeof(double)*N*N*N, hipMemcpyDeviceToHost); hipFree (uacc_0); hipFree (uacc_1); hipFree (uacc_2); hipFree (u_0); hipFree (u_1); hipFree (u_2); hipFree (mu); hipFree (la); hipFree (strx); hipFree (stry); hipFree (strz); }
.text .file "reordered-k.hip" .globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc .p2align 4, 0x90 .type _Z11check_errorPKc,@function _Z11check_errorPKc: # @_Z11check_errorPKc .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB0_2 # %bb.1: popq %rbx .cfi_def_cfa_offset 8 retq .LBB0_2: .cfi_def_cfa_offset 16 movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rbx, %rsi movq %rax, %rdx xorl %eax, %eax callq printf movl $-1, %edi callq exit .Lfunc_end0: .size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc .cfi_endproc # -- End function .globl _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .p2align 4, 0x90 .type _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i,@function _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i: # @_Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .cfi_startproc # %bb.0: subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 208(%rsp), %rax movq %rax, 144(%rsp) leaq 216(%rsp), %rax movq %rax, 152(%rsp) leaq 224(%rsp), %rax movq %rax, 160(%rsp) leaq 232(%rsp), %rax movq %rax, 168(%rsp) leaq 240(%rsp), %rax movq %rax, 176(%rsp) leaq 248(%rsp), %rax movq %rax, 184(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $216, %rsp .cfi_adjust_cfa_offset -216 retq .Lfunc_end1: .size _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .cfi_endproc # -- End function .globl host_code # -- Begin function host_code .p2align 4, 0x90 .type host_code,@function host_code: # @host_code .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $376, %rsp # imm = 0x178 .cfi_def_cfa_offset 432 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, 128(%rsp) # 8-byte Spill movq %r8, %rbx movq %rcx, %r15 movq %rdx, 104(%rsp) # 8-byte Spill movq %rsi, 112(%rsp) # 8-byte Spill movq %rdi, %rbp movslq 472(%rsp), %r12 leaq (,%r12,8), %r13 movq %r12, %r14 imulq %r12, %r14 imulq %r13, %r14 leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_1 # %bb.3: # %_Z11check_errorPKc.exit movq 24(%rsp), %rdi movq %rbp, 120(%rsp) # 8-byte Spill movq %rbp, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_4 # %bb.5: # %_Z11check_errorPKc.exit93 movq 16(%rsp), %rdi movq 112(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_6 # %bb.7: # %_Z11check_errorPKc.exit95 movq 8(%rsp), %rdi movq 104(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 88(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_8 # %bb.9: # %_Z11check_errorPKc.exit97 movq 88(%rsp), %rdi movq %r15, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 80(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_10 # %bb.11: # %_Z11check_errorPKc.exit99 movq 80(%rsp), %rdi movq %rbx, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 72(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_12 # %bb.13: # %_Z11check_errorPKc.exit101 movq 72(%rsp), %rdi movq 128(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 64(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_14 # %bb.15: # %_Z11check_errorPKc.exit103 movq 432(%rsp), %rsi movq 64(%rsp), %rdi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 56(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax movq 120(%rsp), %rbp # 8-byte Reload jne .LBB2_16 # %bb.17: # %_Z11check_errorPKc.exit105 movq 440(%rsp), %rsi movq 56(%rsp), %rdi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 48(%rsp), %rdi movq %r13, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_18 # %bb.19: # %_Z11check_errorPKc.exit107 movq 448(%rsp), %rsi movq 48(%rsp), %rdi movq %r13, %rdx movl $1, %ecx callq hipMemcpy leaq 40(%rsp), %rdi movq %r13, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_20 # %bb.21: # %_Z11check_errorPKc.exit109 movq 456(%rsp), %rsi movq 40(%rsp), %rdi movq %r13, %rdx movl $1, %ecx callq hipMemcpy leaq 32(%rsp), %rdi movq %r13, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_22 # %bb.23: # %_Z11check_errorPKc.exit111 movq 464(%rsp), %rsi movq 32(%rsp), %rdi movq %r13, %rdx movl $1, %ecx callq hipMemcpy movl %r12d, %eax shrl $4, %eax leal 1(%rax), %ecx testb $15, %r12b cmovel %eax, %ecx movl %r12d, %eax shrl %eax leal 1(%rax), %esi testb $1, %r12b cmovel %eax, %esi movq %rsi, %rdi shlq $32, %rdi orq %rcx, %rdi movabsq $8589934608, %rdx # imm = 0x200000010 # kill: def $esi killed $esi killed $rsi movl $2, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_25 # %bb.24: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq 88(%rsp), %rsi movq 80(%rsp), %rdi movq 72(%rsp), %r8 movq 64(%rsp), %r9 movq 56(%rsp), %r10 movq 48(%rsp), %r11 movq 40(%rsp), %rbx movq 32(%rsp), %r15 movq %rax, 264(%rsp) movq %rcx, 256(%rsp) movq %rdx, 248(%rsp) movq %rsi, 240(%rsp) movq %rdi, 232(%rsp) movq %r8, 224(%rsp) movq %r9, 216(%rsp) movq %r10, 208(%rsp) movq %r11, 200(%rsp) movq %rbx, 192(%rsp) movq %r15, 184(%rsp) movl %r12d, 100(%rsp) leaq 264(%rsp), %rax movq %rax, 272(%rsp) leaq 256(%rsp), %rax movq %rax, 280(%rsp) leaq 248(%rsp), %rax movq %rax, 288(%rsp) leaq 240(%rsp), %rax movq %rax, 296(%rsp) leaq 232(%rsp), %rax movq %rax, 304(%rsp) leaq 224(%rsp), %rax movq %rax, 312(%rsp) leaq 216(%rsp), %rax movq %rax, 320(%rsp) leaq 208(%rsp), %rax movq %rax, 328(%rsp) leaq 200(%rsp), %rax movq %rax, 336(%rsp) leaq 192(%rsp), %rax movq %rax, 344(%rsp) leaq 184(%rsp), %rax movq %rax, 352(%rsp) leaq 100(%rsp), %rax movq %rax, 360(%rsp) leaq 168(%rsp), %rdi leaq 152(%rsp), %rsi leaq 144(%rsp), %rdx leaq 136(%rsp), %rcx callq __hipPopCallConfiguration movq 168(%rsp), %rsi movl 176(%rsp), %edx movq 152(%rsp), %rcx movl 160(%rsp), %r8d leaq 272(%rsp), %r9 movl $_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, %edi pushq 136(%rsp) .cfi_adjust_cfa_offset 8 pushq 152(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_25: movq 24(%rsp), %rsi movq %rbp, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rsi movq 112(%rsp), %rdi # 8-byte Reload movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rsi movq 104(%rsp), %rdi # 8-byte Reload movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 88(%rsp), %rdi callq hipFree movq 80(%rsp), %rdi callq hipFree movq 72(%rsp), %rdi callq hipFree movq 64(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree addq $376, %rsp # imm = 0x178 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_1: .cfi_def_cfa_offset 432 movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.1, %esi jmp .LBB2_2 .LBB2_4: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.2, %esi jmp .LBB2_2 .LBB2_6: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.3, %esi jmp .LBB2_2 .LBB2_8: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.4, %esi jmp .LBB2_2 .LBB2_10: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.5, %esi jmp .LBB2_2 .LBB2_12: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.6, %esi jmp .LBB2_2 .LBB2_14: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.7, %esi jmp .LBB2_2 .LBB2_16: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.8, %esi jmp .LBB2_2 .LBB2_18: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.9, %esi jmp .LBB2_2 .LBB2_20: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.10, %esi jmp .LBB2_2 .LBB2_22: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.11, %esi .LBB2_2: movq %rax, %rdx xorl %eax, %eax callq printf movl $-1, %edi callq exit .Lfunc_end2: .size host_code, .Lfunc_end2-host_code .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error : %s, %s\n" .size .L.str, 21 .type _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .section .rodata,"a",@progbits .globl _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .p2align 3, 0x0 _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i: .quad _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .size _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "Failed to allocate device memory for uacc_0\n" .size .L.str.1, 45 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate device memory for uacc_1\n" .size .L.str.2, 45 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate device memory for uacc_2\n" .size .L.str.3, 45 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate device memory for u_0\n" .size .L.str.4, 42 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to allocate device memory for u_1\n" .size .L.str.5, 42 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to allocate device memory for u_2\n" .size .L.str.6, 42 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to allocate device memory for mu\n" .size .L.str.7, 41 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Failed to allocate device memory for la\n" .size .L.str.8, 41 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to allocate device memory for strx\n" .size .L.str.9, 43 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Failed to allocate device memory for stry\n" .size .L.str.10, 43 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Failed to allocate device memory for strz\n" .size .L.str.11, 43 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i" .size .L__unnamed_1, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000b673e_00000000-6_reordered-k.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error : %s, %s\n" .text .globl _Z11check_errorPKc .type _Z11check_errorPKc, @function _Z11check_errorPKc: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L6 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $-1, %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z11check_errorPKc, .-_Z11check_errorPKc .globl _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i .type _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i: .LFB2083: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq 304(%rsp), %rax movq %rax, 16(%rsp) movq 312(%rsp), %rax movq %rax, 8(%rsp) movq 320(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 32(%rsp), %rax movq %rax, 168(%rsp) leaq 24(%rsp), %rax movq %rax, 176(%rsp) movq %rcx, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 184(%rsp) movq %r8, 64(%rsp) leaq 64(%rsp), %rax movq %rax, 192(%rsp) movq %r9, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 200(%rsp) movq 288(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 208(%rsp) movq 296(%rsp), %rax movq %rax, 88(%rsp) leaq 88(%rsp), %rax movq %rax, 216(%rsp) leaq 16(%rsp), %rax movq %rax, 224(%rsp) leaq 8(%rsp), %rax movq %rax, 232(%rsp) movq %rsp, %rax movq %rax, 240(%rsp) leaq 328(%rsp), %rax movq %rax, 248(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $1, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) leaq 104(%rsp), %rcx leaq 96(%rsp), %rdx leaq 124(%rsp), %rsi leaq 112(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 264(%rsp), %rax subq %fs:40, %rax jne .L12 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 104(%rsp) .cfi_def_cfa_offset 296 pushq 104(%rsp) .cfi_def_cfa_offset 304 leaq 176(%rsp), %r9 movq 140(%rsp), %rcx movl 148(%rsp), %r8d movq 128(%rsp), %rsi movl 136(%rsp), %edx leaq _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i .globl _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .type _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, @function _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, .-_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "Failed to allocate device memory for uacc_0\n" .align 8 .LC2: .string "Failed to allocate device memory for uacc_1\n" .align 8 .LC3: .string "Failed to allocate device memory for uacc_2\n" .align 8 .LC4: .string "Failed to allocate device memory for u_0\n" .align 8 .LC5: .string "Failed to allocate device memory for u_1\n" .align 8 .LC6: .string "Failed to allocate device memory for u_2\n" .align 8 .LC7: .string "Failed to allocate device memory for mu\n" .align 8 .LC8: .string "Failed to allocate device memory for la\n" .align 8 .LC9: .string "Failed to allocate device memory for strx\n" .align 8 .LC10: .string "Failed to allocate device memory for stry\n" .align 8 .LC11: .string "Failed to allocate device memory for strz\n" .text .globl host_code .type host_code, @function host_code: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $200, %rsp .cfi_def_cfa_offset 256 movq %rdi, (%rsp) movq %rsi, 8(%rsp) movq %rdx, 16(%rsp) movq %rcx, 24(%rsp) movq %r8, 32(%rsp) movq %r9, 40(%rsp) movq 256(%rsp), %r15 movq 264(%rsp), %r14 movq 272(%rsp), %r13 movq 280(%rsp), %rax movq %rax, 48(%rsp) movq 288(%rsp), %rbx movq %rbx, 56(%rsp) movl 296(%rsp), %r12d movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax movslq %r12d, %rbp movq %rbp, %rbx imulq %rbp, %rbx imulq %rbp, %rbx salq $3, %rbx leaq 72(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC1(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq (%rsp), %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT leaq 80(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC2(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 8(%rsp), %rsi movq 80(%rsp), %rdi call cudaMemcpy@PLT leaq 88(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 16(%rsp), %rsi movq 88(%rsp), %rdi call cudaMemcpy@PLT leaq 96(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC4(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq 96(%rsp), %rdi call cudaMemcpy@PLT leaq 104(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC5(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 32(%rsp), %rsi movq 104(%rsp), %rdi call cudaMemcpy@PLT leaq 112(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC6(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 40(%rsp), %rsi movq 112(%rsp), %rdi call cudaMemcpy@PLT leaq 120(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC7(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r15, %rsi movq 120(%rsp), %rdi call cudaMemcpy@PLT leaq 128(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC8(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 128(%rsp), %rdi call cudaMemcpy@PLT salq $3, %rbp leaq 136(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC9(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbp, %rdx movq %r13, %rsi movq 136(%rsp), %rdi call cudaMemcpy@PLT leaq 144(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC10(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbp, %rdx movq 48(%rsp), %rsi movq 144(%rsp), %rdi call cudaMemcpy@PLT leaq 152(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC11(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbp, %rdx movq 56(%rsp), %rsi movq 152(%rsp), %rdi call cudaMemcpy@PLT movl %r12d, %eax shrl %eax movl %eax, %esi addl $1, %esi testb $1, %r12b cmove %eax, %esi movl %r12d, %edx shrl $4, %edx movl %edx, %eax addl $1, %eax testb $15, %r12b cmove %edx, %eax movl %eax, 172(%rsp) movl %esi, 176(%rsp) movl $16, 160(%rsp) movl $2, 164(%rsp) movl $0, %r9d movl $0, %r8d movq 160(%rsp), %rdx movl $2, %ecx movq 172(%rsp), %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L20: movl $2, %ecx movq %rbx, %rdx movq 72(%rsp), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 80(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 88(%rsp), %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 80(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rdi call cudaFree@PLT movq 96(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rdi call cudaFree@PLT movq 112(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rdi call cudaFree@PLT movq 128(%rsp), %rdi call cudaFree@PLT movq 136(%rsp), %rdi call cudaFree@PLT movq 144(%rsp), %rdi call cudaFree@PLT movq 152(%rsp), %rdi call cudaFree@PLT movq 184(%rsp), %rax subq %fs:40, %rax jne .L24 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq %r12 .cfi_def_cfa_offset 264 pushq 160(%rsp) .cfi_def_cfa_offset 272 pushq 160(%rsp) .cfi_def_cfa_offset 280 pushq 160(%rsp) .cfi_def_cfa_offset 288 pushq 160(%rsp) .cfi_def_cfa_offset 296 pushq 160(%rsp) .cfi_def_cfa_offset 304 movq 160(%rsp), %r9 movq 152(%rsp), %r8 movq 144(%rsp), %rcx movq 136(%rsp), %rdx movq 128(%rsp), %rsi movq 120(%rsp), %rdi call _Z43__device_stub__Z3sw4PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i addq $48, %rsp .cfi_def_cfa_offset 256 jmp .L20 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size host_code, .-host_code .section .rodata.str1.1 .LC12: .string "_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "reordered-k.hip" .globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc .p2align 4, 0x90 .type _Z11check_errorPKc,@function _Z11check_errorPKc: # @_Z11check_errorPKc .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB0_2 # %bb.1: popq %rbx .cfi_def_cfa_offset 8 retq .LBB0_2: .cfi_def_cfa_offset 16 movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rbx, %rsi movq %rax, %rdx xorl %eax, %eax callq printf movl $-1, %edi callq exit .Lfunc_end0: .size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc .cfi_endproc # -- End function .globl _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .p2align 4, 0x90 .type _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i,@function _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i: # @_Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .cfi_startproc # %bb.0: subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 208(%rsp), %rax movq %rax, 144(%rsp) leaq 216(%rsp), %rax movq %rax, 152(%rsp) leaq 224(%rsp), %rax movq %rax, 160(%rsp) leaq 232(%rsp), %rax movq %rax, 168(%rsp) leaq 240(%rsp), %rax movq %rax, 176(%rsp) leaq 248(%rsp), %rax movq %rax, 184(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $216, %rsp .cfi_adjust_cfa_offset -216 retq .Lfunc_end1: .size _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .cfi_endproc # -- End function .globl host_code # -- Begin function host_code .p2align 4, 0x90 .type host_code,@function host_code: # @host_code .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $376, %rsp # imm = 0x178 .cfi_def_cfa_offset 432 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, 128(%rsp) # 8-byte Spill movq %r8, %rbx movq %rcx, %r15 movq %rdx, 104(%rsp) # 8-byte Spill movq %rsi, 112(%rsp) # 8-byte Spill movq %rdi, %rbp movslq 472(%rsp), %r12 leaq (,%r12,8), %r13 movq %r12, %r14 imulq %r12, %r14 imulq %r13, %r14 leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_1 # %bb.3: # %_Z11check_errorPKc.exit movq 24(%rsp), %rdi movq %rbp, 120(%rsp) # 8-byte Spill movq %rbp, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_4 # %bb.5: # %_Z11check_errorPKc.exit93 movq 16(%rsp), %rdi movq 112(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_6 # %bb.7: # %_Z11check_errorPKc.exit95 movq 8(%rsp), %rdi movq 104(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 88(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_8 # %bb.9: # %_Z11check_errorPKc.exit97 movq 88(%rsp), %rdi movq %r15, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 80(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_10 # %bb.11: # %_Z11check_errorPKc.exit99 movq 80(%rsp), %rdi movq %rbx, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 72(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_12 # %bb.13: # %_Z11check_errorPKc.exit101 movq 72(%rsp), %rdi movq 128(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 64(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_14 # %bb.15: # %_Z11check_errorPKc.exit103 movq 432(%rsp), %rsi movq 64(%rsp), %rdi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 56(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax movq 120(%rsp), %rbp # 8-byte Reload jne .LBB2_16 # %bb.17: # %_Z11check_errorPKc.exit105 movq 440(%rsp), %rsi movq 56(%rsp), %rdi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 48(%rsp), %rdi movq %r13, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_18 # %bb.19: # %_Z11check_errorPKc.exit107 movq 448(%rsp), %rsi movq 48(%rsp), %rdi movq %r13, %rdx movl $1, %ecx callq hipMemcpy leaq 40(%rsp), %rdi movq %r13, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_20 # %bb.21: # %_Z11check_errorPKc.exit109 movq 456(%rsp), %rsi movq 40(%rsp), %rdi movq %r13, %rdx movl $1, %ecx callq hipMemcpy leaq 32(%rsp), %rdi movq %r13, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_22 # %bb.23: # %_Z11check_errorPKc.exit111 movq 464(%rsp), %rsi movq 32(%rsp), %rdi movq %r13, %rdx movl $1, %ecx callq hipMemcpy movl %r12d, %eax shrl $4, %eax leal 1(%rax), %ecx testb $15, %r12b cmovel %eax, %ecx movl %r12d, %eax shrl %eax leal 1(%rax), %esi testb $1, %r12b cmovel %eax, %esi movq %rsi, %rdi shlq $32, %rdi orq %rcx, %rdi movabsq $8589934608, %rdx # imm = 0x200000010 # kill: def $esi killed $esi killed $rsi movl $2, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_25 # %bb.24: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq 88(%rsp), %rsi movq 80(%rsp), %rdi movq 72(%rsp), %r8 movq 64(%rsp), %r9 movq 56(%rsp), %r10 movq 48(%rsp), %r11 movq 40(%rsp), %rbx movq 32(%rsp), %r15 movq %rax, 264(%rsp) movq %rcx, 256(%rsp) movq %rdx, 248(%rsp) movq %rsi, 240(%rsp) movq %rdi, 232(%rsp) movq %r8, 224(%rsp) movq %r9, 216(%rsp) movq %r10, 208(%rsp) movq %r11, 200(%rsp) movq %rbx, 192(%rsp) movq %r15, 184(%rsp) movl %r12d, 100(%rsp) leaq 264(%rsp), %rax movq %rax, 272(%rsp) leaq 256(%rsp), %rax movq %rax, 280(%rsp) leaq 248(%rsp), %rax movq %rax, 288(%rsp) leaq 240(%rsp), %rax movq %rax, 296(%rsp) leaq 232(%rsp), %rax movq %rax, 304(%rsp) leaq 224(%rsp), %rax movq %rax, 312(%rsp) leaq 216(%rsp), %rax movq %rax, 320(%rsp) leaq 208(%rsp), %rax movq %rax, 328(%rsp) leaq 200(%rsp), %rax movq %rax, 336(%rsp) leaq 192(%rsp), %rax movq %rax, 344(%rsp) leaq 184(%rsp), %rax movq %rax, 352(%rsp) leaq 100(%rsp), %rax movq %rax, 360(%rsp) leaq 168(%rsp), %rdi leaq 152(%rsp), %rsi leaq 144(%rsp), %rdx leaq 136(%rsp), %rcx callq __hipPopCallConfiguration movq 168(%rsp), %rsi movl 176(%rsp), %edx movq 152(%rsp), %rcx movl 160(%rsp), %r8d leaq 272(%rsp), %r9 movl $_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, %edi pushq 136(%rsp) .cfi_adjust_cfa_offset 8 pushq 152(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_25: movq 24(%rsp), %rsi movq %rbp, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rsi movq 112(%rsp), %rdi # 8-byte Reload movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rsi movq 104(%rsp), %rdi # 8-byte Reload movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 88(%rsp), %rdi callq hipFree movq 80(%rsp), %rdi callq hipFree movq 72(%rsp), %rdi callq hipFree movq 64(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree addq $376, %rsp # imm = 0x178 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_1: .cfi_def_cfa_offset 432 movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.1, %esi jmp .LBB2_2 .LBB2_4: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.2, %esi jmp .LBB2_2 .LBB2_6: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.3, %esi jmp .LBB2_2 .LBB2_8: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.4, %esi jmp .LBB2_2 .LBB2_10: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.5, %esi jmp .LBB2_2 .LBB2_12: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.6, %esi jmp .LBB2_2 .LBB2_14: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.7, %esi jmp .LBB2_2 .LBB2_16: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.8, %esi jmp .LBB2_2 .LBB2_18: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.9, %esi jmp .LBB2_2 .LBB2_20: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.10, %esi jmp .LBB2_2 .LBB2_22: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.11, %esi .LBB2_2: movq %rax, %rdx xorl %eax, %eax callq printf movl $-1, %edi callq exit .Lfunc_end2: .size host_code, .Lfunc_end2-host_code .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error : %s, %s\n" .size .L.str, 21 .type _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .section .rodata,"a",@progbits .globl _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .p2align 3, 0x0 _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i: .quad _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .size _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "Failed to allocate device memory for uacc_0\n" .size .L.str.1, 45 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate device memory for uacc_1\n" .size .L.str.2, 45 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate device memory for uacc_2\n" .size .L.str.3, 45 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate device memory for u_0\n" .size .L.str.4, 42 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to allocate device memory for u_1\n" .size .L.str.5, 42 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to allocate device memory for u_2\n" .size .L.str.6, 42 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to allocate device memory for mu\n" .size .L.str.7, 41 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Failed to allocate device memory for la\n" .size .L.str.8, 41 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to allocate device memory for strx\n" .size .L.str.9, 43 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Failed to allocate device memory for stry\n" .size .L.str.10, 43 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Failed to allocate device memory for strz\n" .size .L.str.11, 43 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3sw4PdS_S_S_S_S_S_S_S_S_S_i" .size .L__unnamed_1, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__sw4PdS_S_S_S_S_S_S_S_S_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3sw4PdS_S_S_S_S_S_S_S_S_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void matrixTriUpper(float *a, int m, int n) { //setting matricies to their upper bound for(int i = 0; i < m; ++i) { for(int j = 0; j < n; ++j) { if(i>j) a[i*n + j] = 0; a[i*n + j] = a[i*n + j]; } } }
code for sm_80 Function : _Z14matrixTriUpperPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fca00078e00ff */ /*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */ /* 0x000fc80003f03270 */ /*0030*/ ISETP.GT.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */ /* 0x000fda0004704670 */ /*0040*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0050*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe200078e00ff */ /*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0070*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */ /* 0x000fe400078e00ff */ /*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */ /* 0x000fe200078e00ff */ /*0090*/ IADD3 R0, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */ /* 0x000fc80007ffe1ff */ /*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */ /* 0x000fe40003f26070 */ /*00b0*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */ /* 0x000fc800078ec0ff */ /*00c0*/ IADD3 R4, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000047a10 */ /* 0x000fc80007ffe1ff */ /*00d0*/ IMAD R11, R5, c[0x0][0x16c], RZ ; /* 0x00005b00050b7a24 */ /* 0x000fe400078e02ff */ /*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x000fe200078e00ff */ /*00f0*/ @!P1 BRA 0x290 ; /* 0x0000019000009947 */ /* 0x000fea0003800000 */ /*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe400078e00ff */ /*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x000fe400078e00ff */ /*0120*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */ /* 0x000fc800078e0202 */ /*0130*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */ /* 0x000fe400078e0002 */ /*0140*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e0003 */ /*0150*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */ /* 0x000fe400078e0004 */ /*0160*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */ /* 0x041fe20007ffe0ff */ /*0170*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */ /* 0x000fe200078e000c */ /*0180*/ IADD3 R8, R6.reuse, 0x2, RZ ; /* 0x0000000206087810 */ /* 0x040fe40007ffe0ff */ /*0190*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */ /* 0x000fe20003f44070 */ /*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */ /* 0x000fe200078e0009 */ /*01b0*/ IADD3 R10, R6, 0x3, RZ ; /* 0x00000003060a7810 */ /* 0x000fc40007ffe0ff */ /*01c0*/ ISETP.GT.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */ /* 0x000fe40003f04070 */ /*01d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */ /* 0x000fe40007ffe0ff */ /*01e0*/ ISETP.GT.U32.AND P3, PT, R5.reuse, R8, PT ; /* 0x000000080500720c */ /* 0x040fe40003f64070 */ /*01f0*/ ISETP.GT.U32.AND P4, PT, R5, R10, PT ; /* 0x0000000a0500720c */ /* 0x000fe40003f84070 */ /*0200*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x000fe20007ffe0ff */ /*0210*/ @P2 STG.E [R2.64+0x4], RZ ; /* 0x000004ff02002986 */ /* 0x0001e2000c101904 */ /*0220*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fc60003f45270 */ /*0230*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */ /* 0x0001e2000c101904 */ /*0240*/ IADD3 R9, P0, R2, 0x10, RZ ; /* 0x0000001002097810 */ /* 0x000fc60007f1e0ff */ /*0250*/ @P3 STG.E [R2.64+0x8], RZ ; /* 0x000008ff02003986 */ /* 0x0001e4000c101904 */ /*0260*/ IMAD.X R12, RZ, RZ, R3, P0 ; /* 0x000000ffff0c7224 */ /* 0x000fe400000e0603 */ /*0270*/ @P4 STG.E [R2.64+0xc], RZ ; /* 0x00000cff02004986 */ /* 0x0001e4000c101904 */ /*0280*/ @P2 BRA 0x160 ; /* 0xfffffed000002947 */ /* 0x000fea000383ffff */ /*0290*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fda0003f05270 */ /*02a0*/ @!P0 BRA 0x390 ; /* 0x000000e000008947 */ /* 0x000fea0003800000 */ /*02b0*/ ISETP.GT.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */ /* 0x000fe20003f04070 */ /*02c0*/ IMAD.IADD R2, R11, 0x1, R6 ; /* 0x000000010b027824 */ /* 0x001fe400078e0206 */ /*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fc800078e00ff */ /*02e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fcc00078e0203 */ /*02f0*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */ /* 0x0001e2000c101904 */ /*0300*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */ /* 0x000fda0003f05270 */ /*0310*/ @!P0 BRA 0x390 ; /* 0x0000007000008947 */ /* 0x000fea0003800000 */ /*0320*/ IADD3 R8, R6.reuse, 0x2, RZ ; /* 0x0000000206087810 */ /* 0x041fe40007ffe0ff */ /*0330*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */ /* 0x000fe40007ffe0ff */ /*0340*/ ISETP.GT.U32.AND P0, PT, R5.reuse, R8, PT ; /* 0x000000080500720c */ /* 0x040fe40003f04070 */ /*0350*/ ISETP.GT.U32.AND P2, PT, R5, R6, PT ; /* 0x000000060500720c */ /* 0x000fe40003f44070 */ /*0360*/ ISETP.EQ.OR P0, PT, R0, 0x2, !P0 ; /* 0x000000020000780c */ /* 0x000fd60004702670 */ /*0370*/ @P2 STG.E [R2.64+0x4], RZ ; /* 0x000004ff02002986 */ /* 0x0001e8000c101904 */ /*0380*/ @!P0 STG.E [R2.64+0x8], RZ ; /* 0x000008ff02008986 */ /* 0x0001e4000c101904 */ /*0390*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */ /* 0x001fc80007ffe0ff */ /*03a0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */ /* 0x000fda0003f06270 */ /*03b0*/ @!P0 BRA 0xd0 ; /* 0xfffffd1000008947 */ /* 0x000fea000383ffff */ /*03c0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*03e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0400*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0410*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0420*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0430*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0440*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0450*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0460*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0470*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void matrixTriUpper(float *a, int m, int n) { //setting matricies to their upper bound for(int i = 0; i < m; ++i) { for(int j = 0; j < n; ++j) { if(i>j) a[i*n + j] = 0; a[i*n + j] = a[i*n + j]; } } }
.file "tmpxft_0007b879_00000000-6_matrixTriUpper.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z14matrixTriUpperPfiiPfii .type _Z36__device_stub__Z14matrixTriUpperPfiiPfii, @function _Z36__device_stub__Z14matrixTriUpperPfiiPfii: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z14matrixTriUpperPfii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z36__device_stub__Z14matrixTriUpperPfiiPfii, .-_Z36__device_stub__Z14matrixTriUpperPfiiPfii .globl _Z14matrixTriUpperPfii .type _Z14matrixTriUpperPfii, @function _Z14matrixTriUpperPfii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z14matrixTriUpperPfiiPfii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14matrixTriUpperPfii, .-_Z14matrixTriUpperPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z14matrixTriUpperPfii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14matrixTriUpperPfii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void matrixTriUpper(float *a, int m, int n) { //setting matricies to their upper bound for(int i = 0; i < m; ++i) { for(int j = 0; j < n; ++j) { if(i>j) a[i*n + j] = 0; a[i*n + j] = a[i*n + j]; } } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void matrixTriUpper(float *a, int m, int n) { //setting matricies to their upper bound for(int i = 0; i < m; ++i) { for(int j = 0; j < n; ++j) { if(i>j) a[i*n + j] = 0; a[i*n + j] = a[i*n + j]; } } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void matrixTriUpper(float *a, int m, int n) { //setting matricies to their upper bound for(int i = 0; i < m; ++i) { for(int j = 0; j < n; ++j) { if(i>j) a[i*n + j] = 0; a[i*n + j] = a[i*n + j]; } } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14matrixTriUpperPfii .globl _Z14matrixTriUpperPfii .p2align 8 .type _Z14matrixTriUpperPfii,@function _Z14matrixTriUpperPfii: s_load_b32 s6, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s6, 1 s_cbranch_scc1 .LBB0_8 s_clause 0x1 s_load_b32 s7, s[0:1], 0xc s_load_b64 s[2:3], s[0:1], 0x0 s_mov_b32 s5, 0 s_mov_b32 s1, 0 s_mov_b32 s8, 0 s_waitcnt lgkmcnt(0) s_cmp_gt_i32 s7, 0 s_cselect_b32 s0, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v0, 0, 1, s0 v_cmp_ne_u32_e64 s0, 1, v0 v_mov_b32_e32 v0, 0 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_add_i32 s8, s8, 1 s_add_i32 s1, s1, s7 s_cmp_eq_u32 s8, s6 s_cbranch_scc1 .LBB0_8 .LBB0_3: s_delay_alu instid0(VALU_DEP_2) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_2 s_mov_b32 s9, 0 s_branch .LBB0_6 .LBB0_5: s_add_i32 s9, s9, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s7, s9 s_cbranch_scc1 .LBB0_2 .LBB0_6: s_cmp_le_u32 s8, s9 s_cbranch_scc1 .LBB0_5 s_add_i32 s4, s1, s9 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[10:11], s[4:5], 2 s_add_u32 s10, s2, s10 s_addc_u32 s11, s3, s11 global_store_b32 v0, v0, s[10:11] s_branch .LBB0_5 .LBB0_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14matrixTriUpperPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 12 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14matrixTriUpperPfii, .Lfunc_end0-_Z14matrixTriUpperPfii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14matrixTriUpperPfii .private_segment_fixed_size: 0 .sgpr_count: 14 .sgpr_spill_count: 0 .symbol: _Z14matrixTriUpperPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 1 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void matrixTriUpper(float *a, int m, int n) { //setting matricies to their upper bound for(int i = 0; i < m; ++i) { for(int j = 0; j < n; ++j) { if(i>j) a[i*n + j] = 0; a[i*n + j] = a[i*n + j]; } } }
.text .file "matrixTriUpper.hip" .globl _Z29__device_stub__matrixTriUpperPfii # -- Begin function _Z29__device_stub__matrixTriUpperPfii .p2align 4, 0x90 .type _Z29__device_stub__matrixTriUpperPfii,@function _Z29__device_stub__matrixTriUpperPfii: # @_Z29__device_stub__matrixTriUpperPfii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z14matrixTriUpperPfii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z29__device_stub__matrixTriUpperPfii, .Lfunc_end0-_Z29__device_stub__matrixTriUpperPfii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14matrixTriUpperPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z14matrixTriUpperPfii,@object # @_Z14matrixTriUpperPfii .section .rodata,"a",@progbits .globl _Z14matrixTriUpperPfii .p2align 3, 0x0 _Z14matrixTriUpperPfii: .quad _Z29__device_stub__matrixTriUpperPfii .size _Z14matrixTriUpperPfii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z14matrixTriUpperPfii" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__matrixTriUpperPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14matrixTriUpperPfii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z14matrixTriUpperPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fca00078e00ff */ /*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */ /* 0x000fc80003f03270 */ /*0030*/ ISETP.GT.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */ /* 0x000fda0004704670 */ /*0040*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0050*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe200078e00ff */ /*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0070*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */ /* 0x000fe400078e00ff */ /*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */ /* 0x000fe200078e00ff */ /*0090*/ IADD3 R0, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */ /* 0x000fc80007ffe1ff */ /*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */ /* 0x000fe40003f26070 */ /*00b0*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */ /* 0x000fc800078ec0ff */ /*00c0*/ IADD3 R4, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000047a10 */ /* 0x000fc80007ffe1ff */ /*00d0*/ IMAD R11, R5, c[0x0][0x16c], RZ ; /* 0x00005b00050b7a24 */ /* 0x000fe400078e02ff */ /*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x000fe200078e00ff */ /*00f0*/ @!P1 BRA 0x290 ; /* 0x0000019000009947 */ /* 0x000fea0003800000 */ /*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe400078e00ff */ /*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x000fe400078e00ff */ /*0120*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */ /* 0x000fc800078e0202 */ /*0130*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */ /* 0x000fe400078e0002 */ /*0140*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */ /* 0x000fe400078e0003 */ /*0150*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */ /* 0x000fe400078e0004 */ /*0160*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */ /* 0x041fe20007ffe0ff */ /*0170*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */ /* 0x000fe200078e000c */ /*0180*/ IADD3 R8, R6.reuse, 0x2, RZ ; /* 0x0000000206087810 */ /* 0x040fe40007ffe0ff */ /*0190*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */ /* 0x000fe20003f44070 */ /*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */ /* 0x000fe200078e0009 */ /*01b0*/ IADD3 R10, R6, 0x3, RZ ; /* 0x00000003060a7810 */ /* 0x000fc40007ffe0ff */ /*01c0*/ ISETP.GT.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */ /* 0x000fe40003f04070 */ /*01d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */ /* 0x000fe40007ffe0ff */ /*01e0*/ ISETP.GT.U32.AND P3, PT, R5.reuse, R8, PT ; /* 0x000000080500720c */ /* 0x040fe40003f64070 */ /*01f0*/ ISETP.GT.U32.AND P4, PT, R5, R10, PT ; /* 0x0000000a0500720c */ /* 0x000fe40003f84070 */ /*0200*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x000fe20007ffe0ff */ /*0210*/ @P2 STG.E [R2.64+0x4], RZ ; /* 0x000004ff02002986 */ /* 0x0001e2000c101904 */ /*0220*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fc60003f45270 */ /*0230*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */ /* 0x0001e2000c101904 */ /*0240*/ IADD3 R9, P0, R2, 0x10, RZ ; /* 0x0000001002097810 */ /* 0x000fc60007f1e0ff */ /*0250*/ @P3 STG.E [R2.64+0x8], RZ ; /* 0x000008ff02003986 */ /* 0x0001e4000c101904 */ /*0260*/ IMAD.X R12, RZ, RZ, R3, P0 ; /* 0x000000ffff0c7224 */ /* 0x000fe400000e0603 */ /*0270*/ @P4 STG.E [R2.64+0xc], RZ ; /* 0x00000cff02004986 */ /* 0x0001e4000c101904 */ /*0280*/ @P2 BRA 0x160 ; /* 0xfffffed000002947 */ /* 0x000fea000383ffff */ /*0290*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fda0003f05270 */ /*02a0*/ @!P0 BRA 0x390 ; /* 0x000000e000008947 */ /* 0x000fea0003800000 */ /*02b0*/ ISETP.GT.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */ /* 0x000fe20003f04070 */ /*02c0*/ IMAD.IADD R2, R11, 0x1, R6 ; /* 0x000000010b027824 */ /* 0x001fe400078e0206 */ /*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fc800078e00ff */ /*02e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fcc00078e0203 */ /*02f0*/ @P0 STG.E [R2.64], RZ ; /* 0x000000ff02000986 */ /* 0x0001e2000c101904 */ /*0300*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */ /* 0x000fda0003f05270 */ /*0310*/ @!P0 BRA 0x390 ; /* 0x0000007000008947 */ /* 0x000fea0003800000 */ /*0320*/ IADD3 R8, R6.reuse, 0x2, RZ ; /* 0x0000000206087810 */ /* 0x041fe40007ffe0ff */ /*0330*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */ /* 0x000fe40007ffe0ff */ /*0340*/ ISETP.GT.U32.AND P0, PT, R5.reuse, R8, PT ; /* 0x000000080500720c */ /* 0x040fe40003f04070 */ /*0350*/ ISETP.GT.U32.AND P2, PT, R5, R6, PT ; /* 0x000000060500720c */ /* 0x000fe40003f44070 */ /*0360*/ ISETP.EQ.OR P0, PT, R0, 0x2, !P0 ; /* 0x000000020000780c */ /* 0x000fd60004702670 */ /*0370*/ @P2 STG.E [R2.64+0x4], RZ ; /* 0x000004ff02002986 */ /* 0x0001e8000c101904 */ /*0380*/ @!P0 STG.E [R2.64+0x8], RZ ; /* 0x000008ff02008986 */ /* 0x0001e4000c101904 */ /*0390*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */ /* 0x001fc80007ffe0ff */ /*03a0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */ /* 0x000fda0003f06270 */ /*03b0*/ @!P0 BRA 0xd0 ; /* 0xfffffd1000008947 */ /* 0x000fea000383ffff */ /*03c0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*03e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0400*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0410*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0420*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0430*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0440*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0450*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0460*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0470*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14matrixTriUpperPfii .globl _Z14matrixTriUpperPfii .p2align 8 .type _Z14matrixTriUpperPfii,@function _Z14matrixTriUpperPfii: s_load_b32 s6, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s6, 1 s_cbranch_scc1 .LBB0_8 s_clause 0x1 s_load_b32 s7, s[0:1], 0xc s_load_b64 s[2:3], s[0:1], 0x0 s_mov_b32 s5, 0 s_mov_b32 s1, 0 s_mov_b32 s8, 0 s_waitcnt lgkmcnt(0) s_cmp_gt_i32 s7, 0 s_cselect_b32 s0, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v0, 0, 1, s0 v_cmp_ne_u32_e64 s0, 1, v0 v_mov_b32_e32 v0, 0 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_add_i32 s8, s8, 1 s_add_i32 s1, s1, s7 s_cmp_eq_u32 s8, s6 s_cbranch_scc1 .LBB0_8 .LBB0_3: s_delay_alu instid0(VALU_DEP_2) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_2 s_mov_b32 s9, 0 s_branch .LBB0_6 .LBB0_5: s_add_i32 s9, s9, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s7, s9 s_cbranch_scc1 .LBB0_2 .LBB0_6: s_cmp_le_u32 s8, s9 s_cbranch_scc1 .LBB0_5 s_add_i32 s4, s1, s9 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[10:11], s[4:5], 2 s_add_u32 s10, s2, s10 s_addc_u32 s11, s3, s11 global_store_b32 v0, v0, s[10:11] s_branch .LBB0_5 .LBB0_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14matrixTriUpperPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 12 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14matrixTriUpperPfii, .Lfunc_end0-_Z14matrixTriUpperPfii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14matrixTriUpperPfii .private_segment_fixed_size: 0 .sgpr_count: 14 .sgpr_spill_count: 0 .symbol: _Z14matrixTriUpperPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 1 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0007b879_00000000-6_matrixTriUpper.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z14matrixTriUpperPfiiPfii .type _Z36__device_stub__Z14matrixTriUpperPfiiPfii, @function _Z36__device_stub__Z14matrixTriUpperPfiiPfii: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z14matrixTriUpperPfii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z36__device_stub__Z14matrixTriUpperPfiiPfii, .-_Z36__device_stub__Z14matrixTriUpperPfiiPfii .globl _Z14matrixTriUpperPfii .type _Z14matrixTriUpperPfii, @function _Z14matrixTriUpperPfii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z14matrixTriUpperPfiiPfii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14matrixTriUpperPfii, .-_Z14matrixTriUpperPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z14matrixTriUpperPfii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14matrixTriUpperPfii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "matrixTriUpper.hip" .globl _Z29__device_stub__matrixTriUpperPfii # -- Begin function _Z29__device_stub__matrixTriUpperPfii .p2align 4, 0x90 .type _Z29__device_stub__matrixTriUpperPfii,@function _Z29__device_stub__matrixTriUpperPfii: # @_Z29__device_stub__matrixTriUpperPfii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z14matrixTriUpperPfii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z29__device_stub__matrixTriUpperPfii, .Lfunc_end0-_Z29__device_stub__matrixTriUpperPfii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14matrixTriUpperPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z14matrixTriUpperPfii,@object # @_Z14matrixTriUpperPfii .section .rodata,"a",@progbits .globl _Z14matrixTriUpperPfii .p2align 3, 0x0 _Z14matrixTriUpperPfii: .quad _Z29__device_stub__matrixTriUpperPfii .size _Z14matrixTriUpperPfii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z14matrixTriUpperPfii" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__matrixTriUpperPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14matrixTriUpperPfii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <thrust/host_vector.h> #include <thrust/device_vector.h> #include <thrust/inner_product.h> #include <thrust/sequence.h> #include <bits/stdc++.h> using namespace std; int main(){ thrust::device_vector<int> d_B(5), d_A(5,15); cout<<"begin\n\n"; for(auto b:d_B) cout<<b<<' '; cout<<endl; for(auto a:d_A) cout<<a<<' '; cout<<endl; thrust::sequence(d_B.begin(), d_B.end()); cout<< thrust::inner_product(d_A.begin(), d_A.end(), d_B.begin(), 0)<<endl; }
#include <hip/hip_runtime.h> #include <thrust/host_vector.h> #include <thrust/device_vector.h> #include <thrust/inner_product.h> #include <thrust/sequence.h> #include <bits/stdc++.h> using namespace std; int main(){ thrust::device_vector<int> d_B(5), d_A(5,15); cout<<"begin\n\n"; for(auto b:d_B) cout<<b<<' '; cout<<endl; for(auto a:d_A) cout<<a<<' '; cout<<endl; thrust::sequence(d_B.begin(), d_B.end()); cout<< thrust::inner_product(d_A.begin(), d_A.end(), d_B.begin(), 0)<<endl; }
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
// #CSCS CUDA Training // // #Example 2.1 - sum vectors, fix number of threads // // #Author Ugo Varetto // // #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the // size of the output vector. // // #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the // domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1) // // #Solution: // Given the maximum number of threads to use compute number of blocks // . total number of threads = T // . number of threads per block = Tb // The number of blocks is = Tb div T; note that it doesn't matter if the integer division // gives a reminder since each GPU thread will iterate over multiple elements and ensure that // the entire domain is processed regardless of the number of threads concurrently executed // // #Code: typical flow: // 1) compute launch grid configuration // 2) allocate data on host(cpu) and device(gpu) // 3) copy data from host to device // 4) launch kernel // 5) read data back // 6) consume data (in this case print result) // 7) free memory // // #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2 // // #Execution: ./sum-vectors-2 // // #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to // cudaThreadSynchronize() is required to wait for the end of kernel execution from // a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost) // kernel execution is guaranteed to be terminated before data are copied // // #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions // are named with C++ convention and the syntax is checked by default against C++ grammar rules // // #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better // // #Note: -arch=sm_13 is the lowest architecture version that supports double precision // // #Note: the example can be extended to read configuration data and array size from the command line // and could be timed to investigate how performance is dependent on single/double precision // and thread block size //#include <cuda_runtime.h> // automatically added by nvcc #include <vector> #include <iostream> #include <iomanip> #include <sstream> #include <string> typedef float real_t; // In this case the number of GPU threads is smaller than the number of elements in the domain: // every iterates over multple elements to ensure than the entire domain is covered __global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) { // compute current thread id int xIndex = blockIdx.x * blockDim.x + threadIdx.x; // iterate over vector: grid can be smaller than vector, it is therefore // required that each thread iterate over more than one vector element while( xIndex < num_elements ) { out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ]; xIndex += gridDim.x * blockDim.x; } } //------------------------------------------------------------------------------ int main( int , char** ) { const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537 const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5; const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes const int THREADS_PER_BLOCK = 32; //number of gpu threads per block const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; // host allocated storage; use std vectors to simplify memory management // and initialization std::vector< real_t > v1 ( VECTOR_SIZE, 1.f ); //initialize all elements to 1 std::vector< real_t > v2 ( VECTOR_SIZE, 2.f ); //initialize all elements to 2 std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0 // gpu allocated storage real_t* dev_in1 = 0; //vector 1 real_t* dev_in2 = 0; //vector 2 real_t* dev_out = 0; //result value cudaMalloc( &dev_in1, SIZE ); cudaMalloc( &dev_in2, SIZE ); cudaMalloc( &dev_out, SIZE ); // copy data to GPU cudaMemcpy( dev_in1, &v1[ 0 ], SIZE, cudaMemcpyHostToDevice ); cudaMemcpy( dev_in2, &v2[ 0 ], SIZE, cudaMemcpyHostToDevice ); // execute kernel with num threads >= num elements sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE ); // read back result cudaMemcpy( &vout[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost ); // print first and last element of vector std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl; // free memory cudaFree( dev_in1 ); cudaFree( dev_in2 ); cudaFree( dev_out ); return 0; }
code for sm_80 Function : _Z11sum_vectorsPKfS0_Pfm .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */ /* 0x000fe40003f06070 */ /*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */ /* 0x000fc80000011400 */ /*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */ /* 0x000fda0003f06100 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */ /* 0x000fe200078e0002 */ /*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */ /* 0x000fc800078e0000 */ /*00b0*/ IMAD.SHL.U32 R6, R8.reuse, 0x4, RZ ; /* 0x0000000408067824 */ /* 0x041fe200078e00ff */ /*00c0*/ SHF.L.U64.HI R7, R8, 0x2, R11 ; /* 0x0000000208077819 */ /* 0x000fc8000001020b */ /*00d0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */ /* 0x000fe40007f1e0ff */ /*00f0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */ /* 0x000fc800007fe4ff */ /*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea8000c1e1900 */ /*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0130*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */ /* 0x000fe20007f1e0ff */ /*0140*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */ /* 0x000fc600078e00ff */ /*0150*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */ /* 0x000fe200007fe4ff */ /*0160*/ IMAD R8, R11, c[0x0][0x0], R0 ; /* 0x000000000b087a24 */ /* 0x000fca00078e0200 */ /*0170*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */ /* 0x000fe40003f06070 */ /*0180*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */ /* 0x000fc80000011408 */ /*0190*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */ /* 0x000fe20003f06100 */ /*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */ /* 0x000fe400078e0008 */ /*01b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */ /* 0x004fca0000000000 */ /*01c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x0001ea000c101904 */ /*01d0*/ @!P0 BRA 0xb0 ; /* 0xfffffed000008947 */ /* 0x000fea000383ffff */ /*01e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
// #CSCS CUDA Training // // #Example 2.1 - sum vectors, fix number of threads // // #Author Ugo Varetto // // #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the // size of the output vector. // // #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the // domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1) // // #Solution: // Given the maximum number of threads to use compute number of blocks // . total number of threads = T // . number of threads per block = Tb // The number of blocks is = Tb div T; note that it doesn't matter if the integer division // gives a reminder since each GPU thread will iterate over multiple elements and ensure that // the entire domain is processed regardless of the number of threads concurrently executed // // #Code: typical flow: // 1) compute launch grid configuration // 2) allocate data on host(cpu) and device(gpu) // 3) copy data from host to device // 4) launch kernel // 5) read data back // 6) consume data (in this case print result) // 7) free memory // // #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2 // // #Execution: ./sum-vectors-2 // // #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to // cudaThreadSynchronize() is required to wait for the end of kernel execution from // a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost) // kernel execution is guaranteed to be terminated before data are copied // // #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions // are named with C++ convention and the syntax is checked by default against C++ grammar rules // // #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better // // #Note: -arch=sm_13 is the lowest architecture version that supports double precision // // #Note: the example can be extended to read configuration data and array size from the command line // and could be timed to investigate how performance is dependent on single/double precision // and thread block size //#include <cuda_runtime.h> // automatically added by nvcc #include <vector> #include <iostream> #include <iomanip> #include <sstream> #include <string> typedef float real_t; // In this case the number of GPU threads is smaller than the number of elements in the domain: // every iterates over multple elements to ensure than the entire domain is covered __global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) { // compute current thread id int xIndex = blockIdx.x * blockDim.x + threadIdx.x; // iterate over vector: grid can be smaller than vector, it is therefore // required that each thread iterate over more than one vector element while( xIndex < num_elements ) { out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ]; xIndex += gridDim.x * blockDim.x; } } //------------------------------------------------------------------------------ int main( int , char** ) { const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537 const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5; const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes const int THREADS_PER_BLOCK = 32; //number of gpu threads per block const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; // host allocated storage; use std vectors to simplify memory management // and initialization std::vector< real_t > v1 ( VECTOR_SIZE, 1.f ); //initialize all elements to 1 std::vector< real_t > v2 ( VECTOR_SIZE, 2.f ); //initialize all elements to 2 std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0 // gpu allocated storage real_t* dev_in1 = 0; //vector 1 real_t* dev_in2 = 0; //vector 2 real_t* dev_out = 0; //result value cudaMalloc( &dev_in1, SIZE ); cudaMalloc( &dev_in2, SIZE ); cudaMalloc( &dev_out, SIZE ); // copy data to GPU cudaMemcpy( dev_in1, &v1[ 0 ], SIZE, cudaMemcpyHostToDevice ); cudaMemcpy( dev_in2, &v2[ 0 ], SIZE, cudaMemcpyHostToDevice ); // execute kernel with num threads >= num elements sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE ); // read back result cudaMemcpy( &vout[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost ); // print first and last element of vector std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl; // free memory cudaFree( dev_in1 ); cudaFree( dev_in2 ); cudaFree( dev_out ); return 0; }
.file "tmpxft_000619c3_00000000-6_002_1_sum-vectors.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4315: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4315: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm .type _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm, @function _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm: .LFB4337: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11sum_vectorsPKfS0_Pfm(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4337: .size _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm, .-_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm .globl _Z11sum_vectorsPKfS0_Pfm .type _Z11sum_vectorsPKfS0_Pfm, @function _Z11sum_vectorsPKfS0_Pfm: .LFB4338: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4338: .size _Z11sum_vectorsPKfS0_Pfm, .-_Z11sum_vectorsPKfS0_Pfm .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z11sum_vectorsPKfS0_Pfm" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4340: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11sum_vectorsPKfS0_Pfm(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4340: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat .align 2 .weak _ZNSt6vectorIfSaIfEED2Ev .type _ZNSt6vectorIfSaIfEED2Ev, @function _ZNSt6vectorIfSaIfEED2Ev: .LFB4664: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L16 subq $8, %rsp .cfi_def_cfa_offset 16 movq 16(%rdi), %rsi subq %rax, %rsi movq %rax, %rdi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .L16: ret .cfi_endproc .LFE4664: .size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev .weak _ZNSt6vectorIfSaIfEED1Ev .set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev .section .rodata.str1.1 .LC4: .string "result: " .LC5: .string ".." .text .globl main .type main, @function main: .LFB4312: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4312 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $144, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movl $262148, %edi .LEHB0: call _Znwm@PLT .LEHE0: movq %rax, %rbx movq %rax, 48(%rsp) leaq 262148(%rax), %rdx movq %rdx, 64(%rsp) movss .LC1(%rip), %xmm0 .L20: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L20 movq %rdx, 56(%rsp) movq $0, 88(%rsp) movq $0, 96(%rsp) movl $262148, %edi .LEHB1: call _Znwm@PLT .LEHE1: movq %rax, %rbp movq %rax, 80(%rsp) leaq 262148(%rax), %rdx movq %rdx, 96(%rsp) movss .LC2(%rip), %xmm0 .L21: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L21 movq %rdx, 88(%rsp) movq $0, 120(%rsp) movq $0, 128(%rsp) movl $262148, %edi .LEHB2: call _Znwm@PLT .LEHE2: movq %rax, %r12 movq %rax, 112(%rsp) leaq 262148(%rax), %rdx movq %rdx, 128(%rsp) .L22: movl $0x00000000, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L22 movq %rdx, 120(%rsp) movq $0, (%rsp) movq $0, 8(%rsp) movq $0, 16(%rsp) movq %rsp, %rdi movl $262148, %esi .LEHB3: call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $262148, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $262148, %esi call cudaMalloc@PLT movl $1, %ecx movl $262148, %edx movq %rbx, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $262148, %edx movq %rbp, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $32, 36(%rsp) movl $1, 40(%rsp) movl $409, 24(%rsp) movl $1, 28(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L23 movl $65537, %ecx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm .L23: movl $2, %ecx movl $262148, %edx movq 16(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd (%r12), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC5(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 262144(%r12), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT .LEHE3: leaq 112(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 80(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 48(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq 136(%rsp), %rax subq %fs:40, %rax jne .L37 movl $0, %eax addq $144, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state endbr64 movq %rax, %rbx leaq 112(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L25: leaq 80(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L26: leaq 48(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq 136(%rsp), %rax subq %fs:40, %rax je .L27 call __stack_chk_fail@PLT .L30: endbr64 movq %rax, %rbx jmp .L25 .L29: endbr64 movq %rax, %rbx jmp .L26 .L27: movq %rbx, %rdi .LEHB4: call _Unwind_Resume@PLT .LEHE4: .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE4312: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA4312: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4312-.LLSDACSB4312 .LLSDACSB4312: .uleb128 .LEHB0-.LFB4312 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB4312 .uleb128 .LEHE1-.LEHB1 .uleb128 .L29-.LFB4312 .uleb128 0 .uleb128 .LEHB2-.LFB4312 .uleb128 .LEHE2-.LEHB2 .uleb128 .L30-.LFB4312 .uleb128 0 .uleb128 .LEHB3-.LFB4312 .uleb128 .LEHE3-.LEHB3 .uleb128 .L31-.LFB4312 .uleb128 0 .uleb128 .LEHB4-.LFB4312 .uleb128 .LEHE4-.LEHB4 .uleb128 0 .uleb128 0 .LLSDACSE4312: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
// #CSCS CUDA Training // // #Example 2.1 - sum vectors, fix number of threads // // #Author Ugo Varetto // // #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the // size of the output vector. // // #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the // domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1) // // #Solution: // Given the maximum number of threads to use compute number of blocks // . total number of threads = T // . number of threads per block = Tb // The number of blocks is = Tb div T; note that it doesn't matter if the integer division // gives a reminder since each GPU thread will iterate over multiple elements and ensure that // the entire domain is processed regardless of the number of threads concurrently executed // // #Code: typical flow: // 1) compute launch grid configuration // 2) allocate data on host(cpu) and device(gpu) // 3) copy data from host to device // 4) launch kernel // 5) read data back // 6) consume data (in this case print result) // 7) free memory // // #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2 // // #Execution: ./sum-vectors-2 // // #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to // cudaThreadSynchronize() is required to wait for the end of kernel execution from // a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost) // kernel execution is guaranteed to be terminated before data are copied // // #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions // are named with C++ convention and the syntax is checked by default against C++ grammar rules // // #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better // // #Note: -arch=sm_13 is the lowest architecture version that supports double precision // // #Note: the example can be extended to read configuration data and array size from the command line // and could be timed to investigate how performance is dependent on single/double precision // and thread block size //#include <cuda_runtime.h> // automatically added by nvcc #include <vector> #include <iostream> #include <iomanip> #include <sstream> #include <string> typedef float real_t; // In this case the number of GPU threads is smaller than the number of elements in the domain: // every iterates over multple elements to ensure than the entire domain is covered __global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) { // compute current thread id int xIndex = blockIdx.x * blockDim.x + threadIdx.x; // iterate over vector: grid can be smaller than vector, it is therefore // required that each thread iterate over more than one vector element while( xIndex < num_elements ) { out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ]; xIndex += gridDim.x * blockDim.x; } } //------------------------------------------------------------------------------ int main( int , char** ) { const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537 const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5; const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes const int THREADS_PER_BLOCK = 32; //number of gpu threads per block const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; // host allocated storage; use std vectors to simplify memory management // and initialization std::vector< real_t > v1 ( VECTOR_SIZE, 1.f ); //initialize all elements to 1 std::vector< real_t > v2 ( VECTOR_SIZE, 2.f ); //initialize all elements to 2 std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0 // gpu allocated storage real_t* dev_in1 = 0; //vector 1 real_t* dev_in2 = 0; //vector 2 real_t* dev_out = 0; //result value cudaMalloc( &dev_in1, SIZE ); cudaMalloc( &dev_in2, SIZE ); cudaMalloc( &dev_out, SIZE ); // copy data to GPU cudaMemcpy( dev_in1, &v1[ 0 ], SIZE, cudaMemcpyHostToDevice ); cudaMemcpy( dev_in2, &v2[ 0 ], SIZE, cudaMemcpyHostToDevice ); // execute kernel with num threads >= num elements sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE ); // read back result cudaMemcpy( &vout[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost ); // print first and last element of vector std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl; // free memory cudaFree( dev_in1 ); cudaFree( dev_in2 ); cudaFree( dev_out ); return 0; }
// #CSCS CUDA Training // // #Example 2.1 - sum vectors, fix number of threads // // #Author Ugo Varetto // // #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the // size of the output vector. // // #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the // domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1) // // #Solution: // Given the maximum number of threads to use compute number of blocks // . total number of threads = T // . number of threads per block = Tb // The number of blocks is = Tb div T; note that it doesn't matter if the integer division // gives a reminder since each GPU thread will iterate over multiple elements and ensure that // the entire domain is processed regardless of the number of threads concurrently executed // // #Code: typical flow: // 1) compute launch grid configuration // 2) allocate data on host(cpu) and device(gpu) // 3) copy data from host to device // 4) launch kernel // 5) read data back // 6) consume data (in this case print result) // 7) free memory // // #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2 // // #Execution: ./sum-vectors-2 // // #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to // cudaThreadSynchronize() is required to wait for the end of kernel execution from // a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost) // kernel execution is guaranteed to be terminated before data are copied // // #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions // are named with C++ convention and the syntax is checked by default against C++ grammar rules // // #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better // // #Note: -arch=sm_13 is the lowest architecture version that supports double precision // // #Note: the example can be extended to read configuration data and array size from the command line // and could be timed to investigate how performance is dependent on single/double precision // and thread block size //#include <cuda_runtime.h> // automatically added by nvcc #include <hip/hip_runtime.h> #include <vector> #include <iostream> #include <iomanip> #include <sstream> #include <string> typedef float real_t; // In this case the number of GPU threads is smaller than the number of elements in the domain: // every iterates over multple elements to ensure than the entire domain is covered __global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) { // compute current thread id int xIndex = blockIdx.x * blockDim.x + threadIdx.x; // iterate over vector: grid can be smaller than vector, it is therefore // required that each thread iterate over more than one vector element while( xIndex < num_elements ) { out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ]; xIndex += gridDim.x * blockDim.x; } } //------------------------------------------------------------------------------ int main( int , char** ) { const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537 const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5; const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes const int THREADS_PER_BLOCK = 32; //number of gpu threads per block const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; // host allocated storage; use std vectors to simplify memory management // and initialization std::vector< real_t > v1 ( VECTOR_SIZE, 1.f ); //initialize all elements to 1 std::vector< real_t > v2 ( VECTOR_SIZE, 2.f ); //initialize all elements to 2 std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0 // gpu allocated storage real_t* dev_in1 = 0; //vector 1 real_t* dev_in2 = 0; //vector 2 real_t* dev_out = 0; //result value hipMalloc( &dev_in1, SIZE ); hipMalloc( &dev_in2, SIZE ); hipMalloc( &dev_out, SIZE ); // copy data to GPU hipMemcpy( dev_in1, &v1[ 0 ], SIZE, hipMemcpyHostToDevice ); hipMemcpy( dev_in2, &v2[ 0 ], SIZE, hipMemcpyHostToDevice ); // execute kernel with num threads >= num elements sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE ); // read back result hipMemcpy( &vout[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost ); // print first and last element of vector std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl; // free memory hipFree( dev_in1 ); hipFree( dev_in2 ); hipFree( dev_out ); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
// #CSCS CUDA Training // // #Example 2.1 - sum vectors, fix number of threads // // #Author Ugo Varetto // // #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the // size of the output vector. // // #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the // domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1) // // #Solution: // Given the maximum number of threads to use compute number of blocks // . total number of threads = T // . number of threads per block = Tb // The number of blocks is = Tb div T; note that it doesn't matter if the integer division // gives a reminder since each GPU thread will iterate over multiple elements and ensure that // the entire domain is processed regardless of the number of threads concurrently executed // // #Code: typical flow: // 1) compute launch grid configuration // 2) allocate data on host(cpu) and device(gpu) // 3) copy data from host to device // 4) launch kernel // 5) read data back // 6) consume data (in this case print result) // 7) free memory // // #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2 // // #Execution: ./sum-vectors-2 // // #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to // cudaThreadSynchronize() is required to wait for the end of kernel execution from // a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost) // kernel execution is guaranteed to be terminated before data are copied // // #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions // are named with C++ convention and the syntax is checked by default against C++ grammar rules // // #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better // // #Note: -arch=sm_13 is the lowest architecture version that supports double precision // // #Note: the example can be extended to read configuration data and array size from the command line // and could be timed to investigate how performance is dependent on single/double precision // and thread block size //#include <cuda_runtime.h> // automatically added by nvcc #include <hip/hip_runtime.h> #include <vector> #include <iostream> #include <iomanip> #include <sstream> #include <string> typedef float real_t; // In this case the number of GPU threads is smaller than the number of elements in the domain: // every iterates over multple elements to ensure than the entire domain is covered __global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) { // compute current thread id int xIndex = blockIdx.x * blockDim.x + threadIdx.x; // iterate over vector: grid can be smaller than vector, it is therefore // required that each thread iterate over more than one vector element while( xIndex < num_elements ) { out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ]; xIndex += gridDim.x * blockDim.x; } } //------------------------------------------------------------------------------ int main( int , char** ) { const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537 const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5; const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes const int THREADS_PER_BLOCK = 32; //number of gpu threads per block const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; // host allocated storage; use std vectors to simplify memory management // and initialization std::vector< real_t > v1 ( VECTOR_SIZE, 1.f ); //initialize all elements to 1 std::vector< real_t > v2 ( VECTOR_SIZE, 2.f ); //initialize all elements to 2 std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0 // gpu allocated storage real_t* dev_in1 = 0; //vector 1 real_t* dev_in2 = 0; //vector 2 real_t* dev_out = 0; //result value hipMalloc( &dev_in1, SIZE ); hipMalloc( &dev_in2, SIZE ); hipMalloc( &dev_out, SIZE ); // copy data to GPU hipMemcpy( dev_in1, &v1[ 0 ], SIZE, hipMemcpyHostToDevice ); hipMemcpy( dev_in2, &v2[ 0 ], SIZE, hipMemcpyHostToDevice ); // execute kernel with num threads >= num elements sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE ); // read back result hipMemcpy( &vout[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost ); // print first and last element of vector std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl; // free memory hipFree( dev_in1 ); hipFree( dev_in2 ); hipFree( dev_out ); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11sum_vectorsPKfS0_Pfm .globl _Z11sum_vectorsPKfS0_Pfm .p2align 8 .type _Z11sum_vectorsPKfS0_Pfm,@function _Z11sum_vectorsPKfS0_Pfm: s_clause 0x1 s_load_b32 s6, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_add_u32 s4, s0, 32 s_addc_u32 s5, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s10, s6, 0xffff s_mov_b32 s6, exec_lo v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_cmpx_gt_u64_e64 s[2:3], v[1:2] s_cbranch_execz .LBB0_3 s_load_b32 s11, s[4:5], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_add_i32 s15, s15, s11 s_mul_i32 s1, s11, s10 v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1] s_mov_b32 s10, 0 .p2align 6 .LBB0_2: v_lshlrev_b64 v[5:6], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v4, 31, v3 v_add_co_u32 v0, vcc_lo, s4, v5 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v6, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4] global_load_b32 v0, v[0:1], off global_load_b32 v7, v[7:8], off v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4 v_add_co_u32 v4, s0, s8, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, s9, v6, s0 v_add_nc_u32_e32 v3, s1, v3 s_or_b32 s10, vcc_lo, s10 s_waitcnt vmcnt(0) v_add_f32_e32 v0, v0, v7 global_store_b32 v[4:5], v0, off s_and_not1_b32 exec_lo, exec_lo, s10 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11sum_vectorsPKfS0_Pfm .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11sum_vectorsPKfS0_Pfm, .Lfunc_end0-_Z11sum_vectorsPKfS0_Pfm .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11sum_vectorsPKfS0_Pfm .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11sum_vectorsPKfS0_Pfm.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
// #CSCS CUDA Training // // #Example 2.1 - sum vectors, fix number of threads // // #Author Ugo Varetto // // #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the // size of the output vector. // // #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the // domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1) // // #Solution: // Given the maximum number of threads to use compute number of blocks // . total number of threads = T // . number of threads per block = Tb // The number of blocks is = Tb div T; note that it doesn't matter if the integer division // gives a reminder since each GPU thread will iterate over multiple elements and ensure that // the entire domain is processed regardless of the number of threads concurrently executed // // #Code: typical flow: // 1) compute launch grid configuration // 2) allocate data on host(cpu) and device(gpu) // 3) copy data from host to device // 4) launch kernel // 5) read data back // 6) consume data (in this case print result) // 7) free memory // // #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2 // // #Execution: ./sum-vectors-2 // // #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to // cudaThreadSynchronize() is required to wait for the end of kernel execution from // a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost) // kernel execution is guaranteed to be terminated before data are copied // // #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions // are named with C++ convention and the syntax is checked by default against C++ grammar rules // // #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better // // #Note: -arch=sm_13 is the lowest architecture version that supports double precision // // #Note: the example can be extended to read configuration data and array size from the command line // and could be timed to investigate how performance is dependent on single/double precision // and thread block size //#include <cuda_runtime.h> // automatically added by nvcc #include <hip/hip_runtime.h> #include <vector> #include <iostream> #include <iomanip> #include <sstream> #include <string> typedef float real_t; // In this case the number of GPU threads is smaller than the number of elements in the domain: // every iterates over multple elements to ensure than the entire domain is covered __global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) { // compute current thread id int xIndex = blockIdx.x * blockDim.x + threadIdx.x; // iterate over vector: grid can be smaller than vector, it is therefore // required that each thread iterate over more than one vector element while( xIndex < num_elements ) { out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ]; xIndex += gridDim.x * blockDim.x; } } //------------------------------------------------------------------------------ int main( int , char** ) { const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537 const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5; const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes const int THREADS_PER_BLOCK = 32; //number of gpu threads per block const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; // host allocated storage; use std vectors to simplify memory management // and initialization std::vector< real_t > v1 ( VECTOR_SIZE, 1.f ); //initialize all elements to 1 std::vector< real_t > v2 ( VECTOR_SIZE, 2.f ); //initialize all elements to 2 std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0 // gpu allocated storage real_t* dev_in1 = 0; //vector 1 real_t* dev_in2 = 0; //vector 2 real_t* dev_out = 0; //result value hipMalloc( &dev_in1, SIZE ); hipMalloc( &dev_in2, SIZE ); hipMalloc( &dev_out, SIZE ); // copy data to GPU hipMemcpy( dev_in1, &v1[ 0 ], SIZE, hipMemcpyHostToDevice ); hipMemcpy( dev_in2, &v2[ 0 ], SIZE, hipMemcpyHostToDevice ); // execute kernel with num threads >= num elements sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE ); // read back result hipMemcpy( &vout[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost ); // print first and last element of vector std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl; // free memory hipFree( dev_in1 ); hipFree( dev_in2 ); hipFree( dev_out ); return 0; }
.text .file "002_1_sum-vectors.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__sum_vectorsPKfS0_Pfm # -- Begin function _Z26__device_stub__sum_vectorsPKfS0_Pfm .p2align 4, 0x90 .type _Z26__device_stub__sum_vectorsPKfS0_Pfm,@function _Z26__device_stub__sum_vectorsPKfS0_Pfm: # @_Z26__device_stub__sum_vectorsPKfS0_Pfm .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11sum_vectorsPKfS0_Pfm, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z26__device_stub__sum_vectorsPKfS0_Pfm, .Lfunc_end0-_Z26__device_stub__sum_vectorsPKfS0_Pfm .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: # %.noexc pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 .cfi_escape 0x2e, 0x00 movl $262148, %edi # imm = 0x40004 callq _Znwm movq %rax, %rbx xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax) # imm = 0x3F800000 addq $4, %rax cmpq $262148, %rax # imm = 0x40004 jne .LBB1_1 # %bb.2: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit .Ltmp0: .cfi_escape 0x2e, 0x00 movl $262148, %edi # imm = 0x40004 callq _Znwm .Ltmp1: # %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i10.preheader movq %rax, %r14 xorl %eax, %eax .p2align 4, 0x90 .LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i10 # =>This Inner Loop Header: Depth=1 movl $1073741824, (%r14,%rax) # imm = 0x40000000 addq $4, %rax cmpq $262148, %rax # imm = 0x40004 jne .LBB1_4 # %bb.5: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit14 .Ltmp3: .cfi_escape 0x2e, 0x00 movl $262148, %edi # imm = 0x40004 callq _Znwm .Ltmp4: # %bb.6: # %.lr.ph.i.i.i.i.i.i.i.i.i15.preheader movq %rax, %r15 .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %rax, %rdi xorl %esi, %esi callq memset@PLT movq $0, 24(%rsp) movq $0, 16(%rsp) movq $0, 8(%rsp) .Ltmp6: .cfi_escape 0x2e, 0x00 leaq 24(%rsp), %rdi movl $262148, %esi # imm = 0x40004 callq hipMalloc .Ltmp7: # %bb.7: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit .Ltmp8: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi movl $262148, %esi # imm = 0x40004 callq hipMalloc .Ltmp9: # %bb.8: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit22 .Ltmp10: .cfi_escape 0x2e, 0x00 leaq 8(%rsp), %rdi movl $262148, %esi # imm = 0x40004 callq hipMalloc .Ltmp11: # %bb.9: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit24 movq 24(%rsp), %rdi .Ltmp12: .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy .Ltmp13: # %bb.10: movq 16(%rsp), %rdi .Ltmp14: .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %r14, %rsi movl $1, %ecx callq hipMemcpy .Ltmp15: # %bb.11: .Ltmp16: .cfi_escape 0x2e, 0x00 movabsq $4294967705, %rdi # imm = 0x100000199 movabsq $4294967328, %rdx # imm = 0x100000020 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp17: # %bb.12: testl %eax, %eax jne .LBB1_15 # %bb.13: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movq $65537, 80(%rsp) # imm = 0x10001 leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) .Ltmp18: .cfi_escape 0x2e, 0x00 leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp19: # %bb.14: # %.noexc25 movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d .Ltmp20: .cfi_escape 0x2e, 0x10 leaq 112(%rsp), %r9 movl $_Z11sum_vectorsPKfS0_Pfm, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp21: .LBB1_15: movq 8(%rsp), %rsi .Ltmp22: .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %r15, %rdi movl $2, %ecx callq hipMemcpy .Ltmp23: # %bb.16: .Ltmp24: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str, %esi movl $8, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp25: # %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp26: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp27: # %bb.18: # %_ZNSolsEf.exit .Ltmp28: movq %rax, %r12 .cfi_escape 0x2e, 0x00 movl $.L.str.1, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp29: # %bb.19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30 movss 262144(%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp30: .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp31: # %bb.20: # %_ZNSolsEf.exit32 movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %r13 testq %r13, %r13 je .LBB1_21 # %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r13) je .LBB1_27 # %bb.26: movzbl 67(%r13), %eax jmp .LBB1_29 .LBB1_27: .Ltmp32: .cfi_escape 0x2e, 0x00 movq %r13, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp33: # %bb.28: # %.noexc46 movq (%r13), %rax .Ltmp34: .cfi_escape 0x2e, 0x00 movq %r13, %rdi movl $10, %esi callq *48(%rax) .Ltmp35: .LBB1_29: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i .Ltmp36: .cfi_escape 0x2e, 0x00 movsbl %al, %esi movq %r12, %rdi callq _ZNSo3putEc .Ltmp37: # %bb.30: # %.noexc48 .Ltmp38: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .Ltmp39: # %bb.31: # %_ZNSolsEPFRSoS_E.exit movq 24(%rsp), %rdi .Ltmp40: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp41: # %bb.32: movq 16(%rsp), %rdi .Ltmp42: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp43: # %bb.33: movq 8(%rsp), %rdi .Ltmp44: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp45: # %bb.34: # %_ZNSt6vectorIfSaIfEED2Ev.exit35 .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_21: .cfi_def_cfa_offset 192 .Ltmp46: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .Ltmp47: # %bb.24: # %.noexc45 .LBB1_35: .Ltmp5: movq %rax, %r12 jmp .LBB1_36 .LBB1_22: .Ltmp2: movq %rax, %r12 jmp .LBB1_37 .LBB1_23: # %_ZNSt6vectorIfSaIfEED2Ev.exit .Ltmp48: movq %rax, %r12 .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .LBB1_36: # %_ZNSt6vectorIfSaIfEED2Ev.exit41 .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .LBB1_37: # %_ZNSt6vectorIfSaIfEED2Ev.exit43 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _Unwind_Resume@PLT .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table1: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5 .byte 0 # On action: cleanup .uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp47-.Ltmp6 # Call between .Ltmp6 and .Ltmp47 .uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48 .byte 0 # On action: cleanup .uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Lfunc_end1-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end1 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11sum_vectorsPKfS0_Pfm, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11sum_vectorsPKfS0_Pfm,@object # @_Z11sum_vectorsPKfS0_Pfm .section .rodata,"a",@progbits .globl _Z11sum_vectorsPKfS0_Pfm .p2align 3, 0x0 _Z11sum_vectorsPKfS0_Pfm: .quad _Z26__device_stub__sum_vectorsPKfS0_Pfm .size _Z11sum_vectorsPKfS0_Pfm, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "result: " .size .L.str, 9 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz ".." .size .L.str.1, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11sum_vectorsPKfS0_Pfm" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__sum_vectorsPKfS0_Pfm .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z11sum_vectorsPKfS0_Pfm .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z11sum_vectorsPKfS0_Pfm .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */ /* 0x000fe40003f06070 */ /*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */ /* 0x000fc80000011400 */ /*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */ /* 0x000fda0003f06100 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */ /* 0x000fe200078e0002 */ /*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */ /* 0x000fc800078e0000 */ /*00b0*/ IMAD.SHL.U32 R6, R8.reuse, 0x4, RZ ; /* 0x0000000408067824 */ /* 0x041fe200078e00ff */ /*00c0*/ SHF.L.U64.HI R7, R8, 0x2, R11 ; /* 0x0000000208077819 */ /* 0x000fc8000001020b */ /*00d0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */ /* 0x000fe40007f1e0ff */ /*00f0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */ /* 0x000fc800007fe4ff */ /*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea8000c1e1900 */ /*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0130*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */ /* 0x000fe20007f1e0ff */ /*0140*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */ /* 0x000fc600078e00ff */ /*0150*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */ /* 0x000fe200007fe4ff */ /*0160*/ IMAD R8, R11, c[0x0][0x0], R0 ; /* 0x000000000b087a24 */ /* 0x000fca00078e0200 */ /*0170*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */ /* 0x000fe40003f06070 */ /*0180*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */ /* 0x000fc80000011408 */ /*0190*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */ /* 0x000fe20003f06100 */ /*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */ /* 0x000fe400078e0008 */ /*01b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */ /* 0x004fca0000000000 */ /*01c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x0001ea000c101904 */ /*01d0*/ @!P0 BRA 0xb0 ; /* 0xfffffed000008947 */ /* 0x000fea000383ffff */ /*01e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11sum_vectorsPKfS0_Pfm .globl _Z11sum_vectorsPKfS0_Pfm .p2align 8 .type _Z11sum_vectorsPKfS0_Pfm,@function _Z11sum_vectorsPKfS0_Pfm: s_clause 0x1 s_load_b32 s6, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_add_u32 s4, s0, 32 s_addc_u32 s5, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s10, s6, 0xffff s_mov_b32 s6, exec_lo v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_cmpx_gt_u64_e64 s[2:3], v[1:2] s_cbranch_execz .LBB0_3 s_load_b32 s11, s[4:5], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_add_i32 s15, s15, s11 s_mul_i32 s1, s11, s10 v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1] s_mov_b32 s10, 0 .p2align 6 .LBB0_2: v_lshlrev_b64 v[5:6], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v4, 31, v3 v_add_co_u32 v0, vcc_lo, s4, v5 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v6, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4] global_load_b32 v0, v[0:1], off global_load_b32 v7, v[7:8], off v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4 v_add_co_u32 v4, s0, s8, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, s9, v6, s0 v_add_nc_u32_e32 v3, s1, v3 s_or_b32 s10, vcc_lo, s10 s_waitcnt vmcnt(0) v_add_f32_e32 v0, v0, v7 global_store_b32 v[4:5], v0, off s_and_not1_b32 exec_lo, exec_lo, s10 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11sum_vectorsPKfS0_Pfm .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11sum_vectorsPKfS0_Pfm, .Lfunc_end0-_Z11sum_vectorsPKfS0_Pfm .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11sum_vectorsPKfS0_Pfm .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11sum_vectorsPKfS0_Pfm.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000619c3_00000000-6_002_1_sum-vectors.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4315: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4315: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm .type _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm, @function _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm: .LFB4337: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11sum_vectorsPKfS0_Pfm(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4337: .size _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm, .-_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm .globl _Z11sum_vectorsPKfS0_Pfm .type _Z11sum_vectorsPKfS0_Pfm, @function _Z11sum_vectorsPKfS0_Pfm: .LFB4338: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4338: .size _Z11sum_vectorsPKfS0_Pfm, .-_Z11sum_vectorsPKfS0_Pfm .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z11sum_vectorsPKfS0_Pfm" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4340: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11sum_vectorsPKfS0_Pfm(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4340: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat .align 2 .weak _ZNSt6vectorIfSaIfEED2Ev .type _ZNSt6vectorIfSaIfEED2Ev, @function _ZNSt6vectorIfSaIfEED2Ev: .LFB4664: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L16 subq $8, %rsp .cfi_def_cfa_offset 16 movq 16(%rdi), %rsi subq %rax, %rsi movq %rax, %rdi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .L16: ret .cfi_endproc .LFE4664: .size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev .weak _ZNSt6vectorIfSaIfEED1Ev .set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev .section .rodata.str1.1 .LC4: .string "result: " .LC5: .string ".." .text .globl main .type main, @function main: .LFB4312: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4312 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $144, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movl $262148, %edi .LEHB0: call _Znwm@PLT .LEHE0: movq %rax, %rbx movq %rax, 48(%rsp) leaq 262148(%rax), %rdx movq %rdx, 64(%rsp) movss .LC1(%rip), %xmm0 .L20: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L20 movq %rdx, 56(%rsp) movq $0, 88(%rsp) movq $0, 96(%rsp) movl $262148, %edi .LEHB1: call _Znwm@PLT .LEHE1: movq %rax, %rbp movq %rax, 80(%rsp) leaq 262148(%rax), %rdx movq %rdx, 96(%rsp) movss .LC2(%rip), %xmm0 .L21: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L21 movq %rdx, 88(%rsp) movq $0, 120(%rsp) movq $0, 128(%rsp) movl $262148, %edi .LEHB2: call _Znwm@PLT .LEHE2: movq %rax, %r12 movq %rax, 112(%rsp) leaq 262148(%rax), %rdx movq %rdx, 128(%rsp) .L22: movl $0x00000000, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L22 movq %rdx, 120(%rsp) movq $0, (%rsp) movq $0, 8(%rsp) movq $0, 16(%rsp) movq %rsp, %rdi movl $262148, %esi .LEHB3: call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $262148, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $262148, %esi call cudaMalloc@PLT movl $1, %ecx movl $262148, %edx movq %rbx, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $262148, %edx movq %rbp, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $32, 36(%rsp) movl $1, 40(%rsp) movl $409, 24(%rsp) movl $1, 28(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L23 movl $65537, %ecx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm .L23: movl $2, %ecx movl $262148, %edx movq 16(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd (%r12), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC5(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 262144(%r12), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT .LEHE3: leaq 112(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 80(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 48(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq 136(%rsp), %rax subq %fs:40, %rax jne .L37 movl $0, %eax addq $144, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state endbr64 movq %rax, %rbx leaq 112(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L25: leaq 80(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L26: leaq 48(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq 136(%rsp), %rax subq %fs:40, %rax je .L27 call __stack_chk_fail@PLT .L30: endbr64 movq %rax, %rbx jmp .L25 .L29: endbr64 movq %rax, %rbx jmp .L26 .L27: movq %rbx, %rdi .LEHB4: call _Unwind_Resume@PLT .LEHE4: .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE4312: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA4312: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4312-.LLSDACSB4312 .LLSDACSB4312: .uleb128 .LEHB0-.LFB4312 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB4312 .uleb128 .LEHE1-.LEHB1 .uleb128 .L29-.LFB4312 .uleb128 0 .uleb128 .LEHB2-.LFB4312 .uleb128 .LEHE2-.LEHB2 .uleb128 .L30-.LFB4312 .uleb128 0 .uleb128 .LEHB3-.LFB4312 .uleb128 .LEHE3-.LEHB3 .uleb128 .L31-.LFB4312 .uleb128 0 .uleb128 .LEHB4-.LFB4312 .uleb128 .LEHE4-.LEHB4 .uleb128 0 .uleb128 0 .LLSDACSE4312: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "002_1_sum-vectors.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__sum_vectorsPKfS0_Pfm # -- Begin function _Z26__device_stub__sum_vectorsPKfS0_Pfm .p2align 4, 0x90 .type _Z26__device_stub__sum_vectorsPKfS0_Pfm,@function _Z26__device_stub__sum_vectorsPKfS0_Pfm: # @_Z26__device_stub__sum_vectorsPKfS0_Pfm .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11sum_vectorsPKfS0_Pfm, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z26__device_stub__sum_vectorsPKfS0_Pfm, .Lfunc_end0-_Z26__device_stub__sum_vectorsPKfS0_Pfm .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: # %.noexc pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 .cfi_escape 0x2e, 0x00 movl $262148, %edi # imm = 0x40004 callq _Znwm movq %rax, %rbx xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax) # imm = 0x3F800000 addq $4, %rax cmpq $262148, %rax # imm = 0x40004 jne .LBB1_1 # %bb.2: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit .Ltmp0: .cfi_escape 0x2e, 0x00 movl $262148, %edi # imm = 0x40004 callq _Znwm .Ltmp1: # %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i10.preheader movq %rax, %r14 xorl %eax, %eax .p2align 4, 0x90 .LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i10 # =>This Inner Loop Header: Depth=1 movl $1073741824, (%r14,%rax) # imm = 0x40000000 addq $4, %rax cmpq $262148, %rax # imm = 0x40004 jne .LBB1_4 # %bb.5: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit14 .Ltmp3: .cfi_escape 0x2e, 0x00 movl $262148, %edi # imm = 0x40004 callq _Znwm .Ltmp4: # %bb.6: # %.lr.ph.i.i.i.i.i.i.i.i.i15.preheader movq %rax, %r15 .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %rax, %rdi xorl %esi, %esi callq memset@PLT movq $0, 24(%rsp) movq $0, 16(%rsp) movq $0, 8(%rsp) .Ltmp6: .cfi_escape 0x2e, 0x00 leaq 24(%rsp), %rdi movl $262148, %esi # imm = 0x40004 callq hipMalloc .Ltmp7: # %bb.7: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit .Ltmp8: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi movl $262148, %esi # imm = 0x40004 callq hipMalloc .Ltmp9: # %bb.8: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit22 .Ltmp10: .cfi_escape 0x2e, 0x00 leaq 8(%rsp), %rdi movl $262148, %esi # imm = 0x40004 callq hipMalloc .Ltmp11: # %bb.9: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit24 movq 24(%rsp), %rdi .Ltmp12: .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy .Ltmp13: # %bb.10: movq 16(%rsp), %rdi .Ltmp14: .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %r14, %rsi movl $1, %ecx callq hipMemcpy .Ltmp15: # %bb.11: .Ltmp16: .cfi_escape 0x2e, 0x00 movabsq $4294967705, %rdi # imm = 0x100000199 movabsq $4294967328, %rdx # imm = 0x100000020 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp17: # %bb.12: testl %eax, %eax jne .LBB1_15 # %bb.13: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movq $65537, 80(%rsp) # imm = 0x10001 leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) .Ltmp18: .cfi_escape 0x2e, 0x00 leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp19: # %bb.14: # %.noexc25 movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d .Ltmp20: .cfi_escape 0x2e, 0x10 leaq 112(%rsp), %r9 movl $_Z11sum_vectorsPKfS0_Pfm, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp21: .LBB1_15: movq 8(%rsp), %rsi .Ltmp22: .cfi_escape 0x2e, 0x00 movl $262148, %edx # imm = 0x40004 movq %r15, %rdi movl $2, %ecx callq hipMemcpy .Ltmp23: # %bb.16: .Ltmp24: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str, %esi movl $8, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp25: # %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp26: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp27: # %bb.18: # %_ZNSolsEf.exit .Ltmp28: movq %rax, %r12 .cfi_escape 0x2e, 0x00 movl $.L.str.1, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp29: # %bb.19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30 movss 262144(%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp30: .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp31: # %bb.20: # %_ZNSolsEf.exit32 movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %r13 testq %r13, %r13 je .LBB1_21 # %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r13) je .LBB1_27 # %bb.26: movzbl 67(%r13), %eax jmp .LBB1_29 .LBB1_27: .Ltmp32: .cfi_escape 0x2e, 0x00 movq %r13, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp33: # %bb.28: # %.noexc46 movq (%r13), %rax .Ltmp34: .cfi_escape 0x2e, 0x00 movq %r13, %rdi movl $10, %esi callq *48(%rax) .Ltmp35: .LBB1_29: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i .Ltmp36: .cfi_escape 0x2e, 0x00 movsbl %al, %esi movq %r12, %rdi callq _ZNSo3putEc .Ltmp37: # %bb.30: # %.noexc48 .Ltmp38: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .Ltmp39: # %bb.31: # %_ZNSolsEPFRSoS_E.exit movq 24(%rsp), %rdi .Ltmp40: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp41: # %bb.32: movq 16(%rsp), %rdi .Ltmp42: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp43: # %bb.33: movq 8(%rsp), %rdi .Ltmp44: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp45: # %bb.34: # %_ZNSt6vectorIfSaIfEED2Ev.exit35 .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_21: .cfi_def_cfa_offset 192 .Ltmp46: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .Ltmp47: # %bb.24: # %.noexc45 .LBB1_35: .Ltmp5: movq %rax, %r12 jmp .LBB1_36 .LBB1_22: .Ltmp2: movq %rax, %r12 jmp .LBB1_37 .LBB1_23: # %_ZNSt6vectorIfSaIfEED2Ev.exit .Ltmp48: movq %rax, %r12 .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .LBB1_36: # %_ZNSt6vectorIfSaIfEED2Ev.exit41 .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .LBB1_37: # %_ZNSt6vectorIfSaIfEED2Ev.exit43 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _Unwind_Resume@PLT .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table1: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5 .byte 0 # On action: cleanup .uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp47-.Ltmp6 # Call between .Ltmp6 and .Ltmp47 .uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48 .byte 0 # On action: cleanup .uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Lfunc_end1-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end1 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11sum_vectorsPKfS0_Pfm, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11sum_vectorsPKfS0_Pfm,@object # @_Z11sum_vectorsPKfS0_Pfm .section .rodata,"a",@progbits .globl _Z11sum_vectorsPKfS0_Pfm .p2align 3, 0x0 _Z11sum_vectorsPKfS0_Pfm: .quad _Z26__device_stub__sum_vectorsPKfS0_Pfm .size _Z11sum_vectorsPKfS0_Pfm, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "result: " .size .L.str, 9 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz ".." .size .L.str.1, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11sum_vectorsPKfS0_Pfm" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__sum_vectorsPKfS0_Pfm .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z11sum_vectorsPKfS0_Pfm .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
__global__ void matrix(float *A, int numElements, int n) { int i = blockDim.x * blockIdx.x + threadIdx.x; int j = blockDim.y * blockIdx.y + threadIdx.y; float a; if (i < n && j< n && i!= (n-1) && i%2==0) { a = A[j*n + i]; A[j*n + i] = A[j*n + i + 1]; A[j*n + i +1] = a; } if (i<n&& j<n && i<j){ A[i*n+j] = A[j*n + i]; } }
code for sm_80 Function : _Z6matrixPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */ /* 0x000e220000002600 */ /*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */ /* 0x000fe20000000800 */ /*0030*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */ /* 0x000fe200000001ff */ /*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e220000002200 */ /*0060*/ BSSY B0, 0x1a0 ; /* 0x0000013000007945 */ /* 0x000fe60003800000 */ /*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e680000002500 */ /*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e620000002100 */ /*0090*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */ /* 0x001fca00078e0202 */ /*00a0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */ /* 0x000fe20003f06270 */ /*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x002fca00078e0203 */ /*00c0*/ ISETP.LT.AND P0, PT, R0.reuse, c[0x0][0x16c], !P0 ; /* 0x00005b0000007a0c */ /* 0x040fe40004701270 */ /*00d0*/ LOP3.LUT R2, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */ /* 0x040fe400078ec0ff */ /*00e0*/ ISETP.EQ.OR P1, PT, R0.reuse, UR4, !P0 ; /* 0x0000000400007c0c */ /* 0x040fe2000c722670 */ /*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0100*/ ISETP.GE.OR P0, PT, R0, R5, !P0 ; /* 0x000000050000720c */ /* 0x000fe40004706670 */ /*0110*/ ISETP.EQ.U32.OR P1, PT, R2, 0x1, P1 ; /* 0x000000010200780c */ /* 0x000fe20000f22470 */ /*0120*/ IMAD R2, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005027a24 */ /* 0x000fc800078e0200 */ /*0130*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fd000078e0204 */ /*0140*/ @P1 BRA 0x190 ; /* 0x0000004000001947 */ /* 0x000fea0003800000 */ /*0150*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */ /* 0x000ea8000c1e1900 */ /*0160*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */ /* 0x000ee8000c1e1900 */ /*0170*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x0041e8000c101904 */ /*0180*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */ /* 0x0081e4000c101904 */ /*0190*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01a0*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x001ea2000c1e1900 */ /*01c0*/ IMAD R5, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000057a24 */ /* 0x000fc800078e0205 */ /*01d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */ /* 0x000fca00078e0204 */ /*01e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */ /* 0x004fe2000c101904 */ /*01f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0200*/ BRA 0x200; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0280*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0290*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
__global__ void matrix(float *A, int numElements, int n) { int i = blockDim.x * blockIdx.x + threadIdx.x; int j = blockDim.y * blockIdx.y + threadIdx.y; float a; if (i < n && j< n && i!= (n-1) && i%2==0) { a = A[j*n + i]; A[j*n + i] = A[j*n + i + 1]; A[j*n + i +1] = a; } if (i<n&& j<n && i<j){ A[i*n+j] = A[j*n + i]; } }
.file "tmpxft_000d7537_00000000-6_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z6matrixPfiiPfii .type _Z27__device_stub__Z6matrixPfiiPfii, @function _Z27__device_stub__Z6matrixPfiiPfii: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6matrixPfii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z27__device_stub__Z6matrixPfiiPfii, .-_Z27__device_stub__Z6matrixPfiiPfii .globl _Z6matrixPfii .type _Z6matrixPfii, @function _Z6matrixPfii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6matrixPfiiPfii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z6matrixPfii, .-_Z6matrixPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6matrixPfii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6matrixPfii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
__global__ void matrix(float *A, int numElements, int n) { int i = blockDim.x * blockIdx.x + threadIdx.x; int j = blockDim.y * blockIdx.y + threadIdx.y; float a; if (i < n && j< n && i!= (n-1) && i%2==0) { a = A[j*n + i]; A[j*n + i] = A[j*n + i + 1]; A[j*n + i +1] = a; } if (i<n&& j<n && i<j){ A[i*n+j] = A[j*n + i]; } }
#include <hip/hip_runtime.h> __global__ void matrix(float *A, int numElements, int n) { int i = blockDim.x * blockIdx.x + threadIdx.x; int j = blockDim.y * blockIdx.y + threadIdx.y; float a; if (i < n && j< n && i!= (n-1) && i%2==0) { a = A[j*n + i]; A[j*n + i] = A[j*n + i + 1]; A[j*n + i +1] = a; } if (i<n&& j<n && i<j){ A[i*n+j] = A[j*n + i]; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> __global__ void matrix(float *A, int numElements, int n) { int i = blockDim.x * blockIdx.x + threadIdx.x; int j = blockDim.y * blockIdx.y + threadIdx.y; float a; if (i < n && j< n && i!= (n-1) && i%2==0) { a = A[j*n + i]; A[j*n + i] = A[j*n + i + 1]; A[j*n + i +1] = a; } if (i<n&& j<n && i<j){ A[i*n+j] = A[j*n + i]; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6matrixPfii .globl _Z6matrixPfii .p2align 8 .type _Z6matrixPfii,@function _Z6matrixPfii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s4, s[0:1], 0xc v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4] s_load_b64 s[2:3], s[0:1], 0x0 s_add_i32 s0, s4, -1 v_and_b32_e32 v3, 1, v0 v_cmp_ne_u32_e64 s0, s0, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_i32_e32 v2, v0, v1 v_cmp_eq_u32_e64 s1, 0, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_i32_e32 vcc_lo, s4, v2 s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) s_and_b32 s0, s1, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_2 v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v2, s0, s2, v2 v_add_co_ci_u32_e64 v3, s0, s3, v3, s0 global_load_b64 v[4:5], v[2:3], off s_waitcnt vmcnt(0) v_mov_b32_e32 v6, v4 global_store_b64 v[2:3], v[5:6], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s1 v_cmp_lt_i32_e64 s0, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s0, vcc_lo s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_4 v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v4, v[2:3], off v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[0:1], v4, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6matrixPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6matrixPfii, .Lfunc_end0-_Z6matrixPfii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6matrixPfii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6matrixPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata