system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void glcm_calculation_45(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=1;i<nx;i++){
if(blockIdx.x==i && idx <((i+1)*nx)-1){
k=max*A[idx]+A[idx-(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | .text
.file "glcm_calculation_45.hip"
.globl _Z34__device_stub__glcm_calculation_45PiS_iii # -- Begin function _Z34__device_stub__glcm_calculation_45PiS_iii
.p2align 4, 0x90
.type _Z34__device_stub__glcm_calculation_45PiS_iii,@function
_Z34__device_stub__glcm_calculation_45PiS_iii: # @_Z34__device_stub__glcm_calculation_45PiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19glcm_calculation_45PiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__glcm_calculation_45PiS_iii, .Lfunc_end0-_Z34__device_stub__glcm_calculation_45PiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19glcm_calculation_45PiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19glcm_calculation_45PiS_iii,@object # @_Z19glcm_calculation_45PiS_iii
.section .rodata,"a",@progbits
.globl _Z19glcm_calculation_45PiS_iii
.p2align 3, 0x0
_Z19glcm_calculation_45PiS_iii:
.quad _Z34__device_stub__glcm_calculation_45PiS_iii
.size _Z19glcm_calculation_45PiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19glcm_calculation_45PiS_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__glcm_calculation_45PiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19glcm_calculation_45PiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19glcm_calculation_45PiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e240000002200 */
/*0040*/ ISETP.GE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe40003f06270 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe400078e0202 */
/*0080*/ IMAD R6, R0, c[0x0][0x0], R5 ; /* 0x0000000000067a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R6, R3, c[0x0][0x170], R6 ; /* 0x00005c0003067a24 */
/* 0x000fe200078e0206 */
/*00a0*/ @!P0 BRA 0x720 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R10.reuse, -0x2, RZ ; /* 0xfffffffe0a027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R4, R6, -c[0x0][0x170], R3 ; /* 0x80005c0006047a10 */
/* 0x000fe40007ffe003 */
/*0130*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fc400078ec0ff */
/*0140*/ IMAD.WIDE.U32 R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0005 */
/*0150*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0005 */
/*0160*/ @!P0 BRA 0x5c0 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x000fe200078e00ff */
/*0180*/ LEA R11, R10.reuse, 0xffffffff, 0x2 ; /* 0xffffffff0a0b7811 */
/* 0x040fe200078e10ff */
/*0190*/ IMAD.MOV R12, RZ, RZ, -R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a00 */
/*01a0*/ LEA R17, R10.reuse, 0xffffffff, 0x1 ; /* 0xffffffff0a117811 */
/* 0x040fe200078e08ff */
/*01b0*/ IMAD R13, R10.reuse, 0x3, -R15.reuse ; /* 0x000000030a0d7824 */
/* 0x140fe200078e0a0f */
/*01c0*/ IADD3 R8, R7, -c[0x0][0x170], RZ ; /* 0x80005c0007087a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD R15, R10, 0x5, -R15 ; /* 0x000000050a0f7824 */
/* 0x000fe200078e0a0f */
/*01e0*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fe40000000f00 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R6.reuse, R17, PT ; /* 0x000000110600720c */
/* 0x040fe20003f26070 */
/*0200*/ BSSY B0, 0x340 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe40003f06070 */
/*0220*/ ISETP.NE.OR P1, PT, R12, -0x1, P1 ; /* 0xffffffff0c00780c */
/* 0x000fc40000f25670 */
/*0230*/ ISETP.GE.U32.AND P3, PT, R6.reuse, R11, PT ; /* 0x0000000b0600720c */
/* 0x040fe40003f66070 */
/*0240*/ IADD3 R19, R9.reuse, 0x1, RZ ; /* 0x0000000109137810 */
/* 0x041fe40007ffe0ff */
/*0250*/ IADD3 R21, R9.reuse, 0x2, RZ ; /* 0x0000000209157810 */
/* 0x040fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P2, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x000fe40003f46070 */
/*0270*/ IADD3 R23, R9, 0x3, RZ ; /* 0x0000000309177810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.OR P0, PT, R0, R19, P0 ; /* 0x000000130000720c */
/* 0x000fc40000705670 */
/*0290*/ ISETP.NE.OR P3, PT, R0.reuse, R21, P3 ; /* 0x000000150000720c */
/* 0x040fe40001f65670 */
/*02a0*/ ISETP.NE.OR P2, PT, R0, R23, P2 ; /* 0x000000170000720c */
/* 0x000fe20001745670 */
/*02b0*/ @P1 BRA 0x330 ; /* 0x0000007000001947 */
/* 0x000fee0003800000 */
/*02c0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*0310*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*0320*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ BSSY B0, 0x3e0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0350*/ @P0 BRA 0x3d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x001ea2000c1e1900 */
/*0380*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe200078e00ff */
/*0390*/ HFMA2.MMA R21, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff157435 */
/* 0x000fe200000001ff */
/*03a0*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*03b0*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*03c0*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ BSSY B0, 0x480 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*03f0*/ @P3 BRA 0x470 ; /* 0x0000007000003947 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x001ea2000c1e1900 */
/*0420*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*0450*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*0460*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ BSSY B0, 0x530 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0490*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @P2 BRA 0x520 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*04b0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*04c0*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x001ea2000c1e1900 */
/*04d0*/ MOV R18, 0x4 ; /* 0x0000000400127802 */
/* 0x000fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*0500*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*0510*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ IMAD.IADD R14, R9, 0x1, R8 ; /* 0x00000001090e7824 */
/* 0x000fe200078e0208 */
/*0540*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe40000000f00 */
/*0550*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0560*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f05270 */
/*0570*/ IMAD R13, R10.reuse, 0x4, R13 ; /* 0x000000040a0d7824 */
/* 0x040fe200078e020d */
/*0580*/ LEA R15, R10.reuse, R15, 0x2 ; /* 0x0000000f0a0f7211 */
/* 0x040fe200078e10ff */
/*0590*/ IMAD R11, R10.reuse, 0x4, R11 ; /* 0x000000040a0b7824 */
/* 0x040fe400078e020b */
/*05a0*/ IMAD R17, R10, 0x4, R17 ; /* 0x000000040a117824 */
/* 0x000fd000078e0211 */
/*05b0*/ @P0 BRA 0x1f0 ; /* 0xfffffc3000000947 */
/* 0x000fea000383ffff */
/*05c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*05d0*/ @!P0 BRA 0x720 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R8, R9.reuse, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x040fe20007ffe0ff */
/*05f0*/ IMAD.IADD R0, R9, 0x1, -R0 ; /* 0x0000000109007824 */
/* 0x000fc800078e0a00 */
/*0600*/ IMAD R11, R8, R10, -0x1 ; /* 0xffffffff080b7424 */
/* 0x000fca00078e020a */
/*0610*/ ISETP.GE.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fe20003f06070 */
/*0620*/ BSSY B0, 0x6f0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0630*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0640*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fe40000705670 */
/*0650*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f25270 */
/*0660*/ @P0 BRA 0x6e0 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0670*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*0680*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0690*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*06a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD R8, R8, c[0x0][0x178], R9 ; /* 0x00005e0008087a24 */
/* 0x004fce00078e0209 */
/*06c0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*06d0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0003e4000c10e184 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ IADD3 R11, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0710*/ @P1 BRA 0x610 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19glcm_calculation_45PiS_iii
.globl _Z19glcm_calculation_45PiS_iii
.p2align 8
.type _Z19glcm_calculation_45PiS_iii,@function
_Z19glcm_calculation_45PiS_iii:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b32 s3, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s3, s14, s3
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
v_add3_u32 v0, s3, v0, v1
v_mov_b32_e32 v1, 0
s_lshl_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s3, s3, -1
v_subrev_nc_u32_e32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v4
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v5, 1
v_add_co_u32 v3, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s1, s1, 1
s_add_i32 s3, s3, s2
s_cmp_lg_u32 s2, s1
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_cmp_eq_u32 s14, s1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, s4, vcc_lo
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v9, v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, s0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[6:7], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_atomic_add_u32 v[6:7], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19glcm_calculation_45PiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19glcm_calculation_45PiS_iii, .Lfunc_end0-_Z19glcm_calculation_45PiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19glcm_calculation_45PiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19glcm_calculation_45PiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3ad2_00000000-6_glcm_calculation_45.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii
.type _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii, @function
_Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19glcm_calculation_45PiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii, .-_Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii
.globl _Z19glcm_calculation_45PiS_iii
.type _Z19glcm_calculation_45PiS_iii, @function
_Z19glcm_calculation_45PiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19glcm_calculation_45PiS_iii, .-_Z19glcm_calculation_45PiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19glcm_calculation_45PiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19glcm_calculation_45PiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "glcm_calculation_45.hip"
.globl _Z34__device_stub__glcm_calculation_45PiS_iii # -- Begin function _Z34__device_stub__glcm_calculation_45PiS_iii
.p2align 4, 0x90
.type _Z34__device_stub__glcm_calculation_45PiS_iii,@function
_Z34__device_stub__glcm_calculation_45PiS_iii: # @_Z34__device_stub__glcm_calculation_45PiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19glcm_calculation_45PiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__glcm_calculation_45PiS_iii, .Lfunc_end0-_Z34__device_stub__glcm_calculation_45PiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19glcm_calculation_45PiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19glcm_calculation_45PiS_iii,@object # @_Z19glcm_calculation_45PiS_iii
.section .rodata,"a",@progbits
.globl _Z19glcm_calculation_45PiS_iii
.p2align 3, 0x0
_Z19glcm_calculation_45PiS_iii:
.quad _Z34__device_stub__glcm_calculation_45PiS_iii
.size _Z19glcm_calculation_45PiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19glcm_calculation_45PiS_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__glcm_calculation_45PiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19glcm_calculation_45PiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void plus_one_kernel(int num_comp, int *y, int *x){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < num_comp){
y[i] = x[i] + 1;
}
} | code for sm_80
Function : _Z15plus_one_kerneliPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void plus_one_kernel(int num_comp, int *y, int *x){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < num_comp){
y[i] = x[i] + 1;
}
} | .file "tmpxft_00138529_00000000-6_kernel_functions_for_math_1d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_
.type _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_, @function
_Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15plus_one_kerneliPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_, .-_Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_
.globl _Z15plus_one_kerneliPiS_
.type _Z15plus_one_kerneliPiS_, @function
_Z15plus_one_kerneliPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15plus_one_kerneliPiS_, .-_Z15plus_one_kerneliPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15plus_one_kerneliPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15plus_one_kerneliPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void plus_one_kernel(int num_comp, int *y, int *x){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < num_comp){
y[i] = x[i] + 1;
}
} | #include <hip/hip_runtime.h>
__global__ void plus_one_kernel(int num_comp, int *y, int *x){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < num_comp){
y[i] = x[i] + 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void plus_one_kernel(int num_comp, int *y, int *x){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < num_comp){
y[i] = x[i] + 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15plus_one_kerneliPiS_
.globl _Z15plus_one_kerneliPiS_
.p2align 8
.type _Z15plus_one_kerneliPiS_,@function
_Z15plus_one_kerneliPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15plus_one_kerneliPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15plus_one_kerneliPiS_, .Lfunc_end0-_Z15plus_one_kerneliPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15plus_one_kerneliPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15plus_one_kerneliPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void plus_one_kernel(int num_comp, int *y, int *x){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < num_comp){
y[i] = x[i] + 1;
}
} | .text
.file "kernel_functions_for_math_1d.hip"
.globl _Z30__device_stub__plus_one_kerneliPiS_ # -- Begin function _Z30__device_stub__plus_one_kerneliPiS_
.p2align 4, 0x90
.type _Z30__device_stub__plus_one_kerneliPiS_,@function
_Z30__device_stub__plus_one_kerneliPiS_: # @_Z30__device_stub__plus_one_kerneliPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15plus_one_kerneliPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__plus_one_kerneliPiS_, .Lfunc_end0-_Z30__device_stub__plus_one_kerneliPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15plus_one_kerneliPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15plus_one_kerneliPiS_,@object # @_Z15plus_one_kerneliPiS_
.section .rodata,"a",@progbits
.globl _Z15plus_one_kerneliPiS_
.p2align 3, 0x0
_Z15plus_one_kerneliPiS_:
.quad _Z30__device_stub__plus_one_kerneliPiS_
.size _Z15plus_one_kerneliPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15plus_one_kerneliPiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__plus_one_kerneliPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15plus_one_kerneliPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15plus_one_kerneliPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15plus_one_kerneliPiS_
.globl _Z15plus_one_kerneliPiS_
.p2align 8
.type _Z15plus_one_kerneliPiS_,@function
_Z15plus_one_kerneliPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15plus_one_kerneliPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15plus_one_kerneliPiS_, .Lfunc_end0-_Z15plus_one_kerneliPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15plus_one_kerneliPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15plus_one_kerneliPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138529_00000000-6_kernel_functions_for_math_1d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_
.type _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_, @function
_Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15plus_one_kerneliPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_, .-_Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_
.globl _Z15plus_one_kerneliPiS_
.type _Z15plus_one_kerneliPiS_, @function
_Z15plus_one_kerneliPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15plus_one_kerneliPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15plus_one_kerneliPiS_, .-_Z15plus_one_kerneliPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15plus_one_kerneliPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15plus_one_kerneliPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_functions_for_math_1d.hip"
.globl _Z30__device_stub__plus_one_kerneliPiS_ # -- Begin function _Z30__device_stub__plus_one_kerneliPiS_
.p2align 4, 0x90
.type _Z30__device_stub__plus_one_kerneliPiS_,@function
_Z30__device_stub__plus_one_kerneliPiS_: # @_Z30__device_stub__plus_one_kerneliPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15plus_one_kerneliPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__plus_one_kerneliPiS_, .Lfunc_end0-_Z30__device_stub__plus_one_kerneliPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15plus_one_kerneliPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15plus_one_kerneliPiS_,@object # @_Z15plus_one_kerneliPiS_
.section .rodata,"a",@progbits
.globl _Z15plus_one_kerneliPiS_
.p2align 3, 0x0
_Z15plus_one_kerneliPiS_:
.quad _Z30__device_stub__plus_one_kerneliPiS_
.size _Z15plus_one_kerneliPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15plus_one_kerneliPiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__plus_one_kerneliPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15plus_one_kerneliPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void distance(float *x, float *y, float *z, int NUM_PART, float *dist)
{
float posx, posy, posz;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idx_dist = idx * (NUM_PART);
for(int i=0; i<NUM_PART; i++)
{
if(idx != i)
{
posx = x[idx] - x[i];
posy = y[idx] - y[i];
posz = z[idx] - z[i];
dist[idx_dist + i] = sqrt(posx * posx + posy * posy + posz * posz);
}
}
}
using namespace std;
int main(int argc, char **argv)
{
float *dev_pos_x, *dev_pos_y, *dev_pos_z, *dev_dist;
float *pos_x, *pos_y, *pos_z, *h_dist;
int NUM_PARTICLES;
if (argc < 2)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
//ifstream infile(argv[1]);
FILE *infile;
infile = fopen(argv[1],"r");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
/*
if(infile.good())
{
infile >> NUM_PARTICLES;
for(int m=0; m <3; m++)
infile >> axis_titles >> axis_titles;
}
else
{
printf("Couldn't open the file for input.\n");
exit(1);
}
*/
fscanf(infile, "%d", &NUM_PARTICLES);
fscanf(infile, "%s %s %s %s", &axis_titles, &dummy, &axis_titles, &dummy);
int size = NUM_PARTICLES * sizeof(float);
pos_x = (float*)malloc(size);
pos_y = (float*)malloc(size);
pos_z = (float*)malloc(size);
h_dist = (float *)malloc(size * size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile, "%e %s %e %s %e %s", &pos_x[i], &dummy, &pos_y[i], &dummy, &pos_z[i], &dummy);
}
////////////////////////////////////////////////////////////////////////////
dim3 grid,block;
block.x = 1;
grid.x = NUM_PARTICLES/block.x;
cudaMalloc((void **) &dev_pos_x, size );
cudaMalloc((void **) &dev_pos_y, size );
cudaMalloc((void **) &dev_pos_z, size );
cudaMalloc((void **) &dev_dist, size * size);
// Check to see if we allocated enough memory.
if (0==dev_pos_z || 0==dev_pos_y|| 0==dev_pos_x)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(dev_pos_x,0,size);
cudaMemset(dev_pos_z,0,size);
cudaMemset(dev_pos_y,0,size);
cudaMemset(dev_dist,0,size*size);
cudaMemcpy(dev_pos_x, pos_x, size, cudaMemcpyHostToDevice );
cudaMemcpy(dev_pos_y, pos_y, size, cudaMemcpyHostToDevice );
cudaMemcpy(dev_pos_z, pos_z, size, cudaMemcpyHostToDevice );
printf("%i\n", NUM_PARTICLES);
for(int k=0; k< NUM_PARTICLES; k++)
printf("%e ", pos_x[k]);
distance<<<block, NUM_PARTICLES >>>(dev_pos_x, dev_pos_y, dev_pos_z, NUM_PARTICLES, dev_dist);
//cudaMemset(dev_dist,1.0,size*size);
cudaMemcpy(h_dist, dev_dist, size * size, cudaMemcpyDeviceToHost );
printf("\n%s\n", "distances");
for(int k=0; k< NUM_PARTICLES * NUM_PARTICLES; k++)
{
printf("%e\n", h_dist[k]);
}
free(pos_x);
free(pos_y);
free(pos_z);
cudaFree(dev_pos_x);
cudaFree(dev_pos_y);
cudaFree(dev_pos_z);
return 0;
} | code for sm_80
Function : _Z8distancePfS_S_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R20, c[0x0][0x178] ; /* 0x00005e0000147a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ IADD3 R2, R20, -0x1, RZ ; /* 0xffffffff14027810 */
/* 0x000fe20007ffe0ff */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e220000002100 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x000fe400078ec0ff */
/*00b0*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R18, R0, c[0x0][0x0], R19 ; /* 0x0000000000127a24 */
/* 0x001fc800078e0213 */
/*00d0*/ IMAD.WIDE R14, R18, R9, c[0x0][0x160] ; /* 0x00005800120e7625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R12, R18, R9, c[0x0][0x168] ; /* 0x00005a00120c7625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R10, R18, R9, c[0x0][0x170] ; /* 0x00005c00120a7625 */
/* 0x000fe200078e0209 */
/*0100*/ @!P0 BRA 0xa40 ; /* 0x0000093000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD R8, R18, c[0x0][0x178], RZ ; /* 0x00005e0012087a24 */
/* 0x000fe200078e02ff */
/*0120*/ IADD3 R26, -R20, c[0x0][0x178], RZ ; /* 0x00005e00141a7a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R27, -R18, RZ, RZ ; /* 0x000000ff121b7210 */
/* 0x000fe20007ffe1ff */
/*0150*/ IMAD.WIDE R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fe200078e0209 */
/*0160*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe40000000f00 */
/*01c0*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fe20003f05270 */
/*01d0*/ BSSY B0, 0x3a0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*01e0*/ @!P0 BRA 0x390 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0240*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0250*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000f22000c1e1900 */
/*0260*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0270*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0280*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0290*/ BSSY B1, 0x380 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*02a0*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*02b0*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*02c0*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*02f0*/ @!P0 BRA 0x330 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0300*/ MOV R16, 0x320 ; /* 0x0000032000107802 */
/* 0x003fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0xdc0 ; /* 0x00000aa000007944 */
/* 0x000fea0003c00000 */
/*0320*/ BRA 0x370 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0330*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0340*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0350*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0360*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ STG.E [R8.64], R22 ; /* 0x0000001608007986 */
/* 0x0001e4000c101904 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R17, R21, 0x1, RZ ; /* 0x0000000115117810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B0, 0x590 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.NE.AND P0, PT, R18, R17, PT ; /* 0x000000111200720c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 BRA 0x580 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R22, [R4.64+0x4] ; /* 0x0000040404167981 */
/* 0x001ea8000c1e1900 */
/*03f0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ee8000c1e1900 */
/*0420*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0430*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0440*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000f22000c1e1900 */
/*0450*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0460*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0470*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0480*/ BSSY B1, 0x570 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0490*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*04a0*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*04b0*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*04e0*/ @!P0 BRA 0x520 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*04f0*/ MOV R16, 0x510 ; /* 0x0000051000107802 */
/* 0x003fe40000000f00 */
/*0500*/ CALL.REL.NOINC 0xdc0 ; /* 0x000008b000007944 */
/* 0x000fea0003c00000 */
/*0510*/ BRA 0x560 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0520*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0530*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0540*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0550*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0560*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0570*/ STG.E [R8.64+0x4], R22 ; /* 0x0000041608007986 */
/* 0x0001e4000c101904 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ IADD3 R17, R21, 0x2, RZ ; /* 0x0000000215117810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ BSSY B0, 0x780 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*05b0*/ ISETP.NE.AND P0, PT, R18, R17, PT ; /* 0x000000111200720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x770 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080404167981 */
/* 0x001ea8000c1e1900 */
/*05e0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0600*/ LDG.E R17, [R6.64+0x8] ; /* 0x0000080406117981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0620*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0630*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f22000c1e1900 */
/*0640*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0650*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0660*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0670*/ BSSY B1, 0x760 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0680*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*0690*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*06a0*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*06c0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*06d0*/ @!P0 BRA 0x710 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R16, 0x700 ; /* 0x0000070000107802 */
/* 0x003fe40000000f00 */
/*06f0*/ CALL.REL.NOINC 0xdc0 ; /* 0x000006c000007944 */
/* 0x000fea0003c00000 */
/*0700*/ BRA 0x750 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0710*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0720*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0730*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0740*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ STG.E [R8.64+0x8], R22 ; /* 0x0000081608007986 */
/* 0x0001e4000c101904 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R17, R21, 0x3, RZ ; /* 0x0000000315117810 */
/* 0x000fe20007ffe0ff */
/*0790*/ BSSY B0, 0x970 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*07a0*/ ISETP.NE.AND P0, PT, R18, R17, PT ; /* 0x000000111200720c */
/* 0x000fda0003f05270 */
/*07b0*/ @!P0 BRA 0x960 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x001ea8000c1e1900 */
/*07d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000ee8000c1e1900 */
/*0800*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0810*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0820*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402177981 */
/* 0x000f22000c1e1900 */
/*0830*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0840*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0850*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0860*/ BSSY B1, 0x950 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0870*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*0880*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*0890*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*08c0*/ @!P0 BRA 0x900 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R16, 0x8f0 ; /* 0x000008f000107802 */
/* 0x003fe40000000f00 */
/*08e0*/ CALL.REL.NOINC 0xdc0 ; /* 0x000004d000007944 */
/* 0x000fea0003c00000 */
/*08f0*/ BRA 0x940 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0900*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0910*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0920*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0930*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ STG.E [R8.64+0xc], R22 ; /* 0x00000c1608007986 */
/* 0x0001e4000c101904 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fe40007ffe0ff */
/*0980*/ IADD3 R6, P4, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007f9e0ff */
/*0990*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f05270 */
/*09a0*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x001fe20007f3e0ff */
/*09b0*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*09c0*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007f5e0ff */
/*09d0*/ IADD3 R4, P3, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc40007f7e0ff */
/*09e0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40000ffe4ff */
/*09f0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0a00*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40001ffe4ff */
/*0a10*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*0a20*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fe20007ffe0ff */
/*0a30*/ @P0 BRA 0x1c0 ; /* 0xfffff78000000947 */
/* 0x000fea000383ffff */
/*0a40*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fda0003f05270 */
/*0a50*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a60*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0a70*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x000fe20007ffe1ff */
/*0a80*/ IMAD R6, R18, c[0x0][0x178], R21 ; /* 0x00005e0012067a24 */
/* 0x000fc800078e0215 */
/*0a90*/ IMAD R0, R0, c[0x0][0x0], R21 ; /* 0x0000000000007a24 */
/* 0x000fc800078e0215 */
/*0aa0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0208 */
/*0ab0*/ IADD3 R19, R0, -R19, RZ ; /* 0x8000001300137210 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ IMAD.WIDE R4, R21, R8, c[0x0][0x170] ; /* 0x00005c0015047625 */
/* 0x000fc800078e0208 */
/*0ad0*/ IMAD.WIDE R2, R21, R8, c[0x0][0x168] ; /* 0x00005a0015027625 */
/* 0x000fc800078e0208 */
/*0ae0*/ IMAD.WIDE R8, R21, R8, c[0x0][0x160] ; /* 0x0000580015087625 */
/* 0x000fca00078e0208 */
/*0af0*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe40000000f00 */
/*0b00*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f05270 */
/*0b10*/ BSSY B0, 0xcf0 ; /* 0x000001d000007945 */
/* 0x000fd80003800000 */
/*0b20*/ @!P0 BRA 0xce0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0b30*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe20000000f00 */
/*0b40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*0b50*/ LDG.E R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea8000c1e1900 */
/*0b60*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee8000c1e1900 */
/*0b70*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0b80*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000f28000c1e1900 */
/*0b90*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000f22000c1e1900 */
/*0ba0*/ BSSY B1, 0xcd0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0bb0*/ FADD R18, -R18, R21 ; /* 0x0000001512127221 */
/* 0x004fc40000000100 */
/*0bc0*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0bd0*/ FMUL R17, R18, R18 ; /* 0x0000001212117220 */
/* 0x000fc80000400000 */
/*0be0*/ FFMA R17, R16, R16, R17 ; /* 0x0000001010117223 */
/* 0x000fe40000000011 */
/*0bf0*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x010fc80000000100 */
/*0c00*/ FFMA R17, R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000011 */
/*0c10*/ MUFU.RSQ R16, R17 ; /* 0x0000001100107308 */
/* 0x0000620000001400 */
/*0c20*/ IADD3 R8, R17, -0xd000000, RZ ; /* 0xf300000011087810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f04070 */
/*0c40*/ @!P0 BRA 0xc80 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0c50*/ MOV R16, 0xc70 ; /* 0x00000c7000107802 */
/* 0x003fe40000000f00 */
/*0c60*/ CALL.REL.NOINC 0xdc0 ; /* 0x0000015000007944 */
/* 0x000fea0003c00000 */
/*0c70*/ BRA 0xcc0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0c80*/ FMUL.FTZ R22, R17, R16 ; /* 0x0000001011167220 */
/* 0x003fe40000410000 */
/*0c90*/ FMUL.FTZ R8, R16, 0.5 ; /* 0x3f00000010087820 */
/* 0x000fe40000410000 */
/*0ca0*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0cb0*/ FFMA R22, R17, R8, R22 ; /* 0x0000000811167223 */
/* 0x000fe40000000016 */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ STG.E [R6.64], R22 ; /* 0x0000001606007986 */
/* 0x0001e4000c101904 */
/*0ce0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0cf0*/ IADD3 R20, R20, -0x1, RZ ; /* 0xffffffff14147810 */
/* 0x000fe40007ffe0ff */
/*0d00*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007f5e0ff */
/*0d10*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f05270 */
/*0d20*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe20007f3e0ff */
/*0d30*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0d40*/ IADD3 R2, P3, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007f7e0ff */
/*0d50*/ IADD3 R0, P4, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc40007f9e0ff */
/*0d60*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0d80*/ IADD3.X R3, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff037210 */
/* 0x000fe40001ffe4ff */
/*0d90*/ IADD3.X R9, RZ, R9, RZ, P4, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200027fe4ff */
/*0da0*/ @P0 BRA 0xb00 ; /* 0xfffffd5000000947 */
/* 0x000fea000383ffff */
/*0db0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dc0*/ LOP3.LUT P0, RZ, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff11ff7812 */
/* 0x000fda000780c0ff */
/*0dd0*/ @!P0 MOV R22, R17 ; /* 0x0000001100168202 */
/* 0x000fe20000000f00 */
/*0de0*/ @!P0 BRA 0xef0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0df0*/ FSETP.GEU.FTZ.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720b */
/* 0x000fda0003f1e000 */
/*0e00*/ @!P0 MOV R22, 0x7fffffff ; /* 0x7fffffff00168802 */
/* 0x000fe20000000f00 */
/*0e10*/ @!P0 BRA 0xef0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0e20*/ FSETP.GTU.FTZ.AND P0, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */
/* 0x000fda0003f1c200 */
/*0e30*/ @P0 FADD.FTZ R22, R17, 1 ; /* 0x3f80000011160421 */
/* 0x000fe20000010000 */
/*0e40*/ @P0 BRA 0xef0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0e50*/ FSETP.NEU.FTZ.AND P0, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */
/* 0x000fda0003f1d200 */
/*0e60*/ @P0 FFMA R24, R17, 1.84467440737095516160e+19, RZ ; /* 0x5f80000011180823 */
/* 0x000fc800000000ff */
/*0e70*/ @P0 MUFU.RSQ R23, R24 ; /* 0x0000001800170308 */
/* 0x000e240000001400 */
/*0e80*/ @P0 FMUL.FTZ R22, R24, R23 ; /* 0x0000001718160220 */
/* 0x001fe40000410000 */
/*0e90*/ @P0 FMUL.FTZ R23, R23, 0.5 ; /* 0x3f00000017170820 */
/* 0x000fe40000410000 */
/*0ea0*/ @P0 FADD.FTZ R25, -R22, -RZ ; /* 0x800000ff16190221 */
/* 0x000fc80000010100 */
/*0eb0*/ @P0 FFMA R25, R22, R25, R24 ; /* 0x0000001916190223 */
/* 0x000fc80000000018 */
/*0ec0*/ @P0 FFMA R23, R25, R23, R22 ; /* 0x0000001719170223 */
/* 0x000fe20000000016 */
/*0ed0*/ @!P0 MOV R22, R17 ; /* 0x0000001100168202 */
/* 0x000fc60000000f00 */
/*0ee0*/ @P0 FMUL.FTZ R22, R23, 2.3283064365386962891e-10 ; /* 0x2f80000017160820 */
/* 0x000fe40000410000 */
/*0ef0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fcc00000001ff */
/*0f00*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff0f010007950 */
/* 0x000fea0003c3ffff */
/*0f10*/ BRA 0xf10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void distance(float *x, float *y, float *z, int NUM_PART, float *dist)
{
float posx, posy, posz;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idx_dist = idx * (NUM_PART);
for(int i=0; i<NUM_PART; i++)
{
if(idx != i)
{
posx = x[idx] - x[i];
posy = y[idx] - y[i];
posz = z[idx] - z[i];
dist[idx_dist + i] = sqrt(posx * posx + posy * posy + posz * posz);
}
}
}
using namespace std;
int main(int argc, char **argv)
{
float *dev_pos_x, *dev_pos_y, *dev_pos_z, *dev_dist;
float *pos_x, *pos_y, *pos_z, *h_dist;
int NUM_PARTICLES;
if (argc < 2)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
//ifstream infile(argv[1]);
FILE *infile;
infile = fopen(argv[1],"r");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
/*
if(infile.good())
{
infile >> NUM_PARTICLES;
for(int m=0; m <3; m++)
infile >> axis_titles >> axis_titles;
}
else
{
printf("Couldn't open the file for input.\n");
exit(1);
}
*/
fscanf(infile, "%d", &NUM_PARTICLES);
fscanf(infile, "%s %s %s %s", &axis_titles, &dummy, &axis_titles, &dummy);
int size = NUM_PARTICLES * sizeof(float);
pos_x = (float*)malloc(size);
pos_y = (float*)malloc(size);
pos_z = (float*)malloc(size);
h_dist = (float *)malloc(size * size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile, "%e %s %e %s %e %s", &pos_x[i], &dummy, &pos_y[i], &dummy, &pos_z[i], &dummy);
}
////////////////////////////////////////////////////////////////////////////
dim3 grid,block;
block.x = 1;
grid.x = NUM_PARTICLES/block.x;
cudaMalloc((void **) &dev_pos_x, size );
cudaMalloc((void **) &dev_pos_y, size );
cudaMalloc((void **) &dev_pos_z, size );
cudaMalloc((void **) &dev_dist, size * size);
// Check to see if we allocated enough memory.
if (0==dev_pos_z || 0==dev_pos_y|| 0==dev_pos_x)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(dev_pos_x,0,size);
cudaMemset(dev_pos_z,0,size);
cudaMemset(dev_pos_y,0,size);
cudaMemset(dev_dist,0,size*size);
cudaMemcpy(dev_pos_x, pos_x, size, cudaMemcpyHostToDevice );
cudaMemcpy(dev_pos_y, pos_y, size, cudaMemcpyHostToDevice );
cudaMemcpy(dev_pos_z, pos_z, size, cudaMemcpyHostToDevice );
printf("%i\n", NUM_PARTICLES);
for(int k=0; k< NUM_PARTICLES; k++)
printf("%e ", pos_x[k]);
distance<<<block, NUM_PARTICLES >>>(dev_pos_x, dev_pos_y, dev_pos_z, NUM_PARTICLES, dev_dist);
//cudaMemset(dev_dist,1.0,size*size);
cudaMemcpy(h_dist, dev_dist, size * size, cudaMemcpyDeviceToHost );
printf("\n%s\n", "distances");
for(int k=0; k< NUM_PARTICLES * NUM_PARTICLES; k++)
{
printf("%e\n", h_dist[k]);
}
free(pos_x);
free(pos_y);
free(pos_z);
cudaFree(dev_pos_x);
cudaFree(dev_pos_y);
cudaFree(dev_pos_z);
return 0;
} | .file "tmpxft_0007be93_00000000-6_CUDA_copy_coordinates_with_C.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
.type _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_, @function
_Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8distancePfS_S_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_, .-_Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
.globl _Z8distancePfS_S_iS_
.type _Z8distancePfS_S_iS_, @function
_Z8distancePfS_S_iS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8distancePfS_S_iS_, .-_Z8distancePfS_S_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nMust pass in cluster_data file on command line!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nUsage: "
.section .rodata.str1.8
.align 8
.LC2:
.string " <cluster_data file> <distances file> \n\n"
.section .rodata.str1.1
.LC3:
.string "r"
.LC4:
.string "%d"
.LC5:
.string "%s %s %s %s"
.LC6:
.string "%e %s %e %s %e %s"
.LC7:
.string "couldn't allocate memory\n"
.LC8:
.string "%i\n"
.LC9:
.string "%e "
.LC10:
.string "distances"
.LC11:
.string "\n%s\n"
.LC12:
.string "%e\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $648, %rsp
.cfi_def_cfa_offset 704
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 632(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L28
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r14
leaq 52(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 368(%rsp), %rcx
leaq 112(%rsp), %rdx
movq %rcx, %r9
movq %rdx, %r8
leaq .LC5(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 52(%rsp), %ebx
leal 0(,%rbx,4), %ebp
movslq %ebp, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 32(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
imull %ebp, %ebp
movslq %ebp, %rdx
movq %rdx, 8(%rsp)
movq %rdx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L13
movq 16(%rsp), %rbp
movl $0, %ebx
.L14:
leaq 368(%rsp), %rcx
pushq %rcx
.cfi_def_cfa_offset 712
pushq %rbp
.cfi_def_cfa_offset 720
movq %rcx, %r9
movq %r12, %r8
movq %r13, %rdx
leaq .LC6(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %r13
addq $4, %r12
addq $4, %rbp
addq $16, %rsp
.cfi_def_cfa_offset 704
cmpl %ebx, 52(%rsp)
jg .L14
.L13:
movl $1, 92(%rsp)
movl $1, 96(%rsp)
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
cmpq $0, 72(%rsp)
je .L15
cmpq $0, 64(%rsp)
je .L15
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L15
movq %r15, %rdx
movl $0, %esi
call cudaMemset@PLT
movq %r15, %rdx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movq %r15, %rdx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movq 8(%rsp), %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %r15, %rdx
movq 24(%rsp), %r12
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
testl %eax, %eax
jle .L18
movl $0, %ebx
leaq .LC9(%rip), %rbp
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L19
.L18:
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L20:
movl $2, %ecx
movq 8(%rsp), %rdx
movq 80(%rsp), %rsi
movq 40(%rsp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L21
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
addq $1, %rbx
imull %eax, %eax
cmpl %ebx, %eax
jg .L22
.L21:
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 632(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L29:
movq 80(%rsp), %r8
movl 52(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8distancePfS_S_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8distancePfS_S_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void distance(float *x, float *y, float *z, int NUM_PART, float *dist)
{
float posx, posy, posz;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idx_dist = idx * (NUM_PART);
for(int i=0; i<NUM_PART; i++)
{
if(idx != i)
{
posx = x[idx] - x[i];
posy = y[idx] - y[i];
posz = z[idx] - z[i];
dist[idx_dist + i] = sqrt(posx * posx + posy * posy + posz * posz);
}
}
}
using namespace std;
int main(int argc, char **argv)
{
float *dev_pos_x, *dev_pos_y, *dev_pos_z, *dev_dist;
float *pos_x, *pos_y, *pos_z, *h_dist;
int NUM_PARTICLES;
if (argc < 2)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
//ifstream infile(argv[1]);
FILE *infile;
infile = fopen(argv[1],"r");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
/*
if(infile.good())
{
infile >> NUM_PARTICLES;
for(int m=0; m <3; m++)
infile >> axis_titles >> axis_titles;
}
else
{
printf("Couldn't open the file for input.\n");
exit(1);
}
*/
fscanf(infile, "%d", &NUM_PARTICLES);
fscanf(infile, "%s %s %s %s", &axis_titles, &dummy, &axis_titles, &dummy);
int size = NUM_PARTICLES * sizeof(float);
pos_x = (float*)malloc(size);
pos_y = (float*)malloc(size);
pos_z = (float*)malloc(size);
h_dist = (float *)malloc(size * size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile, "%e %s %e %s %e %s", &pos_x[i], &dummy, &pos_y[i], &dummy, &pos_z[i], &dummy);
}
////////////////////////////////////////////////////////////////////////////
dim3 grid,block;
block.x = 1;
grid.x = NUM_PARTICLES/block.x;
cudaMalloc((void **) &dev_pos_x, size );
cudaMalloc((void **) &dev_pos_y, size );
cudaMalloc((void **) &dev_pos_z, size );
cudaMalloc((void **) &dev_dist, size * size);
// Check to see if we allocated enough memory.
if (0==dev_pos_z || 0==dev_pos_y|| 0==dev_pos_x)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(dev_pos_x,0,size);
cudaMemset(dev_pos_z,0,size);
cudaMemset(dev_pos_y,0,size);
cudaMemset(dev_dist,0,size*size);
cudaMemcpy(dev_pos_x, pos_x, size, cudaMemcpyHostToDevice );
cudaMemcpy(dev_pos_y, pos_y, size, cudaMemcpyHostToDevice );
cudaMemcpy(dev_pos_z, pos_z, size, cudaMemcpyHostToDevice );
printf("%i\n", NUM_PARTICLES);
for(int k=0; k< NUM_PARTICLES; k++)
printf("%e ", pos_x[k]);
distance<<<block, NUM_PARTICLES >>>(dev_pos_x, dev_pos_y, dev_pos_z, NUM_PARTICLES, dev_dist);
//cudaMemset(dev_dist,1.0,size*size);
cudaMemcpy(h_dist, dev_dist, size * size, cudaMemcpyDeviceToHost );
printf("\n%s\n", "distances");
for(int k=0; k< NUM_PARTICLES * NUM_PARTICLES; k++)
{
printf("%e\n", h_dist[k]);
}
free(pos_x);
free(pos_y);
free(pos_z);
cudaFree(dev_pos_x);
cudaFree(dev_pos_y);
cudaFree(dev_pos_z);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void distance(float *x, float *y, float *z, int NUM_PART, float *dist)
{
float posx, posy, posz;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idx_dist = idx * (NUM_PART);
for(int i=0; i<NUM_PART; i++)
{
if(idx != i)
{
posx = x[idx] - x[i];
posy = y[idx] - y[i];
posz = z[idx] - z[i];
dist[idx_dist + i] = sqrt(posx * posx + posy * posy + posz * posz);
}
}
}
using namespace std;
int main(int argc, char **argv)
{
float *dev_pos_x, *dev_pos_y, *dev_pos_z, *dev_dist;
float *pos_x, *pos_y, *pos_z, *h_dist;
int NUM_PARTICLES;
if (argc < 2)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
//ifstream infile(argv[1]);
FILE *infile;
infile = fopen(argv[1],"r");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
/*
if(infile.good())
{
infile >> NUM_PARTICLES;
for(int m=0; m <3; m++)
infile >> axis_titles >> axis_titles;
}
else
{
printf("Couldn't open the file for input.\n");
exit(1);
}
*/
fscanf(infile, "%d", &NUM_PARTICLES);
fscanf(infile, "%s %s %s %s", &axis_titles, &dummy, &axis_titles, &dummy);
int size = NUM_PARTICLES * sizeof(float);
pos_x = (float*)malloc(size);
pos_y = (float*)malloc(size);
pos_z = (float*)malloc(size);
h_dist = (float *)malloc(size * size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile, "%e %s %e %s %e %s", &pos_x[i], &dummy, &pos_y[i], &dummy, &pos_z[i], &dummy);
}
////////////////////////////////////////////////////////////////////////////
dim3 grid,block;
block.x = 1;
grid.x = NUM_PARTICLES/block.x;
hipMalloc((void **) &dev_pos_x, size );
hipMalloc((void **) &dev_pos_y, size );
hipMalloc((void **) &dev_pos_z, size );
hipMalloc((void **) &dev_dist, size * size);
// Check to see if we allocated enough memory.
if (0==dev_pos_z || 0==dev_pos_y|| 0==dev_pos_x)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(dev_pos_x,0,size);
hipMemset(dev_pos_z,0,size);
hipMemset(dev_pos_y,0,size);
hipMemset(dev_dist,0,size*size);
hipMemcpy(dev_pos_x, pos_x, size, hipMemcpyHostToDevice );
hipMemcpy(dev_pos_y, pos_y, size, hipMemcpyHostToDevice );
hipMemcpy(dev_pos_z, pos_z, size, hipMemcpyHostToDevice );
printf("%i\n", NUM_PARTICLES);
for(int k=0; k< NUM_PARTICLES; k++)
printf("%e ", pos_x[k]);
distance<<<block, NUM_PARTICLES >>>(dev_pos_x, dev_pos_y, dev_pos_z, NUM_PARTICLES, dev_dist);
//cudaMemset(dev_dist,1.0,size*size);
hipMemcpy(h_dist, dev_dist, size * size, hipMemcpyDeviceToHost );
printf("\n%s\n", "distances");
for(int k=0; k< NUM_PARTICLES * NUM_PARTICLES; k++)
{
printf("%e\n", h_dist[k]);
}
free(pos_x);
free(pos_y);
free(pos_z);
hipFree(dev_pos_x);
hipFree(dev_pos_y);
hipFree(dev_pos_z);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void distance(float *x, float *y, float *z, int NUM_PART, float *dist)
{
float posx, posy, posz;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idx_dist = idx * (NUM_PART);
for(int i=0; i<NUM_PART; i++)
{
if(idx != i)
{
posx = x[idx] - x[i];
posy = y[idx] - y[i];
posz = z[idx] - z[i];
dist[idx_dist + i] = sqrt(posx * posx + posy * posy + posz * posz);
}
}
}
using namespace std;
int main(int argc, char **argv)
{
float *dev_pos_x, *dev_pos_y, *dev_pos_z, *dev_dist;
float *pos_x, *pos_y, *pos_z, *h_dist;
int NUM_PARTICLES;
if (argc < 2)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
//ifstream infile(argv[1]);
FILE *infile;
infile = fopen(argv[1],"r");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
/*
if(infile.good())
{
infile >> NUM_PARTICLES;
for(int m=0; m <3; m++)
infile >> axis_titles >> axis_titles;
}
else
{
printf("Couldn't open the file for input.\n");
exit(1);
}
*/
fscanf(infile, "%d", &NUM_PARTICLES);
fscanf(infile, "%s %s %s %s", &axis_titles, &dummy, &axis_titles, &dummy);
int size = NUM_PARTICLES * sizeof(float);
pos_x = (float*)malloc(size);
pos_y = (float*)malloc(size);
pos_z = (float*)malloc(size);
h_dist = (float *)malloc(size * size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile, "%e %s %e %s %e %s", &pos_x[i], &dummy, &pos_y[i], &dummy, &pos_z[i], &dummy);
}
////////////////////////////////////////////////////////////////////////////
dim3 grid,block;
block.x = 1;
grid.x = NUM_PARTICLES/block.x;
hipMalloc((void **) &dev_pos_x, size );
hipMalloc((void **) &dev_pos_y, size );
hipMalloc((void **) &dev_pos_z, size );
hipMalloc((void **) &dev_dist, size * size);
// Check to see if we allocated enough memory.
if (0==dev_pos_z || 0==dev_pos_y|| 0==dev_pos_x)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(dev_pos_x,0,size);
hipMemset(dev_pos_z,0,size);
hipMemset(dev_pos_y,0,size);
hipMemset(dev_dist,0,size*size);
hipMemcpy(dev_pos_x, pos_x, size, hipMemcpyHostToDevice );
hipMemcpy(dev_pos_y, pos_y, size, hipMemcpyHostToDevice );
hipMemcpy(dev_pos_z, pos_z, size, hipMemcpyHostToDevice );
printf("%i\n", NUM_PARTICLES);
for(int k=0; k< NUM_PARTICLES; k++)
printf("%e ", pos_x[k]);
distance<<<block, NUM_PARTICLES >>>(dev_pos_x, dev_pos_y, dev_pos_z, NUM_PARTICLES, dev_dist);
//cudaMemset(dev_dist,1.0,size*size);
hipMemcpy(h_dist, dev_dist, size * size, hipMemcpyDeviceToHost );
printf("\n%s\n", "distances");
for(int k=0; k< NUM_PARTICLES * NUM_PARTICLES; k++)
{
printf("%e\n", h_dist[k]);
}
free(pos_x);
free(pos_y);
free(pos_z);
hipFree(dev_pos_x);
hipFree(dev_pos_y);
hipFree(dev_pos_z);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8distancePfS_S_iS_
.globl _Z8distancePfS_S_iS_
.p2align 8
.type _Z8distancePfS_S_iS_,@function
_Z8distancePfS_S_iS_:
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_mul_lo_u32 v2, v1, s10
v_add_co_u32 v4, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s10, s10, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
v_add_nc_u32_e32 v1, -1, v1
v_add_nc_u32_e32 v2, 1, v2
s_addc_u32 s7, s7, 0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_2
global_load_b32 v3, v[6:7], off
s_clause 0x1
global_load_b32 v10, v0, s[6:7]
global_load_b32 v11, v0, s[4:5]
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[8:9], off
global_load_b32 v14, v0, s[2:3]
s_waitcnt vmcnt(2)
v_dual_sub_f32 v3, v3, v10 :: v_dual_sub_f32 v10, v12, v11
s_waitcnt vmcnt(0)
v_sub_f32_e32 v11, v13, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v3
v_fmac_f32_e32 v3, v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v11, v11
v_mul_f32_e32 v10, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v12, v3, v10, vcc_lo
v_sqrt_f32_e32 v3, v12
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v11, 1, v3
v_add_nc_u32_e32 v10, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v11, v3, v12
v_fma_f32 v13, -v10, v3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v13
v_cndmask_b32_e64 v3, v3, v10, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v14
v_cndmask_b32_e64 v10, v3, v11, s0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x37800000, v10
v_cndmask_b32_e32 v13, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v12, 0x260
v_cndmask_b32_e32 v3, v13, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[10:11], v3, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8distancePfS_S_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8distancePfS_S_iS_, .Lfunc_end0-_Z8distancePfS_S_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8distancePfS_S_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8distancePfS_S_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void distance(float *x, float *y, float *z, int NUM_PART, float *dist)
{
float posx, posy, posz;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idx_dist = idx * (NUM_PART);
for(int i=0; i<NUM_PART; i++)
{
if(idx != i)
{
posx = x[idx] - x[i];
posy = y[idx] - y[i];
posz = z[idx] - z[i];
dist[idx_dist + i] = sqrt(posx * posx + posy * posy + posz * posz);
}
}
}
using namespace std;
int main(int argc, char **argv)
{
float *dev_pos_x, *dev_pos_y, *dev_pos_z, *dev_dist;
float *pos_x, *pos_y, *pos_z, *h_dist;
int NUM_PARTICLES;
if (argc < 2)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
//ifstream infile(argv[1]);
FILE *infile;
infile = fopen(argv[1],"r");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
/*
if(infile.good())
{
infile >> NUM_PARTICLES;
for(int m=0; m <3; m++)
infile >> axis_titles >> axis_titles;
}
else
{
printf("Couldn't open the file for input.\n");
exit(1);
}
*/
fscanf(infile, "%d", &NUM_PARTICLES);
fscanf(infile, "%s %s %s %s", &axis_titles, &dummy, &axis_titles, &dummy);
int size = NUM_PARTICLES * sizeof(float);
pos_x = (float*)malloc(size);
pos_y = (float*)malloc(size);
pos_z = (float*)malloc(size);
h_dist = (float *)malloc(size * size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile, "%e %s %e %s %e %s", &pos_x[i], &dummy, &pos_y[i], &dummy, &pos_z[i], &dummy);
}
////////////////////////////////////////////////////////////////////////////
dim3 grid,block;
block.x = 1;
grid.x = NUM_PARTICLES/block.x;
hipMalloc((void **) &dev_pos_x, size );
hipMalloc((void **) &dev_pos_y, size );
hipMalloc((void **) &dev_pos_z, size );
hipMalloc((void **) &dev_dist, size * size);
// Check to see if we allocated enough memory.
if (0==dev_pos_z || 0==dev_pos_y|| 0==dev_pos_x)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(dev_pos_x,0,size);
hipMemset(dev_pos_z,0,size);
hipMemset(dev_pos_y,0,size);
hipMemset(dev_dist,0,size*size);
hipMemcpy(dev_pos_x, pos_x, size, hipMemcpyHostToDevice );
hipMemcpy(dev_pos_y, pos_y, size, hipMemcpyHostToDevice );
hipMemcpy(dev_pos_z, pos_z, size, hipMemcpyHostToDevice );
printf("%i\n", NUM_PARTICLES);
for(int k=0; k< NUM_PARTICLES; k++)
printf("%e ", pos_x[k]);
distance<<<block, NUM_PARTICLES >>>(dev_pos_x, dev_pos_y, dev_pos_z, NUM_PARTICLES, dev_dist);
//cudaMemset(dev_dist,1.0,size*size);
hipMemcpy(h_dist, dev_dist, size * size, hipMemcpyDeviceToHost );
printf("\n%s\n", "distances");
for(int k=0; k< NUM_PARTICLES * NUM_PARTICLES; k++)
{
printf("%e\n", h_dist[k]);
}
free(pos_x);
free(pos_y);
free(pos_z);
hipFree(dev_pos_x);
hipFree(dev_pos_y);
hipFree(dev_pos_z);
return 0;
} | .text
.file "CUDA_copy_coordinates_with_C.hip"
.globl _Z23__device_stub__distancePfS_S_iS_ # -- Begin function _Z23__device_stub__distancePfS_S_iS_
.p2align 4, 0x90
.type _Z23__device_stub__distancePfS_S_iS_,@function
_Z23__device_stub__distancePfS_S_iS_: # @_Z23__device_stub__distancePfS_S_iS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8distancePfS_S_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__distancePfS_S_iS_, .Lfunc_end0-_Z23__device_stub__distancePfS_S_iS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $744, %rsp # imm = 0x2E8
.cfi_def_cfa_offset 800
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB1_18
# %bb.1:
movq 8(%rsi), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
leaq 4(%rsp), %rdx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 480(%rsp), %rdx
leaq 224(%rsp), %r15
movl $.L.str.5, %esi
movq %r14, %rdi
movq %r15, %rcx
movq %rdx, %r8
movq %r15, %r9
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
shll $2, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, 80(%rsp) # 8-byte Spill
movl %ebx, %edi
imull %edi, %edi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
cmpl $0, 4(%rsp)
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movq 64(%rsp), %rbx # 8-byte Reload
movq 40(%rsp), %r12 # 8-byte Reload
movq 32(%rsp), %r13 # 8-byte Reload
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %r15, %rcx
movq %r12, %r8
movq %r15, %r9
xorl %eax, %eax
pushq %r15
.cfi_adjust_cfa_offset 8
pushq %r13
.cfi_adjust_cfa_offset 8
callq __isoc23_fscanf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
incq %rbp
movslq 4(%rsp), %rax
addq $4, %r13
addq $4, %r12
addq $4, %rbx
cmpq %rax, %rbp
jl .LBB1_3
.LBB1_4: # %._crit_edge
leaq 24(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
cmpq $0, 8(%rsp)
je .LBB1_7
# %bb.5: # %._crit_edge
cmpq $0, 16(%rsp)
je .LBB1_7
# %bb.6: # %._crit_edge
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.8:
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 48(%rsp), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movq 24(%rsp), %rdi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 4(%rsp), %eax
testl %eax, %eax
movq 72(%rsp), %r15 # 8-byte Reload
jle .LBB1_11
# %bb.9: # %.lr.ph71.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph71
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge72
movl %eax, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl 4(%rsp), %esi
movq 48(%rsp), %rdi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 60(%rsp)
movq %rdi, 144(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z8distancePfS_S_iS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
movq 48(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
movl $.L.str.10, %edi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
je .LBB1_16
# %bb.14: # %.lr.ph75.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_15: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
incq %rbx
movl 4(%rsp), %eax
imull %eax, %eax
cmpq %rax, %rbx
jb .LBB1_15
.LBB1_16: # %._crit_edge76
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB1_17
.LBB1_7:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebp
.LBB1_17:
movl %ebp, %eax
addq $744, %rsp # imm = 0x2E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 800
movl $.Lstr.1, %edi
movq %rsi, %rbx
callq puts@PLT
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8distancePfS_S_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8distancePfS_S_iS_,@object # @_Z8distancePfS_S_iS_
.section .rodata,"a",@progbits
.globl _Z8distancePfS_S_iS_
.p2align 3, 0x0
_Z8distancePfS_S_iS_:
.quad _Z23__device_stub__distancePfS_S_iS_
.size _Z8distancePfS_S_iS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nUsage: "
.size .L.str.1, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s %s %s %s"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%e %s %e %s %e %s"
.size .L.str.6, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%i\n"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%e "
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n%s\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "distances"
.size .L.str.11, 10
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%e\n"
.size .L.str.12, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8distancePfS_S_iS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nMust pass in cluster_data file on command line!"
.size .Lstr.1, 50
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " <cluster_data file> <distances file> \n"
.size .Lstr.2, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__distancePfS_S_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8distancePfS_S_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8distancePfS_S_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R20, c[0x0][0x178] ; /* 0x00005e0000147a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ IADD3 R2, R20, -0x1, RZ ; /* 0xffffffff14027810 */
/* 0x000fe20007ffe0ff */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e220000002100 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x000fe400078ec0ff */
/*00b0*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R18, R0, c[0x0][0x0], R19 ; /* 0x0000000000127a24 */
/* 0x001fc800078e0213 */
/*00d0*/ IMAD.WIDE R14, R18, R9, c[0x0][0x160] ; /* 0x00005800120e7625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R12, R18, R9, c[0x0][0x168] ; /* 0x00005a00120c7625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R10, R18, R9, c[0x0][0x170] ; /* 0x00005c00120a7625 */
/* 0x000fe200078e0209 */
/*0100*/ @!P0 BRA 0xa40 ; /* 0x0000093000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD R8, R18, c[0x0][0x178], RZ ; /* 0x00005e0012087a24 */
/* 0x000fe200078e02ff */
/*0120*/ IADD3 R26, -R20, c[0x0][0x178], RZ ; /* 0x00005e00141a7a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R27, -R18, RZ, RZ ; /* 0x000000ff121b7210 */
/* 0x000fe20007ffe1ff */
/*0150*/ IMAD.WIDE R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fe200078e0209 */
/*0160*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe40000000f00 */
/*01c0*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fe20003f05270 */
/*01d0*/ BSSY B0, 0x3a0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*01e0*/ @!P0 BRA 0x390 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0240*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0250*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000f22000c1e1900 */
/*0260*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0270*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0280*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0290*/ BSSY B1, 0x380 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*02a0*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*02b0*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*02c0*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*02f0*/ @!P0 BRA 0x330 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0300*/ MOV R16, 0x320 ; /* 0x0000032000107802 */
/* 0x003fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0xdc0 ; /* 0x00000aa000007944 */
/* 0x000fea0003c00000 */
/*0320*/ BRA 0x370 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0330*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0340*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0350*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0360*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ STG.E [R8.64], R22 ; /* 0x0000001608007986 */
/* 0x0001e4000c101904 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R17, R21, 0x1, RZ ; /* 0x0000000115117810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B0, 0x590 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.NE.AND P0, PT, R18, R17, PT ; /* 0x000000111200720c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 BRA 0x580 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R22, [R4.64+0x4] ; /* 0x0000040404167981 */
/* 0x001ea8000c1e1900 */
/*03f0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ee8000c1e1900 */
/*0420*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0430*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0440*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000f22000c1e1900 */
/*0450*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0460*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0470*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0480*/ BSSY B1, 0x570 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0490*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*04a0*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*04b0*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*04e0*/ @!P0 BRA 0x520 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*04f0*/ MOV R16, 0x510 ; /* 0x0000051000107802 */
/* 0x003fe40000000f00 */
/*0500*/ CALL.REL.NOINC 0xdc0 ; /* 0x000008b000007944 */
/* 0x000fea0003c00000 */
/*0510*/ BRA 0x560 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0520*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0530*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0540*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0550*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0560*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0570*/ STG.E [R8.64+0x4], R22 ; /* 0x0000041608007986 */
/* 0x0001e4000c101904 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ IADD3 R17, R21, 0x2, RZ ; /* 0x0000000215117810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ BSSY B0, 0x780 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*05b0*/ ISETP.NE.AND P0, PT, R18, R17, PT ; /* 0x000000111200720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x770 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080404167981 */
/* 0x001ea8000c1e1900 */
/*05e0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0600*/ LDG.E R17, [R6.64+0x8] ; /* 0x0000080406117981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0620*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0630*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f22000c1e1900 */
/*0640*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0650*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0660*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0670*/ BSSY B1, 0x760 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0680*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*0690*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*06a0*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*06c0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*06d0*/ @!P0 BRA 0x710 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R16, 0x700 ; /* 0x0000070000107802 */
/* 0x003fe40000000f00 */
/*06f0*/ CALL.REL.NOINC 0xdc0 ; /* 0x000006c000007944 */
/* 0x000fea0003c00000 */
/*0700*/ BRA 0x750 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0710*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0720*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0730*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0740*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ STG.E [R8.64+0x8], R22 ; /* 0x0000081608007986 */
/* 0x0001e4000c101904 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R17, R21, 0x3, RZ ; /* 0x0000000315117810 */
/* 0x000fe20007ffe0ff */
/*0790*/ BSSY B0, 0x970 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*07a0*/ ISETP.NE.AND P0, PT, R18, R17, PT ; /* 0x000000111200720c */
/* 0x000fda0003f05270 */
/*07b0*/ @!P0 BRA 0x960 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x001ea8000c1e1900 */
/*07d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000ee8000c1e1900 */
/*0800*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f22000c1e1900 */
/*0810*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x004fc60000000100 */
/*0820*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402177981 */
/* 0x000f22000c1e1900 */
/*0830*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0840*/ FMUL R17, R22, R22 ; /* 0x0000001616117220 */
/* 0x000fc80000400000 */
/*0850*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fe20000000011 */
/*0860*/ BSSY B1, 0x950 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0870*/ FADD R23, -R23, R24 ; /* 0x0000001817177221 */
/* 0x010fc80000000100 */
/*0880*/ FFMA R17, R23, R23, R16 ; /* 0x0000001717117223 */
/* 0x000fca0000000010 */
/*0890*/ IADD3 R16, R17, -0xd000000, RZ ; /* 0xf300000011107810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ MUFU.RSQ R24, R17 ; /* 0x0000001100187308 */
/* 0x0000660000001400 */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R16, 0x727fffff, PT ; /* 0x727fffff1000780c */
/* 0x000fda0003f04070 */
/*08c0*/ @!P0 BRA 0x900 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R16, 0x8f0 ; /* 0x000008f000107802 */
/* 0x003fe40000000f00 */
/*08e0*/ CALL.REL.NOINC 0xdc0 ; /* 0x000004d000007944 */
/* 0x000fea0003c00000 */
/*08f0*/ BRA 0x940 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0900*/ FMUL.FTZ R22, R17, R24 ; /* 0x0000001811167220 */
/* 0x003fe40000410000 */
/*0910*/ FMUL.FTZ R16, R24, 0.5 ; /* 0x3f00000018107820 */
/* 0x000fe40000410000 */
/*0920*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0930*/ FFMA R22, R17, R16, R22 ; /* 0x0000001011167223 */
/* 0x000fe40000000016 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ STG.E [R8.64+0xc], R22 ; /* 0x00000c1608007986 */
/* 0x0001e4000c101904 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fe40007ffe0ff */
/*0980*/ IADD3 R6, P4, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007f9e0ff */
/*0990*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f05270 */
/*09a0*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x001fe20007f3e0ff */
/*09b0*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*09c0*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007f5e0ff */
/*09d0*/ IADD3 R4, P3, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc40007f7e0ff */
/*09e0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40000ffe4ff */
/*09f0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0a00*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40001ffe4ff */
/*0a10*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*0a20*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fe20007ffe0ff */
/*0a30*/ @P0 BRA 0x1c0 ; /* 0xfffff78000000947 */
/* 0x000fea000383ffff */
/*0a40*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fda0003f05270 */
/*0a50*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a60*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0a70*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x000fe20007ffe1ff */
/*0a80*/ IMAD R6, R18, c[0x0][0x178], R21 ; /* 0x00005e0012067a24 */
/* 0x000fc800078e0215 */
/*0a90*/ IMAD R0, R0, c[0x0][0x0], R21 ; /* 0x0000000000007a24 */
/* 0x000fc800078e0215 */
/*0aa0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0208 */
/*0ab0*/ IADD3 R19, R0, -R19, RZ ; /* 0x8000001300137210 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ IMAD.WIDE R4, R21, R8, c[0x0][0x170] ; /* 0x00005c0015047625 */
/* 0x000fc800078e0208 */
/*0ad0*/ IMAD.WIDE R2, R21, R8, c[0x0][0x168] ; /* 0x00005a0015027625 */
/* 0x000fc800078e0208 */
/*0ae0*/ IMAD.WIDE R8, R21, R8, c[0x0][0x160] ; /* 0x0000580015087625 */
/* 0x000fca00078e0208 */
/*0af0*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe40000000f00 */
/*0b00*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f05270 */
/*0b10*/ BSSY B0, 0xcf0 ; /* 0x000001d000007945 */
/* 0x000fd80003800000 */
/*0b20*/ @!P0 BRA 0xce0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0b30*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe20000000f00 */
/*0b40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*0b50*/ LDG.E R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea8000c1e1900 */
/*0b60*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee8000c1e1900 */
/*0b70*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0b80*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000f28000c1e1900 */
/*0b90*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000f22000c1e1900 */
/*0ba0*/ BSSY B1, 0xcd0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0bb0*/ FADD R18, -R18, R21 ; /* 0x0000001512127221 */
/* 0x004fc40000000100 */
/*0bc0*/ FADD R16, R16, -R17 ; /* 0x8000001110107221 */
/* 0x008fe40000000000 */
/*0bd0*/ FMUL R17, R18, R18 ; /* 0x0000001212117220 */
/* 0x000fc80000400000 */
/*0be0*/ FFMA R17, R16, R16, R17 ; /* 0x0000001010117223 */
/* 0x000fe40000000011 */
/*0bf0*/ FADD R22, -R22, R23 ; /* 0x0000001716167221 */
/* 0x010fc80000000100 */
/*0c00*/ FFMA R17, R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000011 */
/*0c10*/ MUFU.RSQ R16, R17 ; /* 0x0000001100107308 */
/* 0x0000620000001400 */
/*0c20*/ IADD3 R8, R17, -0xd000000, RZ ; /* 0xf300000011087810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f04070 */
/*0c40*/ @!P0 BRA 0xc80 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0c50*/ MOV R16, 0xc70 ; /* 0x00000c7000107802 */
/* 0x003fe40000000f00 */
/*0c60*/ CALL.REL.NOINC 0xdc0 ; /* 0x0000015000007944 */
/* 0x000fea0003c00000 */
/*0c70*/ BRA 0xcc0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0c80*/ FMUL.FTZ R22, R17, R16 ; /* 0x0000001011167220 */
/* 0x003fe40000410000 */
/*0c90*/ FMUL.FTZ R8, R16, 0.5 ; /* 0x3f00000010087820 */
/* 0x000fe40000410000 */
/*0ca0*/ FFMA R17, -R22, R22, R17 ; /* 0x0000001616117223 */
/* 0x000fc80000000111 */
/*0cb0*/ FFMA R22, R17, R8, R22 ; /* 0x0000000811167223 */
/* 0x000fe40000000016 */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ STG.E [R6.64], R22 ; /* 0x0000001606007986 */
/* 0x0001e4000c101904 */
/*0ce0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0cf0*/ IADD3 R20, R20, -0x1, RZ ; /* 0xffffffff14147810 */
/* 0x000fe40007ffe0ff */
/*0d00*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007f5e0ff */
/*0d10*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f05270 */
/*0d20*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe20007f3e0ff */
/*0d30*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0d40*/ IADD3 R2, P3, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007f7e0ff */
/*0d50*/ IADD3 R0, P4, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc40007f9e0ff */
/*0d60*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0d80*/ IADD3.X R3, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff037210 */
/* 0x000fe40001ffe4ff */
/*0d90*/ IADD3.X R9, RZ, R9, RZ, P4, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200027fe4ff */
/*0da0*/ @P0 BRA 0xb00 ; /* 0xfffffd5000000947 */
/* 0x000fea000383ffff */
/*0db0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dc0*/ LOP3.LUT P0, RZ, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff11ff7812 */
/* 0x000fda000780c0ff */
/*0dd0*/ @!P0 MOV R22, R17 ; /* 0x0000001100168202 */
/* 0x000fe20000000f00 */
/*0de0*/ @!P0 BRA 0xef0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0df0*/ FSETP.GEU.FTZ.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720b */
/* 0x000fda0003f1e000 */
/*0e00*/ @!P0 MOV R22, 0x7fffffff ; /* 0x7fffffff00168802 */
/* 0x000fe20000000f00 */
/*0e10*/ @!P0 BRA 0xef0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0e20*/ FSETP.GTU.FTZ.AND P0, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */
/* 0x000fda0003f1c200 */
/*0e30*/ @P0 FADD.FTZ R22, R17, 1 ; /* 0x3f80000011160421 */
/* 0x000fe20000010000 */
/*0e40*/ @P0 BRA 0xef0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0e50*/ FSETP.NEU.FTZ.AND P0, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */
/* 0x000fda0003f1d200 */
/*0e60*/ @P0 FFMA R24, R17, 1.84467440737095516160e+19, RZ ; /* 0x5f80000011180823 */
/* 0x000fc800000000ff */
/*0e70*/ @P0 MUFU.RSQ R23, R24 ; /* 0x0000001800170308 */
/* 0x000e240000001400 */
/*0e80*/ @P0 FMUL.FTZ R22, R24, R23 ; /* 0x0000001718160220 */
/* 0x001fe40000410000 */
/*0e90*/ @P0 FMUL.FTZ R23, R23, 0.5 ; /* 0x3f00000017170820 */
/* 0x000fe40000410000 */
/*0ea0*/ @P0 FADD.FTZ R25, -R22, -RZ ; /* 0x800000ff16190221 */
/* 0x000fc80000010100 */
/*0eb0*/ @P0 FFMA R25, R22, R25, R24 ; /* 0x0000001916190223 */
/* 0x000fc80000000018 */
/*0ec0*/ @P0 FFMA R23, R25, R23, R22 ; /* 0x0000001719170223 */
/* 0x000fe20000000016 */
/*0ed0*/ @!P0 MOV R22, R17 ; /* 0x0000001100168202 */
/* 0x000fc60000000f00 */
/*0ee0*/ @P0 FMUL.FTZ R22, R23, 2.3283064365386962891e-10 ; /* 0x2f80000017160820 */
/* 0x000fe40000410000 */
/*0ef0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fcc00000001ff */
/*0f00*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff0f010007950 */
/* 0x000fea0003c3ffff */
/*0f10*/ BRA 0xf10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8distancePfS_S_iS_
.globl _Z8distancePfS_S_iS_
.p2align 8
.type _Z8distancePfS_S_iS_,@function
_Z8distancePfS_S_iS_:
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_mul_lo_u32 v2, v1, s10
v_add_co_u32 v4, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s10, s10, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
v_add_nc_u32_e32 v1, -1, v1
v_add_nc_u32_e32 v2, 1, v2
s_addc_u32 s7, s7, 0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_2
global_load_b32 v3, v[6:7], off
s_clause 0x1
global_load_b32 v10, v0, s[6:7]
global_load_b32 v11, v0, s[4:5]
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[8:9], off
global_load_b32 v14, v0, s[2:3]
s_waitcnt vmcnt(2)
v_dual_sub_f32 v3, v3, v10 :: v_dual_sub_f32 v10, v12, v11
s_waitcnt vmcnt(0)
v_sub_f32_e32 v11, v13, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v3
v_fmac_f32_e32 v3, v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v11, v11
v_mul_f32_e32 v10, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v12, v3, v10, vcc_lo
v_sqrt_f32_e32 v3, v12
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v11, 1, v3
v_add_nc_u32_e32 v10, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v11, v3, v12
v_fma_f32 v13, -v10, v3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v13
v_cndmask_b32_e64 v3, v3, v10, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v14
v_cndmask_b32_e64 v10, v3, v11, s0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x37800000, v10
v_cndmask_b32_e32 v13, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v12, 0x260
v_cndmask_b32_e32 v3, v13, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[10:11], v3, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8distancePfS_S_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8distancePfS_S_iS_, .Lfunc_end0-_Z8distancePfS_S_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8distancePfS_S_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8distancePfS_S_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007be93_00000000-6_CUDA_copy_coordinates_with_C.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
.type _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_, @function
_Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8distancePfS_S_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_, .-_Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
.globl _Z8distancePfS_S_iS_
.type _Z8distancePfS_S_iS_, @function
_Z8distancePfS_S_iS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8distancePfS_S_iS_, .-_Z8distancePfS_S_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nMust pass in cluster_data file on command line!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nUsage: "
.section .rodata.str1.8
.align 8
.LC2:
.string " <cluster_data file> <distances file> \n\n"
.section .rodata.str1.1
.LC3:
.string "r"
.LC4:
.string "%d"
.LC5:
.string "%s %s %s %s"
.LC6:
.string "%e %s %e %s %e %s"
.LC7:
.string "couldn't allocate memory\n"
.LC8:
.string "%i\n"
.LC9:
.string "%e "
.LC10:
.string "distances"
.LC11:
.string "\n%s\n"
.LC12:
.string "%e\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $648, %rsp
.cfi_def_cfa_offset 704
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 632(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L28
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r14
leaq 52(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 368(%rsp), %rcx
leaq 112(%rsp), %rdx
movq %rcx, %r9
movq %rdx, %r8
leaq .LC5(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 52(%rsp), %ebx
leal 0(,%rbx,4), %ebp
movslq %ebp, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 32(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
imull %ebp, %ebp
movslq %ebp, %rdx
movq %rdx, 8(%rsp)
movq %rdx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L13
movq 16(%rsp), %rbp
movl $0, %ebx
.L14:
leaq 368(%rsp), %rcx
pushq %rcx
.cfi_def_cfa_offset 712
pushq %rbp
.cfi_def_cfa_offset 720
movq %rcx, %r9
movq %r12, %r8
movq %r13, %rdx
leaq .LC6(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %r13
addq $4, %r12
addq $4, %rbp
addq $16, %rsp
.cfi_def_cfa_offset 704
cmpl %ebx, 52(%rsp)
jg .L14
.L13:
movl $1, 92(%rsp)
movl $1, 96(%rsp)
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
cmpq $0, 72(%rsp)
je .L15
cmpq $0, 64(%rsp)
je .L15
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L15
movq %r15, %rdx
movl $0, %esi
call cudaMemset@PLT
movq %r15, %rdx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movq %r15, %rdx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movq 8(%rsp), %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %r15, %rdx
movq 24(%rsp), %r12
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
testl %eax, %eax
jle .L18
movl $0, %ebx
leaq .LC9(%rip), %rbp
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L19
.L18:
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L20:
movl $2, %ecx
movq 8(%rsp), %rdx
movq 80(%rsp), %rsi
movq 40(%rsp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L21
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 52(%rsp), %eax
addq $1, %rbx
imull %eax, %eax
cmpl %ebx, %eax
jg .L22
.L21:
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 632(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L29:
movq 80(%rsp), %r8
movl 52(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z34__device_stub__Z8distancePfS_S_iS_PfS_S_iS_
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8distancePfS_S_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8distancePfS_S_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_copy_coordinates_with_C.hip"
.globl _Z23__device_stub__distancePfS_S_iS_ # -- Begin function _Z23__device_stub__distancePfS_S_iS_
.p2align 4, 0x90
.type _Z23__device_stub__distancePfS_S_iS_,@function
_Z23__device_stub__distancePfS_S_iS_: # @_Z23__device_stub__distancePfS_S_iS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8distancePfS_S_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__distancePfS_S_iS_, .Lfunc_end0-_Z23__device_stub__distancePfS_S_iS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $744, %rsp # imm = 0x2E8
.cfi_def_cfa_offset 800
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB1_18
# %bb.1:
movq 8(%rsi), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
leaq 4(%rsp), %rdx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 480(%rsp), %rdx
leaq 224(%rsp), %r15
movl $.L.str.5, %esi
movq %r14, %rdi
movq %r15, %rcx
movq %rdx, %r8
movq %r15, %r9
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
shll $2, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, 80(%rsp) # 8-byte Spill
movl %ebx, %edi
imull %edi, %edi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
cmpl $0, 4(%rsp)
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movq 64(%rsp), %rbx # 8-byte Reload
movq 40(%rsp), %r12 # 8-byte Reload
movq 32(%rsp), %r13 # 8-byte Reload
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %r15, %rcx
movq %r12, %r8
movq %r15, %r9
xorl %eax, %eax
pushq %r15
.cfi_adjust_cfa_offset 8
pushq %r13
.cfi_adjust_cfa_offset 8
callq __isoc23_fscanf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
incq %rbp
movslq 4(%rsp), %rax
addq $4, %r13
addq $4, %r12
addq $4, %rbx
cmpq %rax, %rbp
jl .LBB1_3
.LBB1_4: # %._crit_edge
leaq 24(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
cmpq $0, 8(%rsp)
je .LBB1_7
# %bb.5: # %._crit_edge
cmpq $0, 16(%rsp)
je .LBB1_7
# %bb.6: # %._crit_edge
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.8:
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 48(%rsp), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movq 24(%rsp), %rdi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 4(%rsp), %eax
testl %eax, %eax
movq 72(%rsp), %r15 # 8-byte Reload
jle .LBB1_11
# %bb.9: # %.lr.ph71.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph71
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge72
movl %eax, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl 4(%rsp), %esi
movq 48(%rsp), %rdi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 60(%rsp)
movq %rdi, 144(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z8distancePfS_S_iS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
movq 48(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
movl $.L.str.10, %edi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
je .LBB1_16
# %bb.14: # %.lr.ph75.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_15: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
incq %rbx
movl 4(%rsp), %eax
imull %eax, %eax
cmpq %rax, %rbx
jb .LBB1_15
.LBB1_16: # %._crit_edge76
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB1_17
.LBB1_7:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebp
.LBB1_17:
movl %ebp, %eax
addq $744, %rsp # imm = 0x2E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 800
movl $.Lstr.1, %edi
movq %rsi, %rbx
callq puts@PLT
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8distancePfS_S_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8distancePfS_S_iS_,@object # @_Z8distancePfS_S_iS_
.section .rodata,"a",@progbits
.globl _Z8distancePfS_S_iS_
.p2align 3, 0x0
_Z8distancePfS_S_iS_:
.quad _Z23__device_stub__distancePfS_S_iS_
.size _Z8distancePfS_S_iS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nUsage: "
.size .L.str.1, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s %s %s %s"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%e %s %e %s %e %s"
.size .L.str.6, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%i\n"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%e "
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n%s\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "distances"
.size .L.str.11, 10
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%e\n"
.size .L.str.12, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8distancePfS_S_iS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nMust pass in cluster_data file on command line!"
.size .Lstr.1, 50
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " <cluster_data file> <distances file> \n"
.size .Lstr.2, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__distancePfS_S_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8distancePfS_S_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define WIDTH 512
#define BLOCK_WIDTH 16
#define TILE_WIDTH 16
__global__
void matMulTiledKernel(float *d_M, float *d_N, float *d_P, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
int k, m;
float Pvalue = 0.0;
for(m=0;m<Width/TILE_WIDTH;++m){
Mds[ty][tx] = d_M[Row*Width+m*TILE_WIDTH+tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH+ty)*Width+Col];
__syncthreads();
for(k=0;k<TILE_WIDTH;k++) Pvalue += Mds[ty][k]*Nds[k][tx];
__syncthreads();
}
d_P[Row*Width+Col] = Pvalue;
}
void matMulDevice(float *h_M, float *h_N, float *h_P, int Width)
{
int size = Width * Width * sizeof(float);
float *d_M, *d_N, *d_P;
// Step 1: Allocate and Load M, N to device memory
cudaMalloc((void **)&d_M, size);
cudaMemcpy(d_M, h_M, size, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_N, size);
cudaMemcpy(d_N, h_N, size, cudaMemcpyHostToDevice);
// Step 2: Allocate P on the device
cudaMalloc((void **)&d_P, size);
// Step 3a: Set up execution configuration
int numBlocks = ceil(Width/(float)BLOCK_WIDTH);
dim3 dimGrid(numBlocks,numBlocks);
dim3 dimBlock(BLOCK_WIDTH, BLOCK_WIDTH);
// Step 3b: Launch the device computation threads!
matMulTiledKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, Width);
// Step 4: Copy back result, and free memory on device
cudaMemcpy(h_P, d_P, size, cudaMemcpyDeviceToHost);
cudaFree(d_M); cudaFree(d_N); cudaFree(d_P);
}
int main()
{
float *h_M, *h_N, *h_P;
int i, n = WIDTH, size=sizeof(float)*n*n;
h_P = (float *)malloc(size);
h_M = (float *)malloc(size);
h_N = (float *)malloc(size);
for(i=0;i<n*n;i++){*(h_M+i)=(float)i;
*(h_N+i)=(float)i;}
matMulDevice(h_M,h_N,h_P,n);
} | code for sm_80
Function : _Z17matMulTiledKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R5, R5, R17, 0x4 ; /* 0x0000001105057211 */
/* 0x001fc400078e20ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fca00078e20ff */
/*00c0*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4f0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R14, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e00050e7a24 */
/* 0x100fe200078e0200 */
/*0110*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe20000011413 */
/*0120*/ IMAD R4, R17.reuse, c[0x0][0x178], R0 ; /* 0x00005e0011047a24 */
/* 0x040fe200078e0200 */
/*0130*/ SHF.L.U32 R17, R17, 0x6, RZ ; /* 0x0000000611117819 */
/* 0x000fe200000006ff */
/*0140*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020d */
/*0150*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fc40000000f00 */
/*0190*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe200000006ff */
/*01a0*/ IMAD.WIDE R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*01c0*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fe400078e10ff */
/*01d0*/ SHF.R.S32.HI R15, RZ, 0x4, R5 ; /* 0x00000004ff0f7819 */
/* 0x000fe40000011405 */
/*01e0*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0002e2000c1e1900 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe20007f3e0ff */
/*0230*/ IMAD.WIDE R12, R19, 0x4, R12 ; /* 0x00000004130c7825 */
/* 0x001fc800078e020c */
/*0240*/ ISETP.LE.AND P0, PT, R15, UR4, PT ; /* 0x000000040f007c0c */
/* 0x000fe4000bf03270 */
/*0250*/ IADD3.X R21, RZ, R21, RZ, P1, !PT ; /* 0x00000015ff157210 */
/* 0x002fe20000ffe4ff */
/*0260*/ STS [R16+0x400], R24 ; /* 0x0004001810007388 */
/* 0x004fe80000000800 */
/*0270*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x008fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*02b0*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*02c0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02d0*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*02e0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0300*/ LDS R18, [R0.X4+0x540] ; /* 0x0005400000127984 */
/* 0x000f680000004800 */
/*0310*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f680000004800 */
/*0320*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R8, R26, R8, R23 ; /* 0x000000081a087223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0360*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0370*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fe40000000008 */
/*0380*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0390*/ FFMA R4, R25, R4, R22 ; /* 0x0000000419047223 */
/* 0x010fe40000000016 */
/*03a0*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*03b0*/ FFMA R4, R18, R5, R4 ; /* 0x0000000512047223 */
/* 0x020fe40000000004 */
/*03c0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*03d0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03e0*/ LDS R18, [R0.X4+0x6c0] ; /* 0x0006c00000127984 */
/* 0x000ee40000004800 */
/*03f0*/ FFMA R24, R20, R7, R4 ; /* 0x0000000714187223 */
/* 0x000fe40000000004 */
/*0400*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000f280000000c00 */
/*0420*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x001fc60000000018 */
/*0440*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000e280000004800 */
/*0450*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000e220000004800 */
/*0460*/ FFMA R9, R22, R9, R24 ; /* 0x0000000916097223 */
/* 0x002fc80000000018 */
/*0470*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x004fc80000000009 */
/*0480*/ FFMA R9, R18, R11, R9 ; /* 0x0000000b12097223 */
/* 0x008fc80000000009 */
/*0490*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x010fc80000000009 */
/*04a0*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fc80000000004 */
/*04b0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R23, R8, R7, R23 ; /* 0x0000000708177223 */
/* 0x000fe20000000017 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @!P0 BRA 0x1e0 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*04f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define WIDTH 512
#define BLOCK_WIDTH 16
#define TILE_WIDTH 16
__global__
void matMulTiledKernel(float *d_M, float *d_N, float *d_P, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
int k, m;
float Pvalue = 0.0;
for(m=0;m<Width/TILE_WIDTH;++m){
Mds[ty][tx] = d_M[Row*Width+m*TILE_WIDTH+tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH+ty)*Width+Col];
__syncthreads();
for(k=0;k<TILE_WIDTH;k++) Pvalue += Mds[ty][k]*Nds[k][tx];
__syncthreads();
}
d_P[Row*Width+Col] = Pvalue;
}
void matMulDevice(float *h_M, float *h_N, float *h_P, int Width)
{
int size = Width * Width * sizeof(float);
float *d_M, *d_N, *d_P;
// Step 1: Allocate and Load M, N to device memory
cudaMalloc((void **)&d_M, size);
cudaMemcpy(d_M, h_M, size, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_N, size);
cudaMemcpy(d_N, h_N, size, cudaMemcpyHostToDevice);
// Step 2: Allocate P on the device
cudaMalloc((void **)&d_P, size);
// Step 3a: Set up execution configuration
int numBlocks = ceil(Width/(float)BLOCK_WIDTH);
dim3 dimGrid(numBlocks,numBlocks);
dim3 dimBlock(BLOCK_WIDTH, BLOCK_WIDTH);
// Step 3b: Launch the device computation threads!
matMulTiledKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, Width);
// Step 4: Copy back result, and free memory on device
cudaMemcpy(h_P, d_P, size, cudaMemcpyDeviceToHost);
cudaFree(d_M); cudaFree(d_N); cudaFree(d_P);
}
int main()
{
float *h_M, *h_N, *h_P;
int i, n = WIDTH, size=sizeof(float)*n*n;
h_P = (float *)malloc(size);
h_M = (float *)malloc(size);
h_N = (float *)malloc(size);
for(i=0;i<n*n;i++){*(h_M+i)=(float)i;
*(h_N+i)=(float)i;}
matMulDevice(h_M,h_N,h_P,n);
} | .file "tmpxft_000c3398_00000000-6_matmulTiledCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matMulTiledKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
.globl _Z17matMulTiledKernelPfS_S_i
.type _Z17matMulTiledKernelPfS_S_i, @function
_Z17matMulTiledKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17matMulTiledKernelPfS_S_i, .-_Z17matMulTiledKernelPfS_S_i
.globl _Z12matMulDevicePfS_S_i
.type _Z12matMulDevicePfS_S_i, @function
_Z12matMulDevicePfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl %eax, 36(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12matMulDevicePfS_S_i, .-_Z12matMulDevicePfS_S_i
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %rsi
movl $0, %edx
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rdx,4)
movss %xmm0, (%rsi,%rdx,4)
addq $1, %rdx
cmpq $262144, %rdx
jne .L19
movl $512, %ecx
movq %rbp, %rdx
movq %rbx, %rdi
call _Z12matMulDevicePfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z17matMulTiledKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matMulTiledKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1031798784
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define WIDTH 512
#define BLOCK_WIDTH 16
#define TILE_WIDTH 16
__global__
void matMulTiledKernel(float *d_M, float *d_N, float *d_P, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
int k, m;
float Pvalue = 0.0;
for(m=0;m<Width/TILE_WIDTH;++m){
Mds[ty][tx] = d_M[Row*Width+m*TILE_WIDTH+tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH+ty)*Width+Col];
__syncthreads();
for(k=0;k<TILE_WIDTH;k++) Pvalue += Mds[ty][k]*Nds[k][tx];
__syncthreads();
}
d_P[Row*Width+Col] = Pvalue;
}
void matMulDevice(float *h_M, float *h_N, float *h_P, int Width)
{
int size = Width * Width * sizeof(float);
float *d_M, *d_N, *d_P;
// Step 1: Allocate and Load M, N to device memory
cudaMalloc((void **)&d_M, size);
cudaMemcpy(d_M, h_M, size, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_N, size);
cudaMemcpy(d_N, h_N, size, cudaMemcpyHostToDevice);
// Step 2: Allocate P on the device
cudaMalloc((void **)&d_P, size);
// Step 3a: Set up execution configuration
int numBlocks = ceil(Width/(float)BLOCK_WIDTH);
dim3 dimGrid(numBlocks,numBlocks);
dim3 dimBlock(BLOCK_WIDTH, BLOCK_WIDTH);
// Step 3b: Launch the device computation threads!
matMulTiledKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, Width);
// Step 4: Copy back result, and free memory on device
cudaMemcpy(h_P, d_P, size, cudaMemcpyDeviceToHost);
cudaFree(d_M); cudaFree(d_N); cudaFree(d_P);
}
int main()
{
float *h_M, *h_N, *h_P;
int i, n = WIDTH, size=sizeof(float)*n*n;
h_P = (float *)malloc(size);
h_M = (float *)malloc(size);
h_N = (float *)malloc(size);
for(i=0;i<n*n;i++){*(h_M+i)=(float)i;
*(h_N+i)=(float)i;}
matMulDevice(h_M,h_N,h_P,n);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define WIDTH 512
#define BLOCK_WIDTH 16
#define TILE_WIDTH 16
__global__
void matMulTiledKernel(float *d_M, float *d_N, float *d_P, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
int k, m;
float Pvalue = 0.0;
for(m=0;m<Width/TILE_WIDTH;++m){
Mds[ty][tx] = d_M[Row*Width+m*TILE_WIDTH+tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH+ty)*Width+Col];
__syncthreads();
for(k=0;k<TILE_WIDTH;k++) Pvalue += Mds[ty][k]*Nds[k][tx];
__syncthreads();
}
d_P[Row*Width+Col] = Pvalue;
}
void matMulDevice(float *h_M, float *h_N, float *h_P, int Width)
{
int size = Width * Width * sizeof(float);
float *d_M, *d_N, *d_P;
// Step 1: Allocate and Load M, N to device memory
hipMalloc((void **)&d_M, size);
hipMemcpy(d_M, h_M, size, hipMemcpyHostToDevice);
hipMalloc((void **)&d_N, size);
hipMemcpy(d_N, h_N, size, hipMemcpyHostToDevice);
// Step 2: Allocate P on the device
hipMalloc((void **)&d_P, size);
// Step 3a: Set up execution configuration
int numBlocks = ceil(Width/(float)BLOCK_WIDTH);
dim3 dimGrid(numBlocks,numBlocks);
dim3 dimBlock(BLOCK_WIDTH, BLOCK_WIDTH);
// Step 3b: Launch the device computation threads!
matMulTiledKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, Width);
// Step 4: Copy back result, and free memory on device
hipMemcpy(h_P, d_P, size, hipMemcpyDeviceToHost);
hipFree(d_M); hipFree(d_N); hipFree(d_P);
}
int main()
{
float *h_M, *h_N, *h_P;
int i, n = WIDTH, size=sizeof(float)*n*n;
h_P = (float *)malloc(size);
h_M = (float *)malloc(size);
h_N = (float *)malloc(size);
for(i=0;i<n*n;i++){*(h_M+i)=(float)i;
*(h_N+i)=(float)i;}
matMulDevice(h_M,h_N,h_P,n);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define WIDTH 512
#define BLOCK_WIDTH 16
#define TILE_WIDTH 16
__global__
void matMulTiledKernel(float *d_M, float *d_N, float *d_P, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
int k, m;
float Pvalue = 0.0;
for(m=0;m<Width/TILE_WIDTH;++m){
Mds[ty][tx] = d_M[Row*Width+m*TILE_WIDTH+tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH+ty)*Width+Col];
__syncthreads();
for(k=0;k<TILE_WIDTH;k++) Pvalue += Mds[ty][k]*Nds[k][tx];
__syncthreads();
}
d_P[Row*Width+Col] = Pvalue;
}
void matMulDevice(float *h_M, float *h_N, float *h_P, int Width)
{
int size = Width * Width * sizeof(float);
float *d_M, *d_N, *d_P;
// Step 1: Allocate and Load M, N to device memory
hipMalloc((void **)&d_M, size);
hipMemcpy(d_M, h_M, size, hipMemcpyHostToDevice);
hipMalloc((void **)&d_N, size);
hipMemcpy(d_N, h_N, size, hipMemcpyHostToDevice);
// Step 2: Allocate P on the device
hipMalloc((void **)&d_P, size);
// Step 3a: Set up execution configuration
int numBlocks = ceil(Width/(float)BLOCK_WIDTH);
dim3 dimGrid(numBlocks,numBlocks);
dim3 dimBlock(BLOCK_WIDTH, BLOCK_WIDTH);
// Step 3b: Launch the device computation threads!
matMulTiledKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, Width);
// Step 4: Copy back result, and free memory on device
hipMemcpy(h_P, d_P, size, hipMemcpyDeviceToHost);
hipFree(d_M); hipFree(d_N); hipFree(d_P);
}
int main()
{
float *h_M, *h_N, *h_P;
int i, n = WIDTH, size=sizeof(float)*n*n;
h_P = (float *)malloc(size);
h_M = (float *)malloc(size);
h_N = (float *)malloc(size);
for(i=0;i<n*n;i++){*(h_M+i)=(float)i;
*(h_N+i)=(float)i;}
matMulDevice(h_M,h_N,h_P,n);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matMulTiledKernelPfS_S_i
.globl _Z17matMulTiledKernelPfS_S_i
.p2align 8
.type _Z17matMulTiledKernelPfS_S_i,@function
_Z17matMulTiledKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 4
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_lg_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc1 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matMulTiledKernelPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matMulTiledKernelPfS_S_i, .Lfunc_end0-_Z17matMulTiledKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matMulTiledKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matMulTiledKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define WIDTH 512
#define BLOCK_WIDTH 16
#define TILE_WIDTH 16
__global__
void matMulTiledKernel(float *d_M, float *d_N, float *d_P, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by*TILE_WIDTH + ty;
int Col = bx*TILE_WIDTH + tx;
int k, m;
float Pvalue = 0.0;
for(m=0;m<Width/TILE_WIDTH;++m){
Mds[ty][tx] = d_M[Row*Width+m*TILE_WIDTH+tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH+ty)*Width+Col];
__syncthreads();
for(k=0;k<TILE_WIDTH;k++) Pvalue += Mds[ty][k]*Nds[k][tx];
__syncthreads();
}
d_P[Row*Width+Col] = Pvalue;
}
void matMulDevice(float *h_M, float *h_N, float *h_P, int Width)
{
int size = Width * Width * sizeof(float);
float *d_M, *d_N, *d_P;
// Step 1: Allocate and Load M, N to device memory
hipMalloc((void **)&d_M, size);
hipMemcpy(d_M, h_M, size, hipMemcpyHostToDevice);
hipMalloc((void **)&d_N, size);
hipMemcpy(d_N, h_N, size, hipMemcpyHostToDevice);
// Step 2: Allocate P on the device
hipMalloc((void **)&d_P, size);
// Step 3a: Set up execution configuration
int numBlocks = ceil(Width/(float)BLOCK_WIDTH);
dim3 dimGrid(numBlocks,numBlocks);
dim3 dimBlock(BLOCK_WIDTH, BLOCK_WIDTH);
// Step 3b: Launch the device computation threads!
matMulTiledKernel<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, Width);
// Step 4: Copy back result, and free memory on device
hipMemcpy(h_P, d_P, size, hipMemcpyDeviceToHost);
hipFree(d_M); hipFree(d_N); hipFree(d_P);
}
int main()
{
float *h_M, *h_N, *h_P;
int i, n = WIDTH, size=sizeof(float)*n*n;
h_P = (float *)malloc(size);
h_M = (float *)malloc(size);
h_N = (float *)malloc(size);
for(i=0;i<n*n;i++){*(h_M+i)=(float)i;
*(h_N+i)=(float)i;}
matMulDevice(h_M,h_N,h_P,n);
} | .text
.file "matmulTiledCUDA.hip"
.globl _Z32__device_stub__matMulTiledKernelPfS_S_i # -- Begin function _Z32__device_stub__matMulTiledKernelPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matMulTiledKernelPfS_S_i,@function
_Z32__device_stub__matMulTiledKernelPfS_S_i: # @_Z32__device_stub__matMulTiledKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matMulTiledKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__matMulTiledKernelPfS_S_i, .Lfunc_end0-_Z32__device_stub__matMulTiledKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12matMulDevicePfS_S_i
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.text
.globl _Z12matMulDevicePfS_S_i
.p2align 4, 0x90
.type _Z12matMulDevicePfS_S_i,@function
_Z12matMulDevicePfS_S_i: # @_Z12matMulDevicePfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cvtsi2ss %ebp, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matMulTiledKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12matMulDevicePfS_S_i, .Lfunc_end1-_Z12matMulDevicePfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rcx,4)
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $262144, %rcx # imm = 0x40000
jne .LBB2_1
# %bb.2:
movq %r14, %rdi
movq %rax, %rsi
movq %rbx, %rdx
movl $512, %ecx # imm = 0x200
callq _Z12matMulDevicePfS_S_i
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matMulTiledKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matMulTiledKernelPfS_S_i,@object # @_Z17matMulTiledKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17matMulTiledKernelPfS_S_i
.p2align 3, 0x0
_Z17matMulTiledKernelPfS_S_i:
.quad _Z32__device_stub__matMulTiledKernelPfS_S_i
.size _Z17matMulTiledKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17matMulTiledKernelPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matMulTiledKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matMulTiledKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17matMulTiledKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R5, R5, R17, 0x4 ; /* 0x0000001105057211 */
/* 0x001fc400078e20ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fca00078e20ff */
/*00c0*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4f0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R14, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e00050e7a24 */
/* 0x100fe200078e0200 */
/*0110*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe20000011413 */
/*0120*/ IMAD R4, R17.reuse, c[0x0][0x178], R0 ; /* 0x00005e0011047a24 */
/* 0x040fe200078e0200 */
/*0130*/ SHF.L.U32 R17, R17, 0x6, RZ ; /* 0x0000000611117819 */
/* 0x000fe200000006ff */
/*0140*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020d */
/*0150*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fc40000000f00 */
/*0190*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe200000006ff */
/*01a0*/ IMAD.WIDE R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*01c0*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fe400078e10ff */
/*01d0*/ SHF.R.S32.HI R15, RZ, 0x4, R5 ; /* 0x00000004ff0f7819 */
/* 0x000fe40000011405 */
/*01e0*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0002e2000c1e1900 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe20007f3e0ff */
/*0230*/ IMAD.WIDE R12, R19, 0x4, R12 ; /* 0x00000004130c7825 */
/* 0x001fc800078e020c */
/*0240*/ ISETP.LE.AND P0, PT, R15, UR4, PT ; /* 0x000000040f007c0c */
/* 0x000fe4000bf03270 */
/*0250*/ IADD3.X R21, RZ, R21, RZ, P1, !PT ; /* 0x00000015ff157210 */
/* 0x002fe20000ffe4ff */
/*0260*/ STS [R16+0x400], R24 ; /* 0x0004001810007388 */
/* 0x004fe80000000800 */
/*0270*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x008fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*02b0*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*02c0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02d0*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*02e0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0300*/ LDS R18, [R0.X4+0x540] ; /* 0x0005400000127984 */
/* 0x000f680000004800 */
/*0310*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f680000004800 */
/*0320*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R8, R26, R8, R23 ; /* 0x000000081a087223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0360*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0370*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fe40000000008 */
/*0380*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0390*/ FFMA R4, R25, R4, R22 ; /* 0x0000000419047223 */
/* 0x010fe40000000016 */
/*03a0*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*03b0*/ FFMA R4, R18, R5, R4 ; /* 0x0000000512047223 */
/* 0x020fe40000000004 */
/*03c0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*03d0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03e0*/ LDS R18, [R0.X4+0x6c0] ; /* 0x0006c00000127984 */
/* 0x000ee40000004800 */
/*03f0*/ FFMA R24, R20, R7, R4 ; /* 0x0000000714187223 */
/* 0x000fe40000000004 */
/*0400*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000f280000000c00 */
/*0420*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x001fc60000000018 */
/*0440*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000e280000004800 */
/*0450*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000e220000004800 */
/*0460*/ FFMA R9, R22, R9, R24 ; /* 0x0000000916097223 */
/* 0x002fc80000000018 */
/*0470*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x004fc80000000009 */
/*0480*/ FFMA R9, R18, R11, R9 ; /* 0x0000000b12097223 */
/* 0x008fc80000000009 */
/*0490*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x010fc80000000009 */
/*04a0*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fc80000000004 */
/*04b0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R23, R8, R7, R23 ; /* 0x0000000708177223 */
/* 0x000fe20000000017 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @!P0 BRA 0x1e0 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*04f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matMulTiledKernelPfS_S_i
.globl _Z17matMulTiledKernelPfS_S_i
.p2align 8
.type _Z17matMulTiledKernelPfS_S_i,@function
_Z17matMulTiledKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 4
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_lg_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc1 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matMulTiledKernelPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matMulTiledKernelPfS_S_i, .Lfunc_end0-_Z17matMulTiledKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matMulTiledKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matMulTiledKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3398_00000000-6_matmulTiledCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matMulTiledKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
.globl _Z17matMulTiledKernelPfS_S_i
.type _Z17matMulTiledKernelPfS_S_i, @function
_Z17matMulTiledKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17matMulTiledKernelPfS_S_i, .-_Z17matMulTiledKernelPfS_S_i
.globl _Z12matMulDevicePfS_S_i
.type _Z12matMulDevicePfS_S_i, @function
_Z12matMulDevicePfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl %eax, 36(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matMulTiledKernelPfS_S_iPfS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12matMulDevicePfS_S_i, .-_Z12matMulDevicePfS_S_i
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %rsi
movl $0, %edx
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rdx,4)
movss %xmm0, (%rsi,%rdx,4)
addq $1, %rdx
cmpq $262144, %rdx
jne .L19
movl $512, %ecx
movq %rbp, %rdx
movq %rbx, %rdi
call _Z12matMulDevicePfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z17matMulTiledKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matMulTiledKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1031798784
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmulTiledCUDA.hip"
.globl _Z32__device_stub__matMulTiledKernelPfS_S_i # -- Begin function _Z32__device_stub__matMulTiledKernelPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matMulTiledKernelPfS_S_i,@function
_Z32__device_stub__matMulTiledKernelPfS_S_i: # @_Z32__device_stub__matMulTiledKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matMulTiledKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__matMulTiledKernelPfS_S_i, .Lfunc_end0-_Z32__device_stub__matMulTiledKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12matMulDevicePfS_S_i
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.text
.globl _Z12matMulDevicePfS_S_i
.p2align 4, 0x90
.type _Z12matMulDevicePfS_S_i,@function
_Z12matMulDevicePfS_S_i: # @_Z12matMulDevicePfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cvtsi2ss %ebp, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matMulTiledKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12matMulDevicePfS_S_i, .Lfunc_end1-_Z12matMulDevicePfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rcx,4)
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $262144, %rcx # imm = 0x40000
jne .LBB2_1
# %bb.2:
movq %r14, %rdi
movq %rax, %rsi
movq %rbx, %rdx
movl $512, %ecx # imm = 0x200
callq _Z12matMulDevicePfS_S_i
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matMulTiledKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matMulTiledKernelPfS_S_i,@object # @_Z17matMulTiledKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17matMulTiledKernelPfS_S_i
.p2align 3, 0x0
_Z17matMulTiledKernelPfS_S_i:
.quad _Z32__device_stub__matMulTiledKernelPfS_S_i
.size _Z17matMulTiledKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17matMulTiledKernelPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matMulTiledKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matMulTiledKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // nlm algorithm using shared memory
// also uses transpose *cube
// furthermore uses transpose shared array
// if blockSize=16 or 32 then avoids bank conflicts
__global__ void nlmSharedT(float *out, const float *in, const float *cube,
const int N, const int M, const int window,
const float filtSigma){
const int blockSize = blockDim.x;
const int tid = threadIdx.x;
const int i = blockSize * blockIdx.x + tid; // which pixel, row major
const int winSize = window*window;
const int picSize = N*M;
float sum = 0;
float Dsum = 0;
float maxD = 0;
float tempOut = 0;
float D;
extern __shared__ float sh_mem[];
float *sh_in = &sh_mem[0];
float *sh_cubeSelf = &sh_mem[blockSize];
float *sh_cubeElse = &sh_mem[blockSize+ blockSize*winSize];
if( i >= N*M) return;
const float inI = in[i];
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeSelf[cubeLine*blockSize + tid] = cube[cubeLine*picSize + i];
}
int inIndex;
float temp;
for(int p=0; p<picSize/blockSize; p++){
//inIndex = (i+p*blockSize)%(picSize); // mod % to cycle arround to the start
inIndex = tid+p*blockSize; // this also works, every block starts from the same point
// sync before writing to make sure everyone has read
__syncthreads();
sh_in[tid] = in[inIndex];
//#pragma unroll 8
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeElse[cubeLine*blockSize + tid] = cube[cubeLine*picSize + inIndex];
}
// sync before reading to make sure everyone has writen
__syncthreads();
for(int j=0; j<blockSize; j++){
#pragma unroll 8
for(int k=0; k<winSize; k++){
temp = sh_cubeSelf[k*blockSize + tid]-sh_cubeElse[k*blockSize + j];
sum += temp*temp;
}
D = expf(-sum/filtSigma);
if(D!=1){
Dsum += D;
tempOut += D*sh_in[j];
if( D > maxD){
maxD = D;
}
}
sum = 0;
}
}
tempOut += maxD*inI;
Dsum += maxD;
out[i] = tempOut/Dsum;
} | .file "tmpxft_00028e35_00000000-6_justSharedT.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif
.type _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif, @function
_Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10nlmSharedTPfPKfS1_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif, .-_Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif
.globl _Z10nlmSharedTPfPKfS1_iiif
.type _Z10nlmSharedTPfPKfS1_iiif, @function
_Z10nlmSharedTPfPKfS1_iiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10nlmSharedTPfPKfS1_iiif, .-_Z10nlmSharedTPfPKfS1_iiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10nlmSharedTPfPKfS1_iiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10nlmSharedTPfPKfS1_iiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // nlm algorithm using shared memory
// also uses transpose *cube
// furthermore uses transpose shared array
// if blockSize=16 or 32 then avoids bank conflicts
__global__ void nlmSharedT(float *out, const float *in, const float *cube,
const int N, const int M, const int window,
const float filtSigma){
const int blockSize = blockDim.x;
const int tid = threadIdx.x;
const int i = blockSize * blockIdx.x + tid; // which pixel, row major
const int winSize = window*window;
const int picSize = N*M;
float sum = 0;
float Dsum = 0;
float maxD = 0;
float tempOut = 0;
float D;
extern __shared__ float sh_mem[];
float *sh_in = &sh_mem[0];
float *sh_cubeSelf = &sh_mem[blockSize];
float *sh_cubeElse = &sh_mem[blockSize+ blockSize*winSize];
if( i >= N*M) return;
const float inI = in[i];
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeSelf[cubeLine*blockSize + tid] = cube[cubeLine*picSize + i];
}
int inIndex;
float temp;
for(int p=0; p<picSize/blockSize; p++){
//inIndex = (i+p*blockSize)%(picSize); // mod % to cycle arround to the start
inIndex = tid+p*blockSize; // this also works, every block starts from the same point
// sync before writing to make sure everyone has read
__syncthreads();
sh_in[tid] = in[inIndex];
//#pragma unroll 8
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeElse[cubeLine*blockSize + tid] = cube[cubeLine*picSize + inIndex];
}
// sync before reading to make sure everyone has writen
__syncthreads();
for(int j=0; j<blockSize; j++){
#pragma unroll 8
for(int k=0; k<winSize; k++){
temp = sh_cubeSelf[k*blockSize + tid]-sh_cubeElse[k*blockSize + j];
sum += temp*temp;
}
D = expf(-sum/filtSigma);
if(D!=1){
Dsum += D;
tempOut += D*sh_in[j];
if( D > maxD){
maxD = D;
}
}
sum = 0;
}
}
tempOut += maxD*inI;
Dsum += maxD;
out[i] = tempOut/Dsum;
} | #include <hip/hip_runtime.h>
// nlm algorithm using shared memory
// also uses transpose *cube
// furthermore uses transpose shared array
// if blockSize=16 or 32 then avoids bank conflicts
__global__ void nlmSharedT(float *out, const float *in, const float *cube,
const int N, const int M, const int window,
const float filtSigma){
const int blockSize = blockDim.x;
const int tid = threadIdx.x;
const int i = blockSize * blockIdx.x + tid; // which pixel, row major
const int winSize = window*window;
const int picSize = N*M;
float sum = 0;
float Dsum = 0;
float maxD = 0;
float tempOut = 0;
float D;
extern __shared__ float sh_mem[];
float *sh_in = &sh_mem[0];
float *sh_cubeSelf = &sh_mem[blockSize];
float *sh_cubeElse = &sh_mem[blockSize+ blockSize*winSize];
if( i >= N*M) return;
const float inI = in[i];
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeSelf[cubeLine*blockSize + tid] = cube[cubeLine*picSize + i];
}
int inIndex;
float temp;
for(int p=0; p<picSize/blockSize; p++){
//inIndex = (i+p*blockSize)%(picSize); // mod % to cycle arround to the start
inIndex = tid+p*blockSize; // this also works, every block starts from the same point
// sync before writing to make sure everyone has read
__syncthreads();
sh_in[tid] = in[inIndex];
//#pragma unroll 8
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeElse[cubeLine*blockSize + tid] = cube[cubeLine*picSize + inIndex];
}
// sync before reading to make sure everyone has writen
__syncthreads();
for(int j=0; j<blockSize; j++){
#pragma unroll 8
for(int k=0; k<winSize; k++){
temp = sh_cubeSelf[k*blockSize + tid]-sh_cubeElse[k*blockSize + j];
sum += temp*temp;
}
D = expf(-sum/filtSigma);
if(D!=1){
Dsum += D;
tempOut += D*sh_in[j];
if( D > maxD){
maxD = D;
}
}
sum = 0;
}
}
tempOut += maxD*inI;
Dsum += maxD;
out[i] = tempOut/Dsum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// nlm algorithm using shared memory
// also uses transpose *cube
// furthermore uses transpose shared array
// if blockSize=16 or 32 then avoids bank conflicts
__global__ void nlmSharedT(float *out, const float *in, const float *cube,
const int N, const int M, const int window,
const float filtSigma){
const int blockSize = blockDim.x;
const int tid = threadIdx.x;
const int i = blockSize * blockIdx.x + tid; // which pixel, row major
const int winSize = window*window;
const int picSize = N*M;
float sum = 0;
float Dsum = 0;
float maxD = 0;
float tempOut = 0;
float D;
extern __shared__ float sh_mem[];
float *sh_in = &sh_mem[0];
float *sh_cubeSelf = &sh_mem[blockSize];
float *sh_cubeElse = &sh_mem[blockSize+ blockSize*winSize];
if( i >= N*M) return;
const float inI = in[i];
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeSelf[cubeLine*blockSize + tid] = cube[cubeLine*picSize + i];
}
int inIndex;
float temp;
for(int p=0; p<picSize/blockSize; p++){
//inIndex = (i+p*blockSize)%(picSize); // mod % to cycle arround to the start
inIndex = tid+p*blockSize; // this also works, every block starts from the same point
// sync before writing to make sure everyone has read
__syncthreads();
sh_in[tid] = in[inIndex];
//#pragma unroll 8
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeElse[cubeLine*blockSize + tid] = cube[cubeLine*picSize + inIndex];
}
// sync before reading to make sure everyone has writen
__syncthreads();
for(int j=0; j<blockSize; j++){
#pragma unroll 8
for(int k=0; k<winSize; k++){
temp = sh_cubeSelf[k*blockSize + tid]-sh_cubeElse[k*blockSize + j];
sum += temp*temp;
}
D = expf(-sum/filtSigma);
if(D!=1){
Dsum += D;
tempOut += D*sh_in[j];
if( D > maxD){
maxD = D;
}
}
sum = 0;
}
}
tempOut += maxD*inI;
Dsum += maxD;
out[i] = tempOut/Dsum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10nlmSharedTPfPKfS1_iiif
.globl _Z10nlmSharedTPfPKfS1_iiif
.p2align 8
.type _Z10nlmSharedTPfPKfS1_iiif,@function
_Z10nlmSharedTPfPKfS1_iiif:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s8, 0xffff
s_mul_i32 s3, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_23
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s11, s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_cmp_eq_u32 s11, 0
s_mul_i32 s20, s11, s11
global_load_b32 v6, v[3:4], off
s_cbranch_scc1 .LBB0_4
v_lshlrev_b32_e32 v3, 2, v0
s_and_b32 s8, 0xffff, s8
s_lshl_b32 s9, s2, 2
s_lshl_b32 s8, s8, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v5, 0, s8, v3
v_mov_b32_e32 v3, v1
s_max_u32 s8, s20, 1
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s8, s8, -1
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
v_add_nc_u32_e32 v5, s9, v5
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_cvt_f32_u32_e32 v3, s2
s_sub_i32 s9, 0, s2
s_ashr_i32 s10, s3, 31
v_mov_b32_e32 v9, 0
s_add_i32 s12, s3, s10
v_rcp_iflag_f32_e32 v3, v3
s_xor_b32 s12, s12, s10
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_readfirstlane_b32 s8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s2
s_sub_i32 s9, s12, s9
s_add_i32 s12, s8, 1
s_sub_i32 s13, s9, s2
s_cmp_ge_u32 s9, s2
s_cselect_b32 s8, s12, s8
s_cselect_b32 s9, s13, s9
s_add_i32 s12, s8, 1
s_cmp_ge_u32 s9, s2
s_mov_b32 s9, 0
s_cselect_b32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s8, s8, s10
s_sub_i32 s8, s8, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_22
s_add_i32 s10, s20, 1
s_load_b32 s15, s[0:1], 0x24
s_mul_i32 s10, s10, s2
v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_lshl_b32 s10, s10, 2
s_cmp_lg_u32 s11, 0
v_mov_b32_e32 v13, 0
s_cselect_b32 s11, -1, 0
s_max_u32 s12, s20, 1
s_max_u32 s13, s2, 1
s_and_b32 s14, s12, 5
s_cmp_gt_u32 s20, 7
v_add_nc_u32_e32 v10, 0, v3
s_cselect_b32 s16, -1, 0
s_and_b32 s17, s12, -8
s_cmp_lg_u32 s14, 0
v_add3_u32 v11, 0, s10, v3
s_cselect_b32 s18, -1, 0
s_lshl_b32 s19, s2, 2
v_dual_mov_b32 v14, v0 :: v_dual_mov_b32 v7, 0
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v12, s19, v3
s_lshl_b32 s21, s20, 2
s_lshl_b32 s20, s2, 5
s_add_i32 s21, s21, 4
s_branch .LBB0_7
.LBB0_6:
v_add_nc_u32_e32 v14, s2, v14
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_cbranch_scc1 .LBB0_22
.LBB0_7:
v_mad_u64_u32 v[4:5], null, s9, s2, v[0:1]
v_mov_b32_e32 v5, v13
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v15, v11
s_mov_b32 s22, s12
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s11
global_load_b32 v5, v[4:5], off
v_mov_b32_e32 v4, v14
s_waitcnt vmcnt(0)
ds_store_b32 v10, v5
s_cbranch_vccnz .LBB0_9
.LBB0_8:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s22, s22, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s22, 0
v_lshlrev_b64 v[16:17], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v16, vcc_lo, s6, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
global_load_b32 v5, v[16:17], off
s_waitcnt vmcnt(0)
ds_store_b32 v15, v5
v_add_nc_u32_e32 v15, s19, v15
s_cbranch_scc0 .LBB0_8
.LBB0_9:
s_mov_b32 s22, 0
s_mov_b32 s23, s10
s_mov_b32 s24, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s26
v_add_f32_e32 v8, v8, v4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v7, v4, v5
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s25
s_add_i32 s24, s24, 1
s_add_i32 s23, s23, 4
s_add_i32 s22, s22, 4
s_cmp_eq_u32 s24, s13
s_cbranch_scc1 .LBB0_6
.LBB0_12:
v_mov_b32_e32 v15, 0
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_19
s_mov_b32 s25, 0
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_16
s_mov_b32 s26, 0
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s27, s26, s23
v_dual_mov_b32 v5, s27 :: v_dual_add_nc_u32 v4, s26, v12
s_add_i32 s28, s27, s19
s_add_i32 s25, s25, 8
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v16, s28 :: v_dual_add_nc_u32 v17, s19, v4
ds_load_b32 v4, v4
ds_load_b32 v5, v5
s_add_i32 s27, s28, s19
s_add_i32 s26, s26, s20
v_mov_b32_e32 v18, s27
s_add_i32 s27, s27, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v19, s27
s_add_i32 s27, s27, s19
v_dual_mov_b32 v21, s27 :: v_dual_add_nc_u32 v20, s19, v17
ds_load_b32 v17, v17
ds_load_b32 v16, v16
s_add_i32 s27, s27, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s28, s27, s19
v_dual_mov_b32 v22, s27 :: v_dual_mov_b32 v23, s28
s_add_i32 s27, s28, s19
s_cmp_eq_u32 s17, s25
v_mov_b32_e32 v26, s27
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v17, v16
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v15, v4, v4
v_add_nc_u32_e32 v24, s19, v20
ds_load_b32 v20, v20
ds_load_b32 v18, v18
v_fmac_f32_e32 v15, v5, v5
v_add_nc_u32_e32 v25, s19, v24
ds_load_b32 v24, v24
ds_load_b32 v19, v19
v_add_nc_u32_e32 v27, s19, v25
ds_load_b32 v25, v25
ds_load_b32 v21, v21
s_waitcnt lgkmcnt(4)
v_sub_f32_e32 v18, v20, v18
v_add_nc_u32_e32 v16, s19, v27
ds_load_b32 v17, v27
ds_load_b32 v22, v22
ds_load_b32 v4, v23
ds_load_b32 v5, v26
v_fmac_f32_e32 v15, v18, v18
ds_load_b32 v20, v16
s_waitcnt lgkmcnt(7)
v_dual_sub_f32 v19, v24, v19 :: v_dual_add_nc_u32 v16, s19, v16
s_waitcnt lgkmcnt(5)
v_sub_f32_e32 v18, v25, v21
ds_load_b32 v16, v16
v_fmac_f32_e32 v15, v19, v19
s_waitcnt lgkmcnt(1)
v_dual_sub_f32 v17, v17, v22 :: v_dual_sub_f32 v4, v20, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v18, v18
v_fmac_f32_e32 v15, v17, v17
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v5, v16, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v4, v4
v_fmac_f32_e32 v15, v5, v5
s_cbranch_scc0 .LBB0_15
.LBB0_16:
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB0_19
s_lshl_b32 s25, s25, 2
s_mov_b32 s27, s14
s_add_i32 s26, s21, s25
s_add_i32 s25, s25, 4
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s2, s25, v[3:4]
s_mul_i32 s25, s2, s26
s_mov_b32 s26, 0
s_add_i32 s25, s22, s25
.LBB0_18:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s28, s26, s25
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v16, s28 :: v_dual_add_nc_u32 v5, s26, v4
s_add_i32 s27, s27, -1
s_add_i32 s26, s26, s19
s_cmp_lg_u32 s27, 0
ds_load_b32 v5, v5
ds_load_b32 v16, v16
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v5, v5, v16
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v15, v5, v5
s_cbranch_scc1 .LBB0_18
.LBB0_19:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, s15, s15, -v15
v_div_scale_f32 v17, vcc_lo, -v15, s15, -v15
s_mov_b32 s25, exec_lo
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v16, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v16, v5
v_mul_f32_e32 v16, v17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v18, -v4, v16, v17
v_fmac_f32_e32 v16, v18, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v16, v17
v_div_fmas_f32 v4, v4, v5, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v4, v4, s15, -v15
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v15, v4, 0x3fb8aa3b, -v5
v_rndne_f32_e32 v16, v5
v_fmac_f32_e32 v15, 0x32a5705f, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v16
v_add_f32_e32 v5, v5, v15
v_cvt_i32_f32_e32 v15, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v15
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
v_cmpx_neq_f32_e32 1.0, v4
s_cbranch_execz .LBB0_11
s_lshl_b32 s26, s24, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s26, s26, 0
v_mov_b32_e32 v5, s26
s_mov_b32 s26, exec_lo
ds_load_b32 v5, v5
v_cmpx_gt_f32_e32 v4, v9
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v9, v4
s_branch .LBB0_10
.LBB0_22:
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v6, v9
v_add_f32_e32 v3, v9, v8
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, v3, v3, v7
v_rcp_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v0, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v6, vcc_lo, v7, v3, v7
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v0, v5, v6
v_fmac_f32_e32 v5, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v5, v6
v_div_fmas_f32 v4, v0, v4, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, v3, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10nlmSharedTPfPKfS1_iiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10nlmSharedTPfPKfS1_iiif, .Lfunc_end0-_Z10nlmSharedTPfPKfS1_iiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10nlmSharedTPfPKfS1_iiif
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z10nlmSharedTPfPKfS1_iiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// nlm algorithm using shared memory
// also uses transpose *cube
// furthermore uses transpose shared array
// if blockSize=16 or 32 then avoids bank conflicts
__global__ void nlmSharedT(float *out, const float *in, const float *cube,
const int N, const int M, const int window,
const float filtSigma){
const int blockSize = blockDim.x;
const int tid = threadIdx.x;
const int i = blockSize * blockIdx.x + tid; // which pixel, row major
const int winSize = window*window;
const int picSize = N*M;
float sum = 0;
float Dsum = 0;
float maxD = 0;
float tempOut = 0;
float D;
extern __shared__ float sh_mem[];
float *sh_in = &sh_mem[0];
float *sh_cubeSelf = &sh_mem[blockSize];
float *sh_cubeElse = &sh_mem[blockSize+ blockSize*winSize];
if( i >= N*M) return;
const float inI = in[i];
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeSelf[cubeLine*blockSize + tid] = cube[cubeLine*picSize + i];
}
int inIndex;
float temp;
for(int p=0; p<picSize/blockSize; p++){
//inIndex = (i+p*blockSize)%(picSize); // mod % to cycle arround to the start
inIndex = tid+p*blockSize; // this also works, every block starts from the same point
// sync before writing to make sure everyone has read
__syncthreads();
sh_in[tid] = in[inIndex];
//#pragma unroll 8
for(int cubeLine=0; cubeLine < winSize; cubeLine++){
sh_cubeElse[cubeLine*blockSize + tid] = cube[cubeLine*picSize + inIndex];
}
// sync before reading to make sure everyone has writen
__syncthreads();
for(int j=0; j<blockSize; j++){
#pragma unroll 8
for(int k=0; k<winSize; k++){
temp = sh_cubeSelf[k*blockSize + tid]-sh_cubeElse[k*blockSize + j];
sum += temp*temp;
}
D = expf(-sum/filtSigma);
if(D!=1){
Dsum += D;
tempOut += D*sh_in[j];
if( D > maxD){
maxD = D;
}
}
sum = 0;
}
}
tempOut += maxD*inI;
Dsum += maxD;
out[i] = tempOut/Dsum;
} | .text
.file "justSharedT.hip"
.globl _Z25__device_stub__nlmSharedTPfPKfS1_iiif # -- Begin function _Z25__device_stub__nlmSharedTPfPKfS1_iiif
.p2align 4, 0x90
.type _Z25__device_stub__nlmSharedTPfPKfS1_iiif,@function
_Z25__device_stub__nlmSharedTPfPKfS1_iiif: # @_Z25__device_stub__nlmSharedTPfPKfS1_iiif
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10nlmSharedTPfPKfS1_iiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__nlmSharedTPfPKfS1_iiif, .Lfunc_end0-_Z25__device_stub__nlmSharedTPfPKfS1_iiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10nlmSharedTPfPKfS1_iiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10nlmSharedTPfPKfS1_iiif,@object # @_Z10nlmSharedTPfPKfS1_iiif
.section .rodata,"a",@progbits
.globl _Z10nlmSharedTPfPKfS1_iiif
.p2align 3, 0x0
_Z10nlmSharedTPfPKfS1_iiif:
.quad _Z25__device_stub__nlmSharedTPfPKfS1_iiif
.size _Z10nlmSharedTPfPKfS1_iiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10nlmSharedTPfPKfS1_iiif"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__nlmSharedTPfPKfS1_iiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10nlmSharedTPfPKfS1_iiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00028e35_00000000-6_justSharedT.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif
.type _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif, @function
_Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10nlmSharedTPfPKfS1_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif, .-_Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif
.globl _Z10nlmSharedTPfPKfS1_iiif
.type _Z10nlmSharedTPfPKfS1_iiif, @function
_Z10nlmSharedTPfPKfS1_iiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z10nlmSharedTPfPKfS1_iiifPfPKfS1_iiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10nlmSharedTPfPKfS1_iiif, .-_Z10nlmSharedTPfPKfS1_iiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10nlmSharedTPfPKfS1_iiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10nlmSharedTPfPKfS1_iiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "justSharedT.hip"
.globl _Z25__device_stub__nlmSharedTPfPKfS1_iiif # -- Begin function _Z25__device_stub__nlmSharedTPfPKfS1_iiif
.p2align 4, 0x90
.type _Z25__device_stub__nlmSharedTPfPKfS1_iiif,@function
_Z25__device_stub__nlmSharedTPfPKfS1_iiif: # @_Z25__device_stub__nlmSharedTPfPKfS1_iiif
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10nlmSharedTPfPKfS1_iiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__nlmSharedTPfPKfS1_iiif, .Lfunc_end0-_Z25__device_stub__nlmSharedTPfPKfS1_iiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10nlmSharedTPfPKfS1_iiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10nlmSharedTPfPKfS1_iiif,@object # @_Z10nlmSharedTPfPKfS1_iiif
.section .rodata,"a",@progbits
.globl _Z10nlmSharedTPfPKfS1_iiif
.p2align 3, 0x0
_Z10nlmSharedTPfPKfS1_iiif:
.quad _Z25__device_stub__nlmSharedTPfPKfS1_iiif
.size _Z10nlmSharedTPfPKfS1_iiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10nlmSharedTPfPKfS1_iiif"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__nlmSharedTPfPKfS1_iiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10nlmSharedTPfPKfS1_iiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
#define IDX2C(i, j, ld) ((j)*(ld)+(i))
#define SQR(x) ((x)*(x)) // x^2
__global__ void cutoff_log_kernel(double* device_array, double min_signal){
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
if (device_array[thread_id] < min_signal){
device_array[thread_id] = logf(min_signal);
}
else{
device_array[thread_id] = logf(device_array[thread_id]);
}
} | code for sm_80
Function : _Z17cutoff_log_kernelPdd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ BSSY B0, 0x430 ; /* 0x000003a000007945 */
/* 0x000fe20003800000 */
/*0090*/ DSETP.GEU.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a000400762a */
/* 0x004e1c0003f0e000 */
/*00a0*/ @!P0 BRA 0x270 ; /* 0x000001c000008947 */
/* 0x001fea0003800000 */
/*00b0*/ F2F.F32.F64 R0, R4 ; /* 0x0000000400007310 */
/* 0x000e220000301000 */
/*00c0*/ MOV R9, 0x3e055027 ; /* 0x3e05502700097802 */
/* 0x000fe40000000f00 */
/*00d0*/ FSETP.GEU.AND P1, PT, R0, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x001fc80003f2e000 */
/*00e0*/ FSEL R4, RZ, -23, P1 ; /* 0xc1b80000ff047808 */
/* 0x000fd20000800000 */
/*00f0*/ @!P1 FMUL R0, R0, 8388608 ; /* 0x4b00000000009820 */
/* 0x000fca0000400000 */
/*0100*/ IADD3 R6, R0.reuse, -0x3f2aaaab, RZ ; /* 0xc0d5555500067810 */
/* 0x040fe40007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x7f800000, PT ; /* 0x7f8000000000780c */
/* 0x000fe40003f06070 */
/*0120*/ LOP3.LUT R7, R6, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000006077812 */
/* 0x000fe400078ec0ff */
/*0130*/ FSETP.NEU.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720b */
/* 0x040fe40003f2d000 */
/*0140*/ IADD3 R6, R0, -R7, RZ ; /* 0x8000000700067210 */
/* 0x000fe40007ffe0ff */
/*0150*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e260000201400 */
/*0160*/ FADD R6, R6, -1 ; /* 0xbf80000006067421 */
/* 0x000fc40000000000 */
/*0170*/ @P0 MOV R5, 0x7f800000 ; /* 0x7f80000000050802 */
/* 0x000fe40000000f00 */
/*0180*/ FFMA R9, R6, -R9, 0.14084610342979431152 ; /* 0x3e1039f606097423 */
/* 0x000fc80000000809 */
/*0190*/ FFMA R9, R6, R9, -0.12148627638816833496 ; /* 0xbdf8cdcc06097423 */
/* 0x000fc80000000009 */
/*01a0*/ FFMA R9, R6.reuse, R9, 0.13980610668659210205 ; /* 0x3e0f295506097423 */
/* 0x040fe40000000009 */
/*01b0*/ FFMA R4, R7, 1.1920928955078125e-07, R4 ; /* 0x3400000007047823 */
/* 0x001fe40000000004 */
/*01c0*/ FFMA R9, R6, R9, -0.16684235632419586182 ; /* 0xbe2ad8b906097423 */
/* 0x000fc80000000009 */
/*01d0*/ FFMA R9, R6, R9, 0.20012299716472625732 ; /* 0x3e4ced0b06097423 */
/* 0x000fc80000000009 */
/*01e0*/ FFMA R9, R6, R9, -0.24999669194221496582 ; /* 0xbe7fff2206097423 */
/* 0x000fc80000000009 */
/*01f0*/ FFMA R9, R6, R9, 0.33333182334899902344 ; /* 0x3eaaaa7806097423 */
/* 0x000fc80000000009 */
/*0200*/ FFMA R9, R6, R9, -0.5 ; /* 0xbf00000006097423 */
/* 0x000fc80000000009 */
/*0210*/ FMUL R9, R6, R9 ; /* 0x0000000906097220 */
/* 0x000fc80000400000 */
/*0220*/ FFMA R9, R6, R9, R6 ; /* 0x0000000906097223 */
/* 0x000fc80000000006 */
/*0230*/ FFMA R4, R4, 0.69314718246459960938, R9 ; /* 0x3f31721804047823 */
/* 0x000fe40000000009 */
/*0240*/ @P0 FFMA R4, R0, R5, +INF ; /* 0x7f80000000040423 */
/* 0x000fca0000000005 */
/*0250*/ FSEL R4, R4, -INF , P1 ; /* 0xff80000004047808 */
/* 0x000fe20000800000 */
/*0260*/ BRA 0x420 ; /* 0x000001b000007947 */
/* 0x000fea0003800000 */
/*0270*/ F2F.F32.F64 R0, c[0x0][0x168] ; /* 0x00005a0000007b10 */
/* 0x000e220000301000 */
/*0280*/ MOV R7, 0x3e055027 ; /* 0x3e05502700077802 */
/* 0x000fe40000000f00 */
/*0290*/ FSETP.GEU.AND P1, PT, R0, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x001fda0003f2e000 */
/*02a0*/ @!P1 FMUL R0, R0, 8388608 ; /* 0x4b00000000009820 */
/* 0x000fca0000400000 */
/*02b0*/ IADD3 R4, R0.reuse, -0x3f2aaaab, RZ ; /* 0xc0d5555500047810 */
/* 0x040fe40007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x7f800000, PT ; /* 0x7f8000000000780c */
/* 0x000fe40003f06070 */
/*02d0*/ LOP3.LUT R5, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004057812 */
/* 0x000fc800078ec0ff */
/*02e0*/ IADD3 R4, R0, -R5, RZ ; /* 0x8000000500047210 */
/* 0x000fe40007ffe0ff */
/*02f0*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e260000201400 */
/*0300*/ FADD R6, R4, -1 ; /* 0xbf80000004067421 */
/* 0x000fe20000000000 */
/*0310*/ FSEL R4, RZ, -23, P1 ; /* 0xc1b80000ff047808 */
/* 0x000fe40000800000 */
/*0320*/ @P0 MOV R9, 0x7f800000 ; /* 0x7f80000000090802 */
/* 0x000fe20000000f00 */
/*0330*/ FFMA R7, R6, -R7, 0.14084610342979431152 ; /* 0x3e1039f606077423 */
/* 0x000fe20000000807 */
/*0340*/ FSETP.NEU.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fc60003f2d000 */
/*0350*/ FFMA R7, R6, R7, -0.12148627638816833496 ; /* 0xbdf8cdcc06077423 */
/* 0x000fc80000000007 */
/*0360*/ FFMA R7, R6.reuse, R7, 0.13980610668659210205 ; /* 0x3e0f295506077423 */
/* 0x040fe40000000007 */
/*0370*/ FFMA R4, R5, 1.1920928955078125e-07, R4 ; /* 0x3400000005047823 */
/* 0x001fe40000000004 */
/*0380*/ FFMA R7, R6, R7, -0.16684235632419586182 ; /* 0xbe2ad8b906077423 */
/* 0x000fc80000000007 */
/*0390*/ FFMA R7, R6, R7, 0.20012299716472625732 ; /* 0x3e4ced0b06077423 */
/* 0x000fc80000000007 */
/*03a0*/ FFMA R7, R6, R7, -0.24999669194221496582 ; /* 0xbe7fff2206077423 */
/* 0x000fc80000000007 */
/*03b0*/ FFMA R7, R6, R7, 0.33333182334899902344 ; /* 0x3eaaaa7806077423 */
/* 0x000fc80000000007 */
/*03c0*/ FFMA R7, R6, R7, -0.5 ; /* 0xbf00000006077423 */
/* 0x000fc80000000007 */
/*03d0*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x000fc80000400000 */
/*03e0*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*03f0*/ FFMA R4, R4, 0.69314718246459960938, R7 ; /* 0x3f31721804047823 */
/* 0x000fe40000000007 */
/*0400*/ @P0 FFMA R4, R0, R9, +INF ; /* 0x7f80000000040423 */
/* 0x000fca0000000009 */
/*0410*/ FSEL R4, R4, -INF , P1 ; /* 0xff80000004047808 */
/* 0x000fe40000800000 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x000e240000201800 */
/*0440*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define IDX2C(i, j, ld) ((j)*(ld)+(i))
#define SQR(x) ((x)*(x)) // x^2
__global__ void cutoff_log_kernel(double* device_array, double min_signal){
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
if (device_array[thread_id] < min_signal){
device_array[thread_id] = logf(min_signal);
}
else{
device_array[thread_id] = logf(device_array[thread_id]);
}
} | .file "tmpxft_0001ba2b_00000000-6_cutoff_log_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z17cutoff_log_kernelPddPdd
.type _Z38__device_stub__Z17cutoff_log_kernelPddPdd, @function
_Z38__device_stub__Z17cutoff_log_kernelPddPdd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17cutoff_log_kernelPdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z17cutoff_log_kernelPddPdd, .-_Z38__device_stub__Z17cutoff_log_kernelPddPdd
.globl _Z17cutoff_log_kernelPdd
.type _Z17cutoff_log_kernelPdd, @function
_Z17cutoff_log_kernelPdd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17cutoff_log_kernelPddPdd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cutoff_log_kernelPdd, .-_Z17cutoff_log_kernelPdd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cutoff_log_kernelPdd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cutoff_log_kernelPdd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define IDX2C(i, j, ld) ((j)*(ld)+(i))
#define SQR(x) ((x)*(x)) // x^2
__global__ void cutoff_log_kernel(double* device_array, double min_signal){
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
if (device_array[thread_id] < min_signal){
device_array[thread_id] = logf(min_signal);
}
else{
device_array[thread_id] = logf(device_array[thread_id]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define IDX2C(i, j, ld) ((j)*(ld)+(i))
#define SQR(x) ((x)*(x)) // x^2
__global__ void cutoff_log_kernel(double* device_array, double min_signal){
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
if (device_array[thread_id] < min_signal){
device_array[thread_id] = logf(min_signal);
}
else{
device_array[thread_id] = logf(device_array[thread_id]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define IDX2C(i, j, ld) ((j)*(ld)+(i))
#define SQR(x) ((x)*(x)) // x^2
__global__ void cutoff_log_kernel(double* device_array, double min_signal){
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
if (device_array[thread_id] < min_signal){
device_array[thread_id] = logf(min_signal);
}
else{
device_array[thread_id] = logf(device_array[thread_id]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cutoff_log_kernelPdd
.globl _Z17cutoff_log_kernelPdd
.p2align 8
.type _Z17cutoff_log_kernelPdd,@function
_Z17cutoff_log_kernelPdd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]
v_cndmask_b32_e64 v3, v3, s3, vcc_lo
v_cndmask_b32_e64 v2, v2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
v_log_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x3f317217, v2
v_cmp_gt_f32_e64 s0, 0x7f800000, |v2|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, 0x3f317217, -v3
v_fmamk_f32 v4, v2, 0x3377d1cf, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_cndmask_b32_e64 v2, v2, v3, s0
v_cndmask_b32_e64 v3, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v3
v_cvt_f64_f32_e32 v[2:3], v2
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cutoff_log_kernelPdd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cutoff_log_kernelPdd, .Lfunc_end0-_Z17cutoff_log_kernelPdd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cutoff_log_kernelPdd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cutoff_log_kernelPdd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define IDX2C(i, j, ld) ((j)*(ld)+(i))
#define SQR(x) ((x)*(x)) // x^2
__global__ void cutoff_log_kernel(double* device_array, double min_signal){
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
if (device_array[thread_id] < min_signal){
device_array[thread_id] = logf(min_signal);
}
else{
device_array[thread_id] = logf(device_array[thread_id]);
}
} | .text
.file "cutoff_log_kernel.hip"
.globl _Z32__device_stub__cutoff_log_kernelPdd # -- Begin function _Z32__device_stub__cutoff_log_kernelPdd
.p2align 4, 0x90
.type _Z32__device_stub__cutoff_log_kernelPdd,@function
_Z32__device_stub__cutoff_log_kernelPdd: # @_Z32__device_stub__cutoff_log_kernelPdd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17cutoff_log_kernelPdd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__cutoff_log_kernelPdd, .Lfunc_end0-_Z32__device_stub__cutoff_log_kernelPdd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cutoff_log_kernelPdd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cutoff_log_kernelPdd,@object # @_Z17cutoff_log_kernelPdd
.section .rodata,"a",@progbits
.globl _Z17cutoff_log_kernelPdd
.p2align 3, 0x0
_Z17cutoff_log_kernelPdd:
.quad _Z32__device_stub__cutoff_log_kernelPdd
.size _Z17cutoff_log_kernelPdd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cutoff_log_kernelPdd"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cutoff_log_kernelPdd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cutoff_log_kernelPdd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17cutoff_log_kernelPdd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ BSSY B0, 0x430 ; /* 0x000003a000007945 */
/* 0x000fe20003800000 */
/*0090*/ DSETP.GEU.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a000400762a */
/* 0x004e1c0003f0e000 */
/*00a0*/ @!P0 BRA 0x270 ; /* 0x000001c000008947 */
/* 0x001fea0003800000 */
/*00b0*/ F2F.F32.F64 R0, R4 ; /* 0x0000000400007310 */
/* 0x000e220000301000 */
/*00c0*/ MOV R9, 0x3e055027 ; /* 0x3e05502700097802 */
/* 0x000fe40000000f00 */
/*00d0*/ FSETP.GEU.AND P1, PT, R0, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x001fc80003f2e000 */
/*00e0*/ FSEL R4, RZ, -23, P1 ; /* 0xc1b80000ff047808 */
/* 0x000fd20000800000 */
/*00f0*/ @!P1 FMUL R0, R0, 8388608 ; /* 0x4b00000000009820 */
/* 0x000fca0000400000 */
/*0100*/ IADD3 R6, R0.reuse, -0x3f2aaaab, RZ ; /* 0xc0d5555500067810 */
/* 0x040fe40007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x7f800000, PT ; /* 0x7f8000000000780c */
/* 0x000fe40003f06070 */
/*0120*/ LOP3.LUT R7, R6, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000006077812 */
/* 0x000fe400078ec0ff */
/*0130*/ FSETP.NEU.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720b */
/* 0x040fe40003f2d000 */
/*0140*/ IADD3 R6, R0, -R7, RZ ; /* 0x8000000700067210 */
/* 0x000fe40007ffe0ff */
/*0150*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e260000201400 */
/*0160*/ FADD R6, R6, -1 ; /* 0xbf80000006067421 */
/* 0x000fc40000000000 */
/*0170*/ @P0 MOV R5, 0x7f800000 ; /* 0x7f80000000050802 */
/* 0x000fe40000000f00 */
/*0180*/ FFMA R9, R6, -R9, 0.14084610342979431152 ; /* 0x3e1039f606097423 */
/* 0x000fc80000000809 */
/*0190*/ FFMA R9, R6, R9, -0.12148627638816833496 ; /* 0xbdf8cdcc06097423 */
/* 0x000fc80000000009 */
/*01a0*/ FFMA R9, R6.reuse, R9, 0.13980610668659210205 ; /* 0x3e0f295506097423 */
/* 0x040fe40000000009 */
/*01b0*/ FFMA R4, R7, 1.1920928955078125e-07, R4 ; /* 0x3400000007047823 */
/* 0x001fe40000000004 */
/*01c0*/ FFMA R9, R6, R9, -0.16684235632419586182 ; /* 0xbe2ad8b906097423 */
/* 0x000fc80000000009 */
/*01d0*/ FFMA R9, R6, R9, 0.20012299716472625732 ; /* 0x3e4ced0b06097423 */
/* 0x000fc80000000009 */
/*01e0*/ FFMA R9, R6, R9, -0.24999669194221496582 ; /* 0xbe7fff2206097423 */
/* 0x000fc80000000009 */
/*01f0*/ FFMA R9, R6, R9, 0.33333182334899902344 ; /* 0x3eaaaa7806097423 */
/* 0x000fc80000000009 */
/*0200*/ FFMA R9, R6, R9, -0.5 ; /* 0xbf00000006097423 */
/* 0x000fc80000000009 */
/*0210*/ FMUL R9, R6, R9 ; /* 0x0000000906097220 */
/* 0x000fc80000400000 */
/*0220*/ FFMA R9, R6, R9, R6 ; /* 0x0000000906097223 */
/* 0x000fc80000000006 */
/*0230*/ FFMA R4, R4, 0.69314718246459960938, R9 ; /* 0x3f31721804047823 */
/* 0x000fe40000000009 */
/*0240*/ @P0 FFMA R4, R0, R5, +INF ; /* 0x7f80000000040423 */
/* 0x000fca0000000005 */
/*0250*/ FSEL R4, R4, -INF , P1 ; /* 0xff80000004047808 */
/* 0x000fe20000800000 */
/*0260*/ BRA 0x420 ; /* 0x000001b000007947 */
/* 0x000fea0003800000 */
/*0270*/ F2F.F32.F64 R0, c[0x0][0x168] ; /* 0x00005a0000007b10 */
/* 0x000e220000301000 */
/*0280*/ MOV R7, 0x3e055027 ; /* 0x3e05502700077802 */
/* 0x000fe40000000f00 */
/*0290*/ FSETP.GEU.AND P1, PT, R0, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x001fda0003f2e000 */
/*02a0*/ @!P1 FMUL R0, R0, 8388608 ; /* 0x4b00000000009820 */
/* 0x000fca0000400000 */
/*02b0*/ IADD3 R4, R0.reuse, -0x3f2aaaab, RZ ; /* 0xc0d5555500047810 */
/* 0x040fe40007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x7f800000, PT ; /* 0x7f8000000000780c */
/* 0x000fe40003f06070 */
/*02d0*/ LOP3.LUT R5, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004057812 */
/* 0x000fc800078ec0ff */
/*02e0*/ IADD3 R4, R0, -R5, RZ ; /* 0x8000000500047210 */
/* 0x000fe40007ffe0ff */
/*02f0*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e260000201400 */
/*0300*/ FADD R6, R4, -1 ; /* 0xbf80000004067421 */
/* 0x000fe20000000000 */
/*0310*/ FSEL R4, RZ, -23, P1 ; /* 0xc1b80000ff047808 */
/* 0x000fe40000800000 */
/*0320*/ @P0 MOV R9, 0x7f800000 ; /* 0x7f80000000090802 */
/* 0x000fe20000000f00 */
/*0330*/ FFMA R7, R6, -R7, 0.14084610342979431152 ; /* 0x3e1039f606077423 */
/* 0x000fe20000000807 */
/*0340*/ FSETP.NEU.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fc60003f2d000 */
/*0350*/ FFMA R7, R6, R7, -0.12148627638816833496 ; /* 0xbdf8cdcc06077423 */
/* 0x000fc80000000007 */
/*0360*/ FFMA R7, R6.reuse, R7, 0.13980610668659210205 ; /* 0x3e0f295506077423 */
/* 0x040fe40000000007 */
/*0370*/ FFMA R4, R5, 1.1920928955078125e-07, R4 ; /* 0x3400000005047823 */
/* 0x001fe40000000004 */
/*0380*/ FFMA R7, R6, R7, -0.16684235632419586182 ; /* 0xbe2ad8b906077423 */
/* 0x000fc80000000007 */
/*0390*/ FFMA R7, R6, R7, 0.20012299716472625732 ; /* 0x3e4ced0b06077423 */
/* 0x000fc80000000007 */
/*03a0*/ FFMA R7, R6, R7, -0.24999669194221496582 ; /* 0xbe7fff2206077423 */
/* 0x000fc80000000007 */
/*03b0*/ FFMA R7, R6, R7, 0.33333182334899902344 ; /* 0x3eaaaa7806077423 */
/* 0x000fc80000000007 */
/*03c0*/ FFMA R7, R6, R7, -0.5 ; /* 0xbf00000006077423 */
/* 0x000fc80000000007 */
/*03d0*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x000fc80000400000 */
/*03e0*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*03f0*/ FFMA R4, R4, 0.69314718246459960938, R7 ; /* 0x3f31721804047823 */
/* 0x000fe40000000007 */
/*0400*/ @P0 FFMA R4, R0, R9, +INF ; /* 0x7f80000000040423 */
/* 0x000fca0000000009 */
/*0410*/ FSEL R4, R4, -INF , P1 ; /* 0xff80000004047808 */
/* 0x000fe40000800000 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x000e240000201800 */
/*0440*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cutoff_log_kernelPdd
.globl _Z17cutoff_log_kernelPdd
.p2align 8
.type _Z17cutoff_log_kernelPdd,@function
_Z17cutoff_log_kernelPdd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]
v_cndmask_b32_e64 v3, v3, s3, vcc_lo
v_cndmask_b32_e64 v2, v2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
v_log_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x3f317217, v2
v_cmp_gt_f32_e64 s0, 0x7f800000, |v2|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, 0x3f317217, -v3
v_fmamk_f32 v4, v2, 0x3377d1cf, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_cndmask_b32_e64 v2, v2, v3, s0
v_cndmask_b32_e64 v3, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v3
v_cvt_f64_f32_e32 v[2:3], v2
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cutoff_log_kernelPdd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cutoff_log_kernelPdd, .Lfunc_end0-_Z17cutoff_log_kernelPdd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cutoff_log_kernelPdd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cutoff_log_kernelPdd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001ba2b_00000000-6_cutoff_log_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z17cutoff_log_kernelPddPdd
.type _Z38__device_stub__Z17cutoff_log_kernelPddPdd, @function
_Z38__device_stub__Z17cutoff_log_kernelPddPdd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17cutoff_log_kernelPdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z17cutoff_log_kernelPddPdd, .-_Z38__device_stub__Z17cutoff_log_kernelPddPdd
.globl _Z17cutoff_log_kernelPdd
.type _Z17cutoff_log_kernelPdd, @function
_Z17cutoff_log_kernelPdd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17cutoff_log_kernelPddPdd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cutoff_log_kernelPdd, .-_Z17cutoff_log_kernelPdd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cutoff_log_kernelPdd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cutoff_log_kernelPdd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cutoff_log_kernel.hip"
.globl _Z32__device_stub__cutoff_log_kernelPdd # -- Begin function _Z32__device_stub__cutoff_log_kernelPdd
.p2align 4, 0x90
.type _Z32__device_stub__cutoff_log_kernelPdd,@function
_Z32__device_stub__cutoff_log_kernelPdd: # @_Z32__device_stub__cutoff_log_kernelPdd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17cutoff_log_kernelPdd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__cutoff_log_kernelPdd, .Lfunc_end0-_Z32__device_stub__cutoff_log_kernelPdd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cutoff_log_kernelPdd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cutoff_log_kernelPdd,@object # @_Z17cutoff_log_kernelPdd
.section .rodata,"a",@progbits
.globl _Z17cutoff_log_kernelPdd
.p2align 3, 0x0
_Z17cutoff_log_kernelPdd:
.quad _Z32__device_stub__cutoff_log_kernelPdd
.size _Z17cutoff_log_kernelPdd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cutoff_log_kernelPdd"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cutoff_log_kernelPdd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cutoff_log_kernelPdd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes, system
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
//WORKSHOP: Change this function to a CUDA kernel
void fillArray(int *data, int N)
{
int i;
for( i = 0; i < N; i++)
{
data[i] = i;
}
}
__global__ void fillArray(int *data, int *res)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
res[idx] = data[idx]+idx;
}
__global__ void fillArrayUnified(int *data )
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
data[idx] = data[idx]+idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
//WORKSHOP: Declare data pointers for host and device arrays
// (not necessary if using Unified memory)
int *data;
int i;
const int N = 100;
/*-----------------------------------------*/
// allocate host memory
//data = ( int* ) malloc(N * sizeof(int));
////WORKSHOP: Allocate device memory
//// Remove the host allocation above and use cudaMallocManaged()
//// to allocate on host and device if using unified memory
////Fill the array
////WORKSHOP: Change this function call to a CUDA kernel call
//int *d_data;
//cudaMalloc(&d_data, sizeof(int)*N);
//int *d_res;
//cudaMalloc(&d_res, sizeof(int)*N);
//cudaMemcpy(d_data, data, sizeof(int)*N, cudaMemcpyHostToDevice);
////int blockSize=10;
//fillArray<<<10,10>>>(d_data, d_res);
//cudaMemcpy(data, d_res, sizeof(float)*N, cudaMemcpyDeviceToHost);
//cudaFree(d_res);
//cudaFree(d_data);
/*-----------Unified memory-----------*/
cudaMallocManaged(&data, sizeof(int)*N);
fillArrayUnified<<<10,10>>>(data );
cudaDeviceSynchronize();
//WORKSHOP: Make sure the device has finished
//WORKSHOP: Copy the results to the host
// (not necessary if using unified memory)
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
//Free by cuda
cudaFree(data);
//WORKSHOP: Free the device memory
// (if using unified memory, you can free the host and device
// memory with one cudaFree() call)
return 0;
} | code for sm_80
Function : _Z16fillArrayUnifiedPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9fillArrayPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0205 */
/*0090*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes, system
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
//WORKSHOP: Change this function to a CUDA kernel
void fillArray(int *data, int N)
{
int i;
for( i = 0; i < N; i++)
{
data[i] = i;
}
}
__global__ void fillArray(int *data, int *res)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
res[idx] = data[idx]+idx;
}
__global__ void fillArrayUnified(int *data )
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
data[idx] = data[idx]+idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
//WORKSHOP: Declare data pointers for host and device arrays
// (not necessary if using Unified memory)
int *data;
int i;
const int N = 100;
/*-----------------------------------------*/
// allocate host memory
//data = ( int* ) malloc(N * sizeof(int));
////WORKSHOP: Allocate device memory
//// Remove the host allocation above and use cudaMallocManaged()
//// to allocate on host and device if using unified memory
////Fill the array
////WORKSHOP: Change this function call to a CUDA kernel call
//int *d_data;
//cudaMalloc(&d_data, sizeof(int)*N);
//int *d_res;
//cudaMalloc(&d_res, sizeof(int)*N);
//cudaMemcpy(d_data, data, sizeof(int)*N, cudaMemcpyHostToDevice);
////int blockSize=10;
//fillArray<<<10,10>>>(d_data, d_res);
//cudaMemcpy(data, d_res, sizeof(float)*N, cudaMemcpyDeviceToHost);
//cudaFree(d_res);
//cudaFree(d_data);
/*-----------Unified memory-----------*/
cudaMallocManaged(&data, sizeof(int)*N);
fillArrayUnified<<<10,10>>>(data );
cudaDeviceSynchronize();
//WORKSHOP: Make sure the device has finished
//WORKSHOP: Copy the results to the host
// (not necessary if using unified memory)
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
//Free by cuda
cudaFree(data);
//WORKSHOP: Free the device memory
// (if using unified memory, you can free the host and device
// memory with one cudaFree() call)
return 0;
} | .file "tmpxft_0007fa53_00000000-6_integers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9fillArrayPii
.type _Z9fillArrayPii, @function
_Z9fillArrayPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9fillArrayPii, .-_Z9fillArrayPii
.globl _Z30__device_stub__Z9fillArrayPiS_PiS_
.type _Z30__device_stub__Z9fillArrayPiS_PiS_, @function
_Z30__device_stub__Z9fillArrayPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fillArrayPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9fillArrayPiS_PiS_, .-_Z30__device_stub__Z9fillArrayPiS_PiS_
.globl _Z9fillArrayPiS_
.type _Z9fillArrayPiS_, @function
_Z9fillArrayPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9fillArrayPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9fillArrayPiS_, .-_Z9fillArrayPiS_
.globl _Z36__device_stub__Z16fillArrayUnifiedPiPi
.type _Z36__device_stub__Z16fillArrayUnifiedPiPi, @function
_Z36__device_stub__Z16fillArrayUnifiedPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16fillArrayUnifiedPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z16fillArrayUnifiedPiPi, .-_Z36__device_stub__Z16fillArrayUnifiedPiPi
.globl _Z16fillArrayUnifiedPi
.type _Z16fillArrayUnifiedPi, @function
_Z16fillArrayUnifiedPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16fillArrayUnifiedPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z16fillArrayUnifiedPi, .-_Z16fillArrayUnifiedPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L24:
call cudaDeviceSynchronize@PLT
movl $100, %eax
.L25:
subl $1, %eax
jne .L25
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z36__device_stub__Z16fillArrayUnifiedPiPi
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z16fillArrayUnifiedPi"
.LC2:
.string "_Z9fillArrayPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16fillArrayUnifiedPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fillArrayPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes, system
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
//WORKSHOP: Change this function to a CUDA kernel
void fillArray(int *data, int N)
{
int i;
for( i = 0; i < N; i++)
{
data[i] = i;
}
}
__global__ void fillArray(int *data, int *res)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
res[idx] = data[idx]+idx;
}
__global__ void fillArrayUnified(int *data )
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
data[idx] = data[idx]+idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
//WORKSHOP: Declare data pointers for host and device arrays
// (not necessary if using Unified memory)
int *data;
int i;
const int N = 100;
/*-----------------------------------------*/
// allocate host memory
//data = ( int* ) malloc(N * sizeof(int));
////WORKSHOP: Allocate device memory
//// Remove the host allocation above and use cudaMallocManaged()
//// to allocate on host and device if using unified memory
////Fill the array
////WORKSHOP: Change this function call to a CUDA kernel call
//int *d_data;
//cudaMalloc(&d_data, sizeof(int)*N);
//int *d_res;
//cudaMalloc(&d_res, sizeof(int)*N);
//cudaMemcpy(d_data, data, sizeof(int)*N, cudaMemcpyHostToDevice);
////int blockSize=10;
//fillArray<<<10,10>>>(d_data, d_res);
//cudaMemcpy(data, d_res, sizeof(float)*N, cudaMemcpyDeviceToHost);
//cudaFree(d_res);
//cudaFree(d_data);
/*-----------Unified memory-----------*/
cudaMallocManaged(&data, sizeof(int)*N);
fillArrayUnified<<<10,10>>>(data );
cudaDeviceSynchronize();
//WORKSHOP: Make sure the device has finished
//WORKSHOP: Copy the results to the host
// (not necessary if using unified memory)
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
//Free by cuda
cudaFree(data);
//WORKSHOP: Free the device memory
// (if using unified memory, you can free the host and device
// memory with one cudaFree() call)
return 0;
} | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
//WORKSHOP: Change this function to a CUDA kernel
void fillArray(int *data, int N)
{
int i;
for( i = 0; i < N; i++)
{
data[i] = i;
}
}
__global__ void fillArray(int *data, int *res)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
res[idx] = data[idx]+idx;
}
__global__ void fillArrayUnified(int *data )
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
data[idx] = data[idx]+idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
//WORKSHOP: Declare data pointers for host and device arrays
// (not necessary if using Unified memory)
int *data;
int i;
const int N = 100;
/*-----------------------------------------*/
// allocate host memory
//data = ( int* ) malloc(N * sizeof(int));
////WORKSHOP: Allocate device memory
//// Remove the host allocation above and use cudaMallocManaged()
//// to allocate on host and device if using unified memory
////Fill the array
////WORKSHOP: Change this function call to a CUDA kernel call
//int *d_data;
//cudaMalloc(&d_data, sizeof(int)*N);
//int *d_res;
//cudaMalloc(&d_res, sizeof(int)*N);
//cudaMemcpy(d_data, data, sizeof(int)*N, cudaMemcpyHostToDevice);
////int blockSize=10;
//fillArray<<<10,10>>>(d_data, d_res);
//cudaMemcpy(data, d_res, sizeof(float)*N, cudaMemcpyDeviceToHost);
//cudaFree(d_res);
//cudaFree(d_data);
/*-----------Unified memory-----------*/
hipMallocManaged(&data, sizeof(int)*N);
fillArrayUnified<<<10,10>>>(data );
hipDeviceSynchronize();
//WORKSHOP: Make sure the device has finished
//WORKSHOP: Copy the results to the host
// (not necessary if using unified memory)
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
//Free by cuda
hipFree(data);
//WORKSHOP: Free the device memory
// (if using unified memory, you can free the host and device
// memory with one cudaFree() call)
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
//WORKSHOP: Change this function to a CUDA kernel
void fillArray(int *data, int N)
{
int i;
for( i = 0; i < N; i++)
{
data[i] = i;
}
}
__global__ void fillArray(int *data, int *res)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
res[idx] = data[idx]+idx;
}
__global__ void fillArrayUnified(int *data )
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
data[idx] = data[idx]+idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
//WORKSHOP: Declare data pointers for host and device arrays
// (not necessary if using Unified memory)
int *data;
int i;
const int N = 100;
/*-----------------------------------------*/
// allocate host memory
//data = ( int* ) malloc(N * sizeof(int));
////WORKSHOP: Allocate device memory
//// Remove the host allocation above and use cudaMallocManaged()
//// to allocate on host and device if using unified memory
////Fill the array
////WORKSHOP: Change this function call to a CUDA kernel call
//int *d_data;
//cudaMalloc(&d_data, sizeof(int)*N);
//int *d_res;
//cudaMalloc(&d_res, sizeof(int)*N);
//cudaMemcpy(d_data, data, sizeof(int)*N, cudaMemcpyHostToDevice);
////int blockSize=10;
//fillArray<<<10,10>>>(d_data, d_res);
//cudaMemcpy(data, d_res, sizeof(float)*N, cudaMemcpyDeviceToHost);
//cudaFree(d_res);
//cudaFree(d_data);
/*-----------Unified memory-----------*/
hipMallocManaged(&data, sizeof(int)*N);
fillArrayUnified<<<10,10>>>(data );
hipDeviceSynchronize();
//WORKSHOP: Make sure the device has finished
//WORKSHOP: Copy the results to the host
// (not necessary if using unified memory)
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
//Free by cuda
hipFree(data);
//WORKSHOP: Free the device memory
// (if using unified memory, you can free the host and device
// memory with one cudaFree() call)
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9fillArrayPiS_
.globl _Z9fillArrayPiS_
.p2align 8
.type _Z9fillArrayPiS_,@function
_Z9fillArrayPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9fillArrayPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9fillArrayPiS_, .Lfunc_end0-_Z9fillArrayPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16fillArrayUnifiedPi
.globl _Z16fillArrayUnifiedPi
.p2align 8
.type _Z16fillArrayUnifiedPi,@function
_Z16fillArrayUnifiedPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16fillArrayUnifiedPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16fillArrayUnifiedPi, .Lfunc_end1-_Z16fillArrayUnifiedPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9fillArrayPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9fillArrayPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16fillArrayUnifiedPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16fillArrayUnifiedPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
//WORKSHOP: Change this function to a CUDA kernel
void fillArray(int *data, int N)
{
int i;
for( i = 0; i < N; i++)
{
data[i] = i;
}
}
__global__ void fillArray(int *data, int *res)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
res[idx] = data[idx]+idx;
}
__global__ void fillArrayUnified(int *data )
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
data[idx] = data[idx]+idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
//WORKSHOP: Declare data pointers for host and device arrays
// (not necessary if using Unified memory)
int *data;
int i;
const int N = 100;
/*-----------------------------------------*/
// allocate host memory
//data = ( int* ) malloc(N * sizeof(int));
////WORKSHOP: Allocate device memory
//// Remove the host allocation above and use cudaMallocManaged()
//// to allocate on host and device if using unified memory
////Fill the array
////WORKSHOP: Change this function call to a CUDA kernel call
//int *d_data;
//cudaMalloc(&d_data, sizeof(int)*N);
//int *d_res;
//cudaMalloc(&d_res, sizeof(int)*N);
//cudaMemcpy(d_data, data, sizeof(int)*N, cudaMemcpyHostToDevice);
////int blockSize=10;
//fillArray<<<10,10>>>(d_data, d_res);
//cudaMemcpy(data, d_res, sizeof(float)*N, cudaMemcpyDeviceToHost);
//cudaFree(d_res);
//cudaFree(d_data);
/*-----------Unified memory-----------*/
hipMallocManaged(&data, sizeof(int)*N);
fillArrayUnified<<<10,10>>>(data );
hipDeviceSynchronize();
//WORKSHOP: Make sure the device has finished
//WORKSHOP: Copy the results to the host
// (not necessary if using unified memory)
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
//Free by cuda
hipFree(data);
//WORKSHOP: Free the device memory
// (if using unified memory, you can free the host and device
// memory with one cudaFree() call)
return 0;
} | .text
.file "integers.hip"
.globl _Z9fillArrayPii # -- Begin function _Z9fillArrayPii
.p2align 4, 0x90
.type _Z9fillArrayPii,@function
_Z9fillArrayPii: # @_Z9fillArrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9fillArrayPii, .Lfunc_end0-_Z9fillArrayPii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__fillArrayPiS_ # -- Begin function _Z24__device_stub__fillArrayPiS_
.p2align 4, 0x90
.type _Z24__device_stub__fillArrayPiS_,@function
_Z24__device_stub__fillArrayPiS_: # @_Z24__device_stub__fillArrayPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9fillArrayPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__fillArrayPiS_, .Lfunc_end1-_Z24__device_stub__fillArrayPiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__fillArrayUnifiedPi # -- Begin function _Z31__device_stub__fillArrayUnifiedPi
.p2align 4, 0x90
.type _Z31__device_stub__fillArrayUnifiedPi,@function
_Z31__device_stub__fillArrayUnifiedPi: # @_Z31__device_stub__fillArrayUnifiedPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16fillArrayUnifiedPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z31__device_stub__fillArrayUnifiedPi, .Lfunc_end2-_Z31__device_stub__fillArrayUnifiedPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
movl $1, %edx
callq hipMallocManaged
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16fillArrayUnifiedPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fillArrayPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16fillArrayUnifiedPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fillArrayPiS_,@object # @_Z9fillArrayPiS_
.section .rodata,"a",@progbits
.globl _Z9fillArrayPiS_
.p2align 3, 0x0
_Z9fillArrayPiS_:
.quad _Z24__device_stub__fillArrayPiS_
.size _Z9fillArrayPiS_, 8
.type _Z16fillArrayUnifiedPi,@object # @_Z16fillArrayUnifiedPi
.globl _Z16fillArrayUnifiedPi
.p2align 3, 0x0
_Z16fillArrayUnifiedPi:
.quad _Z31__device_stub__fillArrayUnifiedPi
.size _Z16fillArrayUnifiedPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9fillArrayPiS_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16fillArrayUnifiedPi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fillArrayPiS_
.addrsig_sym _Z31__device_stub__fillArrayUnifiedPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fillArrayPiS_
.addrsig_sym _Z16fillArrayUnifiedPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16fillArrayUnifiedPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9fillArrayPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0205 */
/*0090*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9fillArrayPiS_
.globl _Z9fillArrayPiS_
.p2align 8
.type _Z9fillArrayPiS_,@function
_Z9fillArrayPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9fillArrayPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9fillArrayPiS_, .Lfunc_end0-_Z9fillArrayPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16fillArrayUnifiedPi
.globl _Z16fillArrayUnifiedPi
.p2align 8
.type _Z16fillArrayUnifiedPi,@function
_Z16fillArrayUnifiedPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16fillArrayUnifiedPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16fillArrayUnifiedPi, .Lfunc_end1-_Z16fillArrayUnifiedPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9fillArrayPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9fillArrayPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16fillArrayUnifiedPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16fillArrayUnifiedPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007fa53_00000000-6_integers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9fillArrayPii
.type _Z9fillArrayPii, @function
_Z9fillArrayPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9fillArrayPii, .-_Z9fillArrayPii
.globl _Z30__device_stub__Z9fillArrayPiS_PiS_
.type _Z30__device_stub__Z9fillArrayPiS_PiS_, @function
_Z30__device_stub__Z9fillArrayPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fillArrayPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9fillArrayPiS_PiS_, .-_Z30__device_stub__Z9fillArrayPiS_PiS_
.globl _Z9fillArrayPiS_
.type _Z9fillArrayPiS_, @function
_Z9fillArrayPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9fillArrayPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9fillArrayPiS_, .-_Z9fillArrayPiS_
.globl _Z36__device_stub__Z16fillArrayUnifiedPiPi
.type _Z36__device_stub__Z16fillArrayUnifiedPiPi, @function
_Z36__device_stub__Z16fillArrayUnifiedPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16fillArrayUnifiedPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z16fillArrayUnifiedPiPi, .-_Z36__device_stub__Z16fillArrayUnifiedPiPi
.globl _Z16fillArrayUnifiedPi
.type _Z16fillArrayUnifiedPi, @function
_Z16fillArrayUnifiedPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16fillArrayUnifiedPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z16fillArrayUnifiedPi, .-_Z16fillArrayUnifiedPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L24:
call cudaDeviceSynchronize@PLT
movl $100, %eax
.L25:
subl $1, %eax
jne .L25
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z36__device_stub__Z16fillArrayUnifiedPiPi
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z16fillArrayUnifiedPi"
.LC2:
.string "_Z9fillArrayPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16fillArrayUnifiedPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fillArrayPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "integers.hip"
.globl _Z9fillArrayPii # -- Begin function _Z9fillArrayPii
.p2align 4, 0x90
.type _Z9fillArrayPii,@function
_Z9fillArrayPii: # @_Z9fillArrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9fillArrayPii, .Lfunc_end0-_Z9fillArrayPii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__fillArrayPiS_ # -- Begin function _Z24__device_stub__fillArrayPiS_
.p2align 4, 0x90
.type _Z24__device_stub__fillArrayPiS_,@function
_Z24__device_stub__fillArrayPiS_: # @_Z24__device_stub__fillArrayPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9fillArrayPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__fillArrayPiS_, .Lfunc_end1-_Z24__device_stub__fillArrayPiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__fillArrayUnifiedPi # -- Begin function _Z31__device_stub__fillArrayUnifiedPi
.p2align 4, 0x90
.type _Z31__device_stub__fillArrayUnifiedPi,@function
_Z31__device_stub__fillArrayUnifiedPi: # @_Z31__device_stub__fillArrayUnifiedPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16fillArrayUnifiedPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z31__device_stub__fillArrayUnifiedPi, .Lfunc_end2-_Z31__device_stub__fillArrayUnifiedPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
movl $1, %edx
callq hipMallocManaged
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16fillArrayUnifiedPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fillArrayPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16fillArrayUnifiedPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fillArrayPiS_,@object # @_Z9fillArrayPiS_
.section .rodata,"a",@progbits
.globl _Z9fillArrayPiS_
.p2align 3, 0x0
_Z9fillArrayPiS_:
.quad _Z24__device_stub__fillArrayPiS_
.size _Z9fillArrayPiS_, 8
.type _Z16fillArrayUnifiedPi,@object # @_Z16fillArrayUnifiedPi
.globl _Z16fillArrayUnifiedPi
.p2align 3, 0x0
_Z16fillArrayUnifiedPi:
.quad _Z31__device_stub__fillArrayUnifiedPi
.size _Z16fillArrayUnifiedPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9fillArrayPiS_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16fillArrayUnifiedPi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fillArrayPiS_
.addrsig_sym _Z31__device_stub__fillArrayUnifiedPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fillArrayPiS_
.addrsig_sym _Z16fillArrayUnifiedPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_mull2(float* a, float* b, float* c, int n, int m,int p)
{
int i = blockIdx.x * 32 + threadIdx.x;
int j = blockIdx.y;
float sum = 0.0f;
for (int k = 0; k < p; ++k) {
sum += b[i + n * k] * c[k + p * j];
}
a[i + n * j] = sum;
} | code for sm_80
Function : _Z9gpu_mull2PfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R6, c[0x0][0x180] ; /* 0x0000600000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0080*/ LEA R5, R0, R3, 0x5 ; /* 0x0000000300057211 */
/* 0x001fd200078e28ff */
/*0090*/ @!P0 BRA 0xbb0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00d0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*00f0*/ @!P0 BRA 0xa60 ; /* 0x0000096000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R7, -R6, c[0x0][0x180], RZ ; /* 0x0000600006077a10 */
/* 0x000fe20007ffe1ff */
/*0110*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD R13, R2, c[0x0][0x180], RZ ; /* 0x00006000020d7a24 */
/* 0x002fe200078e02ff */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0140*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f04270 */
/*0150*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.WIDE R12, R13, R8, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R28, R5, R8, c[0x0][0x168] ; /* 0x00005a00051c7625 */
/* 0x000fe400078e0208 */
/*0180*/ @!P0 BRA 0x8e0 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x630 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R16, R8, c[0x0][0x178], R28 ; /* 0x00005e0008107a25 */
/* 0x000fc600078e021c */
/*01f0*/ LDG.E R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x0002e8000c1e1900 */
/*0220*/ LDG.E R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f22000c1e1900 */
/*0240*/ IMAD.WIDE R16, R8, c[0x0][0x178], R16 ; /* 0x00005e0008107a25 */
/* 0x002fc600078e0210 */
/*0250*/ LDG.E R19, [R12.64+0x14] ; /* 0x000014040c137981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000322000c1e1900 */
/*0270*/ IMAD.WIDE R26, R8, c[0x0][0x178], R16 ; /* 0x00005e00081a7a25 */
/* 0x000fca00078e0210 */
/*0280*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R24, R8, c[0x0][0x178], R26 ; /* 0x00005e0008187a25 */
/* 0x000fcc00078e021a */
/*02a0*/ IMAD.WIDE R28, R8.reuse, c[0x0][0x178], R24 ; /* 0x00005e00081c7a25 */
/* 0x041fe400078e0218 */
/*02b0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x002f22000c1e1900 */
/*02d0*/ IMAD.WIDE R16, R8, c[0x0][0x178], R28 ; /* 0x00005e0008107a25 */
/* 0x000fc600078e021c */
/*02e0*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000322000c1e1900 */
/*02f0*/ FFMA R21, R21, R18, R9 ; /* 0x0000001215157223 */
/* 0x004fc60000000009 */
/*0300*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000568000c1e1900 */
/*0310*/ LDG.E R9, [R12.64+0x18] ; /* 0x000018040c097981 */
/* 0x000f62000c1e1900 */
/*0320*/ FFMA R27, R11, R20, R21 ; /* 0x000000140b1b7223 */
/* 0x008fc60000000015 */
/*0330*/ LDG.E R11, [R12.64+0x1c] ; /* 0x00001c040c0b7981 */
/* 0x000ee2000c1e1900 */
/*0340*/ IMAD.WIDE R16, R8, c[0x0][0x178], R16 ; /* 0x00005e0008107a25 */
/* 0x004fca00078e0210 */
/*0350*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x0010e2000c1e1900 */
/*0360*/ IMAD.WIDE R20, R8, c[0x0][0x178], R16 ; /* 0x00005e0008147a25 */
/* 0x000fca00078e0210 */
/*0370*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x0022a2000c1e1900 */
/*0380*/ FFMA R29, R22, R23, R27 ; /* 0x00000017161d7223 */
/* 0x010fe4000000001b */
/*0390*/ IMAD.WIDE R22, R8, c[0x0][0x178], R20 ; /* 0x00005e0008167a25 */
/* 0x000fe200078e0214 */
/*03a0*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000ea6000c1e1900 */
/*03b0*/ FFMA R16, R14, R15, R29 ; /* 0x0000000f0e107223 */
/* 0x001fe4000000001d */
/*03c0*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x002722000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R8, c[0x0][0x178], R22 ; /* 0x00005e00080e7a25 */
/* 0x000fc600078e0216 */
/*03f0*/ LDG.E R21, [R12.64+0x28] ; /* 0x000028040c157981 */
/* 0x000f22000c1e1900 */
/*0400*/ FFMA R25, R26, R25, R16 ; /* 0x000000191a197223 */
/* 0x000fe40000000010 */
/*0410*/ IMAD.WIDE R16, R8.reuse, c[0x0][0x178], R14 ; /* 0x00005e0008107a25 */
/* 0x040fe200078e020e */
/*0420*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000f26000c1e1900 */
/*0430*/ FFMA R10, R19, R10, R25 ; /* 0x0000000a130a7223 */
/* 0x000fe20000000019 */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0450*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000324000c1e1900 */
/*0460*/ IMAD.WIDE R16, R8, c[0x0][0x178], R16 ; /* 0x00005e0008107a25 */
/* 0x002fc800078e0210 */
/*0470*/ FFMA R10, R9, R18, R10 ; /* 0x00000012090a7223 */
/* 0x020fe4000000000a */
/*0480*/ IMAD.WIDE R18, R8, c[0x0][0x178], R16 ; /* 0x00005e0008127a25 */
/* 0x000fe200078e0210 */
/*0490*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000368000c1e1900 */
/*04a0*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R22, R11, R24, R10 ; /* 0x000000180b167223 */
/* 0x008fc6000000000a */
/*04c0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x000162000c1e1900 */
/*04d0*/ IMAD.WIDE R10, R8, c[0x0][0x178], R18 ; /* 0x00005e00080a7a25 */
/* 0x000fc600078e0212 */
/*04e0*/ LDG.E R16, [R12.64+0x34] ; /* 0x000034040c107981 */
/* 0x0020e2000c1e1900 */
/*04f0*/ FFMA R17, R27, R28, R22 ; /* 0x0000001c1b117223 */
/* 0x004fe40000000016 */
/*0500*/ IMAD.WIDE R22, R8, c[0x0][0x178], R10 ; /* 0x00005e0008167a25 */
/* 0x000fe200078e020a */
/*0510*/ LDG.E R27, [R12.64+0x38] ; /* 0x000038040c1b7981 */
/* 0x0000a8000c1e1900 */
/*0520*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ FFMA R29, R29, R20, R17 ; /* 0x000000141d1d7223 */
/* 0x010fc60000000011 */
/*0540*/ LDG.E R17, [R12.64+0x3c] ; /* 0x00003c040c117981 */
/* 0x000128000c1e1900 */
/*0550*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000f22000c1e1900 */
/*0560*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*0570*/ FFMA R14, R21, R14, R29 ; /* 0x0000000e150e7223 */
/* 0x000fc6000000001d */
/*0580*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*0590*/ FFMA R14, R26, R25, R14 ; /* 0x000000191a0e7223 */
/* 0x000fe2000000000e */
/*05a0*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x001fe40007f5e0ff */
/*05b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05d0*/ FFMA R9, R24, R9, R14 ; /* 0x0000000918097223 */
/* 0x020fc8000000000e */
/*05e0*/ FFMA R9, R16, R15, R9 ; /* 0x0000000f10097223 */
/* 0x008fc80000000009 */
/*05f0*/ FFMA R9, R27, R28, R9 ; /* 0x0000001c1b097223 */
/* 0x004fe40000000009 */
/*0600*/ IMAD.WIDE R28, R8, c[0x0][0x178], R22 ; /* 0x00005e00081c7a25 */
/* 0x000fc800078e0216 */
/*0610*/ FFMA R9, R17, R20, R9 ; /* 0x0000001411097223 */
/* 0x010fe20000000009 */
/*0620*/ @P1 BRA 0x1d0 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*0630*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0640*/ @!P1 BRA 0x8c0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R25, [R28.64] ; /* 0x000000041c197981 */
/* 0x0000a2000c1e1900 */
/*0670*/ IMAD.WIDE R20, R8, c[0x0][0x178], R28 ; /* 0x00005e0008147a25 */
/* 0x000fc600078e021c */
/*0680*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x0002e2000c1e1900 */
/*06a0*/ IMAD.WIDE R14, R8, c[0x0][0x178], R20 ; /* 0x00005e00080e7a25 */
/* 0x000fc600078e0214 */
/*06b0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f26000c1e1900 */
/*06c0*/ IMAD.WIDE R16, R8.reuse, c[0x0][0x178], R14 ; /* 0x00005e0008107a25 */
/* 0x040fe200078e020e */
/*06d0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000122000c1e1900 */
/*06f0*/ IMAD.WIDE R10, R8, c[0x0][0x178], R16 ; /* 0x00005e00080a7a25 */
/* 0x000fc600078e0210 */
/*0700*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000566000c1e1900 */
/*0710*/ IMAD.WIDE R18, R8.reuse, c[0x0][0x178], R10 ; /* 0x00005e0008127a25 */
/* 0x040fe200078e020a */
/*0720*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x00116a000c1e1900 */
/*0730*/ IMAD.WIDE R20, R8.reuse, c[0x0][0x178], R18 ; /* 0x00005e0008147a25 */
/* 0x042fe200078e0212 */
/*0740*/ LDG.E R11, [R12.64+0x10] ; /* 0x000010040c0b7981 */
/* 0x001f68000c1e1900 */
/*0750*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R28, R8, c[0x0][0x178], R20 ; /* 0x00005e00081c7a25 */
/* 0x000fc800078e0214 */
/*0770*/ FFMA R17, R24, R25, R9 ; /* 0x0000001918117223 */
/* 0x004fe40000000009 */
/*0780*/ LDG.E R25, [R12.64+0x14] ; /* 0x000014040c197981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R24, [R12.64+0x18] ; /* 0x000018040c187981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ FFMA R23, R23, R22, R17 ; /* 0x0000001617177223 */
/* 0x008fc60000000011 */
/*07c0*/ LDG.E R17, [R12.64+0x1c] ; /* 0x00001c040c117981 */
/* 0x0000e8000c1e1900 */
/*07d0*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x0002e2000c1e1900 */
/*07e0*/ FFMA R23, R27, R14, R23 ; /* 0x0000000e1b177223 */
/* 0x010fc80000000017 */
/*07f0*/ FFMA R16, R26, R16, R23 ; /* 0x000000101a107223 */
/* 0x020fe20000000017 */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0810*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0820*/ FFMA R11, R11, R15, R16 ; /* 0x0000000f0b0b7223 */
/* 0x000fe20000000010 */
/*0830*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.WIDE R28, R8, c[0x0][0x178], R28 ; /* 0x00005e00081c7a25 */
/* 0x002fc800078e021c */
/*0850*/ FFMA R10, R25, R10, R11 ; /* 0x0000000a190a7223 */
/* 0x004fe2000000000b */
/*0860*/ IADD3 R11, P1, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fc60007f3e0ff */
/*0870*/ FFMA R9, R24, R9, R10 ; /* 0x0000000918097223 */
/* 0x000fe2000000000a */
/*0880*/ IADD3.X R10, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0a7210 */
/* 0x000fe40000ffe4ff */
/*0890*/ MOV R12, R11 ; /* 0x0000000b000c7202 */
/* 0x001fe40000000f00 */
/*08a0*/ MOV R13, R10 ; /* 0x0000000a000d7202 */
/* 0x000fe20000000f00 */
/*08b0*/ FFMA R9, R17, R22, R9 ; /* 0x0000001611097223 */
/* 0x008fe40000000009 */
/*08c0*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*08d0*/ @!P0 BRA 0xa60 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD.WIDE R14, R8.reuse, c[0x0][0x178], R28 ; /* 0x00005e00080e7a25 */
/* 0x040fe200078e021c */
/*08f0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x0000a8000c1e1900 */
/*0900*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R16, R8, c[0x0][0x178], R14 ; /* 0x00005e0008107a25 */
/* 0x000fc600078e020e */
/*0920*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0002e8000c1e1900 */
/*0930*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x0000e2000c1e1900 */
/*0940*/ IMAD.WIDE R10, R8, c[0x0][0x178], R16 ; /* 0x00005e00080a7a25 */
/* 0x000fc600078e0210 */
/*0950*/ LDG.E R21, [R12.64+0x8] ; /* 0x000008040c157981 */
/* 0x000128000c1e1900 */
/*0960*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000f28000c1e1900 */
/*0970*/ LDG.E R23, [R12.64+0xc] ; /* 0x00000c040c177981 */
/* 0x000168000c1e1900 */
/*0980*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f62000c1e1900 */
/*0990*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*09b0*/ IADD3 R14, P1, R12, 0x10, RZ ; /* 0x000000100c0e7810 */
/* 0x002fc80007f3e0ff */
/*09c0*/ IADD3.X R15, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0f7210 */
/* 0x000fe40000ffe4ff */
/*09d0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ MOV R12, R14 ; /* 0x0000000e000c7202 */
/* 0x001fe40000000f00 */
/*09f0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0a00*/ FFMA R18, R18, R28, R9 ; /* 0x0000001c12127223 */
/* 0x004fc80000000009 */
/*0a10*/ FFMA R18, R19, R20, R18 ; /* 0x0000001413127223 */
/* 0x008fe40000000012 */
/*0a20*/ IMAD.WIDE R28, R8, c[0x0][0x178], R10 ; /* 0x00005e00081c7a25 */
/* 0x000fc800078e020a */
/*0a30*/ FFMA R18, R21, R22, R18 ; /* 0x0000001615127223 */
/* 0x010fc80000000012 */
/*0a40*/ FFMA R9, R23, R24, R18 ; /* 0x0000001817097223 */
/* 0x020fe20000000012 */
/*0a50*/ @P0 BRA 0x8e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0a70*/ @!P0 BRA 0xbb0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0a80*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD R10, R2, c[0x0][0x180], R4 ; /* 0x00006000020a7a24 */
/* 0x002fe400078e0204 */
/*0aa0*/ IMAD R3, R4, c[0x0][0x178], R3 ; /* 0x00005e0004037a24 */
/* 0x000fca00078e0203 */
/*0ab0*/ LEA R3, R0, R3, 0x5 ; /* 0x0000000300037211 */
/* 0x000fe400078e28ff */
/*0ac0*/ IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fca00078e020f */
/*0ad0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0ae0*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0af0*/ IMAD.WIDE R10, R3, R15, c[0x0][0x168] ; /* 0x00005a00030a7625 */
/* 0x000fc800078e020f */
/*0b00*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*0b10*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a2000c1e1900 */
/*0b20*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*0b30*/ LDG.E R0, [R12.64] ; /* 0x000000040c007981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007f3e0ff */
/*0b60*/ IMAD.WIDE R10, R15, c[0x0][0x178], R10 ; /* 0x00005e000f0a7a25 */
/* 0x001fe200078e020a */
/*0b70*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0b90*/ FFMA R9, R0, R3, R9 ; /* 0x0000000300097223 */
/* 0x004fd40000000009 */
/*0ba0*/ @P0 BRA 0xb00 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0bc0*/ IMAD R2, R2, c[0x0][0x178], R5 ; /* 0x00005e0002027a24 */
/* 0x002fc800078e0205 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_mull2(float* a, float* b, float* c, int n, int m,int p)
{
int i = blockIdx.x * 32 + threadIdx.x;
int j = blockIdx.y;
float sum = 0.0f;
for (int k = 0; k < p; ++k) {
sum += b[i + n * k] * c[k + p * j];
}
a[i + n * j] = sum;
} | .file "tmpxft_000ab429_00000000-6_gpu_mull2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii
.type _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii, @function
_Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9gpu_mull2PfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii, .-_Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii
.globl _Z9gpu_mull2PfS_S_iii
.type _Z9gpu_mull2PfS_S_iii, @function
_Z9gpu_mull2PfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9gpu_mull2PfS_S_iii, .-_Z9gpu_mull2PfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9gpu_mull2PfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_mull2PfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_mull2(float* a, float* b, float* c, int n, int m,int p)
{
int i = blockIdx.x * 32 + threadIdx.x;
int j = blockIdx.y;
float sum = 0.0f;
for (int k = 0; k < p; ++k) {
sum += b[i + n * k] * c[k + p * j];
}
a[i + n * j] = sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_mull2(float* a, float* b, float* c, int n, int m,int p)
{
int i = blockIdx.x * 32 + threadIdx.x;
int j = blockIdx.y;
float sum = 0.0f;
for (int k = 0; k < p; ++k) {
sum += b[i + n * k] * c[k + p * j];
}
a[i + n * j] = sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_mull2(float* a, float* b, float* c, int n, int m,int p)
{
int i = blockIdx.x * 32 + threadIdx.x;
int j = blockIdx.y;
float sum = 0.0f;
for (int k = 0; k < p; ++k) {
sum += b[i + n * k] * c[k + p * j];
}
a[i + n * j] = sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpu_mull2PfS_S_iii
.globl _Z9gpu_mull2PfS_S_iii
.p2align 8
.type _Z9gpu_mull2PfS_S_iii,@function
_Z9gpu_mull2PfS_S_iii:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x18
v_lshl_add_u32 v0, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
s_mul_i32 s2, s15, s9
v_mov_b32_e32 v3, 0
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v1, v0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s6, s[2:3], 0x0
s_add_i32 s9, s9, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_cmp_eq_u32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s6, v2
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v3, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpu_mull2PfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpu_mull2PfS_S_iii, .Lfunc_end0-_Z9gpu_mull2PfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpu_mull2PfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9gpu_mull2PfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_mull2(float* a, float* b, float* c, int n, int m,int p)
{
int i = blockIdx.x * 32 + threadIdx.x;
int j = blockIdx.y;
float sum = 0.0f;
for (int k = 0; k < p; ++k) {
sum += b[i + n * k] * c[k + p * j];
}
a[i + n * j] = sum;
} | .text
.file "gpu_mull2.hip"
.globl _Z24__device_stub__gpu_mull2PfS_S_iii # -- Begin function _Z24__device_stub__gpu_mull2PfS_S_iii
.p2align 4, 0x90
.type _Z24__device_stub__gpu_mull2PfS_S_iii,@function
_Z24__device_stub__gpu_mull2PfS_S_iii: # @_Z24__device_stub__gpu_mull2PfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9gpu_mull2PfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__gpu_mull2PfS_S_iii, .Lfunc_end0-_Z24__device_stub__gpu_mull2PfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_mull2PfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpu_mull2PfS_S_iii,@object # @_Z9gpu_mull2PfS_S_iii
.section .rodata,"a",@progbits
.globl _Z9gpu_mull2PfS_S_iii
.p2align 3, 0x0
_Z9gpu_mull2PfS_S_iii:
.quad _Z24__device_stub__gpu_mull2PfS_S_iii
.size _Z9gpu_mull2PfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9gpu_mull2PfS_S_iii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpu_mull2PfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpu_mull2PfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9gpu_mull2PfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R6, c[0x0][0x180] ; /* 0x0000600000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0080*/ LEA R5, R0, R3, 0x5 ; /* 0x0000000300057211 */
/* 0x001fd200078e28ff */
/*0090*/ @!P0 BRA 0xbb0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00d0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*00f0*/ @!P0 BRA 0xa60 ; /* 0x0000096000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R7, -R6, c[0x0][0x180], RZ ; /* 0x0000600006077a10 */
/* 0x000fe20007ffe1ff */
/*0110*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD R13, R2, c[0x0][0x180], RZ ; /* 0x00006000020d7a24 */
/* 0x002fe200078e02ff */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0140*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f04270 */
/*0150*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.WIDE R12, R13, R8, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R28, R5, R8, c[0x0][0x168] ; /* 0x00005a00051c7625 */
/* 0x000fe400078e0208 */
/*0180*/ @!P0 BRA 0x8e0 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x630 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R16, R8, c[0x0][0x178], R28 ; /* 0x00005e0008107a25 */
/* 0x000fc600078e021c */
/*01f0*/ LDG.E R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x0002e8000c1e1900 */
/*0220*/ LDG.E R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f22000c1e1900 */
/*0240*/ IMAD.WIDE R16, R8, c[0x0][0x178], R16 ; /* 0x00005e0008107a25 */
/* 0x002fc600078e0210 */
/*0250*/ LDG.E R19, [R12.64+0x14] ; /* 0x000014040c137981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000322000c1e1900 */
/*0270*/ IMAD.WIDE R26, R8, c[0x0][0x178], R16 ; /* 0x00005e00081a7a25 */
/* 0x000fca00078e0210 */
/*0280*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R24, R8, c[0x0][0x178], R26 ; /* 0x00005e0008187a25 */
/* 0x000fcc00078e021a */
/*02a0*/ IMAD.WIDE R28, R8.reuse, c[0x0][0x178], R24 ; /* 0x00005e00081c7a25 */
/* 0x041fe400078e0218 */
/*02b0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x002f22000c1e1900 */
/*02d0*/ IMAD.WIDE R16, R8, c[0x0][0x178], R28 ; /* 0x00005e0008107a25 */
/* 0x000fc600078e021c */
/*02e0*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000322000c1e1900 */
/*02f0*/ FFMA R21, R21, R18, R9 ; /* 0x0000001215157223 */
/* 0x004fc60000000009 */
/*0300*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000568000c1e1900 */
/*0310*/ LDG.E R9, [R12.64+0x18] ; /* 0x000018040c097981 */
/* 0x000f62000c1e1900 */
/*0320*/ FFMA R27, R11, R20, R21 ; /* 0x000000140b1b7223 */
/* 0x008fc60000000015 */
/*0330*/ LDG.E R11, [R12.64+0x1c] ; /* 0x00001c040c0b7981 */
/* 0x000ee2000c1e1900 */
/*0340*/ IMAD.WIDE R16, R8, c[0x0][0x178], R16 ; /* 0x00005e0008107a25 */
/* 0x004fca00078e0210 */
/*0350*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x0010e2000c1e1900 */
/*0360*/ IMAD.WIDE R20, R8, c[0x0][0x178], R16 ; /* 0x00005e0008147a25 */
/* 0x000fca00078e0210 */
/*0370*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x0022a2000c1e1900 */
/*0380*/ FFMA R29, R22, R23, R27 ; /* 0x00000017161d7223 */
/* 0x010fe4000000001b */
/*0390*/ IMAD.WIDE R22, R8, c[0x0][0x178], R20 ; /* 0x00005e0008167a25 */
/* 0x000fe200078e0214 */
/*03a0*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000ea6000c1e1900 */
/*03b0*/ FFMA R16, R14, R15, R29 ; /* 0x0000000f0e107223 */
/* 0x001fe4000000001d */
/*03c0*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x002722000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R8, c[0x0][0x178], R22 ; /* 0x00005e00080e7a25 */
/* 0x000fc600078e0216 */
/*03f0*/ LDG.E R21, [R12.64+0x28] ; /* 0x000028040c157981 */
/* 0x000f22000c1e1900 */
/*0400*/ FFMA R25, R26, R25, R16 ; /* 0x000000191a197223 */
/* 0x000fe40000000010 */
/*0410*/ IMAD.WIDE R16, R8.reuse, c[0x0][0x178], R14 ; /* 0x00005e0008107a25 */
/* 0x040fe200078e020e */
/*0420*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000f26000c1e1900 */
/*0430*/ FFMA R10, R19, R10, R25 ; /* 0x0000000a130a7223 */
/* 0x000fe20000000019 */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0450*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000324000c1e1900 */
/*0460*/ IMAD.WIDE R16, R8, c[0x0][0x178], R16 ; /* 0x00005e0008107a25 */
/* 0x002fc800078e0210 */
/*0470*/ FFMA R10, R9, R18, R10 ; /* 0x00000012090a7223 */
/* 0x020fe4000000000a */
/*0480*/ IMAD.WIDE R18, R8, c[0x0][0x178], R16 ; /* 0x00005e0008127a25 */
/* 0x000fe200078e0210 */
/*0490*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000368000c1e1900 */
/*04a0*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R22, R11, R24, R10 ; /* 0x000000180b167223 */
/* 0x008fc6000000000a */
/*04c0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x000162000c1e1900 */
/*04d0*/ IMAD.WIDE R10, R8, c[0x0][0x178], R18 ; /* 0x00005e00080a7a25 */
/* 0x000fc600078e0212 */
/*04e0*/ LDG.E R16, [R12.64+0x34] ; /* 0x000034040c107981 */
/* 0x0020e2000c1e1900 */
/*04f0*/ FFMA R17, R27, R28, R22 ; /* 0x0000001c1b117223 */
/* 0x004fe40000000016 */
/*0500*/ IMAD.WIDE R22, R8, c[0x0][0x178], R10 ; /* 0x00005e0008167a25 */
/* 0x000fe200078e020a */
/*0510*/ LDG.E R27, [R12.64+0x38] ; /* 0x000038040c1b7981 */
/* 0x0000a8000c1e1900 */
/*0520*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ FFMA R29, R29, R20, R17 ; /* 0x000000141d1d7223 */
/* 0x010fc60000000011 */
/*0540*/ LDG.E R17, [R12.64+0x3c] ; /* 0x00003c040c117981 */
/* 0x000128000c1e1900 */
/*0550*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000f22000c1e1900 */
/*0560*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*0570*/ FFMA R14, R21, R14, R29 ; /* 0x0000000e150e7223 */
/* 0x000fc6000000001d */
/*0580*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*0590*/ FFMA R14, R26, R25, R14 ; /* 0x000000191a0e7223 */
/* 0x000fe2000000000e */
/*05a0*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x001fe40007f5e0ff */
/*05b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05d0*/ FFMA R9, R24, R9, R14 ; /* 0x0000000918097223 */
/* 0x020fc8000000000e */
/*05e0*/ FFMA R9, R16, R15, R9 ; /* 0x0000000f10097223 */
/* 0x008fc80000000009 */
/*05f0*/ FFMA R9, R27, R28, R9 ; /* 0x0000001c1b097223 */
/* 0x004fe40000000009 */
/*0600*/ IMAD.WIDE R28, R8, c[0x0][0x178], R22 ; /* 0x00005e00081c7a25 */
/* 0x000fc800078e0216 */
/*0610*/ FFMA R9, R17, R20, R9 ; /* 0x0000001411097223 */
/* 0x010fe20000000009 */
/*0620*/ @P1 BRA 0x1d0 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*0630*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0640*/ @!P1 BRA 0x8c0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R25, [R28.64] ; /* 0x000000041c197981 */
/* 0x0000a2000c1e1900 */
/*0670*/ IMAD.WIDE R20, R8, c[0x0][0x178], R28 ; /* 0x00005e0008147a25 */
/* 0x000fc600078e021c */
/*0680*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x0002e2000c1e1900 */
/*06a0*/ IMAD.WIDE R14, R8, c[0x0][0x178], R20 ; /* 0x00005e00080e7a25 */
/* 0x000fc600078e0214 */
/*06b0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f26000c1e1900 */
/*06c0*/ IMAD.WIDE R16, R8.reuse, c[0x0][0x178], R14 ; /* 0x00005e0008107a25 */
/* 0x040fe200078e020e */
/*06d0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000122000c1e1900 */
/*06f0*/ IMAD.WIDE R10, R8, c[0x0][0x178], R16 ; /* 0x00005e00080a7a25 */
/* 0x000fc600078e0210 */
/*0700*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000566000c1e1900 */
/*0710*/ IMAD.WIDE R18, R8.reuse, c[0x0][0x178], R10 ; /* 0x00005e0008127a25 */
/* 0x040fe200078e020a */
/*0720*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x00116a000c1e1900 */
/*0730*/ IMAD.WIDE R20, R8.reuse, c[0x0][0x178], R18 ; /* 0x00005e0008147a25 */
/* 0x042fe200078e0212 */
/*0740*/ LDG.E R11, [R12.64+0x10] ; /* 0x000010040c0b7981 */
/* 0x001f68000c1e1900 */
/*0750*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R28, R8, c[0x0][0x178], R20 ; /* 0x00005e00081c7a25 */
/* 0x000fc800078e0214 */
/*0770*/ FFMA R17, R24, R25, R9 ; /* 0x0000001918117223 */
/* 0x004fe40000000009 */
/*0780*/ LDG.E R25, [R12.64+0x14] ; /* 0x000014040c197981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R24, [R12.64+0x18] ; /* 0x000018040c187981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ FFMA R23, R23, R22, R17 ; /* 0x0000001617177223 */
/* 0x008fc60000000011 */
/*07c0*/ LDG.E R17, [R12.64+0x1c] ; /* 0x00001c040c117981 */
/* 0x0000e8000c1e1900 */
/*07d0*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x0002e2000c1e1900 */
/*07e0*/ FFMA R23, R27, R14, R23 ; /* 0x0000000e1b177223 */
/* 0x010fc80000000017 */
/*07f0*/ FFMA R16, R26, R16, R23 ; /* 0x000000101a107223 */
/* 0x020fe20000000017 */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0810*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0820*/ FFMA R11, R11, R15, R16 ; /* 0x0000000f0b0b7223 */
/* 0x000fe20000000010 */
/*0830*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.WIDE R28, R8, c[0x0][0x178], R28 ; /* 0x00005e00081c7a25 */
/* 0x002fc800078e021c */
/*0850*/ FFMA R10, R25, R10, R11 ; /* 0x0000000a190a7223 */
/* 0x004fe2000000000b */
/*0860*/ IADD3 R11, P1, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fc60007f3e0ff */
/*0870*/ FFMA R9, R24, R9, R10 ; /* 0x0000000918097223 */
/* 0x000fe2000000000a */
/*0880*/ IADD3.X R10, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0a7210 */
/* 0x000fe40000ffe4ff */
/*0890*/ MOV R12, R11 ; /* 0x0000000b000c7202 */
/* 0x001fe40000000f00 */
/*08a0*/ MOV R13, R10 ; /* 0x0000000a000d7202 */
/* 0x000fe20000000f00 */
/*08b0*/ FFMA R9, R17, R22, R9 ; /* 0x0000001611097223 */
/* 0x008fe40000000009 */
/*08c0*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*08d0*/ @!P0 BRA 0xa60 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD.WIDE R14, R8.reuse, c[0x0][0x178], R28 ; /* 0x00005e00080e7a25 */
/* 0x040fe200078e021c */
/*08f0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x0000a8000c1e1900 */
/*0900*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R16, R8, c[0x0][0x178], R14 ; /* 0x00005e0008107a25 */
/* 0x000fc600078e020e */
/*0920*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0002e8000c1e1900 */
/*0930*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x0000e2000c1e1900 */
/*0940*/ IMAD.WIDE R10, R8, c[0x0][0x178], R16 ; /* 0x00005e00080a7a25 */
/* 0x000fc600078e0210 */
/*0950*/ LDG.E R21, [R12.64+0x8] ; /* 0x000008040c157981 */
/* 0x000128000c1e1900 */
/*0960*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000f28000c1e1900 */
/*0970*/ LDG.E R23, [R12.64+0xc] ; /* 0x00000c040c177981 */
/* 0x000168000c1e1900 */
/*0980*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000f62000c1e1900 */
/*0990*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*09b0*/ IADD3 R14, P1, R12, 0x10, RZ ; /* 0x000000100c0e7810 */
/* 0x002fc80007f3e0ff */
/*09c0*/ IADD3.X R15, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0f7210 */
/* 0x000fe40000ffe4ff */
/*09d0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ MOV R12, R14 ; /* 0x0000000e000c7202 */
/* 0x001fe40000000f00 */
/*09f0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0a00*/ FFMA R18, R18, R28, R9 ; /* 0x0000001c12127223 */
/* 0x004fc80000000009 */
/*0a10*/ FFMA R18, R19, R20, R18 ; /* 0x0000001413127223 */
/* 0x008fe40000000012 */
/*0a20*/ IMAD.WIDE R28, R8, c[0x0][0x178], R10 ; /* 0x00005e00081c7a25 */
/* 0x000fc800078e020a */
/*0a30*/ FFMA R18, R21, R22, R18 ; /* 0x0000001615127223 */
/* 0x010fc80000000012 */
/*0a40*/ FFMA R9, R23, R24, R18 ; /* 0x0000001817097223 */
/* 0x020fe20000000012 */
/*0a50*/ @P0 BRA 0x8e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0a70*/ @!P0 BRA 0xbb0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0a80*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD R10, R2, c[0x0][0x180], R4 ; /* 0x00006000020a7a24 */
/* 0x002fe400078e0204 */
/*0aa0*/ IMAD R3, R4, c[0x0][0x178], R3 ; /* 0x00005e0004037a24 */
/* 0x000fca00078e0203 */
/*0ab0*/ LEA R3, R0, R3, 0x5 ; /* 0x0000000300037211 */
/* 0x000fe400078e28ff */
/*0ac0*/ IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fca00078e020f */
/*0ad0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0ae0*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0af0*/ IMAD.WIDE R10, R3, R15, c[0x0][0x168] ; /* 0x00005a00030a7625 */
/* 0x000fc800078e020f */
/*0b00*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*0b10*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a2000c1e1900 */
/*0b20*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*0b30*/ LDG.E R0, [R12.64] ; /* 0x000000040c007981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007f3e0ff */
/*0b60*/ IMAD.WIDE R10, R15, c[0x0][0x178], R10 ; /* 0x00005e000f0a7a25 */
/* 0x001fe200078e020a */
/*0b70*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0b90*/ FFMA R9, R0, R3, R9 ; /* 0x0000000300097223 */
/* 0x004fd40000000009 */
/*0ba0*/ @P0 BRA 0xb00 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0bc0*/ IMAD R2, R2, c[0x0][0x178], R5 ; /* 0x00005e0002027a24 */
/* 0x002fc800078e0205 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpu_mull2PfS_S_iii
.globl _Z9gpu_mull2PfS_S_iii
.p2align 8
.type _Z9gpu_mull2PfS_S_iii,@function
_Z9gpu_mull2PfS_S_iii:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x18
v_lshl_add_u32 v0, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
s_mul_i32 s2, s15, s9
v_mov_b32_e32 v3, 0
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v1, v0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s6, s[2:3], 0x0
s_add_i32 s9, s9, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_cmp_eq_u32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s6, v2
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v3, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpu_mull2PfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpu_mull2PfS_S_iii, .Lfunc_end0-_Z9gpu_mull2PfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpu_mull2PfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9gpu_mull2PfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab429_00000000-6_gpu_mull2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii
.type _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii, @function
_Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9gpu_mull2PfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii, .-_Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii
.globl _Z9gpu_mull2PfS_S_iii
.type _Z9gpu_mull2PfS_S_iii, @function
_Z9gpu_mull2PfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9gpu_mull2PfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9gpu_mull2PfS_S_iii, .-_Z9gpu_mull2PfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9gpu_mull2PfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_mull2PfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_mull2.hip"
.globl _Z24__device_stub__gpu_mull2PfS_S_iii # -- Begin function _Z24__device_stub__gpu_mull2PfS_S_iii
.p2align 4, 0x90
.type _Z24__device_stub__gpu_mull2PfS_S_iii,@function
_Z24__device_stub__gpu_mull2PfS_S_iii: # @_Z24__device_stub__gpu_mull2PfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9gpu_mull2PfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__gpu_mull2PfS_S_iii, .Lfunc_end0-_Z24__device_stub__gpu_mull2PfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_mull2PfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpu_mull2PfS_S_iii,@object # @_Z9gpu_mull2PfS_S_iii
.section .rodata,"a",@progbits
.globl _Z9gpu_mull2PfS_S_iii
.p2align 3, 0x0
_Z9gpu_mull2PfS_S_iii:
.quad _Z24__device_stub__gpu_mull2PfS_S_iii
.size _Z9gpu_mull2PfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9gpu_mull2PfS_S_iii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpu_mull2PfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpu_mull2PfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define N 100000
__global__ void kernel_add(int a, int b, int *c){
*c = a + b;
}
int main(int argc, char **argv){
int* host_a = (int*) malloc(sizeof(int));
int* host_b = (int*) malloc(sizeof(int));
int* host_c = (int*) malloc(sizeof(int));
int* device_c;
cudaMalloc((void**) &device_c, sizeof(int));
for(int i = 0; i < N; i++){
*host_a = 2;
*host_b = 7;
kernel_add<<<1,1>>>(*host_a, *host_b, device_c);
cudaMemcpy(host_c, device_c, sizeof(int), cudaMemcpyDeviceToHost);
}
cudaFree(&device_c);
printf("%d\n", *host_c);
return 0;
} | code for sm_80
Function : _Z10kernel_addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define N 100000
__global__ void kernel_add(int a, int b, int *c){
*c = a + b;
}
int main(int argc, char **argv){
int* host_a = (int*) malloc(sizeof(int));
int* host_b = (int*) malloc(sizeof(int));
int* host_c = (int*) malloc(sizeof(int));
int* device_c;
cudaMalloc((void**) &device_c, sizeof(int));
for(int i = 0; i < N; i++){
*host_a = 2;
*host_b = 7;
kernel_add<<<1,1>>>(*host_a, *host_b, device_c);
cudaMemcpy(host_c, device_c, sizeof(int), cudaMemcpyDeviceToHost);
}
cudaFree(&device_c);
printf("%d\n", *host_c);
return 0;
} | .file "tmpxft_0014e4c4_00000000-6_Main1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10kernel_addiiPiiiPi
.type _Z32__device_stub__Z10kernel_addiiPiiiPi, @function
_Z32__device_stub__Z10kernel_addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10kernel_addiiPiiiPi, .-_Z32__device_stub__Z10kernel_addiiPiiiPi
.globl _Z10kernel_addiiPi
.type _Z10kernel_addiiPi, @function
_Z10kernel_addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10kernel_addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10kernel_addiiPi, .-_Z10kernel_addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $100000, %ebx
jmp .L13
.L12:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L17
.L13:
movl $7, (%r12)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z32__device_stub__Z10kernel_addiiPiiiPi
jmp .L12
.L17:
leaq 8(%rsp), %rdi
call cudaFree@PLT
movl 0(%rbp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10kernel_addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define N 100000
__global__ void kernel_add(int a, int b, int *c){
*c = a + b;
}
int main(int argc, char **argv){
int* host_a = (int*) malloc(sizeof(int));
int* host_b = (int*) malloc(sizeof(int));
int* host_c = (int*) malloc(sizeof(int));
int* device_c;
cudaMalloc((void**) &device_c, sizeof(int));
for(int i = 0; i < N; i++){
*host_a = 2;
*host_b = 7;
kernel_add<<<1,1>>>(*host_a, *host_b, device_c);
cudaMemcpy(host_c, device_c, sizeof(int), cudaMemcpyDeviceToHost);
}
cudaFree(&device_c);
printf("%d\n", *host_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 100000
__global__ void kernel_add(int a, int b, int *c){
*c = a + b;
}
int main(int argc, char **argv){
int* host_a = (int*) malloc(sizeof(int));
int* host_b = (int*) malloc(sizeof(int));
int* host_c = (int*) malloc(sizeof(int));
int* device_c;
hipMalloc((void**) &device_c, sizeof(int));
for(int i = 0; i < N; i++){
*host_a = 2;
*host_b = 7;
kernel_add<<<1,1>>>(*host_a, *host_b, device_c);
hipMemcpy(host_c, device_c, sizeof(int), hipMemcpyDeviceToHost);
}
hipFree(&device_c);
printf("%d\n", *host_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 100000
__global__ void kernel_add(int a, int b, int *c){
*c = a + b;
}
int main(int argc, char **argv){
int* host_a = (int*) malloc(sizeof(int));
int* host_b = (int*) malloc(sizeof(int));
int* host_c = (int*) malloc(sizeof(int));
int* device_c;
hipMalloc((void**) &device_c, sizeof(int));
for(int i = 0; i < N; i++){
*host_a = 2;
*host_b = 7;
kernel_add<<<1,1>>>(*host_a, *host_b, device_c);
hipMemcpy(host_c, device_c, sizeof(int), hipMemcpyDeviceToHost);
}
hipFree(&device_c);
printf("%d\n", *host_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_addiiPi
.globl _Z10kernel_addiiPi
.p2align 8
.type _Z10kernel_addiiPi,@function
_Z10kernel_addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_addiiPi, .Lfunc_end0-_Z10kernel_addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10kernel_addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 100000
__global__ void kernel_add(int a, int b, int *c){
*c = a + b;
}
int main(int argc, char **argv){
int* host_a = (int*) malloc(sizeof(int));
int* host_b = (int*) malloc(sizeof(int));
int* host_c = (int*) malloc(sizeof(int));
int* device_c;
hipMalloc((void**) &device_c, sizeof(int));
for(int i = 0; i < N; i++){
*host_a = 2;
*host_b = 7;
kernel_add<<<1,1>>>(*host_a, *host_b, device_c);
hipMemcpy(host_c, device_c, sizeof(int), hipMemcpyDeviceToHost);
}
hipFree(&device_c);
printf("%d\n", *host_c);
return 0;
} | .text
.file "Main1.hip"
.globl _Z25__device_stub__kernel_addiiPi # -- Begin function _Z25__device_stub__kernel_addiiPi
.p2align 4, 0x90
.type _Z25__device_stub__kernel_addiiPi,@function
_Z25__device_stub__kernel_addiiPi: # @_Z25__device_stub__kernel_addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_addiiPi, .Lfunc_end0-_Z25__device_stub__kernel_addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $100000, %r12d # imm = 0x186A0
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 80(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movl $2, 20(%rsp)
movl $7, 16(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10kernel_addiiPi, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
leaq 8(%rsp), %rdi
callq hipFree
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_addiiPi,@object # @_Z10kernel_addiiPi
.section .rodata,"a",@progbits
.globl _Z10kernel_addiiPi
.p2align 3, 0x0
_Z10kernel_addiiPi:
.quad _Z25__device_stub__kernel_addiiPi
.size _Z10kernel_addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kernel_addiiPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_addiiPi
.globl _Z10kernel_addiiPi
.p2align 8
.type _Z10kernel_addiiPi,@function
_Z10kernel_addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_addiiPi, .Lfunc_end0-_Z10kernel_addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10kernel_addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014e4c4_00000000-6_Main1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10kernel_addiiPiiiPi
.type _Z32__device_stub__Z10kernel_addiiPiiiPi, @function
_Z32__device_stub__Z10kernel_addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10kernel_addiiPiiiPi, .-_Z32__device_stub__Z10kernel_addiiPiiiPi
.globl _Z10kernel_addiiPi
.type _Z10kernel_addiiPi, @function
_Z10kernel_addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10kernel_addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10kernel_addiiPi, .-_Z10kernel_addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $100000, %ebx
jmp .L13
.L12:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L17
.L13:
movl $7, (%r12)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z32__device_stub__Z10kernel_addiiPiiiPi
jmp .L12
.L17:
leaq 8(%rsp), %rdi
call cudaFree@PLT
movl 0(%rbp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10kernel_addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Main1.hip"
.globl _Z25__device_stub__kernel_addiiPi # -- Begin function _Z25__device_stub__kernel_addiiPi
.p2align 4, 0x90
.type _Z25__device_stub__kernel_addiiPi,@function
_Z25__device_stub__kernel_addiiPi: # @_Z25__device_stub__kernel_addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_addiiPi, .Lfunc_end0-_Z25__device_stub__kernel_addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $100000, %r12d # imm = 0x186A0
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 80(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movl $2, 20(%rsp)
movl $7, 16(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10kernel_addiiPi, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
leaq 8(%rsp), %rdi
callq hipFree
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_addiiPi,@object # @_Z10kernel_addiiPi
.section .rodata,"a",@progbits
.globl _Z10kernel_addiiPi
.p2align 3, 0x0
_Z10kernel_addiiPi:
.quad _Z25__device_stub__kernel_addiiPi
.size _Z10kernel_addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kernel_addiiPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
extern "C" void cudaInit(size_t sizeA);
extern "C" void cudaFinalize();
extern "C" void putGPU(void* h_A, size_t sizeA);
extern "C" void getGPU(void* h_A, size_t sizeA);
void* d_A;
void cudaInit(size_t sizeA){
//allocate memory on device
cudaMalloc( (void**) &d_A, sizeA);
}
void putGPU(void* h_A, size_t sizeA){
//copy host data from argument to device
cudaMemcpy(d_A, h_A, sizeA, cudaMemcpyHostToDevice);
}
void getGPU(void* h_A, size_t sizeA){
//copy data from device to argument array
cudaMemcpy(h_A, d_A, sizeA, cudaMemcpyDeviceToHost);
}
void cudaFinalize(){
//free device memory
cudaFree(d_A);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
extern "C" void cudaInit(size_t sizeA);
extern "C" void cudaFinalize();
extern "C" void putGPU(void* h_A, size_t sizeA);
extern "C" void getGPU(void* h_A, size_t sizeA);
void* d_A;
void cudaInit(size_t sizeA){
//allocate memory on device
cudaMalloc( (void**) &d_A, sizeA);
}
void putGPU(void* h_A, size_t sizeA){
//copy host data from argument to device
cudaMemcpy(d_A, h_A, sizeA, cudaMemcpyHostToDevice);
}
void getGPU(void* h_A, size_t sizeA){
//copy data from device to argument array
cudaMemcpy(h_A, d_A, sizeA, cudaMemcpyDeviceToHost);
}
void cudaFinalize(){
//free device memory
cudaFree(d_A);
} | .file "tmpxft_000d0c68_00000000-6_dsm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl cudaInit
.type cudaInit, @function
cudaInit:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rsi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size cudaInit, .-cudaInit
.globl putGPU
.type putGPU, @function
putGPU:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size putGPU, .-putGPU
.globl getGPU
.type getGPU, @function
getGPU:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movl $2, %ecx
movq d_A(%rip), %rsi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size getGPU, .-getGPU
.globl cudaFinalize
.type cudaFinalize, @function
cudaFinalize:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_A(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size cudaFinalize, .-cudaFinalize
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_A
.bss
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
extern "C" void cudaInit(size_t sizeA);
extern "C" void cudaFinalize();
extern "C" void putGPU(void* h_A, size_t sizeA);
extern "C" void getGPU(void* h_A, size_t sizeA);
void* d_A;
void cudaInit(size_t sizeA){
//allocate memory on device
cudaMalloc( (void**) &d_A, sizeA);
}
void putGPU(void* h_A, size_t sizeA){
//copy host data from argument to device
cudaMemcpy(d_A, h_A, sizeA, cudaMemcpyHostToDevice);
}
void getGPU(void* h_A, size_t sizeA){
//copy data from device to argument array
cudaMemcpy(h_A, d_A, sizeA, cudaMemcpyDeviceToHost);
}
void cudaFinalize(){
//free device memory
cudaFree(d_A);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
extern "C" void cudaInit(size_t sizeA);
extern "C" void cudaFinalize();
extern "C" void putGPU(void* h_A, size_t sizeA);
extern "C" void getGPU(void* h_A, size_t sizeA);
void* d_A;
void cudaInit(size_t sizeA){
//allocate memory on device
hipMalloc( (void**) &d_A, sizeA);
}
void putGPU(void* h_A, size_t sizeA){
//copy host data from argument to device
hipMemcpy(d_A, h_A, sizeA, hipMemcpyHostToDevice);
}
void getGPU(void* h_A, size_t sizeA){
//copy data from device to argument array
hipMemcpy(h_A, d_A, sizeA, hipMemcpyDeviceToHost);
}
void cudaFinalize(){
//free device memory
hipFree(d_A);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
extern "C" void cudaInit(size_t sizeA);
extern "C" void cudaFinalize();
extern "C" void putGPU(void* h_A, size_t sizeA);
extern "C" void getGPU(void* h_A, size_t sizeA);
void* d_A;
void cudaInit(size_t sizeA){
//allocate memory on device
hipMalloc( (void**) &d_A, sizeA);
}
void putGPU(void* h_A, size_t sizeA){
//copy host data from argument to device
hipMemcpy(d_A, h_A, sizeA, hipMemcpyHostToDevice);
}
void getGPU(void* h_A, size_t sizeA){
//copy data from device to argument array
hipMemcpy(h_A, d_A, sizeA, hipMemcpyDeviceToHost);
}
void cudaFinalize(){
//free device memory
hipFree(d_A);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
extern "C" void cudaInit(size_t sizeA);
extern "C" void cudaFinalize();
extern "C" void putGPU(void* h_A, size_t sizeA);
extern "C" void getGPU(void* h_A, size_t sizeA);
void* d_A;
void cudaInit(size_t sizeA){
//allocate memory on device
hipMalloc( (void**) &d_A, sizeA);
}
void putGPU(void* h_A, size_t sizeA){
//copy host data from argument to device
hipMemcpy(d_A, h_A, sizeA, hipMemcpyHostToDevice);
}
void getGPU(void* h_A, size_t sizeA){
//copy data from device to argument array
hipMemcpy(h_A, d_A, sizeA, hipMemcpyDeviceToHost);
}
void cudaFinalize(){
//free device memory
hipFree(d_A);
} | .text
.file "dsm.hip"
.globl cudaInit # -- Begin function cudaInit
.p2align 4, 0x90
.type cudaInit,@function
cudaInit: # @cudaInit
.cfi_startproc
# %bb.0:
movq %rdi, %rsi
movl $d_A, %edi
jmp hipMalloc # TAILCALL
.Lfunc_end0:
.size cudaInit, .Lfunc_end0-cudaInit
.cfi_endproc
# -- End function
.globl putGPU # -- Begin function putGPU
.p2align 4, 0x90
.type putGPU,@function
putGPU: # @putGPU
.cfi_startproc
# %bb.0:
movq %rsi, %rdx
movq %rdi, %rsi
movq d_A(%rip), %rdi
movl $1, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end1:
.size putGPU, .Lfunc_end1-putGPU
.cfi_endproc
# -- End function
.globl getGPU # -- Begin function getGPU
.p2align 4, 0x90
.type getGPU,@function
getGPU: # @getGPU
.cfi_startproc
# %bb.0:
movq %rsi, %rdx
movq d_A(%rip), %rsi
movl $2, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end2:
.size getGPU, .Lfunc_end2-getGPU
.cfi_endproc
# -- End function
.globl cudaFinalize # -- Begin function cudaFinalize
.p2align 4, 0x90
.type cudaFinalize,@function
cudaFinalize: # @cudaFinalize
.cfi_startproc
# %bb.0:
movq d_A(%rip), %rdi
jmp hipFree # TAILCALL
.Lfunc_end3:
.size cudaFinalize, .Lfunc_end3-cudaFinalize
.cfi_endproc
# -- End function
.type d_A,@object # @d_A
.bss
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_A
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d0c68_00000000-6_dsm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl cudaInit
.type cudaInit, @function
cudaInit:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rsi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size cudaInit, .-cudaInit
.globl putGPU
.type putGPU, @function
putGPU:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size putGPU, .-putGPU
.globl getGPU
.type getGPU, @function
getGPU:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movl $2, %ecx
movq d_A(%rip), %rsi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size getGPU, .-getGPU
.globl cudaFinalize
.type cudaFinalize, @function
cudaFinalize:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_A(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size cudaFinalize, .-cudaFinalize
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_A
.bss
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dsm.hip"
.globl cudaInit # -- Begin function cudaInit
.p2align 4, 0x90
.type cudaInit,@function
cudaInit: # @cudaInit
.cfi_startproc
# %bb.0:
movq %rdi, %rsi
movl $d_A, %edi
jmp hipMalloc # TAILCALL
.Lfunc_end0:
.size cudaInit, .Lfunc_end0-cudaInit
.cfi_endproc
# -- End function
.globl putGPU # -- Begin function putGPU
.p2align 4, 0x90
.type putGPU,@function
putGPU: # @putGPU
.cfi_startproc
# %bb.0:
movq %rsi, %rdx
movq %rdi, %rsi
movq d_A(%rip), %rdi
movl $1, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end1:
.size putGPU, .Lfunc_end1-putGPU
.cfi_endproc
# -- End function
.globl getGPU # -- Begin function getGPU
.p2align 4, 0x90
.type getGPU,@function
getGPU: # @getGPU
.cfi_startproc
# %bb.0:
movq %rsi, %rdx
movq d_A(%rip), %rsi
movl $2, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end2:
.size getGPU, .Lfunc_end2-getGPU
.cfi_endproc
# -- End function
.globl cudaFinalize # -- Begin function cudaFinalize
.p2align 4, 0x90
.type cudaFinalize,@function
cudaFinalize: # @cudaFinalize
.cfi_startproc
# %bb.0:
movq d_A(%rip), %rdi
jmp hipFree # TAILCALL
.Lfunc_end3:
.size cudaFinalize, .Lfunc_end3-cudaFinalize
.cfi_endproc
# -- End function
.type d_A,@object # @d_A
.bss
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_A
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda.h>
#include <time.h>
#include <sys/time.h>
#define DEBUG 1
#define NGRID 512
#define NBLOCK 65535
#define CUDA_CHECK(cmd) {cudaError_t error = cmd; if(error!=cudaSuccess){printf("<%s>:%i ",__FILE__,__LINE__); printf("[CUDA] Error: %s\n", cudaGetErrorString(error));}}
/* The exponent given here determines the steps taken in the adding kernel. An
* exponent of 1 results in rounding the size to 2^1 = 2, therefore, in every
* step, two input fields are added and the size shrinks to half of what it was
* before. This influences the size of the result buffer as well (the greater
* this exponent is, the smaller the result will be). */
#define BASE_EXP 4
#define BASE (1 << BASE_EXP)
/* Define this to actually use host memory instead of copying the buffer to the
* GPU (as it turns out, this may actually be worth it) */
#define USE_HOST_PTR
#ifdef USE_HOST_PTR
#define HOST_PTR_POLICY CL_MEM_USE_HOST_PTR
#else
#define HOST_PTR_POLICY CL_MEM_COPY_HOST_PTR
#endif
/**
* These two functions provide std::chrono functionality (see cpp-stuff.cpp for
* an explanation why they're extern).
CUDA nvcc don't support it.
extern void clock_start(void);
extern long clock_delta(void);
*/
__global__ void k_iadd(unsigned *dest, char *sequence, unsigned seq_length)
{
for (unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
id < seq_length;
id += blockDim.x*gridDim.x)
{
unsigned result = 0;
unsigned in_start = id << BASE_EXP;
if (in_start < seq_length)
{
for (unsigned i = in_start; i < in_start + BASE; i++)
{
char nucleobase = sequence[i];
result += nucleobase != '-';
}
}
dest[id] = result;
}
}
__global__ void k_cadd(unsigned *buffer, unsigned doff, unsigned soff)
{
unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
unsigned in_start = soff + (id << BASE_EXP);
unsigned out_pos = doff + id;
unsigned result = 0;
for (unsigned i = in_start; i < in_start + BASE; i++)
{
unsigned value = buffer[i];
result += value;
}
buffer[out_pos] = result;
}
/**
* Rounds a value x up to the next power of 2^exp.
*/
static long round_up_to_power_of_two(long x, int exp)
{
assert(x > 0);
x--;
int i;
for (i = 0; x; i++)
x >>= exp;
for (x = 1; i; i--)
x <<= exp;
return x;
}
/**
* Loads a text file and returns a buffer with the contents.
*/
static char *load_text(const char *filename, long *length_ptr)
{
FILE *fp = fopen(filename, "r");
if (!fp)
{
fprintf(stderr, "Could not load file \"%s\": %s\n", filename, strerror(errno));
return NULL;
}
fseek(fp, 0, SEEK_END);
long length = ftell(fp);
rewind(fp);
long mem_len = length + 1;
if (length_ptr)
*length_ptr = mem_len;
char *content = (char *)calloc(mem_len, 1);
fread(content, 1, length, fp);
fclose(fp);
return content;
}
int main(int argc, char *argv[])
{
dim3 grid1d(NGRID,1,1);
dim3 block1d(NBLOCK,1,1);
unsigned clstsi, clstc, clsto, local_index;
long delta_time;
struct timeval start_time, end_time;
if (argc < 2)
{
fprintf(stderr, "Usage: transalign_killer [--cldev=x.y] <input file>\n");
fprintf(stderr, " --cldev=x.y: x specifies the platform index, y the device index.\n");
return 1;
}
long seq_length;
//CUDA kernel input
char *sequence = load_text(argv[argc - 1], &seq_length);
if (!sequence)
return 1;
//DEBUG
for (int i=0; i<seq_length; ++i)
{
printf("%c", sequence[i]);
}
printf("\n");
seq_length--; // Cut final 0 byte
// FIXME: All the following code relies on seq_length being a multiple of BASE.
long round_seq_length = round_up_to_power_of_two(seq_length, BASE_EXP);
long res_length = 0;
for (long len = round_seq_length / BASE; len; len /= BASE)
res_length += len;
printf("res_length: %d\n", res_length);
// Use some random index to be searched for here
unsigned letter_index = seq_length / 2;
// Create the result buffer
// CUDA kernel output
unsigned *result = (unsigned *)malloc(res_length * sizeof(unsigned));
unsigned *result_gpu;
char *seq_gpu;
//replace clock_start(); with gettimeofday()
gettimeofday(&start_time, NULL);
#if DEBUG
printf("GPU part started\n");
#endif
/*** START OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
// Bandwidth intensive stuff goes here
// Copy the sequence to the video memory (or, generally speaking, the OpenCL device)
CUDA_CHECK(cudaMalloc((void**)&result_gpu, res_length * sizeof(unsigned)));//result_gpu
CUDA_CHECK(cudaMalloc((void**)&seq_gpu, seq_length*sizeof(char)));//seq_gpu
CUDA_CHECK(cudaMemcpy(seq_gpu, sequence, res_length * sizeof(char), cudaMemcpyHostToDevice));
#if DEBUG
printf("GPU malloc and cpy finised\n");
#endif
//replace clock_delta(); with gettimeofday()
gettimeofday(&end_time, NULL);
long bw1_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// GPU intensive stuff goes here
/**
* First, transform every - and \0 into a 0 and every other character into a
* 1. Then, add consecutive fields (BASE fields) together and store them at
* the beginning of the result buffer.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_iadd launching\n");
#endif
k_iadd<<<grid1d,block1d>>>(result_gpu, seq_gpu, seq_length);
#if DEBUG
printf("k_iadd finished\n");
#endif
CUDA_CHECK(cudaMemcpy(result, result_gpu, res_length * sizeof(unsigned), cudaMemcpyDeviceToHost));
#if DEBUG
printf("result back\n");
for (int i = 0; i < res_length; i++)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
#if DEBUG
printf("k_iadd result back\n");
#endif
unsigned input_offset = 0, output_offset = round_seq_length / BASE;
CUDA_CHECK(cudaMemcpy(result_gpu, result, res_length * sizeof(unsigned), cudaMemcpyHostToDevice));
#if DEBUG
printf("k_cadd loop start\n");
#endif
for (unsigned kernels = round_seq_length / (BASE * BASE); kernels > 0; kernels /= BASE)
{
/**
* Then, do this addition recursively until there is only one kernel
* remaining which calculates the total number of non-'-' and non-'\0'
* characters.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_cadd loop %d\n", kernels);
#endif
k_cadd<<<grid1d,block1d>>>(result_gpu, output_offset, input_offset);
input_offset = output_offset;
output_offset += kernels;
}
#if DEBUG
printf("k_cadd loop end\n");
#endif
// Retrieve the result buffer
#if DEBUG
printf("k_cadd loop end\n");
#endif
CUDA_CHECK(cudaMemcpy(result, result_gpu, res_length * sizeof(unsigned), cudaMemcpyDeviceToHost));
#if DEBUG
printf("k_cadd loop end\n");
#endif
gettimeofday(&end_time, NULL);
long gpu_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// Reverse bandwidth intensive stuff goes here
gettimeofday(&end_time, NULL);
long bw2_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// CPU intensive stuff goes here
#if DEBUG
printf("cpu part start\n");
for (int i=0; i<res_length; ++i)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
if (letter_index > result[res_length - 1])
{
fprintf(stderr, "Logical index out of bounds (last index: %u).\n", result[res_length - 1]);
CUDA_CHECK(cudaFree(result_gpu));
CUDA_CHECK(cudaFree(seq_gpu));
exit(-1);
}
if (!letter_index)
{
fprintf(stderr, "Please used 1-based indexing (for whatever reason).\n");
CUDA_CHECK(cudaFree(result_gpu));
CUDA_CHECK(cudaFree(seq_gpu));
exit(-1);
}
/**
* Okay, now we have a buffer which contains a tree of sums, looking
* something like this:
* _
* 4 |
* / \ |
* 3 1 |- result buffer
* / \ / \ |
* 2 1 1 0 _|
* / \ / \ / \ / \
* A G - T C - - - --- sequence buffer
*
* (actually, it looks more like 2 1 1 2 3 3 6)
*
* Now, we walk through it from the top. Let's assume we're looking for the
* logical index 2. We'll compare it to 4: Of course, it's smaller (that was
* the assertition right before this comment), else, we'd be out of bounds.
* No we're comparing it with the left 3 in the next level. It's smaller,
* therefore, this subtree is correct and we move on to the next level.
* There, we compare it to the left 2. 2 is greater/equal to 2, therefore,
* this is _not_ the right subtree, we have to go to the other one (the one
* to the right, below the 1). We subtract the 2 from the left subtree,
* therefore our new "local" index is 0 (we're looking for the nucleobase at
* index 0 in the subtree below the 1). Now, at the sequence level, there
* are always just two possibilities. Either, the local index is 0 or it is
* 1. If it's 1, this will always mean the right nucleobase, since 1 means
* to skip one. The only one to skip is the left one, therefore, the right
* one is the one we're looking for. If the local index is 0, this refers to
* the first nucleobase, which may be either the left or the right,
* depending on whether the left one is actually a nucleobase.
*
* In this case, the local index is 0. Since the left nucleobase is not
* really one (it is '-'), the right one is the one we're looking for; its
* index in the sequence buffer is 3.
*
* The reference implementation seems to go total hazels, since it
* apparently uses 1-based indexing. Logical index 2 would refer to G for
* it, therefore it returns 2 (which is the 1-based index of G in the
* sequence buffer). I can't see it from the code, but that is what the
* result is.
*
*
* For another BASE than 2, it looks like this (BASE 4):
*
* 9
* // \\
* 3 1 3 2
* // \\ // \\ // \\ // \\
* A G - T C - - - C - T T A G - -
*
* Let's assume, we're looking for index 5. Compare it to 9, it's smaller,
* so this is the tree we're looking for. Then compare it to all subtrees:
* 5 is greater than 3, so go right and subtract 3 from 5. 2 is greater than
* 1, so go right and subtract 1 from 2. 1 then is smaller than 3, so the
* third subtree from the left is the one we want to enter now. The index 1
* here refers to the first T, therefore, it is globally the second T in the
* sequence.
*/
// "Current level subtree starting index"; index of the first subtree sum in
// the current level (we skip level 0, i.e., the complete tree)
clstsi = res_length - 1 - BASE;
// "Current level subtree count"; number of subtrees in the current level
clstc = BASE;
// "Current level subtree offset"; index difference of the actual set of
// subtrees we're using from the first one in the current level
clsto = 0;
// Turn 1-based index into 0-based
local_index = letter_index - 1;
for (;;)
{
int subtree;
// "First subtree index", index of the first subtree we're supposed to
// examine
unsigned fsti = clstsi + clsto * BASE;
// We could add a condition (subtree < BASE) to this loop, but this loop
// has to be left before this condition is false anyway (otherwise,
// something is very wrong).
for (subtree = 0; local_index >= result[fsti + subtree]; subtree++)
local_index -= result[fsti + subtree];
// And we'll check it here anyway (#ifdef NDEBUG).
assert(subtree < BASE);
clsto = clsto * BASE + subtree;
// If clstsi is 0, we were at the beginning of the result buffer and are
// therefore finished
if (!clstsi)
break;
clstc *= BASE;
clstsi -= clstc;
}
// Now we need to go to the sequence level which requires an extra step.
unsigned index;
for (index = clsto * BASE; local_index; index++)
if (sequence[index] != '-')
local_index--;
/*** END OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
//replace with gettimeofday for CUDA
gettimeofday(&end_time, NULL);
delta_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
printf("%li us elapsed total\n", delta_time);
printf(" - %li us on bandwidth forth\n", bw1_time);
printf(" - %li us on GPU\n", gpu_time - bw1_time);
printf(" - %li us on bandwidth back\n", bw2_time - gpu_time);
printf(" - %li us on CPU\n", delta_time - bw2_time);
printf("Index for %u: %u\n", letter_index, index);
printf("cnt = %u (index + 1)\n", index + 1);
//free resource
CUDA_CHECK(cudaFree(result_gpu));
CUDA_CHECK(cudaFree(seq_gpu));
return 0;
} | .file "tmpxft_0006f486_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6k_iaddPjPcjPjPcj
.type _Z28__device_stub__Z6k_iaddPjPcjPjPcj, @function
_Z28__device_stub__Z6k_iaddPjPcjPjPcj:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6k_iaddPjPcj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z6k_iaddPjPcjPjPcj, .-_Z28__device_stub__Z6k_iaddPjPcjPjPcj
.globl _Z6k_iaddPjPcj
.type _Z6k_iaddPjPcj, @function
_Z6k_iaddPjPcj:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6k_iaddPjPcjPjPcj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6k_iaddPjPcj, .-_Z6k_iaddPjPcj
.globl _Z27__device_stub__Z6k_caddPjjjPjjj
.type _Z27__device_stub__Z6k_caddPjjjPjjj, @function
_Z27__device_stub__Z6k_caddPjjjPjjj:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6k_caddPjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z27__device_stub__Z6k_caddPjjjPjjj, .-_Z27__device_stub__Z6k_caddPjjjPjjj
.globl _Z6k_caddPjjj
.type _Z6k_caddPjjj, @function
_Z6k_caddPjjj:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6k_caddPjjjPjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6k_caddPjjj, .-_Z6k_caddPjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: transalign_killer [--cldev=x.y] <input file>\n"
.align 8
.LC1:
.string " --cldev=x.y: x specifies the platform index, y the device index.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "r"
.LC3:
.string "Could not load file \"%s\": %s\n"
.LC4:
.string "%c"
.LC5:
.string "\n"
.LC6:
.string "res_length: %d\n"
.LC7:
.string "GPU part started\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/XanClic/transalign-killer/master/cuda/main.cu"
.section .rodata.str1.1
.LC9:
.string "<%s>:%i "
.LC10:
.string "[CUDA] Error: %s\n"
.LC11:
.string "GPU malloc and cpy finised\n"
.LC12:
.string "k_iadd launching\n"
.LC13:
.string "k_iadd finished\n"
.LC14:
.string "result back\n"
.LC15:
.string "%d "
.LC16:
.string "k_iadd result back\n"
.LC17:
.string "k_cadd loop start\n"
.LC18:
.string "k_cadd loop %d\n"
.LC19:
.string "k_cadd loop end\n"
.LC20:
.string "cpu part start\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Logical index out of bounds (last index: %u).\n"
.align 8
.LC22:
.string "Please used 1-based indexing (for whatever reason).\n"
.section .rodata.str1.1
.LC23:
.string "%li us elapsed total\n"
.LC24:
.string " - %li us on bandwidth forth\n"
.LC25:
.string " - %li us on GPU\n"
.LC26:
.string " - %li us on bandwidth back\n"
.LC27:
.string " - %li us on CPU\n"
.LC28:
.string "Index for %u: %u\n"
.LC29:
.string "cnt = %u (index + 1)\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $512, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $65535, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
cmpl $1, %edi
jle .L75
movslq %edi, %rdi
movq -8(%rsi,%rdi,8), %rbp
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L76
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbx, %rdi
call ftell@PLT
movq %rax, %r12
movq %rbx, %rdi
call rewind@PLT
leaq 1(%r12), %rbp
movl $1, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, %r15
movq %rax, (%rsp)
movq %rbx, %r8
movq %r12, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
testq %r15, %r15
je .L60
testq %rbp, %rbp
jle .L23
movq %r15, %rbx
leaq (%r15,%r12), %r13
leaq .LC4(%rip), %rbp
.L24:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %r13, %rax
jne .L24
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbp
subq $1, %rbp
je .L61
.L58:
movl $0, %eax
.L26:
addl $1, %eax
sarq $4, %rbp
jne .L26
testl %eax, %eax
je .L62
movl $1, %r14d
.L27:
salq $4, %r14
subl $1, %eax
jne .L27
movl $16, %ecx
movq %r14, %rax
cqto
idivq %rcx
movq %rax, 24(%rsp)
testq %rax, %rax
je .L63
.L28:
addq %rax, %rbp
leaq 15(%rax), %rdx
testq %rax, %rax
cmovns %rax, %rdx
sarq $4, %rdx
movq %rdx, %rax
jne .L28
.L25:
movq %rbp, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r12, %rax
cqto
idivq %rcx
movq %rax, 16(%rsp)
movl %eax, 36(%rsp)
movq %rbp, %r15
leaq 0(,%rbp,4), %r13
movq %r13, 8(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L77
.L29:
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L78
.L30:
movl $1, %ecx
movq %r15, %rdx
movq (%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L79
.L31:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %rdx
addq 120(%rsp), %rdx
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %rdx
movq %rdx, 40(%rsp)
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L32:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L81
.L33:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbp, %rbp
jle .L34
movl $0, %r12d
leaq .LC15(%rip), %r13
.L35:
movl (%rbx,%r12,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq %r12, %r15
jne .L35
.L34:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %r13d
movl $1, %ecx
movq 8(%rsp), %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L82
.L36:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, %ecx
movq %r14, %rax
cqto
idivq %rcx
movl %eax, %r12d
testl %eax, %eax
je .L37
movl $0, %eax
leaq .LC18(%rip), %r14
movq %rbx, 24(%rsp)
movl %eax, %ebx
jmp .L39
.L75:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L19
.L76:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %r8
movq %rbp, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L19
.L61:
movq %rbp, 24(%rsp)
movl $1, %r14d
jmp .L25
.L62:
movq %rbp, 24(%rsp)
movl $1, %r14d
jmp .L25
.L63:
movq %rax, %rbp
jmp .L25
.L77:
movl $192, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L78:
movl $193, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L79:
movl $194, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L80:
movl %r12d, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z28__device_stub__Z6k_iaddPjPcjPjPcj
jmp .L32
.L81:
movl $223, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L82:
movl $238, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L38:
leal 0(%r13,%r12), %edx
movl %r12d, %eax
shrl $4, %eax
movl %r13d, %ebx
cmpl $15, %r12d
jbe .L83
movl %eax, %r12d
movl %edx, %r13d
.L39:
movl %r12d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L38
movl %ebx, %edx
movl %r13d, %esi
movq 56(%rsp), %rdi
call _Z27__device_stub__Z6k_caddPjjjPjjj
jmp .L38
.L83:
movq 24(%rsp), %rbx
.L37:
leaq .LC19(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L84
.L40:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %rax
addq 120(%rsp), %rax
movq %rax, %rdx
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %rdx
movq %rdx, 24(%rsp)
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %r14
addq 120(%rsp), %r14
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %r14
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbp, %rbp
jle .L41
movl $0, %r12d
leaq .LC15(%rip), %r13
.L42:
movl (%rbx,%r12,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq %r12, %r15
jne .L42
.L41:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl -4(%rbx,%rax), %ecx
movl 16(%rsp), %eax
cmpl %eax, %ecx
jb .L85
cmpl $0, 16(%rsp)
je .L86
subl $17, %ebp
movl 16(%rsp), %edx
subl $1, %edx
movl $0, %r8d
movl $16, %r9d
movl $0, %r10d
.L52:
sall $4, %r8d
leal (%r8,%rbp), %esi
movl %esi, %eax
movl (%rbx,%rax,4), %ecx
cmpl %ecx, %edx
jb .L65
movl $0, %eax
.L50:
subl %ecx, %edx
addl $1, %eax
movl %eax, %edi
leal (%rsi,%rax), %ecx
movl (%rbx,%rcx,4), %ecx
cmpl %ecx, %edx
jnb .L50
.L49:
addl %edi, %r8d
testl %ebp, %ebp
je .L51
sall $4, %r9d
subl %r9d, %ebp
jmp .L52
.L84:
movl $266, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L40
.L85:
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L87
.L44:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L88
.L45:
movl $-1, %edi
call exit@PLT
.L87:
movl $292, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L88:
movl $293, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L86:
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L89
.L47:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L90
.L48:
movl $-1, %edi
call exit@PLT
.L89:
movl $300, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L90:
movl $301, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L65:
movl %r10d, %edi
jmp .L49
.L51:
movl %r8d, %ebx
sall $4, %ebx
testl %edx, %edx
jne .L55
jmp .L53
.L91:
movl $426, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L92:
movl $427, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L19
.L60:
movl $1, %eax
jmp .L19
.L54:
addl $1, %ebx
.L55:
movl %ebx, %eax
movq (%rsp), %rdi
cmpb $45, (%rdi,%rax)
je .L54
addl $1, %ebx
subl $1, %edx
jne .L55
.L53:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %rbp
addq 120(%rsp), %rbp
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %rbp
movq %rbp, %rdx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %r13
movq %r13, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %r15
movq %r15, %rax
subq %r13, %rax
movq %rax, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdx
subq %r15, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
subq %r14, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl 36(%rsp), %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%rbx), %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L91
.L56:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
movl $0, %eax
testl %ebx, %ebx
jne .L92
.L19:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L93
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1(%r12), %rbp
jmp .L58
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC30:
.string "_Z6k_caddPjjj"
.LC31:
.string "_Z6k_iaddPjPcj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z6k_caddPjjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z6k_iaddPjPcj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda.h>
#include <time.h>
#include <sys/time.h>
#define DEBUG 1
#define NGRID 512
#define NBLOCK 65535
#define CUDA_CHECK(cmd) {cudaError_t error = cmd; if(error!=cudaSuccess){printf("<%s>:%i ",__FILE__,__LINE__); printf("[CUDA] Error: %s\n", cudaGetErrorString(error));}}
/* The exponent given here determines the steps taken in the adding kernel. An
* exponent of 1 results in rounding the size to 2^1 = 2, therefore, in every
* step, two input fields are added and the size shrinks to half of what it was
* before. This influences the size of the result buffer as well (the greater
* this exponent is, the smaller the result will be). */
#define BASE_EXP 4
#define BASE (1 << BASE_EXP)
/* Define this to actually use host memory instead of copying the buffer to the
* GPU (as it turns out, this may actually be worth it) */
#define USE_HOST_PTR
#ifdef USE_HOST_PTR
#define HOST_PTR_POLICY CL_MEM_USE_HOST_PTR
#else
#define HOST_PTR_POLICY CL_MEM_COPY_HOST_PTR
#endif
/**
* These two functions provide std::chrono functionality (see cpp-stuff.cpp for
* an explanation why they're extern).
CUDA nvcc don't support it.
extern void clock_start(void);
extern long clock_delta(void);
*/
__global__ void k_iadd(unsigned *dest, char *sequence, unsigned seq_length)
{
for (unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
id < seq_length;
id += blockDim.x*gridDim.x)
{
unsigned result = 0;
unsigned in_start = id << BASE_EXP;
if (in_start < seq_length)
{
for (unsigned i = in_start; i < in_start + BASE; i++)
{
char nucleobase = sequence[i];
result += nucleobase != '-';
}
}
dest[id] = result;
}
}
__global__ void k_cadd(unsigned *buffer, unsigned doff, unsigned soff)
{
unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
unsigned in_start = soff + (id << BASE_EXP);
unsigned out_pos = doff + id;
unsigned result = 0;
for (unsigned i = in_start; i < in_start + BASE; i++)
{
unsigned value = buffer[i];
result += value;
}
buffer[out_pos] = result;
}
/**
* Rounds a value x up to the next power of 2^exp.
*/
static long round_up_to_power_of_two(long x, int exp)
{
assert(x > 0);
x--;
int i;
for (i = 0; x; i++)
x >>= exp;
for (x = 1; i; i--)
x <<= exp;
return x;
}
/**
* Loads a text file and returns a buffer with the contents.
*/
static char *load_text(const char *filename, long *length_ptr)
{
FILE *fp = fopen(filename, "r");
if (!fp)
{
fprintf(stderr, "Could not load file \"%s\": %s\n", filename, strerror(errno));
return NULL;
}
fseek(fp, 0, SEEK_END);
long length = ftell(fp);
rewind(fp);
long mem_len = length + 1;
if (length_ptr)
*length_ptr = mem_len;
char *content = (char *)calloc(mem_len, 1);
fread(content, 1, length, fp);
fclose(fp);
return content;
}
int main(int argc, char *argv[])
{
dim3 grid1d(NGRID,1,1);
dim3 block1d(NBLOCK,1,1);
unsigned clstsi, clstc, clsto, local_index;
long delta_time;
struct timeval start_time, end_time;
if (argc < 2)
{
fprintf(stderr, "Usage: transalign_killer [--cldev=x.y] <input file>\n");
fprintf(stderr, " --cldev=x.y: x specifies the platform index, y the device index.\n");
return 1;
}
long seq_length;
//CUDA kernel input
char *sequence = load_text(argv[argc - 1], &seq_length);
if (!sequence)
return 1;
//DEBUG
for (int i=0; i<seq_length; ++i)
{
printf("%c", sequence[i]);
}
printf("\n");
seq_length--; // Cut final 0 byte
// FIXME: All the following code relies on seq_length being a multiple of BASE.
long round_seq_length = round_up_to_power_of_two(seq_length, BASE_EXP);
long res_length = 0;
for (long len = round_seq_length / BASE; len; len /= BASE)
res_length += len;
printf("res_length: %d\n", res_length);
// Use some random index to be searched for here
unsigned letter_index = seq_length / 2;
// Create the result buffer
// CUDA kernel output
unsigned *result = (unsigned *)malloc(res_length * sizeof(unsigned));
unsigned *result_gpu;
char *seq_gpu;
//replace clock_start(); with gettimeofday()
gettimeofday(&start_time, NULL);
#if DEBUG
printf("GPU part started\n");
#endif
/*** START OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
// Bandwidth intensive stuff goes here
// Copy the sequence to the video memory (or, generally speaking, the OpenCL device)
CUDA_CHECK(cudaMalloc((void**)&result_gpu, res_length * sizeof(unsigned)));//result_gpu
CUDA_CHECK(cudaMalloc((void**)&seq_gpu, seq_length*sizeof(char)));//seq_gpu
CUDA_CHECK(cudaMemcpy(seq_gpu, sequence, res_length * sizeof(char), cudaMemcpyHostToDevice));
#if DEBUG
printf("GPU malloc and cpy finised\n");
#endif
//replace clock_delta(); with gettimeofday()
gettimeofday(&end_time, NULL);
long bw1_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// GPU intensive stuff goes here
/**
* First, transform every - and \0 into a 0 and every other character into a
* 1. Then, add consecutive fields (BASE fields) together and store them at
* the beginning of the result buffer.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_iadd launching\n");
#endif
k_iadd<<<grid1d,block1d>>>(result_gpu, seq_gpu, seq_length);
#if DEBUG
printf("k_iadd finished\n");
#endif
CUDA_CHECK(cudaMemcpy(result, result_gpu, res_length * sizeof(unsigned), cudaMemcpyDeviceToHost));
#if DEBUG
printf("result back\n");
for (int i = 0; i < res_length; i++)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
#if DEBUG
printf("k_iadd result back\n");
#endif
unsigned input_offset = 0, output_offset = round_seq_length / BASE;
CUDA_CHECK(cudaMemcpy(result_gpu, result, res_length * sizeof(unsigned), cudaMemcpyHostToDevice));
#if DEBUG
printf("k_cadd loop start\n");
#endif
for (unsigned kernels = round_seq_length / (BASE * BASE); kernels > 0; kernels /= BASE)
{
/**
* Then, do this addition recursively until there is only one kernel
* remaining which calculates the total number of non-'-' and non-'\0'
* characters.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_cadd loop %d\n", kernels);
#endif
k_cadd<<<grid1d,block1d>>>(result_gpu, output_offset, input_offset);
input_offset = output_offset;
output_offset += kernels;
}
#if DEBUG
printf("k_cadd loop end\n");
#endif
// Retrieve the result buffer
#if DEBUG
printf("k_cadd loop end\n");
#endif
CUDA_CHECK(cudaMemcpy(result, result_gpu, res_length * sizeof(unsigned), cudaMemcpyDeviceToHost));
#if DEBUG
printf("k_cadd loop end\n");
#endif
gettimeofday(&end_time, NULL);
long gpu_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// Reverse bandwidth intensive stuff goes here
gettimeofday(&end_time, NULL);
long bw2_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// CPU intensive stuff goes here
#if DEBUG
printf("cpu part start\n");
for (int i=0; i<res_length; ++i)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
if (letter_index > result[res_length - 1])
{
fprintf(stderr, "Logical index out of bounds (last index: %u).\n", result[res_length - 1]);
CUDA_CHECK(cudaFree(result_gpu));
CUDA_CHECK(cudaFree(seq_gpu));
exit(-1);
}
if (!letter_index)
{
fprintf(stderr, "Please used 1-based indexing (for whatever reason).\n");
CUDA_CHECK(cudaFree(result_gpu));
CUDA_CHECK(cudaFree(seq_gpu));
exit(-1);
}
/**
* Okay, now we have a buffer which contains a tree of sums, looking
* something like this:
* _
* 4 |
* / \ |
* 3 1 |- result buffer
* / \ / \ |
* 2 1 1 0 _|
* / \ / \ / \ / \
* A G - T C - - - --- sequence buffer
*
* (actually, it looks more like 2 1 1 2 3 3 6)
*
* Now, we walk through it from the top. Let's assume we're looking for the
* logical index 2. We'll compare it to 4: Of course, it's smaller (that was
* the assertition right before this comment), else, we'd be out of bounds.
* No we're comparing it with the left 3 in the next level. It's smaller,
* therefore, this subtree is correct and we move on to the next level.
* There, we compare it to the left 2. 2 is greater/equal to 2, therefore,
* this is _not_ the right subtree, we have to go to the other one (the one
* to the right, below the 1). We subtract the 2 from the left subtree,
* therefore our new "local" index is 0 (we're looking for the nucleobase at
* index 0 in the subtree below the 1). Now, at the sequence level, there
* are always just two possibilities. Either, the local index is 0 or it is
* 1. If it's 1, this will always mean the right nucleobase, since 1 means
* to skip one. The only one to skip is the left one, therefore, the right
* one is the one we're looking for. If the local index is 0, this refers to
* the first nucleobase, which may be either the left or the right,
* depending on whether the left one is actually a nucleobase.
*
* In this case, the local index is 0. Since the left nucleobase is not
* really one (it is '-'), the right one is the one we're looking for; its
* index in the sequence buffer is 3.
*
* The reference implementation seems to go total hazels, since it
* apparently uses 1-based indexing. Logical index 2 would refer to G for
* it, therefore it returns 2 (which is the 1-based index of G in the
* sequence buffer). I can't see it from the code, but that is what the
* result is.
*
*
* For another BASE than 2, it looks like this (BASE 4):
*
* 9
* // \\
* 3 1 3 2
* // \\ // \\ // \\ // \\
* A G - T C - - - C - T T A G - -
*
* Let's assume, we're looking for index 5. Compare it to 9, it's smaller,
* so this is the tree we're looking for. Then compare it to all subtrees:
* 5 is greater than 3, so go right and subtract 3 from 5. 2 is greater than
* 1, so go right and subtract 1 from 2. 1 then is smaller than 3, so the
* third subtree from the left is the one we want to enter now. The index 1
* here refers to the first T, therefore, it is globally the second T in the
* sequence.
*/
// "Current level subtree starting index"; index of the first subtree sum in
// the current level (we skip level 0, i.e., the complete tree)
clstsi = res_length - 1 - BASE;
// "Current level subtree count"; number of subtrees in the current level
clstc = BASE;
// "Current level subtree offset"; index difference of the actual set of
// subtrees we're using from the first one in the current level
clsto = 0;
// Turn 1-based index into 0-based
local_index = letter_index - 1;
for (;;)
{
int subtree;
// "First subtree index", index of the first subtree we're supposed to
// examine
unsigned fsti = clstsi + clsto * BASE;
// We could add a condition (subtree < BASE) to this loop, but this loop
// has to be left before this condition is false anyway (otherwise,
// something is very wrong).
for (subtree = 0; local_index >= result[fsti + subtree]; subtree++)
local_index -= result[fsti + subtree];
// And we'll check it here anyway (#ifdef NDEBUG).
assert(subtree < BASE);
clsto = clsto * BASE + subtree;
// If clstsi is 0, we were at the beginning of the result buffer and are
// therefore finished
if (!clstsi)
break;
clstc *= BASE;
clstsi -= clstc;
}
// Now we need to go to the sequence level which requires an extra step.
unsigned index;
for (index = clsto * BASE; local_index; index++)
if (sequence[index] != '-')
local_index--;
/*** END OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
//replace with gettimeofday for CUDA
gettimeofday(&end_time, NULL);
delta_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
printf("%li us elapsed total\n", delta_time);
printf(" - %li us on bandwidth forth\n", bw1_time);
printf(" - %li us on GPU\n", gpu_time - bw1_time);
printf(" - %li us on bandwidth back\n", bw2_time - gpu_time);
printf(" - %li us on CPU\n", delta_time - bw2_time);
printf("Index for %u: %u\n", letter_index, index);
printf("cnt = %u (index + 1)\n", index + 1);
//free resource
CUDA_CHECK(cudaFree(result_gpu));
CUDA_CHECK(cudaFree(seq_gpu));
return 0;
} | #include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <sys/time.h>
#define DEBUG 1
#define NGRID 512
#define NBLOCK 65535
#define CUDA_CHECK(cmd) {hipError_t error = cmd; if(error!=hipSuccess){printf("<%s>:%i ",__FILE__,__LINE__); printf("[CUDA] Error: %s\n", hipGetErrorString(error));}}
/* The exponent given here determines the steps taken in the adding kernel. An
* exponent of 1 results in rounding the size to 2^1 = 2, therefore, in every
* step, two input fields are added and the size shrinks to half of what it was
* before. This influences the size of the result buffer as well (the greater
* this exponent is, the smaller the result will be). */
#define BASE_EXP 4
#define BASE (1 << BASE_EXP)
/* Define this to actually use host memory instead of copying the buffer to the
* GPU (as it turns out, this may actually be worth it) */
#define USE_HOST_PTR
#ifdef USE_HOST_PTR
#define HOST_PTR_POLICY CL_MEM_USE_HOST_PTR
#else
#define HOST_PTR_POLICY CL_MEM_COPY_HOST_PTR
#endif
/**
* These two functions provide std::chrono functionality (see cpp-stuff.cpp for
* an explanation why they're extern).
CUDA nvcc don't support it.
extern void clock_start(void);
extern long clock_delta(void);
*/
__global__ void k_iadd(unsigned *dest, char *sequence, unsigned seq_length)
{
for (unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
id < seq_length;
id += blockDim.x*gridDim.x)
{
unsigned result = 0;
unsigned in_start = id << BASE_EXP;
if (in_start < seq_length)
{
for (unsigned i = in_start; i < in_start + BASE; i++)
{
char nucleobase = sequence[i];
result += nucleobase != '-';
}
}
dest[id] = result;
}
}
__global__ void k_cadd(unsigned *buffer, unsigned doff, unsigned soff)
{
unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
unsigned in_start = soff + (id << BASE_EXP);
unsigned out_pos = doff + id;
unsigned result = 0;
for (unsigned i = in_start; i < in_start + BASE; i++)
{
unsigned value = buffer[i];
result += value;
}
buffer[out_pos] = result;
}
/**
* Rounds a value x up to the next power of 2^exp.
*/
static long round_up_to_power_of_two(long x, int exp)
{
assert(x > 0);
x--;
int i;
for (i = 0; x; i++)
x >>= exp;
for (x = 1; i; i--)
x <<= exp;
return x;
}
/**
* Loads a text file and returns a buffer with the contents.
*/
static char *load_text(const char *filename, long *length_ptr)
{
FILE *fp = fopen(filename, "r");
if (!fp)
{
fprintf(stderr, "Could not load file \"%s\": %s\n", filename, strerror(errno));
return NULL;
}
fseek(fp, 0, SEEK_END);
long length = ftell(fp);
rewind(fp);
long mem_len = length + 1;
if (length_ptr)
*length_ptr = mem_len;
char *content = (char *)calloc(mem_len, 1);
fread(content, 1, length, fp);
fclose(fp);
return content;
}
int main(int argc, char *argv[])
{
dim3 grid1d(NGRID,1,1);
dim3 block1d(NBLOCK,1,1);
unsigned clstsi, clstc, clsto, local_index;
long delta_time;
struct timeval start_time, end_time;
if (argc < 2)
{
fprintf(stderr, "Usage: transalign_killer [--cldev=x.y] <input file>\n");
fprintf(stderr, " --cldev=x.y: x specifies the platform index, y the device index.\n");
return 1;
}
long seq_length;
//CUDA kernel input
char *sequence = load_text(argv[argc - 1], &seq_length);
if (!sequence)
return 1;
//DEBUG
for (int i=0; i<seq_length; ++i)
{
printf("%c", sequence[i]);
}
printf("\n");
seq_length--; // Cut final 0 byte
// FIXME: All the following code relies on seq_length being a multiple of BASE.
long round_seq_length = round_up_to_power_of_two(seq_length, BASE_EXP);
long res_length = 0;
for (long len = round_seq_length / BASE; len; len /= BASE)
res_length += len;
printf("res_length: %d\n", res_length);
// Use some random index to be searched for here
unsigned letter_index = seq_length / 2;
// Create the result buffer
// CUDA kernel output
unsigned *result = (unsigned *)malloc(res_length * sizeof(unsigned));
unsigned *result_gpu;
char *seq_gpu;
//replace clock_start(); with gettimeofday()
gettimeofday(&start_time, NULL);
#if DEBUG
printf("GPU part started\n");
#endif
/*** START OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
// Bandwidth intensive stuff goes here
// Copy the sequence to the video memory (or, generally speaking, the OpenCL device)
CUDA_CHECK(hipMalloc((void**)&result_gpu, res_length * sizeof(unsigned)));//result_gpu
CUDA_CHECK(hipMalloc((void**)&seq_gpu, seq_length*sizeof(char)));//seq_gpu
CUDA_CHECK(hipMemcpy(seq_gpu, sequence, res_length * sizeof(char), hipMemcpyHostToDevice));
#if DEBUG
printf("GPU malloc and cpy finised\n");
#endif
//replace clock_delta(); with gettimeofday()
gettimeofday(&end_time, NULL);
long bw1_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// GPU intensive stuff goes here
/**
* First, transform every - and \0 into a 0 and every other character into a
* 1. Then, add consecutive fields (BASE fields) together and store them at
* the beginning of the result buffer.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_iadd launching\n");
#endif
k_iadd<<<grid1d,block1d>>>(result_gpu, seq_gpu, seq_length);
#if DEBUG
printf("k_iadd finished\n");
#endif
CUDA_CHECK(hipMemcpy(result, result_gpu, res_length * sizeof(unsigned), hipMemcpyDeviceToHost));
#if DEBUG
printf("result back\n");
for (int i = 0; i < res_length; i++)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
#if DEBUG
printf("k_iadd result back\n");
#endif
unsigned input_offset = 0, output_offset = round_seq_length / BASE;
CUDA_CHECK(hipMemcpy(result_gpu, result, res_length * sizeof(unsigned), hipMemcpyHostToDevice));
#if DEBUG
printf("k_cadd loop start\n");
#endif
for (unsigned kernels = round_seq_length / (BASE * BASE); kernels > 0; kernels /= BASE)
{
/**
* Then, do this addition recursively until there is only one kernel
* remaining which calculates the total number of non-'-' and non-'\0'
* characters.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_cadd loop %d\n", kernels);
#endif
k_cadd<<<grid1d,block1d>>>(result_gpu, output_offset, input_offset);
input_offset = output_offset;
output_offset += kernels;
}
#if DEBUG
printf("k_cadd loop end\n");
#endif
// Retrieve the result buffer
#if DEBUG
printf("k_cadd loop end\n");
#endif
CUDA_CHECK(hipMemcpy(result, result_gpu, res_length * sizeof(unsigned), hipMemcpyDeviceToHost));
#if DEBUG
printf("k_cadd loop end\n");
#endif
gettimeofday(&end_time, NULL);
long gpu_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// Reverse bandwidth intensive stuff goes here
gettimeofday(&end_time, NULL);
long bw2_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// CPU intensive stuff goes here
#if DEBUG
printf("cpu part start\n");
for (int i=0; i<res_length; ++i)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
if (letter_index > result[res_length - 1])
{
fprintf(stderr, "Logical index out of bounds (last index: %u).\n", result[res_length - 1]);
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
exit(-1);
}
if (!letter_index)
{
fprintf(stderr, "Please used 1-based indexing (for whatever reason).\n");
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
exit(-1);
}
/**
* Okay, now we have a buffer which contains a tree of sums, looking
* something like this:
* _
* 4 |
* / \ |
* 3 1 |- result buffer
* / \ / \ |
* 2 1 1 0 _|
* / \ / \ / \ / \
* A G - T C - - - --- sequence buffer
*
* (actually, it looks more like 2 1 1 2 3 3 6)
*
* Now, we walk through it from the top. Let's assume we're looking for the
* logical index 2. We'll compare it to 4: Of course, it's smaller (that was
* the assertition right before this comment), else, we'd be out of bounds.
* No we're comparing it with the left 3 in the next level. It's smaller,
* therefore, this subtree is correct and we move on to the next level.
* There, we compare it to the left 2. 2 is greater/equal to 2, therefore,
* this is _not_ the right subtree, we have to go to the other one (the one
* to the right, below the 1). We subtract the 2 from the left subtree,
* therefore our new "local" index is 0 (we're looking for the nucleobase at
* index 0 in the subtree below the 1). Now, at the sequence level, there
* are always just two possibilities. Either, the local index is 0 or it is
* 1. If it's 1, this will always mean the right nucleobase, since 1 means
* to skip one. The only one to skip is the left one, therefore, the right
* one is the one we're looking for. If the local index is 0, this refers to
* the first nucleobase, which may be either the left or the right,
* depending on whether the left one is actually a nucleobase.
*
* In this case, the local index is 0. Since the left nucleobase is not
* really one (it is '-'), the right one is the one we're looking for; its
* index in the sequence buffer is 3.
*
* The reference implementation seems to go total hazels, since it
* apparently uses 1-based indexing. Logical index 2 would refer to G for
* it, therefore it returns 2 (which is the 1-based index of G in the
* sequence buffer). I can't see it from the code, but that is what the
* result is.
*
*
* For another BASE than 2, it looks like this (BASE 4):
*
* 9
* // \\
* 3 1 3 2
* // \\ // \\ // \\ // \\
* A G - T C - - - C - T T A G - -
*
* Let's assume, we're looking for index 5. Compare it to 9, it's smaller,
* so this is the tree we're looking for. Then compare it to all subtrees:
* 5 is greater than 3, so go right and subtract 3 from 5. 2 is greater than
* 1, so go right and subtract 1 from 2. 1 then is smaller than 3, so the
* third subtree from the left is the one we want to enter now. The index 1
* here refers to the first T, therefore, it is globally the second T in the
* sequence.
*/
// "Current level subtree starting index"; index of the first subtree sum in
// the current level (we skip level 0, i.e., the complete tree)
clstsi = res_length - 1 - BASE;
// "Current level subtree count"; number of subtrees in the current level
clstc = BASE;
// "Current level subtree offset"; index difference of the actual set of
// subtrees we're using from the first one in the current level
clsto = 0;
// Turn 1-based index into 0-based
local_index = letter_index - 1;
for (;;)
{
int subtree;
// "First subtree index", index of the first subtree we're supposed to
// examine
unsigned fsti = clstsi + clsto * BASE;
// We could add a condition (subtree < BASE) to this loop, but this loop
// has to be left before this condition is false anyway (otherwise,
// something is very wrong).
for (subtree = 0; local_index >= result[fsti + subtree]; subtree++)
local_index -= result[fsti + subtree];
// And we'll check it here anyway (#ifdef NDEBUG).
assert(subtree < BASE);
clsto = clsto * BASE + subtree;
// If clstsi is 0, we were at the beginning of the result buffer and are
// therefore finished
if (!clstsi)
break;
clstc *= BASE;
clstsi -= clstc;
}
// Now we need to go to the sequence level which requires an extra step.
unsigned index;
for (index = clsto * BASE; local_index; index++)
if (sequence[index] != '-')
local_index--;
/*** END OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
//replace with gettimeofday for CUDA
gettimeofday(&end_time, NULL);
delta_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
printf("%li us elapsed total\n", delta_time);
printf(" - %li us on bandwidth forth\n", bw1_time);
printf(" - %li us on GPU\n", gpu_time - bw1_time);
printf(" - %li us on bandwidth back\n", bw2_time - gpu_time);
printf(" - %li us on CPU\n", delta_time - bw2_time);
printf("Index for %u: %u\n", letter_index, index);
printf("cnt = %u (index + 1)\n", index + 1);
//free resource
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <sys/time.h>
#define DEBUG 1
#define NGRID 512
#define NBLOCK 65535
#define CUDA_CHECK(cmd) {hipError_t error = cmd; if(error!=hipSuccess){printf("<%s>:%i ",__FILE__,__LINE__); printf("[CUDA] Error: %s\n", hipGetErrorString(error));}}
/* The exponent given here determines the steps taken in the adding kernel. An
* exponent of 1 results in rounding the size to 2^1 = 2, therefore, in every
* step, two input fields are added and the size shrinks to half of what it was
* before. This influences the size of the result buffer as well (the greater
* this exponent is, the smaller the result will be). */
#define BASE_EXP 4
#define BASE (1 << BASE_EXP)
/* Define this to actually use host memory instead of copying the buffer to the
* GPU (as it turns out, this may actually be worth it) */
#define USE_HOST_PTR
#ifdef USE_HOST_PTR
#define HOST_PTR_POLICY CL_MEM_USE_HOST_PTR
#else
#define HOST_PTR_POLICY CL_MEM_COPY_HOST_PTR
#endif
/**
* These two functions provide std::chrono functionality (see cpp-stuff.cpp for
* an explanation why they're extern).
CUDA nvcc don't support it.
extern void clock_start(void);
extern long clock_delta(void);
*/
__global__ void k_iadd(unsigned *dest, char *sequence, unsigned seq_length)
{
for (unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
id < seq_length;
id += blockDim.x*gridDim.x)
{
unsigned result = 0;
unsigned in_start = id << BASE_EXP;
if (in_start < seq_length)
{
for (unsigned i = in_start; i < in_start + BASE; i++)
{
char nucleobase = sequence[i];
result += nucleobase != '-';
}
}
dest[id] = result;
}
}
__global__ void k_cadd(unsigned *buffer, unsigned doff, unsigned soff)
{
unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
unsigned in_start = soff + (id << BASE_EXP);
unsigned out_pos = doff + id;
unsigned result = 0;
for (unsigned i = in_start; i < in_start + BASE; i++)
{
unsigned value = buffer[i];
result += value;
}
buffer[out_pos] = result;
}
/**
* Rounds a value x up to the next power of 2^exp.
*/
static long round_up_to_power_of_two(long x, int exp)
{
assert(x > 0);
x--;
int i;
for (i = 0; x; i++)
x >>= exp;
for (x = 1; i; i--)
x <<= exp;
return x;
}
/**
* Loads a text file and returns a buffer with the contents.
*/
static char *load_text(const char *filename, long *length_ptr)
{
FILE *fp = fopen(filename, "r");
if (!fp)
{
fprintf(stderr, "Could not load file \"%s\": %s\n", filename, strerror(errno));
return NULL;
}
fseek(fp, 0, SEEK_END);
long length = ftell(fp);
rewind(fp);
long mem_len = length + 1;
if (length_ptr)
*length_ptr = mem_len;
char *content = (char *)calloc(mem_len, 1);
fread(content, 1, length, fp);
fclose(fp);
return content;
}
int main(int argc, char *argv[])
{
dim3 grid1d(NGRID,1,1);
dim3 block1d(NBLOCK,1,1);
unsigned clstsi, clstc, clsto, local_index;
long delta_time;
struct timeval start_time, end_time;
if (argc < 2)
{
fprintf(stderr, "Usage: transalign_killer [--cldev=x.y] <input file>\n");
fprintf(stderr, " --cldev=x.y: x specifies the platform index, y the device index.\n");
return 1;
}
long seq_length;
//CUDA kernel input
char *sequence = load_text(argv[argc - 1], &seq_length);
if (!sequence)
return 1;
//DEBUG
for (int i=0; i<seq_length; ++i)
{
printf("%c", sequence[i]);
}
printf("\n");
seq_length--; // Cut final 0 byte
// FIXME: All the following code relies on seq_length being a multiple of BASE.
long round_seq_length = round_up_to_power_of_two(seq_length, BASE_EXP);
long res_length = 0;
for (long len = round_seq_length / BASE; len; len /= BASE)
res_length += len;
printf("res_length: %d\n", res_length);
// Use some random index to be searched for here
unsigned letter_index = seq_length / 2;
// Create the result buffer
// CUDA kernel output
unsigned *result = (unsigned *)malloc(res_length * sizeof(unsigned));
unsigned *result_gpu;
char *seq_gpu;
//replace clock_start(); with gettimeofday()
gettimeofday(&start_time, NULL);
#if DEBUG
printf("GPU part started\n");
#endif
/*** START OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
// Bandwidth intensive stuff goes here
// Copy the sequence to the video memory (or, generally speaking, the OpenCL device)
CUDA_CHECK(hipMalloc((void**)&result_gpu, res_length * sizeof(unsigned)));//result_gpu
CUDA_CHECK(hipMalloc((void**)&seq_gpu, seq_length*sizeof(char)));//seq_gpu
CUDA_CHECK(hipMemcpy(seq_gpu, sequence, res_length * sizeof(char), hipMemcpyHostToDevice));
#if DEBUG
printf("GPU malloc and cpy finised\n");
#endif
//replace clock_delta(); with gettimeofday()
gettimeofday(&end_time, NULL);
long bw1_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// GPU intensive stuff goes here
/**
* First, transform every - and \0 into a 0 and every other character into a
* 1. Then, add consecutive fields (BASE fields) together and store them at
* the beginning of the result buffer.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_iadd launching\n");
#endif
k_iadd<<<grid1d,block1d>>>(result_gpu, seq_gpu, seq_length);
#if DEBUG
printf("k_iadd finished\n");
#endif
CUDA_CHECK(hipMemcpy(result, result_gpu, res_length * sizeof(unsigned), hipMemcpyDeviceToHost));
#if DEBUG
printf("result back\n");
for (int i = 0; i < res_length; i++)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
#if DEBUG
printf("k_iadd result back\n");
#endif
unsigned input_offset = 0, output_offset = round_seq_length / BASE;
CUDA_CHECK(hipMemcpy(result_gpu, result, res_length * sizeof(unsigned), hipMemcpyHostToDevice));
#if DEBUG
printf("k_cadd loop start\n");
#endif
for (unsigned kernels = round_seq_length / (BASE * BASE); kernels > 0; kernels /= BASE)
{
/**
* Then, do this addition recursively until there is only one kernel
* remaining which calculates the total number of non-'-' and non-'\0'
* characters.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_cadd loop %d\n", kernels);
#endif
k_cadd<<<grid1d,block1d>>>(result_gpu, output_offset, input_offset);
input_offset = output_offset;
output_offset += kernels;
}
#if DEBUG
printf("k_cadd loop end\n");
#endif
// Retrieve the result buffer
#if DEBUG
printf("k_cadd loop end\n");
#endif
CUDA_CHECK(hipMemcpy(result, result_gpu, res_length * sizeof(unsigned), hipMemcpyDeviceToHost));
#if DEBUG
printf("k_cadd loop end\n");
#endif
gettimeofday(&end_time, NULL);
long gpu_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// Reverse bandwidth intensive stuff goes here
gettimeofday(&end_time, NULL);
long bw2_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// CPU intensive stuff goes here
#if DEBUG
printf("cpu part start\n");
for (int i=0; i<res_length; ++i)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
if (letter_index > result[res_length - 1])
{
fprintf(stderr, "Logical index out of bounds (last index: %u).\n", result[res_length - 1]);
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
exit(-1);
}
if (!letter_index)
{
fprintf(stderr, "Please used 1-based indexing (for whatever reason).\n");
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
exit(-1);
}
/**
* Okay, now we have a buffer which contains a tree of sums, looking
* something like this:
* _
* 4 |
* / \ |
* 3 1 |- result buffer
* / \ / \ |
* 2 1 1 0 _|
* / \ / \ / \ / \
* A G - T C - - - --- sequence buffer
*
* (actually, it looks more like 2 1 1 2 3 3 6)
*
* Now, we walk through it from the top. Let's assume we're looking for the
* logical index 2. We'll compare it to 4: Of course, it's smaller (that was
* the assertition right before this comment), else, we'd be out of bounds.
* No we're comparing it with the left 3 in the next level. It's smaller,
* therefore, this subtree is correct and we move on to the next level.
* There, we compare it to the left 2. 2 is greater/equal to 2, therefore,
* this is _not_ the right subtree, we have to go to the other one (the one
* to the right, below the 1). We subtract the 2 from the left subtree,
* therefore our new "local" index is 0 (we're looking for the nucleobase at
* index 0 in the subtree below the 1). Now, at the sequence level, there
* are always just two possibilities. Either, the local index is 0 or it is
* 1. If it's 1, this will always mean the right nucleobase, since 1 means
* to skip one. The only one to skip is the left one, therefore, the right
* one is the one we're looking for. If the local index is 0, this refers to
* the first nucleobase, which may be either the left or the right,
* depending on whether the left one is actually a nucleobase.
*
* In this case, the local index is 0. Since the left nucleobase is not
* really one (it is '-'), the right one is the one we're looking for; its
* index in the sequence buffer is 3.
*
* The reference implementation seems to go total hazels, since it
* apparently uses 1-based indexing. Logical index 2 would refer to G for
* it, therefore it returns 2 (which is the 1-based index of G in the
* sequence buffer). I can't see it from the code, but that is what the
* result is.
*
*
* For another BASE than 2, it looks like this (BASE 4):
*
* 9
* // \\
* 3 1 3 2
* // \\ // \\ // \\ // \\
* A G - T C - - - C - T T A G - -
*
* Let's assume, we're looking for index 5. Compare it to 9, it's smaller,
* so this is the tree we're looking for. Then compare it to all subtrees:
* 5 is greater than 3, so go right and subtract 3 from 5. 2 is greater than
* 1, so go right and subtract 1 from 2. 1 then is smaller than 3, so the
* third subtree from the left is the one we want to enter now. The index 1
* here refers to the first T, therefore, it is globally the second T in the
* sequence.
*/
// "Current level subtree starting index"; index of the first subtree sum in
// the current level (we skip level 0, i.e., the complete tree)
clstsi = res_length - 1 - BASE;
// "Current level subtree count"; number of subtrees in the current level
clstc = BASE;
// "Current level subtree offset"; index difference of the actual set of
// subtrees we're using from the first one in the current level
clsto = 0;
// Turn 1-based index into 0-based
local_index = letter_index - 1;
for (;;)
{
int subtree;
// "First subtree index", index of the first subtree we're supposed to
// examine
unsigned fsti = clstsi + clsto * BASE;
// We could add a condition (subtree < BASE) to this loop, but this loop
// has to be left before this condition is false anyway (otherwise,
// something is very wrong).
for (subtree = 0; local_index >= result[fsti + subtree]; subtree++)
local_index -= result[fsti + subtree];
// And we'll check it here anyway (#ifdef NDEBUG).
assert(subtree < BASE);
clsto = clsto * BASE + subtree;
// If clstsi is 0, we were at the beginning of the result buffer and are
// therefore finished
if (!clstsi)
break;
clstc *= BASE;
clstsi -= clstc;
}
// Now we need to go to the sequence level which requires an extra step.
unsigned index;
for (index = clsto * BASE; local_index; index++)
if (sequence[index] != '-')
local_index--;
/*** END OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
//replace with gettimeofday for CUDA
gettimeofday(&end_time, NULL);
delta_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
printf("%li us elapsed total\n", delta_time);
printf(" - %li us on bandwidth forth\n", bw1_time);
printf(" - %li us on GPU\n", gpu_time - bw1_time);
printf(" - %li us on bandwidth back\n", bw2_time - gpu_time);
printf(" - %li us on CPU\n", delta_time - bw2_time);
printf("Index for %u: %u\n", letter_index, index);
printf("cnt = %u (index + 1)\n", index + 1);
//free resource
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6k_iaddPjPcj
.globl _Z6k_iaddPjPcj
.p2align 8
.type _Z6k_iaddPjPcj,@function
_Z6k_iaddPjPcj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_9
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 4, v1
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s2, s1, 4
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s9
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_nc_u32_e32 v0, s2, v0
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
s_or_b32 s3, vcc_lo, s3
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_9
.LBB0_4:
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v6, 4, v1
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v6
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v5, 0
s_mov_b32 s10, exec_lo
v_cmpx_ne_u32_e32 -16, v6
s_cbranch_execz .LBB0_2
v_add_co_u32 v3, s0, s6, v0
v_add_nc_u32_e32 v7, 16, v6
v_add_co_ci_u32_e64 v4, null, s7, 0, s0
v_mov_b32_e32 v5, 0
s_mov_b32 s11, 0
.LBB0_7:
global_load_u8 v8, v[3:4], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v3, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v6, v7
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e64 s0, 45, v8
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s11
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6k_iaddPjPcj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6k_iaddPjPcj, .Lfunc_end0-_Z6k_iaddPjPcj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6k_caddPjjj
.globl _Z6k_caddPjjj
.p2align 8
.type _Z6k_caddPjjj,@function
_Z6k_caddPjjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v0, 0
v_lshl_add_u32 v2, v1, 4, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 -16, v2
s_cbranch_execz .LBB1_4
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, 0
v_add_nc_u32_e32 v5, 16, v2
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB1_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s2, v2, v5
s_or_b32 s6, s2, s6
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s6
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s0, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6k_caddPjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6k_caddPjjj, .Lfunc_end1-_Z6k_caddPjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6k_iaddPjPcj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6k_iaddPjPcj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6k_caddPjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6k_caddPjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <sys/time.h>
#define DEBUG 1
#define NGRID 512
#define NBLOCK 65535
#define CUDA_CHECK(cmd) {hipError_t error = cmd; if(error!=hipSuccess){printf("<%s>:%i ",__FILE__,__LINE__); printf("[CUDA] Error: %s\n", hipGetErrorString(error));}}
/* The exponent given here determines the steps taken in the adding kernel. An
* exponent of 1 results in rounding the size to 2^1 = 2, therefore, in every
* step, two input fields are added and the size shrinks to half of what it was
* before. This influences the size of the result buffer as well (the greater
* this exponent is, the smaller the result will be). */
#define BASE_EXP 4
#define BASE (1 << BASE_EXP)
/* Define this to actually use host memory instead of copying the buffer to the
* GPU (as it turns out, this may actually be worth it) */
#define USE_HOST_PTR
#ifdef USE_HOST_PTR
#define HOST_PTR_POLICY CL_MEM_USE_HOST_PTR
#else
#define HOST_PTR_POLICY CL_MEM_COPY_HOST_PTR
#endif
/**
* These two functions provide std::chrono functionality (see cpp-stuff.cpp for
* an explanation why they're extern).
CUDA nvcc don't support it.
extern void clock_start(void);
extern long clock_delta(void);
*/
__global__ void k_iadd(unsigned *dest, char *sequence, unsigned seq_length)
{
for (unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
id < seq_length;
id += blockDim.x*gridDim.x)
{
unsigned result = 0;
unsigned in_start = id << BASE_EXP;
if (in_start < seq_length)
{
for (unsigned i = in_start; i < in_start + BASE; i++)
{
char nucleobase = sequence[i];
result += nucleobase != '-';
}
}
dest[id] = result;
}
}
__global__ void k_cadd(unsigned *buffer, unsigned doff, unsigned soff)
{
unsigned id = blockIdx.x*blockDim.x+threadIdx.x;
unsigned in_start = soff + (id << BASE_EXP);
unsigned out_pos = doff + id;
unsigned result = 0;
for (unsigned i = in_start; i < in_start + BASE; i++)
{
unsigned value = buffer[i];
result += value;
}
buffer[out_pos] = result;
}
/**
* Rounds a value x up to the next power of 2^exp.
*/
static long round_up_to_power_of_two(long x, int exp)
{
assert(x > 0);
x--;
int i;
for (i = 0; x; i++)
x >>= exp;
for (x = 1; i; i--)
x <<= exp;
return x;
}
/**
* Loads a text file and returns a buffer with the contents.
*/
static char *load_text(const char *filename, long *length_ptr)
{
FILE *fp = fopen(filename, "r");
if (!fp)
{
fprintf(stderr, "Could not load file \"%s\": %s\n", filename, strerror(errno));
return NULL;
}
fseek(fp, 0, SEEK_END);
long length = ftell(fp);
rewind(fp);
long mem_len = length + 1;
if (length_ptr)
*length_ptr = mem_len;
char *content = (char *)calloc(mem_len, 1);
fread(content, 1, length, fp);
fclose(fp);
return content;
}
int main(int argc, char *argv[])
{
dim3 grid1d(NGRID,1,1);
dim3 block1d(NBLOCK,1,1);
unsigned clstsi, clstc, clsto, local_index;
long delta_time;
struct timeval start_time, end_time;
if (argc < 2)
{
fprintf(stderr, "Usage: transalign_killer [--cldev=x.y] <input file>\n");
fprintf(stderr, " --cldev=x.y: x specifies the platform index, y the device index.\n");
return 1;
}
long seq_length;
//CUDA kernel input
char *sequence = load_text(argv[argc - 1], &seq_length);
if (!sequence)
return 1;
//DEBUG
for (int i=0; i<seq_length; ++i)
{
printf("%c", sequence[i]);
}
printf("\n");
seq_length--; // Cut final 0 byte
// FIXME: All the following code relies on seq_length being a multiple of BASE.
long round_seq_length = round_up_to_power_of_two(seq_length, BASE_EXP);
long res_length = 0;
for (long len = round_seq_length / BASE; len; len /= BASE)
res_length += len;
printf("res_length: %d\n", res_length);
// Use some random index to be searched for here
unsigned letter_index = seq_length / 2;
// Create the result buffer
// CUDA kernel output
unsigned *result = (unsigned *)malloc(res_length * sizeof(unsigned));
unsigned *result_gpu;
char *seq_gpu;
//replace clock_start(); with gettimeofday()
gettimeofday(&start_time, NULL);
#if DEBUG
printf("GPU part started\n");
#endif
/*** START OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
// Bandwidth intensive stuff goes here
// Copy the sequence to the video memory (or, generally speaking, the OpenCL device)
CUDA_CHECK(hipMalloc((void**)&result_gpu, res_length * sizeof(unsigned)));//result_gpu
CUDA_CHECK(hipMalloc((void**)&seq_gpu, seq_length*sizeof(char)));//seq_gpu
CUDA_CHECK(hipMemcpy(seq_gpu, sequence, res_length * sizeof(char), hipMemcpyHostToDevice));
#if DEBUG
printf("GPU malloc and cpy finised\n");
#endif
//replace clock_delta(); with gettimeofday()
gettimeofday(&end_time, NULL);
long bw1_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// GPU intensive stuff goes here
/**
* First, transform every - and \0 into a 0 and every other character into a
* 1. Then, add consecutive fields (BASE fields) together and store them at
* the beginning of the result buffer.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_iadd launching\n");
#endif
k_iadd<<<grid1d,block1d>>>(result_gpu, seq_gpu, seq_length);
#if DEBUG
printf("k_iadd finished\n");
#endif
CUDA_CHECK(hipMemcpy(result, result_gpu, res_length * sizeof(unsigned), hipMemcpyDeviceToHost));
#if DEBUG
printf("result back\n");
for (int i = 0; i < res_length; i++)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
#if DEBUG
printf("k_iadd result back\n");
#endif
unsigned input_offset = 0, output_offset = round_seq_length / BASE;
CUDA_CHECK(hipMemcpy(result_gpu, result, res_length * sizeof(unsigned), hipMemcpyHostToDevice));
#if DEBUG
printf("k_cadd loop start\n");
#endif
for (unsigned kernels = round_seq_length / (BASE * BASE); kernels > 0; kernels /= BASE)
{
/**
* Then, do this addition recursively until there is only one kernel
* remaining which calculates the total number of non-'-' and non-'\0'
* characters.
*/
//TODO: ADD correct kernel parameters
#if DEBUG
printf("k_cadd loop %d\n", kernels);
#endif
k_cadd<<<grid1d,block1d>>>(result_gpu, output_offset, input_offset);
input_offset = output_offset;
output_offset += kernels;
}
#if DEBUG
printf("k_cadd loop end\n");
#endif
// Retrieve the result buffer
#if DEBUG
printf("k_cadd loop end\n");
#endif
CUDA_CHECK(hipMemcpy(result, result_gpu, res_length * sizeof(unsigned), hipMemcpyDeviceToHost));
#if DEBUG
printf("k_cadd loop end\n");
#endif
gettimeofday(&end_time, NULL);
long gpu_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// Reverse bandwidth intensive stuff goes here
gettimeofday(&end_time, NULL);
long bw2_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
// CPU intensive stuff goes here
#if DEBUG
printf("cpu part start\n");
for (int i=0; i<res_length; ++i)
{
printf("%d ", result[i]);
}
printf("\n");
#endif
if (letter_index > result[res_length - 1])
{
fprintf(stderr, "Logical index out of bounds (last index: %u).\n", result[res_length - 1]);
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
exit(-1);
}
if (!letter_index)
{
fprintf(stderr, "Please used 1-based indexing (for whatever reason).\n");
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
exit(-1);
}
/**
* Okay, now we have a buffer which contains a tree of sums, looking
* something like this:
* _
* 4 |
* / \ |
* 3 1 |- result buffer
* / \ / \ |
* 2 1 1 0 _|
* / \ / \ / \ / \
* A G - T C - - - --- sequence buffer
*
* (actually, it looks more like 2 1 1 2 3 3 6)
*
* Now, we walk through it from the top. Let's assume we're looking for the
* logical index 2. We'll compare it to 4: Of course, it's smaller (that was
* the assertition right before this comment), else, we'd be out of bounds.
* No we're comparing it with the left 3 in the next level. It's smaller,
* therefore, this subtree is correct and we move on to the next level.
* There, we compare it to the left 2. 2 is greater/equal to 2, therefore,
* this is _not_ the right subtree, we have to go to the other one (the one
* to the right, below the 1). We subtract the 2 from the left subtree,
* therefore our new "local" index is 0 (we're looking for the nucleobase at
* index 0 in the subtree below the 1). Now, at the sequence level, there
* are always just two possibilities. Either, the local index is 0 or it is
* 1. If it's 1, this will always mean the right nucleobase, since 1 means
* to skip one. The only one to skip is the left one, therefore, the right
* one is the one we're looking for. If the local index is 0, this refers to
* the first nucleobase, which may be either the left or the right,
* depending on whether the left one is actually a nucleobase.
*
* In this case, the local index is 0. Since the left nucleobase is not
* really one (it is '-'), the right one is the one we're looking for; its
* index in the sequence buffer is 3.
*
* The reference implementation seems to go total hazels, since it
* apparently uses 1-based indexing. Logical index 2 would refer to G for
* it, therefore it returns 2 (which is the 1-based index of G in the
* sequence buffer). I can't see it from the code, but that is what the
* result is.
*
*
* For another BASE than 2, it looks like this (BASE 4):
*
* 9
* // \\
* 3 1 3 2
* // \\ // \\ // \\ // \\
* A G - T C - - - C - T T A G - -
*
* Let's assume, we're looking for index 5. Compare it to 9, it's smaller,
* so this is the tree we're looking for. Then compare it to all subtrees:
* 5 is greater than 3, so go right and subtract 3 from 5. 2 is greater than
* 1, so go right and subtract 1 from 2. 1 then is smaller than 3, so the
* third subtree from the left is the one we want to enter now. The index 1
* here refers to the first T, therefore, it is globally the second T in the
* sequence.
*/
// "Current level subtree starting index"; index of the first subtree sum in
// the current level (we skip level 0, i.e., the complete tree)
clstsi = res_length - 1 - BASE;
// "Current level subtree count"; number of subtrees in the current level
clstc = BASE;
// "Current level subtree offset"; index difference of the actual set of
// subtrees we're using from the first one in the current level
clsto = 0;
// Turn 1-based index into 0-based
local_index = letter_index - 1;
for (;;)
{
int subtree;
// "First subtree index", index of the first subtree we're supposed to
// examine
unsigned fsti = clstsi + clsto * BASE;
// We could add a condition (subtree < BASE) to this loop, but this loop
// has to be left before this condition is false anyway (otherwise,
// something is very wrong).
for (subtree = 0; local_index >= result[fsti + subtree]; subtree++)
local_index -= result[fsti + subtree];
// And we'll check it here anyway (#ifdef NDEBUG).
assert(subtree < BASE);
clsto = clsto * BASE + subtree;
// If clstsi is 0, we were at the beginning of the result buffer and are
// therefore finished
if (!clstsi)
break;
clstc *= BASE;
clstsi -= clstc;
}
// Now we need to go to the sequence level which requires an extra step.
unsigned index;
for (index = clsto * BASE; local_index; index++)
if (sequence[index] != '-')
local_index--;
/*** END OF ROCKET SCIENCE LEVEL RUNTIME-TIME INTENSIVE STUFF ***/
//replace with gettimeofday for CUDA
gettimeofday(&end_time, NULL);
delta_time = (end_time.tv_sec*1000000+end_time.tv_usec) - (start_time.tv_sec*1000000+start_time.tv_usec);
printf("%li us elapsed total\n", delta_time);
printf(" - %li us on bandwidth forth\n", bw1_time);
printf(" - %li us on GPU\n", gpu_time - bw1_time);
printf(" - %li us on bandwidth back\n", bw2_time - gpu_time);
printf(" - %li us on CPU\n", delta_time - bw2_time);
printf("Index for %u: %u\n", letter_index, index);
printf("cnt = %u (index + 1)\n", index + 1);
//free resource
CUDA_CHECK(hipFree(result_gpu));
CUDA_CHECK(hipFree(seq_gpu));
return 0;
} | .text
.file "main.hip"
.globl _Z21__device_stub__k_iaddPjPcj # -- Begin function _Z21__device_stub__k_iaddPjPcj
.p2align 4, 0x90
.type _Z21__device_stub__k_iaddPjPcj,@function
_Z21__device_stub__k_iaddPjPcj: # @_Z21__device_stub__k_iaddPjPcj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6k_iaddPjPcj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__k_iaddPjPcj, .Lfunc_end0-_Z21__device_stub__k_iaddPjPcj
.cfi_endproc
# -- End function
.globl _Z21__device_stub__k_caddPjjj # -- Begin function _Z21__device_stub__k_caddPjjj
.p2align 4, 0x90
.type _Z21__device_stub__k_caddPjjj,@function
_Z21__device_stub__k_caddPjjj: # @_Z21__device_stub__k_caddPjjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6k_caddPjjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__k_caddPjjj, .Lfunc_end1-_Z21__device_stub__k_caddPjjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB2_56
# %bb.1:
movl %edi, %eax
movq -8(%rsi,%rax,8), %rbx
movl $.L.str.28, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB2_57
# %bb.2:
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r15, %rdi
callq ftell
movq %rax, %r12
movq %r15, %rdi
callq rewind
leaq 1(%r12), %r13
movl $1, %esi
movq %r13, %rdi
callq calloc
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %rax, %r12
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
testq %r12, %r12
je .LBB2_58
.LBB2_3: # %.preheader
testq %r13, %r13
jle .LBB2_6
# %bb.4: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbl (%r12,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %r13
jne .LBB2_5
.LBB2_6: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq %r13, %rcx
xorl %eax, %eax
addq $-2, %rcx
je .LBB2_9
# %bb.7: # %.lr.ph.i.preheader
movq %rcx, %rdx
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
sarq $4, %rdx
incl %eax
cmpq $16, %rcx
movq %rdx, %rcx
jae .LBB2_8
.LBB2_9: # %.preheader.i
movl $1, %ebx
testl %eax, %eax
je .LBB2_11
.p2align 4, 0x90
.LBB2_10: # %.lr.ph19.i
# =>This Inner Loop Header: Depth=1
shlq $4, %rbx
decl %eax
jne .LBB2_10
.LBB2_11: # %_ZL24round_up_to_power_of_twoli.exit
leaq 15(%rbx), %rax
testq %rbx, %rbx
movq %rbx, %r14
cmovsq %rax, %r14
sarq $4, %r14
cmpq $31, %rax
movq %r12, 136(%rsp) # 8-byte Spill
jae .LBB2_13
# %bb.12:
xorl %r15d, %r15d
jmp .LBB2_15
.LBB2_13: # %.lr.ph221.preheader
xorl %r15d, %r15d
movq %r14, %rax
.p2align 4, 0x90
.LBB2_14: # %.lr.ph221
# =>This Inner Loop Header: Depth=1
addq %rax, %r15
leaq 15(%rax), %rcx
testq %rax, %rax
cmovsq %rcx, %rax
sarq $4, %rax
cmpq $31, %rcx
jae .LBB2_14
.LBB2_15: # %._crit_edge222
decq %r13
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
leaq (,%r15,4), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %r12
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rdi
movq %rbp, 16(%rsp) # 8-byte Spill
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_17
# %bb.16:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $192, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_17:
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $193, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_19:
movq 24(%rsp), %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_21
# %bb.20:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $194, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_21:
movabsq $4294967808, %rbp # imm = 0x100000200
movl $.Lstr.1, %edi
callq puts@PLT
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %rax # imm = 0xF4240
addq 40(%rsp), %rax
movq %rax, 56(%rsp) # 8-byte Spill
imulq $-1000000, 168(%rsp), %rax # imm = 0xFFF0BDC0
subq 176(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movl $.Lstr.2, %edi
callq puts@PLT
leaq 65023(%rbp), %rdx
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq (%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 88(%rsp)
movl %r13d, 12(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6k_iaddPjPcj, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23:
movq %r13, 48(%rsp) # 8-byte Spill
movl $.Lstr.3, %edi
callq puts@PLT
movq (%rsp), %rsi
movq %r12, %rdi
movq 16(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_25
# %bb.24:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $223, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_25:
movl $.Lstr.4, %edi
callq puts@PLT
testq %r15, %r15
jle .LBB2_28
# %bb.26: # %.lr.ph225.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_27: # %.lr.ph225
# =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r15
jne .LBB2_27
.LBB2_28: # %._crit_edge226
movq 48(%rsp), %r13 # 8-byte Reload
shrq $63, %r13
movl $10, %edi
callq putchar@PLT
movl $.Lstr.5, %edi
callq puts@PLT
movq (%rsp), %rdi
movq %r12, %rsi
movq 16(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_30
# %bb.29:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $238, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_30:
addq %r13, 48(%rsp) # 8-byte Folded Spill
movl $.Lstr.6, %edi
callq puts@PLT
leaq 255(%rbx), %r13
testq %rbx, %rbx
cmovnsq %rbx, %r13
shrq $8, %r13
testl %r13d, %r13d
je .LBB2_35
# %bb.31: # %.lr.ph232
movabsq $4294967808, %rax # imm = 0x100000200
leaq 65023(%rax), %rbp
xorl %ebx, %ebx
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_32: # in Loop: Header=BB2_33 Depth=1
movl %r14d, %ebx
leal (%r14,%r13), %eax
movl %r13d, %ecx
shrl $4, %ecx
movl %eax, %r14d
cmpl $16, %r13d
movl %ecx, %r13d
jb .LBB2_35
.LBB2_33: # =>This Inner Loop Header: Depth=1
movl $.L.str.16, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_32
# %bb.34: # in Loop: Header=BB2_33 Depth=1
movq (%rsp), %rax
movq %rax, 128(%rsp)
movl %r14d, 72(%rsp)
movl %ebx, 12(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z6k_caddPjjj, %edi
leaq 144(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_32
.LBB2_35: # %._crit_edge233
shrq 48(%rsp) # 8-byte Folded Spill
movl $.Lstr.9, %edi
callq puts@PLT
movl $.Lstr.9, %edi
callq puts@PLT
movq (%rsp), %rsi
movq %r12, %rdi
movq 16(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_37
# %bb.36:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $266, %edx # imm = 0x10A
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_37:
movl $.Lstr.9, %edi
callq puts@PLT
leaq 32(%rsp), %r13
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %rax # imm = 0xF4240
movq %rax, 16(%rsp) # 8-byte Spill
movq 40(%rsp), %rbx
movq 64(%rsp), %rbp # 8-byte Reload
addq %rbp, %rbx
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %r13 # imm = 0xF4240
movq 40(%rsp), %r14
addq %rbp, %r14
movl $.Lstr.10, %edi
callq puts@PLT
testq %r15, %r15
jle .LBB2_40
# %bb.38: # %.lr.ph236.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_39: # %.lr.ph236
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbp,4), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r15
jne .LBB2_39
.LBB2_40: # %._crit_edge237
movl $10, %edi
callq putchar@PLT
movl -4(%r12,%r15,4), %edx
movq 48(%rsp), %rsi # 8-byte Reload
cmpl %esi, %edx
jb .LBB2_60
# %bb.41:
testl %esi, %esi
je .LBB2_64
# %bb.42:
movq 56(%rsp), %rax # 8-byte Reload
addq 64(%rsp), %rax # 8-byte Folded Reload
movq %rax, 56(%rsp) # 8-byte Spill
addq 16(%rsp), %rbx # 8-byte Folded Reload
addq %r13, %r14
addl $-17, %r15d
leal -1(%rsi), %eax
movl $16, %ecx
xorl %ebp, %ebp
movq %rsi, %r13
jmp .LBB2_45
.p2align 4, 0x90
.LBB2_43: # in Loop: Header=BB2_45 Depth=1
xorl %ebp, %ebp
.LBB2_44: # %._crit_edge243
# in Loop: Header=BB2_45 Depth=1
addl %edx, %ebp
movl %ecx, %edx
shll $4, %edx
movl %r15d, %esi
subl %edx, %esi
testl %r15d, %r15d
cmovnel %edx, %ecx
cmovel %r15d, %esi
movl %esi, %r15d
je .LBB2_48
.LBB2_45: # =>This Loop Header: Depth=1
# Child Loop BB2_47 Depth 2
movl %ebp, %edx
shll $4, %edx
leal (%r15,%rdx), %esi
movl (%r12,%rsi,4), %esi
cmpl %esi, %eax
jb .LBB2_43
# %bb.46: # %.lr.ph242.preheader
# in Loop: Header=BB2_45 Depth=1
leal (%r15,%rdx), %edi
incl %edi
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_47: # %.lr.ph242
# Parent Loop BB2_45 Depth=1
# => This Inner Loop Header: Depth=2
subl %esi, %eax
leal (%rdi,%rbp), %esi
movl (%r12,%rsi,4), %esi
incl %ebp
cmpl %esi, %eax
jae .LBB2_47
jmp .LBB2_44
.LBB2_48:
shll $4, %ebp
testl %eax, %eax
je .LBB2_51
# %bb.49: # %.lr.ph250.preheader
movq 136(%rsp), %rsi # 8-byte Reload
.p2align 4, 0x90
.LBB2_50: # %.lr.ph250
# =>This Inner Loop Header: Depth=1
movl %ebp, %ecx
xorl %edx, %edx
cmpb $45, (%rsi,%rcx)
setne %dl
incl %ebp
subl %edx, %eax
jne .LBB2_50
.LBB2_51: # %._crit_edge251
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %rax # imm = 0xF4240
movq 64(%rsp), %r15 # 8-byte Reload
addq 40(%rsp), %r15
addq %rax, %r15
movl $.L.str.21, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.22, %edi
movq 56(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rsi
subq %r12, %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movq %r14, %rsi
subq %rbx, %rsi
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
subq %r14, %r15
movl $.L.str.25, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.26, %edi
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
incl %ebp
movl $.L.str.27, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_53
# %bb.52:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $426, %edx # imm = 0x1AA
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_53:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_55
# %bb.54:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $427, %edx # imm = 0x1AB
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_55:
xorl %eax, %eax
jmp .LBB2_59
.LBB2_56:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $52, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $67, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_58
.LBB2_57:
movq stderr(%rip), %r15
callq __errno_location
movl (%rax), %edi
callq strerror
xorl %r12d, %r12d
movl $.L.str.29, %esi
movq %r15, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
# implicit-def: $r13
testq %r12, %r12
jne .LBB2_3
.LBB2_58:
movl $1, %eax
.LBB2_59:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_60:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rdi
movl $.L.str.19, %esi
xorl %eax, %eax
callq fprintf
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_62
# %bb.61:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $292, %edx # imm = 0x124
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_62:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_69
# %bb.63:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $293, %edx # imm = 0x125
jmp .LBB2_68
.LBB2_64:
movq stderr(%rip), %rcx
movl $.L.str.20, %edi
movl $52, %esi
movl $1, %edx
callq fwrite@PLT
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_66
# %bb.65:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $300, %edx # imm = 0x12C
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_66:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_69
# %bb.67:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $301, %edx # imm = 0x12D
.LBB2_68:
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_69:
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6k_iaddPjPcj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6k_caddPjjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6k_iaddPjPcj,@object # @_Z6k_iaddPjPcj
.section .rodata,"a",@progbits
.globl _Z6k_iaddPjPcj
.p2align 3, 0x0
_Z6k_iaddPjPcj:
.quad _Z21__device_stub__k_iaddPjPcj
.size _Z6k_iaddPjPcj, 8
.type _Z6k_caddPjjj,@object # @_Z6k_caddPjjj
.globl _Z6k_caddPjjj
.p2align 3, 0x0
_Z6k_caddPjjj:
.quad _Z21__device_stub__k_caddPjjj
.size _Z6k_caddPjjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: transalign_killer [--cldev=x.y] <input file>\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " --cldev=x.y: x specifies the platform index, y the device index.\n"
.size .L.str.1, 68
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "res_length: %d\n"
.size .L.str.4, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "<%s>:%i "
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/XanClic/transalign-killer/master/cuda/main.hip"
.size .L.str.7, 104
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "[CUDA] Error: %s\n"
.size .L.str.8, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d "
.size .L.str.13, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "k_cadd loop %d\n"
.size .L.str.16, 16
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Logical index out of bounds (last index: %u).\n"
.size .L.str.19, 47
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Please used 1-based indexing (for whatever reason).\n"
.size .L.str.20, 53
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "%li us elapsed total\n"
.size .L.str.21, 22
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " - %li us on bandwidth forth\n"
.size .L.str.22, 30
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " - %li us on GPU\n"
.size .L.str.23, 18
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " - %li us on bandwidth back\n"
.size .L.str.24, 29
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " - %li us on CPU\n"
.size .L.str.25, 18
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Index for %u: %u\n"
.size .L.str.26, 18
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "cnt = %u (index + 1)\n"
.size .L.str.27, 22
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "r"
.size .L.str.28, 2
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Could not load file \"%s\": %s\n"
.size .L.str.29, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6k_iaddPjPcj"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6k_caddPjjj"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU part started"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "GPU malloc and cpy finised"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "k_iadd launching"
.size .Lstr.2, 17
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "k_iadd finished"
.size .Lstr.3, 16
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "result back"
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "k_iadd result back"
.size .Lstr.5, 19
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "k_cadd loop start"
.size .Lstr.6, 18
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "k_cadd loop end"
.size .Lstr.9, 16
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "cpu part start"
.size .Lstr.10, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__k_iaddPjPcj
.addrsig_sym _Z21__device_stub__k_caddPjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6k_iaddPjPcj
.addrsig_sym _Z6k_caddPjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006f486_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6k_iaddPjPcjPjPcj
.type _Z28__device_stub__Z6k_iaddPjPcjPjPcj, @function
_Z28__device_stub__Z6k_iaddPjPcjPjPcj:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6k_iaddPjPcj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z6k_iaddPjPcjPjPcj, .-_Z28__device_stub__Z6k_iaddPjPcjPjPcj
.globl _Z6k_iaddPjPcj
.type _Z6k_iaddPjPcj, @function
_Z6k_iaddPjPcj:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6k_iaddPjPcjPjPcj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6k_iaddPjPcj, .-_Z6k_iaddPjPcj
.globl _Z27__device_stub__Z6k_caddPjjjPjjj
.type _Z27__device_stub__Z6k_caddPjjjPjjj, @function
_Z27__device_stub__Z6k_caddPjjjPjjj:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6k_caddPjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z27__device_stub__Z6k_caddPjjjPjjj, .-_Z27__device_stub__Z6k_caddPjjjPjjj
.globl _Z6k_caddPjjj
.type _Z6k_caddPjjj, @function
_Z6k_caddPjjj:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6k_caddPjjjPjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6k_caddPjjj, .-_Z6k_caddPjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: transalign_killer [--cldev=x.y] <input file>\n"
.align 8
.LC1:
.string " --cldev=x.y: x specifies the platform index, y the device index.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "r"
.LC3:
.string "Could not load file \"%s\": %s\n"
.LC4:
.string "%c"
.LC5:
.string "\n"
.LC6:
.string "res_length: %d\n"
.LC7:
.string "GPU part started\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/XanClic/transalign-killer/master/cuda/main.cu"
.section .rodata.str1.1
.LC9:
.string "<%s>:%i "
.LC10:
.string "[CUDA] Error: %s\n"
.LC11:
.string "GPU malloc and cpy finised\n"
.LC12:
.string "k_iadd launching\n"
.LC13:
.string "k_iadd finished\n"
.LC14:
.string "result back\n"
.LC15:
.string "%d "
.LC16:
.string "k_iadd result back\n"
.LC17:
.string "k_cadd loop start\n"
.LC18:
.string "k_cadd loop %d\n"
.LC19:
.string "k_cadd loop end\n"
.LC20:
.string "cpu part start\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Logical index out of bounds (last index: %u).\n"
.align 8
.LC22:
.string "Please used 1-based indexing (for whatever reason).\n"
.section .rodata.str1.1
.LC23:
.string "%li us elapsed total\n"
.LC24:
.string " - %li us on bandwidth forth\n"
.LC25:
.string " - %li us on GPU\n"
.LC26:
.string " - %li us on bandwidth back\n"
.LC27:
.string " - %li us on CPU\n"
.LC28:
.string "Index for %u: %u\n"
.LC29:
.string "cnt = %u (index + 1)\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $512, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $65535, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
cmpl $1, %edi
jle .L75
movslq %edi, %rdi
movq -8(%rsi,%rdi,8), %rbp
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L76
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbx, %rdi
call ftell@PLT
movq %rax, %r12
movq %rbx, %rdi
call rewind@PLT
leaq 1(%r12), %rbp
movl $1, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, %r15
movq %rax, (%rsp)
movq %rbx, %r8
movq %r12, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
testq %r15, %r15
je .L60
testq %rbp, %rbp
jle .L23
movq %r15, %rbx
leaq (%r15,%r12), %r13
leaq .LC4(%rip), %rbp
.L24:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %r13, %rax
jne .L24
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbp
subq $1, %rbp
je .L61
.L58:
movl $0, %eax
.L26:
addl $1, %eax
sarq $4, %rbp
jne .L26
testl %eax, %eax
je .L62
movl $1, %r14d
.L27:
salq $4, %r14
subl $1, %eax
jne .L27
movl $16, %ecx
movq %r14, %rax
cqto
idivq %rcx
movq %rax, 24(%rsp)
testq %rax, %rax
je .L63
.L28:
addq %rax, %rbp
leaq 15(%rax), %rdx
testq %rax, %rax
cmovns %rax, %rdx
sarq $4, %rdx
movq %rdx, %rax
jne .L28
.L25:
movq %rbp, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r12, %rax
cqto
idivq %rcx
movq %rax, 16(%rsp)
movl %eax, 36(%rsp)
movq %rbp, %r15
leaq 0(,%rbp,4), %r13
movq %r13, 8(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L77
.L29:
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L78
.L30:
movl $1, %ecx
movq %r15, %rdx
movq (%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L79
.L31:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %rdx
addq 120(%rsp), %rdx
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %rdx
movq %rdx, 40(%rsp)
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L32:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L81
.L33:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbp, %rbp
jle .L34
movl $0, %r12d
leaq .LC15(%rip), %r13
.L35:
movl (%rbx,%r12,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq %r12, %r15
jne .L35
.L34:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %r13d
movl $1, %ecx
movq 8(%rsp), %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L82
.L36:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, %ecx
movq %r14, %rax
cqto
idivq %rcx
movl %eax, %r12d
testl %eax, %eax
je .L37
movl $0, %eax
leaq .LC18(%rip), %r14
movq %rbx, 24(%rsp)
movl %eax, %ebx
jmp .L39
.L75:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L19
.L76:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %r8
movq %rbp, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L19
.L61:
movq %rbp, 24(%rsp)
movl $1, %r14d
jmp .L25
.L62:
movq %rbp, 24(%rsp)
movl $1, %r14d
jmp .L25
.L63:
movq %rax, %rbp
jmp .L25
.L77:
movl $192, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L78:
movl $193, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L79:
movl $194, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L80:
movl %r12d, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z28__device_stub__Z6k_iaddPjPcjPjPcj
jmp .L32
.L81:
movl $223, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L82:
movl $238, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L38:
leal 0(%r13,%r12), %edx
movl %r12d, %eax
shrl $4, %eax
movl %r13d, %ebx
cmpl $15, %r12d
jbe .L83
movl %eax, %r12d
movl %edx, %r13d
.L39:
movl %r12d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L38
movl %ebx, %edx
movl %r13d, %esi
movq 56(%rsp), %rdi
call _Z27__device_stub__Z6k_caddPjjjPjjj
jmp .L38
.L83:
movq 24(%rsp), %rbx
.L37:
leaq .LC19(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L84
.L40:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %rax
addq 120(%rsp), %rax
movq %rax, %rdx
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %rdx
movq %rdx, 24(%rsp)
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %r14
addq 120(%rsp), %r14
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %r14
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbp, %rbp
jle .L41
movl $0, %r12d
leaq .LC15(%rip), %r13
.L42:
movl (%rbx,%r12,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq %r12, %r15
jne .L42
.L41:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl -4(%rbx,%rax), %ecx
movl 16(%rsp), %eax
cmpl %eax, %ecx
jb .L85
cmpl $0, 16(%rsp)
je .L86
subl $17, %ebp
movl 16(%rsp), %edx
subl $1, %edx
movl $0, %r8d
movl $16, %r9d
movl $0, %r10d
.L52:
sall $4, %r8d
leal (%r8,%rbp), %esi
movl %esi, %eax
movl (%rbx,%rax,4), %ecx
cmpl %ecx, %edx
jb .L65
movl $0, %eax
.L50:
subl %ecx, %edx
addl $1, %eax
movl %eax, %edi
leal (%rsi,%rax), %ecx
movl (%rbx,%rcx,4), %ecx
cmpl %ecx, %edx
jnb .L50
.L49:
addl %edi, %r8d
testl %ebp, %ebp
je .L51
sall $4, %r9d
subl %r9d, %ebp
jmp .L52
.L84:
movl $266, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L40
.L85:
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L87
.L44:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L88
.L45:
movl $-1, %edi
call exit@PLT
.L87:
movl $292, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L88:
movl $293, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L86:
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L89
.L47:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L90
.L48:
movl $-1, %edi
call exit@PLT
.L89:
movl $300, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L90:
movl $301, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L65:
movl %r10d, %edi
jmp .L49
.L51:
movl %r8d, %ebx
sall $4, %ebx
testl %edx, %edx
jne .L55
jmp .L53
.L91:
movl $426, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L92:
movl $427, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L19
.L60:
movl $1, %eax
jmp .L19
.L54:
addl $1, %ebx
.L55:
movl %ebx, %eax
movq (%rsp), %rdi
cmpb $45, (%rdi,%rax)
je .L54
addl $1, %ebx
subl $1, %edx
jne .L55
.L53:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 112(%rsp), %rbp
addq 120(%rsp), %rbp
imulq $1000000, 96(%rsp), %rax
addq 104(%rsp), %rax
subq %rax, %rbp
movq %rbp, %rdx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %r13
movq %r13, %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %r15
movq %r15, %rax
subq %r13, %rax
movq %rax, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdx
subq %r15, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
subq %r14, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl 36(%rsp), %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%rbx), %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L91
.L56:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
movl $0, %eax
testl %ebx, %ebx
jne .L92
.L19:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L93
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1(%r12), %rbp
jmp .L58
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC30:
.string "_Z6k_caddPjjj"
.LC31:
.string "_Z6k_iaddPjPcj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z6k_caddPjjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z6k_iaddPjPcj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z21__device_stub__k_iaddPjPcj # -- Begin function _Z21__device_stub__k_iaddPjPcj
.p2align 4, 0x90
.type _Z21__device_stub__k_iaddPjPcj,@function
_Z21__device_stub__k_iaddPjPcj: # @_Z21__device_stub__k_iaddPjPcj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6k_iaddPjPcj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__k_iaddPjPcj, .Lfunc_end0-_Z21__device_stub__k_iaddPjPcj
.cfi_endproc
# -- End function
.globl _Z21__device_stub__k_caddPjjj # -- Begin function _Z21__device_stub__k_caddPjjj
.p2align 4, 0x90
.type _Z21__device_stub__k_caddPjjj,@function
_Z21__device_stub__k_caddPjjj: # @_Z21__device_stub__k_caddPjjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6k_caddPjjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__k_caddPjjj, .Lfunc_end1-_Z21__device_stub__k_caddPjjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB2_56
# %bb.1:
movl %edi, %eax
movq -8(%rsi,%rax,8), %rbx
movl $.L.str.28, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB2_57
# %bb.2:
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r15, %rdi
callq ftell
movq %rax, %r12
movq %r15, %rdi
callq rewind
leaq 1(%r12), %r13
movl $1, %esi
movq %r13, %rdi
callq calloc
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %rax, %r12
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
testq %r12, %r12
je .LBB2_58
.LBB2_3: # %.preheader
testq %r13, %r13
jle .LBB2_6
# %bb.4: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbl (%r12,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %r13
jne .LBB2_5
.LBB2_6: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq %r13, %rcx
xorl %eax, %eax
addq $-2, %rcx
je .LBB2_9
# %bb.7: # %.lr.ph.i.preheader
movq %rcx, %rdx
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
sarq $4, %rdx
incl %eax
cmpq $16, %rcx
movq %rdx, %rcx
jae .LBB2_8
.LBB2_9: # %.preheader.i
movl $1, %ebx
testl %eax, %eax
je .LBB2_11
.p2align 4, 0x90
.LBB2_10: # %.lr.ph19.i
# =>This Inner Loop Header: Depth=1
shlq $4, %rbx
decl %eax
jne .LBB2_10
.LBB2_11: # %_ZL24round_up_to_power_of_twoli.exit
leaq 15(%rbx), %rax
testq %rbx, %rbx
movq %rbx, %r14
cmovsq %rax, %r14
sarq $4, %r14
cmpq $31, %rax
movq %r12, 136(%rsp) # 8-byte Spill
jae .LBB2_13
# %bb.12:
xorl %r15d, %r15d
jmp .LBB2_15
.LBB2_13: # %.lr.ph221.preheader
xorl %r15d, %r15d
movq %r14, %rax
.p2align 4, 0x90
.LBB2_14: # %.lr.ph221
# =>This Inner Loop Header: Depth=1
addq %rax, %r15
leaq 15(%rax), %rcx
testq %rax, %rax
cmovsq %rcx, %rax
sarq $4, %rax
cmpq $31, %rcx
jae .LBB2_14
.LBB2_15: # %._crit_edge222
decq %r13
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
leaq (,%r15,4), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %r12
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rdi
movq %rbp, 16(%rsp) # 8-byte Spill
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_17
# %bb.16:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $192, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_17:
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $193, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_19:
movq 24(%rsp), %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_21
# %bb.20:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $194, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_21:
movabsq $4294967808, %rbp # imm = 0x100000200
movl $.Lstr.1, %edi
callq puts@PLT
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %rax # imm = 0xF4240
addq 40(%rsp), %rax
movq %rax, 56(%rsp) # 8-byte Spill
imulq $-1000000, 168(%rsp), %rax # imm = 0xFFF0BDC0
subq 176(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movl $.Lstr.2, %edi
callq puts@PLT
leaq 65023(%rbp), %rdx
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq (%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 88(%rsp)
movl %r13d, 12(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6k_iaddPjPcj, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23:
movq %r13, 48(%rsp) # 8-byte Spill
movl $.Lstr.3, %edi
callq puts@PLT
movq (%rsp), %rsi
movq %r12, %rdi
movq 16(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_25
# %bb.24:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $223, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_25:
movl $.Lstr.4, %edi
callq puts@PLT
testq %r15, %r15
jle .LBB2_28
# %bb.26: # %.lr.ph225.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_27: # %.lr.ph225
# =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r15
jne .LBB2_27
.LBB2_28: # %._crit_edge226
movq 48(%rsp), %r13 # 8-byte Reload
shrq $63, %r13
movl $10, %edi
callq putchar@PLT
movl $.Lstr.5, %edi
callq puts@PLT
movq (%rsp), %rdi
movq %r12, %rsi
movq 16(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_30
# %bb.29:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $238, %edx
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_30:
addq %r13, 48(%rsp) # 8-byte Folded Spill
movl $.Lstr.6, %edi
callq puts@PLT
leaq 255(%rbx), %r13
testq %rbx, %rbx
cmovnsq %rbx, %r13
shrq $8, %r13
testl %r13d, %r13d
je .LBB2_35
# %bb.31: # %.lr.ph232
movabsq $4294967808, %rax # imm = 0x100000200
leaq 65023(%rax), %rbp
xorl %ebx, %ebx
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_32: # in Loop: Header=BB2_33 Depth=1
movl %r14d, %ebx
leal (%r14,%r13), %eax
movl %r13d, %ecx
shrl $4, %ecx
movl %eax, %r14d
cmpl $16, %r13d
movl %ecx, %r13d
jb .LBB2_35
.LBB2_33: # =>This Inner Loop Header: Depth=1
movl $.L.str.16, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_32
# %bb.34: # in Loop: Header=BB2_33 Depth=1
movq (%rsp), %rax
movq %rax, 128(%rsp)
movl %r14d, 72(%rsp)
movl %ebx, 12(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z6k_caddPjjj, %edi
leaq 144(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_32
.LBB2_35: # %._crit_edge233
shrq 48(%rsp) # 8-byte Folded Spill
movl $.Lstr.9, %edi
callq puts@PLT
movl $.Lstr.9, %edi
callq puts@PLT
movq (%rsp), %rsi
movq %r12, %rdi
movq 16(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_37
# %bb.36:
movl %eax, %ebp
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $266, %edx # imm = 0x10A
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_37:
movl $.Lstr.9, %edi
callq puts@PLT
leaq 32(%rsp), %r13
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %rax # imm = 0xF4240
movq %rax, 16(%rsp) # 8-byte Spill
movq 40(%rsp), %rbx
movq 64(%rsp), %rbp # 8-byte Reload
addq %rbp, %rbx
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %r13 # imm = 0xF4240
movq 40(%rsp), %r14
addq %rbp, %r14
movl $.Lstr.10, %edi
callq puts@PLT
testq %r15, %r15
jle .LBB2_40
# %bb.38: # %.lr.ph236.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_39: # %.lr.ph236
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbp,4), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r15
jne .LBB2_39
.LBB2_40: # %._crit_edge237
movl $10, %edi
callq putchar@PLT
movl -4(%r12,%r15,4), %edx
movq 48(%rsp), %rsi # 8-byte Reload
cmpl %esi, %edx
jb .LBB2_60
# %bb.41:
testl %esi, %esi
je .LBB2_64
# %bb.42:
movq 56(%rsp), %rax # 8-byte Reload
addq 64(%rsp), %rax # 8-byte Folded Reload
movq %rax, 56(%rsp) # 8-byte Spill
addq 16(%rsp), %rbx # 8-byte Folded Reload
addq %r13, %r14
addl $-17, %r15d
leal -1(%rsi), %eax
movl $16, %ecx
xorl %ebp, %ebp
movq %rsi, %r13
jmp .LBB2_45
.p2align 4, 0x90
.LBB2_43: # in Loop: Header=BB2_45 Depth=1
xorl %ebp, %ebp
.LBB2_44: # %._crit_edge243
# in Loop: Header=BB2_45 Depth=1
addl %edx, %ebp
movl %ecx, %edx
shll $4, %edx
movl %r15d, %esi
subl %edx, %esi
testl %r15d, %r15d
cmovnel %edx, %ecx
cmovel %r15d, %esi
movl %esi, %r15d
je .LBB2_48
.LBB2_45: # =>This Loop Header: Depth=1
# Child Loop BB2_47 Depth 2
movl %ebp, %edx
shll $4, %edx
leal (%r15,%rdx), %esi
movl (%r12,%rsi,4), %esi
cmpl %esi, %eax
jb .LBB2_43
# %bb.46: # %.lr.ph242.preheader
# in Loop: Header=BB2_45 Depth=1
leal (%r15,%rdx), %edi
incl %edi
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_47: # %.lr.ph242
# Parent Loop BB2_45 Depth=1
# => This Inner Loop Header: Depth=2
subl %esi, %eax
leal (%rdi,%rbp), %esi
movl (%r12,%rsi,4), %esi
incl %ebp
cmpl %esi, %eax
jae .LBB2_47
jmp .LBB2_44
.LBB2_48:
shll $4, %ebp
testl %eax, %eax
je .LBB2_51
# %bb.49: # %.lr.ph250.preheader
movq 136(%rsp), %rsi # 8-byte Reload
.p2align 4, 0x90
.LBB2_50: # %.lr.ph250
# =>This Inner Loop Header: Depth=1
movl %ebp, %ecx
xorl %edx, %edx
cmpb $45, (%rsi,%rcx)
setne %dl
incl %ebp
subl %edx, %eax
jne .LBB2_50
.LBB2_51: # %._crit_edge251
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 32(%rsp), %rax # imm = 0xF4240
movq 64(%rsp), %r15 # 8-byte Reload
addq 40(%rsp), %r15
addq %rax, %r15
movl $.L.str.21, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.22, %edi
movq 56(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rsi
subq %r12, %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movq %r14, %rsi
subq %rbx, %rsi
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
subq %r14, %r15
movl $.L.str.25, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.26, %edi
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
incl %ebp
movl $.L.str.27, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_53
# %bb.52:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $426, %edx # imm = 0x1AA
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_53:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_55
# %bb.54:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $427, %edx # imm = 0x1AB
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_55:
xorl %eax, %eax
jmp .LBB2_59
.LBB2_56:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $52, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $67, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_58
.LBB2_57:
movq stderr(%rip), %r15
callq __errno_location
movl (%rax), %edi
callq strerror
xorl %r12d, %r12d
movl $.L.str.29, %esi
movq %r15, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
# implicit-def: $r13
testq %r12, %r12
jne .LBB2_3
.LBB2_58:
movl $1, %eax
.LBB2_59:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_60:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rdi
movl $.L.str.19, %esi
xorl %eax, %eax
callq fprintf
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_62
# %bb.61:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $292, %edx # imm = 0x124
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_62:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_69
# %bb.63:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $293, %edx # imm = 0x125
jmp .LBB2_68
.LBB2_64:
movq stderr(%rip), %rcx
movl $.L.str.20, %edi
movl $52, %esi
movl $1, %edx
callq fwrite@PLT
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_66
# %bb.65:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $300, %edx # imm = 0x12C
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_66:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_69
# %bb.67:
movl %eax, %ebx
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $301, %edx # imm = 0x12D
.LBB2_68:
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_69:
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6k_iaddPjPcj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6k_caddPjjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6k_iaddPjPcj,@object # @_Z6k_iaddPjPcj
.section .rodata,"a",@progbits
.globl _Z6k_iaddPjPcj
.p2align 3, 0x0
_Z6k_iaddPjPcj:
.quad _Z21__device_stub__k_iaddPjPcj
.size _Z6k_iaddPjPcj, 8
.type _Z6k_caddPjjj,@object # @_Z6k_caddPjjj
.globl _Z6k_caddPjjj
.p2align 3, 0x0
_Z6k_caddPjjj:
.quad _Z21__device_stub__k_caddPjjj
.size _Z6k_caddPjjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: transalign_killer [--cldev=x.y] <input file>\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " --cldev=x.y: x specifies the platform index, y the device index.\n"
.size .L.str.1, 68
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "res_length: %d\n"
.size .L.str.4, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "<%s>:%i "
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/XanClic/transalign-killer/master/cuda/main.hip"
.size .L.str.7, 104
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "[CUDA] Error: %s\n"
.size .L.str.8, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d "
.size .L.str.13, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "k_cadd loop %d\n"
.size .L.str.16, 16
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Logical index out of bounds (last index: %u).\n"
.size .L.str.19, 47
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Please used 1-based indexing (for whatever reason).\n"
.size .L.str.20, 53
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "%li us elapsed total\n"
.size .L.str.21, 22
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " - %li us on bandwidth forth\n"
.size .L.str.22, 30
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " - %li us on GPU\n"
.size .L.str.23, 18
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " - %li us on bandwidth back\n"
.size .L.str.24, 29
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " - %li us on CPU\n"
.size .L.str.25, 18
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Index for %u: %u\n"
.size .L.str.26, 18
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "cnt = %u (index + 1)\n"
.size .L.str.27, 22
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "r"
.size .L.str.28, 2
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Could not load file \"%s\": %s\n"
.size .L.str.29, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6k_iaddPjPcj"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6k_caddPjjj"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU part started"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "GPU malloc and cpy finised"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "k_iadd launching"
.size .Lstr.2, 17
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "k_iadd finished"
.size .Lstr.3, 16
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "result back"
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "k_iadd result back"
.size .Lstr.5, 19
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "k_cadd loop start"
.size .Lstr.6, 18
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "k_cadd loop end"
.size .Lstr.9, 16
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "cpu part start"
.size .Lstr.10, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__k_iaddPjPcj
.addrsig_sym _Z21__device_stub__k_caddPjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6k_iaddPjPcj
.addrsig_sym _Z6k_caddPjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#define d_mat_dvz_dz(z,x) d_mat_dvz_dz[(x)*(nz)+(z)]
#define d_mat_dvx_dx(z,x) d_mat_dvx_dx[(x)*(nz)+(z)]
#define d_Cp(z,x) d_Cp[(x)*(nz)+(z)]
#define d_CpGrad(z,x) d_CpGrad[(x)*(nz)+(z)]
__global__ void ac_pressure_adj(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dvz_dz, float *d_mem_dvx_dx, float *d_mem_dszz_dz, float *d_mem_dsxx_dx, \
float *d_Lambda, float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b,\
float *d_K_z_half, float *d_a_z_half, float *d_b_z_half, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
float *d_K_z, float *d_a_z, float *d_b_z, \
float *d_K_x, float *d_a_x, float *d_b_x, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, \
float *d_Cp, float *d_mat_dvz_dz, float *d_mat_dvx_dx, float * d_CpGrad){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dvz_dz = 0.0;
float dvx_dx = 0.0;
float dphiz_dz = 0.0;
float dphix_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// dvz_dz = c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx));
// dvx_dx = c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) - c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2));
// dphiz_dz = c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
// - c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx));
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// - c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2));
// // update stress
// d_szz(gidz,gidx) += -1.0 * d_Lambda(gidz,gidx)*dt * (d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
// + dvx_dx/d_K_x_half[gidx]/dx + dvz_dz/d_K_z[gidz]/dz);
// d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_szz(gidz, gidx)/dx;
// d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_szz(gidz, gidx)/dz;
// forward difference
// if (gidz == 2) {
// dvz_dz = c1*(d_vz(2,gidx)-d_vz(3,gidx)) + c2*d_vz(4,gidx);
// dphiz_dz = c1*(d_mem_dszz_dz(2,gidx)-d_mem_dszz_dz(3,gidx)) + c2*d_mem_dszz_dz(4,gidx);
// }
// else if (gidz == nz-nPad-3) {
// dvz_dz = c1*d_vz(gidz,gidx) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = c1*d_mem_dszz_dz(gidz,gidx) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else if (gidz == nz-nPad-4) {
// dvz_dz = -c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = -c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else {
dvz_dz = (-c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) + c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx)))/dz;
dphiz_dz = (-c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
+ c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx)))/dz;
// }
// backward difference
// if (gidx == 2) {
// dvx_dx = -c1*d_vx(gidz,gidx) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*d_mem_dsxx_dx(gidz,gidx) + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// if (gidx == 3) {
// dvx_dx = -c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// else if (gidx == nx-3) {
// dvx_dx = c1*(d_vx(gidz,gidx-1)-d_vx(gidz,gidx)) - c2*d_vx(gidz,gidx-2);
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx-1)-d_mem_dsxx_dx(gidz,gidx)) - c2*d_mem_dsxx_dx(gidz,gidx-2);
// }
// else {
dvx_dx = (-c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2)))/dx;
dphix_dx = (-c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
+ c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2)))/dx;
// }
// update stress
d_szz(gidz,gidx) += d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
+ d_ave_Byc_b(gidz, gidx)*dvx_dx/d_K_x_half[gidx]*dt + d_ave_Byc_a(gidz, gidx)*dvz_dz/d_K_z[gidz]*dt;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
}
else {
return;
}
} | .file "tmpxft_00064509_00000000-6_ac_pressure_adj.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.type _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, @function
_Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $600, %rsp
.cfi_def_cfa_offset 608
movq %rdi, 232(%rsp)
movq %rsi, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rcx, 208(%rsp)
movq %r8, 200(%rsp)
movq %r9, 192(%rsp)
movss %xmm0, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movq 608(%rsp), %rax
movq %rax, 184(%rsp)
movq 616(%rsp), %rax
movq %rax, 176(%rsp)
movq 624(%rsp), %rax
movq %rax, 168(%rsp)
movq 632(%rsp), %rax
movq %rax, 160(%rsp)
movq 640(%rsp), %rax
movq %rax, 152(%rsp)
movq 648(%rsp), %rax
movq %rax, 144(%rsp)
movq 656(%rsp), %rax
movq %rax, 136(%rsp)
movq 664(%rsp), %rax
movq %rax, 128(%rsp)
movq 672(%rsp), %rax
movq %rax, 120(%rsp)
movq 680(%rsp), %rax
movq %rax, 112(%rsp)
movq 688(%rsp), %rax
movq %rax, 104(%rsp)
movq 696(%rsp), %rax
movq %rax, 96(%rsp)
movq 704(%rsp), %rax
movq %rax, 88(%rsp)
movq 712(%rsp), %rax
movq %rax, 80(%rsp)
movq 720(%rsp), %rax
movq %rax, 72(%rsp)
movq 728(%rsp), %rax
movq %rax, 64(%rsp)
movq 736(%rsp), %rax
movq %rax, 56(%rsp)
movq 776(%rsp), %rax
movq %rax, 32(%rsp)
movq 784(%rsp), %rax
movq %rax, 24(%rsp)
movq 792(%rsp), %rax
movq %rax, 16(%rsp)
movq 800(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 232(%rsp), %rax
movq %rax, 304(%rsp)
leaq 224(%rsp), %rax
movq %rax, 312(%rsp)
leaq 216(%rsp), %rax
movq %rax, 320(%rsp)
leaq 208(%rsp), %rax
movq %rax, 328(%rsp)
leaq 200(%rsp), %rax
movq %rax, 336(%rsp)
leaq 192(%rsp), %rax
movq %rax, 344(%rsp)
leaq 184(%rsp), %rax
movq %rax, 352(%rsp)
leaq 176(%rsp), %rax
movq %rax, 360(%rsp)
leaq 168(%rsp), %rax
movq %rax, 368(%rsp)
leaq 160(%rsp), %rax
movq %rax, 376(%rsp)
leaq 152(%rsp), %rax
movq %rax, 384(%rsp)
leaq 144(%rsp), %rax
movq %rax, 392(%rsp)
leaq 136(%rsp), %rax
movq %rax, 400(%rsp)
leaq 128(%rsp), %rax
movq %rax, 408(%rsp)
leaq 120(%rsp), %rax
movq %rax, 416(%rsp)
leaq 112(%rsp), %rax
movq %rax, 424(%rsp)
leaq 104(%rsp), %rax
movq %rax, 432(%rsp)
leaq 96(%rsp), %rax
movq %rax, 440(%rsp)
leaq 88(%rsp), %rax
movq %rax, 448(%rsp)
leaq 80(%rsp), %rax
movq %rax, 456(%rsp)
leaq 72(%rsp), %rax
movq %rax, 464(%rsp)
leaq 64(%rsp), %rax
movq %rax, 472(%rsp)
leaq 56(%rsp), %rax
movq %rax, 480(%rsp)
leaq 744(%rsp), %rax
movq %rax, 488(%rsp)
leaq 752(%rsp), %rax
movq %rax, 496(%rsp)
leaq 52(%rsp), %rax
movq %rax, 504(%rsp)
leaq 48(%rsp), %rax
movq %rax, 512(%rsp)
leaq 44(%rsp), %rax
movq %rax, 520(%rsp)
leaq 760(%rsp), %rax
movq %rax, 528(%rsp)
leaq 768(%rsp), %rax
movq %rax, 536(%rsp)
leaq 32(%rsp), %rax
movq %rax, 544(%rsp)
leaq 24(%rsp), %rax
movq %rax, 552(%rsp)
leaq 16(%rsp), %rax
movq %rax, 560(%rsp)
leaq 8(%rsp), %rax
movq %rax, 568(%rsp)
movl $1, 256(%rsp)
movl $1, 260(%rsp)
movl $1, 264(%rsp)
movl $1, 268(%rsp)
movl $1, 272(%rsp)
movl $1, 276(%rsp)
leaq 248(%rsp), %rcx
leaq 240(%rsp), %rdx
leaq 268(%rsp), %rsi
leaq 256(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 248(%rsp)
.cfi_def_cfa_offset 616
pushq 248(%rsp)
.cfi_def_cfa_offset 624
leaq 320(%rsp), %r9
movq 284(%rsp), %rcx
movl 292(%rsp), %r8d
movq 272(%rsp), %rsi
movl 280(%rsp), %edx
leaq _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 608
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .-_Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.globl _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.type _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, @function
_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 216(%rsp)
.cfi_def_cfa_offset 32
pushq 216(%rsp)
.cfi_def_cfa_offset 40
pushq 216(%rsp)
.cfi_def_cfa_offset 48
pushq 216(%rsp)
.cfi_def_cfa_offset 56
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 216(%rsp)
.cfi_def_cfa_offset 96
pushq 216(%rsp)
.cfi_def_cfa_offset 104
pushq 216(%rsp)
.cfi_def_cfa_offset 112
pushq 216(%rsp)
.cfi_def_cfa_offset 120
pushq 216(%rsp)
.cfi_def_cfa_offset 128
pushq 216(%rsp)
.cfi_def_cfa_offset 136
pushq 216(%rsp)
.cfi_def_cfa_offset 144
pushq 216(%rsp)
.cfi_def_cfa_offset 152
pushq 216(%rsp)
.cfi_def_cfa_offset 160
pushq 216(%rsp)
.cfi_def_cfa_offset 168
pushq 216(%rsp)
.cfi_def_cfa_offset 176
pushq 216(%rsp)
.cfi_def_cfa_offset 184
pushq 216(%rsp)
.cfi_def_cfa_offset 192
pushq 216(%rsp)
.cfi_def_cfa_offset 200
pushq 216(%rsp)
.cfi_def_cfa_offset 208
pushq 216(%rsp)
.cfi_def_cfa_offset 216
pushq 216(%rsp)
.cfi_def_cfa_offset 224
call _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
addq $216, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .-_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#define d_mat_dvz_dz(z,x) d_mat_dvz_dz[(x)*(nz)+(z)]
#define d_mat_dvx_dx(z,x) d_mat_dvx_dx[(x)*(nz)+(z)]
#define d_Cp(z,x) d_Cp[(x)*(nz)+(z)]
#define d_CpGrad(z,x) d_CpGrad[(x)*(nz)+(z)]
__global__ void ac_pressure_adj(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dvz_dz, float *d_mem_dvx_dx, float *d_mem_dszz_dz, float *d_mem_dsxx_dx, \
float *d_Lambda, float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b,\
float *d_K_z_half, float *d_a_z_half, float *d_b_z_half, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
float *d_K_z, float *d_a_z, float *d_b_z, \
float *d_K_x, float *d_a_x, float *d_b_x, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, \
float *d_Cp, float *d_mat_dvz_dz, float *d_mat_dvx_dx, float * d_CpGrad){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dvz_dz = 0.0;
float dvx_dx = 0.0;
float dphiz_dz = 0.0;
float dphix_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// dvz_dz = c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx));
// dvx_dx = c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) - c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2));
// dphiz_dz = c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
// - c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx));
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// - c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2));
// // update stress
// d_szz(gidz,gidx) += -1.0 * d_Lambda(gidz,gidx)*dt * (d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
// + dvx_dx/d_K_x_half[gidx]/dx + dvz_dz/d_K_z[gidz]/dz);
// d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_szz(gidz, gidx)/dx;
// d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_szz(gidz, gidx)/dz;
// forward difference
// if (gidz == 2) {
// dvz_dz = c1*(d_vz(2,gidx)-d_vz(3,gidx)) + c2*d_vz(4,gidx);
// dphiz_dz = c1*(d_mem_dszz_dz(2,gidx)-d_mem_dszz_dz(3,gidx)) + c2*d_mem_dszz_dz(4,gidx);
// }
// else if (gidz == nz-nPad-3) {
// dvz_dz = c1*d_vz(gidz,gidx) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = c1*d_mem_dszz_dz(gidz,gidx) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else if (gidz == nz-nPad-4) {
// dvz_dz = -c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = -c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else {
dvz_dz = (-c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) + c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx)))/dz;
dphiz_dz = (-c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
+ c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx)))/dz;
// }
// backward difference
// if (gidx == 2) {
// dvx_dx = -c1*d_vx(gidz,gidx) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*d_mem_dsxx_dx(gidz,gidx) + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// if (gidx == 3) {
// dvx_dx = -c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// else if (gidx == nx-3) {
// dvx_dx = c1*(d_vx(gidz,gidx-1)-d_vx(gidz,gidx)) - c2*d_vx(gidz,gidx-2);
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx-1)-d_mem_dsxx_dx(gidz,gidx)) - c2*d_mem_dsxx_dx(gidz,gidx-2);
// }
// else {
dvx_dx = (-c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2)))/dx;
dphix_dx = (-c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
+ c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2)))/dx;
// }
// update stress
d_szz(gidz,gidx) += d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
+ d_ave_Byc_b(gidz, gidx)*dvx_dx/d_K_x_half[gidx]*dt + d_ave_Byc_a(gidz, gidx)*dvz_dz/d_K_z[gidz]*dt;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
}
else {
return;
}
} | #include <hip/hip_runtime.h>
#define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#define d_mat_dvz_dz(z,x) d_mat_dvz_dz[(x)*(nz)+(z)]
#define d_mat_dvx_dx(z,x) d_mat_dvx_dx[(x)*(nz)+(z)]
#define d_Cp(z,x) d_Cp[(x)*(nz)+(z)]
#define d_CpGrad(z,x) d_CpGrad[(x)*(nz)+(z)]
__global__ void ac_pressure_adj(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dvz_dz, float *d_mem_dvx_dx, float *d_mem_dszz_dz, float *d_mem_dsxx_dx, \
float *d_Lambda, float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b,\
float *d_K_z_half, float *d_a_z_half, float *d_b_z_half, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
float *d_K_z, float *d_a_z, float *d_b_z, \
float *d_K_x, float *d_a_x, float *d_b_x, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, \
float *d_Cp, float *d_mat_dvz_dz, float *d_mat_dvx_dx, float * d_CpGrad){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dvz_dz = 0.0;
float dvx_dx = 0.0;
float dphiz_dz = 0.0;
float dphix_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// dvz_dz = c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx));
// dvx_dx = c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) - c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2));
// dphiz_dz = c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
// - c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx));
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// - c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2));
// // update stress
// d_szz(gidz,gidx) += -1.0 * d_Lambda(gidz,gidx)*dt * (d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
// + dvx_dx/d_K_x_half[gidx]/dx + dvz_dz/d_K_z[gidz]/dz);
// d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_szz(gidz, gidx)/dx;
// d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_szz(gidz, gidx)/dz;
// forward difference
// if (gidz == 2) {
// dvz_dz = c1*(d_vz(2,gidx)-d_vz(3,gidx)) + c2*d_vz(4,gidx);
// dphiz_dz = c1*(d_mem_dszz_dz(2,gidx)-d_mem_dszz_dz(3,gidx)) + c2*d_mem_dszz_dz(4,gidx);
// }
// else if (gidz == nz-nPad-3) {
// dvz_dz = c1*d_vz(gidz,gidx) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = c1*d_mem_dszz_dz(gidz,gidx) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else if (gidz == nz-nPad-4) {
// dvz_dz = -c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = -c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else {
dvz_dz = (-c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) + c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx)))/dz;
dphiz_dz = (-c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
+ c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx)))/dz;
// }
// backward difference
// if (gidx == 2) {
// dvx_dx = -c1*d_vx(gidz,gidx) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*d_mem_dsxx_dx(gidz,gidx) + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// if (gidx == 3) {
// dvx_dx = -c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// else if (gidx == nx-3) {
// dvx_dx = c1*(d_vx(gidz,gidx-1)-d_vx(gidz,gidx)) - c2*d_vx(gidz,gidx-2);
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx-1)-d_mem_dsxx_dx(gidz,gidx)) - c2*d_mem_dsxx_dx(gidz,gidx-2);
// }
// else {
dvx_dx = (-c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2)))/dx;
dphix_dx = (-c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
+ c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2)))/dx;
// }
// update stress
d_szz(gidz,gidx) += d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
+ d_ave_Byc_b(gidz, gidx)*dvx_dx/d_K_x_half[gidx]*dt + d_ave_Byc_a(gidz, gidx)*dvz_dz/d_K_z[gidz]*dt;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
}
else {
return;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#define d_mat_dvz_dz(z,x) d_mat_dvz_dz[(x)*(nz)+(z)]
#define d_mat_dvx_dx(z,x) d_mat_dvx_dx[(x)*(nz)+(z)]
#define d_Cp(z,x) d_Cp[(x)*(nz)+(z)]
#define d_CpGrad(z,x) d_CpGrad[(x)*(nz)+(z)]
__global__ void ac_pressure_adj(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dvz_dz, float *d_mem_dvx_dx, float *d_mem_dszz_dz, float *d_mem_dsxx_dx, \
float *d_Lambda, float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b,\
float *d_K_z_half, float *d_a_z_half, float *d_b_z_half, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
float *d_K_z, float *d_a_z, float *d_b_z, \
float *d_K_x, float *d_a_x, float *d_b_x, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, \
float *d_Cp, float *d_mat_dvz_dz, float *d_mat_dvx_dx, float * d_CpGrad){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dvz_dz = 0.0;
float dvx_dx = 0.0;
float dphiz_dz = 0.0;
float dphix_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// dvz_dz = c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx));
// dvx_dx = c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) - c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2));
// dphiz_dz = c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
// - c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx));
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// - c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2));
// // update stress
// d_szz(gidz,gidx) += -1.0 * d_Lambda(gidz,gidx)*dt * (d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
// + dvx_dx/d_K_x_half[gidx]/dx + dvz_dz/d_K_z[gidz]/dz);
// d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_szz(gidz, gidx)/dx;
// d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_szz(gidz, gidx)/dz;
// forward difference
// if (gidz == 2) {
// dvz_dz = c1*(d_vz(2,gidx)-d_vz(3,gidx)) + c2*d_vz(4,gidx);
// dphiz_dz = c1*(d_mem_dszz_dz(2,gidx)-d_mem_dszz_dz(3,gidx)) + c2*d_mem_dszz_dz(4,gidx);
// }
// else if (gidz == nz-nPad-3) {
// dvz_dz = c1*d_vz(gidz,gidx) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = c1*d_mem_dszz_dz(gidz,gidx) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else if (gidz == nz-nPad-4) {
// dvz_dz = -c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = -c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else {
dvz_dz = (-c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) + c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx)))/dz;
dphiz_dz = (-c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
+ c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx)))/dz;
// }
// backward difference
// if (gidx == 2) {
// dvx_dx = -c1*d_vx(gidz,gidx) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*d_mem_dsxx_dx(gidz,gidx) + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// if (gidx == 3) {
// dvx_dx = -c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// else if (gidx == nx-3) {
// dvx_dx = c1*(d_vx(gidz,gidx-1)-d_vx(gidz,gidx)) - c2*d_vx(gidz,gidx-2);
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx-1)-d_mem_dsxx_dx(gidz,gidx)) - c2*d_mem_dsxx_dx(gidz,gidx-2);
// }
// else {
dvx_dx = (-c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2)))/dx;
dphix_dx = (-c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
+ c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2)))/dx;
// }
// update stress
d_szz(gidz,gidx) += d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
+ d_ave_Byc_b(gidz, gidx)*dvx_dx/d_K_x_half[gidx]*dt + d_ave_Byc_a(gidz, gidx)*dvz_dz/d_K_z[gidz]*dt;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
}
else {
return;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.globl _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.p2align 8
.type _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_,@function
_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
s_load_b32 s4, s[0:1], 0x104
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 0xf8
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e32 1, v1
s_cbranch_execz .LBB0_10
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b64 s[20:21], s[0:1], 0xb8
s_load_b32 s24, s[0:1], 0xd0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_add_i32 s3, s21, -3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_sub_i32 s2, s20, s24
s_add_i32 s2, s2, -3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e32 vcc_lo, s2, v1
v_cmp_ge_i32_e64 s2, s3, v5
v_cmp_lt_i32_e64 s3, 1, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[3:4], null, v5, s20, v[1:2]
s_clause 0x3
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b64 s[22:23], s[0:1], 0x38
v_add_nc_u32_e32 v0, -1, v5
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x48
s_load_b128 s[16:19], s[0:1], 0x88
v_add_nc_u32_e32 v6, 1, v3
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v8, 2, v3
v_add_nc_u32_e32 v10, -1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[12:13], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v13, vcc_lo
v_add_co_u32 v16, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v18, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v20, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v21, vcc_lo, s9, v11, vcc_lo
s_clause 0x3
global_load_b32 v26, v[16:17], off
global_load_b32 v27, v[14:15], off
global_load_b32 v28, v[18:19], off
global_load_b32 v29, v[20:21], off
v_mad_u64_u32 v[14:15], null, v0, s20, v[1:2]
v_add_nc_u32_e32 v0, -2, v5
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_nc_u32_e32 v18, s20, v3
v_ashrrev_i32_e32 v15, 31, v14
v_mad_u64_u32 v[20:21], null, v0, s20, v[1:2]
v_add_co_u32 v16, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v13, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v22, vcc_lo, s10, v12
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v23, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v24, vcc_lo, s10, v14
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_add_co_ci_u32_e32 v25, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v10
v_lshlrev_b64 v[20:21], 2, v[20:21]
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_clause 0x1
global_load_b32 v0, v[22:23], off
global_load_b32 v30, v[24:25], off
v_add_co_u32 v22, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v23, vcc_lo, s11, v19, vcc_lo
v_add_co_u32 v24, vcc_lo, s10, v20
v_add_co_ci_u32_e32 v25, vcc_lo, s11, v21, vcc_lo
s_clause 0x3
global_load_b32 v31, v[6:7], off
global_load_b32 v32, v[16:17], off
global_load_b32 v33, v[8:9], off
global_load_b32 v34, v[10:11], off
s_clause 0x1
global_load_b32 v22, v[22:23], off
global_load_b32 v23, v[24:25], off
v_add_co_u32 v6, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v13, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v15, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v18
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v19, vcc_lo
v_add_co_u32 v14, vcc_lo, s6, v20
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v21, vcc_lo
s_clause 0x3
global_load_b32 v18, v[6:7], off
global_load_b32 v19, v[8:9], off
global_load_b32 v11, v[10:11], off
global_load_b32 v20, v[14:15], off
s_load_b128 s[8:11], s[0:1], 0x70
v_mov_b32_e32 v6, 0
v_add_co_u32 v7, vcc_lo, s14, v12
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v2, v6
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_load_b128 s[4:7], s[0:1], 0xc0
global_load_b32 v21, v[7:8], off
v_add_co_u32 v7, vcc_lo, s12, v12
v_lshlrev_b64 v[14:15], 2, v[1:2]
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v13, vcc_lo
global_load_b32 v24, v[7:8], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v7, vcc_lo, s16, v14
v_add_co_ci_u32_e32 v8, vcc_lo, s17, v15, vcc_lo
global_load_b32 v16, v[16:17], off
global_load_b32 v17, v[7:8], off
v_add_co_u32 v7, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s18, v14
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v15, vcc_lo
global_load_b32 v14, v[7:8], off
global_load_b32 v9, v[9:10], off
v_add_co_u32 v7, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v13, vcc_lo
global_load_b32 v10, v[7:8], off
s_waitcnt vmcnt(19)
v_dual_sub_f32 v12, v26, v27 :: v_dual_sub_f32 v13, v28, v29
s_waitcnt vmcnt(15)
v_dual_sub_f32 v0, v0, v30 :: v_dual_sub_f32 v15, v31, v32
s_waitcnt vmcnt(13)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v0, 0x3f900000, v0 :: v_dual_sub_f32 v25, v33, v34
s_waitcnt vmcnt(11)
v_sub_f32_e32 v22, v22, v23
v_mul_f32_e32 v15, 0x3f900000, v15
v_fma_f32 v0, v22, 0x3d2aaaab, -v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v23, null, s6, s6, v0
v_div_scale_f32 v33, s3, v0, s6, v0
v_rcp_f32_e32 v27, v23
s_waitcnt vmcnt(7)
v_dual_sub_f32 v18, v18, v19 :: v_dual_sub_f32 v11, v11, v20
v_mul_f32_e32 v12, 0x3f900000, v12
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v12, v13, 0x3d2aaaab, -v12
v_fma_f32 v13, v25, 0x3d2aaaab, -v15
s_waitcnt_depctr 0xfff
v_fma_f32 v32, -v23, v27, 1.0
v_div_scale_f32 v15, null, s5, s5, v12
v_div_scale_f32 v22, null, s5, s5, v13
v_div_scale_f32 v28, vcc_lo, v12, s5, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v25, v15
v_rcp_f32_e32 v26, v22
v_div_scale_f32 v29, s2, v13, s5, v13
v_fmac_f32_e32 v27, v32, v27
s_waitcnt_depctr 0xfff
v_fma_f32 v30, -v15, v25, 1.0
v_fma_f32 v31, -v22, v26, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v25, v30, v25 :: v_dual_fmac_f32 v26, v31, v26
v_mul_f32_e32 v31, v33, v27
v_dual_mul_f32 v19, v28, v25 :: v_dual_mul_f32 v30, v29, v26
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v34, -v23, v31, v33
v_fma_f32 v20, -v15, v19, v28
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v32, -v22, v30, v29
v_fmac_f32_e32 v31, v34, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v19, v20, v25
v_fmac_f32_e32 v30, v32, v26
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v15, v19, v28
v_fma_f32 v20, -v22, v30, v29
v_fma_f32 v22, -v23, v31, v33
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v15, v15, v25, v19
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v19, v20, v26, v30
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v12, v15, s5, v12
v_div_fmas_f32 v20, v22, v27, v31
v_div_fixup_f32 v13, v19, s5, v13
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v12, v12, v24
v_div_fixup_f32 v0, v20, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v21
s_waitcnt vmcnt(4)
v_div_scale_f32 v20, null, v16, v16, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v24, v20
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v20, v24, 1.0
v_fmac_f32_e32 v24, v26, v24
v_mul_f32_e32 v18, 0x3f900000, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, v11, 0x3d2aaaab, -v18
v_div_scale_f32 v18, null, s6, s6, v11
v_div_scale_f32 v21, vcc_lo, v11, s6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v22, v18
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v18, v22, 1.0
v_fmac_f32_e32 v22, v15, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v25, v21, v22
v_fma_f32 v27, -v18, v25, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v25, v27, v22
v_fma_f32 v18, -v18, v25, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v18, v18, v22, v25
v_div_fixup_f32 v11, v18, s6, v11
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v14, v11
v_div_scale_f32 v28, s2, v0, v16, v0
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v11, v13, v9
v_div_scale_f32 v23, null, v17, v17, v12
v_div_scale_f32 v26, s3, v12, v17, v12
v_mul_f32_e32 v27, v28, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v15, v23
s_waitcnt_depctr 0xfff
v_fma_f32 v29, -v23, v15, 1.0
v_fmac_f32_e32 v15, v29, v15
v_fma_f32 v29, -v20, v27, v28
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v21, v26, v15
v_fmac_f32_e32 v27, v29, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v22, -v23, v21, v26
v_fma_f32 v18, -v20, v27, v28
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v21, v22, v15
v_div_fmas_f32 v18, v18, v24, v27
s_mov_b32 vcc_lo, s3
v_cmp_ge_i32_e64 s3, s7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v14, -v23, v21, v26
v_div_fixup_f32 v0, v18, v16, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v9, v14, v15, v21
v_fmac_f32_e32 v11, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v9, v9, v17, v12
v_fmac_f32_e32 v11, s4, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v10, v11
global_store_b32 v[7:8], v0, off
v_cmpx_lt_i32_e64 s7, v5
s_not_b32 s5, s7
s_and_not1_b32 s3, s3, exec_lo
s_add_i32 s5, s5, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s5, v5
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 s3, s3, s5
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0xb0
s_load_b64 s[10:11], s[0:1], 0x20
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s22, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s23, v10, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[9:10], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v0, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s4, v0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v5, v6
global_store_b32 v[9:10], v0, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_ge_i32_e64 s2, s7, v1
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e64 s7, v1
s_add_i32 s24, s24, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_not_b32 s5, s24
s_add_i32 s5, s5, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 s2, s2, s5
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x68
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s22, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s23, v4, vcc_lo
global_load_b32 v7, v[7:8], off
global_load_b32 v5, v[5:6], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, s4, v4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v0, v1
global_store_b32 v[2:3], v4, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 504
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .Lfunc_end0-_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
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.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
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.value_kind: global_buffer
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.size: 8
.value_kind: global_buffer
- .address_space: global
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.size: 8
.value_kind: global_buffer
- .offset: 184
.size: 4
.value_kind: by_value
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.size: 4
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.size: 4
.value_kind: by_value
- .address_space: global
.offset: 216
.size: 8
.value_kind: global_buffer
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.offset: 224
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 232
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 240
.size: 8
.value_kind: global_buffer
- .offset: 248
.size: 4
.value_kind: hidden_block_count_x
- .offset: 252
.size: 4
.value_kind: hidden_block_count_y
- .offset: 256
.size: 4
.value_kind: hidden_block_count_z
- .offset: 260
.size: 2
.value_kind: hidden_group_size_x
- .offset: 262
.size: 2
.value_kind: hidden_group_size_y
- .offset: 264
.size: 2
.value_kind: hidden_group_size_z
- .offset: 266
.size: 2
.value_kind: hidden_remainder_x
- .offset: 268
.size: 2
.value_kind: hidden_remainder_y
- .offset: 270
.size: 2
.value_kind: hidden_remainder_z
- .offset: 288
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 296
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 304
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 312
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 504
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#define d_mat_dvz_dz(z,x) d_mat_dvz_dz[(x)*(nz)+(z)]
#define d_mat_dvx_dx(z,x) d_mat_dvx_dx[(x)*(nz)+(z)]
#define d_Cp(z,x) d_Cp[(x)*(nz)+(z)]
#define d_CpGrad(z,x) d_CpGrad[(x)*(nz)+(z)]
__global__ void ac_pressure_adj(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dvz_dz, float *d_mem_dvx_dx, float *d_mem_dszz_dz, float *d_mem_dsxx_dx, \
float *d_Lambda, float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b,\
float *d_K_z_half, float *d_a_z_half, float *d_b_z_half, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
float *d_K_z, float *d_a_z, float *d_b_z, \
float *d_K_x, float *d_a_x, float *d_b_x, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, \
float *d_Cp, float *d_mat_dvz_dz, float *d_mat_dvx_dx, float * d_CpGrad){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dvz_dz = 0.0;
float dvx_dx = 0.0;
float dphiz_dz = 0.0;
float dphix_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// dvz_dz = c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx));
// dvx_dx = c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) - c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2));
// dphiz_dz = c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
// - c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx));
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// - c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2));
// // update stress
// d_szz(gidz,gidx) += -1.0 * d_Lambda(gidz,gidx)*dt * (d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
// + dvx_dx/d_K_x_half[gidx]/dx + dvz_dz/d_K_z[gidz]/dz);
// d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_szz(gidz, gidx)/dx;
// d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_szz(gidz, gidx)/dz;
// forward difference
// if (gidz == 2) {
// dvz_dz = c1*(d_vz(2,gidx)-d_vz(3,gidx)) + c2*d_vz(4,gidx);
// dphiz_dz = c1*(d_mem_dszz_dz(2,gidx)-d_mem_dszz_dz(3,gidx)) + c2*d_mem_dszz_dz(4,gidx);
// }
// else if (gidz == nz-nPad-3) {
// dvz_dz = c1*d_vz(gidz,gidx) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = c1*d_mem_dszz_dz(gidz,gidx) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else if (gidz == nz-nPad-4) {
// dvz_dz = -c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) - c2*d_vz(gidz-1,gidx);
// dphiz_dz = -c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) - c2*d_mem_dszz_dz(gidz-1,gidx);
// }
// else {
dvz_dz = (-c1*(d_vz(gidz+1,gidx)-d_vz(gidz,gidx)) + c2*(d_vz(gidz+2,gidx)-d_vz(gidz-1,gidx)))/dz;
dphiz_dz = (-c1*(d_mem_dszz_dz(gidz+1,gidx)-d_mem_dszz_dz(gidz,gidx)) \
+ c2*(d_mem_dszz_dz(gidz+2,gidx)-d_mem_dszz_dz(gidz-1,gidx)))/dz;
// }
// backward difference
// if (gidx == 2) {
// dvx_dx = -c1*d_vx(gidz,gidx) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*d_mem_dsxx_dx(gidz,gidx) + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// if (gidx == 3) {
// dvx_dx = -c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*d_vx(gidz,gidx+1);
// dphix_dx = -c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
// + c2*d_mem_dsxx_dx(gidz,gidx+1);
// }
// else if (gidx == nx-3) {
// dvx_dx = c1*(d_vx(gidz,gidx-1)-d_vx(gidz,gidx)) - c2*d_vx(gidz,gidx-2);
// dphix_dx = c1*(d_mem_dsxx_dx(gidz,gidx-1)-d_mem_dsxx_dx(gidz,gidx)) - c2*d_mem_dsxx_dx(gidz,gidx-2);
// }
// else {
dvx_dx = (-c1*(d_vx(gidz,gidx)-d_vx(gidz,gidx-1)) + c2*(d_vx(gidz,gidx+1)-d_vx(gidz,gidx-2)))/dx;
dphix_dx = (-c1*(d_mem_dsxx_dx(gidz,gidx)-d_mem_dsxx_dx(gidz,gidx-1)) \
+ c2*(d_mem_dsxx_dx(gidz,gidx+1)-d_mem_dsxx_dx(gidz,gidx-2)))/dx;
// }
// update stress
d_szz(gidz,gidx) += d_a_x_half[gidx]*dphix_dx + d_a_z[gidz]*dphiz_dz \
+ d_ave_Byc_b(gidz, gidx)*dvx_dx/d_K_x_half[gidx]*dt + d_ave_Byc_a(gidz, gidx)*dvz_dz/d_K_z[gidz]*dt;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dvx_dx(gidz, gidx) = d_b_x[gidx]*d_mem_dvx_dx(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dvz_dz(gidz, gidx) = d_b_z_half[gidz]*d_mem_dvz_dz(gidz, gidx) + d_Lambda(gidz, gidx)*d_szz(gidz, gidx)*dt;
}
}
else {
return;
}
} | .text
.file "ac_pressure_adj.hip"
.globl _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_ # -- Begin function _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_,@function
_Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_: # @_Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 400
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 400(%rsp), %rax
movq %rax, 160(%rsp)
leaq 408(%rsp), %rax
movq %rax, 168(%rsp)
leaq 416(%rsp), %rax
movq %rax, 176(%rsp)
leaq 424(%rsp), %rax
movq %rax, 184(%rsp)
leaq 432(%rsp), %rax
movq %rax, 192(%rsp)
leaq 440(%rsp), %rax
movq %rax, 200(%rsp)
leaq 448(%rsp), %rax
movq %rax, 208(%rsp)
leaq 456(%rsp), %rax
movq %rax, 216(%rsp)
leaq 464(%rsp), %rax
movq %rax, 224(%rsp)
leaq 472(%rsp), %rax
movq %rax, 232(%rsp)
leaq 480(%rsp), %rax
movq %rax, 240(%rsp)
leaq 488(%rsp), %rax
movq %rax, 248(%rsp)
leaq 496(%rsp), %rax
movq %rax, 256(%rsp)
leaq 504(%rsp), %rax
movq %rax, 264(%rsp)
leaq 512(%rsp), %rax
movq %rax, 272(%rsp)
leaq 520(%rsp), %rax
movq %rax, 280(%rsp)
leaq 528(%rsp), %rax
movq %rax, 288(%rsp)
leaq 536(%rsp), %rax
movq %rax, 296(%rsp)
leaq 544(%rsp), %rax
movq %rax, 304(%rsp)
leaq 12(%rsp), %rax
movq %rax, 312(%rsp)
leaq 8(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 552(%rsp), %rax
movq %rax, 336(%rsp)
leaq 560(%rsp), %rax
movq %rax, 344(%rsp)
leaq 568(%rsp), %rax
movq %rax, 352(%rsp)
leaq 576(%rsp), %rax
movq %rax, 360(%rsp)
leaq 584(%rsp), %rax
movq %rax, 368(%rsp)
leaq 592(%rsp), %rax
movq %rax, 376(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $408, %rsp # imm = 0x198
.cfi_adjust_cfa_offset -408
retq
.Lfunc_end0:
.size _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .Lfunc_end0-_Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_,@object # @_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.p2align 3, 0x0
_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
.quad _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.size _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_"
.size .L__unnamed_1, 81
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064509_00000000-6_ac_pressure_adj.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.type _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, @function
_Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $600, %rsp
.cfi_def_cfa_offset 608
movq %rdi, 232(%rsp)
movq %rsi, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rcx, 208(%rsp)
movq %r8, 200(%rsp)
movq %r9, 192(%rsp)
movss %xmm0, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movq 608(%rsp), %rax
movq %rax, 184(%rsp)
movq 616(%rsp), %rax
movq %rax, 176(%rsp)
movq 624(%rsp), %rax
movq %rax, 168(%rsp)
movq 632(%rsp), %rax
movq %rax, 160(%rsp)
movq 640(%rsp), %rax
movq %rax, 152(%rsp)
movq 648(%rsp), %rax
movq %rax, 144(%rsp)
movq 656(%rsp), %rax
movq %rax, 136(%rsp)
movq 664(%rsp), %rax
movq %rax, 128(%rsp)
movq 672(%rsp), %rax
movq %rax, 120(%rsp)
movq 680(%rsp), %rax
movq %rax, 112(%rsp)
movq 688(%rsp), %rax
movq %rax, 104(%rsp)
movq 696(%rsp), %rax
movq %rax, 96(%rsp)
movq 704(%rsp), %rax
movq %rax, 88(%rsp)
movq 712(%rsp), %rax
movq %rax, 80(%rsp)
movq 720(%rsp), %rax
movq %rax, 72(%rsp)
movq 728(%rsp), %rax
movq %rax, 64(%rsp)
movq 736(%rsp), %rax
movq %rax, 56(%rsp)
movq 776(%rsp), %rax
movq %rax, 32(%rsp)
movq 784(%rsp), %rax
movq %rax, 24(%rsp)
movq 792(%rsp), %rax
movq %rax, 16(%rsp)
movq 800(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 232(%rsp), %rax
movq %rax, 304(%rsp)
leaq 224(%rsp), %rax
movq %rax, 312(%rsp)
leaq 216(%rsp), %rax
movq %rax, 320(%rsp)
leaq 208(%rsp), %rax
movq %rax, 328(%rsp)
leaq 200(%rsp), %rax
movq %rax, 336(%rsp)
leaq 192(%rsp), %rax
movq %rax, 344(%rsp)
leaq 184(%rsp), %rax
movq %rax, 352(%rsp)
leaq 176(%rsp), %rax
movq %rax, 360(%rsp)
leaq 168(%rsp), %rax
movq %rax, 368(%rsp)
leaq 160(%rsp), %rax
movq %rax, 376(%rsp)
leaq 152(%rsp), %rax
movq %rax, 384(%rsp)
leaq 144(%rsp), %rax
movq %rax, 392(%rsp)
leaq 136(%rsp), %rax
movq %rax, 400(%rsp)
leaq 128(%rsp), %rax
movq %rax, 408(%rsp)
leaq 120(%rsp), %rax
movq %rax, 416(%rsp)
leaq 112(%rsp), %rax
movq %rax, 424(%rsp)
leaq 104(%rsp), %rax
movq %rax, 432(%rsp)
leaq 96(%rsp), %rax
movq %rax, 440(%rsp)
leaq 88(%rsp), %rax
movq %rax, 448(%rsp)
leaq 80(%rsp), %rax
movq %rax, 456(%rsp)
leaq 72(%rsp), %rax
movq %rax, 464(%rsp)
leaq 64(%rsp), %rax
movq %rax, 472(%rsp)
leaq 56(%rsp), %rax
movq %rax, 480(%rsp)
leaq 744(%rsp), %rax
movq %rax, 488(%rsp)
leaq 752(%rsp), %rax
movq %rax, 496(%rsp)
leaq 52(%rsp), %rax
movq %rax, 504(%rsp)
leaq 48(%rsp), %rax
movq %rax, 512(%rsp)
leaq 44(%rsp), %rax
movq %rax, 520(%rsp)
leaq 760(%rsp), %rax
movq %rax, 528(%rsp)
leaq 768(%rsp), %rax
movq %rax, 536(%rsp)
leaq 32(%rsp), %rax
movq %rax, 544(%rsp)
leaq 24(%rsp), %rax
movq %rax, 552(%rsp)
leaq 16(%rsp), %rax
movq %rax, 560(%rsp)
leaq 8(%rsp), %rax
movq %rax, 568(%rsp)
movl $1, 256(%rsp)
movl $1, 260(%rsp)
movl $1, 264(%rsp)
movl $1, 268(%rsp)
movl $1, 272(%rsp)
movl $1, 276(%rsp)
leaq 248(%rsp), %rcx
leaq 240(%rsp), %rdx
leaq 268(%rsp), %rsi
leaq 256(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 248(%rsp)
.cfi_def_cfa_offset 616
pushq 248(%rsp)
.cfi_def_cfa_offset 624
leaq 320(%rsp), %r9
movq 284(%rsp), %rcx
movl 292(%rsp), %r8d
movq 272(%rsp), %rsi
movl 280(%rsp), %edx
leaq _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 608
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .-_Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.globl _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.type _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, @function
_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 216(%rsp)
.cfi_def_cfa_offset 32
pushq 216(%rsp)
.cfi_def_cfa_offset 40
pushq 216(%rsp)
.cfi_def_cfa_offset 48
pushq 216(%rsp)
.cfi_def_cfa_offset 56
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 216(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 216(%rsp)
.cfi_def_cfa_offset 96
pushq 216(%rsp)
.cfi_def_cfa_offset 104
pushq 216(%rsp)
.cfi_def_cfa_offset 112
pushq 216(%rsp)
.cfi_def_cfa_offset 120
pushq 216(%rsp)
.cfi_def_cfa_offset 128
pushq 216(%rsp)
.cfi_def_cfa_offset 136
pushq 216(%rsp)
.cfi_def_cfa_offset 144
pushq 216(%rsp)
.cfi_def_cfa_offset 152
pushq 216(%rsp)
.cfi_def_cfa_offset 160
pushq 216(%rsp)
.cfi_def_cfa_offset 168
pushq 216(%rsp)
.cfi_def_cfa_offset 176
pushq 216(%rsp)
.cfi_def_cfa_offset 184
pushq 216(%rsp)
.cfi_def_cfa_offset 192
pushq 216(%rsp)
.cfi_def_cfa_offset 200
pushq 216(%rsp)
.cfi_def_cfa_offset 208
pushq 216(%rsp)
.cfi_def_cfa_offset 216
pushq 216(%rsp)
.cfi_def_cfa_offset 224
call _Z94__device_stub__Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
addq $216, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .-_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ac_pressure_adj.hip"
.globl _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_ # -- Begin function _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_,@function
_Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_: # @_Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 400
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 400(%rsp), %rax
movq %rax, 160(%rsp)
leaq 408(%rsp), %rax
movq %rax, 168(%rsp)
leaq 416(%rsp), %rax
movq %rax, 176(%rsp)
leaq 424(%rsp), %rax
movq %rax, 184(%rsp)
leaq 432(%rsp), %rax
movq %rax, 192(%rsp)
leaq 440(%rsp), %rax
movq %rax, 200(%rsp)
leaq 448(%rsp), %rax
movq %rax, 208(%rsp)
leaq 456(%rsp), %rax
movq %rax, 216(%rsp)
leaq 464(%rsp), %rax
movq %rax, 224(%rsp)
leaq 472(%rsp), %rax
movq %rax, 232(%rsp)
leaq 480(%rsp), %rax
movq %rax, 240(%rsp)
leaq 488(%rsp), %rax
movq %rax, 248(%rsp)
leaq 496(%rsp), %rax
movq %rax, 256(%rsp)
leaq 504(%rsp), %rax
movq %rax, 264(%rsp)
leaq 512(%rsp), %rax
movq %rax, 272(%rsp)
leaq 520(%rsp), %rax
movq %rax, 280(%rsp)
leaq 528(%rsp), %rax
movq %rax, 288(%rsp)
leaq 536(%rsp), %rax
movq %rax, 296(%rsp)
leaq 544(%rsp), %rax
movq %rax, 304(%rsp)
leaq 12(%rsp), %rax
movq %rax, 312(%rsp)
leaq 8(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 552(%rsp), %rax
movq %rax, 336(%rsp)
leaq 560(%rsp), %rax
movq %rax, 344(%rsp)
leaq 568(%rsp), %rax
movq %rax, 352(%rsp)
leaq 576(%rsp), %rax
movq %rax, 360(%rsp)
leaq 584(%rsp), %rax
movq %rax, 368(%rsp)
leaq 592(%rsp), %rax
movq %rax, 376(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $408, %rsp # imm = 0x198
.cfi_adjust_cfa_offset -408
retq
.Lfunc_end0:
.size _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, .Lfunc_end0-_Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_,@object # @_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.p2align 3, 0x0
_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_:
.quad _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.size _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_"
.size .L__unnamed_1, 81
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15ac_pressure_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
void Usage(char *prog_name);
#define ACCURACY 0.01
typedef float float_type;
#define KERNEL_ITERATIONS 1000
__device__ void warp_reduce(volatile float_type *sdata, const unsigned int thread_id)
{
sdata[thread_id] += sdata[thread_id + 32];
sdata[thread_id] += sdata[thread_id + 16];
sdata[thread_id] += sdata[thread_id + 8];
sdata[thread_id] += sdata[thread_id + 4];
sdata[thread_id] += sdata[thread_id + 2];
sdata[thread_id] += sdata[thread_id + 1];
}
__global__ void reduce_pi(float_type *gdata)
{
extern __shared__ float_type sdata[];
const unsigned int thread_id = threadIdx.x;
const unsigned long long int i = (((unsigned long long int)blockIdx.x) * blockDim.x + threadIdx.x) * KERNEL_ITERATIONS;
float_type current_thread_factor = 0.0f;
for (int it = 0; it < KERNEL_ITERATIONS; it++)
{
const float factor = ((i + it) & 1) ? -1.0f : 1.0f;
current_thread_factor += factor / (((i + it) << 1) + 1);
}
sdata[thread_id] = current_thread_factor;
__syncthreads();
// reduction in shared memory
for (unsigned int stride = blockDim.x >> 1; stride > 32; stride >>= 1)
{
if (thread_id < stride) {
sdata[thread_id] += sdata[thread_id + stride];
}
__syncthreads();
}
if (thread_id < 32)
warp_reduce(sdata, thread_id);
// write result for this block to global memory
if (thread_id == 0)
gdata[blockIdx.x] = sdata[0];
}
double sequential_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
for (i = 0; i < n; i++)
{
factor = (i % 2 == 0) ? 1.0 : -1.0;
sum += factor / (2 * i + 1);
}
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
double parallel_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
float_type *dev_sum;
float_type *cpu_sum;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
long long block_size = 1024;
long long grid_size = ceil(((double)n / KERNEL_ITERATIONS) / block_size);
cpu_sum = (float_type*)calloc(grid_size, sizeof(float_type));
cudaMalloc(&dev_sum, grid_size * sizeof(float_type));
reduce_pi<<< grid_size, block_size, block_size * sizeof(float_type) >>>(dev_sum);
cudaMemcpy(cpu_sum, dev_sum, grid_size * sizeof(float_type), cudaMemcpyDeviceToHost);
factor = ((n - 1) % 2 == 0) ? 1.0 : -1.0;
for (i = 0; i < grid_size; i++)
sum += cpu_sum[i];
cudaFree(dev_sum);
free(cpu_sum);
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
int main(int argc, char *argv[])
{
float elapsed_time_seq;
cudaEvent_t start_time_seq, end_time_seq;
cudaEventCreate(&start_time_seq);
cudaEventCreate(&end_time_seq);
float elapsed_time_parallel;
cudaEvent_t start_time_parallel, end_time_parallel;
cudaEventCreate(&start_time_parallel);
cudaEventCreate(&end_time_parallel);
printf("---------------------Sequential execution---------------------\n");
cudaEventRecord(start_time_seq, 0);
double sum_seq = sequential_solution(argc, argv);
cudaEventRecord(end_time_seq, 0);
cudaEventSynchronize(end_time_seq);
cudaEventElapsedTime(&elapsed_time_seq, start_time_seq, end_time_seq);
printf("----------------------Parallel execution----------------------\n");
cudaEventRecord(start_time_parallel, 0);
double sum_parallel = parallel_solution(argc, argv);
cudaEventRecord(end_time_parallel, 0);
cudaEventSynchronize(end_time_parallel);
cudaEventElapsedTime(&elapsed_time_parallel, start_time_parallel, end_time_parallel);
printf("\nSequential elapsed time: %fs\n", elapsed_time_seq / 1000.0);
printf("Parallel elapsed time: %fs\n", elapsed_time_parallel / 1000.0);
if (fabs(sum_seq - sum_parallel) < ACCURACY)
printf("Test PASSED\n");
else
printf("Test FAILED\n");
return 0;
}
void Usage(char *prog_name)
{
fprintf(stderr, "usage: %s <n>\n", prog_name);
fprintf(stderr, " n is the number of terms and should be >= 1\n");
exit(0);
} | .file "tmpxft_00043036_00000000-6_dz4z1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11warp_reducePVfj
.type _Z11warp_reducePVfj, @function
_Z11warp_reducePVfj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11warp_reducePVfj, .-_Z11warp_reducePVfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: %s <n>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " n is the number of terms and should be >= 1\n"
.text
.globl _Z5UsagePc
.type _Z5UsagePc, @function
_Z5UsagePc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z5UsagePc, .-_Z5UsagePc
.section .rodata.str1.8
.align 8
.LC5:
.string "Before for loop, factor = %f.\n"
.section .rodata.str1.1
.LC6:
.string "After for loop, factor = %f.\n"
.LC8:
.string "With n = %lld terms\n"
.section .rodata.str1.8
.align 8
.LC9:
.string " Our estimate of pi = %.14f\n"
.align 8
.LC11:
.string " Ref estimate of pi = %.14f\n"
.text
.globl _Z19sequential_solutioniPPc
.type _Z19sequential_solutioniPPc, @function
_Z19sequential_solutioniPPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
cmpl $2, %edi
jne .L15
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbp
testq %rax, %rax
jle .L16
pxor %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %eax
movq $0x000000000, 8(%rsp)
movl $0, %ebx
movsd .LC4(%rip), %xmm3
jmp .L11
.L15:
movq (%rsi), %rdi
call _Z5UsagePc
.L16:
movq (%rbx), %rdi
call _Z5UsagePc
.L10:
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movapd %xmm0, %xmm1
divsd %xmm2, %xmm1
addsd 8(%rsp), %xmm1
movsd %xmm1, 8(%rsp)
addq $1, %rbx
addq $2, %rax
cmpq %rbx, %rbp
je .L17
.L11:
movapd %xmm3, %xmm0
testb $1, %bl
jne .L10
movsd .LC3(%rip), %xmm0
jmp .L10
.L17:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm5
mulsd .LC7(%rip), %xmm5
movsd %xmm5, 8(%rsp)
movq %rbx, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z19sequential_solutioniPPc, .-_Z19sequential_solutioniPPc
.globl _Z28__device_stub__Z9reduce_piPfPf
.type _Z28__device_stub__Z9reduce_piPfPf, @function
_Z28__device_stub__Z9reduce_piPfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reduce_piPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z9reduce_piPfPf, .-_Z28__device_stub__Z9reduce_piPfPf
.globl _Z9reduce_piPf
.type _Z9reduce_piPf, @function
_Z9reduce_piPf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9reduce_piPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9reduce_piPf, .-_Z9reduce_piPf
.globl _Z17parallel_solutioniPPc
.type _Z17parallel_solutioniPPc, @function
_Z17parallel_solutioniPPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L40
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbp
testq %rax, %rax
jle .L41
pxor %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC12(%rip), %xmm0
mulsd .LC13(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %r14
movl $4, %esi
movq %r14, %rdi
call calloc@PLT
movq %rax, %r12
leaq 0(,%r14,4), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L31:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq .LC4(%rip), %r13
testb $1, %bpl
je .L32
movq .LC3(%rip), %r13
.L32:
testq %r14, %r14
jle .L37
movq %r12, %rax
leaq (%rbx,%r12), %rdx
movq $0x000000000, 8(%rsp)
.L34:
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L34
.L33:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
mulsd .LC7(%rip), %xmm2
movsd %xmm2, 8(%rsp)
movq %rbp, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L43
movsd 8(%rsp), %xmm0
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movq (%rsi), %rdi
call _Z5UsagePc
.L44:
call __stack_chk_fail@PLT
.L41:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
movq (%rbx), %rdi
call _Z5UsagePc
.L45:
call __stack_chk_fail@PLT
.L42:
movq 24(%rsp), %rdi
call _Z28__device_stub__Z9reduce_piPfPf
jmp .L31
.L37:
movq $0x000000000, 8(%rsp)
jmp .L33
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17parallel_solutioniPPc, .-_Z17parallel_solutioniPPc
.section .rodata.str1.8
.align 8
.LC14:
.string "---------------------Sequential execution---------------------\n"
.align 8
.LC15:
.string "----------------------Parallel execution----------------------\n"
.align 8
.LC16:
.string "\nSequential elapsed time: %fs\n"
.section .rodata.str1.1
.LC17:
.string "Parallel elapsed time: %fs\n"
.LC20:
.string "Test PASSED\n"
.LC21:
.string "Test FAILED\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rsi
movl %ebx, %edi
call _Z19sequential_solutioniPPc
movsd %xmm0, (%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rsi
movl %ebx, %edi
call _Z17parallel_solutioniPPc
movsd %xmm0, 8(%rsp)
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm2
subsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
andpd .LC18(%rip), %xmm0
movsd .LC19(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L52
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L49:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z9reduce_piPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reduce_piPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long -1074790400
.align 8
.LC7:
.long 0
.long 1074790400
.align 8
.LC10:
.long 1413754136
.long 1074340347
.align 8
.LC12:
.long 0
.long 1083129856
.align 8
.LC13:
.long 0
.long 1062207488
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC18:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC19:
.long 1202590843
.long 1065646817
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
void Usage(char *prog_name);
#define ACCURACY 0.01
typedef float float_type;
#define KERNEL_ITERATIONS 1000
__device__ void warp_reduce(volatile float_type *sdata, const unsigned int thread_id)
{
sdata[thread_id] += sdata[thread_id + 32];
sdata[thread_id] += sdata[thread_id + 16];
sdata[thread_id] += sdata[thread_id + 8];
sdata[thread_id] += sdata[thread_id + 4];
sdata[thread_id] += sdata[thread_id + 2];
sdata[thread_id] += sdata[thread_id + 1];
}
__global__ void reduce_pi(float_type *gdata)
{
extern __shared__ float_type sdata[];
const unsigned int thread_id = threadIdx.x;
const unsigned long long int i = (((unsigned long long int)blockIdx.x) * blockDim.x + threadIdx.x) * KERNEL_ITERATIONS;
float_type current_thread_factor = 0.0f;
for (int it = 0; it < KERNEL_ITERATIONS; it++)
{
const float factor = ((i + it) & 1) ? -1.0f : 1.0f;
current_thread_factor += factor / (((i + it) << 1) + 1);
}
sdata[thread_id] = current_thread_factor;
__syncthreads();
// reduction in shared memory
for (unsigned int stride = blockDim.x >> 1; stride > 32; stride >>= 1)
{
if (thread_id < stride) {
sdata[thread_id] += sdata[thread_id + stride];
}
__syncthreads();
}
if (thread_id < 32)
warp_reduce(sdata, thread_id);
// write result for this block to global memory
if (thread_id == 0)
gdata[blockIdx.x] = sdata[0];
}
double sequential_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
for (i = 0; i < n; i++)
{
factor = (i % 2 == 0) ? 1.0 : -1.0;
sum += factor / (2 * i + 1);
}
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
double parallel_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
float_type *dev_sum;
float_type *cpu_sum;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
long long block_size = 1024;
long long grid_size = ceil(((double)n / KERNEL_ITERATIONS) / block_size);
cpu_sum = (float_type*)calloc(grid_size, sizeof(float_type));
cudaMalloc(&dev_sum, grid_size * sizeof(float_type));
reduce_pi<<< grid_size, block_size, block_size * sizeof(float_type) >>>(dev_sum);
cudaMemcpy(cpu_sum, dev_sum, grid_size * sizeof(float_type), cudaMemcpyDeviceToHost);
factor = ((n - 1) % 2 == 0) ? 1.0 : -1.0;
for (i = 0; i < grid_size; i++)
sum += cpu_sum[i];
cudaFree(dev_sum);
free(cpu_sum);
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
int main(int argc, char *argv[])
{
float elapsed_time_seq;
cudaEvent_t start_time_seq, end_time_seq;
cudaEventCreate(&start_time_seq);
cudaEventCreate(&end_time_seq);
float elapsed_time_parallel;
cudaEvent_t start_time_parallel, end_time_parallel;
cudaEventCreate(&start_time_parallel);
cudaEventCreate(&end_time_parallel);
printf("---------------------Sequential execution---------------------\n");
cudaEventRecord(start_time_seq, 0);
double sum_seq = sequential_solution(argc, argv);
cudaEventRecord(end_time_seq, 0);
cudaEventSynchronize(end_time_seq);
cudaEventElapsedTime(&elapsed_time_seq, start_time_seq, end_time_seq);
printf("----------------------Parallel execution----------------------\n");
cudaEventRecord(start_time_parallel, 0);
double sum_parallel = parallel_solution(argc, argv);
cudaEventRecord(end_time_parallel, 0);
cudaEventSynchronize(end_time_parallel);
cudaEventElapsedTime(&elapsed_time_parallel, start_time_parallel, end_time_parallel);
printf("\nSequential elapsed time: %fs\n", elapsed_time_seq / 1000.0);
printf("Parallel elapsed time: %fs\n", elapsed_time_parallel / 1000.0);
if (fabs(sum_seq - sum_parallel) < ACCURACY)
printf("Test PASSED\n");
else
printf("Test FAILED\n");
return 0;
}
void Usage(char *prog_name)
{
fprintf(stderr, "usage: %s <n>\n", prog_name);
fprintf(stderr, " n is the number of terms and should be >= 1\n");
exit(0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
void Usage(char *prog_name);
#define ACCURACY 0.01
typedef float float_type;
#define KERNEL_ITERATIONS 1000
__device__ void warp_reduce(volatile float_type *sdata, const unsigned int thread_id)
{
sdata[thread_id] += sdata[thread_id + 32];
sdata[thread_id] += sdata[thread_id + 16];
sdata[thread_id] += sdata[thread_id + 8];
sdata[thread_id] += sdata[thread_id + 4];
sdata[thread_id] += sdata[thread_id + 2];
sdata[thread_id] += sdata[thread_id + 1];
}
__global__ void reduce_pi(float_type *gdata)
{
extern __shared__ float_type sdata[];
const unsigned int thread_id = threadIdx.x;
const unsigned long long int i = (((unsigned long long int)blockIdx.x) * blockDim.x + threadIdx.x) * KERNEL_ITERATIONS;
float_type current_thread_factor = 0.0f;
for (int it = 0; it < KERNEL_ITERATIONS; it++)
{
const float factor = ((i + it) & 1) ? -1.0f : 1.0f;
current_thread_factor += factor / (((i + it) << 1) + 1);
}
sdata[thread_id] = current_thread_factor;
__syncthreads();
// reduction in shared memory
for (unsigned int stride = blockDim.x >> 1; stride > 32; stride >>= 1)
{
if (thread_id < stride) {
sdata[thread_id] += sdata[thread_id + stride];
}
__syncthreads();
}
if (thread_id < 32)
warp_reduce(sdata, thread_id);
// write result for this block to global memory
if (thread_id == 0)
gdata[blockIdx.x] = sdata[0];
}
double sequential_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
for (i = 0; i < n; i++)
{
factor = (i % 2 == 0) ? 1.0 : -1.0;
sum += factor / (2 * i + 1);
}
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
double parallel_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
float_type *dev_sum;
float_type *cpu_sum;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
long long block_size = 1024;
long long grid_size = ceil(((double)n / KERNEL_ITERATIONS) / block_size);
cpu_sum = (float_type*)calloc(grid_size, sizeof(float_type));
hipMalloc(&dev_sum, grid_size * sizeof(float_type));
reduce_pi<<< grid_size, block_size, block_size * sizeof(float_type) >>>(dev_sum);
hipMemcpy(cpu_sum, dev_sum, grid_size * sizeof(float_type), hipMemcpyDeviceToHost);
factor = ((n - 1) % 2 == 0) ? 1.0 : -1.0;
for (i = 0; i < grid_size; i++)
sum += cpu_sum[i];
hipFree(dev_sum);
free(cpu_sum);
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
int main(int argc, char *argv[])
{
float elapsed_time_seq;
hipEvent_t start_time_seq, end_time_seq;
hipEventCreate(&start_time_seq);
hipEventCreate(&end_time_seq);
float elapsed_time_parallel;
hipEvent_t start_time_parallel, end_time_parallel;
hipEventCreate(&start_time_parallel);
hipEventCreate(&end_time_parallel);
printf("---------------------Sequential execution---------------------\n");
hipEventRecord(start_time_seq, 0);
double sum_seq = sequential_solution(argc, argv);
hipEventRecord(end_time_seq, 0);
hipEventSynchronize(end_time_seq);
hipEventElapsedTime(&elapsed_time_seq, start_time_seq, end_time_seq);
printf("----------------------Parallel execution----------------------\n");
hipEventRecord(start_time_parallel, 0);
double sum_parallel = parallel_solution(argc, argv);
hipEventRecord(end_time_parallel, 0);
hipEventSynchronize(end_time_parallel);
hipEventElapsedTime(&elapsed_time_parallel, start_time_parallel, end_time_parallel);
printf("\nSequential elapsed time: %fs\n", elapsed_time_seq / 1000.0);
printf("Parallel elapsed time: %fs\n", elapsed_time_parallel / 1000.0);
if (fabs(sum_seq - sum_parallel) < ACCURACY)
printf("Test PASSED\n");
else
printf("Test FAILED\n");
return 0;
}
void Usage(char *prog_name)
{
fprintf(stderr, "usage: %s <n>\n", prog_name);
fprintf(stderr, " n is the number of terms and should be >= 1\n");
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
void Usage(char *prog_name);
#define ACCURACY 0.01
typedef float float_type;
#define KERNEL_ITERATIONS 1000
__device__ void warp_reduce(volatile float_type *sdata, const unsigned int thread_id)
{
sdata[thread_id] += sdata[thread_id + 32];
sdata[thread_id] += sdata[thread_id + 16];
sdata[thread_id] += sdata[thread_id + 8];
sdata[thread_id] += sdata[thread_id + 4];
sdata[thread_id] += sdata[thread_id + 2];
sdata[thread_id] += sdata[thread_id + 1];
}
__global__ void reduce_pi(float_type *gdata)
{
extern __shared__ float_type sdata[];
const unsigned int thread_id = threadIdx.x;
const unsigned long long int i = (((unsigned long long int)blockIdx.x) * blockDim.x + threadIdx.x) * KERNEL_ITERATIONS;
float_type current_thread_factor = 0.0f;
for (int it = 0; it < KERNEL_ITERATIONS; it++)
{
const float factor = ((i + it) & 1) ? -1.0f : 1.0f;
current_thread_factor += factor / (((i + it) << 1) + 1);
}
sdata[thread_id] = current_thread_factor;
__syncthreads();
// reduction in shared memory
for (unsigned int stride = blockDim.x >> 1; stride > 32; stride >>= 1)
{
if (thread_id < stride) {
sdata[thread_id] += sdata[thread_id + stride];
}
__syncthreads();
}
if (thread_id < 32)
warp_reduce(sdata, thread_id);
// write result for this block to global memory
if (thread_id == 0)
gdata[blockIdx.x] = sdata[0];
}
double sequential_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
for (i = 0; i < n; i++)
{
factor = (i % 2 == 0) ? 1.0 : -1.0;
sum += factor / (2 * i + 1);
}
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
double parallel_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
float_type *dev_sum;
float_type *cpu_sum;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
long long block_size = 1024;
long long grid_size = ceil(((double)n / KERNEL_ITERATIONS) / block_size);
cpu_sum = (float_type*)calloc(grid_size, sizeof(float_type));
hipMalloc(&dev_sum, grid_size * sizeof(float_type));
reduce_pi<<< grid_size, block_size, block_size * sizeof(float_type) >>>(dev_sum);
hipMemcpy(cpu_sum, dev_sum, grid_size * sizeof(float_type), hipMemcpyDeviceToHost);
factor = ((n - 1) % 2 == 0) ? 1.0 : -1.0;
for (i = 0; i < grid_size; i++)
sum += cpu_sum[i];
hipFree(dev_sum);
free(cpu_sum);
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
int main(int argc, char *argv[])
{
float elapsed_time_seq;
hipEvent_t start_time_seq, end_time_seq;
hipEventCreate(&start_time_seq);
hipEventCreate(&end_time_seq);
float elapsed_time_parallel;
hipEvent_t start_time_parallel, end_time_parallel;
hipEventCreate(&start_time_parallel);
hipEventCreate(&end_time_parallel);
printf("---------------------Sequential execution---------------------\n");
hipEventRecord(start_time_seq, 0);
double sum_seq = sequential_solution(argc, argv);
hipEventRecord(end_time_seq, 0);
hipEventSynchronize(end_time_seq);
hipEventElapsedTime(&elapsed_time_seq, start_time_seq, end_time_seq);
printf("----------------------Parallel execution----------------------\n");
hipEventRecord(start_time_parallel, 0);
double sum_parallel = parallel_solution(argc, argv);
hipEventRecord(end_time_parallel, 0);
hipEventSynchronize(end_time_parallel);
hipEventElapsedTime(&elapsed_time_parallel, start_time_parallel, end_time_parallel);
printf("\nSequential elapsed time: %fs\n", elapsed_time_seq / 1000.0);
printf("Parallel elapsed time: %fs\n", elapsed_time_parallel / 1000.0);
if (fabs(sum_seq - sum_parallel) < ACCURACY)
printf("Test PASSED\n");
else
printf("Test FAILED\n");
return 0;
}
void Usage(char *prog_name)
{
fprintf(stderr, "usage: %s <n>\n", prog_name);
fprintf(stderr, " n is the number of terms and should be >= 1\n");
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reduce_piPf
.globl _Z9reduce_piPf
.p2align 8
.type _Z9reduce_piPf,@function
_Z9reduce_piPf:
s_load_b32 s8, s[0:1], 0x14
v_mov_b32_e32 v1, 0
s_mov_b32 s4, s15
s_mov_b32 s3, 0
s_mov_b64 s[6:7], 0
s_mov_b32 s5, s3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s4, v[0:1]
v_mad_u64_u32 v[4:5], null, v2, 0x7d0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v5
v_mad_u64_u32 v[5:6], null, v3, 0x7d0, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v1, 1, v4
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_clz_i32_u32_e32 v4, v2
s_and_b32 s2, s6, 1
s_cmp_eq_u64 s[2:3], 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_min_u32_e32 v6, 32, v4
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s6, 0x3e8
v_lshlrev_b64 v[4:5], v6, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v4, 1, v4
v_or_b32_e32 v4, v5, v4
v_sub_nc_u32_e32 v5, 32, v6
v_cndmask_b32_e64 v6, -1.0, 1.0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, v4
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v4, v4, v6
v_div_scale_f32 v9, vcc_lo, v6, v4, v6
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v5, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v9
v_div_fmas_f32 v5, v5, v7, v8
v_add_co_u32 v1, vcc_lo, v1, 2
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v4, v5, v4, v6
v_add_f32_e32 v3, v3, v4
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
v_cmp_gt_u16_e64 s2, 0x42, s8
v_lshl_add_u32 v1, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_7
s_and_b32 s2, 0xffff, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmpk_lt_u32 s2, 0x42
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_9
v_lshl_add_u32 v5, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x80, v5
v_cmp_ne_u32_e64 s2, -1, v5
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, v5, s2
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, s2
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_add_f32 v6, v4, v6 :: v_dual_add_nc_u32 v3, 64, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_add_f32 v6, v4, v6 :: v_dual_add_nc_u32 v3, 32, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 16, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_f32 v6, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 8, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_f32 v6, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reduce_piPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reduce_piPf, .Lfunc_end0-_Z9reduce_piPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 128
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reduce_piPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reduce_piPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
void Usage(char *prog_name);
#define ACCURACY 0.01
typedef float float_type;
#define KERNEL_ITERATIONS 1000
__device__ void warp_reduce(volatile float_type *sdata, const unsigned int thread_id)
{
sdata[thread_id] += sdata[thread_id + 32];
sdata[thread_id] += sdata[thread_id + 16];
sdata[thread_id] += sdata[thread_id + 8];
sdata[thread_id] += sdata[thread_id + 4];
sdata[thread_id] += sdata[thread_id + 2];
sdata[thread_id] += sdata[thread_id + 1];
}
__global__ void reduce_pi(float_type *gdata)
{
extern __shared__ float_type sdata[];
const unsigned int thread_id = threadIdx.x;
const unsigned long long int i = (((unsigned long long int)blockIdx.x) * blockDim.x + threadIdx.x) * KERNEL_ITERATIONS;
float_type current_thread_factor = 0.0f;
for (int it = 0; it < KERNEL_ITERATIONS; it++)
{
const float factor = ((i + it) & 1) ? -1.0f : 1.0f;
current_thread_factor += factor / (((i + it) << 1) + 1);
}
sdata[thread_id] = current_thread_factor;
__syncthreads();
// reduction in shared memory
for (unsigned int stride = blockDim.x >> 1; stride > 32; stride >>= 1)
{
if (thread_id < stride) {
sdata[thread_id] += sdata[thread_id + stride];
}
__syncthreads();
}
if (thread_id < 32)
warp_reduce(sdata, thread_id);
// write result for this block to global memory
if (thread_id == 0)
gdata[blockIdx.x] = sdata[0];
}
double sequential_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
for (i = 0; i < n; i++)
{
factor = (i % 2 == 0) ? 1.0 : -1.0;
sum += factor / (2 * i + 1);
}
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
double parallel_solution(int argc, char *argv[])
{
long long n, i;
double factor = 0.0;
double sum = 0.0;
float_type *dev_sum;
float_type *cpu_sum;
if (argc != 2)
Usage(argv[0]);
n = strtoll(argv[1], NULL, 10);
if (n < 1)
Usage(argv[0]);
printf("Before for loop, factor = %f.\n", factor);
long long block_size = 1024;
long long grid_size = ceil(((double)n / KERNEL_ITERATIONS) / block_size);
cpu_sum = (float_type*)calloc(grid_size, sizeof(float_type));
hipMalloc(&dev_sum, grid_size * sizeof(float_type));
reduce_pi<<< grid_size, block_size, block_size * sizeof(float_type) >>>(dev_sum);
hipMemcpy(cpu_sum, dev_sum, grid_size * sizeof(float_type), hipMemcpyDeviceToHost);
factor = ((n - 1) % 2 == 0) ? 1.0 : -1.0;
for (i = 0; i < grid_size; i++)
sum += cpu_sum[i];
hipFree(dev_sum);
free(cpu_sum);
printf("After for loop, factor = %f.\n", factor);
sum = 4.0 * sum;
printf("With n = %lld terms\n", n);
printf(" Our estimate of pi = %.14f\n", sum);
printf(" Ref estimate of pi = %.14f\n", 4.0 * atan(1.0));
return sum;
}
int main(int argc, char *argv[])
{
float elapsed_time_seq;
hipEvent_t start_time_seq, end_time_seq;
hipEventCreate(&start_time_seq);
hipEventCreate(&end_time_seq);
float elapsed_time_parallel;
hipEvent_t start_time_parallel, end_time_parallel;
hipEventCreate(&start_time_parallel);
hipEventCreate(&end_time_parallel);
printf("---------------------Sequential execution---------------------\n");
hipEventRecord(start_time_seq, 0);
double sum_seq = sequential_solution(argc, argv);
hipEventRecord(end_time_seq, 0);
hipEventSynchronize(end_time_seq);
hipEventElapsedTime(&elapsed_time_seq, start_time_seq, end_time_seq);
printf("----------------------Parallel execution----------------------\n");
hipEventRecord(start_time_parallel, 0);
double sum_parallel = parallel_solution(argc, argv);
hipEventRecord(end_time_parallel, 0);
hipEventSynchronize(end_time_parallel);
hipEventElapsedTime(&elapsed_time_parallel, start_time_parallel, end_time_parallel);
printf("\nSequential elapsed time: %fs\n", elapsed_time_seq / 1000.0);
printf("Parallel elapsed time: %fs\n", elapsed_time_parallel / 1000.0);
if (fabs(sum_seq - sum_parallel) < ACCURACY)
printf("Test PASSED\n");
else
printf("Test FAILED\n");
return 0;
}
void Usage(char *prog_name)
{
fprintf(stderr, "usage: %s <n>\n", prog_name);
fprintf(stderr, " n is the number of terms and should be >= 1\n");
exit(0);
} | .text
.file "dz4z1.hip"
.globl _Z24__device_stub__reduce_piPf # -- Begin function _Z24__device_stub__reduce_piPf
.p2align 4, 0x90
.type _Z24__device_stub__reduce_piPf,@function
_Z24__device_stub__reduce_piPf: # @_Z24__device_stub__reduce_piPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9reduce_piPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__reduce_piPf, .Lfunc_end0-_Z24__device_stub__reduce_piPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 3, 0x0 # -- Begin function _Z19sequential_solutioniPPc
.LCPI1_0:
.quad 0xbff0000000000000 # double -1
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x4010000000000000 # double 4
.LCPI1_2:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.text
.globl _Z19sequential_solutioniPPc
.p2align 4, 0x90
.type _Z19sequential_solutioniPPc,@function
_Z19sequential_solutioniPPc: # @_Z19sequential_solutioniPPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
cmpl $2, %edi
jne .LBB1_5
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
testq %rax, %rax
jle .LBB1_5
# %bb.2:
movq %rax, %rbx
movl $.L.str, %edi
xorpd %xmm0, %xmm0
movb $1, %al
callq printf
xorpd %xmm3, %xmm3
movl $1, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
xorl %edx, %edx
testb $1, %cl
sete %dl
movsd .LCPI1_0(,%rdx,8), %xmm0 # xmm0 = mem[0],zero
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
addsd %xmm2, %xmm3
incq %rcx
addq $2, %rax
cmpq %rcx, %rbx
jne .LBB1_3
# %bb.4:
movl $.L.str.1, %edi
movb $1, %al
movsd %xmm3, (%rsp) # 8-byte Spill
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 32
movq (%r14), %rdx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $47, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z19sequential_solutioniPPc, .Lfunc_end1-_Z19sequential_solutioniPPc
.cfi_endproc
# -- End function
.globl _Z5UsagePc # -- Begin function _Z5UsagePc
.p2align 4, 0x90
.type _Z5UsagePc,@function
_Z5UsagePc: # @_Z5UsagePc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rdx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $47, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z5UsagePc, .Lfunc_end2-_Z5UsagePc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17parallel_solutioniPPc
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI3_2:
.quad 0x4010000000000000 # double 4
.LCPI3_4:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.section .rodata.cst16,"aM",@progbits,16
.p2align 3, 0x0
.LCPI3_3:
.quad 0x3ff0000000000000 # double 1
.quad 0xbff0000000000000 # double -1
.text
.globl _Z17parallel_solutioniPPc
.p2align 4, 0x90
.type _Z17parallel_solutioniPPc,@function
_Z17parallel_solutioniPPc: # @_Z17parallel_solutioniPPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
cmpl $2, %edi
jne .LBB3_9
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
testq %rax, %rax
jle .LBB3_9
# %bb.2:
movq %rax, %rbx
xorps %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
mulsd .LCPI3_1(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
leaq (,%r15,4), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl %r15d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9reduce_piPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testq %r15, %r15
jle .LBB3_8
# %bb.5: # %.lr.ph.preheader
xorpd %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
incq %rax
cmpq %rax, %r15
jne .LBB3_6
# %bb.7: # %._crit_edge.loopexit
mulsd .LCPI3_2(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
.LBB3_8: # %._crit_edge
xorl %eax, %eax
testb $1, %bl
sete %al
movsd .LCPI3_3(,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movl $.L.str.1, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd .LCPI3_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_9:
.cfi_def_cfa_offset 128
movq (%r14), %rdx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $47, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size _Z17parallel_solutioniPPc, .Lfunc_end3-_Z17parallel_solutioniPPc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.LCPI4_2:
.quad 0x3f847ae147ae147b # double 0.01
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %ebp, %edi
movq %rbx, %rsi
callq _Z19sequential_solutioniPPc
movaps %xmm0, 48(%rsp) # 16-byte Spill
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %ebp, %edi
movq %rbx, %rsi
callq _Z17parallel_solutioniPPc
movsd %xmm0, 40(%rsp) # 8-byte Spill
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movapd 48(%rsp), %xmm0 # 16-byte Reload
subsd 40(%rsp), %xmm0 # 8-byte Folded Reload
andpd .LCPI4_1(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
movl $.Lstr.3, %eax
movl $.Lstr.2, %edi
cmovaq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reduce_piPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reduce_piPf,@object # @_Z9reduce_piPf
.section .rodata,"a",@progbits
.globl _Z9reduce_piPf
.p2align 3, 0x0
_Z9reduce_piPf:
.quad _Z24__device_stub__reduce_piPf
.size _Z9reduce_piPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Before for loop, factor = %f.\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "After for loop, factor = %f.\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "With n = %lld terms\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Our estimate of pi = %.14f\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Ref estimate of pi = %.14f\n"
.size .L.str.4, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nSequential elapsed time: %fs\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Parallel elapsed time: %fs\n"
.size .L.str.8, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "usage: %s <n>\n"
.size .L.str.11, 15
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " n is the number of terms and should be >= 1\n"
.size .L.str.12, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reduce_piPf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "---------------------Sequential execution---------------------"
.size .Lstr, 63
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "----------------------Parallel execution----------------------"
.size .Lstr.1, 63
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test FAILED"
.size .Lstr.2, 12
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Test PASSED"
.size .Lstr.3, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reduce_piPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reduce_piPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00043036_00000000-6_dz4z1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11warp_reducePVfj
.type _Z11warp_reducePVfj, @function
_Z11warp_reducePVfj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11warp_reducePVfj, .-_Z11warp_reducePVfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: %s <n>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " n is the number of terms and should be >= 1\n"
.text
.globl _Z5UsagePc
.type _Z5UsagePc, @function
_Z5UsagePc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z5UsagePc, .-_Z5UsagePc
.section .rodata.str1.8
.align 8
.LC5:
.string "Before for loop, factor = %f.\n"
.section .rodata.str1.1
.LC6:
.string "After for loop, factor = %f.\n"
.LC8:
.string "With n = %lld terms\n"
.section .rodata.str1.8
.align 8
.LC9:
.string " Our estimate of pi = %.14f\n"
.align 8
.LC11:
.string " Ref estimate of pi = %.14f\n"
.text
.globl _Z19sequential_solutioniPPc
.type _Z19sequential_solutioniPPc, @function
_Z19sequential_solutioniPPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
cmpl $2, %edi
jne .L15
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbp
testq %rax, %rax
jle .L16
pxor %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %eax
movq $0x000000000, 8(%rsp)
movl $0, %ebx
movsd .LC4(%rip), %xmm3
jmp .L11
.L15:
movq (%rsi), %rdi
call _Z5UsagePc
.L16:
movq (%rbx), %rdi
call _Z5UsagePc
.L10:
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movapd %xmm0, %xmm1
divsd %xmm2, %xmm1
addsd 8(%rsp), %xmm1
movsd %xmm1, 8(%rsp)
addq $1, %rbx
addq $2, %rax
cmpq %rbx, %rbp
je .L17
.L11:
movapd %xmm3, %xmm0
testb $1, %bl
jne .L10
movsd .LC3(%rip), %xmm0
jmp .L10
.L17:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm5
mulsd .LC7(%rip), %xmm5
movsd %xmm5, 8(%rsp)
movq %rbx, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z19sequential_solutioniPPc, .-_Z19sequential_solutioniPPc
.globl _Z28__device_stub__Z9reduce_piPfPf
.type _Z28__device_stub__Z9reduce_piPfPf, @function
_Z28__device_stub__Z9reduce_piPfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reduce_piPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z9reduce_piPfPf, .-_Z28__device_stub__Z9reduce_piPfPf
.globl _Z9reduce_piPf
.type _Z9reduce_piPf, @function
_Z9reduce_piPf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9reduce_piPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9reduce_piPf, .-_Z9reduce_piPf
.globl _Z17parallel_solutioniPPc
.type _Z17parallel_solutioniPPc, @function
_Z17parallel_solutioniPPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L40
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbp
testq %rax, %rax
jle .L41
pxor %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC12(%rip), %xmm0
mulsd .LC13(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %r14
movl $4, %esi
movq %r14, %rdi
call calloc@PLT
movq %rax, %r12
leaq 0(,%r14,4), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L31:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq .LC4(%rip), %r13
testb $1, %bpl
je .L32
movq .LC3(%rip), %r13
.L32:
testq %r14, %r14
jle .L37
movq %r12, %rax
leaq (%rbx,%r12), %rdx
movq $0x000000000, 8(%rsp)
.L34:
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L34
.L33:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
mulsd .LC7(%rip), %xmm2
movsd %xmm2, 8(%rsp)
movq %rbp, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L43
movsd 8(%rsp), %xmm0
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movq (%rsi), %rdi
call _Z5UsagePc
.L44:
call __stack_chk_fail@PLT
.L41:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
movq (%rbx), %rdi
call _Z5UsagePc
.L45:
call __stack_chk_fail@PLT
.L42:
movq 24(%rsp), %rdi
call _Z28__device_stub__Z9reduce_piPfPf
jmp .L31
.L37:
movq $0x000000000, 8(%rsp)
jmp .L33
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17parallel_solutioniPPc, .-_Z17parallel_solutioniPPc
.section .rodata.str1.8
.align 8
.LC14:
.string "---------------------Sequential execution---------------------\n"
.align 8
.LC15:
.string "----------------------Parallel execution----------------------\n"
.align 8
.LC16:
.string "\nSequential elapsed time: %fs\n"
.section .rodata.str1.1
.LC17:
.string "Parallel elapsed time: %fs\n"
.LC20:
.string "Test PASSED\n"
.LC21:
.string "Test FAILED\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rsi
movl %ebx, %edi
call _Z19sequential_solutioniPPc
movsd %xmm0, (%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rsi
movl %ebx, %edi
call _Z17parallel_solutioniPPc
movsd %xmm0, 8(%rsp)
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm2
subsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
andpd .LC18(%rip), %xmm0
movsd .LC19(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L52
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L49:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z9reduce_piPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reduce_piPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long -1074790400
.align 8
.LC7:
.long 0
.long 1074790400
.align 8
.LC10:
.long 1413754136
.long 1074340347
.align 8
.LC12:
.long 0
.long 1083129856
.align 8
.LC13:
.long 0
.long 1062207488
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC18:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC19:
.long 1202590843
.long 1065646817
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dz4z1.hip"
.globl _Z24__device_stub__reduce_piPf # -- Begin function _Z24__device_stub__reduce_piPf
.p2align 4, 0x90
.type _Z24__device_stub__reduce_piPf,@function
_Z24__device_stub__reduce_piPf: # @_Z24__device_stub__reduce_piPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9reduce_piPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__reduce_piPf, .Lfunc_end0-_Z24__device_stub__reduce_piPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 3, 0x0 # -- Begin function _Z19sequential_solutioniPPc
.LCPI1_0:
.quad 0xbff0000000000000 # double -1
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x4010000000000000 # double 4
.LCPI1_2:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.text
.globl _Z19sequential_solutioniPPc
.p2align 4, 0x90
.type _Z19sequential_solutioniPPc,@function
_Z19sequential_solutioniPPc: # @_Z19sequential_solutioniPPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
cmpl $2, %edi
jne .LBB1_5
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
testq %rax, %rax
jle .LBB1_5
# %bb.2:
movq %rax, %rbx
movl $.L.str, %edi
xorpd %xmm0, %xmm0
movb $1, %al
callq printf
xorpd %xmm3, %xmm3
movl $1, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
xorl %edx, %edx
testb $1, %cl
sete %dl
movsd .LCPI1_0(,%rdx,8), %xmm0 # xmm0 = mem[0],zero
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
addsd %xmm2, %xmm3
incq %rcx
addq $2, %rax
cmpq %rcx, %rbx
jne .LBB1_3
# %bb.4:
movl $.L.str.1, %edi
movb $1, %al
movsd %xmm3, (%rsp) # 8-byte Spill
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 32
movq (%r14), %rdx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $47, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z19sequential_solutioniPPc, .Lfunc_end1-_Z19sequential_solutioniPPc
.cfi_endproc
# -- End function
.globl _Z5UsagePc # -- Begin function _Z5UsagePc
.p2align 4, 0x90
.type _Z5UsagePc,@function
_Z5UsagePc: # @_Z5UsagePc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rdx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $47, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z5UsagePc, .Lfunc_end2-_Z5UsagePc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17parallel_solutioniPPc
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI3_2:
.quad 0x4010000000000000 # double 4
.LCPI3_4:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.section .rodata.cst16,"aM",@progbits,16
.p2align 3, 0x0
.LCPI3_3:
.quad 0x3ff0000000000000 # double 1
.quad 0xbff0000000000000 # double -1
.text
.globl _Z17parallel_solutioniPPc
.p2align 4, 0x90
.type _Z17parallel_solutioniPPc,@function
_Z17parallel_solutioniPPc: # @_Z17parallel_solutioniPPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
cmpl $2, %edi
jne .LBB3_9
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
testq %rax, %rax
jle .LBB3_9
# %bb.2:
movq %rax, %rbx
xorps %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
mulsd .LCPI3_1(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
leaq (,%r15,4), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl %r15d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9reduce_piPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testq %r15, %r15
jle .LBB3_8
# %bb.5: # %.lr.ph.preheader
xorpd %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
incq %rax
cmpq %rax, %r15
jne .LBB3_6
# %bb.7: # %._crit_edge.loopexit
mulsd .LCPI3_2(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
.LBB3_8: # %._crit_edge
xorl %eax, %eax
testb $1, %bl
sete %al
movsd .LCPI3_3(,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movl $.L.str.1, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd .LCPI3_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_9:
.cfi_def_cfa_offset 128
movq (%r14), %rdx
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $47, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size _Z17parallel_solutioniPPc, .Lfunc_end3-_Z17parallel_solutioniPPc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.LCPI4_2:
.quad 0x3f847ae147ae147b # double 0.01
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %ebp, %edi
movq %rbx, %rsi
callq _Z19sequential_solutioniPPc
movaps %xmm0, 48(%rsp) # 16-byte Spill
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %ebp, %edi
movq %rbx, %rsi
callq _Z17parallel_solutioniPPc
movsd %xmm0, 40(%rsp) # 8-byte Spill
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movapd 48(%rsp), %xmm0 # 16-byte Reload
subsd 40(%rsp), %xmm0 # 8-byte Folded Reload
andpd .LCPI4_1(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
movl $.Lstr.3, %eax
movl $.Lstr.2, %edi
cmovaq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reduce_piPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reduce_piPf,@object # @_Z9reduce_piPf
.section .rodata,"a",@progbits
.globl _Z9reduce_piPf
.p2align 3, 0x0
_Z9reduce_piPf:
.quad _Z24__device_stub__reduce_piPf
.size _Z9reduce_piPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Before for loop, factor = %f.\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "After for loop, factor = %f.\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "With n = %lld terms\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Our estimate of pi = %.14f\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Ref estimate of pi = %.14f\n"
.size .L.str.4, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nSequential elapsed time: %fs\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Parallel elapsed time: %fs\n"
.size .L.str.8, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "usage: %s <n>\n"
.size .L.str.11, 15
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " n is the number of terms and should be >= 1\n"
.size .L.str.12, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reduce_piPf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "---------------------Sequential execution---------------------"
.size .Lstr, 63
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "----------------------Parallel execution----------------------"
.size .Lstr.1, 63
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test FAILED"
.size .Lstr.2, 12
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Test PASSED"
.size .Lstr.3, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reduce_piPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reduce_piPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void hoCalc(double* rn, double* soilHeat, double* ho, int width_band) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < width_band) {
ho[col] = rn[col] - soilHeat[col];
col += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z6hoCalcPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, -R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000102 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void hoCalc(double* rn, double* soilHeat, double* ho, int width_band) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < width_band) {
ho[col] = rn[col] - soilHeat[col];
col += blockDim.x * gridDim.x;
}
} | .file "tmpxft_00197d1a_00000000-6_hoCalc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6hoCalcPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i
.globl _Z6hoCalcPdS_S_i
.type _Z6hoCalcPdS_S_i, @function
_Z6hoCalcPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6hoCalcPdS_S_i, .-_Z6hoCalcPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6hoCalcPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6hoCalcPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void hoCalc(double* rn, double* soilHeat, double* ho, int width_band) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < width_band) {
ho[col] = rn[col] - soilHeat[col];
col += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void hoCalc(double* rn, double* soilHeat, double* ho, int width_band) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < width_band) {
ho[col] = rn[col] - soilHeat[col];
col += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void hoCalc(double* rn, double* soilHeat, double* ho, int width_band) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < width_band) {
ho[col] = rn[col] - soilHeat[col];
col += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6hoCalcPdS_S_i
.globl _Z6hoCalcPdS_S_i
.p2align 8
.type _Z6hoCalcPdS_S_i,@function
_Z6hoCalcPdS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], -v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6hoCalcPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6hoCalcPdS_S_i, .Lfunc_end0-_Z6hoCalcPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6hoCalcPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6hoCalcPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void hoCalc(double* rn, double* soilHeat, double* ho, int width_band) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < width_band) {
ho[col] = rn[col] - soilHeat[col];
col += blockDim.x * gridDim.x;
}
} | .text
.file "hoCalc.hip"
.globl _Z21__device_stub__hoCalcPdS_S_i # -- Begin function _Z21__device_stub__hoCalcPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__hoCalcPdS_S_i,@function
_Z21__device_stub__hoCalcPdS_S_i: # @_Z21__device_stub__hoCalcPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6hoCalcPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__hoCalcPdS_S_i, .Lfunc_end0-_Z21__device_stub__hoCalcPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6hoCalcPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6hoCalcPdS_S_i,@object # @_Z6hoCalcPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6hoCalcPdS_S_i
.p2align 3, 0x0
_Z6hoCalcPdS_S_i:
.quad _Z21__device_stub__hoCalcPdS_S_i
.size _Z6hoCalcPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6hoCalcPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__hoCalcPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6hoCalcPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6hoCalcPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, -R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000102 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6hoCalcPdS_S_i
.globl _Z6hoCalcPdS_S_i
.p2align 8
.type _Z6hoCalcPdS_S_i,@function
_Z6hoCalcPdS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], -v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6hoCalcPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6hoCalcPdS_S_i, .Lfunc_end0-_Z6hoCalcPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6hoCalcPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6hoCalcPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00197d1a_00000000-6_hoCalc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6hoCalcPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i
.globl _Z6hoCalcPdS_S_i
.type _Z6hoCalcPdS_S_i, @function
_Z6hoCalcPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6hoCalcPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6hoCalcPdS_S_i, .-_Z6hoCalcPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6hoCalcPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6hoCalcPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hoCalc.hip"
.globl _Z21__device_stub__hoCalcPdS_S_i # -- Begin function _Z21__device_stub__hoCalcPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__hoCalcPdS_S_i,@function
_Z21__device_stub__hoCalcPdS_S_i: # @_Z21__device_stub__hoCalcPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6hoCalcPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__hoCalcPdS_S_i, .Lfunc_end0-_Z21__device_stub__hoCalcPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6hoCalcPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6hoCalcPdS_S_i,@object # @_Z6hoCalcPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6hoCalcPdS_S_i
.p2align 3, 0x0
_Z6hoCalcPdS_S_i:
.quad _Z21__device_stub__hoCalcPdS_S_i
.size _Z6hoCalcPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6hoCalcPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__hoCalcPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6hoCalcPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Copyright (C) 2007-2012 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Anoop Saldanha <anoopsaldanha@gmail.com>
*
* The Cuda kernel for MPM AC.
*
* \todo - This is a basic version of the kernel.
* - Support 16 bit state tables.
* - Texture memory.
* - Multiple threads per blocks of threads. Make use of
* shared memory/texture memory.
*/
#define FRAGNUM 4
extern "C"
__global__ void SCACCudaSearch64(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int pid = blockIdx.x * blockDim.x + threadIdx.x; //packet id
unsigned int fid = threadIdx.y; //fragment id
if (pid >= nop)
return;
unsigned int buflen = *((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 8));
unsigned int *state_depth_table = (unsigned int *)*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 16));
unsigned char *buf = (d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 24);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int fraglen = buflen / FRAGNUM;
unsigned int fragbeg = fraglen * fid;
unsigned int fragend = fragbeg + fraglen;
if(fid == FRAGNUM - 1)
fragend = buflen;
unsigned int *results = (results_buffer + ((o_buffer[pid] - d_buffer_start_offset + fragbeg) * 2) + 1);
for (u = fragbeg; u < fragend; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
unsigned int distance = 0;
for( ; u < buflen;u++)
{
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
distance++;
if(state_depth_table[state & 0x00FFFFFF] <= distance)
break;
if(state & 0xFF000000)
{
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
/* if(fid == FRAGNUM - 1)
{
unsigned int *res = results_buffer + ((o_buffer[pid] - d_buffer_start_offset) * 2);
for(unsigned int i = 0; i < buflen * 2 ; i++)
{
printf("%d ",res[i]);
}
printf("\n");
}
*/
return;
}
extern "C"
__global__ void SCACCudaSearch32(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= nop)
return;
unsigned int buflen = *((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 4));
unsigned char *buf = (d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 8);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int *results = (results_buffer + ((o_buffer[tid] - d_buffer_start_offset) * 2) + 1);
for (u = 0; u < buflen; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
return;
} | .file "tmpxft_000da6d8_00000000-6_util-mpm-ac-cuda-kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_
.type _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_, @function
_Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq SCACCudaSearch64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_, .-_Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_
.globl SCACCudaSearch64
.type SCACCudaSearch64, @function
SCACCudaSearch64:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size SCACCudaSearch64, .-SCACCudaSearch64
.globl _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_
.type _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_, @function
_Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq SCACCudaSearch32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_, .-_Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_
.globl SCACCudaSearch32
.type SCACCudaSearch32, @function
SCACCudaSearch32:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size SCACCudaSearch32, .-SCACCudaSearch32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "SCACCudaSearch32"
.LC1:
.string "SCACCudaSearch64"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq SCACCudaSearch32(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq SCACCudaSearch64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Copyright (C) 2007-2012 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Anoop Saldanha <anoopsaldanha@gmail.com>
*
* The Cuda kernel for MPM AC.
*
* \todo - This is a basic version of the kernel.
* - Support 16 bit state tables.
* - Texture memory.
* - Multiple threads per blocks of threads. Make use of
* shared memory/texture memory.
*/
#define FRAGNUM 4
extern "C"
__global__ void SCACCudaSearch64(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int pid = blockIdx.x * blockDim.x + threadIdx.x; //packet id
unsigned int fid = threadIdx.y; //fragment id
if (pid >= nop)
return;
unsigned int buflen = *((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 8));
unsigned int *state_depth_table = (unsigned int *)*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 16));
unsigned char *buf = (d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 24);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int fraglen = buflen / FRAGNUM;
unsigned int fragbeg = fraglen * fid;
unsigned int fragend = fragbeg + fraglen;
if(fid == FRAGNUM - 1)
fragend = buflen;
unsigned int *results = (results_buffer + ((o_buffer[pid] - d_buffer_start_offset + fragbeg) * 2) + 1);
for (u = fragbeg; u < fragend; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
unsigned int distance = 0;
for( ; u < buflen;u++)
{
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
distance++;
if(state_depth_table[state & 0x00FFFFFF] <= distance)
break;
if(state & 0xFF000000)
{
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
/* if(fid == FRAGNUM - 1)
{
unsigned int *res = results_buffer + ((o_buffer[pid] - d_buffer_start_offset) * 2);
for(unsigned int i = 0; i < buflen * 2 ; i++)
{
printf("%d ",res[i]);
}
printf("\n");
}
*/
return;
}
extern "C"
__global__ void SCACCudaSearch32(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= nop)
return;
unsigned int buflen = *((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 4));
unsigned char *buf = (d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 8);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int *results = (results_buffer + ((o_buffer[tid] - d_buffer_start_offset) * 2) + 1);
for (u = 0; u < buflen; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
return;
} | #include <hip/hip_runtime.h>
/* Copyright (C) 2007-2012 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Anoop Saldanha <anoopsaldanha@gmail.com>
*
* The Cuda kernel for MPM AC.
*
* \todo - This is a basic version of the kernel.
* - Support 16 bit state tables.
* - Texture memory.
* - Multiple threads per blocks of threads. Make use of
* shared memory/texture memory.
*/
#define FRAGNUM 4
extern "C"
__global__ void SCACCudaSearch64(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int pid = blockIdx.x * blockDim.x + threadIdx.x; //packet id
unsigned int fid = threadIdx.y; //fragment id
if (pid >= nop)
return;
unsigned int buflen = *((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 8));
unsigned int *state_depth_table = (unsigned int *)*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 16));
unsigned char *buf = (d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 24);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int fraglen = buflen / FRAGNUM;
unsigned int fragbeg = fraglen * fid;
unsigned int fragend = fragbeg + fraglen;
if(fid == FRAGNUM - 1)
fragend = buflen;
unsigned int *results = (results_buffer + ((o_buffer[pid] - d_buffer_start_offset + fragbeg) * 2) + 1);
for (u = fragbeg; u < fragend; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
unsigned int distance = 0;
for( ; u < buflen;u++)
{
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
distance++;
if(state_depth_table[state & 0x00FFFFFF] <= distance)
break;
if(state & 0xFF000000)
{
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
/* if(fid == FRAGNUM - 1)
{
unsigned int *res = results_buffer + ((o_buffer[pid] - d_buffer_start_offset) * 2);
for(unsigned int i = 0; i < buflen * 2 ; i++)
{
printf("%d ",res[i]);
}
printf("\n");
}
*/
return;
}
extern "C"
__global__ void SCACCudaSearch32(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= nop)
return;
unsigned int buflen = *((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 4));
unsigned char *buf = (d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 8);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int *results = (results_buffer + ((o_buffer[tid] - d_buffer_start_offset) * 2) + 1);
for (u = 0; u < buflen; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* Copyright (C) 2007-2012 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Anoop Saldanha <anoopsaldanha@gmail.com>
*
* The Cuda kernel for MPM AC.
*
* \todo - This is a basic version of the kernel.
* - Support 16 bit state tables.
* - Texture memory.
* - Multiple threads per blocks of threads. Make use of
* shared memory/texture memory.
*/
#define FRAGNUM 4
extern "C"
__global__ void SCACCudaSearch64(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int pid = blockIdx.x * blockDim.x + threadIdx.x; //packet id
unsigned int fid = threadIdx.y; //fragment id
if (pid >= nop)
return;
unsigned int buflen = *((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 8));
unsigned int *state_depth_table = (unsigned int *)*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 16));
unsigned char *buf = (d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 24);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int fraglen = buflen / FRAGNUM;
unsigned int fragbeg = fraglen * fid;
unsigned int fragend = fragbeg + fraglen;
if(fid == FRAGNUM - 1)
fragend = buflen;
unsigned int *results = (results_buffer + ((o_buffer[pid] - d_buffer_start_offset + fragbeg) * 2) + 1);
for (u = fragbeg; u < fragend; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
unsigned int distance = 0;
for( ; u < buflen;u++)
{
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
distance++;
if(state_depth_table[state & 0x00FFFFFF] <= distance)
break;
if(state & 0xFF000000)
{
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
/* if(fid == FRAGNUM - 1)
{
unsigned int *res = results_buffer + ((o_buffer[pid] - d_buffer_start_offset) * 2);
for(unsigned int i = 0; i < buflen * 2 ; i++)
{
printf("%d ",res[i]);
}
printf("\n");
}
*/
return;
}
extern "C"
__global__ void SCACCudaSearch32(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= nop)
return;
unsigned int buflen = *((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 4));
unsigned char *buf = (d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 8);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int *results = (results_buffer + ((o_buffer[tid] - d_buffer_start_offset) * 2) + 1);
for (u = 0; u < buflen; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected SCACCudaSearch64
.globl SCACCudaSearch64
.p2align 8
.type SCACCudaSearch64,@function
SCACCudaSearch64:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s15, s2, v[1:2]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v5
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v6, 0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_nc_u32_e32 v7, s4, v1
s_clause 0x1
global_load_b32 v14, v7, s[0:1]
global_load_b128 v[1:4], v7, s[0:1] offset:8
s_waitcnt vmcnt(1)
v_lshrrev_b32_e32 v8, 2, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v8, v0
v_add_nc_u32_e32 v11, v9, v8
v_add_lshl_u32 v5, v9, v7, 1
v_add_co_u32 v7, s0, s0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, null, s1, 0, s0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, v7, 24
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v10, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v0
v_mov_b32_e32 v16, 0
v_dual_mov_b32 v8, v9 :: v_dual_mov_b32 v7, 0
s_mov_b32 s1, 0
v_cndmask_b32_e32 v11, v11, v14, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, v5, 4
v_add_co_ci_u32_e64 v15, s0, 0, v6, s0
s_mov_b32 s0, exec_lo
v_cmpx_lt_u32_e64 v9, v11
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v7, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v13, v10
v_mov_b32_e32 v12, v9
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v12, vcc_lo, v12, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v12, v11
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v19, vcc_lo, v17, v12
v_add_co_ci_u32_e32 v20, vcc_lo, v18, v13, vcc_lo
global_load_u8 v8, v[19:20], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v8, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v19, s4, s2, v8
v_add_co_ci_u32_e64 v20, null, s3, 0, s4
s_mov_b32 s4, exec_lo
global_load_u8 v8, v[19:20], off
v_dual_mov_b32 v20, 0 :: v_dual_and_b32 v19, 0xffffff, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[19:20], 10, v[19:20]
v_add_co_u32 v10, vcc_lo, v1, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v16, vcc_lo, v2, v20, vcc_lo
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v8, 2, v8
v_add_co_u32 v19, vcc_lo, v10, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v16, vcc_lo
flat_load_b32 v16, v[19:20]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_u32_e32 0xffffff, v16
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v19, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mov_b32_e32 v20, v8
v_lshlrev_b64 v[21:22], 2, v[7:8]
v_add_nc_u32_e32 v7, 2, v7
v_and_b32_e32 v8, 0xffffff, v16
v_lshlrev_b64 v[19:20], 2, v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v21, vcc_lo, v0, v21
v_add_co_ci_u32_e32 v22, vcc_lo, v15, v22, vcc_lo
v_add_co_u32 v19, vcc_lo, v0, v19
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v20, vcc_lo, v15, v20, vcc_lo
s_clause 0x1
global_store_b32 v[21:22], v12, off
global_store_b32 v[19:20], v8, off
s_branch .LBB0_3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v8, v11
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s4, exec_lo
v_cmpx_lt_u32_e64 v8, v14
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v12, 0
s_mov_b32 s5, 0
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v10, v12
v_cmp_gt_u64_e32 vcc_lo, v[11:12], v[9:10]
v_cndmask_b32_e32 v9, v9, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v10, vcc_lo, v17, v9
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v18, vcc_lo
s_branch .LBB0_11
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s8
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
v_add_nc_u32_e32 v8, s0, v9
s_and_not1_b32 s6, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v8, v14
s_and_b32 s8, vcc_lo, exec_lo
s_or_b32 s6, s6, s8
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s6
s_or_b32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_14
.LBB0_11:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v10, s0
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
s_or_b32 s6, s6, exec_lo
global_load_u8 v8, v[12:13], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v8, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s7, s2, v8
v_add_co_ci_u32_e64 v13, null, s3, 0, s7
s_add_i32 s7, s0, 1
global_load_u8 v8, v[12:13], off
v_dual_mov_b32 v13, 0 :: v_dual_and_b32 v12, 0xffffff, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 10, v[12:13]
v_add_co_u32 v12, vcc_lo, v1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v13, vcc_lo, v2, v13, vcc_lo
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v8, 2, v8
v_add_co_u32 v12, vcc_lo, v12, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
flat_load_b32 v16, v[12:13]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v12, 0xffffff, v16
v_lshlrev_b32_e32 v8, 2, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v17, vcc_lo, v3, v8
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
flat_load_b32 v8, v[17:18]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, s7, v8
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_10
s_mov_b32 s8, exec_lo
v_cmpx_lt_u32_e32 0xffffff, v16
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v17, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mov_b32_e32 v18, v8
v_lshlrev_b64 v[19:20], 2, v[7:8]
v_add_nc_u32_e32 v7, 2, v7
v_add_nc_u32_e32 v8, s0, v9
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v19, vcc_lo, v0, v19
v_add_co_ci_u32_e32 v20, vcc_lo, v15, v20, vcc_lo
v_add_co_u32 v17, vcc_lo, v0, v17
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v18, vcc_lo, v15, v18, vcc_lo
s_clause 0x1
global_store_b32 v[19:20], v8, off
global_store_b32 v[17:18], v12, off
s_branch .LBB0_9
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
global_store_b32 v[5:6], v7, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel SCACCudaSearch64
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size SCACCudaSearch64, .Lfunc_end0-SCACCudaSearch64
.section .AMDGPU.csdata,"",@progbits
.text
.protected SCACCudaSearch32
.globl SCACCudaSearch32
.p2align 8
.type SCACCudaSearch32,@function
SCACCudaSearch32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_8
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s5, 0
global_load_b32 v0, v[0:1], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_nc_u32_e32 v3, s4, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v3
global_load_b32 v4, v3, s[2:3]
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB1_7
v_add_co_u32 v2, s2, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x28
v_mov_b32_e32 v6, 0
v_add_co_u32 v7, vcc_lo, v2, 8
global_load_b32 v5, v[2:3], off offset:4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v1, vcc_lo
v_mov_b32_e32 v2, v6
v_mov_b32_e32 v11, v6
s_mov_b64 s[2:3], 0
s_branch .LBB1_4
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s6
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_cmp_eq_u32_e32 vcc_lo, s2, v4
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_6
.LBB1_4:
v_add_co_u32 v12, vcc_lo, v7, s2
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v8, vcc_lo
v_and_b32_e32 v11, 0xffffff, v11
global_load_u8 v3, v[12:13], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0xffff, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s6, s0, v3
v_add_co_ci_u32_e64 v13, null, s1, 0, s6
s_mov_b32 s6, exec_lo
global_load_u8 v3, v[12:13], off
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 10, v[11:12]
v_add_co_u32 v11, vcc_lo, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v12, vcc_lo, v6, v12, vcc_lo
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v3, 2, v3
v_add_co_u32 v11, vcc_lo, v11, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
flat_load_b32 v11, v[11:12]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_u32_e32 0xffffff, v11
s_cbranch_execz .LBB1_3
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v12, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mov_b32 v13, v3 :: v_dual_and_b32 v16, 0xffffff, v11
v_lshlrev_b64 v[14:15], 2, v[2:3]
v_dual_mov_b32 v3, s2 :: v_dual_add_nc_u32 v2, 2, v2
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, v9, v14
v_add_co_ci_u32_e32 v15, vcc_lo, v10, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, v9, v12
v_add_co_ci_u32_e32 v13, vcc_lo, v10, v13, vcc_lo
s_clause 0x1
global_store_b32 v[14:15], v3, off
global_store_b32 v[12:13], v16, off
s_branch .LBB1_3
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s5
.LBB1_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
global_store_b32 v[0:1], v2, off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel SCACCudaSearch32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size SCACCudaSearch32, .Lfunc_end1-SCACCudaSearch32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: SCACCudaSearch64
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: SCACCudaSearch64.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: SCACCudaSearch32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: SCACCudaSearch32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* Copyright (C) 2007-2012 Open Information Security Foundation
*
* You can copy, redistribute or modify this Program under the terms of
* the GNU General Public License version 2 as published by the Free
* Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* \file
*
* \author Anoop Saldanha <anoopsaldanha@gmail.com>
*
* The Cuda kernel for MPM AC.
*
* \todo - This is a basic version of the kernel.
* - Support 16 bit state tables.
* - Texture memory.
* - Multiple threads per blocks of threads. Make use of
* shared memory/texture memory.
*/
#define FRAGNUM 4
extern "C"
__global__ void SCACCudaSearch64(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int pid = blockIdx.x * blockDim.x + threadIdx.x; //packet id
unsigned int fid = threadIdx.y; //fragment id
if (pid >= nop)
return;
unsigned int buflen = *((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 8));
unsigned int *state_depth_table = (unsigned int *)*((unsigned long *)(d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 16));
unsigned char *buf = (d_buffer + (o_buffer[pid] - d_buffer_start_offset) + 24);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int fraglen = buflen / FRAGNUM;
unsigned int fragbeg = fraglen * fid;
unsigned int fragend = fragbeg + fraglen;
if(fid == FRAGNUM - 1)
fragend = buflen;
unsigned int *results = (results_buffer + ((o_buffer[pid] - d_buffer_start_offset + fragbeg) * 2) + 1);
for (u = fragbeg; u < fragend; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
unsigned int distance = 0;
for( ; u < buflen;u++)
{
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
distance++;
if(state_depth_table[state & 0x00FFFFFF] <= distance)
break;
if(state & 0xFF000000)
{
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
/* if(fid == FRAGNUM - 1)
{
unsigned int *res = results_buffer + ((o_buffer[pid] - d_buffer_start_offset) * 2);
for(unsigned int i = 0; i < buflen * 2 ; i++)
{
printf("%d ",res[i]);
}
printf("\n");
}
*/
return;
}
extern "C"
__global__ void SCACCudaSearch32(unsigned char *d_buffer,
unsigned int d_buffer_start_offset,
unsigned int *o_buffer,
unsigned int *results_buffer,
unsigned int nop,
unsigned char *tolower)
{
unsigned int u = 0;
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= nop)
return;
unsigned int buflen = *((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset)));
unsigned int (*state_table_u32)[256] =
(unsigned int (*)[256])*((unsigned int *)(d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 4));
unsigned char *buf = (d_buffer + (o_buffer[tid] - d_buffer_start_offset) + 8);
unsigned int state = 0;
unsigned int matches = 0;
unsigned int *results = (results_buffer + ((o_buffer[tid] - d_buffer_start_offset) * 2) + 1);
for (u = 0; u < buflen; u++) {
state = state_table_u32[state & 0x00FFFFFF][tolower[buf[u]]];
if (state & 0xFF000000) {
results[matches++] = u;
results[matches++] = state & 0x00FFFFFF;
}
}
*(results - 1) = matches;
return;
} | .text
.file "util-mpm-ac-cuda-kernel.hip"
.globl __device_stub__SCACCudaSearch64 # -- Begin function __device_stub__SCACCudaSearch64
.p2align 4, 0x90
.type __device_stub__SCACCudaSearch64,@function
__device_stub__SCACCudaSearch64: # @__device_stub__SCACCudaSearch64
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $SCACCudaSearch64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__SCACCudaSearch64, .Lfunc_end0-__device_stub__SCACCudaSearch64
.cfi_endproc
# -- End function
.globl __device_stub__SCACCudaSearch32 # -- Begin function __device_stub__SCACCudaSearch32
.p2align 4, 0x90
.type __device_stub__SCACCudaSearch32,@function
__device_stub__SCACCudaSearch32: # @__device_stub__SCACCudaSearch32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $SCACCudaSearch32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__SCACCudaSearch32, .Lfunc_end1-__device_stub__SCACCudaSearch32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $SCACCudaSearch64, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $SCACCudaSearch32, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type SCACCudaSearch64,@object # @SCACCudaSearch64
.section .rodata,"a",@progbits
.globl SCACCudaSearch64
.p2align 3, 0x0
SCACCudaSearch64:
.quad __device_stub__SCACCudaSearch64
.size SCACCudaSearch64, 8
.type SCACCudaSearch32,@object # @SCACCudaSearch32
.globl SCACCudaSearch32
.p2align 3, 0x0
SCACCudaSearch32:
.quad __device_stub__SCACCudaSearch32
.size SCACCudaSearch32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "SCACCudaSearch64"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "SCACCudaSearch32"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__SCACCudaSearch64
.addrsig_sym __device_stub__SCACCudaSearch32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym SCACCudaSearch64
.addrsig_sym SCACCudaSearch32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000da6d8_00000000-6_util-mpm-ac-cuda-kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_
.type _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_, @function
_Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq SCACCudaSearch64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_, .-_Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_
.globl SCACCudaSearch64
.type SCACCudaSearch64, @function
SCACCudaSearch64:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16SCACCudaSearch64PhjPjS0_jS_PhjPjS0_jS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size SCACCudaSearch64, .-SCACCudaSearch64
.globl _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_
.type _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_, @function
_Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq SCACCudaSearch32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_, .-_Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_
.globl SCACCudaSearch32
.type SCACCudaSearch32, @function
SCACCudaSearch32:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16SCACCudaSearch32PhjPjS0_jS_PhjPjS0_jS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size SCACCudaSearch32, .-SCACCudaSearch32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "SCACCudaSearch32"
.LC1:
.string "SCACCudaSearch64"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq SCACCudaSearch32(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq SCACCudaSearch64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "util-mpm-ac-cuda-kernel.hip"
.globl __device_stub__SCACCudaSearch64 # -- Begin function __device_stub__SCACCudaSearch64
.p2align 4, 0x90
.type __device_stub__SCACCudaSearch64,@function
__device_stub__SCACCudaSearch64: # @__device_stub__SCACCudaSearch64
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $SCACCudaSearch64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__SCACCudaSearch64, .Lfunc_end0-__device_stub__SCACCudaSearch64
.cfi_endproc
# -- End function
.globl __device_stub__SCACCudaSearch32 # -- Begin function __device_stub__SCACCudaSearch32
.p2align 4, 0x90
.type __device_stub__SCACCudaSearch32,@function
__device_stub__SCACCudaSearch32: # @__device_stub__SCACCudaSearch32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $SCACCudaSearch32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__SCACCudaSearch32, .Lfunc_end1-__device_stub__SCACCudaSearch32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $SCACCudaSearch64, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $SCACCudaSearch32, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type SCACCudaSearch64,@object # @SCACCudaSearch64
.section .rodata,"a",@progbits
.globl SCACCudaSearch64
.p2align 3, 0x0
SCACCudaSearch64:
.quad __device_stub__SCACCudaSearch64
.size SCACCudaSearch64, 8
.type SCACCudaSearch32,@object # @SCACCudaSearch32
.globl SCACCudaSearch32
.p2align 3, 0x0
SCACCudaSearch32:
.quad __device_stub__SCACCudaSearch32
.size SCACCudaSearch32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "SCACCudaSearch64"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "SCACCudaSearch32"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__SCACCudaSearch64
.addrsig_sym __device_stub__SCACCudaSearch32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym SCACCudaSearch64
.addrsig_sym SCACCudaSearch32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cstdlib>
#include <iostream>
__global__ void DivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
if (!(threadIdx.x % 2))
a[x] = a[x] * (threadIdx.x + 1);
else
a[x] = a[x] * (threadIdx.x % 5);
}
__global__ void NoDivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
a[x] = threadIdx.x;
}
int main(int argc, char** argv) {
if (argc == 2) {
int N = atoi(argv[1]);
size_t size = N * sizeof(float);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* h_A = (float*)malloc(size);
if (h_A == NULL) {
std::cerr << "Failed malloc for h_A!\n";
return 1;
}
for (int i = 0; i < N; i++) {
h_A[i] = i + 1;
}
float* d_A = NULL;
cudaMalloc((void**)&d_A, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
const int BLOCK_SIZE = 1024;
const int GRID_SIZE = (N - 1) / BLOCK_SIZE + 1;
cudaEventRecord(start);
DivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float msecs = 0;
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "(Divergency) Kernel Time: " << msecs << " ms.\n";
cudaEventRecord(start);
NoDivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "(Non-Divergency) Kernel Time: " << msecs << " ms.\n";
cudaFree(d_A);
free(h_A);
}
return 0;
} | code for sm_80
Function : _Z18NoDivergencyKernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R7 ; /* 0x0000000700057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0207 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16DivergencyKernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0080*/ LOP3.LUT R0, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107007812 */
/* 0x000fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00a0*/ @!P0 IMAD.WIDE.U32 R4, R7, -0x33333333, RZ ; /* 0xcccccccd07048825 */
/* 0x000fca00078e00ff */
/*00b0*/ @!P0 SHF.R.U32.HI R4, RZ, 0x2, R5 ; /* 0x00000002ff048819 */
/* 0x000fca0000011605 */
/*00c0*/ @!P0 IMAD R0, R4, -0x5, R7 ; /* 0xfffffffb04008824 */
/* 0x000fe200078e0207 */
/*00d0*/ @P0 IADD3 R0, R7, 0x1, RZ ; /* 0x0000000107000810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x000ea40000201000 */
/*00f0*/ FMUL R5, R6, R5 ; /* 0x0000000506057220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cstdlib>
#include <iostream>
__global__ void DivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
if (!(threadIdx.x % 2))
a[x] = a[x] * (threadIdx.x + 1);
else
a[x] = a[x] * (threadIdx.x % 5);
}
__global__ void NoDivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
a[x] = threadIdx.x;
}
int main(int argc, char** argv) {
if (argc == 2) {
int N = atoi(argv[1]);
size_t size = N * sizeof(float);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* h_A = (float*)malloc(size);
if (h_A == NULL) {
std::cerr << "Failed malloc for h_A!\n";
return 1;
}
for (int i = 0; i < N; i++) {
h_A[i] = i + 1;
}
float* d_A = NULL;
cudaMalloc((void**)&d_A, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
const int BLOCK_SIZE = 1024;
const int GRID_SIZE = (N - 1) / BLOCK_SIZE + 1;
cudaEventRecord(start);
DivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float msecs = 0;
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "(Divergency) Kernel Time: " << msecs << " ms.\n";
cudaEventRecord(start);
NoDivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "(Non-Divergency) Kernel Time: " << msecs << " ms.\n";
cudaFree(d_A);
free(h_A);
}
return 0;
} | .file "tmpxft_000795a8_00000000-6_main_conditions.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16DivergencyKernelPfiPfi
.type _Z37__device_stub__Z16DivergencyKernelPfiPfi, @function
_Z37__device_stub__Z16DivergencyKernelPfiPfi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16DivergencyKernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z16DivergencyKernelPfiPfi, .-_Z37__device_stub__Z16DivergencyKernelPfiPfi
.globl _Z16DivergencyKernelPfi
.type _Z16DivergencyKernelPfi, @function
_Z16DivergencyKernelPfi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16DivergencyKernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z16DivergencyKernelPfi, .-_Z16DivergencyKernelPfi
.globl _Z39__device_stub__Z18NoDivergencyKernelPfiPfi
.type _Z39__device_stub__Z18NoDivergencyKernelPfiPfi, @function
_Z39__device_stub__Z18NoDivergencyKernelPfiPfi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18NoDivergencyKernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z39__device_stub__Z18NoDivergencyKernelPfiPfi, .-_Z39__device_stub__Z18NoDivergencyKernelPfiPfi
.globl _Z18NoDivergencyKernelPfi
.type _Z18NoDivergencyKernelPfi, @function
_Z18NoDivergencyKernelPfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18NoDivergencyKernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z18NoDivergencyKernelPfi, .-_Z18NoDivergencyKernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed malloc for h_A!\n"
.LC2:
.string "(Divergency) Kernel Time: "
.LC3:
.string " ms.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "(Non-Divergency) Kernel Time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L31
.L19:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r12d
movslq %eax, %r13
salq $2, %r13
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L21
testl %ebx, %ebx
jle .L23
leal -1(%rbx), %eax
addq $2, %rax
movl $1, %edx
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, -4(%rbp,%rdx,4)
addq $1, %rdx
cmpq %rax, %rdx
jne .L24
.L23:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leal -1(%rbx), %eax
movl $1024, %ecx
cltd
idivl %ecx
leal 1(%rax), %ebx
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L26:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
jmp .L19
.L21:
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %eax
jmp .L19
.L33:
movl %r12d, %esi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z16DivergencyKernelPfiPfi
jmp .L25
.L34:
movl %r12d, %esi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z18NoDivergencyKernelPfiPfi
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z18NoDivergencyKernelPfi"
.LC6:
.string "_Z16DivergencyKernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z18NoDivergencyKernelPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16DivergencyKernelPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cstdlib>
#include <iostream>
__global__ void DivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
if (!(threadIdx.x % 2))
a[x] = a[x] * (threadIdx.x + 1);
else
a[x] = a[x] * (threadIdx.x % 5);
}
__global__ void NoDivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
a[x] = threadIdx.x;
}
int main(int argc, char** argv) {
if (argc == 2) {
int N = atoi(argv[1]);
size_t size = N * sizeof(float);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* h_A = (float*)malloc(size);
if (h_A == NULL) {
std::cerr << "Failed malloc for h_A!\n";
return 1;
}
for (int i = 0; i < N; i++) {
h_A[i] = i + 1;
}
float* d_A = NULL;
cudaMalloc((void**)&d_A, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
const int BLOCK_SIZE = 1024;
const int GRID_SIZE = (N - 1) / BLOCK_SIZE + 1;
cudaEventRecord(start);
DivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float msecs = 0;
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "(Divergency) Kernel Time: " << msecs << " ms.\n";
cudaEventRecord(start);
NoDivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "(Non-Divergency) Kernel Time: " << msecs << " ms.\n";
cudaFree(d_A);
free(h_A);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
__global__ void DivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
if (!(threadIdx.x % 2))
a[x] = a[x] * (threadIdx.x + 1);
else
a[x] = a[x] * (threadIdx.x % 5);
}
__global__ void NoDivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
a[x] = threadIdx.x;
}
int main(int argc, char** argv) {
if (argc == 2) {
int N = atoi(argv[1]);
size_t size = N * sizeof(float);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float* h_A = (float*)malloc(size);
if (h_A == NULL) {
std::cerr << "Failed malloc for h_A!\n";
return 1;
}
for (int i = 0; i < N; i++) {
h_A[i] = i + 1;
}
float* d_A = NULL;
hipMalloc((void**)&d_A, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
const int BLOCK_SIZE = 1024;
const int GRID_SIZE = (N - 1) / BLOCK_SIZE + 1;
hipEventRecord(start);
DivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
float msecs = 0;
hipEventElapsedTime(&msecs, start, stop);
std::cout << "(Divergency) Kernel Time: " << msecs << " ms.\n";
hipEventRecord(start);
NoDivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&msecs, start, stop);
std::cout << "(Non-Divergency) Kernel Time: " << msecs << " ms.\n";
hipFree(d_A);
free(h_A);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
__global__ void DivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
if (!(threadIdx.x % 2))
a[x] = a[x] * (threadIdx.x + 1);
else
a[x] = a[x] * (threadIdx.x % 5);
}
__global__ void NoDivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
a[x] = threadIdx.x;
}
int main(int argc, char** argv) {
if (argc == 2) {
int N = atoi(argv[1]);
size_t size = N * sizeof(float);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float* h_A = (float*)malloc(size);
if (h_A == NULL) {
std::cerr << "Failed malloc for h_A!\n";
return 1;
}
for (int i = 0; i < N; i++) {
h_A[i] = i + 1;
}
float* d_A = NULL;
hipMalloc((void**)&d_A, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
const int BLOCK_SIZE = 1024;
const int GRID_SIZE = (N - 1) / BLOCK_SIZE + 1;
hipEventRecord(start);
DivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
float msecs = 0;
hipEventElapsedTime(&msecs, start, stop);
std::cout << "(Divergency) Kernel Time: " << msecs << " ms.\n";
hipEventRecord(start);
NoDivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&msecs, start, stop);
std::cout << "(Non-Divergency) Kernel Time: " << msecs << " ms.\n";
hipFree(d_A);
free(h_A);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16DivergencyKernelPfi
.globl _Z16DivergencyKernelPfi
.p2align 8
.type _Z16DivergencyKernelPfi,@function
_Z16DivergencyKernelPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v4, 1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 1, v4
global_load_b32 v3, v[1:2], off
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s0, exec_lo, s0
v_mul_hi_u32 v4, v0, 0x33333334
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v4, 5, v4
v_sub_nc_u32_e32 v4, v0, v4
s_and_not1_saveexec_b32 s0, s0
v_or_b32_e32 v4, 1, v0
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v3, v0
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16DivergencyKernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16DivergencyKernelPfi, .Lfunc_end0-_Z16DivergencyKernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18NoDivergencyKernelPfi
.globl _Z18NoDivergencyKernelPfi
.p2align 8
.type _Z18NoDivergencyKernelPfi,@function
_Z18NoDivergencyKernelPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18NoDivergencyKernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18NoDivergencyKernelPfi, .Lfunc_end1-_Z18NoDivergencyKernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16DivergencyKernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16DivergencyKernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18NoDivergencyKernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18NoDivergencyKernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
__global__ void DivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
if (!(threadIdx.x % 2))
a[x] = a[x] * (threadIdx.x + 1);
else
a[x] = a[x] * (threadIdx.x % 5);
}
__global__ void NoDivergencyKernel(float* a, int N) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
a[x] = threadIdx.x;
}
int main(int argc, char** argv) {
if (argc == 2) {
int N = atoi(argv[1]);
size_t size = N * sizeof(float);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float* h_A = (float*)malloc(size);
if (h_A == NULL) {
std::cerr << "Failed malloc for h_A!\n";
return 1;
}
for (int i = 0; i < N; i++) {
h_A[i] = i + 1;
}
float* d_A = NULL;
hipMalloc((void**)&d_A, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
const int BLOCK_SIZE = 1024;
const int GRID_SIZE = (N - 1) / BLOCK_SIZE + 1;
hipEventRecord(start);
DivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
float msecs = 0;
hipEventElapsedTime(&msecs, start, stop);
std::cout << "(Divergency) Kernel Time: " << msecs << " ms.\n";
hipEventRecord(start);
NoDivergencyKernel<<<BLOCK_SIZE, GRID_SIZE>>>(d_A, N);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&msecs, start, stop);
std::cout << "(Non-Divergency) Kernel Time: " << msecs << " ms.\n";
hipFree(d_A);
free(h_A);
}
return 0;
} | .text
.file "main_conditions.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__DivergencyKernelPfi # -- Begin function _Z31__device_stub__DivergencyKernelPfi
.p2align 4, 0x90
.type _Z31__device_stub__DivergencyKernelPfi,@function
_Z31__device_stub__DivergencyKernelPfi: # @_Z31__device_stub__DivergencyKernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16DivergencyKernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__DivergencyKernelPfi, .Lfunc_end0-_Z31__device_stub__DivergencyKernelPfi
.cfi_endproc
# -- End function
.globl _Z33__device_stub__NoDivergencyKernelPfi # -- Begin function _Z33__device_stub__NoDivergencyKernelPfi
.p2align 4, 0x90
.type _Z33__device_stub__NoDivergencyKernelPfi,@function
_Z33__device_stub__NoDivergencyKernelPfi: # @_Z33__device_stub__NoDivergencyKernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18NoDivergencyKernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z33__device_stub__NoDivergencyKernelPfi, .Lfunc_end1-_Z33__device_stub__NoDivergencyKernelPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB2_11
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r14d, %r15
shlq $2, %r15
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %r15, %rdi
callq malloc
movq %rax, %rbx
testq %rax, %rax
je .LBB2_13
# %bb.2: # %.preheader
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB2_4
.LBB2_5: # %._crit_edge
movabsq $4294968320, %r12 # imm = 0x100000400
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%r14), %eax
leal 1022(%r14), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $10, %r15d
incl %r15d
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq (%r15,%r12), %r13
addq $-1024, %r13 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16DivergencyKernelPfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18NoDivergencyKernelPfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
testq %rbx, %rbx
je .LBB2_12
.LBB2_11:
xorl %r15d, %r15d
.LBB2_12:
movl %r15d, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 160
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $1, %r15d
testq %rbx, %rbx
jne .LBB2_11
jmp .LBB2_12
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16DivergencyKernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18NoDivergencyKernelPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16DivergencyKernelPfi,@object # @_Z16DivergencyKernelPfi
.section .rodata,"a",@progbits
.globl _Z16DivergencyKernelPfi
.p2align 3, 0x0
_Z16DivergencyKernelPfi:
.quad _Z31__device_stub__DivergencyKernelPfi
.size _Z16DivergencyKernelPfi, 8
.type _Z18NoDivergencyKernelPfi,@object # @_Z18NoDivergencyKernelPfi
.globl _Z18NoDivergencyKernelPfi
.p2align 3, 0x0
_Z18NoDivergencyKernelPfi:
.quad _Z33__device_stub__NoDivergencyKernelPfi
.size _Z18NoDivergencyKernelPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed malloc for h_A!\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "(Divergency) Kernel Time: "
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ms.\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "(Non-Divergency) Kernel Time: "
.size .L.str.3, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16DivergencyKernelPfi"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18NoDivergencyKernelPfi"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__DivergencyKernelPfi
.addrsig_sym _Z33__device_stub__NoDivergencyKernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16DivergencyKernelPfi
.addrsig_sym _Z18NoDivergencyKernelPfi
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18NoDivergencyKernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R7 ; /* 0x0000000700057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0207 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16DivergencyKernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0080*/ LOP3.LUT R0, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107007812 */
/* 0x000fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00a0*/ @!P0 IMAD.WIDE.U32 R4, R7, -0x33333333, RZ ; /* 0xcccccccd07048825 */
/* 0x000fca00078e00ff */
/*00b0*/ @!P0 SHF.R.U32.HI R4, RZ, 0x2, R5 ; /* 0x00000002ff048819 */
/* 0x000fca0000011605 */
/*00c0*/ @!P0 IMAD R0, R4, -0x5, R7 ; /* 0xfffffffb04008824 */
/* 0x000fe200078e0207 */
/*00d0*/ @P0 IADD3 R0, R7, 0x1, RZ ; /* 0x0000000107000810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x000ea40000201000 */
/*00f0*/ FMUL R5, R6, R5 ; /* 0x0000000506057220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16DivergencyKernelPfi
.globl _Z16DivergencyKernelPfi
.p2align 8
.type _Z16DivergencyKernelPfi,@function
_Z16DivergencyKernelPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v4, 1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 1, v4
global_load_b32 v3, v[1:2], off
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s0, exec_lo, s0
v_mul_hi_u32 v4, v0, 0x33333334
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v4, 5, v4
v_sub_nc_u32_e32 v4, v0, v4
s_and_not1_saveexec_b32 s0, s0
v_or_b32_e32 v4, 1, v0
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v3, v0
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16DivergencyKernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16DivergencyKernelPfi, .Lfunc_end0-_Z16DivergencyKernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18NoDivergencyKernelPfi
.globl _Z18NoDivergencyKernelPfi
.p2align 8
.type _Z18NoDivergencyKernelPfi,@function
_Z18NoDivergencyKernelPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18NoDivergencyKernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18NoDivergencyKernelPfi, .Lfunc_end1-_Z18NoDivergencyKernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16DivergencyKernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16DivergencyKernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18NoDivergencyKernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18NoDivergencyKernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000795a8_00000000-6_main_conditions.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16DivergencyKernelPfiPfi
.type _Z37__device_stub__Z16DivergencyKernelPfiPfi, @function
_Z37__device_stub__Z16DivergencyKernelPfiPfi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16DivergencyKernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z16DivergencyKernelPfiPfi, .-_Z37__device_stub__Z16DivergencyKernelPfiPfi
.globl _Z16DivergencyKernelPfi
.type _Z16DivergencyKernelPfi, @function
_Z16DivergencyKernelPfi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16DivergencyKernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z16DivergencyKernelPfi, .-_Z16DivergencyKernelPfi
.globl _Z39__device_stub__Z18NoDivergencyKernelPfiPfi
.type _Z39__device_stub__Z18NoDivergencyKernelPfiPfi, @function
_Z39__device_stub__Z18NoDivergencyKernelPfiPfi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18NoDivergencyKernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z39__device_stub__Z18NoDivergencyKernelPfiPfi, .-_Z39__device_stub__Z18NoDivergencyKernelPfiPfi
.globl _Z18NoDivergencyKernelPfi
.type _Z18NoDivergencyKernelPfi, @function
_Z18NoDivergencyKernelPfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18NoDivergencyKernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z18NoDivergencyKernelPfi, .-_Z18NoDivergencyKernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed malloc for h_A!\n"
.LC2:
.string "(Divergency) Kernel Time: "
.LC3:
.string " ms.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "(Non-Divergency) Kernel Time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L31
.L19:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r12d
movslq %eax, %r13
salq $2, %r13
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L21
testl %ebx, %ebx
jle .L23
leal -1(%rbx), %eax
addq $2, %rax
movl $1, %edx
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, -4(%rbp,%rdx,4)
addq $1, %rdx
cmpq %rax, %rdx
jne .L24
.L23:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leal -1(%rbx), %eax
movl $1024, %ecx
cltd
idivl %ecx
leal 1(%rax), %ebx
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L26:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
jmp .L19
.L21:
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %eax
jmp .L19
.L33:
movl %r12d, %esi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z16DivergencyKernelPfiPfi
jmp .L25
.L34:
movl %r12d, %esi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z18NoDivergencyKernelPfiPfi
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z18NoDivergencyKernelPfi"
.LC6:
.string "_Z16DivergencyKernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z18NoDivergencyKernelPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16DivergencyKernelPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main_conditions.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__DivergencyKernelPfi # -- Begin function _Z31__device_stub__DivergencyKernelPfi
.p2align 4, 0x90
.type _Z31__device_stub__DivergencyKernelPfi,@function
_Z31__device_stub__DivergencyKernelPfi: # @_Z31__device_stub__DivergencyKernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16DivergencyKernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__DivergencyKernelPfi, .Lfunc_end0-_Z31__device_stub__DivergencyKernelPfi
.cfi_endproc
# -- End function
.globl _Z33__device_stub__NoDivergencyKernelPfi # -- Begin function _Z33__device_stub__NoDivergencyKernelPfi
.p2align 4, 0x90
.type _Z33__device_stub__NoDivergencyKernelPfi,@function
_Z33__device_stub__NoDivergencyKernelPfi: # @_Z33__device_stub__NoDivergencyKernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18NoDivergencyKernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z33__device_stub__NoDivergencyKernelPfi, .Lfunc_end1-_Z33__device_stub__NoDivergencyKernelPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB2_11
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r14d, %r15
shlq $2, %r15
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %r15, %rdi
callq malloc
movq %rax, %rbx
testq %rax, %rax
je .LBB2_13
# %bb.2: # %.preheader
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB2_4
.LBB2_5: # %._crit_edge
movabsq $4294968320, %r12 # imm = 0x100000400
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%r14), %eax
leal 1022(%r14), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $10, %r15d
incl %r15d
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq (%r15,%r12), %r13
addq $-1024, %r13 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16DivergencyKernelPfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18NoDivergencyKernelPfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
testq %rbx, %rbx
je .LBB2_12
.LBB2_11:
xorl %r15d, %r15d
.LBB2_12:
movl %r15d, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 160
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $1, %r15d
testq %rbx, %rbx
jne .LBB2_11
jmp .LBB2_12
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16DivergencyKernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18NoDivergencyKernelPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16DivergencyKernelPfi,@object # @_Z16DivergencyKernelPfi
.section .rodata,"a",@progbits
.globl _Z16DivergencyKernelPfi
.p2align 3, 0x0
_Z16DivergencyKernelPfi:
.quad _Z31__device_stub__DivergencyKernelPfi
.size _Z16DivergencyKernelPfi, 8
.type _Z18NoDivergencyKernelPfi,@object # @_Z18NoDivergencyKernelPfi
.globl _Z18NoDivergencyKernelPfi
.p2align 3, 0x0
_Z18NoDivergencyKernelPfi:
.quad _Z33__device_stub__NoDivergencyKernelPfi
.size _Z18NoDivergencyKernelPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed malloc for h_A!\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "(Divergency) Kernel Time: "
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ms.\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "(Non-Divergency) Kernel Time: "
.size .L.str.3, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16DivergencyKernelPfi"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18NoDivergencyKernelPfi"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__DivergencyKernelPfi
.addrsig_sym _Z33__device_stub__NoDivergencyKernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16DivergencyKernelPfi
.addrsig_sym _Z18NoDivergencyKernelPfi
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //optimization homework #4 cs 677 Theodore Jagodits
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>
#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
//add constant memory
__constant__ float c_inp[MAX_CONST];
//tiling complete
__global__ void unknown_algo_inp2(float *inp2, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp = 0.0f;
unsigned int curr = 0, pos_x;
for(unsigned int count = 0; count < num_tiles; count++){
//find position
pos_x = count * TILE_SIZE + threadIdx.x;
//check bounds and load tile
if(pos_x < col && tx < row){
temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= tx){
temp += temp_shared_2[threadIdx.x * TILE_SIZE + tile];
}
curr ++;
}
}
if(ty < row && tx < col){
result[ty*row + tx] = 30;
}
}
__global__ void unknown_algo_inp1(float *inp1, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_1[TILE_SIZE][TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp, local;
unsigned int curr = 0, pos_y;
//preload local
if(tx < row && ty < row){
temp = 0.0f;
local = inp1[row*tx + ty];
}
for(unsigned int count = 0; count < num_tiles; count++){
pos_y = count * TILE_SIZE + threadIdx.y;
//decrease load by letting one thread do it
if(pos_y < col && tx < row){
temp_shared_1[threadIdx.x][threadIdx.y] = inp1[pos_y];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= ty){
temp += temp_shared_1[threadIdx.x][tile] * local;
}
curr++;
}
}
if(tx < row && ty < col){
result[tx*row + ty] = temp;
}
}
void cpu_v(float *inp1, float *inp2, float *result, int row, int col, float *temp){
for(int i = 0 ; i < row; i++){
temp[i] = 0.0f;
for(int j = 0; j < col; j++){
temp[i] += inp2[i*row + j];
result[i*row + j] = temp[i];
for(int k = 0; k < col; k++){
result[i*row + j] += inp1[j] * inp1[k];
}
}
}
}
int compare_res(float *d_res, float *h_res, int row, int col){
int check = 0;
for(int i = 0; i < row; i++){
for(int j = 0; j < col; j++){
if(d_res[i*row + j] != h_res[i*row +j]){
check += 1;
}
}
}
return check;
}
int main( int argc, char **argv ){
int row = DEFAULT_ROW;
int col = DEFAULT_COL;
if(argc == 3){
row = atoi(argv[1]);
col = atoi(argv[2]);
}
//create vars
int input1_bytes = col * sizeof(float);
int num_bytes = row * col * sizeof(float);
//event timers
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
clock_t start_cpu, end_cpu;
//malloc device
float *d_input1 = (float *) malloc(input1_bytes);
float *d_input2 = (float *) malloc(num_bytes);
float *d_result = (float *) malloc(num_bytes);
//malloc host
float *h_input1 = (float *) malloc(input1_bytes);
float *h_input2 = (float *) malloc(num_bytes);
float *h_result = (float *) malloc(num_bytes);
//malloc test
float *temp = (float *) malloc(row* sizeof(float));
float *cpu_res = (float *) malloc(num_bytes);
//cuda malloc
cudaMalloc(&d_input1, input1_bytes);
cudaMalloc(&d_input2, num_bytes);
cudaMalloc(&d_result, num_bytes);
//put in data
for(int o = 0; o < row; o++){
for(int p = 0; p < col; p++){
h_input2[row * o + p] = 1.0f;
}
}
for(int i = 0; i < col; i++){
h_input1[i] = 1.0f;
}
//copy over memory
cudaMemcpy(d_input1, h_input1, input1_bytes, cudaMemcpyHostToDevice);
//cudaMemcpy(d_input2, h_input2, num_bytes, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_inp, h_input2, num_bytes);
//declare block and grid size for kernel
int block_size = TILE_SIZE;
//make grids x y
int grid_x = (int)ceil((float)row/block_size);
int grid_y = (int)ceil((float)col/block_size);
dim3 dim_grid (grid_x, grid_y);
dim3 dim_block (block_size, block_size);
//start timer
cudaEventRecord(start);
//run kernel on inp2
unknown_algo_inp2<<< dim_grid, dim_block >>> (d_input2, d_result, row, col, grid_x);
//inp1
//unknown_algo_inp1<<< dim_grid, dim_block >>> (d_input1, d_result, row, col, grid_x);
//end timer
cudaEventRecord(stop);
// Copy result back to host
cudaMemcpy(h_result, d_result, num_bytes, cudaMemcpyDeviceToHost);
//synchronize https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
//cpu version
start_cpu = clock();
cpu_v(h_input1, h_input2, cpu_res, row, col, temp);
end_cpu = clock();
int error_count = compare_res(h_result, cpu_res, row, col);
printf("error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n", error_count, milliseconds, ((float)((end_cpu-start_cpu)*1000))/CLOCKS_PER_SEC);
printf("gridx: %d gridy: %d\n", grid_x, grid_y);
//print error check
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)h_result[i*row + j]);
}
printf("\n");
}
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)cpu_res[i*row + j]);
}
printf("\n");
}
//free all vars
free(h_input1);
free(h_input2);
free(h_result);
free(temp);
cudaFree(d_input1);
cudaFree(d_input2);
cudaFree(d_result);
return 0;
} | code for sm_80
Function : _Z17unknown_algo_inp1PfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x140 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc60003f65270 */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R3, R3, c[0x0][0x0], R8 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0208 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R4, R5, c[0x0][0x4], R2 ; /* 0x0000010005047a24 */
/* 0x002fca00078e0202 */
/*00c0*/ ISETP.GE.OR P2, PT, R4.reuse, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x040fe40000746670 */
/*00d0*/ ISETP.GE.OR P1, PT, R4, c[0x0][0x174], P0 ; /* 0x00005d0004007a0c */
/* 0x000fd60000726670 */
/*00e0*/ @P2 BRA 0x130 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R6, R3, c[0x0][0x170], R4 ; /* 0x00005c0003067a24 */
/* 0x000fc800078e0204 */
/*0110*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0207 */
/*0120*/ LDG.E R5, [R6.64] ; /* 0x0000000806057981 */
/* 0x000164000c1e1900 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ @!P3 BRA 0x640 ; /* 0x000004f00000b947 */
/* 0x000fea0003800000 */
/*0150*/ SHF.L.U32 R9, R8, 0x6, RZ ; /* 0x0000000608097819 */
/* 0x000fe200000006ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0170*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0190*/ IMAD R11, R2, 0x4, R9 ; /* 0x00000004020b7824 */
/* 0x000fe400078e0209 */
/*01a0*/ ISETP.GE.U32.OR P2, PT, R2, c[0x0][0x174], P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000746470 */
/*01b0*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x001fca0000000f00 */
/*01c0*/ @!P2 IMAD.WIDE.U32 R6, R2, R7, c[0x0][0x160] ; /* 0x000058000206a625 */
/* 0x000fcc00078e0007 */
/*01d0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000080606a981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ ISETP.LT.U32.AND P6, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe2000bfc1070 */
/*01f0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0200*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0210*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007ffe0ff */
/*0230*/ ISETP.LT.U32.AND P5, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfa1070 */
/*0240*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fcc000fffe03f */
/*0250*/ ISETP.LT.U32.AND P4, PT, R4.reuse, UR5, PT ; /* 0x0000000504007c0c */
/* 0x040fe2000bf81070 */
/*0260*/ UIADD3 UR5, UR4, 0x5, URZ ; /* 0x0000000504057890 */
/* 0x000fe2000fffe03f */
/*0270*/ @!P2 STS [R11], R6 ; /* 0x000000060b00a388 */
/* 0x004fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.LT.U32.AND P2, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x000fe2000bf41070 */
/*02a0*/ UIADD3 UR6, UR4, 0x4, URZ ; /* 0x0000000404067890 */
/* 0x000fcc000fffe03f */
/*02b0*/ ISETP.LT.U32.AND P3, PT, R4.reuse, UR6, PT ; /* 0x0000000604007c0c */
/* 0x040fe2000bf61070 */
/*02c0*/ UIADD3 UR6, UR4, 0x7, URZ ; /* 0x0000000704067890 */
/* 0x000fe2000fffe03f */
/*02d0*/ @!P6 LDS R10, [R9] ; /* 0x00000000090ae984 */
/* 0x000e280000000800 */
/*02e0*/ @!P5 LDS R7, [R9+0x4] ; /* 0x000004000907d984 */
/* 0x000e680000000800 */
/*02f0*/ @!P4 LDS R12, [R9+0xc] ; /* 0x00000c00090cc984 */
/* 0x000fe80000000800 */
/*0300*/ @!P3 LDS R6, [R9+0x10] ; /* 0x000010000906b984 */
/* 0x000fe20000000800 */
/*0310*/ @!P6 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500e223 */
/* 0x021fe20000000000 */
/*0320*/ ISETP.LT.U32.AND P6, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fc4000bfc1070 */
/*0330*/ @!P2 LDS R10, [R9+0x8] ; /* 0x00000800090aa984 */
/* 0x000e220000000800 */
/*0340*/ UIADD3 UR5, UR4, 0x6, URZ ; /* 0x0000000604057890 */
/* 0x000fe2000fffe03f */
/*0350*/ @!P5 FFMA R0, R5, R7, R0 ; /* 0x000000070500d223 */
/* 0x002fca0000000000 */
/*0360*/ ISETP.LT.U32.AND P5, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfa1070 */
/*0370*/ UIADD3 UR5, UR4, 0x8, URZ ; /* 0x0000000804057890 */
/* 0x000fc6000fffe03f */
/*0380*/ @!P6 LDS R13, [R9+0x14] ; /* 0x00001400090de984 */
/* 0x000e720000000800 */
/*0390*/ @!P5 LDS R7, [R9+0x18] ; /* 0x000018000907d984 */
/* 0x000ea20000000800 */
/*03a0*/ @!P2 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500a223 */
/* 0x001fe20000000000 */
/*03b0*/ ISETP.LT.U32.AND P2, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x000fe2000bf41070 */
/*03c0*/ UIADD3 UR6, UR4, 0x9, URZ ; /* 0x0000000904067890 */
/* 0x000fc4000fffe03f */
/*03d0*/ @!P4 FFMA R0, R5.reuse, R12, R0 ; /* 0x0000000c0500c223 */
/* 0x040fe20000000000 */
/*03e0*/ ISETP.LT.U32.AND P4, PT, R4.reuse, UR5, PT ; /* 0x0000000504007c0c */
/* 0x040fe2000bf81070 */
/*03f0*/ UIADD3 UR5, UR4, 0xa, URZ ; /* 0x0000000a04057890 */
/* 0x000fe4000fffe03f */
/*0400*/ @!P3 FFMA R0, R5.reuse, R6, R0 ; /* 0x000000060500b223 */
/* 0x040fe20000000000 */
/*0410*/ ISETP.LT.U32.AND P3, PT, R4.reuse, UR6, PT ; /* 0x0000000604007c0c */
/* 0x040fe2000bf61070 */
/*0420*/ UIADD3 UR6, UR4, 0xc, URZ ; /* 0x0000000c04067890 */
/* 0x000fe4000fffe03f */
/*0430*/ @!P6 FFMA R0, R5, R13, R0 ; /* 0x0000000d0500e223 */
/* 0x002fe20000000000 */
/*0440*/ ISETP.LT.U32.AND P6, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfc1070 */
/*0450*/ @!P2 LDS R10, [R9+0x1c] ; /* 0x00001c00090aa984 */
/* 0x000e220000000800 */
/*0460*/ UIADD3 UR5, UR4, 0xb, URZ ; /* 0x0000000b04057890 */
/* 0x000fc6000fffe03f */
/*0470*/ @!P4 LDS R6, [R9+0x20] ; /* 0x000020000906c984 */
/* 0x000e620000000800 */
/*0480*/ @!P5 FFMA R0, R5, R7, R0 ; /* 0x000000070500d223 */
/* 0x004fe40000000000 */
/*0490*/ ISETP.LT.U32.AND P5, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfa1070 */
/*04a0*/ @!P3 LDS R12, [R9+0x24] ; /* 0x00002400090cb984 */
/* 0x000ea20000000800 */
/*04b0*/ UIADD3 UR5, UR4, 0xd, URZ ; /* 0x0000000d04057890 */
/* 0x000fc6000fffe03f */
/*04c0*/ @!P6 LDS R13, [R9+0x28] ; /* 0x00002800090de984 */
/* 0x000ef00000000800 */
/*04d0*/ @!P5 LDS R7, [R9+0x2c] ; /* 0x00002c000907d984 */
/* 0x000f220000000800 */
/*04e0*/ @!P2 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500a223 */
/* 0x001fe20000000000 */
/*04f0*/ ISETP.LT.U32.AND P2, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x000fe2000bf41070 */
/*0500*/ UIADD3 UR6, UR4, 0xe, URZ ; /* 0x0000000e04067890 */
/* 0x000fc4000fffe03f */
/*0510*/ @!P4 FFMA R0, R5.reuse, R6, R0 ; /* 0x000000060500c223 */
/* 0x042fe20000000000 */
/*0520*/ ISETP.LT.U32.AND P4, PT, R4.reuse, UR5, PT ; /* 0x0000000504007c0c */
/* 0x040fe2000bf81070 */
/*0530*/ UIADD3 UR5, UR4, 0xf, URZ ; /* 0x0000000f04057890 */
/* 0x000fe4000fffe03f */
/*0540*/ @!P3 FFMA R0, R5.reuse, R12, R0 ; /* 0x0000000c0500b223 */
/* 0x044fe20000000000 */
/*0550*/ ISETP.LT.U32.AND P3, PT, R4.reuse, UR6, PT ; /* 0x0000000604007c0c */
/* 0x040fe2000bf61070 */
/*0560*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0570*/ @!P6 FFMA R0, R5.reuse, R13, R0 ; /* 0x0000000d0500e223 */
/* 0x048fe20000000000 */
/*0580*/ ISETP.LT.U32.AND P6, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfc1070 */
/*0590*/ @!P2 LDS R6, [R9+0x30] ; /* 0x000030000906a984 */
/* 0x000e280000000800 */
/*05a0*/ @!P4 LDS R10, [R9+0x34] ; /* 0x00003400090ac984 */
/* 0x000e620000000800 */
/*05b0*/ @!P5 FFMA R0, R5, R7, R0 ; /* 0x000000070500d223 */
/* 0x010fc60000000000 */
/*05c0*/ @!P3 LDS R12, [R9+0x38] ; /* 0x00003800090cb984 */
/* 0x000ea80000000800 */
/*05d0*/ @!P6 LDS R13, [R9+0x3c] ; /* 0x00003c00090de984 */
/* 0x000ee20000000800 */
/*05e0*/ @!P2 FFMA R0, R5, R6, R0 ; /* 0x000000060500a223 */
/* 0x001fe20000000000 */
/*05f0*/ ISETP.GE.U32.AND P2, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fc60003f46070 */
/*0600*/ @!P4 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500c223 */
/* 0x002fc80000000000 */
/*0610*/ @!P3 FFMA R0, R5, R12, R0 ; /* 0x0000000c0500b223 */
/* 0x004fc80000000000 */
/*0620*/ @!P6 FFMA R0, R5, R13, R0 ; /* 0x0000000d0500e223 */
/* 0x008fe40000000000 */
/*0630*/ @!P2 BRA 0x1a0 ; /* 0xfffffb600000a947 */
/* 0x000fea000383ffff */
/*0640*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD R3, R3, c[0x0][0x170], R4 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0204 */
/*0670*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0680*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101908 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17unknown_algo_inp2PfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc60003f25270 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0050*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R4 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0204 */
/*0090*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20000706670 */
/*00a0*/ @!P1 BRA 0x1a0 ; /* 0x000000f000009947 */
/* 0x000fd80003800000 */
/*00b0*/ IMAD R4, R4, 0x10, R2.reuse ; /* 0x0000001004047824 */
/* 0x100fe200078e0202 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R5, R3, c[0x0][0x170], R2 ; /* 0x00005c0003057a24 */
/* 0x000fe400078e0202 */
/*00e0*/ IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404077824 */
/* 0x000fca00078e00ff */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe40003f26070 */
/*0100*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x170], P1 ; /* 0x00005c0000007a0c */
/* 0x000fe40000f26670 */
/*0120*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fd60007ffe0ff */
/*0130*/ @!P1 SHF.L.U32 R4, R5.reuse, 0x2, RZ ; /* 0x0000000205049819 */
/* 0x040fe400000006ff */
/*0140*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fc80007ffe0ff */
/*0150*/ @!P1 LDC R4, c[0x3][R4] ; /* 0x00c0000004049b82 */
/* 0x000e240000000800 */
/*0160*/ @!P1 STS [R7], R4 ; /* 0x0000000407009388 */
/* 0x0011e80000000800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f26070 */
/*0190*/ @!P1 BRA 0xf0 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R5, 0x41f00000 ; /* 0x41f0000000057802 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //optimization homework #4 cs 677 Theodore Jagodits
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>
#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
//add constant memory
__constant__ float c_inp[MAX_CONST];
//tiling complete
__global__ void unknown_algo_inp2(float *inp2, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp = 0.0f;
unsigned int curr = 0, pos_x;
for(unsigned int count = 0; count < num_tiles; count++){
//find position
pos_x = count * TILE_SIZE + threadIdx.x;
//check bounds and load tile
if(pos_x < col && tx < row){
temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= tx){
temp += temp_shared_2[threadIdx.x * TILE_SIZE + tile];
}
curr ++;
}
}
if(ty < row && tx < col){
result[ty*row + tx] = 30;
}
}
__global__ void unknown_algo_inp1(float *inp1, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_1[TILE_SIZE][TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp, local;
unsigned int curr = 0, pos_y;
//preload local
if(tx < row && ty < row){
temp = 0.0f;
local = inp1[row*tx + ty];
}
for(unsigned int count = 0; count < num_tiles; count++){
pos_y = count * TILE_SIZE + threadIdx.y;
//decrease load by letting one thread do it
if(pos_y < col && tx < row){
temp_shared_1[threadIdx.x][threadIdx.y] = inp1[pos_y];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= ty){
temp += temp_shared_1[threadIdx.x][tile] * local;
}
curr++;
}
}
if(tx < row && ty < col){
result[tx*row + ty] = temp;
}
}
void cpu_v(float *inp1, float *inp2, float *result, int row, int col, float *temp){
for(int i = 0 ; i < row; i++){
temp[i] = 0.0f;
for(int j = 0; j < col; j++){
temp[i] += inp2[i*row + j];
result[i*row + j] = temp[i];
for(int k = 0; k < col; k++){
result[i*row + j] += inp1[j] * inp1[k];
}
}
}
}
int compare_res(float *d_res, float *h_res, int row, int col){
int check = 0;
for(int i = 0; i < row; i++){
for(int j = 0; j < col; j++){
if(d_res[i*row + j] != h_res[i*row +j]){
check += 1;
}
}
}
return check;
}
int main( int argc, char **argv ){
int row = DEFAULT_ROW;
int col = DEFAULT_COL;
if(argc == 3){
row = atoi(argv[1]);
col = atoi(argv[2]);
}
//create vars
int input1_bytes = col * sizeof(float);
int num_bytes = row * col * sizeof(float);
//event timers
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
clock_t start_cpu, end_cpu;
//malloc device
float *d_input1 = (float *) malloc(input1_bytes);
float *d_input2 = (float *) malloc(num_bytes);
float *d_result = (float *) malloc(num_bytes);
//malloc host
float *h_input1 = (float *) malloc(input1_bytes);
float *h_input2 = (float *) malloc(num_bytes);
float *h_result = (float *) malloc(num_bytes);
//malloc test
float *temp = (float *) malloc(row* sizeof(float));
float *cpu_res = (float *) malloc(num_bytes);
//cuda malloc
cudaMalloc(&d_input1, input1_bytes);
cudaMalloc(&d_input2, num_bytes);
cudaMalloc(&d_result, num_bytes);
//put in data
for(int o = 0; o < row; o++){
for(int p = 0; p < col; p++){
h_input2[row * o + p] = 1.0f;
}
}
for(int i = 0; i < col; i++){
h_input1[i] = 1.0f;
}
//copy over memory
cudaMemcpy(d_input1, h_input1, input1_bytes, cudaMemcpyHostToDevice);
//cudaMemcpy(d_input2, h_input2, num_bytes, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_inp, h_input2, num_bytes);
//declare block and grid size for kernel
int block_size = TILE_SIZE;
//make grids x y
int grid_x = (int)ceil((float)row/block_size);
int grid_y = (int)ceil((float)col/block_size);
dim3 dim_grid (grid_x, grid_y);
dim3 dim_block (block_size, block_size);
//start timer
cudaEventRecord(start);
//run kernel on inp2
unknown_algo_inp2<<< dim_grid, dim_block >>> (d_input2, d_result, row, col, grid_x);
//inp1
//unknown_algo_inp1<<< dim_grid, dim_block >>> (d_input1, d_result, row, col, grid_x);
//end timer
cudaEventRecord(stop);
// Copy result back to host
cudaMemcpy(h_result, d_result, num_bytes, cudaMemcpyDeviceToHost);
//synchronize https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
//cpu version
start_cpu = clock();
cpu_v(h_input1, h_input2, cpu_res, row, col, temp);
end_cpu = clock();
int error_count = compare_res(h_result, cpu_res, row, col);
printf("error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n", error_count, milliseconds, ((float)((end_cpu-start_cpu)*1000))/CLOCKS_PER_SEC);
printf("gridx: %d gridy: %d\n", grid_x, grid_y);
//print error check
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)h_result[i*row + j]);
}
printf("\n");
}
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)cpu_res[i*row + j]);
}
printf("\n");
}
//free all vars
free(h_input1);
free(h_input2);
free(h_result);
free(temp);
cudaFree(d_input1);
cudaFree(d_input2);
cudaFree(d_result);
return 0;
} | .file "tmpxft_00091176_00000000-6_v5_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5cpu_vPfS_S_iiS_
.type _Z5cpu_vPfS_S_iiS_, @function
_Z5cpu_vPfS_S_iiS_:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L13
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r10
movq %rsi, %rbx
movq %rdx, %rbp
movl %ecx, %r12d
movl %r8d, %r13d
movslq %ecx, %rcx
leaq (%r9,%rcx,4), %r14
movslq %r8d, %rax
leaq (%rdi,%rax,4), %rsi
movl $0, %r11d
movq %r9, %rcx
.L8:
movq %rcx, %rdx
movl $0x00000000, (%rcx)
testl %r13d, %r13d
jle .L5
movslq %r11d, %r8
salq $2, %r8
leaq (%rbx,%r8), %r9
addq %rbp, %r8
movq %r10, %rdi
.L7:
movss (%rdx), %xmm0
addss (%r9), %xmm0
movss %xmm0, (%rdx)
movq %r8, %r15
movss %xmm0, (%r8)
movq %r10, %rax
.L6:
movss (%rdi), %xmm0
mulss (%rax), %xmm0
addss (%r15), %xmm0
movss %xmm0, (%r15)
addq $4, %rax
cmpq %rsi, %rax
jne .L6
addq $4, %r9
addq $4, %r8
addq $4, %rdi
cmpq %rsi, %rdi
jne .L7
.L5:
addq $4, %rcx
addl %r12d, %r11d
cmpq %r14, %rcx
jne .L8
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3669:
.size _Z5cpu_vPfS_S_iiS_, .-_Z5cpu_vPfS_S_iiS_
.globl _Z11compare_resPfS_ii
.type _Z11compare_resPfS_ii, @function
_Z11compare_resPfS_ii:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L24
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $0, %r11d
movl $0, %r10d
movl $0, %r9d
movslq %ecx, %rbx
jmp .L18
.L25:
addl $1, %r9d
.L19:
addq $4, %rax
cmpq %r8, %rax
je .L23
.L21:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L25
je .L19
jmp .L25
.L23:
addl $1, %r10d
addl %edx, %r11d
cmpl %r10d, %edx
je .L16
.L18:
testl %ecx, %ecx
jle .L23
movslq %r11d, %r8
leaq 0(,%r8,4), %rax
addq %rbx, %r8
salq $2, %r8
jmp .L21
.L24:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %r9d
movl %r9d, %eax
ret
.L16:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %r9d, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11compare_resPfS_ii, .-_Z11compare_resPfS_ii
.globl _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
.type _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii, @function
_Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17unknown_algo_inp2PfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii, .-_Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
.globl _Z17unknown_algo_inp2PfS_iii
.type _Z17unknown_algo_inp2PfS_iii, @function
_Z17unknown_algo_inp2PfS_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z17unknown_algo_inp2PfS_iii, .-_Z17unknown_algo_inp2PfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "gridx: %d gridy: %d\n"
.LC8:
.string "%d. "
.LC9:
.string "%d "
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $128, %r13d
movl $128, %r14d
cmpl $3, %edi
je .L68
.L40:
movslq %r13d, %rbp
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leal 0(,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 88(%rsp)
movl %r14d, %ebx
imull %r13d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 96(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 104(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 40(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movslq %r14d, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 56(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r14d, %r14d
jle .L41
movl %r14d, %edi
movl $0, %esi
movl $0, %ecx
movss .LC1(%rip), %xmm0
movq %r15, %r8
jmp .L42
.L68:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L40
.L44:
movslq %esi, %rdx
leaq (%r8,%rdx,4), %rax
addq %rbp, %rdx
leaq (%r8,%rdx,4), %rdx
.L43:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L43
.L45:
addl $1, %ecx
addl %edi, %esi
cmpl %ecx, %r14d
je .L41
.L42:
testl %r13d, %r13d
jg .L44
jmp .L45
.L41:
testl %r13d, %r13d
jle .L46
movq 24(%rsp), %rcx
movq %rcx, %rax
leaq (%rcx,%rbp,4), %rdx
movss .LC1(%rip), %xmm0
.L47:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L47
.L46:
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
leaq _ZL5c_inp(%rip), %rdi
call cudaMemcpyToSymbol@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L48
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L48:
cvttss2sil %xmm3, %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L49
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L49:
cvttss2sil %xmm3, %r12d
movl %r15d, 112(%rsp)
movl %r12d, 116(%rsp)
movl $1, 120(%rsp)
movl $16, 124(%rsp)
movl $16, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L50:
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 104(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 68(%rsp)
leaq 68(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
call clock@PLT
movq %rax, (%rsp)
movq 56(%rsp), %r9
movl %r13d, %r8d
movl %r14d, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z5cpu_vPfS_S_iiS_
call clock@PLT
movq %rax, %rbx
movl %r13d, %ecx
movl %r14d, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z11compare_resPfS_ii
movq (%rsp), %rcx
subq %rcx, %rbx
imulq $1000, %rbx, %rdx
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
divss .LC5(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl %r12d, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r14d, %r14d
jle .L51
movl %r14d, 8(%rsp)
movl $0, %r15d
movl $0, %eax
leaq .LC9(%rip), %r12
movq %rbp, 16(%rsp)
movl %r14d, 12(%rsp)
movl %r13d, (%rsp)
movq 32(%rsp), %r13
movl %eax, %r14d
jmp .L54
.L69:
movl %r15d, %r8d
movl %r13d, %ecx
movl %r14d, %edx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
jmp .L50
.L60:
movl %ecx, %r14d
.L54:
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jle .L52
movslq %r15d, %rax
leaq 0(%r13,%rax,4), %rbx
movq 16(%rsp), %rcx
addq %rcx, %rax
leaq 0(%r13,%rax,4), %rbp
.L53:
cvttss2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L53
.L52:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r14), %ecx
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %ecx, 12(%rsp)
jne .L60
movl (%rsp), %r13d
movl %r14d, (%rsp)
movl $0, %eax
movl $0, %r14d
leaq .LC9(%rip), %r12
movl %r13d, 8(%rsp)
movl %eax, %r13d
movq 48(%rsp), %r15
movl %ecx, 12(%rsp)
jmp .L57
.L61:
movl %eax, %r14d
.L57:
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L55
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 16(%rsp), %rcx
addq %rcx, %rax
leaq (%r15,%rax,4), %rbp
.L56:
cvttss2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L56
.L55:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r14), %eax
movl 12(%rsp), %ecx
addl %ecx, %r13d
cmpl %r14d, (%rsp)
jne .L61
.L51:
movq 24(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii
.type _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii, @function
_Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii:
.LFB3698:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17unknown_algo_inp1PfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii, .-_Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii
.globl _Z17unknown_algo_inp1PfS_iii
.type _Z17unknown_algo_inp1PfS_iii, @function
_Z17unknown_algo_inp1PfS_iii:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z17unknown_algo_inp1PfS_iii, .-_Z17unknown_algo_inp1PfS_iii
.section .rodata.str1.1
.LC12:
.string "_Z17unknown_algo_inp1PfS_iii"
.LC13:
.string "_Z17unknown_algo_inp2PfS_iii"
.LC14:
.string "c_inp"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z17unknown_algo_inp1PfS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z17unknown_algo_inp2PfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $64000, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5c_inp(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5c_inp
.comm _ZL5c_inp,64000,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1031798784
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1232348160
.align 4
.LC11:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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