system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cuda_runtime.h>
#include <cufft.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include "knn.cuh"
//#include "gpu_data.h"
#define gpu_errchk(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(cudaError_t code, const char *file, int line,
bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "gpu_assert: %s %s %d\n",
cudaGetErrorString(code), file, line);
exit(code);
}
}
#define BW 1024
template<typename T> void cudaMemsetType(T *dev_ptr, T val, int n_vals)
{
thrust::device_ptr<T> thrust_dev_ptr(dev_ptr);
thrust::fill(thrust_dev_ptr, thrust_dev_ptr + n_vals, val);
}
// Uses reduction to quickly add things.
__global__ void correlationKernel(float* cij, float*sum, int total_size)
{
extern __shared__ float shmem[];
// atomically add the accumulated loss per block into the global accumulator
uint s_thread_index = threadIdx.x;
uint thread_index = blockIdx.x * blockDim.x + threadIdx.x;
while(thread_index < total_size)
{
shmem[s_thread_index] = cij[thread_index];
thread_index += blockDim.x * gridDim.x;
}
__syncthreads();
for(int stride = blockDim.x/2; stride > 0; stride /= 2)
{
if(s_thread_index < stride)
{
shmem[s_thread_index] += shmem[s_thread_index + stride];
}
__syncthreads();
}
if (threadIdx.x == 0){
atomicAdd(sum, shmem[0]);
}
}
// Called to get the sum from correlationKernel.
// cij is a lot larger than total_size, but we only want that much of it.
float correlationKernelSum(float* cij, int total_size)
{
// Inialize loss on the device to be zero
float sum, *d_sum;
gpu_errchk( cudaMalloc(&d_sum, sizeof(float)) );
cudaMemsetType<float>(d_sum, 0.0, 1);
float *gpu_cij;
gpu_errchk( cudaMalloc(&gpu_cij, total_size * sizeof(float)) );
gpu_errchk(cudaMemcpy(gpu_cij, cij, total_size * sizeof(float),
cudaMemcpyHostToDevice));
// Accumulate the total loss on the device by invoking a kernel
int n_blocks = std::min(65535, (total_size + BW - 1) / BW);
correlationKernel <<<n_blocks, BW, BW * sizeof(float)>>>(gpu_cij, d_sum, total_size);
gpu_errchk( cudaMemcpy(&sum, d_sum, sizeof(float), cudaMemcpyDeviceToHost) );
gpu_errchk( cudaFree(d_sum) );
gpu_errchk( cudaFree(gpu_cij) );
// Return the sum
return sum;
}
// This using threads to help us sort in parallel.
__global__
void mergeSortKernel( float *src, float*dst, float * followsrc, float * followdst, int section, int num_section, int total_size)
{
uint thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int low = thread_index * section * num_section;
int mid, hi;
int slice = 0;
// Now we do stuff for each section.
while(slice < num_section && low < total_size)
{
mid = min(low + section/2, total_size);
hi = min(low + section, total_size);
merge(src, dst, followsrc, followdst,low, mid, hi);
low += section;
slice ++;
}
}
/*
* This function merges 2 lists [low to mid), [mid to hi) not in places.
*/
__device__
void merge(float *src, float *dst, float* followsrc, float* followdst, int low, int mid, int hi)
{
int a_counter = low;
int b_counter = mid;
for (int i = low; i < hi; i++) {
if (a_counter < mid && (b_counter >= hi || src[a_counter] > src[b_counter])) {
dst[i] = src[a_counter];
followdst[i] = followsrc[a_counter];
a_counter ++;
}
else
{
if (src[a_counter] == src[b_counter])
{
if (followsrc[a_counter] > followsrc[b_counter])
{
dst[i] = src[a_counter];
followdst[i] = followsrc[a_counter];
a_counter ++;
}
else
{
dst[i] = src[b_counter];
followdst[i] = followsrc[b_counter];
b_counter ++;
}
}
else
{
dst[i] = src[b_counter];
followdst[i] = followsrc[b_counter];
b_counter ++;
}
}
}
}
/*
* This function allocates memory for the device objects, and calls the merge kernel.
* Here, we start with small sections and sort them, and doubling the section size each time.
*/
void callMergeKernel(const unsigned int blocks, const unsigned int threadsPerBlock, float * cij, float * cijr, int total_size)
{
//Allocate GPU...
float *gpu_src;
gpu_errchk(cudaMalloc((void **) &gpu_src, total_size * sizeof(float)));
gpu_errchk(cudaMemcpy(gpu_src, cij, total_size * sizeof(float),
cudaMemcpyHostToDevice));
float *gpu_dst;
gpu_errchk(cudaMalloc((void **) &gpu_dst, total_size * sizeof(float)));
gpu_errchk(cudaMemset(gpu_dst, 0, total_size * sizeof(float)));
float *gpu_fsrc;
gpu_errchk(cudaMalloc((void **) &gpu_fsrc, total_size * sizeof(float)));
gpu_errchk(cudaMemcpy(gpu_fsrc, cijr, total_size * sizeof(float),
cudaMemcpyHostToDevice));
float *gpu_fdst;
gpu_errchk(cudaMalloc((void **) &gpu_fdst, total_size * sizeof(float)));
gpu_errchk(cudaMemset(gpu_fdst, 0, total_size * sizeof(float)));
int total_threads = blocks * threadsPerBlock;
for (int section = 2; section< total_size *2; section <<= 1) {
int num_section = total_size / ((total_threads) * section) + 1;
mergeSortKernel<<<blocks, threadsPerBlock>>>(gpu_src, gpu_dst, gpu_fsrc, gpu_fdst, section, num_section, total_size);
float *temp = gpu_dst;
gpu_dst = gpu_src;
gpu_src = temp;
temp = gpu_fdst;
gpu_fdst = gpu_fsrc;
gpu_fsrc = temp;
}
gpu_errchk(cudaMemcpy(cij, gpu_src, total_size * sizeof(float),
cudaMemcpyDeviceToHost));
gpu_errchk(cudaMemcpy(cijr, gpu_fsrc, total_size * sizeof(float),
cudaMemcpyDeviceToHost));
gpu_errchk( cudaFree(gpu_fsrc) );
gpu_errchk( cudaFree(gpu_src) );
gpu_errchk( cudaFree(gpu_dst) );
gpu_errchk( cudaFree(gpu_fdst) );
} | /* CUDA blur
* Kevin Yuh, 2014 */
#ifndef CUDA_FFT_CONVOLVE_CUH
#define CUDA_FFT_CONVOLVE_CUH
#include <hipfft/hipfft.h>
float correlationKernelSum(float* cij, int total_size);
void merge(float *src, float *dst, float* followsrc, float* followdst, int low, int mid, int hi);
void callMergeKernel(const unsigned int blocks, const unsigned intthreadsPerBlock, float*, float*, int);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* CUDA blur
* Kevin Yuh, 2014 */
#ifndef CUDA_FFT_CONVOLVE_CUH
#define CUDA_FFT_CONVOLVE_CUH
#include <hipfft/hipfft.h>
float correlationKernelSum(float* cij, int total_size);
void merge(float *src, float *dst, float* followsrc, float* followdst, int low, int mid, int hi);
void callMergeKernel(const unsigned int blocks, const unsigned intthreadsPerBlock, float*, float*, int);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* CUDA blur
* Kevin Yuh, 2014 */
#ifndef CUDA_FFT_CONVOLVE_CUH
#define CUDA_FFT_CONVOLVE_CUH
#include <hipfft/hipfft.h>
float correlationKernelSum(float* cij, int total_size);
void merge(float *src, float *dst, float* followsrc, float* followdst, int low, int mid, int hi);
void callMergeKernel(const unsigned int blocks, const unsigned intthreadsPerBlock, float*, float*, int);
#endif | .text
.file "knn.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15mergeSortKernelPfS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD R2, R0, c[0x0][0x180], RZ ; /* 0x0000600000027a24 */
/* 0x000fc600078e02ff */
/*0060*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R19, R2, c[0x0][0x184], RZ ; /* 0x0000610002137a24 */
/* 0x000fca00078e02ff */
/*0080*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x188], !P0 ; /* 0x0000620013007a0c */
/* 0x000fda0004706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, R3, 0x1 ; /* 0x0000000100007424 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*00e0*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fe200078e02ff */
/*00f0*/ LOP3.LUT R16, R19.reuse, 0x1, RZ, 0x3c, !PT ; /* 0x0000000113107812 */
/* 0x040fe200078e3cff */
/*0100*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe20000000800 */
/*0110*/ IADD3 R15, -R19, -0x2, RZ ; /* 0xfffffffe130f7810 */
/* 0x000fe20007ffe1ff */
/*0120*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe2000f8e333f */
/*0130*/ LOP3.LUT R14, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff0e7212 */
/* 0x000fe200078e33ff */
/*0140*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc40008011404 */
/*0150*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0160*/ IADD3 R0, R19, c[0x0][0x180], RZ ; /* 0x0000600013007a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ BSSY B1, 0xd80 ; /* 0x00000c0000017945 */
/* 0x000fe20003800000 */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0013 */
/*0190*/ IMNMX R12, R0, c[0x0][0x188], PT ; /* 0x00006200000c7a17 */
/* 0x000fc80003800200 */
/*01a0*/ ISETP.GE.AND P0, PT, R19, R12, PT ; /* 0x0000000c1300720c */
/* 0x000fe20003f06270 */
/*01b0*/ IMAD.MOV.U32 R19, RZ, RZ, R0 ; /* 0x000000ffff137224 */
/* 0x000fd800078e0000 */
/*01c0*/ @P0 BRA 0xd70 ; /* 0x00000ba000000947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV R18, RZ, RZ, -c[0x0][0x180] ; /* 0x80006000ff127624 */
/* 0x000fe200078e02ff */
/*01e0*/ IADD3 R0, R13, UR4, RZ ; /* 0x000000040d007c10 */
/* 0x000fe2000fffe0ff */
/*01f0*/ BSSY B0, 0x660 ; /* 0x0000046000007945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R23, RZ, RZ, R13 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000d */
/*0210*/ IMAD R20, R17.reuse, R18.reuse, R14 ; /* 0x0000001211147224 */
/* 0x0c0fe200078e020e */
/*0220*/ IMNMX R0, R0, c[0x0][0x188], PT ; /* 0x0000620000007a17 */
/* 0x000fe20003800200 */
/*0230*/ IMAD R3, R17, R18, R16 ; /* 0x0000001211037224 */
/* 0x000fc600078e0210 */
/*0240*/ IMNMX R20, R20, UR5, !PT ; /* 0x0000000514147c17 */
/* 0x000fe2000f800200 */
/*0250*/ IMAD.MOV.U32 R21, RZ, RZ, R0 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0000 */
/*0260*/ IMAD.IADD R3, R3, 0x1, -R20 ; /* 0x0000000103037824 */
/* 0x000fca00078e0a14 */
/*0270*/ LOP3.LUT R3, R3, 0x1, RZ, 0xc0, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ec0ff */
/*0280*/ ISETP.NE.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f05070 */
/*0290*/ @P0 BRA 0x650 ; /* 0x000003b000000947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.WIDE R8, R13, R10, c[0x0][0x160] ; /* 0x000058000d087625 */
/* 0x000fca00078e020a */
/*02c0*/ LDG.E R25, [R8.64] ; /* 0x0000000608197981 */
/* 0x000162000c1e1900 */
/*02d0*/ ISETP.GE.AND P1, PT, R13.reuse, R0, PT ; /* 0x000000000d00720c */
/* 0x040fe20003f26270 */
/*02e0*/ IMAD.SHL.U32 R6, R13.reuse, 0x4, RZ ; /* 0x000000040d067824 */
/* 0x040fe200078e00ff */
/*02f0*/ SHF.R.S32.HI R2, RZ, 0x1f, R13 ; /* 0x0000001fff027819 */
/* 0x000fe2000001140d */
/*0300*/ BSSY B2, 0x420 ; /* 0x0000011000027945 */
/* 0x000fe20003800000 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0320*/ IMAD.WIDE R10, R0, R10, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fe200078e020a */
/*0330*/ SHF.L.U64.HI R7, R13, 0x2, R2 ; /* 0x000000020d077819 */
/* 0x000fe40000010202 */
/*0340*/ IADD3 R2, P2, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x040fe40007f5e0ff */
/*0350*/ IADD3 R4, P3, R6, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x000fc40007f7e0ff */
/*0360*/ IADD3 R6, P4, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f9e0ff */
/*0370*/ IADD3.X R3, R7.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0007037a10 */
/* 0x040fe400017fe4ff */
/*0380*/ IADD3.X R5, R7.reuse, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0007057a10 */
/* 0x040fe40001ffe4ff */
/*0390*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe200027fe4ff */
/*03a0*/ @P1 BRA 0x410 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P1, PT, R0, R12, PT ; /* 0x0000000c0000720c */
/* 0x001fe40003f26270 */
/*03c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*03d0*/ @P1 BRA 0x410 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea4000c1e1900 */
/*0400*/ FSETP.GT.AND P0, PT, R8, R21, PT ; /* 0x000000150800720b */
/* 0x004fd00003f04000 */
/*0410*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0420*/ BSSY B2, 0x640 ; /* 0x0000021000027945 */
/* 0x000fe20003800000 */
/*0430*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0440*/ @P0 BRA 0x5e0 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R29, [R10.64] ; /* 0x000000060a1d7981 */
/* 0x000ea2000c1e1900 */
/*0460*/ LEA R8, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000087a11 */
/* 0x000fc800078210ff */
/*0470*/ LEA.HI.X R9, R0, c[0x0][0x174], R9, 0x2, P1 ; /* 0x00005d0000097a11 */
/* 0x000fe400008f1409 */
/*0480*/ FSETP.NEU.AND P0, PT, R25, R29, PT ; /* 0x0000001d1900720b */
/* 0x024fda0003f0d000 */
/*0490*/ @!P0 BRA 0x500 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*04a0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0001e8000c101906 */
/*04b0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R21, R0, 0x1, RZ ; /* 0x0000000100157810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ IMAD.MOV.U32 R23, RZ, RZ, R13 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000d */
/*04e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0041e2000c101906 */
/*04f0*/ BRA 0x630 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0500*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R11, [R8.64] ; /* 0x00000006080b7981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FSETP.GT.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x004fda0003f04000 */
/*0530*/ @!P0 STG.E [R2.64], R29 ; /* 0x0000001d02008986 */
/* 0x0001e8000c101906 */
/*0540*/ @!P0 LDG.E R27, [R8.64] ; /* 0x00000006081b8981 */
/* 0x000ea8000c1e1900 */
/*0550*/ @!P0 STG.E [R4.64], R27 ; /* 0x0000001b04008986 */
/* 0x0041e8000c101906 */
/*0560*/ @P0 STG.E [R2.64], R25 ; /* 0x0000001902000986 */
/* 0x0001e8000c101906 */
/*0570*/ @P0 LDG.E R11, [R6.64] ; /* 0x00000006060b0981 */
/* 0x000ea2000c1e1900 */
/*0580*/ @!P0 IMAD.MOV.U32 R23, RZ, RZ, R13 ; /* 0x000000ffff178224 */
/* 0x000fe200078e000d */
/*0590*/ @!P0 IADD3 R21, R0, 0x1, RZ ; /* 0x0000000100158810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ @P0 IMAD.MOV.U32 R21, RZ, RZ, R0 ; /* 0x000000ffff150224 */
/* 0x000fe200078e0000 */
/*05b0*/ @P0 IADD3 R23, R13, 0x1, RZ ; /* 0x000000010d170810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0041e2000c101906 */
/*05d0*/ BRA 0x630 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*05e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0201e8000c101906 */
/*05f0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IADD3 R23, R13, 0x1, RZ ; /* 0x000000010d177810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.MOV.U32 R21, RZ, RZ, R0 ; /* 0x000000ffff157224 */
/* 0x000fc400078e0000 */
/*0620*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c101906 */
/*0630*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ IMAD R3, R17, R18, R15 ; /* 0x0000001211037224 */
/* 0x001fca00078e020f */
/*0670*/ ISETP.NE.AND P0, PT, R3, R20, PT ; /* 0x000000140300720c */
/* 0x000fda0003f05270 */
/*0680*/ @!P0 BRA 0xd70 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE R10, R13, R4, c[0x0][0x178] ; /* 0x00005e000d0a7625 */
/* 0x000fc800078e0204 */
/*06b0*/ IMAD.WIDE R4, R13, R4, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x000fc800078e0204 */
/*06c0*/ IMAD.MOV.U32 R27, RZ, RZ, R11 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e000b */
/*06d0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0005 */
/*06e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc800078e00ff */
/*06f0*/ IMAD.WIDE R2, R23, R18, c[0x0][0x160] ; /* 0x0000580017027625 */
/* 0x000fca00078e0212 */
/*0700*/ LDG.E R25, [R2.64] ; /* 0x0000000602197981 */
/* 0x000162000c1e1900 */
/*0710*/ ISETP.GE.AND P1, PT, R23.reuse, R0, PT ; /* 0x000000001700720c */
/* 0x040fe20003f26270 */
/*0720*/ BSSY B0, 0x800 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0730*/ SHF.R.S32.HI R8, RZ, 0x1f, R23 ; /* 0x0000001fff087819 */
/* 0x000fe40000011417 */
/*0740*/ LEA R6, P2, R23.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0017067a11 */
/* 0x040fe400078410ff */
/*0750*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0760*/ LEA.HI.X R7, R23, c[0x0][0x174], R8, 0x2, P2 ; /* 0x00005d0017077a11 */
/* 0x000fe200010f1408 */
/*0770*/ IMAD.WIDE R8, R21, R18, c[0x0][0x160] ; /* 0x0000580015087625 */
/* 0x000fc800078e0212 */
/*0780*/ @P1 BRA 0x7f0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GE.AND P1, PT, R21, R12, PT ; /* 0x0000000c1500720c */
/* 0x001fe40003f26270 */
/*07a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*07b0*/ @P1 BRA 0x7f0 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ FSETP.GT.AND P0, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x004fd00003f04000 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0800*/ BSSY B0, 0xa10 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0820*/ SHF.R.S32.HI R20, RZ, 0x1f, R21 ; /* 0x0000001fff147819 */
/* 0x000fe20000011415 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, R27 ; /* 0x000000ffff037224 */
/* 0x000fe400078e001b */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0850*/ @P0 BRA 0x9c0 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0860*/ LDG.E R29, [R8.64] ; /* 0x00000006081d7981 */
/* 0x000ea2000c1e1900 */
/*0870*/ LEA R10, P1, R21, c[0x0][0x170], 0x2 ; /* 0x00005c00150a7a11 */
/* 0x000fc800078210ff */
/*0880*/ LEA.HI.X R11, R21, c[0x0][0x174], R20, 0x2, P1 ; /* 0x00005d00150b7a11 */
/* 0x000fe400008f1414 */
/*0890*/ FSETP.NEU.AND P0, PT, R25, R29, PT ; /* 0x0000001d1900720b */
/* 0x024fda0003f0d000 */
/*08a0*/ @!P0 BRA 0x900 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*08b0*/ STG.E [R4.64], R29 ; /* 0x0000001d04007986 */
/* 0x0001e8000c101906 */
/*08c0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115157810 */
/* 0x000fc60007ffe0ff */
/*08e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0041e2000c101906 */
/*08f0*/ BRA 0xa00 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0900*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R9, [R10.64] ; /* 0x000000060a097981 */
/* 0x000ea4000c1e1900 */
/*0920*/ FSETP.GT.AND P0, PT, R8, R9, PT ; /* 0x000000090800720b */
/* 0x004fda0003f04000 */
/*0930*/ @!P0 STG.E [R4.64], R29 ; /* 0x0000001d04008986 */
/* 0x0001e8000c101906 */
/*0940*/ @!P0 LDG.E R27, [R10.64] ; /* 0x000000060a1b8981 */
/* 0x000ea8000c1e1900 */
/*0950*/ @!P0 STG.E [R2.64], R27 ; /* 0x0000001b02008986 */
/* 0x0041e8000c101906 */
/*0960*/ @P0 STG.E [R4.64], R25 ; /* 0x0000001904000986 */
/* 0x0001e8000c101906 */
/*0970*/ @P0 LDG.E R9, [R6.64] ; /* 0x0000000606090981 */
/* 0x000ea2000c1e1900 */
/*0980*/ @!P0 IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115158810 */
/* 0x000fc40007ffe0ff */
/*0990*/ @P0 IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117170810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0041e2000c101906 */
/*09b0*/ BRA 0xa00 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09c0*/ STG.E [R4.64], R25 ; /* 0x0000001904007986 */
/* 0x0201e8000c101906 */
/*09d0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fc60007ffe0ff */
/*09f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101906 */
/*0a00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.WIDE R6, R23, R18, c[0x0][0x160] ; /* 0x0000580017067625 */
/* 0x001fca00078e0212 */
/*0a20*/ LDG.E R25, [R6.64] ; /* 0x0000000606197981 */
/* 0x000162000c1e1900 */
/*0a30*/ ISETP.GE.AND P2, PT, R23.reuse, R0, PT ; /* 0x000000001700720c */
/* 0x040fe20003f46270 */
/*0a40*/ BSSY B0, 0xb20 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0a50*/ SHF.R.S32.HI R10, RZ, 0x1f, R23 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011417 */
/*0a60*/ LEA R8, P1, R23.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0017087a11 */
/* 0x040fe400078210ff */
/*0a70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a80*/ LEA.HI.X R9, R23, c[0x0][0x174], R10, 0x2, P1 ; /* 0x00005d0017097a11 */
/* 0x000fe200008f140a */
/*0a90*/ IMAD.WIDE R10, R21, R18, c[0x0][0x160] ; /* 0x00005800150a7625 */
/* 0x000fc800078e0212 */
/*0aa0*/ @P2 BRA 0xb10 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0ab0*/ ISETP.GE.AND P1, PT, R21, R12, PT ; /* 0x0000000c1500720c */
/* 0x001fe40003f26270 */
/*0ac0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0ad0*/ @P1 BRA 0xb10 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0ae0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R27, [R10.64] ; /* 0x000000060a1b7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FSETP.GT.AND P0, PT, R6, R27, PT ; /* 0x0000001b0600720b */
/* 0x004fd00003f04000 */
/*0b10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0b20*/ BSSY B0, 0xd00 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0b30*/ SHF.R.S32.HI R18, RZ, 0x1f, R21 ; /* 0x0000001fff127819 */
/* 0x000fe20000011415 */
/*0b40*/ @P0 BRA 0xcb0 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0b50*/ LDG.E R29, [R10.64] ; /* 0x000000060a1d7981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ LEA R6, P1, R21, c[0x0][0x170], 0x2 ; /* 0x00005c0015067a11 */
/* 0x000fc800078210ff */
/*0b70*/ LEA.HI.X R7, R21, c[0x0][0x174], R18, 0x2, P1 ; /* 0x00005d0015077a11 */
/* 0x000fe400008f1412 */
/*0b80*/ FSETP.NEU.AND P0, PT, R25, R29, PT ; /* 0x0000001d1900720b */
/* 0x024fda0003f0d000 */
/*0b90*/ @!P0 BRA 0xbf0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ STG.E [R4.64+0x4], R29 ; /* 0x0000041d04007986 */
/* 0x0001e8000c101906 */
/*0bb0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0bc0*/ IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115157810 */
/* 0x000fc60007ffe0ff */
/*0bd0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0041e2000c101906 */
/*0be0*/ BRA 0xcf0 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0bf0*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FSETP.GT.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x004fda0003f04000 */
/*0c20*/ @!P0 STG.E [R4.64+0x4], R29 ; /* 0x0000041d04008986 */
/* 0x0001e8000c101906 */
/*0c30*/ @!P0 LDG.E R27, [R6.64] ; /* 0x00000006061b8981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ @!P0 STG.E [R2.64+0x4], R27 ; /* 0x0000041b02008986 */
/* 0x0041e8000c101906 */
/*0c50*/ @P0 STG.E [R4.64+0x4], R25 ; /* 0x0000041904000986 */
/* 0x0001e8000c101906 */
/*0c60*/ @P0 LDG.E R11, [R8.64] ; /* 0x00000006080b0981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ @!P0 IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115158810 */
/* 0x000fc40007ffe0ff */
/*0c80*/ @P0 IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117170810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ @P0 STG.E [R2.64+0x4], R11 ; /* 0x0000040b02000986 */
/* 0x0041e2000c101906 */
/*0ca0*/ BRA 0xcf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ STG.E [R4.64+0x4], R25 ; /* 0x0000041904007986 */
/* 0x0201e8000c101906 */
/*0cc0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea2000c1e1900 */
/*0cd0*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fc60007ffe0ff */
/*0ce0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0041e8000c101906 */
/*0cf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d00*/ IADD3 R13, R13, 0x2, RZ ; /* 0x000000020d0d7810 */
/* 0x000fe40007ffe0ff */
/*0d10*/ IADD3 R10, P1, R2, 0x8, RZ ; /* 0x00000008020a7810 */
/* 0x000fe40007f3e0ff */
/*0d20*/ ISETP.GE.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720c */
/* 0x000fe40003f06270 */
/*0d30*/ IADD3 R4, P2, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x001fe20007f5e0ff */
/*0d40*/ IMAD.X R27, RZ, RZ, R3, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fc800008e0603 */
/*0d50*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00010e0605 */
/*0d60*/ @!P0 BRA 0x6e0 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*0d70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d80*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ ISETP.LT.AND P1, PT, R19, c[0x0][0x188], PT ; /* 0x0000620013007a0c */
/* 0x000fe40003f21270 */
/*0da0*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x184], PT ; /* 0x0000610011007a0c */
/* 0x000fda0003f06270 */
/*0db0*/ @!P0 BRA P1, 0x160 ; /* 0xfffff3a000008947 */
/* 0x000fea000083ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17correlationKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0207 */
/*0060*/ IMAD.SHL.U32 R4, R7, 0x4, RZ ; /* 0x0000000407047824 */
/* 0x000fc600078e00ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x100 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*00a0*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fc60000000f00 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, R0.reuse ; /* 0x000000ffff057224 */
/* 0x100fe400078e0000 */
/*00c0*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*00e0*/ @!P0 BRA 0xb0 ; /* 0xffffffc000008947 */
/* 0x000fea000383ffff */
/*00f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0100*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0110*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0002 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e40000004800 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0180*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f05270 */
/*0190*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01a0*/ @!P1 BRA 0x260 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @!P1 LEA R0, R3, R4, 0x2 ; /* 0x0000000403009211 */
/* 0x000fe200078e10ff */
/*01e0*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x001fe20000004800 */
/*01f0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0200*/ @!P1 LDS R5, [R0] ; /* 0x0000000000059984 */
/* 0x000e240000000800 */
/*0210*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0220*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0250*/ @P1 BRA 0x1c0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0260*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0270*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe200078e00ff */
/*0290*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*02a0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e786 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //STL
#include <iostream>
#include <string>
#include <vector>
#include <time.h>
using namespace std;
///*OCTAVE M-script*/ xfp=single(0.0:0.1:6.3);Xfp=single(dct(xfp));clc;length(Xfp);Xfp(1:5)
unsigned i;
const unsigned N = 2048;
unsigned gpuThr = 256;
unsigned gpuBl = N / gpuThr;
vector < float > inputVec( N );
string letter, subFp; const string sep( "_" );
//=========================== gpu ===========================
__device__ float d_x[ N ], d_Xfp32[ N ], d_ix[ N ];
__device__ double d_Xfp64[ N ]; //double size per dimension in comparision to floats array in global memory; for 2D results in quadratic size
__constant__ unsigned d_N[ 1 ];
__global__ void printKernel()
{
unsigned resNo = 10;
for ( unsigned i = 0; i < resNo; i++ )
printf( "x[%i]: %f\n", i, d_x[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "d_Xfp32[%i]: %.6f; d_Xfp64[%i]: %.6f\n", i, d_Xfp32[ i ], i, d_Xfp64[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "ix[%i]: %f\n", i, d_ix[ i ] );
double acc = 0.0f;
for( unsigned i = 0; i < N; i++ )
acc += ( d_Xfp32[ i ] - d_Xfp64[ i ] ) * ( d_Xfp32[ i ] - d_Xfp64[ i ] );
acc /= N;
printf( "mean difference in dct float vs double accumulators: %.6f\n", sqrtf( acc ) );
}
__global__ void idctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = ( float( ind ) + 0.5f ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = sqrtf( 1.0f / float( N ) ) * d_Xfp32[ 0 ];
float accDC = 0.0f, tmpx = 0.0f;
for ( unsigned k = 1; k < N; k++ )
{
tmpx = d_Xfp32[ k ];
tmpX += tmpx * sqrConst * __cosf( constVal * ( float( k ) ) );
accDC += tmpx;
}
d_ix[ ind ] = tmpX;
}
__global__ void dctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp32[ ind ] = tmpX;
d_Xfp32[ 0 ] = accDC / sqrtf( float( N ) );
}
__global__ void dctKernelDouble()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
double tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp64[ ind ] = tmpX;
d_Xfp64[ 0 ] = accDC / sqrtf( float( N ) );
}
int main( int argc, char* argv[] )
{
for(i=0;i<(unsigned)inputVec.size();i++)inputVec[i]=0.1f*i;
cudaMemcpyToSymbol( d_x, &inputVec[ 0 ], sizeof( float ) * ( unsigned )inputVec.size() );
cudaMemcpyToSymbol( d_N, &N, sizeof( unsigned ) );
clock_t t = clock();
dctKernelFloat<<< gpuBl, gpuThr >>>();
cudaDeviceSynchronize();
cout << "CPU clocks float accumulator: " << double( clock() - t ) << endl;
t = clock();
dctKernelDouble<<< gpuBl, gpuThr >>>();
cudaDeviceSynchronize();
cout << "CPU clocks double accumulator: " << double( clock() - t ) << endl;
t = clock();
idctKernelFloat<<< gpuBl, gpuThr >>>();
cudaDeviceSynchronize();
cout << "CPU clocks idct float accumulator: " << double( clock() - t ) << endl;
printKernel<<< 1, 1 >>>();
cudaFree( d_x );
cudaFree( d_ix );
cudaFree( d_Xfp32 );
cudaFree( d_Xfp64 );
cudaFree( d_N );
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
//P.S. Please note, that streaming data from GPU to RAM is costly in both directions - keep computations in GPU. | .file "tmpxft_00062169_00000000-6_dct1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4769:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L6
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L6:
ret
.cfi_endproc
.LFE4769:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.text
.globl _Z30__device_stub__Z11printKernelvv
.type _Z30__device_stub__Z11printKernelvv, @function
_Z30__device_stub__Z11printKernelvv:
.LFB4058:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11printKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z30__device_stub__Z11printKernelvv, .-_Z30__device_stub__Z11printKernelvv
.globl _Z11printKernelv
.type _Z11printKernelv, @function
_Z11printKernelv:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11printKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z11printKernelv, .-_Z11printKernelv
.globl _Z34__device_stub__Z15idctKernelFloatvv
.type _Z34__device_stub__Z15idctKernelFloatvv, @function
_Z34__device_stub__Z15idctKernelFloatvv:
.LFB4060:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15idctKernelFloatv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z34__device_stub__Z15idctKernelFloatvv, .-_Z34__device_stub__Z15idctKernelFloatvv
.globl _Z15idctKernelFloatv
.type _Z15idctKernelFloatv, @function
_Z15idctKernelFloatv:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15idctKernelFloatvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z15idctKernelFloatv, .-_Z15idctKernelFloatv
.globl _Z33__device_stub__Z14dctKernelFloatvv
.type _Z33__device_stub__Z14dctKernelFloatvv, @function
_Z33__device_stub__Z14dctKernelFloatvv:
.LFB4062:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14dctKernelFloatv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4062:
.size _Z33__device_stub__Z14dctKernelFloatvv, .-_Z33__device_stub__Z14dctKernelFloatvv
.globl _Z14dctKernelFloatv
.type _Z14dctKernelFloatv, @function
_Z14dctKernelFloatv:
.LFB4063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14dctKernelFloatvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _Z14dctKernelFloatv, .-_Z14dctKernelFloatv
.globl _Z34__device_stub__Z15dctKernelDoublevv
.type _Z34__device_stub__Z15dctKernelDoublevv, @function
_Z34__device_stub__Z15dctKernelDoublevv:
.LFB4064:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15dctKernelDoublev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z34__device_stub__Z15dctKernelDoublevv, .-_Z34__device_stub__Z15dctKernelDoublevv
.globl _Z15dctKernelDoublev
.type _Z15dctKernelDoublev, @function
_Z15dctKernelDoublev:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15dctKernelDoublevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z15dctKernelDoublev, .-_Z15dctKernelDoublev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CPU clocks float accumulator: "
.align 8
.LC2:
.string "CPU clocks double accumulator: "
.align 8
.LC3:
.string "CPU clocks idct float accumulator: "
.text
.globl main
.type main, @function
main:
.LFB4033:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl $0, i(%rip)
movq inputVec(%rip), %rsi
movq 8+inputVec(%rip), %rax
subq %rsi, %rax
sarq $2, %rax
movq %rax, %rdx
testl %eax, %eax
je .L42
movl $0, %eax
movss .LC0(%rip), %xmm1
.L45:
movl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rsi,%rax,4)
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
movq inputVec(%rip), %rsi
movq 8+inputVec(%rip), %rcx
subq %rsi, %rcx
sarq $2, %rcx
movq %rcx, %rdx
cmpl %ecx, %eax
jb .L45
.L42:
movl %edx, %edx
salq $2, %rdx
movl $1, %r8d
movl $0, %ecx
leaq _ZL3d_x(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1N(%rip), %rsi
leaq _ZL3d_N(%rip), %rdi
call cudaMemcpyToSymbol@PLT
call clock@PLT
movq %rax, %rbp
movl gpuThr(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl gpuBl(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L46:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movl gpuThr(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl gpuBl(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L47:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movl gpuThr(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl gpuBl(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L48:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L49:
leaq _ZL3d_x(%rip), %rdi
call cudaFree@PLT
leaq _ZL4d_ix(%rip), %rdi
call cudaFree@PLT
leaq _ZL7d_Xfp32(%rip), %rdi
call cudaFree@PLT
leaq _ZL7d_Xfp64(%rip), %rdi
call cudaFree@PLT
leaq _ZL3d_N(%rip), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call _Z33__device_stub__Z14dctKernelFloatvv
jmp .L46
.L53:
call _Z34__device_stub__Z15dctKernelDoublevv
jmp .L47
.L54:
call _Z34__device_stub__Z15idctKernelFloatvv
jmp .L48
.L55:
call _Z30__device_stub__Z11printKernelvv
jmp .L49
.cfi_endproc
.LFE4033:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z15dctKernelDoublev"
.LC5:
.string "_Z14dctKernelFloatv"
.LC6:
.string "_Z15idctKernelFloatv"
.LC7:
.string "_Z11printKernelv"
.LC8:
.string "d_x"
.LC9:
.string "d_Xfp32"
.LC10:
.string "d_ix"
.LC11:
.string "d_Xfp64"
.LC12:
.string "d_N"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15dctKernelDoublev(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dctKernelFloatv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15idctKernelFloatv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11printKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_Xfp32(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_ix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $16384, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_Xfp64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_i, @function
_GLOBAL__sub_I_i:
.LFB4774:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $2048, %eax
movl $0, %edx
divl gpuThr(%rip)
movl %eax, gpuBl(%rip)
movq $0, inputVec(%rip)
movq $0, 8+inputVec(%rip)
movq $0, 16+inputVec(%rip)
movl $8192, %edi
call _Znwm@PLT
movq %rax, inputVec(%rip)
leaq 8192(%rax), %rdx
movq %rdx, 16+inputVec(%rip)
movl $0x00000000, (%rax)
addq $4, %rax
.L59:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L59
movq %rdx, 8+inputVec(%rip)
leaq __dso_handle(%rip), %rbx
movq %rbx, %rdx
leaq inputVec(%rip), %rsi
leaq _ZNSt6vectorIfSaIfEED1Ev(%rip), %rdi
call __cxa_atexit@PLT
leaq 16+_Z6letterB5cxx11(%rip), %rax
movq %rax, _Z6letterB5cxx11(%rip)
movq $0, 8+_Z6letterB5cxx11(%rip)
movb $0, 16+_Z6letterB5cxx11(%rip)
movq %rbx, %rdx
leaq -16(%rax), %rsi
movq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rbp
movq %rbp, %rdi
call __cxa_atexit@PLT
leaq 16+_Z5subFpB5cxx11(%rip), %rax
movq %rax, _Z5subFpB5cxx11(%rip)
movq $0, 8+_Z5subFpB5cxx11(%rip)
movb $0, 16+_Z5subFpB5cxx11(%rip)
movq %rbx, %rdx
leaq -16(%rax), %rsi
movq %rbp, %rdi
call __cxa_atexit@PLT
leaq 16+_ZL3sep(%rip), %rax
movq %rax, _ZL3sep(%rip)
movb $95, 16+_ZL3sep(%rip)
movq $1, 8+_ZL3sep(%rip)
movb $0, 17+_ZL3sep(%rip)
movq %rbx, %rdx
leaq -16(%rax), %rsi
movq %rbp, %rdi
call __cxa_atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4774:
.size _GLOBAL__sub_I_i, .-_GLOBAL__sub_I_i
.section .init_array
.align 8
.quad _GLOBAL__sub_I_i
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3d_N
.comm _ZL3d_N,4,4
.local _ZL7d_Xfp64
.comm _ZL7d_Xfp64,16384,32
.local _ZL4d_ix
.comm _ZL4d_ix,8192,32
.local _ZL7d_Xfp32
.comm _ZL7d_Xfp32,8192,32
.local _ZL3d_x
.comm _ZL3d_x,8192,32
.local _ZL3sep
.comm _ZL3sep,32,32
.globl _Z5subFpB5cxx11
.bss
.align 32
.type _Z5subFpB5cxx11, @object
.size _Z5subFpB5cxx11, 32
_Z5subFpB5cxx11:
.zero 32
.globl _Z6letterB5cxx11
.align 32
.type _Z6letterB5cxx11, @object
.size _Z6letterB5cxx11, 32
_Z6letterB5cxx11:
.zero 32
.globl inputVec
.align 16
.type inputVec, @object
.size inputVec, 24
inputVec:
.zero 24
.globl gpuBl
.align 4
.type gpuBl, @object
.size gpuBl, 4
gpuBl:
.zero 4
.globl gpuThr
.data
.align 4
.type gpuThr, @object
.size gpuThr, 4
gpuThr:
.long 256
.section .rodata
.align 4
.type _ZL1N, @object
.size _ZL1N, 4
_ZL1N:
.long 2048
.globl i
.bss
.align 4
.type i, @object
.size i, 4
i:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1036831949
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //STL
#include <iostream>
#include <string>
#include <vector>
#include <time.h>
using namespace std;
///*OCTAVE M-script*/ xfp=single(0.0:0.1:6.3);Xfp=single(dct(xfp));clc;length(Xfp);Xfp(1:5)
unsigned i;
const unsigned N = 2048;
unsigned gpuThr = 256;
unsigned gpuBl = N / gpuThr;
vector < float > inputVec( N );
string letter, subFp; const string sep( "_" );
//=========================== gpu ===========================
__device__ float d_x[ N ], d_Xfp32[ N ], d_ix[ N ];
__device__ double d_Xfp64[ N ]; //double size per dimension in comparision to floats array in global memory; for 2D results in quadratic size
__constant__ unsigned d_N[ 1 ];
__global__ void printKernel()
{
unsigned resNo = 10;
for ( unsigned i = 0; i < resNo; i++ )
printf( "x[%i]: %f\n", i, d_x[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "d_Xfp32[%i]: %.6f; d_Xfp64[%i]: %.6f\n", i, d_Xfp32[ i ], i, d_Xfp64[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "ix[%i]: %f\n", i, d_ix[ i ] );
double acc = 0.0f;
for( unsigned i = 0; i < N; i++ )
acc += ( d_Xfp32[ i ] - d_Xfp64[ i ] ) * ( d_Xfp32[ i ] - d_Xfp64[ i ] );
acc /= N;
printf( "mean difference in dct float vs double accumulators: %.6f\n", sqrtf( acc ) );
}
__global__ void idctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = ( float( ind ) + 0.5f ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = sqrtf( 1.0f / float( N ) ) * d_Xfp32[ 0 ];
float accDC = 0.0f, tmpx = 0.0f;
for ( unsigned k = 1; k < N; k++ )
{
tmpx = d_Xfp32[ k ];
tmpX += tmpx * sqrConst * __cosf( constVal * ( float( k ) ) );
accDC += tmpx;
}
d_ix[ ind ] = tmpX;
}
__global__ void dctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp32[ ind ] = tmpX;
d_Xfp32[ 0 ] = accDC / sqrtf( float( N ) );
}
__global__ void dctKernelDouble()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
double tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp64[ ind ] = tmpX;
d_Xfp64[ 0 ] = accDC / sqrtf( float( N ) );
}
int main( int argc, char* argv[] )
{
for(i=0;i<(unsigned)inputVec.size();i++)inputVec[i]=0.1f*i;
cudaMemcpyToSymbol( d_x, &inputVec[ 0 ], sizeof( float ) * ( unsigned )inputVec.size() );
cudaMemcpyToSymbol( d_N, &N, sizeof( unsigned ) );
clock_t t = clock();
dctKernelFloat<<< gpuBl, gpuThr >>>();
cudaDeviceSynchronize();
cout << "CPU clocks float accumulator: " << double( clock() - t ) << endl;
t = clock();
dctKernelDouble<<< gpuBl, gpuThr >>>();
cudaDeviceSynchronize();
cout << "CPU clocks double accumulator: " << double( clock() - t ) << endl;
t = clock();
idctKernelFloat<<< gpuBl, gpuThr >>>();
cudaDeviceSynchronize();
cout << "CPU clocks idct float accumulator: " << double( clock() - t ) << endl;
printKernel<<< 1, 1 >>>();
cudaFree( d_x );
cudaFree( d_ix );
cudaFree( d_Xfp32 );
cudaFree( d_Xfp64 );
cudaFree( d_N );
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
}
//P.S. Please note, that streaming data from GPU to RAM is costly in both directions - keep computations in GPU. | //STL
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <vector>
#include <time.h>
using namespace std;
///*OCTAVE M-script*/ xfp=single(0.0:0.1:6.3);Xfp=single(dct(xfp));clc;length(Xfp);Xfp(1:5)
unsigned i;
const unsigned N = 2048;
unsigned gpuThr = 256;
unsigned gpuBl = N / gpuThr;
vector < float > inputVec( N );
string letter, subFp; const string sep( "_" );
//=========================== gpu ===========================
__device__ float d_x[ N ], d_Xfp32[ N ], d_ix[ N ];
__device__ double d_Xfp64[ N ]; //double size per dimension in comparision to floats array in global memory; for 2D results in quadratic size
__constant__ unsigned d_N[ 1 ];
__global__ void printKernel()
{
unsigned resNo = 10;
for ( unsigned i = 0; i < resNo; i++ )
printf( "x[%i]: %f\n", i, d_x[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "d_Xfp32[%i]: %.6f; d_Xfp64[%i]: %.6f\n", i, d_Xfp32[ i ], i, d_Xfp64[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "ix[%i]: %f\n", i, d_ix[ i ] );
double acc = 0.0f;
for( unsigned i = 0; i < N; i++ )
acc += ( d_Xfp32[ i ] - d_Xfp64[ i ] ) * ( d_Xfp32[ i ] - d_Xfp64[ i ] );
acc /= N;
printf( "mean difference in dct float vs double accumulators: %.6f\n", sqrtf( acc ) );
}
__global__ void idctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = ( float( ind ) + 0.5f ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = sqrtf( 1.0f / float( N ) ) * d_Xfp32[ 0 ];
float accDC = 0.0f, tmpx = 0.0f;
for ( unsigned k = 1; k < N; k++ )
{
tmpx = d_Xfp32[ k ];
tmpX += tmpx * sqrConst * __cosf( constVal * ( float( k ) ) );
accDC += tmpx;
}
d_ix[ ind ] = tmpX;
}
__global__ void dctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp32[ ind ] = tmpX;
d_Xfp32[ 0 ] = accDC / sqrtf( float( N ) );
}
__global__ void dctKernelDouble()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
double tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp64[ ind ] = tmpX;
d_Xfp64[ 0 ] = accDC / sqrtf( float( N ) );
}
int main( int argc, char* argv[] )
{
for(i=0;i<(unsigned)inputVec.size();i++)inputVec[i]=0.1f*i;
hipMemcpyToSymbol( HIP_SYMBOL(d_x), &inputVec[ 0 ], sizeof( float ) * ( unsigned )inputVec.size() );
hipMemcpyToSymbol( HIP_SYMBOL(d_N), &N, sizeof( unsigned ) );
clock_t t = clock();
dctKernelFloat<<< gpuBl, gpuThr >>>();
hipDeviceSynchronize();
cout << "CPU clocks float accumulator: " << double( clock() - t ) << endl;
t = clock();
dctKernelDouble<<< gpuBl, gpuThr >>>();
hipDeviceSynchronize();
cout << "CPU clocks double accumulator: " << double( clock() - t ) << endl;
t = clock();
idctKernelFloat<<< gpuBl, gpuThr >>>();
hipDeviceSynchronize();
cout << "CPU clocks idct float accumulator: " << double( clock() - t ) << endl;
printKernel<<< 1, 1 >>>();
hipFree( d_x );
hipFree( d_ix );
hipFree( d_Xfp32 );
hipFree( d_Xfp64 );
hipFree( d_N );
hipDeviceSynchronize();
hipDeviceReset();
return 0;
}
//P.S. Please note, that streaming data from GPU to RAM is costly in both directions - keep computations in GPU. |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //STL
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <vector>
#include <time.h>
using namespace std;
///*OCTAVE M-script*/ xfp=single(0.0:0.1:6.3);Xfp=single(dct(xfp));clc;length(Xfp);Xfp(1:5)
unsigned i;
const unsigned N = 2048;
unsigned gpuThr = 256;
unsigned gpuBl = N / gpuThr;
vector < float > inputVec( N );
string letter, subFp; const string sep( "_" );
//=========================== gpu ===========================
__device__ float d_x[ N ], d_Xfp32[ N ], d_ix[ N ];
__device__ double d_Xfp64[ N ]; //double size per dimension in comparision to floats array in global memory; for 2D results in quadratic size
__constant__ unsigned d_N[ 1 ];
__global__ void printKernel()
{
unsigned resNo = 10;
for ( unsigned i = 0; i < resNo; i++ )
printf( "x[%i]: %f\n", i, d_x[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "d_Xfp32[%i]: %.6f; d_Xfp64[%i]: %.6f\n", i, d_Xfp32[ i ], i, d_Xfp64[ i ] );
for ( unsigned i = 0; i < resNo; i++ )
printf( "ix[%i]: %f\n", i, d_ix[ i ] );
double acc = 0.0f;
for( unsigned i = 0; i < N; i++ )
acc += ( d_Xfp32[ i ] - d_Xfp64[ i ] ) * ( d_Xfp32[ i ] - d_Xfp64[ i ] );
acc /= N;
printf( "mean difference in dct float vs double accumulators: %.6f\n", sqrtf( acc ) );
}
__global__ void idctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = ( float( ind ) + 0.5f ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = sqrtf( 1.0f / float( N ) ) * d_Xfp32[ 0 ];
float accDC = 0.0f, tmpx = 0.0f;
for ( unsigned k = 1; k < N; k++ )
{
tmpx = d_Xfp32[ k ];
tmpX += tmpx * sqrConst * __cosf( constVal * ( float( k ) ) );
accDC += tmpx;
}
d_ix[ ind ] = tmpX;
}
__global__ void dctKernelFloat()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
float tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp32[ ind ] = tmpX;
d_Xfp32[ 0 ] = accDC / sqrtf( float( N ) );
}
__global__ void dctKernelDouble()
{
unsigned ind = blockIdx.x * blockDim.x + threadIdx.x;
float constVal = float( ind ) * 3.14159265f / float( N );
float sqrConst = sqrtf( 2.0f / float( N ) );
double tmpX = 0.0f, accDC = 0.0f, tmpx = 0.0f;
for ( unsigned i = 0; i < N; i++ )
{
tmpx = d_x[ i ];
tmpX += sqrConst * tmpx * __cosf( constVal * ( float( i ) + 0.5f ) );
accDC += tmpx;
}
d_Xfp64[ ind ] = tmpX;
d_Xfp64[ 0 ] = accDC / sqrtf( float( N ) );
}
int main( int argc, char* argv[] )
{
for(i=0;i<(unsigned)inputVec.size();i++)inputVec[i]=0.1f*i;
hipMemcpyToSymbol( HIP_SYMBOL(d_x), &inputVec[ 0 ], sizeof( float ) * ( unsigned )inputVec.size() );
hipMemcpyToSymbol( HIP_SYMBOL(d_N), &N, sizeof( unsigned ) );
clock_t t = clock();
dctKernelFloat<<< gpuBl, gpuThr >>>();
hipDeviceSynchronize();
cout << "CPU clocks float accumulator: " << double( clock() - t ) << endl;
t = clock();
dctKernelDouble<<< gpuBl, gpuThr >>>();
hipDeviceSynchronize();
cout << "CPU clocks double accumulator: " << double( clock() - t ) << endl;
t = clock();
idctKernelFloat<<< gpuBl, gpuThr >>>();
hipDeviceSynchronize();
cout << "CPU clocks idct float accumulator: " << double( clock() - t ) << endl;
printKernel<<< 1, 1 >>>();
hipFree( d_x );
hipFree( d_ix );
hipFree( d_Xfp32 );
hipFree( d_Xfp64 );
hipFree( d_N );
hipDeviceSynchronize();
hipDeviceReset();
return 0;
}
//P.S. Please note, that streaming data from GPU to RAM is costly in both directions - keep computations in GPU. | .text
.file "dct1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED2Ev,comdat
.weak _ZNSt6vectorIfSaIfEED2Ev # -- Begin function _ZNSt6vectorIfSaIfEED2Ev
.p2align 4, 0x90
.type _ZNSt6vectorIfSaIfEED2Ev,@function
_ZNSt6vectorIfSaIfEED2Ev: # @_ZNSt6vectorIfSaIfEED2Ev
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
testq %rdi, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit
retq
.Lfunc_end0:
.size _ZNSt6vectorIfSaIfEED2Ev, .Lfunc_end0-_ZNSt6vectorIfSaIfEED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq (%rdi), %rdi
addq $16, %rax
cmpq %rax, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
retq
.Lfunc_end1:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, .Lfunc_end1-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_endproc
# -- End function
.text
.globl _Z26__device_stub__printKernelv # -- Begin function _Z26__device_stub__printKernelv
.p2align 4, 0x90
.type _Z26__device_stub__printKernelv,@function
_Z26__device_stub__printKernelv: # @_Z26__device_stub__printKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11printKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z26__device_stub__printKernelv, .Lfunc_end2-_Z26__device_stub__printKernelv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__idctKernelFloatv # -- Begin function _Z30__device_stub__idctKernelFloatv
.p2align 4, 0x90
.type _Z30__device_stub__idctKernelFloatv,@function
_Z30__device_stub__idctKernelFloatv: # @_Z30__device_stub__idctKernelFloatv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15idctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end3:
.size _Z30__device_stub__idctKernelFloatv, .Lfunc_end3-_Z30__device_stub__idctKernelFloatv
.cfi_endproc
# -- End function
.globl _Z29__device_stub__dctKernelFloatv # -- Begin function _Z29__device_stub__dctKernelFloatv
.p2align 4, 0x90
.type _Z29__device_stub__dctKernelFloatv,@function
_Z29__device_stub__dctKernelFloatv: # @_Z29__device_stub__dctKernelFloatv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14dctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end4:
.size _Z29__device_stub__dctKernelFloatv, .Lfunc_end4-_Z29__device_stub__dctKernelFloatv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__dctKernelDoublev # -- Begin function _Z30__device_stub__dctKernelDoublev
.p2align 4, 0x90
.type _Z30__device_stub__dctKernelDoublev,@function
_Z30__device_stub__dctKernelDoublev: # @_Z30__device_stub__dctKernelDoublev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15dctKernelDoublev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end5:
.size _Z30__device_stub__dctKernelDoublev, .Lfunc_end5-_Z30__device_stub__dctKernelDoublev
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x3dcccccd # float 0.100000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
movq inputVec+8(%rip), %rdx
movq inputVec(%rip), %rsi
subq %rsi, %rdx
testq %rax, %rdx
je .LBB6_1
# %bb.2: # %.lr.ph.preheader
movq %rdx, %rcx
shrq $2, %rcx
movl %ecx, %edi
xorl %ecx, %ecx
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rdi
jne .LBB6_3
jmp .LBB6_4
.LBB6_1:
xorl %ecx, %ecx
.LBB6_4: # %._crit_edge
movabsq $4294967296, %rbx # imm = 0x100000000
movl %ecx, i(%rip)
andq %rax, %rdx
movl $d_x, %edi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $d_N, %edi
movl $_ZL1N, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
callq clock
movq %rax, %r14
movl gpuBl(%rip), %edi
movl gpuThr(%rip), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14dctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB6_25
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB6_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB6_10
.LBB6_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB6_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r14
movl gpuBl(%rip), %edi
movl gpuThr(%rip), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15dctKernelDoublev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB6_25
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%r14)
je .LBB6_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB6_16
.LBB6_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB6_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r14
movl gpuBl(%rip), %edi
movl gpuThr(%rip), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_18
# %bb.17:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15idctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_18:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB6_25
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%r14)
je .LBB6_21
# %bb.20:
movzbl 67(%r14), %ecx
jmp .LBB6_22
.LBB6_21:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB6_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_24
# %bb.23:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11printKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_24:
movl $d_x, %edi
callq hipFree
movl $d_ix, %edi
callq hipFree
movl $d_Xfp32, %edi
callq hipFree
movl $d_Xfp64, %edi
callq hipFree
movl $d_N, %edi
callq hipFree
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_25:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_dct1d.hip
.type _GLOBAL__sub_I_dct1d.hip,@function
_GLOBAL__sub_I_dct1d.hip: # @_GLOBAL__sub_I_dct1d.hip
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $2048, %eax # imm = 0x800
xorl %edx, %edx
divl gpuThr(%rip)
movl %eax, gpuBl(%rip)
xorps %xmm0, %xmm0
movups %xmm0, inputVec(%rip)
movq $0, inputVec+16(%rip)
movl $8192, %edi # imm = 0x2000
callq _Znwm
movq %rax, inputVec(%rip)
movq %rax, inputVec+8(%rip)
leaq 8192(%rax), %rbx
movq %rbx, inputVec+16(%rip)
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, inputVec+8(%rip)
movl $_ZNSt6vectorIfSaIfEED2Ev, %edi
movl $inputVec, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z6letterB5cxx11, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z5subFpB5cxx11, %esi
movl $__dso_handle, %edx
popq %rbx
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end7:
.size _GLOBAL__sub_I_dct1d.hip, .Lfunc_end7-_GLOBAL__sub_I_dct1d.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11printKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15idctKernelFloatv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dctKernelFloatv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15dctKernelDoublev, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_x, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_Xfp32, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_ix, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_Xfp64, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $16384, %r9d # imm = 0x4000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_N, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type i,@object # @i
.bss
.globl i
.p2align 2, 0x0
i:
.long 0 # 0x0
.size i, 4
.type gpuThr,@object # @gpuThr
.data
.globl gpuThr
.p2align 2, 0x0
gpuThr:
.long 256 # 0x100
.size gpuThr, 4
.type gpuBl,@object # @gpuBl
.bss
.globl gpuBl
.p2align 2, 0x0
gpuBl:
.long 0 # 0x0
.size gpuBl, 4
.type inputVec,@object # @inputVec
.globl inputVec
.p2align 3, 0x0
inputVec:
.zero 24
.size inputVec, 24
.hidden __dso_handle
.type _Z6letterB5cxx11,@object # @_Z6letterB5cxx11
.data
.globl _Z6letterB5cxx11
.p2align 3, 0x0
_Z6letterB5cxx11:
.quad _Z6letterB5cxx11+16
.quad 0 # 0x0
.zero 16
.size _Z6letterB5cxx11, 32
.type _Z5subFpB5cxx11,@object # @_Z5subFpB5cxx11
.globl _Z5subFpB5cxx11
.p2align 3, 0x0
_Z5subFpB5cxx11:
.quad _Z5subFpB5cxx11+16
.quad 0 # 0x0
.zero 16
.size _Z5subFpB5cxx11, 32
.type d_x,@object # @d_x
.local d_x
.comm d_x,8192,16
.type d_Xfp32,@object # @d_Xfp32
.local d_Xfp32
.comm d_Xfp32,8192,16
.type d_ix,@object # @d_ix
.local d_ix
.comm d_ix,8192,16
.type d_Xfp64,@object # @d_Xfp64
.local d_Xfp64
.comm d_Xfp64,16384,16
.type d_N,@object # @d_N
.local d_N
.comm d_N,4,4
.type _Z11printKernelv,@object # @_Z11printKernelv
.section .rodata,"a",@progbits
.globl _Z11printKernelv
.p2align 3, 0x0
_Z11printKernelv:
.quad _Z26__device_stub__printKernelv
.size _Z11printKernelv, 8
.type _Z15idctKernelFloatv,@object # @_Z15idctKernelFloatv
.globl _Z15idctKernelFloatv
.p2align 3, 0x0
_Z15idctKernelFloatv:
.quad _Z30__device_stub__idctKernelFloatv
.size _Z15idctKernelFloatv, 8
.type _Z14dctKernelFloatv,@object # @_Z14dctKernelFloatv
.globl _Z14dctKernelFloatv
.p2align 3, 0x0
_Z14dctKernelFloatv:
.quad _Z29__device_stub__dctKernelFloatv
.size _Z14dctKernelFloatv, 8
.type _Z15dctKernelDoublev,@object # @_Z15dctKernelDoublev
.globl _Z15dctKernelDoublev
.p2align 3, 0x0
_Z15dctKernelDoublev:
.quad _Z30__device_stub__dctKernelDoublev
.size _Z15dctKernelDoublev, 8
.type _ZL1N,@object # @_ZL1N
.p2align 2, 0x0
_ZL1N:
.long 2048 # 0x800
.size _ZL1N, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU clocks float accumulator: "
.size .L.str, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU clocks double accumulator: "
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU clocks idct float accumulator: "
.size .L.str.7, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11printKernelv"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15idctKernelFloatv"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14dctKernelFloatv"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15dctKernelDoublev"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "d_x"
.size .L__unnamed_5, 4
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "d_Xfp32"
.size .L__unnamed_6, 8
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "d_ix"
.size .L__unnamed_7, 5
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "d_Xfp64"
.size .L__unnamed_8, 8
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "d_N"
.size .L__unnamed_9, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_dct1d.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z26__device_stub__printKernelv
.addrsig_sym _Z30__device_stub__idctKernelFloatv
.addrsig_sym _Z29__device_stub__dctKernelFloatv
.addrsig_sym _Z30__device_stub__dctKernelDoublev
.addrsig_sym _GLOBAL__sub_I_dct1d.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym inputVec
.addrsig_sym __dso_handle
.addrsig_sym _Z6letterB5cxx11
.addrsig_sym _Z5subFpB5cxx11
.addrsig_sym d_x
.addrsig_sym d_Xfp32
.addrsig_sym d_ix
.addrsig_sym d_Xfp64
.addrsig_sym d_N
.addrsig_sym _Z11printKernelv
.addrsig_sym _Z15idctKernelFloatv
.addrsig_sym _Z14dctKernelFloatv
.addrsig_sym _Z15dctKernelDoublev
.addrsig_sym _ZL1N
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062169_00000000-6_dct1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4769:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L6
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L6:
ret
.cfi_endproc
.LFE4769:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.text
.globl _Z30__device_stub__Z11printKernelvv
.type _Z30__device_stub__Z11printKernelvv, @function
_Z30__device_stub__Z11printKernelvv:
.LFB4058:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11printKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z30__device_stub__Z11printKernelvv, .-_Z30__device_stub__Z11printKernelvv
.globl _Z11printKernelv
.type _Z11printKernelv, @function
_Z11printKernelv:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11printKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z11printKernelv, .-_Z11printKernelv
.globl _Z34__device_stub__Z15idctKernelFloatvv
.type _Z34__device_stub__Z15idctKernelFloatvv, @function
_Z34__device_stub__Z15idctKernelFloatvv:
.LFB4060:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15idctKernelFloatv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z34__device_stub__Z15idctKernelFloatvv, .-_Z34__device_stub__Z15idctKernelFloatvv
.globl _Z15idctKernelFloatv
.type _Z15idctKernelFloatv, @function
_Z15idctKernelFloatv:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15idctKernelFloatvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z15idctKernelFloatv, .-_Z15idctKernelFloatv
.globl _Z33__device_stub__Z14dctKernelFloatvv
.type _Z33__device_stub__Z14dctKernelFloatvv, @function
_Z33__device_stub__Z14dctKernelFloatvv:
.LFB4062:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14dctKernelFloatv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4062:
.size _Z33__device_stub__Z14dctKernelFloatvv, .-_Z33__device_stub__Z14dctKernelFloatvv
.globl _Z14dctKernelFloatv
.type _Z14dctKernelFloatv, @function
_Z14dctKernelFloatv:
.LFB4063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14dctKernelFloatvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _Z14dctKernelFloatv, .-_Z14dctKernelFloatv
.globl _Z34__device_stub__Z15dctKernelDoublevv
.type _Z34__device_stub__Z15dctKernelDoublevv, @function
_Z34__device_stub__Z15dctKernelDoublevv:
.LFB4064:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15dctKernelDoublev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z34__device_stub__Z15dctKernelDoublevv, .-_Z34__device_stub__Z15dctKernelDoublevv
.globl _Z15dctKernelDoublev
.type _Z15dctKernelDoublev, @function
_Z15dctKernelDoublev:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15dctKernelDoublevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z15dctKernelDoublev, .-_Z15dctKernelDoublev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CPU clocks float accumulator: "
.align 8
.LC2:
.string "CPU clocks double accumulator: "
.align 8
.LC3:
.string "CPU clocks idct float accumulator: "
.text
.globl main
.type main, @function
main:
.LFB4033:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl $0, i(%rip)
movq inputVec(%rip), %rsi
movq 8+inputVec(%rip), %rax
subq %rsi, %rax
sarq $2, %rax
movq %rax, %rdx
testl %eax, %eax
je .L42
movl $0, %eax
movss .LC0(%rip), %xmm1
.L45:
movl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rsi,%rax,4)
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
movq inputVec(%rip), %rsi
movq 8+inputVec(%rip), %rcx
subq %rsi, %rcx
sarq $2, %rcx
movq %rcx, %rdx
cmpl %ecx, %eax
jb .L45
.L42:
movl %edx, %edx
salq $2, %rdx
movl $1, %r8d
movl $0, %ecx
leaq _ZL3d_x(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1N(%rip), %rsi
leaq _ZL3d_N(%rip), %rdi
call cudaMemcpyToSymbol@PLT
call clock@PLT
movq %rax, %rbp
movl gpuThr(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl gpuBl(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L46:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movl gpuThr(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl gpuBl(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L47:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movl gpuThr(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl gpuBl(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L48:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L49:
leaq _ZL3d_x(%rip), %rdi
call cudaFree@PLT
leaq _ZL4d_ix(%rip), %rdi
call cudaFree@PLT
leaq _ZL7d_Xfp32(%rip), %rdi
call cudaFree@PLT
leaq _ZL7d_Xfp64(%rip), %rdi
call cudaFree@PLT
leaq _ZL3d_N(%rip), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call _Z33__device_stub__Z14dctKernelFloatvv
jmp .L46
.L53:
call _Z34__device_stub__Z15dctKernelDoublevv
jmp .L47
.L54:
call _Z34__device_stub__Z15idctKernelFloatvv
jmp .L48
.L55:
call _Z30__device_stub__Z11printKernelvv
jmp .L49
.cfi_endproc
.LFE4033:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z15dctKernelDoublev"
.LC5:
.string "_Z14dctKernelFloatv"
.LC6:
.string "_Z15idctKernelFloatv"
.LC7:
.string "_Z11printKernelv"
.LC8:
.string "d_x"
.LC9:
.string "d_Xfp32"
.LC10:
.string "d_ix"
.LC11:
.string "d_Xfp64"
.LC12:
.string "d_N"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15dctKernelDoublev(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dctKernelFloatv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15idctKernelFloatv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11printKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_Xfp32(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_ix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $16384, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_Xfp64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_i, @function
_GLOBAL__sub_I_i:
.LFB4774:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $2048, %eax
movl $0, %edx
divl gpuThr(%rip)
movl %eax, gpuBl(%rip)
movq $0, inputVec(%rip)
movq $0, 8+inputVec(%rip)
movq $0, 16+inputVec(%rip)
movl $8192, %edi
call _Znwm@PLT
movq %rax, inputVec(%rip)
leaq 8192(%rax), %rdx
movq %rdx, 16+inputVec(%rip)
movl $0x00000000, (%rax)
addq $4, %rax
.L59:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L59
movq %rdx, 8+inputVec(%rip)
leaq __dso_handle(%rip), %rbx
movq %rbx, %rdx
leaq inputVec(%rip), %rsi
leaq _ZNSt6vectorIfSaIfEED1Ev(%rip), %rdi
call __cxa_atexit@PLT
leaq 16+_Z6letterB5cxx11(%rip), %rax
movq %rax, _Z6letterB5cxx11(%rip)
movq $0, 8+_Z6letterB5cxx11(%rip)
movb $0, 16+_Z6letterB5cxx11(%rip)
movq %rbx, %rdx
leaq -16(%rax), %rsi
movq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rbp
movq %rbp, %rdi
call __cxa_atexit@PLT
leaq 16+_Z5subFpB5cxx11(%rip), %rax
movq %rax, _Z5subFpB5cxx11(%rip)
movq $0, 8+_Z5subFpB5cxx11(%rip)
movb $0, 16+_Z5subFpB5cxx11(%rip)
movq %rbx, %rdx
leaq -16(%rax), %rsi
movq %rbp, %rdi
call __cxa_atexit@PLT
leaq 16+_ZL3sep(%rip), %rax
movq %rax, _ZL3sep(%rip)
movb $95, 16+_ZL3sep(%rip)
movq $1, 8+_ZL3sep(%rip)
movb $0, 17+_ZL3sep(%rip)
movq %rbx, %rdx
leaq -16(%rax), %rsi
movq %rbp, %rdi
call __cxa_atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4774:
.size _GLOBAL__sub_I_i, .-_GLOBAL__sub_I_i
.section .init_array
.align 8
.quad _GLOBAL__sub_I_i
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3d_N
.comm _ZL3d_N,4,4
.local _ZL7d_Xfp64
.comm _ZL7d_Xfp64,16384,32
.local _ZL4d_ix
.comm _ZL4d_ix,8192,32
.local _ZL7d_Xfp32
.comm _ZL7d_Xfp32,8192,32
.local _ZL3d_x
.comm _ZL3d_x,8192,32
.local _ZL3sep
.comm _ZL3sep,32,32
.globl _Z5subFpB5cxx11
.bss
.align 32
.type _Z5subFpB5cxx11, @object
.size _Z5subFpB5cxx11, 32
_Z5subFpB5cxx11:
.zero 32
.globl _Z6letterB5cxx11
.align 32
.type _Z6letterB5cxx11, @object
.size _Z6letterB5cxx11, 32
_Z6letterB5cxx11:
.zero 32
.globl inputVec
.align 16
.type inputVec, @object
.size inputVec, 24
inputVec:
.zero 24
.globl gpuBl
.align 4
.type gpuBl, @object
.size gpuBl, 4
gpuBl:
.zero 4
.globl gpuThr
.data
.align 4
.type gpuThr, @object
.size gpuThr, 4
gpuThr:
.long 256
.section .rodata
.align 4
.type _ZL1N, @object
.size _ZL1N, 4
_ZL1N:
.long 2048
.globl i
.bss
.align 4
.type i, @object
.size i, 4
i:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1036831949
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dct1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED2Ev,comdat
.weak _ZNSt6vectorIfSaIfEED2Ev # -- Begin function _ZNSt6vectorIfSaIfEED2Ev
.p2align 4, 0x90
.type _ZNSt6vectorIfSaIfEED2Ev,@function
_ZNSt6vectorIfSaIfEED2Ev: # @_ZNSt6vectorIfSaIfEED2Ev
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
testq %rdi, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit
retq
.Lfunc_end0:
.size _ZNSt6vectorIfSaIfEED2Ev, .Lfunc_end0-_ZNSt6vectorIfSaIfEED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq (%rdi), %rdi
addq $16, %rax
cmpq %rax, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
retq
.Lfunc_end1:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, .Lfunc_end1-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_endproc
# -- End function
.text
.globl _Z26__device_stub__printKernelv # -- Begin function _Z26__device_stub__printKernelv
.p2align 4, 0x90
.type _Z26__device_stub__printKernelv,@function
_Z26__device_stub__printKernelv: # @_Z26__device_stub__printKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11printKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z26__device_stub__printKernelv, .Lfunc_end2-_Z26__device_stub__printKernelv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__idctKernelFloatv # -- Begin function _Z30__device_stub__idctKernelFloatv
.p2align 4, 0x90
.type _Z30__device_stub__idctKernelFloatv,@function
_Z30__device_stub__idctKernelFloatv: # @_Z30__device_stub__idctKernelFloatv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15idctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end3:
.size _Z30__device_stub__idctKernelFloatv, .Lfunc_end3-_Z30__device_stub__idctKernelFloatv
.cfi_endproc
# -- End function
.globl _Z29__device_stub__dctKernelFloatv # -- Begin function _Z29__device_stub__dctKernelFloatv
.p2align 4, 0x90
.type _Z29__device_stub__dctKernelFloatv,@function
_Z29__device_stub__dctKernelFloatv: # @_Z29__device_stub__dctKernelFloatv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14dctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end4:
.size _Z29__device_stub__dctKernelFloatv, .Lfunc_end4-_Z29__device_stub__dctKernelFloatv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__dctKernelDoublev # -- Begin function _Z30__device_stub__dctKernelDoublev
.p2align 4, 0x90
.type _Z30__device_stub__dctKernelDoublev,@function
_Z30__device_stub__dctKernelDoublev: # @_Z30__device_stub__dctKernelDoublev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15dctKernelDoublev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end5:
.size _Z30__device_stub__dctKernelDoublev, .Lfunc_end5-_Z30__device_stub__dctKernelDoublev
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x3dcccccd # float 0.100000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
movq inputVec+8(%rip), %rdx
movq inputVec(%rip), %rsi
subq %rsi, %rdx
testq %rax, %rdx
je .LBB6_1
# %bb.2: # %.lr.ph.preheader
movq %rdx, %rcx
shrq $2, %rcx
movl %ecx, %edi
xorl %ecx, %ecx
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rdi
jne .LBB6_3
jmp .LBB6_4
.LBB6_1:
xorl %ecx, %ecx
.LBB6_4: # %._crit_edge
movabsq $4294967296, %rbx # imm = 0x100000000
movl %ecx, i(%rip)
andq %rax, %rdx
movl $d_x, %edi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $d_N, %edi
movl $_ZL1N, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
callq clock
movq %rax, %r14
movl gpuBl(%rip), %edi
movl gpuThr(%rip), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14dctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB6_25
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB6_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB6_10
.LBB6_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB6_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r14
movl gpuBl(%rip), %edi
movl gpuThr(%rip), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15dctKernelDoublev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB6_25
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%r14)
je .LBB6_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB6_16
.LBB6_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB6_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r14
movl gpuBl(%rip), %edi
movl gpuThr(%rip), %edx
orq %rbx, %rdi
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_18
# %bb.17:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15idctKernelFloatv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_18:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB6_25
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%r14)
je .LBB6_21
# %bb.20:
movzbl 67(%r14), %ecx
jmp .LBB6_22
.LBB6_21:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB6_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_24
# %bb.23:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11printKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_24:
movl $d_x, %edi
callq hipFree
movl $d_ix, %edi
callq hipFree
movl $d_Xfp32, %edi
callq hipFree
movl $d_Xfp64, %edi
callq hipFree
movl $d_N, %edi
callq hipFree
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_25:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_dct1d.hip
.type _GLOBAL__sub_I_dct1d.hip,@function
_GLOBAL__sub_I_dct1d.hip: # @_GLOBAL__sub_I_dct1d.hip
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $2048, %eax # imm = 0x800
xorl %edx, %edx
divl gpuThr(%rip)
movl %eax, gpuBl(%rip)
xorps %xmm0, %xmm0
movups %xmm0, inputVec(%rip)
movq $0, inputVec+16(%rip)
movl $8192, %edi # imm = 0x2000
callq _Znwm
movq %rax, inputVec(%rip)
movq %rax, inputVec+8(%rip)
leaq 8192(%rax), %rbx
movq %rbx, inputVec+16(%rip)
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, inputVec+8(%rip)
movl $_ZNSt6vectorIfSaIfEED2Ev, %edi
movl $inputVec, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z6letterB5cxx11, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_Z5subFpB5cxx11, %esi
movl $__dso_handle, %edx
popq %rbx
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end7:
.size _GLOBAL__sub_I_dct1d.hip, .Lfunc_end7-_GLOBAL__sub_I_dct1d.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11printKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15idctKernelFloatv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dctKernelFloatv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15dctKernelDoublev, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_x, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_Xfp32, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_ix, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_Xfp64, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $16384, %r9d # imm = 0x4000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_N, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type i,@object # @i
.bss
.globl i
.p2align 2, 0x0
i:
.long 0 # 0x0
.size i, 4
.type gpuThr,@object # @gpuThr
.data
.globl gpuThr
.p2align 2, 0x0
gpuThr:
.long 256 # 0x100
.size gpuThr, 4
.type gpuBl,@object # @gpuBl
.bss
.globl gpuBl
.p2align 2, 0x0
gpuBl:
.long 0 # 0x0
.size gpuBl, 4
.type inputVec,@object # @inputVec
.globl inputVec
.p2align 3, 0x0
inputVec:
.zero 24
.size inputVec, 24
.hidden __dso_handle
.type _Z6letterB5cxx11,@object # @_Z6letterB5cxx11
.data
.globl _Z6letterB5cxx11
.p2align 3, 0x0
_Z6letterB5cxx11:
.quad _Z6letterB5cxx11+16
.quad 0 # 0x0
.zero 16
.size _Z6letterB5cxx11, 32
.type _Z5subFpB5cxx11,@object # @_Z5subFpB5cxx11
.globl _Z5subFpB5cxx11
.p2align 3, 0x0
_Z5subFpB5cxx11:
.quad _Z5subFpB5cxx11+16
.quad 0 # 0x0
.zero 16
.size _Z5subFpB5cxx11, 32
.type d_x,@object # @d_x
.local d_x
.comm d_x,8192,16
.type d_Xfp32,@object # @d_Xfp32
.local d_Xfp32
.comm d_Xfp32,8192,16
.type d_ix,@object # @d_ix
.local d_ix
.comm d_ix,8192,16
.type d_Xfp64,@object # @d_Xfp64
.local d_Xfp64
.comm d_Xfp64,16384,16
.type d_N,@object # @d_N
.local d_N
.comm d_N,4,4
.type _Z11printKernelv,@object # @_Z11printKernelv
.section .rodata,"a",@progbits
.globl _Z11printKernelv
.p2align 3, 0x0
_Z11printKernelv:
.quad _Z26__device_stub__printKernelv
.size _Z11printKernelv, 8
.type _Z15idctKernelFloatv,@object # @_Z15idctKernelFloatv
.globl _Z15idctKernelFloatv
.p2align 3, 0x0
_Z15idctKernelFloatv:
.quad _Z30__device_stub__idctKernelFloatv
.size _Z15idctKernelFloatv, 8
.type _Z14dctKernelFloatv,@object # @_Z14dctKernelFloatv
.globl _Z14dctKernelFloatv
.p2align 3, 0x0
_Z14dctKernelFloatv:
.quad _Z29__device_stub__dctKernelFloatv
.size _Z14dctKernelFloatv, 8
.type _Z15dctKernelDoublev,@object # @_Z15dctKernelDoublev
.globl _Z15dctKernelDoublev
.p2align 3, 0x0
_Z15dctKernelDoublev:
.quad _Z30__device_stub__dctKernelDoublev
.size _Z15dctKernelDoublev, 8
.type _ZL1N,@object # @_ZL1N
.p2align 2, 0x0
_ZL1N:
.long 2048 # 0x800
.size _ZL1N, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU clocks float accumulator: "
.size .L.str, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU clocks double accumulator: "
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU clocks idct float accumulator: "
.size .L.str.7, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11printKernelv"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15idctKernelFloatv"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14dctKernelFloatv"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15dctKernelDoublev"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "d_x"
.size .L__unnamed_5, 4
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "d_Xfp32"
.size .L__unnamed_6, 8
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "d_ix"
.size .L__unnamed_7, 5
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "d_Xfp64"
.size .L__unnamed_8, 8
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "d_N"
.size .L__unnamed_9, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_dct1d.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z26__device_stub__printKernelv
.addrsig_sym _Z30__device_stub__idctKernelFloatv
.addrsig_sym _Z29__device_stub__dctKernelFloatv
.addrsig_sym _Z30__device_stub__dctKernelDoublev
.addrsig_sym _GLOBAL__sub_I_dct1d.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym inputVec
.addrsig_sym __dso_handle
.addrsig_sym _Z6letterB5cxx11
.addrsig_sym _Z5subFpB5cxx11
.addrsig_sym d_x
.addrsig_sym d_Xfp32
.addrsig_sym d_ix
.addrsig_sym d_Xfp64
.addrsig_sym d_N
.addrsig_sym _Z11printKernelv
.addrsig_sym _Z15idctKernelFloatv
.addrsig_sym _Z14dctKernelFloatv
.addrsig_sym _Z15dctKernelDoublev
.addrsig_sym _ZL1N
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void oddevenSort(int *d_in,int size,int oe_flag,int &d_ch_flag){
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int p = 2*idx+oe_flag;
if(p+1<size){
if(d_in[p]>d_in[p+1]){
int temp = d_in[p];
d_in[p] = d_in[p+1];
d_in[p+1] = temp;
d_ch_flag = 1;
}
}
}
void init(int *p,const int size){
srand((unsigned int)time(NULL));
for(int i=0;i<size;i++){
p[i] = rand()%size;
}
}
void show(int *p,const int size){
for(int i=0;i<size;i++){
printf("%d ",p[i]);
}
printf("\n");
}
void bubbleSort(int *p,const int size){
for(int i=0;i<size-1;i++){
for(int j=0;j<size-i-1;j++){
if(p[j]>p[j+1]){
int temp = p[j];
p[j] = p[j+1];
p[j+1] = temp;
}
}
}
}
int main(){
int size = 10*1024;
int *h_in;
int *h_out;
h_in = (int *)malloc(size*sizeof(int));
h_out = (int *)malloc(size*sizeof(int));
init(h_in,size);
//show(h_in,size);
//printf("\n");
int *d_in;
int *d_ch_flag;
cudaMalloc((int **)&d_in,size*sizeof(int));
cudaMalloc((int **)&d_ch_flag,sizeof(int));
cudaMemcpy(d_in,h_in,size*sizeof(int),cudaMemcpyHostToDevice);
int oe_flag = 0;//判断当前进行排序的类型
int ch_flag = 1;//判断数组是否发生改变
dim3 block(10);
dim3 thread(1024/2);
time_t t_start = clock();
while(ch_flag||oe_flag){//偶排序和奇排序必须成对出现
ch_flag = 0;
cudaMemcpy(d_ch_flag,&ch_flag,sizeof(int),cudaMemcpyHostToDevice);
oddevenSort<<<block,thread>>>(d_in,size,oe_flag,d_ch_flag[0]);
cudaMemcpy(&ch_flag,d_ch_flag,sizeof(int),cudaMemcpyDeviceToHost);
oe_flag = 1^oe_flag;
}
time_t t_end = clock();
cudaMemcpy(h_out,d_in,size*sizeof(int),cudaMemcpyDeviceToHost);
//show(h_out,size);
printf("GPU time:%fms\n",difftime(t_end,t_start));
t_start = clock();
bubbleSort(h_in,size);
t_end = clock();
printf("CPU time:%fms\n",difftime(t_end,t_start));
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_ch_flag);
return 0;
} | code for sm_80
Function : _Z11oddevenSortPiiiRi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LEA R0, R0, c[0x0][0x16c], 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fc800078e08ff */
/*0050*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f04270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0120*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void oddevenSort(int *d_in,int size,int oe_flag,int &d_ch_flag){
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int p = 2*idx+oe_flag;
if(p+1<size){
if(d_in[p]>d_in[p+1]){
int temp = d_in[p];
d_in[p] = d_in[p+1];
d_in[p+1] = temp;
d_ch_flag = 1;
}
}
}
void init(int *p,const int size){
srand((unsigned int)time(NULL));
for(int i=0;i<size;i++){
p[i] = rand()%size;
}
}
void show(int *p,const int size){
for(int i=0;i<size;i++){
printf("%d ",p[i]);
}
printf("\n");
}
void bubbleSort(int *p,const int size){
for(int i=0;i<size-1;i++){
for(int j=0;j<size-i-1;j++){
if(p[j]>p[j+1]){
int temp = p[j];
p[j] = p[j+1];
p[j+1] = temp;
}
}
}
}
int main(){
int size = 10*1024;
int *h_in;
int *h_out;
h_in = (int *)malloc(size*sizeof(int));
h_out = (int *)malloc(size*sizeof(int));
init(h_in,size);
//show(h_in,size);
//printf("\n");
int *d_in;
int *d_ch_flag;
cudaMalloc((int **)&d_in,size*sizeof(int));
cudaMalloc((int **)&d_ch_flag,sizeof(int));
cudaMemcpy(d_in,h_in,size*sizeof(int),cudaMemcpyHostToDevice);
int oe_flag = 0;//判断当前进行排序的类型
int ch_flag = 1;//判断数组是否发生改变
dim3 block(10);
dim3 thread(1024/2);
time_t t_start = clock();
while(ch_flag||oe_flag){//偶排序和奇排序必须成对出现
ch_flag = 0;
cudaMemcpy(d_ch_flag,&ch_flag,sizeof(int),cudaMemcpyHostToDevice);
oddevenSort<<<block,thread>>>(d_in,size,oe_flag,d_ch_flag[0]);
cudaMemcpy(&ch_flag,d_ch_flag,sizeof(int),cudaMemcpyDeviceToHost);
oe_flag = 1^oe_flag;
}
time_t t_end = clock();
cudaMemcpy(h_out,d_in,size*sizeof(int),cudaMemcpyDeviceToHost);
//show(h_out,size);
printf("GPU time:%fms\n",difftime(t_end,t_start));
t_start = clock();
bubbleSort(h_in,size);
t_end = clock();
printf("CPU time:%fms\n",difftime(t_end,t_start));
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_ch_flag);
return 0;
} | .file "tmpxft_00074dfb_00000000-6_OddevenSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L3
movq %r12, %rbx
movslq %ebp, %rax
leaq (%r12,%rax,4), %r12
.L5:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4initPii, .-_Z4initPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z4showPii
.type _Z4showPii, @function
_Z4showPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L9
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L10:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
.L9:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4showPii, .-_Z4showPii
.globl _Z10bubbleSortPii
.type _Z10bubbleSortPii, @function
_Z10bubbleSortPii:
.LFB2059:
.cfi_startproc
endbr64
cmpl $1, %esi
jle .L13
leaq 4(%rdi), %r9
jmp .L15
.L16:
addq $4, %rax
cmpq %r8, %rax
je .L22
.L17:
movl (%rax), %edx
movl 4(%rax), %ecx
cmpl %ecx, %edx
jle .L16
movl %ecx, (%rax)
movl %edx, 4(%rax)
jmp .L16
.L22:
subl $1, %esi
cmpl $1, %esi
je .L13
.L15:
cmpl $1, %esi
jle .L23
movq %rdi, %rax
leal -2(%rsi), %edx
leaq (%r9,%rdx,4), %r8
jmp .L17
.L23:
subl $1, %esi
jmp .L15
.L13:
ret
.cfi_endproc
.LFE2059:
.size _Z10bubbleSortPii, .-_Z10bubbleSortPii
.globl _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
.type _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_, @function
_Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11oddevenSortPiiiRi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_, .-_Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
.globl _Z11oddevenSortPiiiRi
.type _Z11oddevenSortPiiiRi, @function
_Z11oddevenSortPiiiRi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11oddevenSortPiiiRi, .-_Z11oddevenSortPiiiRi
.section .rodata.str1.1
.LC2:
.string "GPU time:%fms\n"
.LC3:
.string "CPU time:%fms\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40960, %edi
call malloc@PLT
movq %rax, %r12
movl $40960, %edi
call malloc@PLT
movq %rax, %r13
movl $10240, %esi
movq %r12, %rdi
call _Z4initPii
leaq 16(%rsp), %rdi
movl $40960, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40960, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 12(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
call clock@PLT
movq %rax, %r14
cmpl $0, 12(%rsp)
je .L33
movl $0, %ebx
leaq 12(%rsp), %rbp
jmp .L35
.L34:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
xorl $1, %ebx
movl %ebx, %eax
orl 12(%rsp), %eax
je .L33
.L35:
movl $0, 12(%rsp)
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movq 24(%rsp), %rcx
movl %ebx, %edx
movl $10240, %esi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
jmp .L34
.L33:
call clock@PLT
movq %rax, %rbx
movl $2, %ecx
movl $40960, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r14, %rsi
movq %rbx, %rdi
call difftime@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $10240, %esi
movq %r12, %rdi
call _Z10bubbleSortPii
call clock@PLT
movq %rax, %rdi
movq %rbx, %rsi
call difftime@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11oddevenSortPiiiRi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11oddevenSortPiiiRi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void oddevenSort(int *d_in,int size,int oe_flag,int &d_ch_flag){
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int p = 2*idx+oe_flag;
if(p+1<size){
if(d_in[p]>d_in[p+1]){
int temp = d_in[p];
d_in[p] = d_in[p+1];
d_in[p+1] = temp;
d_ch_flag = 1;
}
}
}
void init(int *p,const int size){
srand((unsigned int)time(NULL));
for(int i=0;i<size;i++){
p[i] = rand()%size;
}
}
void show(int *p,const int size){
for(int i=0;i<size;i++){
printf("%d ",p[i]);
}
printf("\n");
}
void bubbleSort(int *p,const int size){
for(int i=0;i<size-1;i++){
for(int j=0;j<size-i-1;j++){
if(p[j]>p[j+1]){
int temp = p[j];
p[j] = p[j+1];
p[j+1] = temp;
}
}
}
}
int main(){
int size = 10*1024;
int *h_in;
int *h_out;
h_in = (int *)malloc(size*sizeof(int));
h_out = (int *)malloc(size*sizeof(int));
init(h_in,size);
//show(h_in,size);
//printf("\n");
int *d_in;
int *d_ch_flag;
cudaMalloc((int **)&d_in,size*sizeof(int));
cudaMalloc((int **)&d_ch_flag,sizeof(int));
cudaMemcpy(d_in,h_in,size*sizeof(int),cudaMemcpyHostToDevice);
int oe_flag = 0;//判断当前进行排序的类型
int ch_flag = 1;//判断数组是否发生改变
dim3 block(10);
dim3 thread(1024/2);
time_t t_start = clock();
while(ch_flag||oe_flag){//偶排序和奇排序必须成对出现
ch_flag = 0;
cudaMemcpy(d_ch_flag,&ch_flag,sizeof(int),cudaMemcpyHostToDevice);
oddevenSort<<<block,thread>>>(d_in,size,oe_flag,d_ch_flag[0]);
cudaMemcpy(&ch_flag,d_ch_flag,sizeof(int),cudaMemcpyDeviceToHost);
oe_flag = 1^oe_flag;
}
time_t t_end = clock();
cudaMemcpy(h_out,d_in,size*sizeof(int),cudaMemcpyDeviceToHost);
//show(h_out,size);
printf("GPU time:%fms\n",difftime(t_end,t_start));
t_start = clock();
bubbleSort(h_in,size);
t_end = clock();
printf("CPU time:%fms\n",difftime(t_end,t_start));
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_ch_flag);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void oddevenSort(int *d_in,int size,int oe_flag,int &d_ch_flag){
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int p = 2*idx+oe_flag;
if(p+1<size){
if(d_in[p]>d_in[p+1]){
int temp = d_in[p];
d_in[p] = d_in[p+1];
d_in[p+1] = temp;
d_ch_flag = 1;
}
}
}
void init(int *p,const int size){
srand((unsigned int)time(NULL));
for(int i=0;i<size;i++){
p[i] = rand()%size;
}
}
void show(int *p,const int size){
for(int i=0;i<size;i++){
printf("%d ",p[i]);
}
printf("\n");
}
void bubbleSort(int *p,const int size){
for(int i=0;i<size-1;i++){
for(int j=0;j<size-i-1;j++){
if(p[j]>p[j+1]){
int temp = p[j];
p[j] = p[j+1];
p[j+1] = temp;
}
}
}
}
int main(){
int size = 10*1024;
int *h_in;
int *h_out;
h_in = (int *)malloc(size*sizeof(int));
h_out = (int *)malloc(size*sizeof(int));
init(h_in,size);
//show(h_in,size);
//printf("\n");
int *d_in;
int *d_ch_flag;
hipMalloc((int **)&d_in,size*sizeof(int));
hipMalloc((int **)&d_ch_flag,sizeof(int));
hipMemcpy(d_in,h_in,size*sizeof(int),hipMemcpyHostToDevice);
int oe_flag = 0;//判断当前进行排序的类型
int ch_flag = 1;//判断数组是否发生改变
dim3 block(10);
dim3 thread(1024/2);
time_t t_start = clock();
while(ch_flag||oe_flag){//偶排序和奇排序必须成对出现
ch_flag = 0;
hipMemcpy(d_ch_flag,&ch_flag,sizeof(int),hipMemcpyHostToDevice);
oddevenSort<<<block,thread>>>(d_in,size,oe_flag,d_ch_flag[0]);
hipMemcpy(&ch_flag,d_ch_flag,sizeof(int),hipMemcpyDeviceToHost);
oe_flag = 1^oe_flag;
}
time_t t_end = clock();
hipMemcpy(h_out,d_in,size*sizeof(int),hipMemcpyDeviceToHost);
//show(h_out,size);
printf("GPU time:%fms\n",difftime(t_end,t_start));
t_start = clock();
bubbleSort(h_in,size);
t_end = clock();
printf("CPU time:%fms\n",difftime(t_end,t_start));
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_ch_flag);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void oddevenSort(int *d_in,int size,int oe_flag,int &d_ch_flag){
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int p = 2*idx+oe_flag;
if(p+1<size){
if(d_in[p]>d_in[p+1]){
int temp = d_in[p];
d_in[p] = d_in[p+1];
d_in[p+1] = temp;
d_ch_flag = 1;
}
}
}
void init(int *p,const int size){
srand((unsigned int)time(NULL));
for(int i=0;i<size;i++){
p[i] = rand()%size;
}
}
void show(int *p,const int size){
for(int i=0;i<size;i++){
printf("%d ",p[i]);
}
printf("\n");
}
void bubbleSort(int *p,const int size){
for(int i=0;i<size-1;i++){
for(int j=0;j<size-i-1;j++){
if(p[j]>p[j+1]){
int temp = p[j];
p[j] = p[j+1];
p[j+1] = temp;
}
}
}
}
int main(){
int size = 10*1024;
int *h_in;
int *h_out;
h_in = (int *)malloc(size*sizeof(int));
h_out = (int *)malloc(size*sizeof(int));
init(h_in,size);
//show(h_in,size);
//printf("\n");
int *d_in;
int *d_ch_flag;
hipMalloc((int **)&d_in,size*sizeof(int));
hipMalloc((int **)&d_ch_flag,sizeof(int));
hipMemcpy(d_in,h_in,size*sizeof(int),hipMemcpyHostToDevice);
int oe_flag = 0;//判断当前进行排序的类型
int ch_flag = 1;//判断数组是否发生改变
dim3 block(10);
dim3 thread(1024/2);
time_t t_start = clock();
while(ch_flag||oe_flag){//偶排序和奇排序必须成对出现
ch_flag = 0;
hipMemcpy(d_ch_flag,&ch_flag,sizeof(int),hipMemcpyHostToDevice);
oddevenSort<<<block,thread>>>(d_in,size,oe_flag,d_ch_flag[0]);
hipMemcpy(&ch_flag,d_ch_flag,sizeof(int),hipMemcpyDeviceToHost);
oe_flag = 1^oe_flag;
}
time_t t_end = clock();
hipMemcpy(h_out,d_in,size*sizeof(int),hipMemcpyDeviceToHost);
//show(h_out,size);
printf("GPU time:%fms\n",difftime(t_end,t_start));
t_start = clock();
bubbleSort(h_in,size);
t_end = clock();
printf("CPU time:%fms\n",difftime(t_end,t_start));
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_ch_flag);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11oddevenSortPiiiRi
.globl _Z11oddevenSortPiiiRi
.p2align 8
.type _Z11oddevenSortPiiiRi,@function
_Z11oddevenSortPiiiRi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_lshl_add_u32 v2, v1, 1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, 1, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 1
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
s_waitcnt lgkmcnt(0)
global_store_b32 v6, v7, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11oddevenSortPiiiRi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11oddevenSortPiiiRi, .Lfunc_end0-_Z11oddevenSortPiiiRi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11oddevenSortPiiiRi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11oddevenSortPiiiRi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void oddevenSort(int *d_in,int size,int oe_flag,int &d_ch_flag){
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int p = 2*idx+oe_flag;
if(p+1<size){
if(d_in[p]>d_in[p+1]){
int temp = d_in[p];
d_in[p] = d_in[p+1];
d_in[p+1] = temp;
d_ch_flag = 1;
}
}
}
void init(int *p,const int size){
srand((unsigned int)time(NULL));
for(int i=0;i<size;i++){
p[i] = rand()%size;
}
}
void show(int *p,const int size){
for(int i=0;i<size;i++){
printf("%d ",p[i]);
}
printf("\n");
}
void bubbleSort(int *p,const int size){
for(int i=0;i<size-1;i++){
for(int j=0;j<size-i-1;j++){
if(p[j]>p[j+1]){
int temp = p[j];
p[j] = p[j+1];
p[j+1] = temp;
}
}
}
}
int main(){
int size = 10*1024;
int *h_in;
int *h_out;
h_in = (int *)malloc(size*sizeof(int));
h_out = (int *)malloc(size*sizeof(int));
init(h_in,size);
//show(h_in,size);
//printf("\n");
int *d_in;
int *d_ch_flag;
hipMalloc((int **)&d_in,size*sizeof(int));
hipMalloc((int **)&d_ch_flag,sizeof(int));
hipMemcpy(d_in,h_in,size*sizeof(int),hipMemcpyHostToDevice);
int oe_flag = 0;//判断当前进行排序的类型
int ch_flag = 1;//判断数组是否发生改变
dim3 block(10);
dim3 thread(1024/2);
time_t t_start = clock();
while(ch_flag||oe_flag){//偶排序和奇排序必须成对出现
ch_flag = 0;
hipMemcpy(d_ch_flag,&ch_flag,sizeof(int),hipMemcpyHostToDevice);
oddevenSort<<<block,thread>>>(d_in,size,oe_flag,d_ch_flag[0]);
hipMemcpy(&ch_flag,d_ch_flag,sizeof(int),hipMemcpyDeviceToHost);
oe_flag = 1^oe_flag;
}
time_t t_end = clock();
hipMemcpy(h_out,d_in,size*sizeof(int),hipMemcpyDeviceToHost);
//show(h_out,size);
printf("GPU time:%fms\n",difftime(t_end,t_start));
t_start = clock();
bubbleSort(h_in,size);
t_end = clock();
printf("CPU time:%fms\n",difftime(t_end,t_start));
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_ch_flag);
return 0;
} | .text
.file "OddevenSort.hip"
.globl _Z26__device_stub__oddevenSortPiiiRi # -- Begin function _Z26__device_stub__oddevenSortPiiiRi
.p2align 4, 0x90
.type _Z26__device_stub__oddevenSortPiiiRi,@function
_Z26__device_stub__oddevenSortPiiiRi: # @_Z26__device_stub__oddevenSortPiiiRi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11oddevenSortPiiiRi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__oddevenSortPiiiRi, .Lfunc_end0-_Z26__device_stub__oddevenSortPiiiRi
.cfi_endproc
# -- End function
.globl _Z4initPii # -- Begin function _Z4initPii
.p2align 4, 0x90
.type _Z4initPii,@function
_Z4initPii: # @_Z4initPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4initPii, .Lfunc_end1-_Z4initPii
.cfi_endproc
# -- End function
.globl _Z4showPii # -- Begin function _Z4showPii
.p2align 4, 0x90
.type _Z4showPii,@function
_Z4showPii: # @_Z4showPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z4showPii, .Lfunc_end2-_Z4showPii
.cfi_endproc
# -- End function
.globl _Z10bubbleSortPii # -- Begin function _Z10bubbleSortPii
.p2align 4, 0x90
.type _Z10bubbleSortPii,@function
_Z10bubbleSortPii: # @_Z10bubbleSortPii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
cmpl $2, %esi
jl .LBB3_8
# %bb.1: # %.preheader.preheader
leal -1(%rsi), %eax
xorl %ecx, %ecx
movl %eax, %edx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incl %ecx
decl %edx
cmpl %eax, %ecx
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
movl %edx, %edx
movl %ecx, %r8d
subl %esi, %r8d
cmpl $-2, %r8d
jg .LBB3_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
xorl %r8d, %r8d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %r8
cmpq %r8, %rdx
je .LBB3_7
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdi,%r8,4), %r9d
movl 4(%rdi,%r8,4), %r10d
cmpl %r10d, %r9d
jle .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movl %r10d, (%rdi,%r8,4)
movl %r9d, 4(%rdi,%r8,4)
jmp .LBB3_6
.LBB3_8: # %._crit_edge24
retq
.Lfunc_end3:
.size _Z10bubbleSortPii, .Lfunc_end3-_Z10bubbleSortPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40960, %edi # imm = 0xA000
callq malloc
movq %rax, %rbx
movl $40960, %edi # imm = 0xA000
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
shll $11, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10240, %r14 # imm = 0x2800
jne .LBB4_1
# %bb.2: # %_Z4initPii.exit
leaq 16(%rsp), %rdi
movl $40960, %esi # imm = 0xA000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $40960, %edx # imm = 0xA000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $1, 4(%rsp)
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
cmpl $0, 4(%rsp)
je .LBB4_7
# %bb.3: # %.lr.ph
xorl %r15d, %r15d
movabsq $4294967306, %r12 # imm = 0x10000000A
leaq 4(%rsp), %r13
leaq 502(%r12), %rbp
leaq 112(%rsp), %r14
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_6: # in Loop: Header=BB4_4 Depth=1
movq 8(%rsp), %rsi
movl $4, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
xorl $1, %r15d
movl 4(%rsp), %eax
orl %r15d, %eax
je .LBB4_7
.LBB4_4: # =>This Inner Loop Header: Depth=1
movl $0, 4(%rsp)
movq 8(%rsp), %rdi
movl $4, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5: # in Loop: Header=BB4_4 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movl $10240, 28(%rsp) # imm = 0x2800
movl %r15d, 24(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z11oddevenSortPiiiRi, %edi
movq %r14, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_6
.LBB4_7: # %._crit_edge
callq clock
movq %rax, %r14
movq 16(%rsp), %rsi
movl $40960, %edx # imm = 0xA000
movq 40(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
callq difftime
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %r15d, %r15d
movl $10239, %r12d # imm = 0x27FF
callq clock
movq %rax, %r14
jmp .LBB4_8
.p2align 4, 0x90
.LBB4_12: # %._crit_edge.i
# in Loop: Header=BB4_8 Depth=1
incl %r15d
decq %r12
cmpl $10239, %r15d # imm = 0x27FF
je .LBB4_13
.LBB4_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
xorl %eax, %eax
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=2
incq %rax
cmpq %rax, %r12
je .LBB4_12
.LBB4_9: # %.lr.ph.i26
# Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rax,4), %ecx
movl 4(%rbx,%rax,4), %edx
cmpl %edx, %ecx
jle .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=2
movl %edx, (%rbx,%rax,4)
movl %ecx, 4(%rbx,%rax,4)
jmp .LBB4_11
.LBB4_13: # %_Z10bubbleSortPii.exit
callq clock
movq %rax, %rdi
movq %r14, %rsi
callq difftime
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11oddevenSortPiiiRi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11oddevenSortPiiiRi,@object # @_Z11oddevenSortPiiiRi
.section .rodata,"a",@progbits
.globl _Z11oddevenSortPiiiRi
.p2align 3, 0x0
_Z11oddevenSortPiiiRi:
.quad _Z26__device_stub__oddevenSortPiiiRi
.size _Z11oddevenSortPiiiRi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU time:%fms\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU time:%fms\n"
.size .L.str.3, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11oddevenSortPiiiRi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__oddevenSortPiiiRi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11oddevenSortPiiiRi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11oddevenSortPiiiRi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LEA R0, R0, c[0x0][0x16c], 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fc800078e08ff */
/*0050*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f04270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0120*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11oddevenSortPiiiRi
.globl _Z11oddevenSortPiiiRi
.p2align 8
.type _Z11oddevenSortPiiiRi,@function
_Z11oddevenSortPiiiRi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_lshl_add_u32 v2, v1, 1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, 1, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 1
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
s_waitcnt lgkmcnt(0)
global_store_b32 v6, v7, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11oddevenSortPiiiRi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11oddevenSortPiiiRi, .Lfunc_end0-_Z11oddevenSortPiiiRi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11oddevenSortPiiiRi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11oddevenSortPiiiRi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074dfb_00000000-6_OddevenSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L3
movq %r12, %rbx
movslq %ebp, %rax
leaq (%r12,%rax,4), %r12
.L5:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4initPii, .-_Z4initPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z4showPii
.type _Z4showPii, @function
_Z4showPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L9
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L10:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
.L9:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4showPii, .-_Z4showPii
.globl _Z10bubbleSortPii
.type _Z10bubbleSortPii, @function
_Z10bubbleSortPii:
.LFB2059:
.cfi_startproc
endbr64
cmpl $1, %esi
jle .L13
leaq 4(%rdi), %r9
jmp .L15
.L16:
addq $4, %rax
cmpq %r8, %rax
je .L22
.L17:
movl (%rax), %edx
movl 4(%rax), %ecx
cmpl %ecx, %edx
jle .L16
movl %ecx, (%rax)
movl %edx, 4(%rax)
jmp .L16
.L22:
subl $1, %esi
cmpl $1, %esi
je .L13
.L15:
cmpl $1, %esi
jle .L23
movq %rdi, %rax
leal -2(%rsi), %edx
leaq (%r9,%rdx,4), %r8
jmp .L17
.L23:
subl $1, %esi
jmp .L15
.L13:
ret
.cfi_endproc
.LFE2059:
.size _Z10bubbleSortPii, .-_Z10bubbleSortPii
.globl _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
.type _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_, @function
_Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11oddevenSortPiiiRi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_, .-_Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
.globl _Z11oddevenSortPiiiRi
.type _Z11oddevenSortPiiiRi, @function
_Z11oddevenSortPiiiRi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11oddevenSortPiiiRi, .-_Z11oddevenSortPiiiRi
.section .rodata.str1.1
.LC2:
.string "GPU time:%fms\n"
.LC3:
.string "CPU time:%fms\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40960, %edi
call malloc@PLT
movq %rax, %r12
movl $40960, %edi
call malloc@PLT
movq %rax, %r13
movl $10240, %esi
movq %r12, %rdi
call _Z4initPii
leaq 16(%rsp), %rdi
movl $40960, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40960, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 12(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
call clock@PLT
movq %rax, %r14
cmpl $0, 12(%rsp)
je .L33
movl $0, %ebx
leaq 12(%rsp), %rbp
jmp .L35
.L34:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
xorl $1, %ebx
movl %ebx, %eax
orl 12(%rsp), %eax
je .L33
.L35:
movl $0, 12(%rsp)
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movq 24(%rsp), %rcx
movl %ebx, %edx
movl $10240, %esi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11oddevenSortPiiiRiPiiiS_
jmp .L34
.L33:
call clock@PLT
movq %rax, %rbx
movl $2, %ecx
movl $40960, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r14, %rsi
movq %rbx, %rdi
call difftime@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $10240, %esi
movq %r12, %rdi
call _Z10bubbleSortPii
call clock@PLT
movq %rax, %rdi
movq %rbx, %rsi
call difftime@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11oddevenSortPiiiRi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11oddevenSortPiiiRi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "OddevenSort.hip"
.globl _Z26__device_stub__oddevenSortPiiiRi # -- Begin function _Z26__device_stub__oddevenSortPiiiRi
.p2align 4, 0x90
.type _Z26__device_stub__oddevenSortPiiiRi,@function
_Z26__device_stub__oddevenSortPiiiRi: # @_Z26__device_stub__oddevenSortPiiiRi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11oddevenSortPiiiRi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__oddevenSortPiiiRi, .Lfunc_end0-_Z26__device_stub__oddevenSortPiiiRi
.cfi_endproc
# -- End function
.globl _Z4initPii # -- Begin function _Z4initPii
.p2align 4, 0x90
.type _Z4initPii,@function
_Z4initPii: # @_Z4initPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4initPii, .Lfunc_end1-_Z4initPii
.cfi_endproc
# -- End function
.globl _Z4showPii # -- Begin function _Z4showPii
.p2align 4, 0x90
.type _Z4showPii,@function
_Z4showPii: # @_Z4showPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z4showPii, .Lfunc_end2-_Z4showPii
.cfi_endproc
# -- End function
.globl _Z10bubbleSortPii # -- Begin function _Z10bubbleSortPii
.p2align 4, 0x90
.type _Z10bubbleSortPii,@function
_Z10bubbleSortPii: # @_Z10bubbleSortPii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
cmpl $2, %esi
jl .LBB3_8
# %bb.1: # %.preheader.preheader
leal -1(%rsi), %eax
xorl %ecx, %ecx
movl %eax, %edx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incl %ecx
decl %edx
cmpl %eax, %ecx
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
movl %edx, %edx
movl %ecx, %r8d
subl %esi, %r8d
cmpl $-2, %r8d
jg .LBB3_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
xorl %r8d, %r8d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %r8
cmpq %r8, %rdx
je .LBB3_7
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdi,%r8,4), %r9d
movl 4(%rdi,%r8,4), %r10d
cmpl %r10d, %r9d
jle .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movl %r10d, (%rdi,%r8,4)
movl %r9d, 4(%rdi,%r8,4)
jmp .LBB3_6
.LBB3_8: # %._crit_edge24
retq
.Lfunc_end3:
.size _Z10bubbleSortPii, .Lfunc_end3-_Z10bubbleSortPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40960, %edi # imm = 0xA000
callq malloc
movq %rax, %rbx
movl $40960, %edi # imm = 0xA000
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
shll $11, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10240, %r14 # imm = 0x2800
jne .LBB4_1
# %bb.2: # %_Z4initPii.exit
leaq 16(%rsp), %rdi
movl $40960, %esi # imm = 0xA000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $40960, %edx # imm = 0xA000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $1, 4(%rsp)
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
cmpl $0, 4(%rsp)
je .LBB4_7
# %bb.3: # %.lr.ph
xorl %r15d, %r15d
movabsq $4294967306, %r12 # imm = 0x10000000A
leaq 4(%rsp), %r13
leaq 502(%r12), %rbp
leaq 112(%rsp), %r14
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_6: # in Loop: Header=BB4_4 Depth=1
movq 8(%rsp), %rsi
movl $4, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
xorl $1, %r15d
movl 4(%rsp), %eax
orl %r15d, %eax
je .LBB4_7
.LBB4_4: # =>This Inner Loop Header: Depth=1
movl $0, 4(%rsp)
movq 8(%rsp), %rdi
movl $4, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5: # in Loop: Header=BB4_4 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movl $10240, 28(%rsp) # imm = 0x2800
movl %r15d, 24(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z11oddevenSortPiiiRi, %edi
movq %r14, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_6
.LBB4_7: # %._crit_edge
callq clock
movq %rax, %r14
movq 16(%rsp), %rsi
movl $40960, %edx # imm = 0xA000
movq 40(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
callq difftime
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %r15d, %r15d
movl $10239, %r12d # imm = 0x27FF
callq clock
movq %rax, %r14
jmp .LBB4_8
.p2align 4, 0x90
.LBB4_12: # %._crit_edge.i
# in Loop: Header=BB4_8 Depth=1
incl %r15d
decq %r12
cmpl $10239, %r15d # imm = 0x27FF
je .LBB4_13
.LBB4_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
xorl %eax, %eax
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=2
incq %rax
cmpq %rax, %r12
je .LBB4_12
.LBB4_9: # %.lr.ph.i26
# Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rax,4), %ecx
movl 4(%rbx,%rax,4), %edx
cmpl %edx, %ecx
jle .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=2
movl %edx, (%rbx,%rax,4)
movl %ecx, 4(%rbx,%rax,4)
jmp .LBB4_11
.LBB4_13: # %_Z10bubbleSortPii.exit
callq clock
movq %rax, %rdi
movq %r14, %rsi
callq difftime
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11oddevenSortPiiiRi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11oddevenSortPiiiRi,@object # @_Z11oddevenSortPiiiRi
.section .rodata,"a",@progbits
.globl _Z11oddevenSortPiiiRi
.p2align 3, 0x0
_Z11oddevenSortPiiiRi:
.quad _Z26__device_stub__oddevenSortPiiiRi
.size _Z11oddevenSortPiiiRi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU time:%fms\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU time:%fms\n"
.size .L.str.3, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11oddevenSortPiiiRi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__oddevenSortPiiiRi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11oddevenSortPiiiRi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "mat-rvect-add.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MatRvectAdd::MatRvectAdd(Op* left, Op* right)
: Op("mat_rvect_add", left->shape_get(), {left, right})
{}
void MatRvectAdd::compile()
{
auto& g = Graph::instance();
auto& cleft = g.compiled(preds()[0]);
auto& cright = g.compiled(preds()[1]);
std::size_t n = cleft.out_shape[0];
std::size_t p = cleft.out_shape[1];
Shape out_shape({int(n), int(p)});
dbl_t* out_data = tensor_alloc(out_shape.total());
auto out_node = rt::Node::op_mat_rvect_add(cleft.out_data, cright.out_data, out_data,
n, p, {cleft.out_node, cright.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "mat-rvect-add.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MatRvectAdd::MatRvectAdd(Op* left, Op* right)
: Op("mat_rvect_add", left->shape_get(), {left, right})
{}
void MatRvectAdd::compile()
{
auto& g = Graph::instance();
auto& cleft = g.compiled(preds()[0]);
auto& cright = g.compiled(preds()[1]);
std::size_t n = cleft.out_shape[0];
std::size_t p = cleft.out_shape[1];
Shape out_shape({int(n), int(p)});
dbl_t* out_data = tensor_alloc(out_shape.total());
auto out_node = rt::Node::op_mat_rvect_add(cleft.out_data, cright.out_data, out_data,
n, p, {cleft.out_node, cright.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .file "tmpxft_000b0f6e_00000000-6_mat-rvect-add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops11MatRvectAddD2Ev,"axG",@progbits,_ZN3ops11MatRvectAddD5Ev,comdat
.align 2
.weak _ZN3ops11MatRvectAddD2Ev
.type _ZN3ops11MatRvectAddD2Ev, @function
_ZN3ops11MatRvectAddD2Ev:
.LFB5662:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZN3ops11MatRvectAddD2Ev, .-_ZN3ops11MatRvectAddD2Ev
.weak _ZN3ops11MatRvectAddD1Ev
.set _ZN3ops11MatRvectAddD1Ev,_ZN3ops11MatRvectAddD2Ev
.section .text._ZN3ops11MatRvectAddD0Ev,"axG",@progbits,_ZN3ops11MatRvectAddD5Ev,comdat
.align 2
.weak _ZN3ops11MatRvectAddD0Ev
.type _ZN3ops11MatRvectAddD0Ev, @function
_ZN3ops11MatRvectAddD0Ev:
.LFB5664:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5664:
.size _ZN3ops11MatRvectAddD0Ev, .-_ZN3ops11MatRvectAddD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4959:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4959:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4982:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4982:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.type _ZN3ops11MatRvectAddC2EPNS_2OpES2_, @function
_ZN3ops11MatRvectAddC2EPNS_2OpES2_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, (%rsp)
leaq 16(%rax), %rdx
movq %rdx, 16(%rsp)
movq %rbx, (%rax)
movq %r12, 8(%rax)
movq %rdx, 8(%rsp)
movq %rbx, %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
.LEHE1:
movq %rax, %rdx
leaq 64(%rsp), %rsi
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movabsq $7162261016002453869, %rax
movq %rax, 80(%rsp)
movabsq $7234013964066317686, %rax
movq %rax, 85(%rsp)
movq $13, 72(%rsp)
movb $0, 93(%rsp)
movq %rsp, %rcx
leaq 32(%rsp), %r8
movq %rbp, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
jmp .L53
.L49:
endbr64
movq %rax, %rbx
movq (%rsp), %rdi
movq 16(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L39
call _ZdlPvm@PLT
.L39:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L53:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L40
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L40:
movq (%rsp), %rdi
testq %rdi, %rdi
je .L41
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L41:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L42
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L42:
leaq 16+_ZTVN3ops11MatRvectAddE(%rip), %rax
movq %rax, 0(%rbp)
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L44:
movq %rsp, %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L39
.L47:
endbr64
movq %rax, %rbx
jmp .L44
.L45:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L49-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L47-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L48-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops11MatRvectAddC2EPNS_2OpES2_, .-_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.globl _ZN3ops11MatRvectAddC1EPNS_2OpES2_
.set _ZN3ops11MatRvectAddC1EPNS_2OpES2_,_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5173:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L58
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L58:
ret
.cfi_endproc
.LFE5173:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops11MatRvectAdd7compileEv
.type _ZN3ops11MatRvectAdd7compileEv, @function
_ZN3ops11MatRvectAdd7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -152(%rbp)
leaq -80(%rbp), %rdi
movq %r12, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L62
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L62:
leaq -80(%rbp), %rdi
movq %r12, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq -152(%rbp), %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE7:
movq %rax, %r14
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L63
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L63:
leaq 64(%rbx), %r13
movl $0, %esi
movq %r13, %rdi
.LEHB8:
call _ZNK3ops5ShapeixEm@PLT
movl %eax, %r15d
cltq
movq %rax, -160(%rbp)
movl $1, %esi
movq %r13, %rdi
call _ZNK3ops5ShapeixEm@PLT
.LEHE8:
movslq %eax, %rcx
movq %rcx, -168(%rbp)
salq $32, %rax
movl %r15d, %r13d
orq %rax, %r13
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB9:
call _Znwm@PLT
.LEHE9:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
leaq -80(%rbp), %rsi
leaq -144(%rbp), %rdi
.LEHB10:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE10:
jmp .L108
.L99:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L66
call _ZdlPvm@PLT
.L66:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L108:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L68
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L68:
leaq -144(%rbp), %rdi
.LEHB12:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %rdi
call _Z12tensor_allocm@PLT
.LEHE12:
movq %rax, %r13
movq 56(%rbx), %rax
movq %rax, -176(%rbp)
movq 56(%r14), %r15
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq -176(%rbp), %rcx
movq %rcx, (%rax)
movq %r15, 8(%rax)
movq %rdx, -72(%rbp)
movq 88(%r14), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r9
movq -168(%rbp), %r8
movq -160(%rbp), %rcx
movq %r13, %rdx
.LEHB14:
call _ZN2rt4Node16op_mat_rvect_addEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE14:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L72
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L72:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB15:
call _Znwm@PLT
.LEHE15:
jmp .L109
.L100:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L71:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L91
call __stack_chk_fail@PLT
.L109:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB16:
call _Znwm@PLT
.LEHE16:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r13
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r12, %rsi
movq -152(%rbp), %rdi
.LEHB17:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE17:
jmp .L110
.L101:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L71
call _ZdlPvm@PLT
jmp .L71
.L110:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L79
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L79:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L80
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L80:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L61
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L61:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L111
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L102:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L78:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L71
call _ZdlPvm@PLT
jmp .L71
.L93:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L83
call __stack_chk_fail@PLT
.L83:
movq %rbx, %rdi
.LEHB18:
call _Unwind_Resume@PLT
.L94:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L85
call __stack_chk_fail@PLT
.L85:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L95:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L87
call __stack_chk_fail@PLT
.L87:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L97:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L71
.L98:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L78
.L96:
endbr64
movq %rax, %rbx
jmp .L71
.L91:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE18:
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L93-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L94-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L99-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L95-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L96-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 .L100-.LFB4617
.uleb128 0
.uleb128 .LEHB14-.LFB4617
.uleb128 .LEHE14-.LEHB14
.uleb128 .L97-.LFB4617
.uleb128 0
.uleb128 .LEHB15-.LFB4617
.uleb128 .LEHE15-.LEHB15
.uleb128 .L101-.LFB4617
.uleb128 0
.uleb128 .LEHB16-.LFB4617
.uleb128 .LEHE16-.LEHB16
.uleb128 .L102-.LFB4617
.uleb128 0
.uleb128 .LEHB17-.LFB4617
.uleb128 .LEHE17-.LEHB17
.uleb128 .L98-.LFB4617
.uleb128 0
.uleb128 .LEHB18-.LFB4617
.uleb128 .LEHE18-.LEHB18
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops11MatRvectAdd7compileEv, .-_ZN3ops11MatRvectAdd7compileEv
.weak _ZTSN3ops11MatRvectAddE
.section .rodata._ZTSN3ops11MatRvectAddE,"aG",@progbits,_ZTSN3ops11MatRvectAddE,comdat
.align 16
.type _ZTSN3ops11MatRvectAddE, @object
.size _ZTSN3ops11MatRvectAddE, 20
_ZTSN3ops11MatRvectAddE:
.string "N3ops11MatRvectAddE"
.weak _ZTIN3ops11MatRvectAddE
.section .data.rel.ro._ZTIN3ops11MatRvectAddE,"awG",@progbits,_ZTIN3ops11MatRvectAddE,comdat
.align 8
.type _ZTIN3ops11MatRvectAddE, @object
.size _ZTIN3ops11MatRvectAddE, 24
_ZTIN3ops11MatRvectAddE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops11MatRvectAddE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops11MatRvectAddE
.section .data.rel.ro._ZTVN3ops11MatRvectAddE,"awG",@progbits,_ZTVN3ops11MatRvectAddE,comdat
.align 8
.type _ZTVN3ops11MatRvectAddE, @object
.size _ZTVN3ops11MatRvectAddE, 48
_ZTVN3ops11MatRvectAddE:
.quad 0
.quad _ZTIN3ops11MatRvectAddE
.quad _ZN3ops11MatRvectAddD1Ev
.quad _ZN3ops11MatRvectAddD0Ev
.quad _ZN3ops11MatRvectAdd7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "mat-rvect-add.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MatRvectAdd::MatRvectAdd(Op* left, Op* right)
: Op("mat_rvect_add", left->shape_get(), {left, right})
{}
void MatRvectAdd::compile()
{
auto& g = Graph::instance();
auto& cleft = g.compiled(preds()[0]);
auto& cright = g.compiled(preds()[1]);
std::size_t n = cleft.out_shape[0];
std::size_t p = cleft.out_shape[1];
Shape out_shape({int(n), int(p)});
dbl_t* out_data = tensor_alloc(out_shape.total());
auto out_node = rt::Node::op_mat_rvect_add(cleft.out_data, cright.out_data, out_data,
n, p, {cleft.out_node, cright.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | #include <hip/hip_runtime.h>
#include "mat-rvect-add.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MatRvectAdd::MatRvectAdd(Op* left, Op* right)
: Op("mat_rvect_add", left->shape_get(), {left, right})
{}
void MatRvectAdd::compile()
{
auto& g = Graph::instance();
auto& cleft = g.compiled(preds()[0]);
auto& cright = g.compiled(preds()[1]);
std::size_t n = cleft.out_shape[0];
std::size_t p = cleft.out_shape[1];
Shape out_shape({int(n), int(p)});
dbl_t* out_data = tensor_alloc(out_shape.total());
auto out_node = rt::Node::op_mat_rvect_add(cleft.out_data, cright.out_data, out_data,
n, p, {cleft.out_node, cright.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "mat-rvect-add.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MatRvectAdd::MatRvectAdd(Op* left, Op* right)
: Op("mat_rvect_add", left->shape_get(), {left, right})
{}
void MatRvectAdd::compile()
{
auto& g = Graph::instance();
auto& cleft = g.compiled(preds()[0]);
auto& cright = g.compiled(preds()[1]);
std::size_t n = cleft.out_shape[0];
std::size_t p = cleft.out_shape[1];
Shape out_shape({int(n), int(p)});
dbl_t* out_data = tensor_alloc(out_shape.total());
auto out_node = rt::Node::op_mat_rvect_add(cleft.out_data, cright.out_data, out_data,
n, p, {cleft.out_node, cright.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "mat-rvect-add.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MatRvectAdd::MatRvectAdd(Op* left, Op* right)
: Op("mat_rvect_add", left->shape_get(), {left, right})
{}
void MatRvectAdd::compile()
{
auto& g = Graph::instance();
auto& cleft = g.compiled(preds()[0]);
auto& cright = g.compiled(preds()[1]);
std::size_t n = cleft.out_shape[0];
std::size_t p = cleft.out_shape[1];
Shape out_shape({int(n), int(p)});
dbl_t* out_data = tensor_alloc(out_shape.total());
auto out_node = rt::Node::op_mat_rvect_add(cleft.out_data, cright.out_data, out_data,
n, p, {cleft.out_node, cright.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.file "mat-rvect-add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops11MatRvectAddC2EPNS_2OpES2_,@function
_ZN3ops11MatRvectAddC2EPNS_2OpES2_: # @_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
movabsq $7162261016002453869, %rax # imm = 0x636576725F74616D
movq %rax, 48(%rsp)
movabsq $7234013964066317686, %rax # imm = 0x6464615F74636576
movq %rax, 53(%rsp)
movq $13, 40(%rsp)
movb $0, 61(%rsp)
.Ltmp0:
movq %rsi, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r12, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
callq _ZdlPv
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops11MatRvectAddE+16, (%rbx)
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
jmp .LBB0_14
.LBB0_10:
.Ltmp5:
movq %rax, %rbx
.LBB0_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_16
# %bb.15:
callq _ZdlPv
jmp .LBB0_16
.LBB0_11:
.Ltmp2:
movq %rax, %rbx
.LBB0_16: # %.body
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_18
# %bb.17: # %.critedge.i.i23
callq _ZdlPv
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops11MatRvectAddC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops11MatRvectAdd7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops11MatRvectAdd7compileEv
.p2align 4, 0x90
.type _ZN3ops11MatRvectAdd7compileEv,@function
_ZN3ops11MatRvectAdd7compileEv: # @_ZN3ops11MatRvectAdd7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
callq _ZN3ops5Graph8instanceEv
movq %rax, %r12
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 48(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %r12, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r15
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 48(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %r12, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, %rbp
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit47
leaq 64(%r15), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, %r13d
movl $1, %esi
movq %rbx, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp15:
movl $8, %edi
callq _Znwm
.Ltmp16:
# %bb.7: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 16(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 32(%rsp)
movl %r13d, (%rax)
movl %ebx, 76(%rsp) # 4-byte Spill
movl %ebx, 4(%rax)
movq %rcx, 24(%rsp)
.Ltmp18:
leaq 48(%rsp), %rdi
leaq 16(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp19:
# %bb.8:
movq %r12, 136(%rsp) # 8-byte Spill
movq %r14, 144(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_10
# %bb.9:
callq _ZdlPv
.LBB1_10: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.Ltmp21:
movl %r13d, %ebx
leaq 48(%rsp), %rdi
callq _ZNK3ops5Shape5totalEv
.Ltmp22:
# %bb.11:
movslq %eax, %rdi
.Ltmp23:
callq _Z12tensor_allocm
.Ltmp24:
# %bb.12:
movq %rax, %r12
movq 88(%r15), %r14
movq 88(%rbp), %r13
movq 56(%r15), %r15
movq 56(%rbp), %rbp
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp26:
movl $16, %edi
callq _Znwm
.Ltmp27:
# %bb.13: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movslq %ebx, %rcx
movslq 76(%rsp), %r8 # 4-byte Folded Reload
movq %rax, 16(%rsp)
movq %rax, %rdx
addq $16, %rdx
movq %rdx, 32(%rsp)
movq %r15, (%rax)
movq %rbp, 8(%rax)
movq %rdx, 24(%rsp)
.Ltmp29:
leaq 16(%rsp), %r9
movq %r14, %rdi
movq %r13, %rsi
movq %r12, %rdx
callq _ZN2rt4Node16op_mat_rvect_addEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp30:
# %bb.14:
movq %rax, %rbx
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_16
# %bb.15:
callq _ZdlPv
.LBB1_16: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp32:
movl $8, %edi
callq _Znwm
.Ltmp33:
# %bb.17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit59
movq %rax, 112(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 128(%rsp)
movq %rbx, (%rax)
movq %rcx, 120(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp35:
movl $8, %edi
callq _Znwm
.Ltmp36:
# %bb.18: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r12, (%rax)
movq %rcx, 88(%rsp)
.Ltmp38:
movq %r12, (%rsp)
leaq 112(%rsp), %rdx
leaq 80(%rsp), %rcx
leaq 48(%rsp), %r9
movq 136(%rsp), %rdi # 8-byte Reload
movq 144(%rsp), %rsi # 8-byte Reload
movq %rbx, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp39:
# %bb.19:
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_21
# %bb.20:
callq _ZdlPv
.LBB1_21: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZdlPv
.LBB1_23: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit67
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_25
# %bb.24:
callq _ZdlPv
.LBB1_25: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 208
.Ltmp40:
jmp .LBB1_28
.LBB1_27:
.Ltmp37:
.LBB1_28:
movq %rax, %rbx
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_31
# %bb.29: # %.body61.sink.split
callq _ZdlPv
jmp .LBB1_31
.LBB1_30:
.Ltmp34:
movq %rax, %rbx
.LBB1_31: # %.body61
movq 112(%rsp), %rdi
jmp .LBB1_35
.LBB1_32:
.Ltmp31:
jmp .LBB1_34
.LBB1_33:
.Ltmp28:
.LBB1_34:
movq %rax, %rbx
movq 16(%rsp), %rdi
.LBB1_35: # %.body61
testq %rdi, %rdi
je .LBB1_44
# %bb.36:
callq _ZdlPv
jmp .LBB1_44
.LBB1_37:
.Ltmp20:
jmp .LBB1_39
.LBB1_38:
.Ltmp17:
.LBB1_39:
movq %rax, %rbx
movq 16(%rsp), %rdi
jmp .LBB1_45
.LBB1_40:
.Ltmp14:
jmp .LBB1_43
.LBB1_41:
.Ltmp11:
jmp .LBB1_43
.LBB1_42:
.Ltmp25:
.LBB1_43: # %.body57
movq %rax, %rbx
.LBB1_44: # %.body57
movq 48(%rsp), %rdi
.LBB1_45: # %.body57
testq %rdi, %rdi
je .LBB1_47
# %bb.46:
callq _ZdlPv
.LBB1_47:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops11MatRvectAdd7compileEv, .Lfunc_end1-_ZN3ops11MatRvectAdd7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin1 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin1 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin1 # >> Call Site 14 <<
.uleb128 .Lfunc_end1-.Ltmp39 # Call between .Ltmp39 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops11MatRvectAddD0Ev,"axG",@progbits,_ZN3ops11MatRvectAddD0Ev,comdat
.weak _ZN3ops11MatRvectAddD0Ev # -- Begin function _ZN3ops11MatRvectAddD0Ev
.p2align 4, 0x90
.type _ZN3ops11MatRvectAddD0Ev,@function
_ZN3ops11MatRvectAddD0Ev: # @_ZN3ops11MatRvectAddD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops11MatRvectAddD0Ev, .Lfunc_end3-_ZN3ops11MatRvectAddD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "mat_rvect_add"
.size .L.str, 14
.type _ZTVN3ops11MatRvectAddE,@object # @_ZTVN3ops11MatRvectAddE
.section .rodata,"a",@progbits
.globl _ZTVN3ops11MatRvectAddE
.p2align 3, 0x0
_ZTVN3ops11MatRvectAddE:
.quad 0
.quad _ZTIN3ops11MatRvectAddE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops11MatRvectAddD0Ev
.quad _ZN3ops11MatRvectAdd7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops11MatRvectAddE, 48
.type _ZTSN3ops11MatRvectAddE,@object # @_ZTSN3ops11MatRvectAddE
.globl _ZTSN3ops11MatRvectAddE
_ZTSN3ops11MatRvectAddE:
.asciz "N3ops11MatRvectAddE"
.size _ZTSN3ops11MatRvectAddE, 20
.type _ZTIN3ops11MatRvectAddE,@object # @_ZTIN3ops11MatRvectAddE
.globl _ZTIN3ops11MatRvectAddE
.p2align 3, 0x0
_ZTIN3ops11MatRvectAddE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops11MatRvectAddE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops11MatRvectAddE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops11MatRvectAddC1EPNS_2OpES2_
.type _ZN3ops11MatRvectAddC1EPNS_2OpES2_,@function
.set _ZN3ops11MatRvectAddC1EPNS_2OpES2_, _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops11MatRvectAddE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops11MatRvectAddE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b0f6e_00000000-6_mat-rvect-add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops11MatRvectAddD2Ev,"axG",@progbits,_ZN3ops11MatRvectAddD5Ev,comdat
.align 2
.weak _ZN3ops11MatRvectAddD2Ev
.type _ZN3ops11MatRvectAddD2Ev, @function
_ZN3ops11MatRvectAddD2Ev:
.LFB5662:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZN3ops11MatRvectAddD2Ev, .-_ZN3ops11MatRvectAddD2Ev
.weak _ZN3ops11MatRvectAddD1Ev
.set _ZN3ops11MatRvectAddD1Ev,_ZN3ops11MatRvectAddD2Ev
.section .text._ZN3ops11MatRvectAddD0Ev,"axG",@progbits,_ZN3ops11MatRvectAddD5Ev,comdat
.align 2
.weak _ZN3ops11MatRvectAddD0Ev
.type _ZN3ops11MatRvectAddD0Ev, @function
_ZN3ops11MatRvectAddD0Ev:
.LFB5664:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5664:
.size _ZN3ops11MatRvectAddD0Ev, .-_ZN3ops11MatRvectAddD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4959:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4959:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4982:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4982:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.type _ZN3ops11MatRvectAddC2EPNS_2OpES2_, @function
_ZN3ops11MatRvectAddC2EPNS_2OpES2_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, (%rsp)
leaq 16(%rax), %rdx
movq %rdx, 16(%rsp)
movq %rbx, (%rax)
movq %r12, 8(%rax)
movq %rdx, 8(%rsp)
movq %rbx, %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
.LEHE1:
movq %rax, %rdx
leaq 64(%rsp), %rsi
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movabsq $7162261016002453869, %rax
movq %rax, 80(%rsp)
movabsq $7234013964066317686, %rax
movq %rax, 85(%rsp)
movq $13, 72(%rsp)
movb $0, 93(%rsp)
movq %rsp, %rcx
leaq 32(%rsp), %r8
movq %rbp, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
jmp .L53
.L49:
endbr64
movq %rax, %rbx
movq (%rsp), %rdi
movq 16(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L39
call _ZdlPvm@PLT
.L39:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L53:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L40
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L40:
movq (%rsp), %rdi
testq %rdi, %rdi
je .L41
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L41:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L42
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L42:
leaq 16+_ZTVN3ops11MatRvectAddE(%rip), %rax
movq %rax, 0(%rbp)
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L44:
movq %rsp, %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L39
.L47:
endbr64
movq %rax, %rbx
jmp .L44
.L45:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L49-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L47-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L48-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops11MatRvectAddC2EPNS_2OpES2_, .-_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.globl _ZN3ops11MatRvectAddC1EPNS_2OpES2_
.set _ZN3ops11MatRvectAddC1EPNS_2OpES2_,_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5173:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L58
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L58:
ret
.cfi_endproc
.LFE5173:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops11MatRvectAdd7compileEv
.type _ZN3ops11MatRvectAdd7compileEv, @function
_ZN3ops11MatRvectAdd7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -152(%rbp)
leaq -80(%rbp), %rdi
movq %r12, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L62
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L62:
leaq -80(%rbp), %rdi
movq %r12, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq -152(%rbp), %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE7:
movq %rax, %r14
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L63
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L63:
leaq 64(%rbx), %r13
movl $0, %esi
movq %r13, %rdi
.LEHB8:
call _ZNK3ops5ShapeixEm@PLT
movl %eax, %r15d
cltq
movq %rax, -160(%rbp)
movl $1, %esi
movq %r13, %rdi
call _ZNK3ops5ShapeixEm@PLT
.LEHE8:
movslq %eax, %rcx
movq %rcx, -168(%rbp)
salq $32, %rax
movl %r15d, %r13d
orq %rax, %r13
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB9:
call _Znwm@PLT
.LEHE9:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
leaq -80(%rbp), %rsi
leaq -144(%rbp), %rdi
.LEHB10:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE10:
jmp .L108
.L99:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L66
call _ZdlPvm@PLT
.L66:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L108:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L68
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L68:
leaq -144(%rbp), %rdi
.LEHB12:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %rdi
call _Z12tensor_allocm@PLT
.LEHE12:
movq %rax, %r13
movq 56(%rbx), %rax
movq %rax, -176(%rbp)
movq 56(%r14), %r15
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq -176(%rbp), %rcx
movq %rcx, (%rax)
movq %r15, 8(%rax)
movq %rdx, -72(%rbp)
movq 88(%r14), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r9
movq -168(%rbp), %r8
movq -160(%rbp), %rcx
movq %r13, %rdx
.LEHB14:
call _ZN2rt4Node16op_mat_rvect_addEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE14:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L72
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L72:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB15:
call _Znwm@PLT
.LEHE15:
jmp .L109
.L100:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L71:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L91
call __stack_chk_fail@PLT
.L109:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB16:
call _Znwm@PLT
.LEHE16:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r13
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r12, %rsi
movq -152(%rbp), %rdi
.LEHB17:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE17:
jmp .L110
.L101:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L71
call _ZdlPvm@PLT
jmp .L71
.L110:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L79
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L79:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L80
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L80:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L61
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L61:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L111
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L102:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L78:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L71
call _ZdlPvm@PLT
jmp .L71
.L93:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L83
call __stack_chk_fail@PLT
.L83:
movq %rbx, %rdi
.LEHB18:
call _Unwind_Resume@PLT
.L94:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L85
call __stack_chk_fail@PLT
.L85:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L95:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L87
call __stack_chk_fail@PLT
.L87:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L97:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L71
.L98:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L78
.L96:
endbr64
movq %rax, %rbx
jmp .L71
.L91:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE18:
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L93-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L94-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L99-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L95-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L96-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 .L100-.LFB4617
.uleb128 0
.uleb128 .LEHB14-.LFB4617
.uleb128 .LEHE14-.LEHB14
.uleb128 .L97-.LFB4617
.uleb128 0
.uleb128 .LEHB15-.LFB4617
.uleb128 .LEHE15-.LEHB15
.uleb128 .L101-.LFB4617
.uleb128 0
.uleb128 .LEHB16-.LFB4617
.uleb128 .LEHE16-.LEHB16
.uleb128 .L102-.LFB4617
.uleb128 0
.uleb128 .LEHB17-.LFB4617
.uleb128 .LEHE17-.LEHB17
.uleb128 .L98-.LFB4617
.uleb128 0
.uleb128 .LEHB18-.LFB4617
.uleb128 .LEHE18-.LEHB18
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops11MatRvectAdd7compileEv, .-_ZN3ops11MatRvectAdd7compileEv
.weak _ZTSN3ops11MatRvectAddE
.section .rodata._ZTSN3ops11MatRvectAddE,"aG",@progbits,_ZTSN3ops11MatRvectAddE,comdat
.align 16
.type _ZTSN3ops11MatRvectAddE, @object
.size _ZTSN3ops11MatRvectAddE, 20
_ZTSN3ops11MatRvectAddE:
.string "N3ops11MatRvectAddE"
.weak _ZTIN3ops11MatRvectAddE
.section .data.rel.ro._ZTIN3ops11MatRvectAddE,"awG",@progbits,_ZTIN3ops11MatRvectAddE,comdat
.align 8
.type _ZTIN3ops11MatRvectAddE, @object
.size _ZTIN3ops11MatRvectAddE, 24
_ZTIN3ops11MatRvectAddE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops11MatRvectAddE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops11MatRvectAddE
.section .data.rel.ro._ZTVN3ops11MatRvectAddE,"awG",@progbits,_ZTVN3ops11MatRvectAddE,comdat
.align 8
.type _ZTVN3ops11MatRvectAddE, @object
.size _ZTVN3ops11MatRvectAddE, 48
_ZTVN3ops11MatRvectAddE:
.quad 0
.quad _ZTIN3ops11MatRvectAddE
.quad _ZN3ops11MatRvectAddD1Ev
.quad _ZN3ops11MatRvectAddD0Ev
.quad _ZN3ops11MatRvectAdd7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat-rvect-add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops11MatRvectAddC2EPNS_2OpES2_,@function
_ZN3ops11MatRvectAddC2EPNS_2OpES2_: # @_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
movabsq $7162261016002453869, %rax # imm = 0x636576725F74616D
movq %rax, 48(%rsp)
movabsq $7234013964066317686, %rax # imm = 0x6464615F74636576
movq %rax, 53(%rsp)
movq $13, 40(%rsp)
movb $0, 61(%rsp)
.Ltmp0:
movq %rsi, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r12, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
callq _ZdlPv
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops11MatRvectAddE+16, (%rbx)
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
jmp .LBB0_14
.LBB0_10:
.Ltmp5:
movq %rax, %rbx
.LBB0_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_16
# %bb.15:
callq _ZdlPv
jmp .LBB0_16
.LBB0_11:
.Ltmp2:
movq %rax, %rbx
.LBB0_16: # %.body
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_18
# %bb.17: # %.critedge.i.i23
callq _ZdlPv
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops11MatRvectAddC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops11MatRvectAddC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops11MatRvectAdd7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops11MatRvectAdd7compileEv
.p2align 4, 0x90
.type _ZN3ops11MatRvectAdd7compileEv,@function
_ZN3ops11MatRvectAdd7compileEv: # @_ZN3ops11MatRvectAdd7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
callq _ZN3ops5Graph8instanceEv
movq %rax, %r12
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 48(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %r12, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r15
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 48(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %r12, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, %rbp
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit47
leaq 64(%r15), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, %r13d
movl $1, %esi
movq %rbx, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp15:
movl $8, %edi
callq _Znwm
.Ltmp16:
# %bb.7: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 16(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 32(%rsp)
movl %r13d, (%rax)
movl %ebx, 76(%rsp) # 4-byte Spill
movl %ebx, 4(%rax)
movq %rcx, 24(%rsp)
.Ltmp18:
leaq 48(%rsp), %rdi
leaq 16(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp19:
# %bb.8:
movq %r12, 136(%rsp) # 8-byte Spill
movq %r14, 144(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_10
# %bb.9:
callq _ZdlPv
.LBB1_10: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.Ltmp21:
movl %r13d, %ebx
leaq 48(%rsp), %rdi
callq _ZNK3ops5Shape5totalEv
.Ltmp22:
# %bb.11:
movslq %eax, %rdi
.Ltmp23:
callq _Z12tensor_allocm
.Ltmp24:
# %bb.12:
movq %rax, %r12
movq 88(%r15), %r14
movq 88(%rbp), %r13
movq 56(%r15), %r15
movq 56(%rbp), %rbp
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp26:
movl $16, %edi
callq _Znwm
.Ltmp27:
# %bb.13: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movslq %ebx, %rcx
movslq 76(%rsp), %r8 # 4-byte Folded Reload
movq %rax, 16(%rsp)
movq %rax, %rdx
addq $16, %rdx
movq %rdx, 32(%rsp)
movq %r15, (%rax)
movq %rbp, 8(%rax)
movq %rdx, 24(%rsp)
.Ltmp29:
leaq 16(%rsp), %r9
movq %r14, %rdi
movq %r13, %rsi
movq %r12, %rdx
callq _ZN2rt4Node16op_mat_rvect_addEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp30:
# %bb.14:
movq %rax, %rbx
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_16
# %bb.15:
callq _ZdlPv
.LBB1_16: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp32:
movl $8, %edi
callq _Znwm
.Ltmp33:
# %bb.17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit59
movq %rax, 112(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 128(%rsp)
movq %rbx, (%rax)
movq %rcx, 120(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp35:
movl $8, %edi
callq _Znwm
.Ltmp36:
# %bb.18: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r12, (%rax)
movq %rcx, 88(%rsp)
.Ltmp38:
movq %r12, (%rsp)
leaq 112(%rsp), %rdx
leaq 80(%rsp), %rcx
leaq 48(%rsp), %r9
movq 136(%rsp), %rdi # 8-byte Reload
movq 144(%rsp), %rsi # 8-byte Reload
movq %rbx, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp39:
# %bb.19:
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_21
# %bb.20:
callq _ZdlPv
.LBB1_21: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZdlPv
.LBB1_23: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit67
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_25
# %bb.24:
callq _ZdlPv
.LBB1_25: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 208
.Ltmp40:
jmp .LBB1_28
.LBB1_27:
.Ltmp37:
.LBB1_28:
movq %rax, %rbx
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_31
# %bb.29: # %.body61.sink.split
callq _ZdlPv
jmp .LBB1_31
.LBB1_30:
.Ltmp34:
movq %rax, %rbx
.LBB1_31: # %.body61
movq 112(%rsp), %rdi
jmp .LBB1_35
.LBB1_32:
.Ltmp31:
jmp .LBB1_34
.LBB1_33:
.Ltmp28:
.LBB1_34:
movq %rax, %rbx
movq 16(%rsp), %rdi
.LBB1_35: # %.body61
testq %rdi, %rdi
je .LBB1_44
# %bb.36:
callq _ZdlPv
jmp .LBB1_44
.LBB1_37:
.Ltmp20:
jmp .LBB1_39
.LBB1_38:
.Ltmp17:
.LBB1_39:
movq %rax, %rbx
movq 16(%rsp), %rdi
jmp .LBB1_45
.LBB1_40:
.Ltmp14:
jmp .LBB1_43
.LBB1_41:
.Ltmp11:
jmp .LBB1_43
.LBB1_42:
.Ltmp25:
.LBB1_43: # %.body57
movq %rax, %rbx
.LBB1_44: # %.body57
movq 48(%rsp), %rdi
.LBB1_45: # %.body57
testq %rdi, %rdi
je .LBB1_47
# %bb.46:
callq _ZdlPv
.LBB1_47:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops11MatRvectAdd7compileEv, .Lfunc_end1-_ZN3ops11MatRvectAdd7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin1 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin1 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin1 # >> Call Site 14 <<
.uleb128 .Lfunc_end1-.Ltmp39 # Call between .Ltmp39 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops11MatRvectAddD0Ev,"axG",@progbits,_ZN3ops11MatRvectAddD0Ev,comdat
.weak _ZN3ops11MatRvectAddD0Ev # -- Begin function _ZN3ops11MatRvectAddD0Ev
.p2align 4, 0x90
.type _ZN3ops11MatRvectAddD0Ev,@function
_ZN3ops11MatRvectAddD0Ev: # @_ZN3ops11MatRvectAddD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops11MatRvectAddD0Ev, .Lfunc_end3-_ZN3ops11MatRvectAddD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "mat_rvect_add"
.size .L.str, 14
.type _ZTVN3ops11MatRvectAddE,@object # @_ZTVN3ops11MatRvectAddE
.section .rodata,"a",@progbits
.globl _ZTVN3ops11MatRvectAddE
.p2align 3, 0x0
_ZTVN3ops11MatRvectAddE:
.quad 0
.quad _ZTIN3ops11MatRvectAddE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops11MatRvectAddD0Ev
.quad _ZN3ops11MatRvectAdd7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops11MatRvectAddE, 48
.type _ZTSN3ops11MatRvectAddE,@object # @_ZTSN3ops11MatRvectAddE
.globl _ZTSN3ops11MatRvectAddE
_ZTSN3ops11MatRvectAddE:
.asciz "N3ops11MatRvectAddE"
.size _ZTSN3ops11MatRvectAddE, 20
.type _ZTIN3ops11MatRvectAddE,@object # @_ZTIN3ops11MatRvectAddE
.globl _ZTIN3ops11MatRvectAddE
.p2align 3, 0x0
_ZTIN3ops11MatRvectAddE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops11MatRvectAddE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops11MatRvectAddE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops11MatRvectAddC1EPNS_2OpES2_
.type _ZN3ops11MatRvectAddC1EPNS_2OpES2_,@function
.set _ZN3ops11MatRvectAddC1EPNS_2OpES2_, _ZN3ops11MatRvectAddC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops11MatRvectAddE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops11MatRvectAddE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************************************//**
* \file intermediatePressure.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side of the poission equation
*/
#include "intermediatePressure.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void intermediatePressure(double *rhs2, double *uhat, int *ghostTagsP, int *hybridTagsP, int *ghostTagsUV, double *distance_from_u_to_body, double *distance_from_v_to_body, double *ym, double *yp, double *xm, double *xp, double *dx, double *dy, int nx, int ny)
{
if (threadIdx.x + blockDim.x * blockIdx.x >= nx*ny)
return;
int ip = threadIdx.x + blockDim.x * blockIdx.x,
I = ip % nx,
J = ip / nx,
iu = (nx-1)*J + I,
iv = (nx-1)*ny + nx*J +I;
double temp = 0;
//Outside immersed body
if (hybridTagsP[ip] != -1)
{
//EAST
//check if east pressure node is outside of the body
if (ghostTagsP[ip+1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp -= uhat[iu]/distance_from_u_to_body[ip];
}
else
temp -= uhat[iu]/dx[I];
}
//WEST
//check if west pressure node is outside of the body
if (ghostTagsP[ip-1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp += uhat[iu-1]/distance_from_u_to_body[ip];
}
else
temp += uhat[iu-1]/dx[I];
}
//NORTH
//check if north pressure node is outside of the body
if (ghostTagsP[ip+nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp -= uhat[iv]/distance_from_v_to_body[ip];
}
else
temp -= uhat[iv]/dy[J];
}
//SOUTH
//check if south velocity node is outside of the body
if (ghostTagsP[ip-nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp += uhat[iv-nx]/distance_from_v_to_body[ip];
}
else
temp += uhat[iv-nx]/dy[J];
}
}
//end outside immersed body
//if just inside body
else if (ghostTagsP[ip] > 0)
{
//EAST
if (ghostTagsP[ip+1] == 0)
temp -= uhat[iu]/dx[I];
//WEST
if (ghostTagsP[ip-1] == 0)
temp += uhat[iu - 1]/dx[I];
//NORTH
if (ghostTagsP[ip+nx] == 0)
temp -= uhat[iv]/dy[J];
//SOUTH
if (ghostTagsP[ip-nx] == 0)
temp += uhat[iv-nx]/dy[J];
}
//end just inside body
//everywhere else
else
{
//EAST
//if not on the east wall and east is outside the body, add east term
if (I != nx-1)//not at east boundry
temp -= uhat[iu]/dx[I];
else if (I == nx-1)//at east boundry
temp -= xp[J]/dx[I];
//WEST
//if not on west wall and west is outside the body, add west term
if (I != 0)//not at west boundary
temp += uhat[iu - 1]/dx[I];
else if (I == 0)//at the west boundary
temp += xm[J]/dx[I];
//NORTH
//if not on north wall and north is outside the body, add north term
if (J != ny-1)//not at north boundry
temp -= uhat[iv]/dy[J];
else if (J == ny-1)//at north boundry
temp -= yp[(nx-1)+I]/dy[J];
//SOUTH
//if not on south wall and south is outside the body, add south term
if (J != 0)//not at south boundry
temp += uhat[iv-nx]/dy[J];
else if (J == 0)//at south boundry
temp += ym[(nx-1)+I]/dy[J];
}//end everywhere else
rhs2[ip] = temp;
}
} | .file "tmpxft_0010e93b_00000000-6_intermediatePressure.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
.type _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii, @function
_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 320(%rsp), %rax
movq %rax, 56(%rsp)
movq 328(%rsp), %rax
movq %rax, 48(%rsp)
movq 336(%rsp), %rax
movq %rax, 40(%rsp)
movq 344(%rsp), %rax
movq %rax, 32(%rsp)
movq 352(%rsp), %rax
movq %rax, 24(%rsp)
movq 360(%rsp), %rax
movq %rax, 16(%rsp)
movq 368(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
leaq 376(%rsp), %rax
movq %rax, 280(%rsp)
leaq 384(%rsp), %rax
movq %rax, 288(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 328
pushq 120(%rsp)
.cfi_def_cfa_offset 336
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii, .-_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
.globl _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.type _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, @function
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .-_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************************************//**
* \file intermediatePressure.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side of the poission equation
*/
#include "intermediatePressure.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void intermediatePressure(double *rhs2, double *uhat, int *ghostTagsP, int *hybridTagsP, int *ghostTagsUV, double *distance_from_u_to_body, double *distance_from_v_to_body, double *ym, double *yp, double *xm, double *xp, double *dx, double *dy, int nx, int ny)
{
if (threadIdx.x + blockDim.x * blockIdx.x >= nx*ny)
return;
int ip = threadIdx.x + blockDim.x * blockIdx.x,
I = ip % nx,
J = ip / nx,
iu = (nx-1)*J + I,
iv = (nx-1)*ny + nx*J +I;
double temp = 0;
//Outside immersed body
if (hybridTagsP[ip] != -1)
{
//EAST
//check if east pressure node is outside of the body
if (ghostTagsP[ip+1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp -= uhat[iu]/distance_from_u_to_body[ip];
}
else
temp -= uhat[iu]/dx[I];
}
//WEST
//check if west pressure node is outside of the body
if (ghostTagsP[ip-1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp += uhat[iu-1]/distance_from_u_to_body[ip];
}
else
temp += uhat[iu-1]/dx[I];
}
//NORTH
//check if north pressure node is outside of the body
if (ghostTagsP[ip+nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp -= uhat[iv]/distance_from_v_to_body[ip];
}
else
temp -= uhat[iv]/dy[J];
}
//SOUTH
//check if south velocity node is outside of the body
if (ghostTagsP[ip-nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp += uhat[iv-nx]/distance_from_v_to_body[ip];
}
else
temp += uhat[iv-nx]/dy[J];
}
}
//end outside immersed body
//if just inside body
else if (ghostTagsP[ip] > 0)
{
//EAST
if (ghostTagsP[ip+1] == 0)
temp -= uhat[iu]/dx[I];
//WEST
if (ghostTagsP[ip-1] == 0)
temp += uhat[iu - 1]/dx[I];
//NORTH
if (ghostTagsP[ip+nx] == 0)
temp -= uhat[iv]/dy[J];
//SOUTH
if (ghostTagsP[ip-nx] == 0)
temp += uhat[iv-nx]/dy[J];
}
//end just inside body
//everywhere else
else
{
//EAST
//if not on the east wall and east is outside the body, add east term
if (I != nx-1)//not at east boundry
temp -= uhat[iu]/dx[I];
else if (I == nx-1)//at east boundry
temp -= xp[J]/dx[I];
//WEST
//if not on west wall and west is outside the body, add west term
if (I != 0)//not at west boundary
temp += uhat[iu - 1]/dx[I];
else if (I == 0)//at the west boundary
temp += xm[J]/dx[I];
//NORTH
//if not on north wall and north is outside the body, add north term
if (J != ny-1)//not at north boundry
temp -= uhat[iv]/dy[J];
else if (J == ny-1)//at north boundry
temp -= yp[(nx-1)+I]/dy[J];
//SOUTH
//if not on south wall and south is outside the body, add south term
if (J != 0)//not at south boundry
temp += uhat[iv-nx]/dy[J];
else if (J == 0)//at south boundry
temp += ym[(nx-1)+I]/dy[J];
}//end everywhere else
rhs2[ip] = temp;
}
} | /***************************************************************************//**
* \file intermediatePressure.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side of the poission equation
*/
#include <hip/hip_runtime.h>
#include "intermediatePressure.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void intermediatePressure(double *rhs2, double *uhat, int *ghostTagsP, int *hybridTagsP, int *ghostTagsUV, double *distance_from_u_to_body, double *distance_from_v_to_body, double *ym, double *yp, double *xm, double *xp, double *dx, double *dy, int nx, int ny)
{
if (threadIdx.x + blockDim.x * blockIdx.x >= nx*ny)
return;
int ip = threadIdx.x + blockDim.x * blockIdx.x,
I = ip % nx,
J = ip / nx,
iu = (nx-1)*J + I,
iv = (nx-1)*ny + nx*J +I;
double temp = 0;
//Outside immersed body
if (hybridTagsP[ip] != -1)
{
//EAST
//check if east pressure node is outside of the body
if (ghostTagsP[ip+1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp -= uhat[iu]/distance_from_u_to_body[ip];
}
else
temp -= uhat[iu]/dx[I];
}
//WEST
//check if west pressure node is outside of the body
if (ghostTagsP[ip-1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp += uhat[iu-1]/distance_from_u_to_body[ip];
}
else
temp += uhat[iu-1]/dx[I];
}
//NORTH
//check if north pressure node is outside of the body
if (ghostTagsP[ip+nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp -= uhat[iv]/distance_from_v_to_body[ip];
}
else
temp -= uhat[iv]/dy[J];
}
//SOUTH
//check if south velocity node is outside of the body
if (ghostTagsP[ip-nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp += uhat[iv-nx]/distance_from_v_to_body[ip];
}
else
temp += uhat[iv-nx]/dy[J];
}
}
//end outside immersed body
//if just inside body
else if (ghostTagsP[ip] > 0)
{
//EAST
if (ghostTagsP[ip+1] == 0)
temp -= uhat[iu]/dx[I];
//WEST
if (ghostTagsP[ip-1] == 0)
temp += uhat[iu - 1]/dx[I];
//NORTH
if (ghostTagsP[ip+nx] == 0)
temp -= uhat[iv]/dy[J];
//SOUTH
if (ghostTagsP[ip-nx] == 0)
temp += uhat[iv-nx]/dy[J];
}
//end just inside body
//everywhere else
else
{
//EAST
//if not on the east wall and east is outside the body, add east term
if (I != nx-1)//not at east boundry
temp -= uhat[iu]/dx[I];
else if (I == nx-1)//at east boundry
temp -= xp[J]/dx[I];
//WEST
//if not on west wall and west is outside the body, add west term
if (I != 0)//not at west boundary
temp += uhat[iu - 1]/dx[I];
else if (I == 0)//at the west boundary
temp += xm[J]/dx[I];
//NORTH
//if not on north wall and north is outside the body, add north term
if (J != ny-1)//not at north boundry
temp -= uhat[iv]/dy[J];
else if (J == ny-1)//at north boundry
temp -= yp[(nx-1)+I]/dy[J];
//SOUTH
//if not on south wall and south is outside the body, add south term
if (J != 0)//not at south boundry
temp += uhat[iv-nx]/dy[J];
else if (J == 0)//at south boundry
temp += ym[(nx-1)+I]/dy[J];
}//end everywhere else
rhs2[ip] = temp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***************************************************************************//**
* \file intermediatePressure.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side of the poission equation
*/
#include <hip/hip_runtime.h>
#include "intermediatePressure.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void intermediatePressure(double *rhs2, double *uhat, int *ghostTagsP, int *hybridTagsP, int *ghostTagsUV, double *distance_from_u_to_body, double *distance_from_v_to_body, double *ym, double *yp, double *xm, double *xp, double *dx, double *dy, int nx, int ny)
{
if (threadIdx.x + blockDim.x * blockIdx.x >= nx*ny)
return;
int ip = threadIdx.x + blockDim.x * blockIdx.x,
I = ip % nx,
J = ip / nx,
iu = (nx-1)*J + I,
iv = (nx-1)*ny + nx*J +I;
double temp = 0;
//Outside immersed body
if (hybridTagsP[ip] != -1)
{
//EAST
//check if east pressure node is outside of the body
if (ghostTagsP[ip+1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp -= uhat[iu]/distance_from_u_to_body[ip];
}
else
temp -= uhat[iu]/dx[I];
}
//WEST
//check if west pressure node is outside of the body
if (ghostTagsP[ip-1] == -1)
{
if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
{
temp += uhat[iu-1]/distance_from_u_to_body[ip];
}
else
temp += uhat[iu-1]/dx[I];
}
//NORTH
//check if north pressure node is outside of the body
if (ghostTagsP[ip+nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp -= uhat[iv]/distance_from_v_to_body[ip];
}
else
temp -= uhat[iv]/dy[J];
}
//SOUTH
//check if south velocity node is outside of the body
if (ghostTagsP[ip-nx] == -1)
{
if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
{
temp += uhat[iv-nx]/distance_from_v_to_body[ip];
}
else
temp += uhat[iv-nx]/dy[J];
}
}
//end outside immersed body
//if just inside body
else if (ghostTagsP[ip] > 0)
{
//EAST
if (ghostTagsP[ip+1] == 0)
temp -= uhat[iu]/dx[I];
//WEST
if (ghostTagsP[ip-1] == 0)
temp += uhat[iu - 1]/dx[I];
//NORTH
if (ghostTagsP[ip+nx] == 0)
temp -= uhat[iv]/dy[J];
//SOUTH
if (ghostTagsP[ip-nx] == 0)
temp += uhat[iv-nx]/dy[J];
}
//end just inside body
//everywhere else
else
{
//EAST
//if not on the east wall and east is outside the body, add east term
if (I != nx-1)//not at east boundry
temp -= uhat[iu]/dx[I];
else if (I == nx-1)//at east boundry
temp -= xp[J]/dx[I];
//WEST
//if not on west wall and west is outside the body, add west term
if (I != 0)//not at west boundary
temp += uhat[iu - 1]/dx[I];
else if (I == 0)//at the west boundary
temp += xm[J]/dx[I];
//NORTH
//if not on north wall and north is outside the body, add north term
if (J != ny-1)//not at north boundry
temp -= uhat[iv]/dy[J];
else if (J == ny-1)//at north boundry
temp -= yp[(nx-1)+I]/dy[J];
//SOUTH
//if not on south wall and south is outside the body, add south term
if (J != 0)//not at south boundry
temp += uhat[iv-nx]/dy[J];
else if (J == 0)//at south boundry
temp += ym[(nx-1)+I]/dy[J];
}//end everywhere else
rhs2[ip] = temp;
}
} | .text
.file "intermediatePressure.hip"
.globl _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii # -- Begin function _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.p2align 4, 0x90
.type _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@function
_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii: # @_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .Lfunc_end0-_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@object # @_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.section .rodata,"a",@progbits
.globl _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.p2align 3, 0x0
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii:
.quad _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.size _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii"
.size .L__unnamed_1, 74
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010e93b_00000000-6_intermediatePressure.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
.type _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii, @function
_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 320(%rsp), %rax
movq %rax, 56(%rsp)
movq 328(%rsp), %rax
movq %rax, 48(%rsp)
movq 336(%rsp), %rax
movq %rax, 40(%rsp)
movq 344(%rsp), %rax
movq %rax, 32(%rsp)
movq 352(%rsp), %rax
movq %rax, 24(%rsp)
movq 360(%rsp), %rax
movq %rax, 16(%rsp)
movq 368(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
leaq 376(%rsp), %rax
movq %rax, 280(%rsp)
leaq 384(%rsp), %rax
movq %rax, 288(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 328
pushq 120(%rsp)
.cfi_def_cfa_offset 336
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii, .-_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
.globl _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.type _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, @function
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .-_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "intermediatePressure.hip"
.globl _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii # -- Begin function _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.p2align 4, 0x90
.type _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@function
_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii: # @_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .Lfunc_end0-_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@object # @_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.section .rodata,"a",@progbits
.globl _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.p2align 3, 0x0
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii:
.quad _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.size _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii"
.size .L__unnamed_1, 74
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void elementwiseDiv(float *a, const float *b, const size_t len)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= len)
return;
a[idx] /= b[idx] + 1e-6f;
} | code for sm_80
Function : _Z14elementwiseDivPfPKfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0100*/ BSSY B0, 0x1d0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0110*/ FADD R6, R4, 9.9999999747524270788e-07 ; /* 0x358637bd04067421 */
/* 0x004fc80000000000 */
/*0120*/ MUFU.RCP R9, R6 ; /* 0x0000000600097308 */
/* 0x000e300000001000 */
/*0130*/ FCHK P0, R7, R6 ; /* 0x0000000607007302 */
/* 0x008e620000000000 */
/*0140*/ FFMA R0, -R6, R9, 1 ; /* 0x3f80000006007423 */
/* 0x001fc80000000109 */
/*0150*/ FFMA R0, R9, R0, R9 ; /* 0x0000000009007223 */
/* 0x000fc80000000009 */
/*0160*/ FFMA R9, R7, R0, RZ ; /* 0x0000000007097223 */
/* 0x000fc800000000ff */
/*0170*/ FFMA R8, -R6, R9, R7 ; /* 0x0000000906087223 */
/* 0x000fc80000000107 */
/*0180*/ FFMA R9, R0, R8, R9 ; /* 0x0000000800097223 */
/* 0x000fe20000000009 */
/*0190*/ @!P0 BRA 0x1c0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*01a0*/ MOV R0, 0x1c0 ; /* 0x000001c000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ CALL.REL.NOINC 0x1f0 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ SHF.R.U32.HI R5, RZ, 0x17, R6.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011606 */
/*0200*/ BSSY B1, 0x850 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0210*/ SHF.R.U32.HI R4, RZ, 0x17, R7.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011607 */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0230*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*0250*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0260*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fc40007ffe0ff */
/*0270*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0290*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02a0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02b0*/ @!P0 BRA 0x430 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*02d0*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*02e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02f0*/ @P0 BRA 0x830 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0300*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0310*/ @!P0 BRA 0x810 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0330*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0340*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*0350*/ @!P1 BRA !P2, 0x810 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0360*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0370*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0380*/ @P1 BRA 0x7f0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0390*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*03a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03b0*/ @P0 BRA 0x7c0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03c0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*03d0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03e0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0400*/ @!P0 FFMA R8, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007088823 */
/* 0x000fe400000000ff */
/*0410*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0420*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LEA R6, R5, 0xc0800000, 0x17 ; /* 0xc080000005067811 */
/* 0x000fe200078eb8ff */
/*0440*/ BSSY B2, 0x7b0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0450*/ IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a06 */
/*0460*/ IADD3 R6, R4, -0x7f, RZ ; /* 0xffffff8104067810 */
/* 0x000fc60007ffe0ff */
/*0470*/ MUFU.RCP R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001000 */
/*0480*/ FADD.FTZ R11, -R9, -RZ ; /* 0x800000ff090b7221 */
/* 0x000fe40000010100 */
/*0490*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*04a0*/ FFMA R4, R7, R11, 1 ; /* 0x3f80000007047423 */
/* 0x001fc8000000000b */
/*04b0*/ FFMA R13, R7, R4, R7 ; /* 0x00000004070d7223 */
/* 0x000fc80000000007 */
/*04c0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R7, R11, R4, R8 ; /* 0x000000040b077223 */
/* 0x000fc80000000008 */
/*04e0*/ FFMA R12, R13, R7, R4 ; /* 0x000000070d0c7223 */
/* 0x000fe20000000004 */
/*04f0*/ IADD3 R7, R6, 0x7f, -R5 ; /* 0x0000007f06077810 */
/* 0x000fc60007ffe805 */
/*0500*/ FFMA R8, R11, R12, R8 ; /* 0x0000000c0b087223 */
/* 0x000fe40000000008 */
/*0510*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0520*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0530*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0540*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0550*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0560*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0580*/ @!P0 BRA 0x790 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05a0*/ @P0 BRA 0x760 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05c0*/ @P0 BRA 0x7a0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05e0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05f0*/ @!P0 BRA 0x7a0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0600*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0610*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0620*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0630*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0640*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0650*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0660*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0680*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0690*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*06a0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06b0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06c0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06d0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06f0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0700*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0710*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0720*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0730*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0740*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0750*/ BRA 0x7a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0770*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0790*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*07a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x840 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*07d0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07e0*/ BRA 0x840 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0800*/ BRA 0x840 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0810*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0820*/ BRA 0x840 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0830*/ FADD.FTZ R4, R7, R6 ; /* 0x0000000607047221 */
/* 0x000fe40000010000 */
/*0840*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0004 */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff77004007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void elementwiseDiv(float *a, const float *b, const size_t len)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= len)
return;
a[idx] /= b[idx] + 1e-6f;
} | .file "tmpxft_000f31f7_00000000-6_elementwiseDiv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm
.type _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm, @function
_Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14elementwiseDivPfPKfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm, .-_Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm
.globl _Z14elementwiseDivPfPKfm
.type _Z14elementwiseDivPfPKfm, @function
_Z14elementwiseDivPfPKfm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14elementwiseDivPfPKfm, .-_Z14elementwiseDivPfPKfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14elementwiseDivPfPKfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14elementwiseDivPfPKfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void elementwiseDiv(float *a, const float *b, const size_t len)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= len)
return;
a[idx] /= b[idx] + 1e-6f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void elementwiseDiv(float *a, const float *b, const size_t len)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= len)
return;
a[idx] /= b[idx] + 1e-6f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void elementwiseDiv(float *a, const float *b, const size_t len)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= len)
return;
a[idx] /= b[idx] + 1e-6f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14elementwiseDivPfPKfm
.globl _Z14elementwiseDivPfPKfm
.p2align 8
.type _Z14elementwiseDivPfPKfm,@function
_Z14elementwiseDivPfPKfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, 0x358637bd, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14elementwiseDivPfPKfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14elementwiseDivPfPKfm, .Lfunc_end0-_Z14elementwiseDivPfPKfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14elementwiseDivPfPKfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14elementwiseDivPfPKfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void elementwiseDiv(float *a, const float *b, const size_t len)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= len)
return;
a[idx] /= b[idx] + 1e-6f;
} | .text
.file "elementwiseDiv.hip"
.globl _Z29__device_stub__elementwiseDivPfPKfm # -- Begin function _Z29__device_stub__elementwiseDivPfPKfm
.p2align 4, 0x90
.type _Z29__device_stub__elementwiseDivPfPKfm,@function
_Z29__device_stub__elementwiseDivPfPKfm: # @_Z29__device_stub__elementwiseDivPfPKfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14elementwiseDivPfPKfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__elementwiseDivPfPKfm, .Lfunc_end0-_Z29__device_stub__elementwiseDivPfPKfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14elementwiseDivPfPKfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14elementwiseDivPfPKfm,@object # @_Z14elementwiseDivPfPKfm
.section .rodata,"a",@progbits
.globl _Z14elementwiseDivPfPKfm
.p2align 3, 0x0
_Z14elementwiseDivPfPKfm:
.quad _Z29__device_stub__elementwiseDivPfPKfm
.size _Z14elementwiseDivPfPKfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14elementwiseDivPfPKfm"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__elementwiseDivPfPKfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14elementwiseDivPfPKfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14elementwiseDivPfPKfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0100*/ BSSY B0, 0x1d0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0110*/ FADD R6, R4, 9.9999999747524270788e-07 ; /* 0x358637bd04067421 */
/* 0x004fc80000000000 */
/*0120*/ MUFU.RCP R9, R6 ; /* 0x0000000600097308 */
/* 0x000e300000001000 */
/*0130*/ FCHK P0, R7, R6 ; /* 0x0000000607007302 */
/* 0x008e620000000000 */
/*0140*/ FFMA R0, -R6, R9, 1 ; /* 0x3f80000006007423 */
/* 0x001fc80000000109 */
/*0150*/ FFMA R0, R9, R0, R9 ; /* 0x0000000009007223 */
/* 0x000fc80000000009 */
/*0160*/ FFMA R9, R7, R0, RZ ; /* 0x0000000007097223 */
/* 0x000fc800000000ff */
/*0170*/ FFMA R8, -R6, R9, R7 ; /* 0x0000000906087223 */
/* 0x000fc80000000107 */
/*0180*/ FFMA R9, R0, R8, R9 ; /* 0x0000000800097223 */
/* 0x000fe20000000009 */
/*0190*/ @!P0 BRA 0x1c0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*01a0*/ MOV R0, 0x1c0 ; /* 0x000001c000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ CALL.REL.NOINC 0x1f0 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ SHF.R.U32.HI R5, RZ, 0x17, R6.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011606 */
/*0200*/ BSSY B1, 0x850 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0210*/ SHF.R.U32.HI R4, RZ, 0x17, R7.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011607 */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0230*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*0250*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0260*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fc40007ffe0ff */
/*0270*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0290*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02a0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02b0*/ @!P0 BRA 0x430 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*02d0*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*02e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02f0*/ @P0 BRA 0x830 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0300*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0310*/ @!P0 BRA 0x810 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0330*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0340*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*0350*/ @!P1 BRA !P2, 0x810 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0360*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0370*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0380*/ @P1 BRA 0x7f0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0390*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*03a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03b0*/ @P0 BRA 0x7c0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03c0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*03d0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03e0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0400*/ @!P0 FFMA R8, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007088823 */
/* 0x000fe400000000ff */
/*0410*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0420*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LEA R6, R5, 0xc0800000, 0x17 ; /* 0xc080000005067811 */
/* 0x000fe200078eb8ff */
/*0440*/ BSSY B2, 0x7b0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0450*/ IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a06 */
/*0460*/ IADD3 R6, R4, -0x7f, RZ ; /* 0xffffff8104067810 */
/* 0x000fc60007ffe0ff */
/*0470*/ MUFU.RCP R7, R9 ; /* 0x0000000900077308 */
/* 0x000e220000001000 */
/*0480*/ FADD.FTZ R11, -R9, -RZ ; /* 0x800000ff090b7221 */
/* 0x000fe40000010100 */
/*0490*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*04a0*/ FFMA R4, R7, R11, 1 ; /* 0x3f80000007047423 */
/* 0x001fc8000000000b */
/*04b0*/ FFMA R13, R7, R4, R7 ; /* 0x00000004070d7223 */
/* 0x000fc80000000007 */
/*04c0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R7, R11, R4, R8 ; /* 0x000000040b077223 */
/* 0x000fc80000000008 */
/*04e0*/ FFMA R12, R13, R7, R4 ; /* 0x000000070d0c7223 */
/* 0x000fe20000000004 */
/*04f0*/ IADD3 R7, R6, 0x7f, -R5 ; /* 0x0000007f06077810 */
/* 0x000fc60007ffe805 */
/*0500*/ FFMA R8, R11, R12, R8 ; /* 0x0000000c0b087223 */
/* 0x000fe40000000008 */
/*0510*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0520*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0530*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0540*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0550*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0560*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0580*/ @!P0 BRA 0x790 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05a0*/ @P0 BRA 0x760 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05c0*/ @P0 BRA 0x7a0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05e0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05f0*/ @!P0 BRA 0x7a0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0600*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0610*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0620*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0630*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0640*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0650*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0660*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0680*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0690*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*06a0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06b0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06c0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06d0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06f0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0700*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0710*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0720*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0730*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0740*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0750*/ BRA 0x7a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0770*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0790*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*07a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x840 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*07d0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07e0*/ BRA 0x840 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0800*/ BRA 0x840 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0810*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0820*/ BRA 0x840 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0830*/ FADD.FTZ R4, R7, R6 ; /* 0x0000000607047221 */
/* 0x000fe40000010000 */
/*0840*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0004 */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff77004007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14elementwiseDivPfPKfm
.globl _Z14elementwiseDivPfPKfm
.p2align 8
.type _Z14elementwiseDivPfPKfm,@function
_Z14elementwiseDivPfPKfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, 0x358637bd, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14elementwiseDivPfPKfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14elementwiseDivPfPKfm, .Lfunc_end0-_Z14elementwiseDivPfPKfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14elementwiseDivPfPKfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14elementwiseDivPfPKfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f31f7_00000000-6_elementwiseDiv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm
.type _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm, @function
_Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14elementwiseDivPfPKfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm, .-_Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm
.globl _Z14elementwiseDivPfPKfm
.type _Z14elementwiseDivPfPKfm, @function
_Z14elementwiseDivPfPKfm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14elementwiseDivPfPKfmPfPKfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14elementwiseDivPfPKfm, .-_Z14elementwiseDivPfPKfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14elementwiseDivPfPKfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14elementwiseDivPfPKfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "elementwiseDiv.hip"
.globl _Z29__device_stub__elementwiseDivPfPKfm # -- Begin function _Z29__device_stub__elementwiseDivPfPKfm
.p2align 4, 0x90
.type _Z29__device_stub__elementwiseDivPfPKfm,@function
_Z29__device_stub__elementwiseDivPfPKfm: # @_Z29__device_stub__elementwiseDivPfPKfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14elementwiseDivPfPKfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__elementwiseDivPfPKfm, .Lfunc_end0-_Z29__device_stub__elementwiseDivPfPKfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14elementwiseDivPfPKfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14elementwiseDivPfPKfm,@object # @_Z14elementwiseDivPfPKfm
.section .rodata,"a",@progbits
.globl _Z14elementwiseDivPfPKfm
.p2align 3, 0x0
_Z14elementwiseDivPfPKfm:
.quad _Z29__device_stub__elementwiseDivPfPKfm
.size _Z14elementwiseDivPfPKfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14elementwiseDivPfPKfm"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__elementwiseDivPfPKfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14elementwiseDivPfPKfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define TILE_DIM 32
template<typename T>
__device__ void getColumn(const T* matrix, const int col, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[index * cols + col];
}
template<typename T>
__device__ void updateColumn(T* matrix, const int col, const T* column,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
matrix[index * cols + col] = column[index];
}
template<typename T>
__device__ void matrixAddColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] + tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnAddMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] + matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixSubColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] - tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnSubMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] - matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixTimesColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] * tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnTimesMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] * matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixDivColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] / tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnDivMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] / matrix[row * cols + col];
result[row * cols + col] = value;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define TILE_DIM 32
template<typename T>
__device__ void getColumn(const T* matrix, const int col, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[index * cols + col];
}
template<typename T>
__device__ void updateColumn(T* matrix, const int col, const T* column,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
matrix[index * cols + col] = column[index];
}
template<typename T>
__device__ void matrixAddColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] + tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnAddMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] + matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixSubColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] - tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnSubMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] - matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixTimesColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] * tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnTimesMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] * matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixDivColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] / tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnDivMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] / matrix[row * cols + col];
result[row * cols + col] = value;
}
} | .file "tmpxft_00093832_00000000-6_Column.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2039:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define TILE_DIM 32
template<typename T>
__device__ void getColumn(const T* matrix, const int col, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[index * cols + col];
}
template<typename T>
__device__ void updateColumn(T* matrix, const int col, const T* column,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
matrix[index * cols + col] = column[index];
}
template<typename T>
__device__ void matrixAddColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] + tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnAddMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] + matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixSubColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] - tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnSubMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] - matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixTimesColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] * tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnTimesMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] * matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixDivColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] / tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnDivMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] / matrix[row * cols + col];
result[row * cols + col] = value;
}
} | #include <hip/hip_runtime.h>
#define TILE_DIM 32
template<typename T>
__device__ void getColumn(const T* matrix, const int col, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[index * cols + col];
}
template<typename T>
__device__ void updateColumn(T* matrix, const int col, const T* column,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
matrix[index * cols + col] = column[index];
}
template<typename T>
__device__ void matrixAddColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] + tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnAddMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] + matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixSubColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] - tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnSubMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] - matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixTimesColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] * tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnTimesMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] * matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixDivColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] / tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnDivMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] / matrix[row * cols + col];
result[row * cols + col] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define TILE_DIM 32
template<typename T>
__device__ void getColumn(const T* matrix, const int col, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[index * cols + col];
}
template<typename T>
__device__ void updateColumn(T* matrix, const int col, const T* column,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
matrix[index * cols + col] = column[index];
}
template<typename T>
__device__ void matrixAddColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] + tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnAddMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] + matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixSubColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] - tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnSubMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] - matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixTimesColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] * tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnTimesMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] * matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixDivColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] / tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnDivMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] / matrix[row * cols + col];
result[row * cols + col] = value;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define TILE_DIM 32
template<typename T>
__device__ void getColumn(const T* matrix, const int col, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[index * cols + col];
}
template<typename T>
__device__ void updateColumn(T* matrix, const int col, const T* column,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
matrix[index * cols + col] = column[index];
}
template<typename T>
__device__ void matrixAddColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] + tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnAddMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] + matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixSubColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] - tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnSubMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] - matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixTimesColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] * tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnTimesMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] * matrix[row * cols + col];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void matrixDivColumn(const T* matrix, const T* column, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = matrix[row * cols + col] / tile[ty];
result[row * cols + col] = value;
}
}
template<typename T>
__device__ void columnDivMatrix(const T* column, const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (ty == 0) {
int r = row + tx;
if (r < rows) {
tile[tx] = column[r];
} else {
tile[tx] = 0;
}
}
__syncthreads();
if (row < rows && col < cols) {
T value = tile[ty] / matrix[row * cols + col];
result[row * cols + col] = value;
}
} | .text
.file "Column.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00093832_00000000-6_Column.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2039:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Column.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Alexandre Maros - 2016
*
* Cuda Matrix Multiplication with Global Memory.
*
* nvcc cuda_matrix_global.cu -o cg.o
*
* Implemented by Alexandre Maros for learning purposes.
* A version of this code using Shared Memory is in here:
* https://github.com/alepmaros/cuda_matrix_multiplication
*
* Distributed under the MIT Lincese.
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
//32x32
#define NTHREADS_X 32
#define NTHREADS_Y 32
#define THREADS_PER_BLOCK NTHREADS_X * NTHREADS_Y
/* A macro used for error checking in CUDA function calls
* Credit to: http://stackoverflow.com/a/14038590 for the gpuErrchk macro.
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void matrix_mul(int *a, int *b, int *c, int a_ncolumns, int c_nlines, int c_ncolumns)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int line = blockIdx.y * blockDim.y + threadIdx.y;
if (column >= c_ncolumns || line >= c_nlines)
return;
int i, sum = 0;
int beginA = a_ncolumns * line;
int beginB = column;
for (i = 0; i < a_ncolumns; i++)
{
sum += a[beginA + i] * b[i * c_ncolumns + beginB];
}
c[line * c_ncolumns + column] = sum;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int a_nlines, a_ncolumns;
int b_nlines, b_ncolumns;
int c_nlines, c_ncolumns;
size_t a_size, b_size, c_size;
int i, j;
cudaEvent_t start, stop;
gpuErrchk( cudaEventCreate(&start) );
gpuErrchk( cudaEventCreate(&stop) );
scanf("%d", &a_nlines);
scanf("%d", &a_ncolumns);
scanf("%d", &b_nlines);
scanf("%d", &b_ncolumns);
c_nlines = a_nlines;
c_ncolumns = b_ncolumns;
#ifdef __DEBUG
printf("a_nlines: %d\na_ncolumns: %d\nb_nlines: %d\nb_ncolumns: %d\nc_nlines: %d\nc_ncolumns: %d\n", a_nlines, a_ncolumns, b_nlines, b_ncolumns, c_nlines, c_ncolumns);
#endif
if ( a_ncolumns != b_nlines )
{
printf("Number of columns in Matrix A should be equals to number of lines in Matrix B\n");
return EXIT_FAILURE;
}
a_size = a_nlines * a_ncolumns * sizeof(int);
b_size = b_nlines * b_ncolumns * sizeof(int);
c_size = c_nlines * c_ncolumns * sizeof(int);
gpuErrchk( cudaMalloc((void **) &d_a, a_size) );
gpuErrchk( cudaMalloc((void **) &d_b, b_size) );
gpuErrchk( cudaMalloc((void **) &d_c, c_size) );
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
memset(c, 0, c_nlines*c_ncolumns*sizeof(int));
for (i = 0; i < a_nlines; i++)
{
for (j = 0; j < a_ncolumns; j++)
{
scanf("%d", &a[i * a_ncolumns + j]);
}
}
for (i = 0; i < b_nlines; i++)
{
for (j = 0; j < b_ncolumns; j++)
{
scanf("%d", &b[i * b_ncolumns + j]);
}
}
gpuErrchk( cudaMemcpy(d_a, a, a_size, cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_b, b, b_size, cudaMemcpyHostToDevice) );
dim3 tbloco = dim3(
(int) std::ceil( (double) c_ncolumns / NTHREADS_X ),
(int) std::ceil ( (double) c_nlines / NTHREADS_Y ),
1
);
dim3 tthreads = dim3(
NTHREADS_X,
NTHREADS_Y,
1
);
#ifdef __DEBUG
printf("tbloco.x: %d tbloco.y: %d tbloco.z: %d\n", tbloco.x, tbloco.y, tbloco.z);
printf("tthreads.x: %d tthreads.y: %d\n", tthreads.x, tthreads.y);
#endif
cudaEventRecord(start);
// kernel call
matrix_mul<<<tbloco,tthreads>>>(d_a, d_b, d_c, a_ncolumns, c_nlines, c_ncolumns);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaEventRecord(stop) );
gpuErrchk( cudaMemcpy(c, d_c, c_size, cudaMemcpyDeviceToHost) );
gpuErrchk( cudaEventSynchronize(stop) );
#ifndef __NO_OUTPUT
// print Matrix
for (i = 0; i < c_nlines; i++)
{
for (j = 0; j < c_ncolumns; j++)
{
printf("%d ", c[i * c_ncolumns + j]);
}
printf("\n");
}
printf("\n");
#endif
#ifdef __TIME
float milliseconds = 0;
gpuErrchk( cudaEventElapsedTime(&milliseconds, start, stop) );
printf("%.5f\n", milliseconds);
#endif
free(a); free(b); free(c);
gpuErrchk( cudaFree(d_a) );
gpuErrchk( cudaFree(d_b) );
gpuErrchk( cudaFree(d_c) );
return 0;
} | code for sm_80
Function : _Z10matrix_mulPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc30 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb20 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*01a0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01c0*/ @!P0 BRA 0x980 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6b0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0270*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0290*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02b0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02c0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02d0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02e0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02f0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0300*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0310*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0320*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0340*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0360*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0370*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0380*/ IMAD R16, R21, R20, R24 ; /* 0x0000001415107224 */
/* 0x004fe400078e0218 */
/*0390*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03b0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03d0*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x008fe400078e0210 */
/*03e0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03f0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0400*/ IMAD R26, R26, R27, R16 ; /* 0x0000001b1a1a7224 */
/* 0x010fe200078e0210 */
/*0410*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0420*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0430*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0440*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x020fe400078e021a */
/*0450*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0460*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0470*/ IMAD R26, R9, R8, R26 ; /* 0x00000008091a7224 */
/* 0x000fe200078e021a */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0490*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04c0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04d0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x000fe400078e021a */
/*04e0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04f0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0500*/ IMAD R26, R21, R20, R26 ; /* 0x00000014151a7224 */
/* 0x004fc400078e021a */
/*0510*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD R28, R29, R28, R26 ; /* 0x0000001c1d1c7224 */
/* 0x000fe400078e021a */
/*0540*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0550*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0570*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0580*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0590*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05a0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05b0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05c0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x000fc800078e021c */
/*05d0*/ IMAD R25, R16, R25, R14 ; /* 0x0000001910197224 */
/* 0x010fe200078e020e */
/*05e0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ IMAD R18, R18, R22, R25 ; /* 0x0000001612127224 */
/* 0x020fe200078e0219 */
/*0600*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0610*/ IMAD R15, R24, R15, R18 ; /* 0x0000000f180f7224 */
/* 0x000fe200078e0212 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD R10, R10, R17, R15 ; /* 0x000000110a0a7224 */
/* 0x004fc800078e020f */
/*0670*/ IMAD R10, R20, R29, R10 ; /* 0x0000001d140a7224 */
/* 0x000fc800078e020a */
/*0680*/ IMAD R10, R19, R21, R10 ; /* 0x00000015130a7224 */
/* 0x000fc800078e020a */
/*0690*/ IMAD R24, R11, R26, R10 ; /* 0x0000001a0b187224 */
/* 0x008fe200078e020a */
/*06a0*/ @P1 BRA 0x210 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x960 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06e0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0700*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0710*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0720*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0730*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0740*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0760*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0770*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0780*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07a0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07d0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07e0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0810*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0820*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0830*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0840*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0860*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0870*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0880*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08a0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08d0*/ IMAD R22, R23, R22, R24 ; /* 0x0000001617167224 */
/* 0x004fc800078e0218 */
/*08e0*/ IMAD R16, R16, R25, R22 ; /* 0x0000001910107224 */
/* 0x008fc800078e0216 */
/*08f0*/ IMAD R16, R26, R27, R16 ; /* 0x0000001b1a107224 */
/* 0x020fc800078e0210 */
/*0900*/ IMAD R29, R14, R29, R16 ; /* 0x0000001d0e1d7224 */
/* 0x000fc800078e0210 */
/*0910*/ IMAD R18, R18, R28, R29 ; /* 0x0000001c12127224 */
/* 0x000fc800078e021d */
/*0920*/ IMAD R15, R20, R15, R18 ; /* 0x0000000f140f7224 */
/* 0x000fc800078e0212 */
/*0930*/ IMAD R24, R17, R8, R15 ; /* 0x0000000811187224 */
/* 0x010fe400078e020f */
/*0940*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0950*/ IMAD R24, R19, R21, R24 ; /* 0x0000001513187224 */
/* 0x000fe400078e0218 */
/*0960*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0990*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09b0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09c0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09d0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a00*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a30*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a60*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a70*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a90*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0aa0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x004fc800078e0218 */
/*0ad0*/ IMAD R18, R17, R19, R18 ; /* 0x0000001311127224 */
/* 0x008fe400078e0212 */
/*0ae0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0af0*/ IMAD R18, R21, R20, R18 ; /* 0x0000001415127224 */
/* 0x010fc800078e0212 */
/*0b00*/ IMAD R24, R23, R22, R18 ; /* 0x0000001617187224 */
/* 0x020fe200078e0212 */
/*0b10*/ @P0 BRA 0x980 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b20*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b30*/ @!P0 BRA 0xc30 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b40*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b50*/ IMAD R6, R3, c[0x0][0x178], R2 ; /* 0x00005e0003067a24 */
/* 0x000fe400078e0202 */
/*0b60*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b70*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b80*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0b90*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0ba0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bb0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0bd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0be0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bf0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c10*/ IMAD R24, R5, R2, R24 ; /* 0x0000000205187224 */
/* 0x004fc800078e0218 */
/*0c20*/ @P0 BRA 0xb90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c30*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c40*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c50*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c60*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Alexandre Maros - 2016
*
* Cuda Matrix Multiplication with Global Memory.
*
* nvcc cuda_matrix_global.cu -o cg.o
*
* Implemented by Alexandre Maros for learning purposes.
* A version of this code using Shared Memory is in here:
* https://github.com/alepmaros/cuda_matrix_multiplication
*
* Distributed under the MIT Lincese.
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
//32x32
#define NTHREADS_X 32
#define NTHREADS_Y 32
#define THREADS_PER_BLOCK NTHREADS_X * NTHREADS_Y
/* A macro used for error checking in CUDA function calls
* Credit to: http://stackoverflow.com/a/14038590 for the gpuErrchk macro.
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void matrix_mul(int *a, int *b, int *c, int a_ncolumns, int c_nlines, int c_ncolumns)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int line = blockIdx.y * blockDim.y + threadIdx.y;
if (column >= c_ncolumns || line >= c_nlines)
return;
int i, sum = 0;
int beginA = a_ncolumns * line;
int beginB = column;
for (i = 0; i < a_ncolumns; i++)
{
sum += a[beginA + i] * b[i * c_ncolumns + beginB];
}
c[line * c_ncolumns + column] = sum;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int a_nlines, a_ncolumns;
int b_nlines, b_ncolumns;
int c_nlines, c_ncolumns;
size_t a_size, b_size, c_size;
int i, j;
cudaEvent_t start, stop;
gpuErrchk( cudaEventCreate(&start) );
gpuErrchk( cudaEventCreate(&stop) );
scanf("%d", &a_nlines);
scanf("%d", &a_ncolumns);
scanf("%d", &b_nlines);
scanf("%d", &b_ncolumns);
c_nlines = a_nlines;
c_ncolumns = b_ncolumns;
#ifdef __DEBUG
printf("a_nlines: %d\na_ncolumns: %d\nb_nlines: %d\nb_ncolumns: %d\nc_nlines: %d\nc_ncolumns: %d\n", a_nlines, a_ncolumns, b_nlines, b_ncolumns, c_nlines, c_ncolumns);
#endif
if ( a_ncolumns != b_nlines )
{
printf("Number of columns in Matrix A should be equals to number of lines in Matrix B\n");
return EXIT_FAILURE;
}
a_size = a_nlines * a_ncolumns * sizeof(int);
b_size = b_nlines * b_ncolumns * sizeof(int);
c_size = c_nlines * c_ncolumns * sizeof(int);
gpuErrchk( cudaMalloc((void **) &d_a, a_size) );
gpuErrchk( cudaMalloc((void **) &d_b, b_size) );
gpuErrchk( cudaMalloc((void **) &d_c, c_size) );
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
memset(c, 0, c_nlines*c_ncolumns*sizeof(int));
for (i = 0; i < a_nlines; i++)
{
for (j = 0; j < a_ncolumns; j++)
{
scanf("%d", &a[i * a_ncolumns + j]);
}
}
for (i = 0; i < b_nlines; i++)
{
for (j = 0; j < b_ncolumns; j++)
{
scanf("%d", &b[i * b_ncolumns + j]);
}
}
gpuErrchk( cudaMemcpy(d_a, a, a_size, cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_b, b, b_size, cudaMemcpyHostToDevice) );
dim3 tbloco = dim3(
(int) std::ceil( (double) c_ncolumns / NTHREADS_X ),
(int) std::ceil ( (double) c_nlines / NTHREADS_Y ),
1
);
dim3 tthreads = dim3(
NTHREADS_X,
NTHREADS_Y,
1
);
#ifdef __DEBUG
printf("tbloco.x: %d tbloco.y: %d tbloco.z: %d\n", tbloco.x, tbloco.y, tbloco.z);
printf("tthreads.x: %d tthreads.y: %d\n", tthreads.x, tthreads.y);
#endif
cudaEventRecord(start);
// kernel call
matrix_mul<<<tbloco,tthreads>>>(d_a, d_b, d_c, a_ncolumns, c_nlines, c_ncolumns);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaEventRecord(stop) );
gpuErrchk( cudaMemcpy(c, d_c, c_size, cudaMemcpyDeviceToHost) );
gpuErrchk( cudaEventSynchronize(stop) );
#ifndef __NO_OUTPUT
// print Matrix
for (i = 0; i < c_nlines; i++)
{
for (j = 0; j < c_ncolumns; j++)
{
printf("%d ", c[i * c_ncolumns + j]);
}
printf("\n");
}
printf("\n");
#endif
#ifdef __TIME
float milliseconds = 0;
gpuErrchk( cudaEventElapsedTime(&milliseconds, start, stop) );
printf("%.5f\n", milliseconds);
#endif
free(a); free(b); free(c);
gpuErrchk( cudaFree(d_a) );
gpuErrchk( cudaFree(d_b) );
gpuErrchk( cudaFree(d_c) );
return 0;
} | .file "tmpxft_000c3dd8_00000000-6_mm_omp_vs_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
.type _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10matrix_mulPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
.globl _Z10matrix_mulPiS_S_iii
.type _Z10matrix_mulPiS_S_iii, @function
_Z10matrix_mulPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10matrix_mulPiS_S_iii, .-_Z10matrix_mulPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/roboGen8/MPPI-Codes/master/research/trial/mm_omp_vs_cuda.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d"
.section .rodata.str1.8
.align 8
.LC3:
.string "Number of columns in Matrix A should be equals to number of lines in Matrix B\n"
.section .rodata.str1.1
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rsi
leaq .LC2(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 60(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 64(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 68(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 56(%rsp), %eax
movl %eax, 12(%rsp)
movl 68(%rsp), %r15d
movl 60(%rsp), %edx
movl 64(%rsp), %eax
cmpl %eax, %edx
je .L20
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L19:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl 12(%rsp), %ecx
imull %ecx, %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %r14
movq %r14, 24(%rsp)
imull %r15d, %eax
cltq
leaq 0(,%rax,4), %r12
movq %r12, %r13
movq %r12, 32(%rsp)
movl %ecx, %eax
imull %r15d, %eax
cltq
leaq 0(,%rax,4), %rbp
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $97, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $98, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $99, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movl $0, %r13d
leaq .LC2(%rip), %r14
cmpl $0, 56(%rsp)
jle .L23
movl %r15d, 40(%rsp)
jmp .L22
.L24:
imull %r13d, %eax
addl %r15d, %eax
cltq
leaq (%r12,%rax,4), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %r15d
movl 60(%rsp), %eax
cmpl %r15d, %eax
jg .L24
.L25:
addl $1, %r13d
cmpl %r13d, 56(%rsp)
jle .L49
.L22:
movl 60(%rsp), %eax
movl $0, %r15d
testl %eax, %eax
jg .L24
jmp .L25
.L49:
movl 40(%rsp), %r15d
.L23:
movl $0, %r13d
leaq .LC2(%rip), %r14
cmpl $0, 64(%rsp)
jle .L27
movl %r15d, 40(%rsp)
jmp .L26
.L28:
imull %r13d, %eax
addl %r15d, %eax
cltq
leaq (%rbx,%rax,4), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %r15d
movl 68(%rsp), %eax
cmpl %r15d, %eax
jg .L28
.L29:
addl $1, %r13d
cmpl %r13d, 64(%rsp)
jle .L51
.L26:
movl 68(%rsp), %eax
movl $0, %r15d
testl %eax, %eax
jg .L28
jmp .L29
.L51:
movl 40(%rsp), %r15d
.L27:
movl $1, %ecx
movq 24(%rsp), %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $123, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq 32(%rsp), %rdx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $124, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
pxor %xmm0, %xmm0
cvtsi2sdl 12(%rsp), %xmm0
mulsd .LC4(%rip), %xmm0
call ceil@PLT
movsd %xmm0, 24(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC4(%rip), %xmm0
call ceil@PLT
cvttsd2sil %xmm0, %eax
movl %eax, 112(%rsp)
cvttsd2sil 24(%rsp), %eax
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl $32, 124(%rsp)
movl $32, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L30:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $147, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $148, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $149, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $150, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
cmpl $0, 12(%rsp)
jle .L31
movl $0, %ecx
movl $0, %r14d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC5(%rip), %r13
movq %r12, 32(%rsp)
movq %rbx, 40(%rsp)
movl %ecx, %r12d
jmp .L32
.L55:
movl %r15d, %r9d
movl 12(%rsp), %r8d
movl 60(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
jmp .L30
.L34:
movslq %r12d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L33:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L33
.L35:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r15d, %r12d
cmpl %r14d, 12(%rsp)
je .L52
.L32:
testl %r15d, %r15d
jg .L34
jmp .L35
.L52:
movq 32(%rsp), %r12
movq 40(%rsp), %rbx
.L31:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $174, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $175, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $176, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
jmp .L19
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10matrix_mulPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1067450368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Alexandre Maros - 2016
*
* Cuda Matrix Multiplication with Global Memory.
*
* nvcc cuda_matrix_global.cu -o cg.o
*
* Implemented by Alexandre Maros for learning purposes.
* A version of this code using Shared Memory is in here:
* https://github.com/alepmaros/cuda_matrix_multiplication
*
* Distributed under the MIT Lincese.
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
//32x32
#define NTHREADS_X 32
#define NTHREADS_Y 32
#define THREADS_PER_BLOCK NTHREADS_X * NTHREADS_Y
/* A macro used for error checking in CUDA function calls
* Credit to: http://stackoverflow.com/a/14038590 for the gpuErrchk macro.
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void matrix_mul(int *a, int *b, int *c, int a_ncolumns, int c_nlines, int c_ncolumns)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int line = blockIdx.y * blockDim.y + threadIdx.y;
if (column >= c_ncolumns || line >= c_nlines)
return;
int i, sum = 0;
int beginA = a_ncolumns * line;
int beginB = column;
for (i = 0; i < a_ncolumns; i++)
{
sum += a[beginA + i] * b[i * c_ncolumns + beginB];
}
c[line * c_ncolumns + column] = sum;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int a_nlines, a_ncolumns;
int b_nlines, b_ncolumns;
int c_nlines, c_ncolumns;
size_t a_size, b_size, c_size;
int i, j;
cudaEvent_t start, stop;
gpuErrchk( cudaEventCreate(&start) );
gpuErrchk( cudaEventCreate(&stop) );
scanf("%d", &a_nlines);
scanf("%d", &a_ncolumns);
scanf("%d", &b_nlines);
scanf("%d", &b_ncolumns);
c_nlines = a_nlines;
c_ncolumns = b_ncolumns;
#ifdef __DEBUG
printf("a_nlines: %d\na_ncolumns: %d\nb_nlines: %d\nb_ncolumns: %d\nc_nlines: %d\nc_ncolumns: %d\n", a_nlines, a_ncolumns, b_nlines, b_ncolumns, c_nlines, c_ncolumns);
#endif
if ( a_ncolumns != b_nlines )
{
printf("Number of columns in Matrix A should be equals to number of lines in Matrix B\n");
return EXIT_FAILURE;
}
a_size = a_nlines * a_ncolumns * sizeof(int);
b_size = b_nlines * b_ncolumns * sizeof(int);
c_size = c_nlines * c_ncolumns * sizeof(int);
gpuErrchk( cudaMalloc((void **) &d_a, a_size) );
gpuErrchk( cudaMalloc((void **) &d_b, b_size) );
gpuErrchk( cudaMalloc((void **) &d_c, c_size) );
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
memset(c, 0, c_nlines*c_ncolumns*sizeof(int));
for (i = 0; i < a_nlines; i++)
{
for (j = 0; j < a_ncolumns; j++)
{
scanf("%d", &a[i * a_ncolumns + j]);
}
}
for (i = 0; i < b_nlines; i++)
{
for (j = 0; j < b_ncolumns; j++)
{
scanf("%d", &b[i * b_ncolumns + j]);
}
}
gpuErrchk( cudaMemcpy(d_a, a, a_size, cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(d_b, b, b_size, cudaMemcpyHostToDevice) );
dim3 tbloco = dim3(
(int) std::ceil( (double) c_ncolumns / NTHREADS_X ),
(int) std::ceil ( (double) c_nlines / NTHREADS_Y ),
1
);
dim3 tthreads = dim3(
NTHREADS_X,
NTHREADS_Y,
1
);
#ifdef __DEBUG
printf("tbloco.x: %d tbloco.y: %d tbloco.z: %d\n", tbloco.x, tbloco.y, tbloco.z);
printf("tthreads.x: %d tthreads.y: %d\n", tthreads.x, tthreads.y);
#endif
cudaEventRecord(start);
// kernel call
matrix_mul<<<tbloco,tthreads>>>(d_a, d_b, d_c, a_ncolumns, c_nlines, c_ncolumns);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaEventRecord(stop) );
gpuErrchk( cudaMemcpy(c, d_c, c_size, cudaMemcpyDeviceToHost) );
gpuErrchk( cudaEventSynchronize(stop) );
#ifndef __NO_OUTPUT
// print Matrix
for (i = 0; i < c_nlines; i++)
{
for (j = 0; j < c_ncolumns; j++)
{
printf("%d ", c[i * c_ncolumns + j]);
}
printf("\n");
}
printf("\n");
#endif
#ifdef __TIME
float milliseconds = 0;
gpuErrchk( cudaEventElapsedTime(&milliseconds, start, stop) );
printf("%.5f\n", milliseconds);
#endif
free(a); free(b); free(c);
gpuErrchk( cudaFree(d_a) );
gpuErrchk( cudaFree(d_b) );
gpuErrchk( cudaFree(d_c) );
return 0;
} | /*
* Alexandre Maros - 2016
*
* Cuda Matrix Multiplication with Global Memory.
*
* nvcc cuda_matrix_global.cu -o cg.o
*
* Implemented by Alexandre Maros for learning purposes.
* A version of this code using Shared Memory is in here:
* https://github.com/alepmaros/cuda_matrix_multiplication
*
* Distributed under the MIT Lincese.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
//32x32
#define NTHREADS_X 32
#define NTHREADS_Y 32
#define THREADS_PER_BLOCK NTHREADS_X * NTHREADS_Y
/* A macro used for error checking in CUDA function calls
* Credit to: http://stackoverflow.com/a/14038590 for the gpuErrchk macro.
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void matrix_mul(int *a, int *b, int *c, int a_ncolumns, int c_nlines, int c_ncolumns)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int line = blockIdx.y * blockDim.y + threadIdx.y;
if (column >= c_ncolumns || line >= c_nlines)
return;
int i, sum = 0;
int beginA = a_ncolumns * line;
int beginB = column;
for (i = 0; i < a_ncolumns; i++)
{
sum += a[beginA + i] * b[i * c_ncolumns + beginB];
}
c[line * c_ncolumns + column] = sum;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int a_nlines, a_ncolumns;
int b_nlines, b_ncolumns;
int c_nlines, c_ncolumns;
size_t a_size, b_size, c_size;
int i, j;
hipEvent_t start, stop;
gpuErrchk( hipEventCreate(&start) );
gpuErrchk( hipEventCreate(&stop) );
scanf("%d", &a_nlines);
scanf("%d", &a_ncolumns);
scanf("%d", &b_nlines);
scanf("%d", &b_ncolumns);
c_nlines = a_nlines;
c_ncolumns = b_ncolumns;
#ifdef __DEBUG
printf("a_nlines: %d\na_ncolumns: %d\nb_nlines: %d\nb_ncolumns: %d\nc_nlines: %d\nc_ncolumns: %d\n", a_nlines, a_ncolumns, b_nlines, b_ncolumns, c_nlines, c_ncolumns);
#endif
if ( a_ncolumns != b_nlines )
{
printf("Number of columns in Matrix A should be equals to number of lines in Matrix B\n");
return EXIT_FAILURE;
}
a_size = a_nlines * a_ncolumns * sizeof(int);
b_size = b_nlines * b_ncolumns * sizeof(int);
c_size = c_nlines * c_ncolumns * sizeof(int);
gpuErrchk( hipMalloc((void **) &d_a, a_size) );
gpuErrchk( hipMalloc((void **) &d_b, b_size) );
gpuErrchk( hipMalloc((void **) &d_c, c_size) );
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
memset(c, 0, c_nlines*c_ncolumns*sizeof(int));
for (i = 0; i < a_nlines; i++)
{
for (j = 0; j < a_ncolumns; j++)
{
scanf("%d", &a[i * a_ncolumns + j]);
}
}
for (i = 0; i < b_nlines; i++)
{
for (j = 0; j < b_ncolumns; j++)
{
scanf("%d", &b[i * b_ncolumns + j]);
}
}
gpuErrchk( hipMemcpy(d_a, a, a_size, hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_b, b, b_size, hipMemcpyHostToDevice) );
dim3 tbloco = dim3(
(int) std::ceil( (double) c_ncolumns / NTHREADS_X ),
(int) std::ceil ( (double) c_nlines / NTHREADS_Y ),
1
);
dim3 tthreads = dim3(
NTHREADS_X,
NTHREADS_Y,
1
);
#ifdef __DEBUG
printf("tbloco.x: %d tbloco.y: %d tbloco.z: %d\n", tbloco.x, tbloco.y, tbloco.z);
printf("tthreads.x: %d tthreads.y: %d\n", tthreads.x, tthreads.y);
#endif
hipEventRecord(start);
// kernel call
matrix_mul<<<tbloco,tthreads>>>(d_a, d_b, d_c, a_ncolumns, c_nlines, c_ncolumns);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipEventRecord(stop) );
gpuErrchk( hipMemcpy(c, d_c, c_size, hipMemcpyDeviceToHost) );
gpuErrchk( hipEventSynchronize(stop) );
#ifndef __NO_OUTPUT
// print Matrix
for (i = 0; i < c_nlines; i++)
{
for (j = 0; j < c_ncolumns; j++)
{
printf("%d ", c[i * c_ncolumns + j]);
}
printf("\n");
}
printf("\n");
#endif
#ifdef __TIME
float milliseconds = 0;
gpuErrchk( hipEventElapsedTime(&milliseconds, start, stop) );
printf("%.5f\n", milliseconds);
#endif
free(a); free(b); free(c);
gpuErrchk( hipFree(d_a) );
gpuErrchk( hipFree(d_b) );
gpuErrchk( hipFree(d_c) );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Alexandre Maros - 2016
*
* Cuda Matrix Multiplication with Global Memory.
*
* nvcc cuda_matrix_global.cu -o cg.o
*
* Implemented by Alexandre Maros for learning purposes.
* A version of this code using Shared Memory is in here:
* https://github.com/alepmaros/cuda_matrix_multiplication
*
* Distributed under the MIT Lincese.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
//32x32
#define NTHREADS_X 32
#define NTHREADS_Y 32
#define THREADS_PER_BLOCK NTHREADS_X * NTHREADS_Y
/* A macro used for error checking in CUDA function calls
* Credit to: http://stackoverflow.com/a/14038590 for the gpuErrchk macro.
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void matrix_mul(int *a, int *b, int *c, int a_ncolumns, int c_nlines, int c_ncolumns)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int line = blockIdx.y * blockDim.y + threadIdx.y;
if (column >= c_ncolumns || line >= c_nlines)
return;
int i, sum = 0;
int beginA = a_ncolumns * line;
int beginB = column;
for (i = 0; i < a_ncolumns; i++)
{
sum += a[beginA + i] * b[i * c_ncolumns + beginB];
}
c[line * c_ncolumns + column] = sum;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int a_nlines, a_ncolumns;
int b_nlines, b_ncolumns;
int c_nlines, c_ncolumns;
size_t a_size, b_size, c_size;
int i, j;
hipEvent_t start, stop;
gpuErrchk( hipEventCreate(&start) );
gpuErrchk( hipEventCreate(&stop) );
scanf("%d", &a_nlines);
scanf("%d", &a_ncolumns);
scanf("%d", &b_nlines);
scanf("%d", &b_ncolumns);
c_nlines = a_nlines;
c_ncolumns = b_ncolumns;
#ifdef __DEBUG
printf("a_nlines: %d\na_ncolumns: %d\nb_nlines: %d\nb_ncolumns: %d\nc_nlines: %d\nc_ncolumns: %d\n", a_nlines, a_ncolumns, b_nlines, b_ncolumns, c_nlines, c_ncolumns);
#endif
if ( a_ncolumns != b_nlines )
{
printf("Number of columns in Matrix A should be equals to number of lines in Matrix B\n");
return EXIT_FAILURE;
}
a_size = a_nlines * a_ncolumns * sizeof(int);
b_size = b_nlines * b_ncolumns * sizeof(int);
c_size = c_nlines * c_ncolumns * sizeof(int);
gpuErrchk( hipMalloc((void **) &d_a, a_size) );
gpuErrchk( hipMalloc((void **) &d_b, b_size) );
gpuErrchk( hipMalloc((void **) &d_c, c_size) );
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
memset(c, 0, c_nlines*c_ncolumns*sizeof(int));
for (i = 0; i < a_nlines; i++)
{
for (j = 0; j < a_ncolumns; j++)
{
scanf("%d", &a[i * a_ncolumns + j]);
}
}
for (i = 0; i < b_nlines; i++)
{
for (j = 0; j < b_ncolumns; j++)
{
scanf("%d", &b[i * b_ncolumns + j]);
}
}
gpuErrchk( hipMemcpy(d_a, a, a_size, hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_b, b, b_size, hipMemcpyHostToDevice) );
dim3 tbloco = dim3(
(int) std::ceil( (double) c_ncolumns / NTHREADS_X ),
(int) std::ceil ( (double) c_nlines / NTHREADS_Y ),
1
);
dim3 tthreads = dim3(
NTHREADS_X,
NTHREADS_Y,
1
);
#ifdef __DEBUG
printf("tbloco.x: %d tbloco.y: %d tbloco.z: %d\n", tbloco.x, tbloco.y, tbloco.z);
printf("tthreads.x: %d tthreads.y: %d\n", tthreads.x, tthreads.y);
#endif
hipEventRecord(start);
// kernel call
matrix_mul<<<tbloco,tthreads>>>(d_a, d_b, d_c, a_ncolumns, c_nlines, c_ncolumns);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipEventRecord(stop) );
gpuErrchk( hipMemcpy(c, d_c, c_size, hipMemcpyDeviceToHost) );
gpuErrchk( hipEventSynchronize(stop) );
#ifndef __NO_OUTPUT
// print Matrix
for (i = 0; i < c_nlines; i++)
{
for (j = 0; j < c_ncolumns; j++)
{
printf("%d ", c[i * c_ncolumns + j]);
}
printf("\n");
}
printf("\n");
#endif
#ifdef __TIME
float milliseconds = 0;
gpuErrchk( hipEventElapsedTime(&milliseconds, start, stop) );
printf("%.5f\n", milliseconds);
#endif
free(a); free(b); free(c);
gpuErrchk( hipFree(d_a) );
gpuErrchk( hipFree(d_b) );
gpuErrchk( hipFree(d_c) );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_mulPiS_S_iii
.globl _Z10matrix_mulPiS_S_iii
.p2align 8
.type _Z10matrix_mulPiS_S_iii,@function
_Z10matrix_mulPiS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s3, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_mulPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_mulPiS_S_iii, .Lfunc_end0-_Z10matrix_mulPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_mulPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_mulPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Alexandre Maros - 2016
*
* Cuda Matrix Multiplication with Global Memory.
*
* nvcc cuda_matrix_global.cu -o cg.o
*
* Implemented by Alexandre Maros for learning purposes.
* A version of this code using Shared Memory is in here:
* https://github.com/alepmaros/cuda_matrix_multiplication
*
* Distributed under the MIT Lincese.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
//32x32
#define NTHREADS_X 32
#define NTHREADS_Y 32
#define THREADS_PER_BLOCK NTHREADS_X * NTHREADS_Y
/* A macro used for error checking in CUDA function calls
* Credit to: http://stackoverflow.com/a/14038590 for the gpuErrchk macro.
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void matrix_mul(int *a, int *b, int *c, int a_ncolumns, int c_nlines, int c_ncolumns)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int line = blockIdx.y * blockDim.y + threadIdx.y;
if (column >= c_ncolumns || line >= c_nlines)
return;
int i, sum = 0;
int beginA = a_ncolumns * line;
int beginB = column;
for (i = 0; i < a_ncolumns; i++)
{
sum += a[beginA + i] * b[i * c_ncolumns + beginB];
}
c[line * c_ncolumns + column] = sum;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int a_nlines, a_ncolumns;
int b_nlines, b_ncolumns;
int c_nlines, c_ncolumns;
size_t a_size, b_size, c_size;
int i, j;
hipEvent_t start, stop;
gpuErrchk( hipEventCreate(&start) );
gpuErrchk( hipEventCreate(&stop) );
scanf("%d", &a_nlines);
scanf("%d", &a_ncolumns);
scanf("%d", &b_nlines);
scanf("%d", &b_ncolumns);
c_nlines = a_nlines;
c_ncolumns = b_ncolumns;
#ifdef __DEBUG
printf("a_nlines: %d\na_ncolumns: %d\nb_nlines: %d\nb_ncolumns: %d\nc_nlines: %d\nc_ncolumns: %d\n", a_nlines, a_ncolumns, b_nlines, b_ncolumns, c_nlines, c_ncolumns);
#endif
if ( a_ncolumns != b_nlines )
{
printf("Number of columns in Matrix A should be equals to number of lines in Matrix B\n");
return EXIT_FAILURE;
}
a_size = a_nlines * a_ncolumns * sizeof(int);
b_size = b_nlines * b_ncolumns * sizeof(int);
c_size = c_nlines * c_ncolumns * sizeof(int);
gpuErrchk( hipMalloc((void **) &d_a, a_size) );
gpuErrchk( hipMalloc((void **) &d_b, b_size) );
gpuErrchk( hipMalloc((void **) &d_c, c_size) );
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
memset(c, 0, c_nlines*c_ncolumns*sizeof(int));
for (i = 0; i < a_nlines; i++)
{
for (j = 0; j < a_ncolumns; j++)
{
scanf("%d", &a[i * a_ncolumns + j]);
}
}
for (i = 0; i < b_nlines; i++)
{
for (j = 0; j < b_ncolumns; j++)
{
scanf("%d", &b[i * b_ncolumns + j]);
}
}
gpuErrchk( hipMemcpy(d_a, a, a_size, hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(d_b, b, b_size, hipMemcpyHostToDevice) );
dim3 tbloco = dim3(
(int) std::ceil( (double) c_ncolumns / NTHREADS_X ),
(int) std::ceil ( (double) c_nlines / NTHREADS_Y ),
1
);
dim3 tthreads = dim3(
NTHREADS_X,
NTHREADS_Y,
1
);
#ifdef __DEBUG
printf("tbloco.x: %d tbloco.y: %d tbloco.z: %d\n", tbloco.x, tbloco.y, tbloco.z);
printf("tthreads.x: %d tthreads.y: %d\n", tthreads.x, tthreads.y);
#endif
hipEventRecord(start);
// kernel call
matrix_mul<<<tbloco,tthreads>>>(d_a, d_b, d_c, a_ncolumns, c_nlines, c_ncolumns);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipEventRecord(stop) );
gpuErrchk( hipMemcpy(c, d_c, c_size, hipMemcpyDeviceToHost) );
gpuErrchk( hipEventSynchronize(stop) );
#ifndef __NO_OUTPUT
// print Matrix
for (i = 0; i < c_nlines; i++)
{
for (j = 0; j < c_ncolumns; j++)
{
printf("%d ", c[i * c_ncolumns + j]);
}
printf("\n");
}
printf("\n");
#endif
#ifdef __TIME
float milliseconds = 0;
gpuErrchk( hipEventElapsedTime(&milliseconds, start, stop) );
printf("%.5f\n", milliseconds);
#endif
free(a); free(b); free(c);
gpuErrchk( hipFree(d_a) );
gpuErrchk( hipFree(d_b) );
gpuErrchk( hipFree(d_c) );
return 0;
} | .text
.file "mm_omp_vs_cuda.hip"
.globl _Z25__device_stub__matrix_mulPiS_S_iii # -- Begin function _Z25__device_stub__matrix_mulPiS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__matrix_mulPiS_S_iii,@function
_Z25__device_stub__matrix_mulPiS_S_iii: # @_Z25__device_stub__matrix_mulPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10matrix_mulPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPiS_S_iii, .Lfunc_end0-_Z25__device_stub__matrix_mulPiS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fa0000000000000 # double 0.03125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 96(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 80(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit66
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq %rsp, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %eax
movl 8(%rsp), %ebx
cmpl %ebx, %eax
jne .LBB1_6
# %bb.8:
movl 12(%rsp), %ecx
movl 4(%rsp), %r12d
movq %rcx, 16(%rsp) # 8-byte Spill
imull %ecx, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_Z9gpuAssert10hipError_tPKcib.exit68
imull %r12d, %ebx
movslq %ebx, %r15
shlq $2, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit70
movl %r12d, %eax
imull 16(%rsp), %eax # 4-byte Folded Reload
movslq %eax, %rbp
shlq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.14: # %_Z9gpuAssert10hipError_tPKcib.exit72
movq %r14, 24(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r15, 88(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbp, %rdx
callq memset@PLT
cmpl $0, 12(%rsp)
jle .LBB1_20
# %bb.15: # %.preheader95.preheader
xorl %r13d, %r13d
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_19: # %._crit_edge
# in Loop: Header=BB1_16 Depth=1
incl %r13d
cmpl 12(%rsp), %r13d
jge .LBB1_20
.LBB1_16: # %.preheader95
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movl (%rsp), %eax
testl %eax, %eax
jle .LBB1_19
# %bb.17: # %.lr.ph.preheader
# in Loop: Header=BB1_16 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_18: # %.lr.ph
# Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
imull %r13d, %eax
cltq
addq %r15, %rax
leaq (%rbx,%rax,4), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB1_18
jmp .LBB1_19
.LBB1_6:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ecx
jmp .LBB1_7
.LBB1_20: # %.preheader94
cmpl $0, 8(%rsp)
jle .LBB1_26
# %bb.21: # %.preheader93.preheader
xorl %r13d, %r13d
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_25: # %._crit_edge100
# in Loop: Header=BB1_22 Depth=1
incl %r13d
cmpl 8(%rsp), %r13d
jge .LBB1_26
.LBB1_22: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_25
# %bb.23: # %.lr.ph99.preheader
# in Loop: Header=BB1_22 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_24: # %.lr.ph99
# Parent Loop BB1_22 Depth=1
# => This Inner Loop Header: Depth=2
imull %r13d, %eax
cltq
addq %r15, %rax
leaq (%r14,%rax,4), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB1_24
jmp .LBB1_25
.LBB1_26: # %._crit_edge102
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq 24(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit74
movq 48(%rsp), %rdi
movq %r14, %rsi
movq 88(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_29
# %bb.30: # %_Z9gpuAssert10hipError_tPKcib.exit76
cvtsi2sd %r12d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
xorps %xmm0, %xmm0
cvtsi2sdl 16(%rsp), %xmm0 # 4-byte Folded Reload
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r13d
shlq $32, %r13
orq %r15, %r13
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 76(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 72(%rsp)
movl %r12d, 68(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z10matrix_mulPiS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_32:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_33
# %bb.34: # %_Z9gpuAssert10hipError_tPKcib.exit78
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_35
# %bb.36: # %_Z9gpuAssert10hipError_tPKcib.exit80
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_37
# %bb.38: # %_Z9gpuAssert10hipError_tPKcib.exit82
movq %rbx, 24(%rsp) # 8-byte Spill
movq 80(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_51
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit84.preheader
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB1_45
# %bb.40: # %.preheader.lr.ph
xorl %r13d, %r13d
xorl %r15d, %r15d
jmp .LBB1_41
.p2align 4, 0x90
.LBB1_44: # %_Z9gpuAssert10hipError_tPKcib.exit84
# in Loop: Header=BB1_41 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %r13d
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
movq %rbx, %r12
je .LBB1_45
.LBB1_41: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_43 Depth 2
testl %r12d, %r12d
movq %r12, %rbx
jle .LBB1_44
# %bb.42: # %.lr.ph104
# in Loop: Header=BB1_41 Depth=1
movl %r13d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_43: # Parent Loop BB1_41 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %rbx
jne .LBB1_43
jmp .LBB1_44
.LBB1_45: # %_Z9gpuAssert10hipError_tPKcib.exit84._crit_edge
movl $10, %edi
callq putchar@PLT
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z9gpuAssert10hipError_tPKcib.exit86
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z9gpuAssert10hipError_tPKcib.exit88
movq 40(%rsp), %rdi
callq hipFree
xorl %ecx, %ecx
testl %eax, %eax
jne .LBB1_50
.LBB1_7: # %_Z9gpuAssert10hipError_tPKcib.exit90
movl %ecx, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $99, %r8d
jmp .LBB1_2
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $100, %r8d
jmp .LBB1_2
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $101, %r8d
jmp .LBB1_2
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB1_2
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB1_2
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $149, %r8d
jmp .LBB1_2
.LBB1_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $150, %r8d
jmp .LBB1_2
.LBB1_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $151, %r8d
jmp .LBB1_2
.LBB1_51:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $152, %r8d
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $176, %r8d
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $177, %r8d
jmp .LBB1_2
.LBB1_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $178, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_mulPiS_S_iii,@object # @_Z10matrix_mulPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPiS_S_iii
.p2align 3, 0x0
_Z10matrix_mulPiS_S_iii:
.quad _Z25__device_stub__matrix_mulPiS_S_iii
.size _Z10matrix_mulPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/roboGen8/MPPI-Codes/master/research/trial/mm_omp_vs_cuda.hip"
.size .L.str, 118
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_mulPiS_S_iii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Number of columns in Matrix A should be equals to number of lines in Matrix B"
.size .Lstr, 78
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_mulPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrix_mulPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc30 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb20 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*01a0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01c0*/ @!P0 BRA 0x980 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6b0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0270*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0290*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02b0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02c0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02d0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02e0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02f0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0300*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0310*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0320*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0340*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0360*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0370*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0380*/ IMAD R16, R21, R20, R24 ; /* 0x0000001415107224 */
/* 0x004fe400078e0218 */
/*0390*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03b0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03d0*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x008fe400078e0210 */
/*03e0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03f0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0400*/ IMAD R26, R26, R27, R16 ; /* 0x0000001b1a1a7224 */
/* 0x010fe200078e0210 */
/*0410*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0420*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0430*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0440*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x020fe400078e021a */
/*0450*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0460*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0470*/ IMAD R26, R9, R8, R26 ; /* 0x00000008091a7224 */
/* 0x000fe200078e021a */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0490*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04c0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04d0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x000fe400078e021a */
/*04e0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04f0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0500*/ IMAD R26, R21, R20, R26 ; /* 0x00000014151a7224 */
/* 0x004fc400078e021a */
/*0510*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD R28, R29, R28, R26 ; /* 0x0000001c1d1c7224 */
/* 0x000fe400078e021a */
/*0540*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0550*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0570*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0580*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0590*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05a0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05b0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05c0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x000fc800078e021c */
/*05d0*/ IMAD R25, R16, R25, R14 ; /* 0x0000001910197224 */
/* 0x010fe200078e020e */
/*05e0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ IMAD R18, R18, R22, R25 ; /* 0x0000001612127224 */
/* 0x020fe200078e0219 */
/*0600*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0610*/ IMAD R15, R24, R15, R18 ; /* 0x0000000f180f7224 */
/* 0x000fe200078e0212 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD R10, R10, R17, R15 ; /* 0x000000110a0a7224 */
/* 0x004fc800078e020f */
/*0670*/ IMAD R10, R20, R29, R10 ; /* 0x0000001d140a7224 */
/* 0x000fc800078e020a */
/*0680*/ IMAD R10, R19, R21, R10 ; /* 0x00000015130a7224 */
/* 0x000fc800078e020a */
/*0690*/ IMAD R24, R11, R26, R10 ; /* 0x0000001a0b187224 */
/* 0x008fe200078e020a */
/*06a0*/ @P1 BRA 0x210 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x960 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06e0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0700*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0710*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0720*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0730*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0740*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0760*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0770*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0780*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07a0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07d0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07e0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0810*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0820*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0830*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0840*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0860*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0870*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0880*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08a0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08d0*/ IMAD R22, R23, R22, R24 ; /* 0x0000001617167224 */
/* 0x004fc800078e0218 */
/*08e0*/ IMAD R16, R16, R25, R22 ; /* 0x0000001910107224 */
/* 0x008fc800078e0216 */
/*08f0*/ IMAD R16, R26, R27, R16 ; /* 0x0000001b1a107224 */
/* 0x020fc800078e0210 */
/*0900*/ IMAD R29, R14, R29, R16 ; /* 0x0000001d0e1d7224 */
/* 0x000fc800078e0210 */
/*0910*/ IMAD R18, R18, R28, R29 ; /* 0x0000001c12127224 */
/* 0x000fc800078e021d */
/*0920*/ IMAD R15, R20, R15, R18 ; /* 0x0000000f140f7224 */
/* 0x000fc800078e0212 */
/*0930*/ IMAD R24, R17, R8, R15 ; /* 0x0000000811187224 */
/* 0x010fe400078e020f */
/*0940*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0950*/ IMAD R24, R19, R21, R24 ; /* 0x0000001513187224 */
/* 0x000fe400078e0218 */
/*0960*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0990*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09b0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09c0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09d0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a00*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a30*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a60*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a70*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a90*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0aa0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x004fc800078e0218 */
/*0ad0*/ IMAD R18, R17, R19, R18 ; /* 0x0000001311127224 */
/* 0x008fe400078e0212 */
/*0ae0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0af0*/ IMAD R18, R21, R20, R18 ; /* 0x0000001415127224 */
/* 0x010fc800078e0212 */
/*0b00*/ IMAD R24, R23, R22, R18 ; /* 0x0000001617187224 */
/* 0x020fe200078e0212 */
/*0b10*/ @P0 BRA 0x980 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b20*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b30*/ @!P0 BRA 0xc30 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b40*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b50*/ IMAD R6, R3, c[0x0][0x178], R2 ; /* 0x00005e0003067a24 */
/* 0x000fe400078e0202 */
/*0b60*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b70*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b80*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0b90*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0ba0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bb0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0bd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0be0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bf0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c10*/ IMAD R24, R5, R2, R24 ; /* 0x0000000205187224 */
/* 0x004fc800078e0218 */
/*0c20*/ @P0 BRA 0xb90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c30*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c40*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c50*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c60*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_mulPiS_S_iii
.globl _Z10matrix_mulPiS_S_iii
.p2align 8
.type _Z10matrix_mulPiS_S_iii,@function
_Z10matrix_mulPiS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s3, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_mulPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_mulPiS_S_iii, .Lfunc_end0-_Z10matrix_mulPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_mulPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_mulPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3dd8_00000000-6_mm_omp_vs_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
.type _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10matrix_mulPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
.globl _Z10matrix_mulPiS_S_iii
.type _Z10matrix_mulPiS_S_iii, @function
_Z10matrix_mulPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10matrix_mulPiS_S_iii, .-_Z10matrix_mulPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/roboGen8/MPPI-Codes/master/research/trial/mm_omp_vs_cuda.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d"
.section .rodata.str1.8
.align 8
.LC3:
.string "Number of columns in Matrix A should be equals to number of lines in Matrix B\n"
.section .rodata.str1.1
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rsi
leaq .LC2(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 60(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 64(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 68(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 56(%rsp), %eax
movl %eax, 12(%rsp)
movl 68(%rsp), %r15d
movl 60(%rsp), %edx
movl 64(%rsp), %eax
cmpl %eax, %edx
je .L20
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L19:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl 12(%rsp), %ecx
imull %ecx, %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %r14
movq %r14, 24(%rsp)
imull %r15d, %eax
cltq
leaq 0(,%rax,4), %r12
movq %r12, %r13
movq %r12, 32(%rsp)
movl %ecx, %eax
imull %r15d, %eax
cltq
leaq 0(,%rax,4), %rbp
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $97, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $98, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $99, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movl $0, %r13d
leaq .LC2(%rip), %r14
cmpl $0, 56(%rsp)
jle .L23
movl %r15d, 40(%rsp)
jmp .L22
.L24:
imull %r13d, %eax
addl %r15d, %eax
cltq
leaq (%r12,%rax,4), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %r15d
movl 60(%rsp), %eax
cmpl %r15d, %eax
jg .L24
.L25:
addl $1, %r13d
cmpl %r13d, 56(%rsp)
jle .L49
.L22:
movl 60(%rsp), %eax
movl $0, %r15d
testl %eax, %eax
jg .L24
jmp .L25
.L49:
movl 40(%rsp), %r15d
.L23:
movl $0, %r13d
leaq .LC2(%rip), %r14
cmpl $0, 64(%rsp)
jle .L27
movl %r15d, 40(%rsp)
jmp .L26
.L28:
imull %r13d, %eax
addl %r15d, %eax
cltq
leaq (%rbx,%rax,4), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %r15d
movl 68(%rsp), %eax
cmpl %r15d, %eax
jg .L28
.L29:
addl $1, %r13d
cmpl %r13d, 64(%rsp)
jle .L51
.L26:
movl 68(%rsp), %eax
movl $0, %r15d
testl %eax, %eax
jg .L28
jmp .L29
.L51:
movl 40(%rsp), %r15d
.L27:
movl $1, %ecx
movq 24(%rsp), %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $123, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq 32(%rsp), %rdx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $124, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
pxor %xmm0, %xmm0
cvtsi2sdl 12(%rsp), %xmm0
mulsd .LC4(%rip), %xmm0
call ceil@PLT
movsd %xmm0, 24(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC4(%rip), %xmm0
call ceil@PLT
cvttsd2sil %xmm0, %eax
movl %eax, 112(%rsp)
cvttsd2sil 24(%rsp), %eax
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl $32, 124(%rsp)
movl $32, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L30:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $147, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $148, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $149, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $150, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
cmpl $0, 12(%rsp)
jle .L31
movl $0, %ecx
movl $0, %r14d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC5(%rip), %r13
movq %r12, 32(%rsp)
movq %rbx, 40(%rsp)
movl %ecx, %r12d
jmp .L32
.L55:
movl %r15d, %r9d
movl 12(%rsp), %r8d
movl 60(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z37__device_stub__Z10matrix_mulPiS_S_iiiPiS_S_iii
jmp .L30
.L34:
movslq %r12d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L33:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L33
.L35:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r15d, %r12d
cmpl %r14d, 12(%rsp)
je .L52
.L32:
testl %r15d, %r15d
jg .L34
jmp .L35
.L52:
movq 32(%rsp), %r12
movq 40(%rsp), %rbx
.L31:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $174, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $175, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $176, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %eax
jmp .L19
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10matrix_mulPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1067450368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm_omp_vs_cuda.hip"
.globl _Z25__device_stub__matrix_mulPiS_S_iii # -- Begin function _Z25__device_stub__matrix_mulPiS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__matrix_mulPiS_S_iii,@function
_Z25__device_stub__matrix_mulPiS_S_iii: # @_Z25__device_stub__matrix_mulPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10matrix_mulPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPiS_S_iii, .Lfunc_end0-_Z25__device_stub__matrix_mulPiS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fa0000000000000 # double 0.03125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 96(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 80(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit66
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq %rsp, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %eax
movl 8(%rsp), %ebx
cmpl %ebx, %eax
jne .LBB1_6
# %bb.8:
movl 12(%rsp), %ecx
movl 4(%rsp), %r12d
movq %rcx, 16(%rsp) # 8-byte Spill
imull %ecx, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_Z9gpuAssert10hipError_tPKcib.exit68
imull %r12d, %ebx
movslq %ebx, %r15
shlq $2, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit70
movl %r12d, %eax
imull 16(%rsp), %eax # 4-byte Folded Reload
movslq %eax, %rbp
shlq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.14: # %_Z9gpuAssert10hipError_tPKcib.exit72
movq %r14, 24(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r15, 88(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbp, %rdx
callq memset@PLT
cmpl $0, 12(%rsp)
jle .LBB1_20
# %bb.15: # %.preheader95.preheader
xorl %r13d, %r13d
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_19: # %._crit_edge
# in Loop: Header=BB1_16 Depth=1
incl %r13d
cmpl 12(%rsp), %r13d
jge .LBB1_20
.LBB1_16: # %.preheader95
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movl (%rsp), %eax
testl %eax, %eax
jle .LBB1_19
# %bb.17: # %.lr.ph.preheader
# in Loop: Header=BB1_16 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_18: # %.lr.ph
# Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
imull %r13d, %eax
cltq
addq %r15, %rax
leaq (%rbx,%rax,4), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB1_18
jmp .LBB1_19
.LBB1_6:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ecx
jmp .LBB1_7
.LBB1_20: # %.preheader94
cmpl $0, 8(%rsp)
jle .LBB1_26
# %bb.21: # %.preheader93.preheader
xorl %r13d, %r13d
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_25: # %._crit_edge100
# in Loop: Header=BB1_22 Depth=1
incl %r13d
cmpl 8(%rsp), %r13d
jge .LBB1_26
.LBB1_22: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_25
# %bb.23: # %.lr.ph99.preheader
# in Loop: Header=BB1_22 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_24: # %.lr.ph99
# Parent Loop BB1_22 Depth=1
# => This Inner Loop Header: Depth=2
imull %r13d, %eax
cltq
addq %r15, %rax
leaq (%r14,%rax,4), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB1_24
jmp .LBB1_25
.LBB1_26: # %._crit_edge102
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq 24(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit74
movq 48(%rsp), %rdi
movq %r14, %rsi
movq 88(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_29
# %bb.30: # %_Z9gpuAssert10hipError_tPKcib.exit76
cvtsi2sd %r12d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
xorps %xmm0, %xmm0
cvtsi2sdl 16(%rsp), %xmm0 # 4-byte Folded Reload
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r13d
shlq $32, %r13
orq %r15, %r13
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 76(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 72(%rsp)
movl %r12d, 68(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z10matrix_mulPiS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_32:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_33
# %bb.34: # %_Z9gpuAssert10hipError_tPKcib.exit78
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_35
# %bb.36: # %_Z9gpuAssert10hipError_tPKcib.exit80
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_37
# %bb.38: # %_Z9gpuAssert10hipError_tPKcib.exit82
movq %rbx, 24(%rsp) # 8-byte Spill
movq 80(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_51
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit84.preheader
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB1_45
# %bb.40: # %.preheader.lr.ph
xorl %r13d, %r13d
xorl %r15d, %r15d
jmp .LBB1_41
.p2align 4, 0x90
.LBB1_44: # %_Z9gpuAssert10hipError_tPKcib.exit84
# in Loop: Header=BB1_41 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %r13d
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
movq %rbx, %r12
je .LBB1_45
.LBB1_41: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_43 Depth 2
testl %r12d, %r12d
movq %r12, %rbx
jle .LBB1_44
# %bb.42: # %.lr.ph104
# in Loop: Header=BB1_41 Depth=1
movl %r13d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_43: # Parent Loop BB1_41 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %rbx
jne .LBB1_43
jmp .LBB1_44
.LBB1_45: # %_Z9gpuAssert10hipError_tPKcib.exit84._crit_edge
movl $10, %edi
callq putchar@PLT
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z9gpuAssert10hipError_tPKcib.exit86
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z9gpuAssert10hipError_tPKcib.exit88
movq 40(%rsp), %rdi
callq hipFree
xorl %ecx, %ecx
testl %eax, %eax
jne .LBB1_50
.LBB1_7: # %_Z9gpuAssert10hipError_tPKcib.exit90
movl %ecx, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $99, %r8d
jmp .LBB1_2
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $100, %r8d
jmp .LBB1_2
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $101, %r8d
jmp .LBB1_2
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB1_2
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB1_2
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $149, %r8d
jmp .LBB1_2
.LBB1_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $150, %r8d
jmp .LBB1_2
.LBB1_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $151, %r8d
jmp .LBB1_2
.LBB1_51:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $152, %r8d
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $176, %r8d
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $177, %r8d
jmp .LBB1_2
.LBB1_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $178, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_mulPiS_S_iii,@object # @_Z10matrix_mulPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPiS_S_iii
.p2align 3, 0x0
_Z10matrix_mulPiS_S_iii:
.quad _Z25__device_stub__matrix_mulPiS_S_iii
.size _Z10matrix_mulPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/roboGen8/MPPI-Codes/master/research/trial/mm_omp_vs_cuda.hip"
.size .L.str, 118
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_mulPiS_S_iii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Number of columns in Matrix A should be equals to number of lines in Matrix B"
.size .Lstr, 78
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_mulPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define _EPSILON 0.001
#define _ABS(x) ( x > 0.0f ? x : -x )
__host__ int allclose(float* A, float* B, int len)
{
int returnval = 0;
for (int i = 0; i < len; i++)
{
if ( _ABS(A[i] - B[i]) > _EPSILON )
returnval = -1;
break;
}
return returnval;
}
// row-column dot-product for matrix multiplication.
__device__ float rowcol_dot(float * matrix_a, float * matrix_b, int row, int col, int N)
{
float val = 0;
for (int k = 0; k < N; k++)
{
val += matrix_a[row*N + k] * matrix_b[col + k*N];
}
return val;
}
// Matrix multiplication kernel that is parallelized over row/column tuples.
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
output_matrix[col + row * N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
}
__host__ int main()
{
cudaSetDevice(0);
int N = 4;
int num_bytes = sizeof(float) * N * N;
float h_A[] = {1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0};
float h_B[] = {14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0};
float h_AxB[] = {140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0};
float* d_A;
float* d_B;
float* d_output;
cudaMalloc((float **) &d_A, num_bytes);
cudaMalloc((float **) &d_B, num_bytes);
cudaMemcpy(d_A, h_A, num_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, num_bytes, cudaMemcpyHostToDevice);
cudaMalloc((float**) &d_output, num_bytes);
float* h_output;
h_output = (float*)malloc(num_bytes);
dim3 block(2, 2, 1);
dim3 grid(2, 2, 1);
matrix_mult_ker <<< grid, block >>> (d_A, d_B, d_output, N);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, num_bytes, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_output);
cudaDeviceReset();
if(allclose(h_AxB, h_output, N*N) < 0)
{
printf("Error! Output of kernel does not match expected output.\n");
free(h_output);
return -1;
}
else
{
printf("Success! Output of kernel matches expected output.\n");
free(h_output);
return 0;
}
} | code for sm_80
Function : _Z15matrix_mult_kerPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define _EPSILON 0.001
#define _ABS(x) ( x > 0.0f ? x : -x )
__host__ int allclose(float* A, float* B, int len)
{
int returnval = 0;
for (int i = 0; i < len; i++)
{
if ( _ABS(A[i] - B[i]) > _EPSILON )
returnval = -1;
break;
}
return returnval;
}
// row-column dot-product for matrix multiplication.
__device__ float rowcol_dot(float * matrix_a, float * matrix_b, int row, int col, int N)
{
float val = 0;
for (int k = 0; k < N; k++)
{
val += matrix_a[row*N + k] * matrix_b[col + k*N];
}
return val;
}
// Matrix multiplication kernel that is parallelized over row/column tuples.
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
output_matrix[col + row * N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
}
__host__ int main()
{
cudaSetDevice(0);
int N = 4;
int num_bytes = sizeof(float) * N * N;
float h_A[] = {1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0};
float h_B[] = {14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0};
float h_AxB[] = {140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0};
float* d_A;
float* d_B;
float* d_output;
cudaMalloc((float **) &d_A, num_bytes);
cudaMalloc((float **) &d_B, num_bytes);
cudaMemcpy(d_A, h_A, num_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, num_bytes, cudaMemcpyHostToDevice);
cudaMalloc((float**) &d_output, num_bytes);
float* h_output;
h_output = (float*)malloc(num_bytes);
dim3 block(2, 2, 1);
dim3 grid(2, 2, 1);
matrix_mult_ker <<< grid, block >>> (d_A, d_B, d_output, N);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, num_bytes, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_output);
cudaDeviceReset();
if(allclose(h_AxB, h_output, N*N) < 0)
{
printf("Error! Output of kernel does not match expected output.\n");
free(h_output);
return -1;
}
else
{
printf("Success! Output of kernel matches expected output.\n");
free(h_output);
return 0;
}
} | .file "tmpxft_000e4817_00000000-6_matrix_ker.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8allclosePfS_i
.type _Z8allclosePfS_i, @function
_Z8allclosePfS_i:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
testl %edx, %edx
jle .L3
movss (%rdi), %xmm1
movss (%rsi), %xmm2
movaps %xmm1, %xmm0
subss %xmm2, %xmm0
pxor %xmm3, %xmm3
comiss %xmm3, %xmm0
jbe .L7
.L5:
cvtss2sd %xmm0, %xmm0
comisd .LC2(%rip), %xmm0
seta %al
movzbl %al, %eax
negl %eax
.L3:
ret
.L7:
xorps .LC1(%rip), %xmm1
subss %xmm2, %xmm1
movaps %xmm1, %xmm0
jmp .L5
.cfi_endproc
.LFE2057:
.size _Z8allclosePfS_i, .-_Z8allclosePfS_i
.globl _Z10rowcol_dotPfS_iii
.type _Z10rowcol_dotPfS_iii, @function
_Z10rowcol_dotPfS_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10rowcol_dotPfS_iii, .-_Z10rowcol_dotPfS_iii
.globl _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.type _Z15matrix_mult_kerPfS_S_i, @function
_Z15matrix_mult_kerPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15matrix_mult_kerPfS_S_i, .-_Z15matrix_mult_kerPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC15:
.string "Error! Output of kernel does not match expected output.\n"
.align 8
.LC16:
.string "Success! Output of kernel matches expected output.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $256, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movss .LC3(%rip), %xmm3
movss %xmm3, 48(%rsp)
movss .LC4(%rip), %xmm2
movss %xmm2, 52(%rsp)
movss .LC5(%rip), %xmm1
movss %xmm1, 56(%rsp)
movss .LC6(%rip), %xmm0
movss %xmm0, 60(%rsp)
movss %xmm3, 64(%rsp)
movss %xmm2, 68(%rsp)
movss %xmm1, 72(%rsp)
movss %xmm0, 76(%rsp)
movss %xmm3, 80(%rsp)
movss %xmm2, 84(%rsp)
movss %xmm1, 88(%rsp)
movss %xmm0, 92(%rsp)
movss %xmm3, 96(%rsp)
movss %xmm2, 100(%rsp)
movss %xmm1, 104(%rsp)
movss %xmm0, 108(%rsp)
movss .LC7(%rip), %xmm3
movss %xmm3, 112(%rsp)
movss .LC8(%rip), %xmm2
movss %xmm2, 116(%rsp)
movss .LC9(%rip), %xmm1
movss %xmm1, 120(%rsp)
movss .LC10(%rip), %xmm0
movss %xmm0, 124(%rsp)
movss %xmm3, 128(%rsp)
movss %xmm2, 132(%rsp)
movss %xmm1, 136(%rsp)
movss %xmm0, 140(%rsp)
movss %xmm3, 144(%rsp)
movss %xmm2, 148(%rsp)
movss %xmm1, 152(%rsp)
movss %xmm0, 156(%rsp)
movss %xmm3, 160(%rsp)
movss %xmm2, 164(%rsp)
movss %xmm1, 168(%rsp)
movss %xmm0, 172(%rsp)
movss .LC11(%rip), %xmm3
movss %xmm3, 176(%rsp)
movss .LC12(%rip), %xmm2
movss %xmm2, 180(%rsp)
movss .LC13(%rip), %xmm1
movss %xmm1, 184(%rsp)
movss .LC14(%rip), %xmm0
movss %xmm0, 188(%rsp)
movss %xmm3, 192(%rsp)
movss %xmm2, 196(%rsp)
movss %xmm1, 200(%rsp)
movss %xmm0, 204(%rsp)
movss %xmm3, 208(%rsp)
movss %xmm2, 212(%rsp)
movss %xmm1, 216(%rsp)
movss %xmm0, 220(%rsp)
movss %xmm3, 224(%rsp)
movss %xmm2, 228(%rsp)
movss %xmm1, 232(%rsp)
movss %xmm0, 236(%rsp)
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L19:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
leaq 176(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
call _Z8allclosePfS_i
testl %eax, %eax
js .L25
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L18:
movq 248(%rsp), %rdx
subq %fs:40, %rdx
jne .L26
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $4, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
jmp .L19
.L25:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movl $-1, %eax
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC17:
.string "_Z15matrix_mult_kerPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1073741824
.align 4
.LC5:
.long 1077936128
.align 4
.LC6:
.long 1082130432
.align 4
.LC7:
.long 1096810496
.align 4
.LC8:
.long 1095761920
.align 4
.LC9:
.long 1094713344
.align 4
.LC10:
.long 1093664768
.align 4
.LC11:
.long 1124859904
.align 4
.LC12:
.long 1124204544
.align 4
.LC13:
.long 1123024896
.align 4
.LC14:
.long 1121714176
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define _EPSILON 0.001
#define _ABS(x) ( x > 0.0f ? x : -x )
__host__ int allclose(float* A, float* B, int len)
{
int returnval = 0;
for (int i = 0; i < len; i++)
{
if ( _ABS(A[i] - B[i]) > _EPSILON )
returnval = -1;
break;
}
return returnval;
}
// row-column dot-product for matrix multiplication.
__device__ float rowcol_dot(float * matrix_a, float * matrix_b, int row, int col, int N)
{
float val = 0;
for (int k = 0; k < N; k++)
{
val += matrix_a[row*N + k] * matrix_b[col + k*N];
}
return val;
}
// Matrix multiplication kernel that is parallelized over row/column tuples.
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
output_matrix[col + row * N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
}
__host__ int main()
{
cudaSetDevice(0);
int N = 4;
int num_bytes = sizeof(float) * N * N;
float h_A[] = {1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0};
float h_B[] = {14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0};
float h_AxB[] = {140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0};
float* d_A;
float* d_B;
float* d_output;
cudaMalloc((float **) &d_A, num_bytes);
cudaMalloc((float **) &d_B, num_bytes);
cudaMemcpy(d_A, h_A, num_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, num_bytes, cudaMemcpyHostToDevice);
cudaMalloc((float**) &d_output, num_bytes);
float* h_output;
h_output = (float*)malloc(num_bytes);
dim3 block(2, 2, 1);
dim3 grid(2, 2, 1);
matrix_mult_ker <<< grid, block >>> (d_A, d_B, d_output, N);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, num_bytes, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_output);
cudaDeviceReset();
if(allclose(h_AxB, h_output, N*N) < 0)
{
printf("Error! Output of kernel does not match expected output.\n");
free(h_output);
return -1;
}
else
{
printf("Success! Output of kernel matches expected output.\n");
free(h_output);
return 0;
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define _EPSILON 0.001
#define _ABS(x) ( x > 0.0f ? x : -x )
__host__ int allclose(float* A, float* B, int len)
{
int returnval = 0;
for (int i = 0; i < len; i++)
{
if ( _ABS(A[i] - B[i]) > _EPSILON )
returnval = -1;
break;
}
return returnval;
}
// row-column dot-product for matrix multiplication.
__device__ float rowcol_dot(float * matrix_a, float * matrix_b, int row, int col, int N)
{
float val = 0;
for (int k = 0; k < N; k++)
{
val += matrix_a[row*N + k] * matrix_b[col + k*N];
}
return val;
}
// Matrix multiplication kernel that is parallelized over row/column tuples.
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
output_matrix[col + row * N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
}
__host__ int main()
{
hipSetDevice(0);
int N = 4;
int num_bytes = sizeof(float) * N * N;
float h_A[] = {1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0};
float h_B[] = {14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0};
float h_AxB[] = {140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0};
float* d_A;
float* d_B;
float* d_output;
hipMalloc((float **) &d_A, num_bytes);
hipMalloc((float **) &d_B, num_bytes);
hipMemcpy(d_A, h_A, num_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, num_bytes, hipMemcpyHostToDevice);
hipMalloc((float**) &d_output, num_bytes);
float* h_output;
h_output = (float*)malloc(num_bytes);
dim3 block(2, 2, 1);
dim3 grid(2, 2, 1);
matrix_mult_ker <<< grid, block >>> (d_A, d_B, d_output, N);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, num_bytes, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_output);
hipDeviceReset();
if(allclose(h_AxB, h_output, N*N) < 0)
{
printf("Error! Output of kernel does not match expected output.\n");
free(h_output);
return -1;
}
else
{
printf("Success! Output of kernel matches expected output.\n");
free(h_output);
return 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define _EPSILON 0.001
#define _ABS(x) ( x > 0.0f ? x : -x )
__host__ int allclose(float* A, float* B, int len)
{
int returnval = 0;
for (int i = 0; i < len; i++)
{
if ( _ABS(A[i] - B[i]) > _EPSILON )
returnval = -1;
break;
}
return returnval;
}
// row-column dot-product for matrix multiplication.
__device__ float rowcol_dot(float * matrix_a, float * matrix_b, int row, int col, int N)
{
float val = 0;
for (int k = 0; k < N; k++)
{
val += matrix_a[row*N + k] * matrix_b[col + k*N];
}
return val;
}
// Matrix multiplication kernel that is parallelized over row/column tuples.
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
output_matrix[col + row * N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
}
__host__ int main()
{
hipSetDevice(0);
int N = 4;
int num_bytes = sizeof(float) * N * N;
float h_A[] = {1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0};
float h_B[] = {14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0};
float h_AxB[] = {140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0};
float* d_A;
float* d_B;
float* d_output;
hipMalloc((float **) &d_A, num_bytes);
hipMalloc((float **) &d_B, num_bytes);
hipMemcpy(d_A, h_A, num_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, num_bytes, hipMemcpyHostToDevice);
hipMalloc((float**) &d_output, num_bytes);
float* h_output;
h_output = (float*)malloc(num_bytes);
dim3 block(2, 2, 1);
dim3 grid(2, 2, 1);
matrix_mult_ker <<< grid, block >>> (d_A, d_B, d_output, N);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, num_bytes, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_output);
hipDeviceReset();
if(allclose(h_AxB, h_output, N*N) < 0)
{
printf("Error! Output of kernel does not match expected output.\n");
free(h_output);
return -1;
}
else
{
printf("Success! Output of kernel matches expected output.\n");
free(h_output);
return 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrix_mult_kerPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 8
.type _Z15matrix_mult_kerPfS_S_i,@function
_Z15matrix_mult_kerPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrix_mult_kerPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrix_mult_kerPfS_S_i, .Lfunc_end0-_Z15matrix_mult_kerPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrix_mult_kerPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrix_mult_kerPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define _EPSILON 0.001
#define _ABS(x) ( x > 0.0f ? x : -x )
__host__ int allclose(float* A, float* B, int len)
{
int returnval = 0;
for (int i = 0; i < len; i++)
{
if ( _ABS(A[i] - B[i]) > _EPSILON )
returnval = -1;
break;
}
return returnval;
}
// row-column dot-product for matrix multiplication.
__device__ float rowcol_dot(float * matrix_a, float * matrix_b, int row, int col, int N)
{
float val = 0;
for (int k = 0; k < N; k++)
{
val += matrix_a[row*N + k] * matrix_b[col + k*N];
}
return val;
}
// Matrix multiplication kernel that is parallelized over row/column tuples.
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
output_matrix[col + row * N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
}
__host__ int main()
{
hipSetDevice(0);
int N = 4;
int num_bytes = sizeof(float) * N * N;
float h_A[] = {1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0, \
1.0, 2.0, 3.0, 4.0};
float h_B[] = {14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0, \
14.0, 13.0, 12.0, 11.0};
float h_AxB[] = {140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0, \
140.0, 130.0, 120.0, 110.0};
float* d_A;
float* d_B;
float* d_output;
hipMalloc((float **) &d_A, num_bytes);
hipMalloc((float **) &d_B, num_bytes);
hipMemcpy(d_A, h_A, num_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, num_bytes, hipMemcpyHostToDevice);
hipMalloc((float**) &d_output, num_bytes);
float* h_output;
h_output = (float*)malloc(num_bytes);
dim3 block(2, 2, 1);
dim3 grid(2, 2, 1);
matrix_mult_ker <<< grid, block >>> (d_A, d_B, d_output, N);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, num_bytes, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_output);
hipDeviceReset();
if(allclose(h_AxB, h_output, N*N) < 0)
{
printf("Error! Output of kernel does not match expected output.\n");
free(h_output);
return -1;
}
else
{
printf("Success! Output of kernel matches expected output.\n");
free(h_output);
return 0;
}
} | .text
.file "matrix_ker.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8allclosePfS_i
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl _Z8allclosePfS_i
.p2align 4, 0x90
.type _Z8allclosePfS_i,@function
_Z8allclosePfS_i: # @_Z8allclosePfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_1
# %bb.3:
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
xorps .LCPI0_0(%rip), %xmm0
subss %xmm1, %xmm2
subss %xmm1, %xmm0
xorps %xmm1, %xmm1
cmpltss %xmm2, %xmm1
andps %xmm1, %xmm2
andnps %xmm0, %xmm1
orps %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorl %eax, %eax
ucomisd .LCPI0_1(%rip), %xmm0
seta %al
negl %eax
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z8allclosePfS_i, .Lfunc_end0-_Z8allclosePfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrix_mult_kerPfS_S_i # -- Begin function _Z30__device_stub__matrix_mult_kerPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrix_mult_kerPfS_S_i,@function
_Z30__device_stub__matrix_mult_kerPfS_S_i: # @_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrix_mult_kerPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__matrix_mult_kerPfS_S_i, .Lfunc_end1-_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI2_1:
.long 0x41600000 # float 14
.long 0x41500000 # float 13
.long 0x41400000 # float 12
.long 0x41300000 # float 11
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x430c0000 # float 140
.LCPI2_3:
.long 0xc30c0000 # float -140
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_4:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 208(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 256(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [1.4E+1,1.3E+1,1.2E+1,1.1E+1]
movaps %xmm0, 144(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movl $64, %edi
callq malloc
movq %rax, %rbx
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrix_mult_kerPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
movss .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm0, %xmm2
xorps %xmm0, %xmm0
cmpltss %xmm1, %xmm0
andps %xmm0, %xmm1
andnps %xmm2, %xmm0
orps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
xorl %ebp, %ebp
ucomisd .LCPI2_4(%rip), %xmm0
seta %bpl
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmovaq %rax, %rdi
negl %ebp
callq puts@PLT
movq %rbx, %rdi
callq free
movl %ebp, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrix_mult_kerPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrix_mult_kerPfS_S_i,@object # @_Z15matrix_mult_kerPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 3, 0x0
_Z15matrix_mult_kerPfS_S_i:
.quad _Z30__device_stub__matrix_mult_kerPfS_S_i
.size _Z15matrix_mult_kerPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrix_mult_kerPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success! Output of kernel matches expected output."
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error! Output of kernel does not match expected output."
.size .Lstr.1, 56
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrix_mult_kerPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrix_mult_kerPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrix_mult_kerPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrix_mult_kerPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 8
.type _Z15matrix_mult_kerPfS_S_i,@function
_Z15matrix_mult_kerPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrix_mult_kerPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrix_mult_kerPfS_S_i, .Lfunc_end0-_Z15matrix_mult_kerPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrix_mult_kerPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrix_mult_kerPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e4817_00000000-6_matrix_ker.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8allclosePfS_i
.type _Z8allclosePfS_i, @function
_Z8allclosePfS_i:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
testl %edx, %edx
jle .L3
movss (%rdi), %xmm1
movss (%rsi), %xmm2
movaps %xmm1, %xmm0
subss %xmm2, %xmm0
pxor %xmm3, %xmm3
comiss %xmm3, %xmm0
jbe .L7
.L5:
cvtss2sd %xmm0, %xmm0
comisd .LC2(%rip), %xmm0
seta %al
movzbl %al, %eax
negl %eax
.L3:
ret
.L7:
xorps .LC1(%rip), %xmm1
subss %xmm2, %xmm1
movaps %xmm1, %xmm0
jmp .L5
.cfi_endproc
.LFE2057:
.size _Z8allclosePfS_i, .-_Z8allclosePfS_i
.globl _Z10rowcol_dotPfS_iii
.type _Z10rowcol_dotPfS_iii, @function
_Z10rowcol_dotPfS_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10rowcol_dotPfS_iii, .-_Z10rowcol_dotPfS_iii
.globl _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.type _Z15matrix_mult_kerPfS_S_i, @function
_Z15matrix_mult_kerPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15matrix_mult_kerPfS_S_i, .-_Z15matrix_mult_kerPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC15:
.string "Error! Output of kernel does not match expected output.\n"
.align 8
.LC16:
.string "Success! Output of kernel matches expected output.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $256, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movss .LC3(%rip), %xmm3
movss %xmm3, 48(%rsp)
movss .LC4(%rip), %xmm2
movss %xmm2, 52(%rsp)
movss .LC5(%rip), %xmm1
movss %xmm1, 56(%rsp)
movss .LC6(%rip), %xmm0
movss %xmm0, 60(%rsp)
movss %xmm3, 64(%rsp)
movss %xmm2, 68(%rsp)
movss %xmm1, 72(%rsp)
movss %xmm0, 76(%rsp)
movss %xmm3, 80(%rsp)
movss %xmm2, 84(%rsp)
movss %xmm1, 88(%rsp)
movss %xmm0, 92(%rsp)
movss %xmm3, 96(%rsp)
movss %xmm2, 100(%rsp)
movss %xmm1, 104(%rsp)
movss %xmm0, 108(%rsp)
movss .LC7(%rip), %xmm3
movss %xmm3, 112(%rsp)
movss .LC8(%rip), %xmm2
movss %xmm2, 116(%rsp)
movss .LC9(%rip), %xmm1
movss %xmm1, 120(%rsp)
movss .LC10(%rip), %xmm0
movss %xmm0, 124(%rsp)
movss %xmm3, 128(%rsp)
movss %xmm2, 132(%rsp)
movss %xmm1, 136(%rsp)
movss %xmm0, 140(%rsp)
movss %xmm3, 144(%rsp)
movss %xmm2, 148(%rsp)
movss %xmm1, 152(%rsp)
movss %xmm0, 156(%rsp)
movss %xmm3, 160(%rsp)
movss %xmm2, 164(%rsp)
movss %xmm1, 168(%rsp)
movss %xmm0, 172(%rsp)
movss .LC11(%rip), %xmm3
movss %xmm3, 176(%rsp)
movss .LC12(%rip), %xmm2
movss %xmm2, 180(%rsp)
movss .LC13(%rip), %xmm1
movss %xmm1, 184(%rsp)
movss .LC14(%rip), %xmm0
movss %xmm0, 188(%rsp)
movss %xmm3, 192(%rsp)
movss %xmm2, 196(%rsp)
movss %xmm1, 200(%rsp)
movss %xmm0, 204(%rsp)
movss %xmm3, 208(%rsp)
movss %xmm2, 212(%rsp)
movss %xmm1, 216(%rsp)
movss %xmm0, 220(%rsp)
movss %xmm3, 224(%rsp)
movss %xmm2, 228(%rsp)
movss %xmm1, 232(%rsp)
movss %xmm0, 236(%rsp)
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L19:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
leaq 176(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
call _Z8allclosePfS_i
testl %eax, %eax
js .L25
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L18:
movq 248(%rsp), %rdx
subq %fs:40, %rdx
jne .L26
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $4, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
jmp .L19
.L25:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movl $-1, %eax
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC17:
.string "_Z15matrix_mult_kerPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1073741824
.align 4
.LC5:
.long 1077936128
.align 4
.LC6:
.long 1082130432
.align 4
.LC7:
.long 1096810496
.align 4
.LC8:
.long 1095761920
.align 4
.LC9:
.long 1094713344
.align 4
.LC10:
.long 1093664768
.align 4
.LC11:
.long 1124859904
.align 4
.LC12:
.long 1124204544
.align 4
.LC13:
.long 1123024896
.align 4
.LC14:
.long 1121714176
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_ker.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8allclosePfS_i
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl _Z8allclosePfS_i
.p2align 4, 0x90
.type _Z8allclosePfS_i,@function
_Z8allclosePfS_i: # @_Z8allclosePfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_1
# %bb.3:
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
xorps .LCPI0_0(%rip), %xmm0
subss %xmm1, %xmm2
subss %xmm1, %xmm0
xorps %xmm1, %xmm1
cmpltss %xmm2, %xmm1
andps %xmm1, %xmm2
andnps %xmm0, %xmm1
orps %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorl %eax, %eax
ucomisd .LCPI0_1(%rip), %xmm0
seta %al
negl %eax
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z8allclosePfS_i, .Lfunc_end0-_Z8allclosePfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrix_mult_kerPfS_S_i # -- Begin function _Z30__device_stub__matrix_mult_kerPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrix_mult_kerPfS_S_i,@function
_Z30__device_stub__matrix_mult_kerPfS_S_i: # @_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrix_mult_kerPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__matrix_mult_kerPfS_S_i, .Lfunc_end1-_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI2_1:
.long 0x41600000 # float 14
.long 0x41500000 # float 13
.long 0x41400000 # float 12
.long 0x41300000 # float 11
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x430c0000 # float 140
.LCPI2_3:
.long 0xc30c0000 # float -140
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_4:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 208(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 256(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [1.4E+1,1.3E+1,1.2E+1,1.1E+1]
movaps %xmm0, 144(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movl $64, %edi
callq malloc
movq %rax, %rbx
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrix_mult_kerPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
movss .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm0, %xmm2
xorps %xmm0, %xmm0
cmpltss %xmm1, %xmm0
andps %xmm0, %xmm1
andnps %xmm2, %xmm0
orps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
xorl %ebp, %ebp
ucomisd .LCPI2_4(%rip), %xmm0
seta %bpl
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmovaq %rax, %rdi
negl %ebp
callq puts@PLT
movq %rbx, %rdi
callq free
movl %ebp, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrix_mult_kerPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrix_mult_kerPfS_S_i,@object # @_Z15matrix_mult_kerPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 3, 0x0
_Z15matrix_mult_kerPfS_S_i:
.quad _Z30__device_stub__matrix_mult_kerPfS_S_i
.size _Z15matrix_mult_kerPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrix_mult_kerPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success! Output of kernel matches expected output."
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error! Output of kernel does not match expected output."
.size .Lstr.1, 56
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrix_mult_kerPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrix_mult_kerPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "dot-graph.hh"
#include <fstream>
namespace utils
{
DotGraph::DotGraph(const std::string& name)
: name_(name)
{}
void DotGraph::write_dot(std::ostream& os) const
{
os << "digraph " << name_ << "\n";
os << "{\n";
for (auto it : vs_)
{
os << " n" << it.second << " [label=\"";
for (char c : it.first)
{
if (c == '"')
os << "\\\"";
else
os << c;
}
os << "\"]\n";
}
for (auto it : es_)
os << " n" << it.first << " -> n" << it.second << "\n";
os << "}\n";
}
void DotGraph::write_file(const std::string& path) const
{
std::ofstream os(path);
write_dot(os);
}
void DotGraph::write_png(const std::string& path) const
{
(void) path;
}
std::size_t DotGraph::add_vertex(const std::string& name)
{
auto it = vs_.find(name);
if (it != vs_.end())
return it->second;
std::size_t id = vs_.size();
vs_[name] = id;
return id;
}
void DotGraph::add_edge(const std::string& a, const std::string& b)
{
auto v1 = add_vertex(a);
auto v2 = add_vertex(b);
es_.insert({v1, v2});
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "dot-graph.hh"
#include <fstream>
namespace utils
{
DotGraph::DotGraph(const std::string& name)
: name_(name)
{}
void DotGraph::write_dot(std::ostream& os) const
{
os << "digraph " << name_ << "\n";
os << "{\n";
for (auto it : vs_)
{
os << " n" << it.second << " [label=\"";
for (char c : it.first)
{
if (c == '"')
os << "\\\"";
else
os << c;
}
os << "\"]\n";
}
for (auto it : es_)
os << " n" << it.first << " -> n" << it.second << "\n";
os << "}\n";
}
void DotGraph::write_file(const std::string& path) const
{
std::ofstream os(path);
write_dot(os);
}
void DotGraph::write_png(const std::string& path) const
{
(void) path;
}
std::size_t DotGraph::add_vertex(const std::string& name)
{
auto it = vs_.find(name);
if (it != vs_.end())
return it->second;
std::size_t id = vs_.size();
vs_[name] = id;
return id;
}
void DotGraph::add_edge(const std::string& a, const std::string& b)
{
auto v1 = add_vertex(a);
auto v2 = add_vertex(b);
es_.insert({v1, v2});
}
} | #include <hip/hip_runtime.h>
#include "dot-graph.hh"
#include <fstream>
namespace utils
{
DotGraph::DotGraph(const std::string& name)
: name_(name)
{}
void DotGraph::write_dot(std::ostream& os) const
{
os << "digraph " << name_ << "\n";
os << "{\n";
for (auto it : vs_)
{
os << " n" << it.second << " [label=\"";
for (char c : it.first)
{
if (c == '"')
os << "\\\"";
else
os << c;
}
os << "\"]\n";
}
for (auto it : es_)
os << " n" << it.first << " -> n" << it.second << "\n";
os << "}\n";
}
void DotGraph::write_file(const std::string& path) const
{
std::ofstream os(path);
write_dot(os);
}
void DotGraph::write_png(const std::string& path) const
{
(void) path;
}
std::size_t DotGraph::add_vertex(const std::string& name)
{
auto it = vs_.find(name);
if (it != vs_.end())
return it->second;
std::size_t id = vs_.size();
vs_[name] = id;
return id;
}
void DotGraph::add_edge(const std::string& a, const std::string& b)
{
auto v1 = add_vertex(a);
auto v2 = add_vertex(b);
es_.insert({v1, v2});
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "dot-graph.hh"
#include <fstream>
namespace utils
{
DotGraph::DotGraph(const std::string& name)
: name_(name)
{}
void DotGraph::write_dot(std::ostream& os) const
{
os << "digraph " << name_ << "\n";
os << "{\n";
for (auto it : vs_)
{
os << " n" << it.second << " [label=\"";
for (char c : it.first)
{
if (c == '"')
os << "\\\"";
else
os << c;
}
os << "\"]\n";
}
for (auto it : es_)
os << " n" << it.first << " -> n" << it.second << "\n";
os << "}\n";
}
void DotGraph::write_file(const std::string& path) const
{
std::ofstream os(path);
write_dot(os);
}
void DotGraph::write_png(const std::string& path) const
{
(void) path;
}
std::size_t DotGraph::add_vertex(const std::string& name)
{
auto it = vs_.find(name);
if (it != vs_.end())
return it->second;
std::size_t id = vs_.size();
vs_[name] = id;
return id;
}
void DotGraph::add_edge(const std::string& a, const std::string& b)
{
auto v1 = add_vertex(a);
auto v2 = add_vertex(b);
es_.insert({v1, v2});
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Author: Jose F. Martinez Rivera
// Course: ICOM4036 - 040
// Professor: Wilson Rivera Gallego
// Assignment 2 - CUDA Implementation
#define V 8
#define E 11
#define MAX_WEIGHT 1000000
#define TRUE 1
#define FALSE 0
typedef int boolean;
//
//Represents an edge or path between Vertices
typedef struct
{
int u;
int v;
} Edge;
//Represents a Vertex
typedef struct
{
int title;
boolean visited;
} Vertex;
//Finds the weight of the path from vertex u to vertex v
__device__ __host__ int findEdge(Vertex u, Vertex v, Edge *edges, int *weights)
{
int i;
for(i = 0; i < E; i++)
{
if(edges[i].u == u.title && edges[i].v == v.title)
{
return weights[i];
}
}
return MAX_WEIGHT;
}
__global__ void Find_Vertex(Vertex *vertices, Edge *edges, int *weights, int *length, int *updateLength)
{
int u = threadIdx.x;
if(vertices[u].visited == FALSE)
{
vertices[u].visited = TRUE;
int v;
for(v = 0; v < V; v++)
{
//Find the weight of the edge
int weight = findEdge(vertices[u], vertices[v], edges, weights);
//Checks if the weight is a candidate
if(weight < MAX_WEIGHT)
{
//If the weight is shorter than the current weight, replace it
if(updateLength[v] > length[u] + weight)
{
updateLength[v] = length[u] + weight;
}
}
}
}
} | code for sm_80
Function : _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ea4000c1e1900 */
/*0060*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0001e2000c101904 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e00ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0110*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea8000c1e1900 */
/*0120*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000162000c1e1900 */
/*0140*/ IADD3 R10, R10, 0x2, RZ ; /* 0x000000020a0a7810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B1, 0x770 ; /* 0x0000061000017945 */
/* 0x000fe20003800000 */
/*0160*/ BSSY B0, 0x730 ; /* 0x000005c000007945 */
/* 0x000fe40003800000 */
/*0170*/ ISETP.NE.AND P0, PT, R10, 0x8, PT ; /* 0x000000080a00780c */
/* 0x000fc40003f05270 */
/*0180*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0190*/ @P1 BRA 0x1f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x001ea2000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*01e0*/ @!P1 BRA 0x720 ; /* 0x0000053000009947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x001ea4000c1e1900 */
/*0200*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0210*/ @P1 BRA 0x270 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ HFMA2.MMA R15, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0f7435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0250*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0260*/ @!P1 BRA 0x720 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R15, [R4.64+0x10] ; /* 0x00001004040f7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0290*/ @P1 BRA 0x2f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x2 ; /* 0x00000002ff0f7424 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*02e0*/ @!P1 BRA 0x720 ; /* 0x0000043000009947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R15, [R4.64+0x18] ; /* 0x00001804040f7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0310*/ @P1 BRA 0x370 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0320*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0330*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3 ; /* 0x00000003ff0f7424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0350*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0360*/ @!P1 BRA 0x720 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R15, [R4.64+0x20] ; /* 0x00002004040f7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0390*/ @P1 BRA 0x3f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R14, [R4.64+0x24] ; /* 0x00002404040e7981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*03d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*03e0*/ @!P1 BRA 0x720 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*03f0*/ LDG.E R15, [R4.64+0x28] ; /* 0x00002804040f7981 */
/* 0x000ea4000c1e1900 */
/*0400*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0410*/ @P1 BRA 0x470 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0420*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.MOV.U32 R15, RZ, RZ, 0x5 ; /* 0x00000005ff0f7424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0450*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0460*/ @!P1 BRA 0x720 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R15, [R4.64+0x30] ; /* 0x00003004040f7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0490*/ @P1 BRA 0x4f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*04a0*/ LDG.E R14, [R4.64+0x34] ; /* 0x00003404040e7981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x6 ; /* 0x00000006ff0f7424 */
/* 0x000fe200078e00ff */
/*04c0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe40000000f00 */
/*04d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*04e0*/ @!P1 BRA 0x720 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*04f0*/ LDG.E R15, [R4.64+0x38] ; /* 0x00003804040f7981 */
/* 0x000ea4000c1e1900 */
/*0500*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0510*/ @P1 BRA 0x570 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E R14, [R4.64+0x3c] ; /* 0x00003c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, 0x7 ; /* 0x00000007ff0f7424 */
/* 0x000fe400078e00ff */
/*0540*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0550*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0560*/ @!P1 BRA 0x720 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R15, [R4.64+0x40] ; /* 0x00004004040f7981 */
/* 0x000ea4000c1e1900 */
/*0580*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0590*/ @P1 BRA 0x5f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*05a0*/ LDG.E R14, [R4.64+0x44] ; /* 0x00004404040e7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe400078e00ff */
/*05c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*05d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*05e0*/ @!P1 BRA 0x720 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R15, [R4.64+0x48] ; /* 0x00004804040f7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0610*/ @P1 BRA 0x670 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R14, [R4.64+0x4c] ; /* 0x00004c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.MOV.U32 R15, RZ, RZ, 0x9 ; /* 0x00000009ff0f7424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0650*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0660*/ @!P1 BRA 0x720 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0670*/ LDG.E R15, [R4.64+0x50] ; /* 0x00005004040f7981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, 0xf4240 ; /* 0x000f4240ff107424 */
/* 0x000fe200078e00ff */
/*0690*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*06a0*/ @P1 BREAK B0 ; /* 0x0000000000001942 */
/* 0x000fe20003800000 */
/*06b0*/ @P1 BRA 0x760 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R14, [R4.64+0x54] ; /* 0x00005404040e7981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*06e0*/ @P1 BREAK B0 ; /* 0x0000000000001942 */
/* 0x000fe20003800000 */
/*06f0*/ @P1 BRA 0x760 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R15, RZ, RZ, 0xa ; /* 0x0000000aff0f7424 */
/* 0x000fe400078e00ff */
/*0710*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ LEA R14, P1, R15, c[0x0][0x170], 0x2 ; /* 0x00005c000f0e7a11 */
/* 0x000fc800078210ff */
/*0740*/ LEA.HI.X R15, R15, c[0x0][0x174], R16, 0x2, P1 ; /* 0x00005d000f0f7a11 */
/* 0x000fca00008f1410 */
/*0750*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000168000c1e1900 */
/*0760*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0770*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0780*/ ISETP.GT.AND P1, PT, R16, 0xf423f, PT ; /* 0x000f423f1000780c */
/* 0x020fe20003f24270 */
/*0790*/ BSSY B1, 0x850 ; /* 0x000000b000017945 */
/* 0x000fd80003800000 */
/*07a0*/ @P1 BRA 0x840 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*07b0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x001fe200000001ff */
/*07c0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000eb2000c1e1900 */
/*07d0*/ IMAD.WIDE R14, R0, R15, c[0x0][0x178] ; /* 0x00005e00000e7625 */
/* 0x000fcc00078e020f */
/*07e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee4000c1e1900 */
/*07f0*/ IMAD.IADD R16, R15, 0x1, R16 ; /* 0x000000010f107824 */
/* 0x008fca00078e0210 */
/*0800*/ ISETP.GT.AND P1, PT, R13, R16, PT ; /* 0x000000100d00720c */
/* 0x004fda0003f24270 */
/*0810*/ @P1 STG.E [R8.64], R16 ; /* 0x0000001008001986 */
/* 0x0001e8000c101904 */
/*0820*/ @P1 LDG.E R12, [R2.64] ; /* 0x00000004020c1981 */
/* 0x000168000c1e1900 */
/*0830*/ @P1 LDG.E R11, [R4.64] ; /* 0x00000004040b1981 */
/* 0x000164000c1e1900 */
/*0840*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R13, [R6.64+0x8] ; /* 0x00000804060d7981 */
/* 0x000364000c1e1900 */
/*0860*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x020fe20003f25270 */
/*0870*/ BSSY B2, 0xe70 ; /* 0x000005f000027945 */
/* 0x000fe20003800000 */
/*0880*/ BSSY B1, 0xe30 ; /* 0x000005a000017945 */
/* 0x000ff60003800000 */
/*0890*/ @P1 BRA 0x8f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x003ea2000c1e1900 */
/*08b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*08c0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*08d0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*08e0*/ @!P1 BRA 0xe20 ; /* 0x0000053000009947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x002ea4000c1e1900 */
/*0900*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0910*/ @P1 BRA 0x970 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0920*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0930*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0940*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0950*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0960*/ @!P1 BRA 0xe20 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0970*/ LDG.E R11, [R4.64+0x10] ; /* 0x00001004040b7981 */
/* 0x000ea4000c1e1900 */
/*0980*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0990*/ @P1 BRA 0x9f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*09a0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x001ea2000c1e1900 */
/*09b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x2 ; /* 0x00000002ff0b7424 */
/* 0x000fe200078e00ff */
/*09c0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*09d0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*09e0*/ @!P1 BRA 0xe20 ; /* 0x0000043000009947 */
/* 0x000fea0003800000 */
/*09f0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000ea4000c1e1900 */
/*0a00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0a10*/ @P1 BRA 0xa70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0a20*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3 ; /* 0x00000003ff0b7424 */
/* 0x000fe200078e00ff */
/*0a40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0a50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0a60*/ @!P1 BRA 0xe20 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0a70*/ LDG.E R11, [R4.64+0x20] ; /* 0x00002004040b7981 */
/* 0x000ea4000c1e1900 */
/*0a80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0a90*/ @P1 BRA 0xaf0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R14, [R4.64+0x24] ; /* 0x00002404040e7981 */
/* 0x001ea2000c1e1900 */
/*0ab0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*0ac0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0ad0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0ae0*/ @!P1 BRA 0xe20 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0af0*/ LDG.E R11, [R4.64+0x28] ; /* 0x00002804040b7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0b10*/ @P1 BRA 0xb70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0b20*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0b30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x5 ; /* 0x00000005ff0b7424 */
/* 0x000fe200078e00ff */
/*0b40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0b50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0b60*/ @!P1 BRA 0xe20 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0b70*/ LDG.E R11, [R4.64+0x30] ; /* 0x00003004040b7981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0b90*/ @P1 BRA 0xbf0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0ba0*/ LDG.E R14, [R4.64+0x34] ; /* 0x00003404040e7981 */
/* 0x001ea2000c1e1900 */
/*0bb0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x6 ; /* 0x00000006ff0b7424 */
/* 0x000fe200078e00ff */
/*0bc0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0bd0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0be0*/ @!P1 BRA 0xe20 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*0bf0*/ LDG.E R11, [R4.64+0x38] ; /* 0x00003804040b7981 */
/* 0x000ea4000c1e1900 */
/*0c00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0c10*/ @P1 BRA 0xc70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0c20*/ LDG.E R14, [R4.64+0x3c] ; /* 0x00003c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0c30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7 ; /* 0x00000007ff0b7424 */
/* 0x000fe200078e00ff */
/*0c40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0c50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0c60*/ @!P1 BRA 0xe20 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0c70*/ LDG.E R11, [R4.64+0x40] ; /* 0x00004004040b7981 */
/* 0x000ea4000c1e1900 */
/*0c80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0c90*/ @P1 BRA 0xcf0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E R14, [R4.64+0x44] ; /* 0x00004404040e7981 */
/* 0x001ea2000c1e1900 */
/*0cb0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*0cc0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0cd0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0ce0*/ @!P1 BRA 0xe20 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0cf0*/ LDG.E R11, [R4.64+0x48] ; /* 0x00004804040b7981 */
/* 0x000ea4000c1e1900 */
/*0d00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0d10*/ @P1 BRA 0xd70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0d20*/ LDG.E R14, [R4.64+0x4c] ; /* 0x00004c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0d30*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.36441802978515625e-07 ; /* 0x00000009ff0b7435 */
/* 0x000fe200000001ff */
/*0d40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0d50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0d60*/ @!P1 BRA 0xe20 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0d70*/ LDG.E R11, [R4.64+0x50] ; /* 0x00005004040b7981 */
/* 0x000ea4000c1e1900 */
/*0d80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fe20003f25270 */
/*0d90*/ IMAD.MOV.U32 R11, RZ, RZ, 0xf4240 ; /* 0x000f4240ff0b7424 */
/* 0x000fd800078e00ff */
/*0da0*/ @P1 BREAK B1 ; /* 0x0000000000011942 */
/* 0x000fe20003800000 */
/*0db0*/ @P1 BRA 0xe60 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0dc0*/ LDG.E R12, [R4.64+0x54] ; /* 0x00005404040c7981 */
/* 0x000ea4000c1e1900 */
/*0dd0*/ ISETP.NE.AND P1, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x004fda0003f25270 */
/*0de0*/ @P1 BREAK B1 ; /* 0x0000000000011942 */
/* 0x000fe20003800000 */
/*0df0*/ @P1 BRA 0xe60 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0e00*/ IMAD.MOV.U32 R11, RZ, RZ, 0xa ; /* 0x0000000aff0b7424 */
/* 0x000fe400078e00ff */
/*0e10*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0e20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0e30*/ LEA R12, P1, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b0c7a11 */
/* 0x000fc800078210ff */
/*0e40*/ LEA.HI.X R13, R11, c[0x0][0x174], R14, 0x2, P1 ; /* 0x00005d000b0d7a11 */
/* 0x000fca00008f140e */
/*0e50*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000168000c1e1900 */
/*0e60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e70*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0e80*/ ISETP.GT.AND P1, PT, R11, 0xf423f, PT ; /* 0x000f423f0b00780c */
/* 0x020fe20003f24270 */
/*0e90*/ BSSY B2, 0xf30 ; /* 0x0000009000027945 */
/* 0x000fd80003800000 */
/*0ea0*/ @P1 BRA 0xf20 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0eb0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x001fe200078e00ff */
/*0ec0*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ea6000c1e1900 */
/*0ed0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x178] ; /* 0x00005e00000c7625 */
/* 0x000fcc00078e020d */
/*0ee0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0ef0*/ IMAD.IADD R11, R12, 0x1, R11 ; /* 0x000000010c0b7824 */
/* 0x008fca00078e020b */
/*0f00*/ ISETP.GT.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x004fda0003f24270 */
/*0f10*/ @P1 STG.E [R8.64+0x4], R11 ; /* 0x0000040b08001986 */
/* 0x0001e4000c101904 */
/*0f20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f30*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x001fe40007f3e0ff */
/*0f40*/ IADD3 R6, P2, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007f5e0ff */
/*0f50*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*0f60*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0f70*/ @!P0 CALL.REL.NOINC 0xf90 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*0f80*/ BRA 0x110 ; /* 0xfffff18000007947 */
/* 0x000fea000383ffff */
/*0f90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fa0*/ BRA 0xfa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Author: Jose F. Martinez Rivera
// Course: ICOM4036 - 040
// Professor: Wilson Rivera Gallego
// Assignment 2 - CUDA Implementation
#define V 8
#define E 11
#define MAX_WEIGHT 1000000
#define TRUE 1
#define FALSE 0
typedef int boolean;
//
//Represents an edge or path between Vertices
typedef struct
{
int u;
int v;
} Edge;
//Represents a Vertex
typedef struct
{
int title;
boolean visited;
} Vertex;
//Finds the weight of the path from vertex u to vertex v
__device__ __host__ int findEdge(Vertex u, Vertex v, Edge *edges, int *weights)
{
int i;
for(i = 0; i < E; i++)
{
if(edges[i].u == u.title && edges[i].v == v.title)
{
return weights[i];
}
}
return MAX_WEIGHT;
}
__global__ void Find_Vertex(Vertex *vertices, Edge *edges, int *weights, int *length, int *updateLength)
{
int u = threadIdx.x;
if(vertices[u].visited == FALSE)
{
vertices[u].visited = TRUE;
int v;
for(v = 0; v < V; v++)
{
//Find the weight of the edge
int weight = findEdge(vertices[u], vertices[v], edges, weights);
//Checks if the weight is a candidate
if(weight < MAX_WEIGHT)
{
//If the weight is shorter than the current weight, replace it
if(updateLength[v] > length[u] + weight)
{
updateLength[v] = length[u] + weight;
}
}
}
}
} | .file "tmpxft_000bfcde_00000000-6_Find_Vertex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8findEdge6VertexS_P4EdgePi
.type _Z8findEdge6VertexS_P4EdgePi, @function
_Z8findEdge6VertexS_P4EdgePi:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
jmp .L6
.L4:
addq $1, %rax
cmpq $11, %rax
je .L8
.L6:
cmpl %edi, (%rdx,%rax,8)
jne .L4
cmpl %esi, 4(%rdx,%rax,8)
jne .L4
movl (%rcx,%rax,4), %eax
ret
.L8:
movl $1000000, %eax
ret
.cfi_endproc
.LFE2027:
.size _Z8findEdge6VertexS_P4EdgePi, .-_Z8findEdge6VertexS_P4EdgePi
.globl _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_
.type _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_, @function
_Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Find_VertexP6VertexP4EdgePiS3_S3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_, .-_Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_
.globl _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.type _Z11Find_VertexP6VertexP4EdgePiS3_S3_, @function
_Z11Find_VertexP6VertexP4EdgePiS3_S3_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11Find_VertexP6VertexP4EdgePiS3_S3_, .-_Z11Find_VertexP6VertexP4EdgePiS3_S3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11Find_VertexP6VertexP4EdgePiS3_S3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Find_VertexP6VertexP4EdgePiS3_S3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Author: Jose F. Martinez Rivera
// Course: ICOM4036 - 040
// Professor: Wilson Rivera Gallego
// Assignment 2 - CUDA Implementation
#define V 8
#define E 11
#define MAX_WEIGHT 1000000
#define TRUE 1
#define FALSE 0
typedef int boolean;
//
//Represents an edge or path between Vertices
typedef struct
{
int u;
int v;
} Edge;
//Represents a Vertex
typedef struct
{
int title;
boolean visited;
} Vertex;
//Finds the weight of the path from vertex u to vertex v
__device__ __host__ int findEdge(Vertex u, Vertex v, Edge *edges, int *weights)
{
int i;
for(i = 0; i < E; i++)
{
if(edges[i].u == u.title && edges[i].v == v.title)
{
return weights[i];
}
}
return MAX_WEIGHT;
}
__global__ void Find_Vertex(Vertex *vertices, Edge *edges, int *weights, int *length, int *updateLength)
{
int u = threadIdx.x;
if(vertices[u].visited == FALSE)
{
vertices[u].visited = TRUE;
int v;
for(v = 0; v < V; v++)
{
//Find the weight of the edge
int weight = findEdge(vertices[u], vertices[v], edges, weights);
//Checks if the weight is a candidate
if(weight < MAX_WEIGHT)
{
//If the weight is shorter than the current weight, replace it
if(updateLength[v] > length[u] + weight)
{
updateLength[v] = length[u] + weight;
}
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Author: Jose F. Martinez Rivera
// Course: ICOM4036 - 040
// Professor: Wilson Rivera Gallego
// Assignment 2 - CUDA Implementation
#define V 8
#define E 11
#define MAX_WEIGHT 1000000
#define TRUE 1
#define FALSE 0
typedef int boolean;
//
//Represents an edge or path between Vertices
typedef struct
{
int u;
int v;
} Edge;
//Represents a Vertex
typedef struct
{
int title;
boolean visited;
} Vertex;
//Finds the weight of the path from vertex u to vertex v
__device__ __host__ int findEdge(Vertex u, Vertex v, Edge *edges, int *weights)
{
int i;
for(i = 0; i < E; i++)
{
if(edges[i].u == u.title && edges[i].v == v.title)
{
return weights[i];
}
}
return MAX_WEIGHT;
}
__global__ void Find_Vertex(Vertex *vertices, Edge *edges, int *weights, int *length, int *updateLength)
{
int u = threadIdx.x;
if(vertices[u].visited == FALSE)
{
vertices[u].visited = TRUE;
int v;
for(v = 0; v < V; v++)
{
//Find the weight of the edge
int weight = findEdge(vertices[u], vertices[v], edges, weights);
//Checks if the weight is a candidate
if(weight < MAX_WEIGHT)
{
//If the weight is shorter than the current weight, replace it
if(updateLength[v] > length[u] + weight)
{
updateLength[v] = length[u] + weight;
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Author: Jose F. Martinez Rivera
// Course: ICOM4036 - 040
// Professor: Wilson Rivera Gallego
// Assignment 2 - CUDA Implementation
#define V 8
#define E 11
#define MAX_WEIGHT 1000000
#define TRUE 1
#define FALSE 0
typedef int boolean;
//
//Represents an edge or path between Vertices
typedef struct
{
int u;
int v;
} Edge;
//Represents a Vertex
typedef struct
{
int title;
boolean visited;
} Vertex;
//Finds the weight of the path from vertex u to vertex v
__device__ __host__ int findEdge(Vertex u, Vertex v, Edge *edges, int *weights)
{
int i;
for(i = 0; i < E; i++)
{
if(edges[i].u == u.title && edges[i].v == v.title)
{
return weights[i];
}
}
return MAX_WEIGHT;
}
__global__ void Find_Vertex(Vertex *vertices, Edge *edges, int *weights, int *length, int *updateLength)
{
int u = threadIdx.x;
if(vertices[u].visited == FALSE)
{
vertices[u].visited = TRUE;
int v;
for(v = 0; v < V; v++)
{
//Find the weight of the edge
int weight = findEdge(vertices[u], vertices[v], edges, weights);
//Checks if the weight is a candidate
if(weight < MAX_WEIGHT)
{
//If the weight is shorter than the current weight, replace it
if(updateLength[v] > length[u] + weight)
{
updateLength[v] = length[u] + weight;
}
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.globl _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.p2align 8
.type _Z11Find_VertexP6VertexP4EdgePiS3_S3_,@function
_Z11Find_VertexP6VertexP4EdgePiS3_S3_:
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
s_mov_b32 s11, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[8:9] offset:4
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_14
s_load_b256 s[0:7], s[0:1], 0x8
v_add_co_u32 v1, s10, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v2, null, s9, 0, s10
v_lshlrev_b32_e32 v3, 3, v0
v_dual_mov_b32 v7, 1 :: v_dual_lshlrev_b32 v6, 2, v0
v_add_co_u32 v4, vcc_lo, v1, 4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
global_store_b32 v[4:5], v7, off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s4, s4, v6
v_mov_b32_e32 v6, 0
v_add_co_u32 v0, s10, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s9, 0, s10
v_add_co_ci_u32_e64 v3, null, s5, 0, s4
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_mov_b32 s10, s11
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, 8
s_cbranch_scc0 .LBB0_14
.LBB0_3:
s_lshl_b64 s[4:5], s[10:11], 3
s_mov_b64 s[12:13], 0
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_clause 0x1
global_load_b32 v7, v[0:1], off
global_load_b32 v8, v6, s[4:5]
s_mov_b32 s14, 0
s_mov_b64 s[4:5], s[0:1]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s17, exec_lo, s20
v_mov_b32_e32 v9, s19
s_or_b32 s14, s17, s14
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s17, s16, exec_lo
s_or_b32 s15, s15, s17
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_9
.LBB0_5:
global_load_b32 v4, v6, s[4:5] offset:-4
s_mov_b32 s19, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s17, v4, v7
v_cmpx_eq_u32_e64 v4, v7
s_cbranch_execz .LBB0_7
global_load_b32 v4, v6, s[4:5]
s_and_not1_b32 s17, s17, exec_lo
s_mov_b32 s18, -1
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v4, v8
s_and_b32 s20, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s17, s17, s20
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s19
v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
s_and_not1_b32 s16, s16, exec_lo
s_and_b32 s18, s18, exec_lo
s_mov_b32 s20, -1
s_or_b32 s16, s16, s18
s_and_saveexec_b32 s18, s17
s_cbranch_execz .LBB0_4
s_add_u32 s22, s12, 4
s_addc_u32 s23, s13, 0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s22, 44
v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
s_cselect_b32 s17, -1, 0
s_mov_b32 s19, 0xf4240
s_and_not1_b32 s16, s16, exec_lo
s_or_not1_b32 s20, s17, exec_lo
s_mov_b64 s[12:13], s[22:23]
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s4, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_11
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v9, v[4:5], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0xf4240, v9
s_cbranch_execz .LBB0_2
s_lshl_b64 s[4:5], s[10:11], 2
global_load_b32 v4, v[2:3], off
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
global_load_b32 v5, v6, s[4:5]
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v4, v4, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v5, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v6, v4, s[4:5]
s_branch .LBB0_2
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Find_VertexP6VertexP4EdgePiS3_S3_, .Lfunc_end0-_Z11Find_VertexP6VertexP4EdgePiS3_S3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z11Find_VertexP6VertexP4EdgePiS3_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Author: Jose F. Martinez Rivera
// Course: ICOM4036 - 040
// Professor: Wilson Rivera Gallego
// Assignment 2 - CUDA Implementation
#define V 8
#define E 11
#define MAX_WEIGHT 1000000
#define TRUE 1
#define FALSE 0
typedef int boolean;
//
//Represents an edge or path between Vertices
typedef struct
{
int u;
int v;
} Edge;
//Represents a Vertex
typedef struct
{
int title;
boolean visited;
} Vertex;
//Finds the weight of the path from vertex u to vertex v
__device__ __host__ int findEdge(Vertex u, Vertex v, Edge *edges, int *weights)
{
int i;
for(i = 0; i < E; i++)
{
if(edges[i].u == u.title && edges[i].v == v.title)
{
return weights[i];
}
}
return MAX_WEIGHT;
}
__global__ void Find_Vertex(Vertex *vertices, Edge *edges, int *weights, int *length, int *updateLength)
{
int u = threadIdx.x;
if(vertices[u].visited == FALSE)
{
vertices[u].visited = TRUE;
int v;
for(v = 0; v < V; v++)
{
//Find the weight of the edge
int weight = findEdge(vertices[u], vertices[v], edges, weights);
//Checks if the weight is a candidate
if(weight < MAX_WEIGHT)
{
//If the weight is shorter than the current weight, replace it
if(updateLength[v] > length[u] + weight)
{
updateLength[v] = length[u] + weight;
}
}
}
}
} | .text
.file "Find_Vertex.hip"
.globl _Z8findEdge6VertexS_P4EdgePi # -- Begin function _Z8findEdge6VertexS_P4EdgePi
.p2align 4, 0x90
.type _Z8findEdge6VertexS_P4EdgePi,@function
_Z8findEdge6VertexS_P4EdgePi: # @_Z8findEdge6VertexS_P4EdgePi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_1 Depth=1
incq %rax
cmpq $11, %rax
je .LBB0_5
.LBB0_1: # =>This Inner Loop Header: Depth=1
cmpl %edi, (%rdx,%rax,8)
jne .LBB0_4
# %bb.2: # in Loop: Header=BB0_1 Depth=1
cmpl %esi, 4(%rdx,%rax,8)
jne .LBB0_4
# %bb.3:
movl (%rcx,%rax,4), %eax
retq
.LBB0_5:
movl $1000000, %eax # imm = 0xF4240
retq
.Lfunc_end0:
.size _Z8findEdge6VertexS_P4EdgePi, .Lfunc_end0-_Z8findEdge6VertexS_P4EdgePi
.cfi_endproc
# -- End function
.globl _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_ # -- Begin function _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.p2align 4, 0x90
.type _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_,@function
_Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_: # @_Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Find_VertexP6VertexP4EdgePiS3_S3_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_, .Lfunc_end1-_Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Find_VertexP6VertexP4EdgePiS3_S3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Find_VertexP6VertexP4EdgePiS3_S3_,@object # @_Z11Find_VertexP6VertexP4EdgePiS3_S3_
.section .rodata,"a",@progbits
.globl _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.p2align 3, 0x0
_Z11Find_VertexP6VertexP4EdgePiS3_S3_:
.quad _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.size _Z11Find_VertexP6VertexP4EdgePiS3_S3_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Find_VertexP6VertexP4EdgePiS3_S3_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ea4000c1e1900 */
/*0060*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0001e2000c101904 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e00ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0110*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea8000c1e1900 */
/*0120*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000162000c1e1900 */
/*0140*/ IADD3 R10, R10, 0x2, RZ ; /* 0x000000020a0a7810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B1, 0x770 ; /* 0x0000061000017945 */
/* 0x000fe20003800000 */
/*0160*/ BSSY B0, 0x730 ; /* 0x000005c000007945 */
/* 0x000fe40003800000 */
/*0170*/ ISETP.NE.AND P0, PT, R10, 0x8, PT ; /* 0x000000080a00780c */
/* 0x000fc40003f05270 */
/*0180*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0190*/ @P1 BRA 0x1f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x001ea2000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*01e0*/ @!P1 BRA 0x720 ; /* 0x0000053000009947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x001ea4000c1e1900 */
/*0200*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0210*/ @P1 BRA 0x270 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ HFMA2.MMA R15, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0f7435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0250*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0260*/ @!P1 BRA 0x720 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R15, [R4.64+0x10] ; /* 0x00001004040f7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0290*/ @P1 BRA 0x2f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x2 ; /* 0x00000002ff0f7424 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*02e0*/ @!P1 BRA 0x720 ; /* 0x0000043000009947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R15, [R4.64+0x18] ; /* 0x00001804040f7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0310*/ @P1 BRA 0x370 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0320*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0330*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3 ; /* 0x00000003ff0f7424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0350*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0360*/ @!P1 BRA 0x720 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R15, [R4.64+0x20] ; /* 0x00002004040f7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0390*/ @P1 BRA 0x3f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R14, [R4.64+0x24] ; /* 0x00002404040e7981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*03d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*03e0*/ @!P1 BRA 0x720 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*03f0*/ LDG.E R15, [R4.64+0x28] ; /* 0x00002804040f7981 */
/* 0x000ea4000c1e1900 */
/*0400*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0410*/ @P1 BRA 0x470 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0420*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.MOV.U32 R15, RZ, RZ, 0x5 ; /* 0x00000005ff0f7424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0450*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0460*/ @!P1 BRA 0x720 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R15, [R4.64+0x30] ; /* 0x00003004040f7981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0490*/ @P1 BRA 0x4f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*04a0*/ LDG.E R14, [R4.64+0x34] ; /* 0x00003404040e7981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x6 ; /* 0x00000006ff0f7424 */
/* 0x000fe200078e00ff */
/*04c0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe40000000f00 */
/*04d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*04e0*/ @!P1 BRA 0x720 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*04f0*/ LDG.E R15, [R4.64+0x38] ; /* 0x00003804040f7981 */
/* 0x000ea4000c1e1900 */
/*0500*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0510*/ @P1 BRA 0x570 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E R14, [R4.64+0x3c] ; /* 0x00003c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, 0x7 ; /* 0x00000007ff0f7424 */
/* 0x000fe400078e00ff */
/*0540*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0550*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0560*/ @!P1 BRA 0x720 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R15, [R4.64+0x40] ; /* 0x00004004040f7981 */
/* 0x000ea4000c1e1900 */
/*0580*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0590*/ @P1 BRA 0x5f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*05a0*/ LDG.E R14, [R4.64+0x44] ; /* 0x00004404040e7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe400078e00ff */
/*05c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*05d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*05e0*/ @!P1 BRA 0x720 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R15, [R4.64+0x48] ; /* 0x00004804040f7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*0610*/ @P1 BRA 0x670 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R14, [R4.64+0x4c] ; /* 0x00004c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.MOV.U32 R15, RZ, RZ, 0x9 ; /* 0x00000009ff0f7424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0650*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*0660*/ @!P1 BRA 0x720 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0670*/ LDG.E R15, [R4.64+0x50] ; /* 0x00005004040f7981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, 0xf4240 ; /* 0x000f4240ff107424 */
/* 0x000fe200078e00ff */
/*0690*/ ISETP.NE.AND P1, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f25270 */
/*06a0*/ @P1 BREAK B0 ; /* 0x0000000000001942 */
/* 0x000fe20003800000 */
/*06b0*/ @P1 BRA 0x760 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R14, [R4.64+0x54] ; /* 0x00005404040e7981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x024fda0003f25270 */
/*06e0*/ @P1 BREAK B0 ; /* 0x0000000000001942 */
/* 0x000fe20003800000 */
/*06f0*/ @P1 BRA 0x760 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R15, RZ, RZ, 0xa ; /* 0x0000000aff0f7424 */
/* 0x000fe400078e00ff */
/*0710*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ LEA R14, P1, R15, c[0x0][0x170], 0x2 ; /* 0x00005c000f0e7a11 */
/* 0x000fc800078210ff */
/*0740*/ LEA.HI.X R15, R15, c[0x0][0x174], R16, 0x2, P1 ; /* 0x00005d000f0f7a11 */
/* 0x000fca00008f1410 */
/*0750*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000168000c1e1900 */
/*0760*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0770*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0780*/ ISETP.GT.AND P1, PT, R16, 0xf423f, PT ; /* 0x000f423f1000780c */
/* 0x020fe20003f24270 */
/*0790*/ BSSY B1, 0x850 ; /* 0x000000b000017945 */
/* 0x000fd80003800000 */
/*07a0*/ @P1 BRA 0x840 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*07b0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x001fe200000001ff */
/*07c0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000eb2000c1e1900 */
/*07d0*/ IMAD.WIDE R14, R0, R15, c[0x0][0x178] ; /* 0x00005e00000e7625 */
/* 0x000fcc00078e020f */
/*07e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee4000c1e1900 */
/*07f0*/ IMAD.IADD R16, R15, 0x1, R16 ; /* 0x000000010f107824 */
/* 0x008fca00078e0210 */
/*0800*/ ISETP.GT.AND P1, PT, R13, R16, PT ; /* 0x000000100d00720c */
/* 0x004fda0003f24270 */
/*0810*/ @P1 STG.E [R8.64], R16 ; /* 0x0000001008001986 */
/* 0x0001e8000c101904 */
/*0820*/ @P1 LDG.E R12, [R2.64] ; /* 0x00000004020c1981 */
/* 0x000168000c1e1900 */
/*0830*/ @P1 LDG.E R11, [R4.64] ; /* 0x00000004040b1981 */
/* 0x000164000c1e1900 */
/*0840*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R13, [R6.64+0x8] ; /* 0x00000804060d7981 */
/* 0x000364000c1e1900 */
/*0860*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x020fe20003f25270 */
/*0870*/ BSSY B2, 0xe70 ; /* 0x000005f000027945 */
/* 0x000fe20003800000 */
/*0880*/ BSSY B1, 0xe30 ; /* 0x000005a000017945 */
/* 0x000ff60003800000 */
/*0890*/ @P1 BRA 0x8f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x003ea2000c1e1900 */
/*08b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*08c0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*08d0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*08e0*/ @!P1 BRA 0xe20 ; /* 0x0000053000009947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x002ea4000c1e1900 */
/*0900*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0910*/ @P1 BRA 0x970 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0920*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0930*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0940*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0950*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0960*/ @!P1 BRA 0xe20 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0970*/ LDG.E R11, [R4.64+0x10] ; /* 0x00001004040b7981 */
/* 0x000ea4000c1e1900 */
/*0980*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0990*/ @P1 BRA 0x9f0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*09a0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x001ea2000c1e1900 */
/*09b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x2 ; /* 0x00000002ff0b7424 */
/* 0x000fe200078e00ff */
/*09c0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*09d0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*09e0*/ @!P1 BRA 0xe20 ; /* 0x0000043000009947 */
/* 0x000fea0003800000 */
/*09f0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000ea4000c1e1900 */
/*0a00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0a10*/ @P1 BRA 0xa70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0a20*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3 ; /* 0x00000003ff0b7424 */
/* 0x000fe200078e00ff */
/*0a40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0a50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0a60*/ @!P1 BRA 0xe20 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0a70*/ LDG.E R11, [R4.64+0x20] ; /* 0x00002004040b7981 */
/* 0x000ea4000c1e1900 */
/*0a80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0a90*/ @P1 BRA 0xaf0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R14, [R4.64+0x24] ; /* 0x00002404040e7981 */
/* 0x001ea2000c1e1900 */
/*0ab0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*0ac0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0ad0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0ae0*/ @!P1 BRA 0xe20 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0af0*/ LDG.E R11, [R4.64+0x28] ; /* 0x00002804040b7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0b10*/ @P1 BRA 0xb70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0b20*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0b30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x5 ; /* 0x00000005ff0b7424 */
/* 0x000fe200078e00ff */
/*0b40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0b50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0b60*/ @!P1 BRA 0xe20 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0b70*/ LDG.E R11, [R4.64+0x30] ; /* 0x00003004040b7981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0b90*/ @P1 BRA 0xbf0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0ba0*/ LDG.E R14, [R4.64+0x34] ; /* 0x00003404040e7981 */
/* 0x001ea2000c1e1900 */
/*0bb0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x6 ; /* 0x00000006ff0b7424 */
/* 0x000fe200078e00ff */
/*0bc0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0bd0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0be0*/ @!P1 BRA 0xe20 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*0bf0*/ LDG.E R11, [R4.64+0x38] ; /* 0x00003804040b7981 */
/* 0x000ea4000c1e1900 */
/*0c00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0c10*/ @P1 BRA 0xc70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0c20*/ LDG.E R14, [R4.64+0x3c] ; /* 0x00003c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0c30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7 ; /* 0x00000007ff0b7424 */
/* 0x000fe200078e00ff */
/*0c40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0c50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0c60*/ @!P1 BRA 0xe20 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0c70*/ LDG.E R11, [R4.64+0x40] ; /* 0x00004004040b7981 */
/* 0x000ea4000c1e1900 */
/*0c80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0c90*/ @P1 BRA 0xcf0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E R14, [R4.64+0x44] ; /* 0x00004404040e7981 */
/* 0x001ea2000c1e1900 */
/*0cb0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*0cc0*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0cd0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0ce0*/ @!P1 BRA 0xe20 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0cf0*/ LDG.E R11, [R4.64+0x48] ; /* 0x00004804040b7981 */
/* 0x000ea4000c1e1900 */
/*0d00*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f25270 */
/*0d10*/ @P1 BRA 0xd70 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0d20*/ LDG.E R14, [R4.64+0x4c] ; /* 0x00004c04040e7981 */
/* 0x001ea2000c1e1900 */
/*0d30*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.36441802978515625e-07 ; /* 0x00000009ff0b7435 */
/* 0x000fe200000001ff */
/*0d40*/ ISETP.NE.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fe20003f25270 */
/*0d50*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd800078e00ff */
/*0d60*/ @!P1 BRA 0xe20 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0d70*/ LDG.E R11, [R4.64+0x50] ; /* 0x00005004040b7981 */
/* 0x000ea4000c1e1900 */
/*0d80*/ ISETP.NE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fe20003f25270 */
/*0d90*/ IMAD.MOV.U32 R11, RZ, RZ, 0xf4240 ; /* 0x000f4240ff0b7424 */
/* 0x000fd800078e00ff */
/*0da0*/ @P1 BREAK B1 ; /* 0x0000000000011942 */
/* 0x000fe20003800000 */
/*0db0*/ @P1 BRA 0xe60 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0dc0*/ LDG.E R12, [R4.64+0x54] ; /* 0x00005404040c7981 */
/* 0x000ea4000c1e1900 */
/*0dd0*/ ISETP.NE.AND P1, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x004fda0003f25270 */
/*0de0*/ @P1 BREAK B1 ; /* 0x0000000000011942 */
/* 0x000fe20003800000 */
/*0df0*/ @P1 BRA 0xe60 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0e00*/ IMAD.MOV.U32 R11, RZ, RZ, 0xa ; /* 0x0000000aff0b7424 */
/* 0x000fe400078e00ff */
/*0e10*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0e20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0e30*/ LEA R12, P1, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b0c7a11 */
/* 0x000fc800078210ff */
/*0e40*/ LEA.HI.X R13, R11, c[0x0][0x174], R14, 0x2, P1 ; /* 0x00005d000b0d7a11 */
/* 0x000fca00008f140e */
/*0e50*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000168000c1e1900 */
/*0e60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e70*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0e80*/ ISETP.GT.AND P1, PT, R11, 0xf423f, PT ; /* 0x000f423f0b00780c */
/* 0x020fe20003f24270 */
/*0e90*/ BSSY B2, 0xf30 ; /* 0x0000009000027945 */
/* 0x000fd80003800000 */
/*0ea0*/ @P1 BRA 0xf20 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0eb0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x001fe200078e00ff */
/*0ec0*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ea6000c1e1900 */
/*0ed0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x178] ; /* 0x00005e00000c7625 */
/* 0x000fcc00078e020d */
/*0ee0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0ef0*/ IMAD.IADD R11, R12, 0x1, R11 ; /* 0x000000010c0b7824 */
/* 0x008fca00078e020b */
/*0f00*/ ISETP.GT.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x004fda0003f24270 */
/*0f10*/ @P1 STG.E [R8.64+0x4], R11 ; /* 0x0000040b08001986 */
/* 0x0001e4000c101904 */
/*0f20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f30*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x001fe40007f3e0ff */
/*0f40*/ IADD3 R6, P2, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007f5e0ff */
/*0f50*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*0f60*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0f70*/ @!P0 CALL.REL.NOINC 0xf90 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*0f80*/ BRA 0x110 ; /* 0xfffff18000007947 */
/* 0x000fea000383ffff */
/*0f90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fa0*/ BRA 0xfa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.globl _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.p2align 8
.type _Z11Find_VertexP6VertexP4EdgePiS3_S3_,@function
_Z11Find_VertexP6VertexP4EdgePiS3_S3_:
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
s_mov_b32 s11, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[8:9] offset:4
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_14
s_load_b256 s[0:7], s[0:1], 0x8
v_add_co_u32 v1, s10, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v2, null, s9, 0, s10
v_lshlrev_b32_e32 v3, 3, v0
v_dual_mov_b32 v7, 1 :: v_dual_lshlrev_b32 v6, 2, v0
v_add_co_u32 v4, vcc_lo, v1, 4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
global_store_b32 v[4:5], v7, off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s4, s4, v6
v_mov_b32_e32 v6, 0
v_add_co_u32 v0, s10, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s9, 0, s10
v_add_co_ci_u32_e64 v3, null, s5, 0, s4
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_mov_b32 s10, s11
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, 8
s_cbranch_scc0 .LBB0_14
.LBB0_3:
s_lshl_b64 s[4:5], s[10:11], 3
s_mov_b64 s[12:13], 0
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_clause 0x1
global_load_b32 v7, v[0:1], off
global_load_b32 v8, v6, s[4:5]
s_mov_b32 s14, 0
s_mov_b64 s[4:5], s[0:1]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s17, exec_lo, s20
v_mov_b32_e32 v9, s19
s_or_b32 s14, s17, s14
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s17, s16, exec_lo
s_or_b32 s15, s15, s17
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_9
.LBB0_5:
global_load_b32 v4, v6, s[4:5] offset:-4
s_mov_b32 s19, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s17, v4, v7
v_cmpx_eq_u32_e64 v4, v7
s_cbranch_execz .LBB0_7
global_load_b32 v4, v6, s[4:5]
s_and_not1_b32 s17, s17, exec_lo
s_mov_b32 s18, -1
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v4, v8
s_and_b32 s20, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s17, s17, s20
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s19
v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
s_and_not1_b32 s16, s16, exec_lo
s_and_b32 s18, s18, exec_lo
s_mov_b32 s20, -1
s_or_b32 s16, s16, s18
s_and_saveexec_b32 s18, s17
s_cbranch_execz .LBB0_4
s_add_u32 s22, s12, 4
s_addc_u32 s23, s13, 0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s22, 44
v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
s_cselect_b32 s17, -1, 0
s_mov_b32 s19, 0xf4240
s_and_not1_b32 s16, s16, exec_lo
s_or_not1_b32 s20, s17, exec_lo
s_mov_b64 s[12:13], s[22:23]
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s4, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_11
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v9, v[4:5], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0xf4240, v9
s_cbranch_execz .LBB0_2
s_lshl_b64 s[4:5], s[10:11], 2
global_load_b32 v4, v[2:3], off
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
global_load_b32 v5, v6, s[4:5]
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v4, v4, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v5, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v6, v4, s[4:5]
s_branch .LBB0_2
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Find_VertexP6VertexP4EdgePiS3_S3_, .Lfunc_end0-_Z11Find_VertexP6VertexP4EdgePiS3_S3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z11Find_VertexP6VertexP4EdgePiS3_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bfcde_00000000-6_Find_Vertex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8findEdge6VertexS_P4EdgePi
.type _Z8findEdge6VertexS_P4EdgePi, @function
_Z8findEdge6VertexS_P4EdgePi:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
jmp .L6
.L4:
addq $1, %rax
cmpq $11, %rax
je .L8
.L6:
cmpl %edi, (%rdx,%rax,8)
jne .L4
cmpl %esi, 4(%rdx,%rax,8)
jne .L4
movl (%rcx,%rax,4), %eax
ret
.L8:
movl $1000000, %eax
ret
.cfi_endproc
.LFE2027:
.size _Z8findEdge6VertexS_P4EdgePi, .-_Z8findEdge6VertexS_P4EdgePi
.globl _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_
.type _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_, @function
_Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Find_VertexP6VertexP4EdgePiS3_S3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_, .-_Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_
.globl _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.type _Z11Find_VertexP6VertexP4EdgePiS3_S3_, @function
_Z11Find_VertexP6VertexP4EdgePiS3_S3_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z11Find_VertexP6VertexP4EdgePiS3_S3_P6VertexP4EdgePiS3_S3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11Find_VertexP6VertexP4EdgePiS3_S3_, .-_Z11Find_VertexP6VertexP4EdgePiS3_S3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11Find_VertexP6VertexP4EdgePiS3_S3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Find_VertexP6VertexP4EdgePiS3_S3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Find_Vertex.hip"
.globl _Z8findEdge6VertexS_P4EdgePi # -- Begin function _Z8findEdge6VertexS_P4EdgePi
.p2align 4, 0x90
.type _Z8findEdge6VertexS_P4EdgePi,@function
_Z8findEdge6VertexS_P4EdgePi: # @_Z8findEdge6VertexS_P4EdgePi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_1 Depth=1
incq %rax
cmpq $11, %rax
je .LBB0_5
.LBB0_1: # =>This Inner Loop Header: Depth=1
cmpl %edi, (%rdx,%rax,8)
jne .LBB0_4
# %bb.2: # in Loop: Header=BB0_1 Depth=1
cmpl %esi, 4(%rdx,%rax,8)
jne .LBB0_4
# %bb.3:
movl (%rcx,%rax,4), %eax
retq
.LBB0_5:
movl $1000000, %eax # imm = 0xF4240
retq
.Lfunc_end0:
.size _Z8findEdge6VertexS_P4EdgePi, .Lfunc_end0-_Z8findEdge6VertexS_P4EdgePi
.cfi_endproc
# -- End function
.globl _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_ # -- Begin function _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.p2align 4, 0x90
.type _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_,@function
_Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_: # @_Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Find_VertexP6VertexP4EdgePiS3_S3_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_, .Lfunc_end1-_Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Find_VertexP6VertexP4EdgePiS3_S3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Find_VertexP6VertexP4EdgePiS3_S3_,@object # @_Z11Find_VertexP6VertexP4EdgePiS3_S3_
.section .rodata,"a",@progbits
.globl _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.p2align 3, 0x0
_Z11Find_VertexP6VertexP4EdgePiS3_S3_:
.quad _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.size _Z11Find_VertexP6VertexP4EdgePiS3_S3_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Find_VertexP6VertexP4EdgePiS3_S3_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Find_VertexP6VertexP4EdgePiS3_S3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Find_VertexP6VertexP4EdgePiS3_S3_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gArgmax(float* out, const float* data, size_t rows, size_t cols) {
size_t row = blockIdx.x;
size_t startInd = row * cols;
float maxScore = -99999;
size_t maxInd;
for(size_t col = 0; col < cols; ++col) {
size_t ind = startInd + col;
float score = data[ind];
if(score > maxScore) {
maxScore = score;
maxInd = col;
}
}
out[row] = maxInd;
} | code for sm_80
Function : _Z7gArgmaxPfPKfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*0020*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR18, c[0x0][0x118] ; /* 0x0000460000127ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*0050*/ @!P0 BRA 0x590 ; /* 0x0000053000008947 */
/* 0x001fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0070*/ UMOV UR11, 0x3 ; /* 0x00000003000b7882 */
/* 0x000fe20000000000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R0, P0, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe20007f1e1ff */
/*00c0*/ ULOP3.LUT UR11, UR11, UR8, URZ, 0xc0, !UPT ; /* 0x000000080b0b7292 */
/* 0x000fe2000f8ec03f */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00e0*/ UIMAD.WIDE.U32 UR4, UR6, UR8, URZ ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e003f */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*0100*/ IADD3.X R0, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02007810 */
/* 0x000fe200007fe4ff */
/*0110*/ UIMAD UR12, UR6, UR9, UR5 ; /* 0x00000009060c72a4 */
/* 0x000fe2000f8e0205 */
/*0120*/ ISETP.NE.U32.AND P0, PT, RZ, UR11, PT ; /* 0x0000000bff007c0c */
/* 0x000fc4000bf05070 */
/*0130*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe20003f26110 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, -0x383cb080 ; /* 0xc7c34f80ff007424 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0160*/ @!P1 BRA 0x430 ; /* 0x000002c000009947 */
/* 0x000fea0003800000 */
/*0170*/ ULDC.64 UR14, c[0x0][0x168] ; /* 0x00005a00000e7ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD.MOV.U32 R0, RZ, RZ, -0x383cb080 ; /* 0xc7c34f80ff007424 */
/* 0x000fe200078e00ff */
/*0190*/ ULEA UR9, UP0, UR4, UR14, 0x2 ; /* 0x0000000e04097291 */
/* 0x000fe2000f80103f */
/*01a0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR16, c[0x0][0x178] ; /* 0x00005e0000107ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*01d0*/ ULEA.HI.X UR10, UR4, UR15, UR12, 0x2, UP0 ; /* 0x0000000f040a7291 */
/* 0x000fe400080f140c */
/*01e0*/ UIADD3 UR9, UP0, UR9, 0x8, URZ ; /* 0x0000000809097890 */
/* 0x000fe4000ff1e03f */
/*01f0*/ UIADD3 UR7, UP1, UR11, -UR16, URZ ; /* 0x800000100b077290 */
/* 0x000fc4000ff3e03f */
/*0200*/ UIADD3.X UR10, URZ, UR10, URZ, UP0, !UPT ; /* 0x0000000a3f0a7290 */
/* 0x000fe400087fe43f */
/*0210*/ IMAD.U32 R2, RZ, RZ, UR9 ; /* 0x00000009ff027e24 */
/* 0x000fe2000f8e00ff */
/*0220*/ UIADD3.X UR8, URZ, ~UR17, URZ, UP1, !UPT ; /* 0x800000113f087290 */
/* 0x000fc60008ffe43f */
/*0230*/ IMAD.U32 R3, RZ, RZ, UR10 ; /* 0x0000000aff037e24 */
/* 0x000fca000f8e00ff */
/*0240*/ LDG.E R5, [R2.64+-0x8] ; /* 0xfffff81202057981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc1202077981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R9, [R2.64] ; /* 0x0000001202097981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000412020b7981 */
/* 0x000f62000c1e1900 */
/*0280*/ IADD3 R13, P3, R17, 0x1, RZ ; /* 0x00000001110d7810 */
/* 0x000fca0007f7e0ff */
/*0290*/ IMAD.X R6, RZ, RZ, R10, P3 ; /* 0x000000ffff067224 */
/* 0x000fe200018e060a */
/*02a0*/ FSETP.GT.AND P1, PT, R5, R0, PT ; /* 0x000000000500720b */
/* 0x004fc80003f24000 */
/*02b0*/ FSEL R0, R5, R0, P1 ; /* 0x0000000005007208 */
/* 0x000fc80000800000 */
/*02c0*/ FSETP.GT.AND P2, PT, R7, R0, PT ; /* 0x000000000700720b */
/* 0x008fc80003f44000 */
/*02d0*/ FSEL R0, R7, R0, P2 ; /* 0x0000000007007208 */
/* 0x000fc80001000000 */
/*02e0*/ FSETP.GT.AND P3, PT, R9, R0, PT ; /* 0x000000000900720b */
/* 0x010fc80003f64000 */
/*02f0*/ FSEL R0, R9, R0, P3 ; /* 0x0000000009007208 */
/* 0x000fe40001800000 */
/*0300*/ @!P2 SEL R13, R17.reuse, R8, P1 ; /* 0x00000008110da207 */
/* 0x040fe40000800000 */
/*0310*/ @!P2 SEL R6, R10, R15, P1 ; /* 0x0000000f0a06a207 */
/* 0x000fe40000800000 */
/*0320*/ IADD3 R4, P2, R17.reuse, 0x2, RZ ; /* 0x0000000211047810 */
/* 0x040fe40007f5e0ff */
/*0330*/ IADD3 R8, P4, R17.reuse, 0x3, RZ ; /* 0x0000000311087810 */
/* 0x040fe40007f9e0ff */
/*0340*/ IADD3 R17, P1, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007f3e0ff */
/*0350*/ IMAD.X R5, RZ, RZ, R10.reuse, P2 ; /* 0x000000ffff057224 */
/* 0x100fe200010e060a */
/*0360*/ FSETP.GT.AND P2, PT, R11, R0.reuse, PT ; /* 0x000000000b00720b */
/* 0x0a0fe20003f44000 */
/*0370*/ IMAD.X R15, RZ, RZ, R10.reuse, P4 ; /* 0x000000ffff0f7224 */
/* 0x100fe200020e060a */
/*0380*/ IADD3 R7, P4, R17, UR7, RZ ; /* 0x0000000711077c10 */
/* 0x000fe2000ff9e0ff */
/*0390*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*03a0*/ FSEL R0, R11, R0, P2 ; /* 0x000000000b007208 */
/* 0x000fc40001000000 */
/*03b0*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25070 */
/*03c0*/ IADD3.X R7, R10, UR8, RZ, P4, !PT ; /* 0x000000080a077c10 */
/* 0x000fe4000a7fe4ff */
/*03d0*/ IADD3 R2, P4, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007f9e0ff */
/*03e0*/ ISETP.NE.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40003f25310 */
/*03f0*/ @!P2 SEL R8, R4, R13, P3 ; /* 0x0000000d0408a207 */
/* 0x000fe20001800000 */
/*0400*/ IMAD.X R3, RZ, RZ, R3, P4 ; /* 0x000000ffff037224 */
/* 0x000fe200020e0603 */
/*0410*/ @!P2 SEL R15, R5, R6, P3 ; /* 0x00000006050fa207 */
/* 0x000fd20001800000 */
/*0420*/ @P1 BRA 0x240 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 BRA 0x590 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R5, P0, R17, UR4, RZ ; /* 0x0000000411057c10 */
/* 0x000fe2000ff1e0ff */
/*0450*/ UIADD3 UR4, UP0, URZ, -UR11, URZ ; /* 0x8000000b3f047290 */
/* 0x000fc6000ff1e03f */
/*0460*/ LEA R2, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005027a11 */
/* 0x000fe200078210ff */
/*0470*/ UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f057890 */
/* 0x000fe200087fe43f */
/*0480*/ IADD3.X R4, R10, UR12, RZ, P0, !PT ; /* 0x0000000c0a047c10 */
/* 0x000fc800087fe4ff */
/*0490*/ LEA.HI.X R5, R5, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b0005057a11 */
/* 0x000fca00008f1404 */
/*04a0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0005 */
/*04b0*/ LDG.E R3, [R2.64] ; /* 0x0000001202037981 */
/* 0x0000a2000c1e1900 */
/*04c0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc8000ff1e03f */
/*04d0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*04e0*/ ISETP.NE.U32.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05070 */
/*04f0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f5e0ff */
/*0500*/ ISETP.NE.AND.EX P0, PT, RZ, UR5, PT, P0 ; /* 0x00000005ff007c0c */
/* 0x000fc6000bf05300 */
/*0510*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0520*/ FSETP.GT.AND P1, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fc80003f24000 */
/*0530*/ SEL R8, R17.reuse, R8, P1 ; /* 0x0000000811087207 */
/* 0x040fe40000800000 */
/*0540*/ IADD3 R17, P3, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe40007f7e0ff */
/*0550*/ SEL R15, R10, R15, P1 ; /* 0x0000000f0a0f7207 */
/* 0x000fe40000800000 */
/*0560*/ FSEL R0, R3, R0, P1 ; /* 0x0000000003007208 */
/* 0x000fe20000800000 */
/*0570*/ IMAD.X R10, RZ, RZ, R10, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200018e060a */
/*0580*/ @P0 BRA 0x4a0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*05a0*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*05c0*/ ULEA UR4, UP0, UR6, UR4, 0x2 ; /* 0x0000000406047291 */
/* 0x000fc6000f80103f */
/*05d0*/ I2F.U64 R3, R2 ; /* 0x0000000200037312 */
/* 0x000e220000301000 */
/*05e0*/ ULEA.HI.X UR6, UR6, UR5, URZ, 0x2, UP0 ; /* 0x0000000506067291 */
/* 0x000fe400080f143f */
/*05f0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fc8000f8e00ff */
/*0600*/ IMAD.U32 R5, RZ, RZ, UR6 ; /* 0x00000006ff057e24 */
/* 0x000fca000f8e00ff */
/*0610*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101912 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gArgmax(float* out, const float* data, size_t rows, size_t cols) {
size_t row = blockIdx.x;
size_t startInd = row * cols;
float maxScore = -99999;
size_t maxInd;
for(size_t col = 0; col < cols; ++col) {
size_t ind = startInd + col;
float score = data[ind];
if(score > maxScore) {
maxScore = score;
maxInd = col;
}
}
out[row] = maxInd;
} | .file "tmpxft_000c209f_00000000-6_gArgmax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm
.type _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm, @function
_Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7gArgmaxPfPKfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm, .-_Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm
.globl _Z7gArgmaxPfPKfmm
.type _Z7gArgmaxPfPKfmm, @function
_Z7gArgmaxPfPKfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7gArgmaxPfPKfmm, .-_Z7gArgmaxPfPKfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7gArgmaxPfPKfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7gArgmaxPfPKfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gArgmax(float* out, const float* data, size_t rows, size_t cols) {
size_t row = blockIdx.x;
size_t startInd = row * cols;
float maxScore = -99999;
size_t maxInd;
for(size_t col = 0; col < cols; ++col) {
size_t ind = startInd + col;
float score = data[ind];
if(score > maxScore) {
maxScore = score;
maxInd = col;
}
}
out[row] = maxInd;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gArgmax(float* out, const float* data, size_t rows, size_t cols) {
size_t row = blockIdx.x;
size_t startInd = row * cols;
float maxScore = -99999;
size_t maxInd;
for(size_t col = 0; col < cols; ++col) {
size_t ind = startInd + col;
float score = data[ind];
if(score > maxScore) {
maxScore = score;
maxInd = col;
}
}
out[row] = maxInd;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gArgmax(float* out, const float* data, size_t rows, size_t cols) {
size_t row = blockIdx.x;
size_t startInd = row * cols;
float maxScore = -99999;
size_t maxInd;
for(size_t col = 0; col < cols; ++col) {
size_t ind = startInd + col;
float score = data[ind];
if(score > maxScore) {
maxScore = score;
maxInd = col;
}
}
out[row] = maxInd;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7gArgmaxPfPKfmm
.globl _Z7gArgmaxPfPKfmm
.p2align 8
.type _Z7gArgmaxPfPKfmm,@function
_Z7gArgmaxPfPKfmm:
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x8
s_mul_i32 s10, s2, s5
s_mul_hi_u32 s11, s2, s4
v_mov_b32_e32 v0, 0xc7c34f80
s_add_i32 s11, s11, s10
s_mul_i32 s10, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
.LBB0_2:
s_load_b32 s12, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s12, v0
v_cndmask_b32_e64 v0, v0, s12, vcc_lo
s_and_b32 s12, vcc_lo, exec_lo
s_cselect_b32 s11, s7, s11
s_cselect_b32 s10, s6, s10
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_eq_u64 s[4:5], s[6:7]
s_cbranch_scc0 .LBB0_2
s_clz_i32_u32 s4, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s6, s4, 32
s_lshl_b64 s[4:5], s[10:11], s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s4, s4, 1
s_or_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s4, 32, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f32 v0, v0, s4
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7gArgmaxPfPKfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7gArgmaxPfPKfmm, .Lfunc_end0-_Z7gArgmaxPfPKfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7gArgmaxPfPKfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7gArgmaxPfPKfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gArgmax(float* out, const float* data, size_t rows, size_t cols) {
size_t row = blockIdx.x;
size_t startInd = row * cols;
float maxScore = -99999;
size_t maxInd;
for(size_t col = 0; col < cols; ++col) {
size_t ind = startInd + col;
float score = data[ind];
if(score > maxScore) {
maxScore = score;
maxInd = col;
}
}
out[row] = maxInd;
} | .text
.file "gArgmax.hip"
.globl _Z22__device_stub__gArgmaxPfPKfmm # -- Begin function _Z22__device_stub__gArgmaxPfPKfmm
.p2align 4, 0x90
.type _Z22__device_stub__gArgmaxPfPKfmm,@function
_Z22__device_stub__gArgmaxPfPKfmm: # @_Z22__device_stub__gArgmaxPfPKfmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7gArgmaxPfPKfmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__gArgmaxPfPKfmm, .Lfunc_end0-_Z22__device_stub__gArgmaxPfPKfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7gArgmaxPfPKfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7gArgmaxPfPKfmm,@object # @_Z7gArgmaxPfPKfmm
.section .rodata,"a",@progbits
.globl _Z7gArgmaxPfPKfmm
.p2align 3, 0x0
_Z7gArgmaxPfPKfmm:
.quad _Z22__device_stub__gArgmaxPfPKfmm
.size _Z7gArgmaxPfPKfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7gArgmaxPfPKfmm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__gArgmaxPfPKfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7gArgmaxPfPKfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7gArgmaxPfPKfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*0020*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR18, c[0x0][0x118] ; /* 0x0000460000127ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*0050*/ @!P0 BRA 0x590 ; /* 0x0000053000008947 */
/* 0x001fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0070*/ UMOV UR11, 0x3 ; /* 0x00000003000b7882 */
/* 0x000fe20000000000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R0, P0, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe20007f1e1ff */
/*00c0*/ ULOP3.LUT UR11, UR11, UR8, URZ, 0xc0, !UPT ; /* 0x000000080b0b7292 */
/* 0x000fe2000f8ec03f */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00e0*/ UIMAD.WIDE.U32 UR4, UR6, UR8, URZ ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e003f */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*0100*/ IADD3.X R0, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02007810 */
/* 0x000fe200007fe4ff */
/*0110*/ UIMAD UR12, UR6, UR9, UR5 ; /* 0x00000009060c72a4 */
/* 0x000fe2000f8e0205 */
/*0120*/ ISETP.NE.U32.AND P0, PT, RZ, UR11, PT ; /* 0x0000000bff007c0c */
/* 0x000fc4000bf05070 */
/*0130*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe20003f26110 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, -0x383cb080 ; /* 0xc7c34f80ff007424 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0160*/ @!P1 BRA 0x430 ; /* 0x000002c000009947 */
/* 0x000fea0003800000 */
/*0170*/ ULDC.64 UR14, c[0x0][0x168] ; /* 0x00005a00000e7ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD.MOV.U32 R0, RZ, RZ, -0x383cb080 ; /* 0xc7c34f80ff007424 */
/* 0x000fe200078e00ff */
/*0190*/ ULEA UR9, UP0, UR4, UR14, 0x2 ; /* 0x0000000e04097291 */
/* 0x000fe2000f80103f */
/*01a0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR16, c[0x0][0x178] ; /* 0x00005e0000107ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*01d0*/ ULEA.HI.X UR10, UR4, UR15, UR12, 0x2, UP0 ; /* 0x0000000f040a7291 */
/* 0x000fe400080f140c */
/*01e0*/ UIADD3 UR9, UP0, UR9, 0x8, URZ ; /* 0x0000000809097890 */
/* 0x000fe4000ff1e03f */
/*01f0*/ UIADD3 UR7, UP1, UR11, -UR16, URZ ; /* 0x800000100b077290 */
/* 0x000fc4000ff3e03f */
/*0200*/ UIADD3.X UR10, URZ, UR10, URZ, UP0, !UPT ; /* 0x0000000a3f0a7290 */
/* 0x000fe400087fe43f */
/*0210*/ IMAD.U32 R2, RZ, RZ, UR9 ; /* 0x00000009ff027e24 */
/* 0x000fe2000f8e00ff */
/*0220*/ UIADD3.X UR8, URZ, ~UR17, URZ, UP1, !UPT ; /* 0x800000113f087290 */
/* 0x000fc60008ffe43f */
/*0230*/ IMAD.U32 R3, RZ, RZ, UR10 ; /* 0x0000000aff037e24 */
/* 0x000fca000f8e00ff */
/*0240*/ LDG.E R5, [R2.64+-0x8] ; /* 0xfffff81202057981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc1202077981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R9, [R2.64] ; /* 0x0000001202097981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000412020b7981 */
/* 0x000f62000c1e1900 */
/*0280*/ IADD3 R13, P3, R17, 0x1, RZ ; /* 0x00000001110d7810 */
/* 0x000fca0007f7e0ff */
/*0290*/ IMAD.X R6, RZ, RZ, R10, P3 ; /* 0x000000ffff067224 */
/* 0x000fe200018e060a */
/*02a0*/ FSETP.GT.AND P1, PT, R5, R0, PT ; /* 0x000000000500720b */
/* 0x004fc80003f24000 */
/*02b0*/ FSEL R0, R5, R0, P1 ; /* 0x0000000005007208 */
/* 0x000fc80000800000 */
/*02c0*/ FSETP.GT.AND P2, PT, R7, R0, PT ; /* 0x000000000700720b */
/* 0x008fc80003f44000 */
/*02d0*/ FSEL R0, R7, R0, P2 ; /* 0x0000000007007208 */
/* 0x000fc80001000000 */
/*02e0*/ FSETP.GT.AND P3, PT, R9, R0, PT ; /* 0x000000000900720b */
/* 0x010fc80003f64000 */
/*02f0*/ FSEL R0, R9, R0, P3 ; /* 0x0000000009007208 */
/* 0x000fe40001800000 */
/*0300*/ @!P2 SEL R13, R17.reuse, R8, P1 ; /* 0x00000008110da207 */
/* 0x040fe40000800000 */
/*0310*/ @!P2 SEL R6, R10, R15, P1 ; /* 0x0000000f0a06a207 */
/* 0x000fe40000800000 */
/*0320*/ IADD3 R4, P2, R17.reuse, 0x2, RZ ; /* 0x0000000211047810 */
/* 0x040fe40007f5e0ff */
/*0330*/ IADD3 R8, P4, R17.reuse, 0x3, RZ ; /* 0x0000000311087810 */
/* 0x040fe40007f9e0ff */
/*0340*/ IADD3 R17, P1, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007f3e0ff */
/*0350*/ IMAD.X R5, RZ, RZ, R10.reuse, P2 ; /* 0x000000ffff057224 */
/* 0x100fe200010e060a */
/*0360*/ FSETP.GT.AND P2, PT, R11, R0.reuse, PT ; /* 0x000000000b00720b */
/* 0x0a0fe20003f44000 */
/*0370*/ IMAD.X R15, RZ, RZ, R10.reuse, P4 ; /* 0x000000ffff0f7224 */
/* 0x100fe200020e060a */
/*0380*/ IADD3 R7, P4, R17, UR7, RZ ; /* 0x0000000711077c10 */
/* 0x000fe2000ff9e0ff */
/*0390*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*03a0*/ FSEL R0, R11, R0, P2 ; /* 0x000000000b007208 */
/* 0x000fc40001000000 */
/*03b0*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25070 */
/*03c0*/ IADD3.X R7, R10, UR8, RZ, P4, !PT ; /* 0x000000080a077c10 */
/* 0x000fe4000a7fe4ff */
/*03d0*/ IADD3 R2, P4, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007f9e0ff */
/*03e0*/ ISETP.NE.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40003f25310 */
/*03f0*/ @!P2 SEL R8, R4, R13, P3 ; /* 0x0000000d0408a207 */
/* 0x000fe20001800000 */
/*0400*/ IMAD.X R3, RZ, RZ, R3, P4 ; /* 0x000000ffff037224 */
/* 0x000fe200020e0603 */
/*0410*/ @!P2 SEL R15, R5, R6, P3 ; /* 0x00000006050fa207 */
/* 0x000fd20001800000 */
/*0420*/ @P1 BRA 0x240 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 BRA 0x590 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R5, P0, R17, UR4, RZ ; /* 0x0000000411057c10 */
/* 0x000fe2000ff1e0ff */
/*0450*/ UIADD3 UR4, UP0, URZ, -UR11, URZ ; /* 0x8000000b3f047290 */
/* 0x000fc6000ff1e03f */
/*0460*/ LEA R2, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005027a11 */
/* 0x000fe200078210ff */
/*0470*/ UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f057890 */
/* 0x000fe200087fe43f */
/*0480*/ IADD3.X R4, R10, UR12, RZ, P0, !PT ; /* 0x0000000c0a047c10 */
/* 0x000fc800087fe4ff */
/*0490*/ LEA.HI.X R5, R5, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b0005057a11 */
/* 0x000fca00008f1404 */
/*04a0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0005 */
/*04b0*/ LDG.E R3, [R2.64] ; /* 0x0000001202037981 */
/* 0x0000a2000c1e1900 */
/*04c0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc8000ff1e03f */
/*04d0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*04e0*/ ISETP.NE.U32.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05070 */
/*04f0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f5e0ff */
/*0500*/ ISETP.NE.AND.EX P0, PT, RZ, UR5, PT, P0 ; /* 0x00000005ff007c0c */
/* 0x000fc6000bf05300 */
/*0510*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0520*/ FSETP.GT.AND P1, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fc80003f24000 */
/*0530*/ SEL R8, R17.reuse, R8, P1 ; /* 0x0000000811087207 */
/* 0x040fe40000800000 */
/*0540*/ IADD3 R17, P3, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe40007f7e0ff */
/*0550*/ SEL R15, R10, R15, P1 ; /* 0x0000000f0a0f7207 */
/* 0x000fe40000800000 */
/*0560*/ FSEL R0, R3, R0, P1 ; /* 0x0000000003007208 */
/* 0x000fe20000800000 */
/*0570*/ IMAD.X R10, RZ, RZ, R10, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200018e060a */
/*0580*/ @P0 BRA 0x4a0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*05a0*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*05c0*/ ULEA UR4, UP0, UR6, UR4, 0x2 ; /* 0x0000000406047291 */
/* 0x000fc6000f80103f */
/*05d0*/ I2F.U64 R3, R2 ; /* 0x0000000200037312 */
/* 0x000e220000301000 */
/*05e0*/ ULEA.HI.X UR6, UR6, UR5, URZ, 0x2, UP0 ; /* 0x0000000506067291 */
/* 0x000fe400080f143f */
/*05f0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fc8000f8e00ff */
/*0600*/ IMAD.U32 R5, RZ, RZ, UR6 ; /* 0x00000006ff057e24 */
/* 0x000fca000f8e00ff */
/*0610*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101912 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7gArgmaxPfPKfmm
.globl _Z7gArgmaxPfPKfmm
.p2align 8
.type _Z7gArgmaxPfPKfmm,@function
_Z7gArgmaxPfPKfmm:
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x8
s_mul_i32 s10, s2, s5
s_mul_hi_u32 s11, s2, s4
v_mov_b32_e32 v0, 0xc7c34f80
s_add_i32 s11, s11, s10
s_mul_i32 s10, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
.LBB0_2:
s_load_b32 s12, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s12, v0
v_cndmask_b32_e64 v0, v0, s12, vcc_lo
s_and_b32 s12, vcc_lo, exec_lo
s_cselect_b32 s11, s7, s11
s_cselect_b32 s10, s6, s10
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_eq_u64 s[4:5], s[6:7]
s_cbranch_scc0 .LBB0_2
s_clz_i32_u32 s4, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s6, s4, 32
s_lshl_b64 s[4:5], s[10:11], s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s4, s4, 1
s_or_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s4, 32, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f32 v0, v0, s4
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7gArgmaxPfPKfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7gArgmaxPfPKfmm, .Lfunc_end0-_Z7gArgmaxPfPKfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7gArgmaxPfPKfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7gArgmaxPfPKfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c209f_00000000-6_gArgmax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm
.type _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm, @function
_Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7gArgmaxPfPKfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm, .-_Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm
.globl _Z7gArgmaxPfPKfmm
.type _Z7gArgmaxPfPKfmm, @function
_Z7gArgmaxPfPKfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7gArgmaxPfPKfmmPfPKfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7gArgmaxPfPKfmm, .-_Z7gArgmaxPfPKfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7gArgmaxPfPKfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7gArgmaxPfPKfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gArgmax.hip"
.globl _Z22__device_stub__gArgmaxPfPKfmm # -- Begin function _Z22__device_stub__gArgmaxPfPKfmm
.p2align 4, 0x90
.type _Z22__device_stub__gArgmaxPfPKfmm,@function
_Z22__device_stub__gArgmaxPfPKfmm: # @_Z22__device_stub__gArgmaxPfPKfmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7gArgmaxPfPKfmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__gArgmaxPfPKfmm, .Lfunc_end0-_Z22__device_stub__gArgmaxPfPKfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7gArgmaxPfPKfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7gArgmaxPfPKfmm,@object # @_Z7gArgmaxPfPKfmm
.section .rodata,"a",@progbits
.globl _Z7gArgmaxPfPKfmm
.p2align 3, 0x0
_Z7gArgmaxPfPKfmm:
.quad _Z22__device_stub__gArgmaxPfPKfmm
.size _Z7gArgmaxPfPKfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7gArgmaxPfPKfmm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__gArgmaxPfPKfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7gArgmaxPfPKfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* *
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
static const int WORK_SIZE = 10;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
/*
define CUDA_CHECK_RETURN(value)
{
cudaError_t _m_cudaStat = value;
if (_m_cudaStat != cudaSuccess) {
fprintf(stderr, "Error %s at line %d in file %s\n",
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);
exit(1);
} }
*/
__global__ void sort(int *a,int i,int n)
{
int tid = threadIdx.x;
int p;
int temp;
if(i%2==0)
{
p=tid*2;
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
else
{
p=tid*2+1;
if(p<n-1)
{
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
}
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(void)
{
int a[WORK_SIZE];
int i;
int *da;
cudaMalloc((void**) &da, sizeof(int) * WORK_SIZE);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d:",i);
scanf("%d",&a[i]);
}
cudaMemcpy(da, a, sizeof(int) * WORK_SIZE, cudaMemcpyHostToDevice);
for(i=0;i<WORK_SIZE;i++)
{
sort<<<1,WORK_SIZE/2>>>(da,i,WORK_SIZE);
}
cudaThreadSynchronize(); // Wait for the GPU launched work to complete
cudaGetLastError();
cudaMemcpy(a, da, sizeof(int) * WORK_SIZE, cudaMemcpyDeviceToHost);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d\t",a[i]);
}
printf("\n");
cudaFree((void*) da);
return 0;
} | code for sm_80
Function : _Z4sortPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0050*/ LOP3.LUT R0, R0, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0000007a12 */
/* 0x000fc800078ec0ff */
/*0060*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05070 */
/*0070*/ IMAD.SHL.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007824 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd000078e0203 */
/*0090*/ @P0 BRA 0x170 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ ULDC UR5, c[0x0][0x16c] ; /* 0x00005b0000057ab9 */
/* 0x000fe40000000800 */
/*00d0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fcc000fffe13f */
/*00e0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080602057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*0120*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0130*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0140*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101906 */
/*0150*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe2000c101906 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*0190*/ ISETP.GT.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f04270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101906 */
/*01c0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101906 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* *
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
static const int WORK_SIZE = 10;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
/*
define CUDA_CHECK_RETURN(value)
{
cudaError_t _m_cudaStat = value;
if (_m_cudaStat != cudaSuccess) {
fprintf(stderr, "Error %s at line %d in file %s\n",
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);
exit(1);
} }
*/
__global__ void sort(int *a,int i,int n)
{
int tid = threadIdx.x;
int p;
int temp;
if(i%2==0)
{
p=tid*2;
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
else
{
p=tid*2+1;
if(p<n-1)
{
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
}
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(void)
{
int a[WORK_SIZE];
int i;
int *da;
cudaMalloc((void**) &da, sizeof(int) * WORK_SIZE);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d:",i);
scanf("%d",&a[i]);
}
cudaMemcpy(da, a, sizeof(int) * WORK_SIZE, cudaMemcpyHostToDevice);
for(i=0;i<WORK_SIZE;i++)
{
sort<<<1,WORK_SIZE/2>>>(da,i,WORK_SIZE);
}
cudaThreadSynchronize(); // Wait for the GPU launched work to complete
cudaGetLastError();
cudaMemcpy(a, da, sizeof(int) * WORK_SIZE, cudaMemcpyDeviceToHost);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d\t",a[i]);
}
printf("\n");
cudaFree((void*) da);
return 0;
} | .file "tmpxft_00124e75_00000000-6_BubbleSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4sortPiiiPiii
.type _Z25__device_stub__Z4sortPiiiPiii, @function
_Z25__device_stub__Z4sortPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z4sortPiiiPiii, .-_Z25__device_stub__Z4sortPiiiPiii
.globl _Z4sortPiii
.type _Z4sortPiii, @function
_Z4sortPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4sortPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4sortPiii, .-_Z4sortPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d:"
.LC1:
.string "%d"
.LC2:
.string "%d\t"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rbx
movq %rbx, %r12
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r13
.L12:
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
cmpl $10, %ebp
jne .L12
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebp
jmp .L14
.L13:
addl $1, %ebp
cmpl $10, %ebp
je .L21
.L14:
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $10, %edx
movl %ebp, %esi
movq (%rsp), %rdi
call _Z25__device_stub__Z4sortPiiiPiii
jmp .L13
.L21:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq 40(%rbx), %r12
leaq .LC2(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4sortPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* *
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
static const int WORK_SIZE = 10;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
/*
define CUDA_CHECK_RETURN(value)
{
cudaError_t _m_cudaStat = value;
if (_m_cudaStat != cudaSuccess) {
fprintf(stderr, "Error %s at line %d in file %s\n",
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);
exit(1);
} }
*/
__global__ void sort(int *a,int i,int n)
{
int tid = threadIdx.x;
int p;
int temp;
if(i%2==0)
{
p=tid*2;
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
else
{
p=tid*2+1;
if(p<n-1)
{
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
}
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(void)
{
int a[WORK_SIZE];
int i;
int *da;
cudaMalloc((void**) &da, sizeof(int) * WORK_SIZE);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d:",i);
scanf("%d",&a[i]);
}
cudaMemcpy(da, a, sizeof(int) * WORK_SIZE, cudaMemcpyHostToDevice);
for(i=0;i<WORK_SIZE;i++)
{
sort<<<1,WORK_SIZE/2>>>(da,i,WORK_SIZE);
}
cudaThreadSynchronize(); // Wait for the GPU launched work to complete
cudaGetLastError();
cudaMemcpy(a, da, sizeof(int) * WORK_SIZE, cudaMemcpyDeviceToHost);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d\t",a[i]);
}
printf("\n");
cudaFree((void*) da);
return 0;
} | /* *
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
static const int WORK_SIZE = 10;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
/*
define CUDA_CHECK_RETURN(value)
{
cudaError_t _m_cudaStat = value;
if (_m_cudaStat != cudaSuccess) {
fprintf(stderr, "Error %s at line %d in file %s\n",
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);
exit(1);
} }
*/
__global__ void sort(int *a,int i,int n)
{
int tid = threadIdx.x;
int p;
int temp;
if(i%2==0)
{
p=tid*2;
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
else
{
p=tid*2+1;
if(p<n-1)
{
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
}
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(void)
{
int a[WORK_SIZE];
int i;
int *da;
hipMalloc((void**) &da, sizeof(int) * WORK_SIZE);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d:",i);
scanf("%d",&a[i]);
}
hipMemcpy(da, a, sizeof(int) * WORK_SIZE, hipMemcpyHostToDevice);
for(i=0;i<WORK_SIZE;i++)
{
sort<<<1,WORK_SIZE/2>>>(da,i,WORK_SIZE);
}
hipDeviceSynchronize(); // Wait for the GPU launched work to complete
hipGetLastError();
hipMemcpy(a, da, sizeof(int) * WORK_SIZE, hipMemcpyDeviceToHost);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d\t",a[i]);
}
printf("\n");
hipFree((void*) da);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* *
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
static const int WORK_SIZE = 10;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
/*
define CUDA_CHECK_RETURN(value)
{
cudaError_t _m_cudaStat = value;
if (_m_cudaStat != cudaSuccess) {
fprintf(stderr, "Error %s at line %d in file %s\n",
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);
exit(1);
} }
*/
__global__ void sort(int *a,int i,int n)
{
int tid = threadIdx.x;
int p;
int temp;
if(i%2==0)
{
p=tid*2;
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
else
{
p=tid*2+1;
if(p<n-1)
{
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
}
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(void)
{
int a[WORK_SIZE];
int i;
int *da;
hipMalloc((void**) &da, sizeof(int) * WORK_SIZE);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d:",i);
scanf("%d",&a[i]);
}
hipMemcpy(da, a, sizeof(int) * WORK_SIZE, hipMemcpyHostToDevice);
for(i=0;i<WORK_SIZE;i++)
{
sort<<<1,WORK_SIZE/2>>>(da,i,WORK_SIZE);
}
hipDeviceSynchronize(); // Wait for the GPU launched work to complete
hipGetLastError();
hipMemcpy(a, da, sizeof(int) * WORK_SIZE, hipMemcpyDeviceToHost);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d\t",a[i]);
}
printf("\n");
hipFree((void*) da);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPiii
.globl _Z4sortPiii
.p2align 8
.type _Z4sortPiii,@function
_Z4sortPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s4, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_mov_b32 s4, -1
s_cbranch_vccz .LBB0_5
s_load_b32 s0, s[0:1], 0xc
v_or_b32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v4, 2, v1
v_lshlrev_b32_e32 v3, 2, v0
s_clause 0x1
global_load_b32 v1, v4, s[2:3]
global_load_b32 v2, v3, s[2:3] offset:8
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
v_add_co_u32 v4, s1, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, s3, 0, s1
v_add_co_u32 v6, s1, s2, v3
v_add_co_ci_u32_e64 v7, null, s3, 0, s1
s_clause 0x1
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v1, off offset:8
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s4, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_8
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v2, 4, v3
s_clause 0x1
global_load_b32 v0, v3, s[2:3]
global_load_b32 v1, v2, s[2:3]
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v0, v1
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s3, 0, s0
v_add_co_u32 v5, s0, s2, v2
v_add_co_ci_u32_e64 v6, null, s3, 0, s0
s_clause 0x1
global_store_b32 v[3:4], v1, off
global_store_b32 v[5:6], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPiii, .Lfunc_end0-_Z4sortPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPiii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4sortPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* *
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
static const int WORK_SIZE = 10;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
/*
define CUDA_CHECK_RETURN(value)
{
cudaError_t _m_cudaStat = value;
if (_m_cudaStat != cudaSuccess) {
fprintf(stderr, "Error %s at line %d in file %s\n",
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);
exit(1);
} }
*/
__global__ void sort(int *a,int i,int n)
{
int tid = threadIdx.x;
int p;
int temp;
if(i%2==0)
{
p=tid*2;
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
else
{
p=tid*2+1;
if(p<n-1)
{
if(a[p]>a[p+1])
{
temp = a[p];
a[p] = a[p+1];
a[p+1] =temp;
}
}
}
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(void)
{
int a[WORK_SIZE];
int i;
int *da;
hipMalloc((void**) &da, sizeof(int) * WORK_SIZE);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d:",i);
scanf("%d",&a[i]);
}
hipMemcpy(da, a, sizeof(int) * WORK_SIZE, hipMemcpyHostToDevice);
for(i=0;i<WORK_SIZE;i++)
{
sort<<<1,WORK_SIZE/2>>>(da,i,WORK_SIZE);
}
hipDeviceSynchronize(); // Wait for the GPU launched work to complete
hipGetLastError();
hipMemcpy(a, da, sizeof(int) * WORK_SIZE, hipMemcpyDeviceToHost);
for(i=0;i<WORK_SIZE;i++)
{
printf("%d\t",a[i]);
}
printf("\n");
hipFree((void*) da);
return 0;
} | .text
.file "BubbleSort.hip"
.globl _Z19__device_stub__sortPiii # -- Begin function _Z19__device_stub__sortPiii
.p2align 4, 0x90
.type _Z19__device_stub__sortPiii,@function
_Z19__device_stub__sortPiii: # @_Z19__device_stub__sortPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4sortPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__sortPiii, .Lfunc_end0-_Z19__device_stub__sortPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
addq $4, %rbx
cmpq $10, %r14
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 4(%rbx), %r14
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 80(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incl %r12d
cmpl $10, %r12d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r12d, 20(%rsp)
movl $10, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPiii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceSynchronize
callq hipGetLastError
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sortPiii,@object # @_Z4sortPiii
.section .rodata,"a",@progbits
.globl _Z4sortPiii
.p2align 3, 0x0
_Z4sortPiii:
.quad _Z19__device_stub__sortPiii
.size _Z4sortPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d:"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPiii"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sortPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4sortPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0050*/ LOP3.LUT R0, R0, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0000007a12 */
/* 0x000fc800078ec0ff */
/*0060*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05070 */
/*0070*/ IMAD.SHL.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007824 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd000078e0203 */
/*0090*/ @P0 BRA 0x170 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ ULDC UR5, c[0x0][0x16c] ; /* 0x00005b0000057ab9 */
/* 0x000fe40000000800 */
/*00d0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fcc000fffe13f */
/*00e0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080602057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*0120*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0130*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0140*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101906 */
/*0150*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe2000c101906 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*0190*/ ISETP.GT.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f04270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101906 */
/*01c0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101906 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPiii
.globl _Z4sortPiii
.p2align 8
.type _Z4sortPiii,@function
_Z4sortPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s4, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_mov_b32 s4, -1
s_cbranch_vccz .LBB0_5
s_load_b32 s0, s[0:1], 0xc
v_or_b32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v4, 2, v1
v_lshlrev_b32_e32 v3, 2, v0
s_clause 0x1
global_load_b32 v1, v4, s[2:3]
global_load_b32 v2, v3, s[2:3] offset:8
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
v_add_co_u32 v4, s1, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, s3, 0, s1
v_add_co_u32 v6, s1, s2, v3
v_add_co_ci_u32_e64 v7, null, s3, 0, s1
s_clause 0x1
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v1, off offset:8
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s4, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_8
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v2, 4, v3
s_clause 0x1
global_load_b32 v0, v3, s[2:3]
global_load_b32 v1, v2, s[2:3]
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v0, v1
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s3, 0, s0
v_add_co_u32 v5, s0, s2, v2
v_add_co_ci_u32_e64 v6, null, s3, 0, s0
s_clause 0x1
global_store_b32 v[3:4], v1, off
global_store_b32 v[5:6], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPiii, .Lfunc_end0-_Z4sortPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPiii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4sortPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00124e75_00000000-6_BubbleSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4sortPiiiPiii
.type _Z25__device_stub__Z4sortPiiiPiii, @function
_Z25__device_stub__Z4sortPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z4sortPiiiPiii, .-_Z25__device_stub__Z4sortPiiiPiii
.globl _Z4sortPiii
.type _Z4sortPiii, @function
_Z4sortPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4sortPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4sortPiii, .-_Z4sortPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d:"
.LC1:
.string "%d"
.LC2:
.string "%d\t"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rbx
movq %rbx, %r12
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r13
.L12:
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
cmpl $10, %ebp
jne .L12
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebp
jmp .L14
.L13:
addl $1, %ebp
cmpl $10, %ebp
je .L21
.L14:
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $10, %edx
movl %ebp, %esi
movq (%rsp), %rdi
call _Z25__device_stub__Z4sortPiiiPiii
jmp .L13
.L21:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq 40(%rbx), %r12
leaq .LC2(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4sortPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BubbleSort.hip"
.globl _Z19__device_stub__sortPiii # -- Begin function _Z19__device_stub__sortPiii
.p2align 4, 0x90
.type _Z19__device_stub__sortPiii,@function
_Z19__device_stub__sortPiii: # @_Z19__device_stub__sortPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4sortPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__sortPiii, .Lfunc_end0-_Z19__device_stub__sortPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
addq $4, %rbx
cmpq $10, %r14
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 4(%rbx), %r14
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 80(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incl %r12d
cmpl $10, %r12d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r12d, 20(%rsp)
movl $10, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPiii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceSynchronize
callq hipGetLastError
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sortPiii,@object # @_Z4sortPiii
.section .rodata,"a",@progbits
.globl _Z4sortPiii
.p2align 3, 0x0
_Z4sortPiii:
.quad _Z19__device_stub__sortPiii
.size _Z4sortPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d:"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPiii"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sortPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <time.h>
#include <sstream>
#include <iostream>
#ifndef __CUDACC_RTC__
#define __CUDACC_RTC__
#endif
#include <device_functions.h>
using namespace std;
#define imin(a, b) (a<b? a:b)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__ void dot(float *a, float *b, float *c) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0.0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0) {
if (cacheIndex < i) {
cache[cacheIndex] = cache[cacheIndex] + cache[cacheIndex + i];
}
__syncthreads();
i = i / 2;
}
if (cacheIndex == 0) {
c[blockIdx.x] = cache[0];
}
}
int main(void) {
float *a, *b, *c, result, cpu_result;
float *dev_a, *dev_b, *dev_c;
a = new float[N];
b = new float[N];
c = new float[N];
result = 0;
cpu_result = 0;
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2;
c[i] = 0;
}
cout << "start" << endl;
for (int i = 0; i < N; i++) {
cpu_result += a[i] * b[i];
}
cout << cpu_result << endl;
cudaMalloc((void**)&dev_a, sizeof(float)*N);
cudaMalloc((void**)&dev_b, sizeof(float)*N);
cudaMalloc((void**)&dev_c, sizeof(float)*blocksPerGrid);
cudaMemcpy(dev_a, a, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemset(dev_c, 0, sizeof(float)*blocksPerGrid);
dot <<< blocksPerGrid, threadsPerBlock >>> (dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(float)*blocksPerGrid, cudaMemcpyDeviceToHost);
for (int j = 0; j < blocksPerGrid; j++)
{
result += c[j];
}
std::cout << result << std::endl;
system("pause");
cudaDeviceReset();
delete[] a;
delete[] b;
delete[] c;
return 0;
} | code for sm_80
Function : _Z3dotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R4, R3.reuse, R0, 0x2 ; /* 0x0000000003049211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R2, [R8.X4] ; /* 0x0000000008029984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R4] ; /* 0x0000000004059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R2 ; /* 0x0000000208009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <time.h>
#include <sstream>
#include <iostream>
#ifndef __CUDACC_RTC__
#define __CUDACC_RTC__
#endif
#include <device_functions.h>
using namespace std;
#define imin(a, b) (a<b? a:b)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__ void dot(float *a, float *b, float *c) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0.0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0) {
if (cacheIndex < i) {
cache[cacheIndex] = cache[cacheIndex] + cache[cacheIndex + i];
}
__syncthreads();
i = i / 2;
}
if (cacheIndex == 0) {
c[blockIdx.x] = cache[0];
}
}
int main(void) {
float *a, *b, *c, result, cpu_result;
float *dev_a, *dev_b, *dev_c;
a = new float[N];
b = new float[N];
c = new float[N];
result = 0;
cpu_result = 0;
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2;
c[i] = 0;
}
cout << "start" << endl;
for (int i = 0; i < N; i++) {
cpu_result += a[i] * b[i];
}
cout << cpu_result << endl;
cudaMalloc((void**)&dev_a, sizeof(float)*N);
cudaMalloc((void**)&dev_b, sizeof(float)*N);
cudaMalloc((void**)&dev_c, sizeof(float)*blocksPerGrid);
cudaMemcpy(dev_a, a, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemset(dev_c, 0, sizeof(float)*blocksPerGrid);
dot <<< blocksPerGrid, threadsPerBlock >>> (dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(float)*blocksPerGrid, cudaMemcpyDeviceToHost);
for (int j = 0; j < blocksPerGrid; j++)
{
result += c[j];
}
std::cout << result << std::endl;
system("pause");
cudaDeviceReset();
delete[] a;
delete[] b;
delete[] c;
return 0;
} | .file "tmpxft_00144bed_00000000-6_dotProduct.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3730:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3730:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB3752:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3752:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB3753:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3753:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "start"
.LC2:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB3727:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $135168, %edi
call _Znam@PLT
movq %rax, %rbp
movl $135168, %edi
call _Znam@PLT
movq %rax, %rbx
movl $135168, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addq $1, %rax
cmpq $33792, %rax
jne .L12
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
pxor %xmm1, %xmm1
.L13:
movss 0(%rbp,%rax), %xmm0
mulss (%rbx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $135168, %rax
jne .L13
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $135168, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $135168, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rax
leaq 128(%r12), %rdx
pxor %xmm0, %xmm0
.L15:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L15
cvtss2sd %xmm0, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rdi
call system@PLT
call cudaDeviceReset@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3755:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3755:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <time.h>
#include <sstream>
#include <iostream>
#ifndef __CUDACC_RTC__
#define __CUDACC_RTC__
#endif
#include <device_functions.h>
using namespace std;
#define imin(a, b) (a<b? a:b)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__ void dot(float *a, float *b, float *c) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0.0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0) {
if (cacheIndex < i) {
cache[cacheIndex] = cache[cacheIndex] + cache[cacheIndex + i];
}
__syncthreads();
i = i / 2;
}
if (cacheIndex == 0) {
c[blockIdx.x] = cache[0];
}
}
int main(void) {
float *a, *b, *c, result, cpu_result;
float *dev_a, *dev_b, *dev_c;
a = new float[N];
b = new float[N];
c = new float[N];
result = 0;
cpu_result = 0;
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2;
c[i] = 0;
}
cout << "start" << endl;
for (int i = 0; i < N; i++) {
cpu_result += a[i] * b[i];
}
cout << cpu_result << endl;
cudaMalloc((void**)&dev_a, sizeof(float)*N);
cudaMalloc((void**)&dev_b, sizeof(float)*N);
cudaMalloc((void**)&dev_c, sizeof(float)*blocksPerGrid);
cudaMemcpy(dev_a, a, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemset(dev_c, 0, sizeof(float)*blocksPerGrid);
dot <<< blocksPerGrid, threadsPerBlock >>> (dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(float)*blocksPerGrid, cudaMemcpyDeviceToHost);
for (int j = 0; j < blocksPerGrid; j++)
{
result += c[j];
}
std::cout << result << std::endl;
system("pause");
cudaDeviceReset();
delete[] a;
delete[] b;
delete[] c;
return 0;
} | #include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <time.h>
#include <sstream>
#include <iostream>
#ifndef __CUDACC_RTC__
#define __CUDACC_RTC__
#endif
#include <hip/device_functions.h>
using namespace std;
#define imin(a, b) (a<b? a:b)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__ void dot(float *a, float *b, float *c) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0.0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0) {
if (cacheIndex < i) {
cache[cacheIndex] = cache[cacheIndex] + cache[cacheIndex + i];
}
__syncthreads();
i = i / 2;
}
if (cacheIndex == 0) {
c[blockIdx.x] = cache[0];
}
}
int main(void) {
float *a, *b, *c, result, cpu_result;
float *dev_a, *dev_b, *dev_c;
a = new float[N];
b = new float[N];
c = new float[N];
result = 0;
cpu_result = 0;
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2;
c[i] = 0;
}
cout << "start" << endl;
for (int i = 0; i < N; i++) {
cpu_result += a[i] * b[i];
}
cout << cpu_result << endl;
hipMalloc((void**)&dev_a, sizeof(float)*N);
hipMalloc((void**)&dev_b, sizeof(float)*N);
hipMalloc((void**)&dev_c, sizeof(float)*blocksPerGrid);
hipMemcpy(dev_a, a, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemset(dev_c, 0, sizeof(float)*blocksPerGrid);
dot <<< blocksPerGrid, threadsPerBlock >>> (dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(float)*blocksPerGrid, hipMemcpyDeviceToHost);
for (int j = 0; j < blocksPerGrid; j++)
{
result += c[j];
}
std::cout << result << std::endl;
system("pause");
hipDeviceReset();
delete[] a;
delete[] b;
delete[] c;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <time.h>
#include <sstream>
#include <iostream>
#ifndef __CUDACC_RTC__
#define __CUDACC_RTC__
#endif
#include <hip/device_functions.h>
using namespace std;
#define imin(a, b) (a<b? a:b)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__ void dot(float *a, float *b, float *c) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0.0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0) {
if (cacheIndex < i) {
cache[cacheIndex] = cache[cacheIndex] + cache[cacheIndex + i];
}
__syncthreads();
i = i / 2;
}
if (cacheIndex == 0) {
c[blockIdx.x] = cache[0];
}
}
int main(void) {
float *a, *b, *c, result, cpu_result;
float *dev_a, *dev_b, *dev_c;
a = new float[N];
b = new float[N];
c = new float[N];
result = 0;
cpu_result = 0;
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2;
c[i] = 0;
}
cout << "start" << endl;
for (int i = 0; i < N; i++) {
cpu_result += a[i] * b[i];
}
cout << cpu_result << endl;
hipMalloc((void**)&dev_a, sizeof(float)*N);
hipMalloc((void**)&dev_b, sizeof(float)*N);
hipMalloc((void**)&dev_c, sizeof(float)*blocksPerGrid);
hipMemcpy(dev_a, a, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemset(dev_c, 0, sizeof(float)*blocksPerGrid);
dot <<< blocksPerGrid, threadsPerBlock >>> (dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(float)*blocksPerGrid, hipMemcpyDeviceToHost);
for (int j = 0; j < blocksPerGrid; j++)
{
result += c[j];
}
std::cout << result << std::endl;
system("pause");
hipDeviceReset();
delete[] a;
delete[] b;
delete[] c;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <time.h>
#include <sstream>
#include <iostream>
#ifndef __CUDACC_RTC__
#define __CUDACC_RTC__
#endif
#include <hip/device_functions.h>
using namespace std;
#define imin(a, b) (a<b? a:b)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__ void dot(float *a, float *b, float *c) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0.0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0) {
if (cacheIndex < i) {
cache[cacheIndex] = cache[cacheIndex] + cache[cacheIndex + i];
}
__syncthreads();
i = i / 2;
}
if (cacheIndex == 0) {
c[blockIdx.x] = cache[0];
}
}
int main(void) {
float *a, *b, *c, result, cpu_result;
float *dev_a, *dev_b, *dev_c;
a = new float[N];
b = new float[N];
c = new float[N];
result = 0;
cpu_result = 0;
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2;
c[i] = 0;
}
cout << "start" << endl;
for (int i = 0; i < N; i++) {
cpu_result += a[i] * b[i];
}
cout << cpu_result << endl;
hipMalloc((void**)&dev_a, sizeof(float)*N);
hipMalloc((void**)&dev_b, sizeof(float)*N);
hipMalloc((void**)&dev_c, sizeof(float)*blocksPerGrid);
hipMemcpy(dev_a, a, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemset(dev_c, 0, sizeof(float)*blocksPerGrid);
dot <<< blocksPerGrid, threadsPerBlock >>> (dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(float)*blocksPerGrid, hipMemcpyDeviceToHost);
for (int j = 0; j < blocksPerGrid; j++)
{
result += c[j];
}
std::cout << result << std::endl;
system("pause");
hipDeviceReset();
delete[] a;
delete[] b;
delete[] c;
return 0;
} | .text
.file "dotProduct.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $135168, %edi # imm = 0x21000
callq _Znam
movq %rax, %rbx
movl $135168, %edi # imm = 0x21000
callq _Znam
movq %rax, %r14
movl $135168, %edi # imm = 0x21000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
movl $135168, %edx # imm = 0x21000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
addl $2, %r12d
cmpq $33792, %rax # imm = 0x8400
jne .LBB1_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_21
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_5
# %bb.4:
movzbl 67(%r12), %eax
jmp .LBB1_6
.LBB1_5:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $33792, %rax # imm = 0x8400
jne .LBB1_7
# %bb.8:
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%r12)
je .LBB1_11
# %bb.10:
movzbl 67(%r12), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $32, %rax
jne .LBB1_15
# %bb.16:
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r12)
je .LBB1_19
# %bb.18:
movzbl 67(%r12), %ecx
jmp .LBB1_20
.LBB1_19:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
callq system
callq hipDeviceReset
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "start"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "pause"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3dotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R4, R3.reuse, R0, 0x2 ; /* 0x0000000003049211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R2, [R8.X4] ; /* 0x0000000008029984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R4] ; /* 0x0000000004059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R2 ; /* 0x0000000208009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144bed_00000000-6_dotProduct.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3730:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3730:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB3752:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3752:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB3753:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3753:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "start"
.LC2:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB3727:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $135168, %edi
call _Znam@PLT
movq %rax, %rbp
movl $135168, %edi
call _Znam@PLT
movq %rax, %rbx
movl $135168, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addq $1, %rax
cmpq $33792, %rax
jne .L12
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
pxor %xmm1, %xmm1
.L13:
movss 0(%rbp,%rax), %xmm0
mulss (%rbx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $135168, %rax
jne .L13
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $135168, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $135168, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rax
leaq 128(%r12), %rdx
pxor %xmm0, %xmm0
.L15:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L15
cvtss2sd %xmm0, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rdi
call system@PLT
call cudaDeviceReset@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3755:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3755:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dotProduct.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $135168, %edi # imm = 0x21000
callq _Znam
movq %rax, %rbx
movl $135168, %edi # imm = 0x21000
callq _Znam
movq %rax, %r14
movl $135168, %edi # imm = 0x21000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
movl $135168, %edx # imm = 0x21000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
addl $2, %r12d
cmpq $33792, %rax # imm = 0x8400
jne .LBB1_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_21
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_5
# %bb.4:
movzbl 67(%r12), %eax
jmp .LBB1_6
.LBB1_5:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $33792, %rax # imm = 0x8400
jne .LBB1_7
# %bb.8:
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%r12)
je .LBB1_11
# %bb.10:
movzbl 67(%r12), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $32, %rax
jne .LBB1_15
# %bb.16:
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r12)
je .LBB1_19
# %bb.18:
movzbl 67(%r12), %ecx
jmp .LBB1_20
.LBB1_19:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
callq system
callq hipDeviceReset
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "start"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "pause"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <stdio.h>
const int N = 16;
const int blocksize = 16;
__global__
void simple(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
int main()
{
//used to get data
float *c = new float[N];
float *to_square = new float[N];
to_square[0]=1;
//fill c with numbers
for (int i=1; i < N; i++){
to_square[i]=to_square[i-1]*2;
}
//pointer to cuda data
float *cd;
const int size = N*sizeof(float);
//allocate data on gpu
cudaMalloc( (void**)&cd, size );
dim3 dimBlock( blocksize, 1 );
dim3 dimGrid( 1, 1 );
//upload data to gpu
cudaMemcpy( cd, to_square, size, cudaMemcpyHostToDevice );
//start computation
simple<<<dimGrid, dimBlock>>>(cd);
//sync
cudaThreadSynchronize();
//download data
cudaMemcpy( c, cd, size, cudaMemcpyDeviceToHost );
//free data on gpu
cudaFree( cd );
//display data
printf("\n");
for (int i = 0; i < N; i++)
printf("gpu:%f cpu: %f \n", c[i],sqrt(to_square[i]));
printf("\n");
delete[] c;
printf("done\n");
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z6simplePf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ BSSY B0, 0x140 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0070*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x004fe20007ffe0ff */
/*0080*/ MUFU.RSQ R5, R0 ; /* 0x0000000000057308 */
/* 0x0000660000001400 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*00a0*/ @!P0 BRA 0xf0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, 0xd0 ; /* 0x000000d000097802 */
/* 0x003fe40000000f00 */
/*00c0*/ CALL.REL.NOINC 0x160 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*00d0*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*00e0*/ BRA 0x130 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*00f0*/ FMUL.FTZ R7, R0, R5 ; /* 0x0000000500077220 */
/* 0x003fe40000410000 */
/*0100*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0110*/ FFMA R0, -R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc80000000100 */
/*0120*/ FFMA R5, R0, R5, R7 ; /* 0x0000000500057223 */
/* 0x000fe40000000007 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0170*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0180*/ @!P0 BRA 0x290 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*01a0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*01b0*/ @!P0 BRA 0x290 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*01d0*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*01e0*/ @P0 BRA 0x290 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*01f0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*0200*/ @P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000050823 */
/* 0x000fc800000000ff */
/*0210*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0220*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0230*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*0240*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0250*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*0260*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0270*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0280*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0290*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*02a0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fc80000000f00 */
/*02c0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffd3004007950 */
/* 0x000fea0003c3ffff */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <stdio.h>
const int N = 16;
const int blocksize = 16;
__global__
void simple(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
int main()
{
//used to get data
float *c = new float[N];
float *to_square = new float[N];
to_square[0]=1;
//fill c with numbers
for (int i=1; i < N; i++){
to_square[i]=to_square[i-1]*2;
}
//pointer to cuda data
float *cd;
const int size = N*sizeof(float);
//allocate data on gpu
cudaMalloc( (void**)&cd, size );
dim3 dimBlock( blocksize, 1 );
dim3 dimGrid( 1, 1 );
//upload data to gpu
cudaMemcpy( cd, to_square, size, cudaMemcpyHostToDevice );
//start computation
simple<<<dimGrid, dimBlock>>>(cd);
//sync
cudaThreadSynchronize();
//download data
cudaMemcpy( c, cd, size, cudaMemcpyDeviceToHost );
//free data on gpu
cudaFree( cd );
//display data
printf("\n");
for (int i = 0; i < N; i++)
printf("gpu:%f cpu: %f \n", c[i],sqrt(to_square[i]));
printf("\n");
delete[] c;
printf("done\n");
return EXIT_SUCCESS;
} | .file "tmpxft_000f7148_00000000-6_simple_mod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6simplePfPf
.type _Z25__device_stub__Z6simplePfPf, @function
_Z25__device_stub__Z6simplePfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6simplePf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6simplePfPf, .-_Z25__device_stub__Z6simplePfPf
.globl _Z6simplePf
.type _Z6simplePf, @function
_Z6simplePf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6simplePfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6simplePf, .-_Z6simplePf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n"
.LC3:
.string "gpu:%f cpu: %f \n"
.LC4:
.string "done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call _Znam@PLT
movq %rax, %r12
movl $64, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0x3f800000, (%rax)
leaq 60(%rax), %rdx
.L12:
movss (%rax), %xmm0
addss %xmm0, %xmm0
movss %xmm0, 4(%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r13
.L17:
movss 0(%rbp,%rbx), %xmm1
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L22
sqrtss %xmm1, %xmm1
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx), %xmm0
cvtss2sd %xmm1, %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _ZdaPv@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6simplePfPf
jmp .L13
.L22:
movaps %xmm1, %xmm0
call sqrtf@PLT
movaps %xmm0, %xmm1
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6simplePf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6simplePf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <stdio.h>
const int N = 16;
const int blocksize = 16;
__global__
void simple(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
int main()
{
//used to get data
float *c = new float[N];
float *to_square = new float[N];
to_square[0]=1;
//fill c with numbers
for (int i=1; i < N; i++){
to_square[i]=to_square[i-1]*2;
}
//pointer to cuda data
float *cd;
const int size = N*sizeof(float);
//allocate data on gpu
cudaMalloc( (void**)&cd, size );
dim3 dimBlock( blocksize, 1 );
dim3 dimGrid( 1, 1 );
//upload data to gpu
cudaMemcpy( cd, to_square, size, cudaMemcpyHostToDevice );
//start computation
simple<<<dimGrid, dimBlock>>>(cd);
//sync
cudaThreadSynchronize();
//download data
cudaMemcpy( c, cd, size, cudaMemcpyDeviceToHost );
//free data on gpu
cudaFree( cd );
//display data
printf("\n");
for (int i = 0; i < N; i++)
printf("gpu:%f cpu: %f \n", c[i],sqrt(to_square[i]));
printf("\n");
delete[] c;
printf("done\n");
return EXIT_SUCCESS;
} | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <hip/hip_runtime.h>
#include <stdio.h>
const int N = 16;
const int blocksize = 16;
__global__
void simple(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
int main()
{
//used to get data
float *c = new float[N];
float *to_square = new float[N];
to_square[0]=1;
//fill c with numbers
for (int i=1; i < N; i++){
to_square[i]=to_square[i-1]*2;
}
//pointer to cuda data
float *cd;
const int size = N*sizeof(float);
//allocate data on gpu
hipMalloc( (void**)&cd, size );
dim3 dimBlock( blocksize, 1 );
dim3 dimGrid( 1, 1 );
//upload data to gpu
hipMemcpy( cd, to_square, size, hipMemcpyHostToDevice );
//start computation
simple<<<dimGrid, dimBlock>>>(cd);
//sync
hipDeviceSynchronize();
//download data
hipMemcpy( c, cd, size, hipMemcpyDeviceToHost );
//free data on gpu
hipFree( cd );
//display data
printf("\n");
for (int i = 0; i < N; i++)
printf("gpu:%f cpu: %f \n", c[i],sqrt(to_square[i]));
printf("\n");
delete[] c;
printf("done\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <hip/hip_runtime.h>
#include <stdio.h>
const int N = 16;
const int blocksize = 16;
__global__
void simple(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
int main()
{
//used to get data
float *c = new float[N];
float *to_square = new float[N];
to_square[0]=1;
//fill c with numbers
for (int i=1; i < N; i++){
to_square[i]=to_square[i-1]*2;
}
//pointer to cuda data
float *cd;
const int size = N*sizeof(float);
//allocate data on gpu
hipMalloc( (void**)&cd, size );
dim3 dimBlock( blocksize, 1 );
dim3 dimGrid( 1, 1 );
//upload data to gpu
hipMemcpy( cd, to_square, size, hipMemcpyHostToDevice );
//start computation
simple<<<dimGrid, dimBlock>>>(cd);
//sync
hipDeviceSynchronize();
//download data
hipMemcpy( c, cd, size, hipMemcpyDeviceToHost );
//free data on gpu
hipFree( cd );
//display data
printf("\n");
for (int i = 0; i < N; i++)
printf("gpu:%f cpu: %f \n", c[i],sqrt(to_square[i]));
printf("\n");
delete[] c;
printf("done\n");
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6simplePf
.globl _Z6simplePf
.p2align 8
.type _Z6simplePf,@function
_Z6simplePf:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6simplePf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6simplePf, .Lfunc_end0-_Z6simplePf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6simplePf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6simplePf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <hip/hip_runtime.h>
#include <stdio.h>
const int N = 16;
const int blocksize = 16;
__global__
void simple(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
int main()
{
//used to get data
float *c = new float[N];
float *to_square = new float[N];
to_square[0]=1;
//fill c with numbers
for (int i=1; i < N; i++){
to_square[i]=to_square[i-1]*2;
}
//pointer to cuda data
float *cd;
const int size = N*sizeof(float);
//allocate data on gpu
hipMalloc( (void**)&cd, size );
dim3 dimBlock( blocksize, 1 );
dim3 dimGrid( 1, 1 );
//upload data to gpu
hipMemcpy( cd, to_square, size, hipMemcpyHostToDevice );
//start computation
simple<<<dimGrid, dimBlock>>>(cd);
//sync
hipDeviceSynchronize();
//download data
hipMemcpy( c, cd, size, hipMemcpyDeviceToHost );
//free data on gpu
hipFree( cd );
//display data
printf("\n");
for (int i = 0; i < N; i++)
printf("gpu:%f cpu: %f \n", c[i],sqrt(to_square[i]));
printf("\n");
delete[] c;
printf("done\n");
return EXIT_SUCCESS;
} | .text
.file "simple_mod.hip"
.globl _Z21__device_stub__simplePf # -- Begin function _Z21__device_stub__simplePf
.p2align 4, 0x90
.type _Z21__device_stub__simplePf,@function
_Z21__device_stub__simplePf: # @_Z21__device_stub__simplePf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6simplePf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__simplePf, .Lfunc_end0-_Z21__device_stub__simplePf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq _Znam
movq %rax, %rbx
movl $64, %edi
callq _Znam
movq %rax, %r14
movl $1065353216, (%rax) # imm = 0x3F800000
movl $1, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addss %xmm0, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6simplePf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # %call.sqrt
# in Loop: Header=BB1_5 Depth=1
movss %xmm2, 12(%rsp) # 4-byte Spill
callq sqrt
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movapd %xmm0, %xmm1
.LBB1_8: # %.split
# in Loop: Header=BB1_5 Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %r15
cmpq $16, %r15
je .LBB1_9
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI1_1(%rip), %xmm0
jb .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
xorps %xmm1, %xmm1
sqrtsd %xmm0, %xmm1
jmp .LBB1_8
.LBB1_9:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq _ZdaPv
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6simplePf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6simplePf,@object # @_Z6simplePf
.section .rodata,"a",@progbits
.globl _Z6simplePf
.p2align 3, 0x0
_Z6simplePf:
.quad _Z21__device_stub__simplePf
.size _Z6simplePf, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "gpu:%f cpu: %f \n"
.size .L.str.1, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6simplePf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__simplePf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6simplePf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6simplePf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ BSSY B0, 0x140 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0070*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x004fe20007ffe0ff */
/*0080*/ MUFU.RSQ R5, R0 ; /* 0x0000000000057308 */
/* 0x0000660000001400 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*00a0*/ @!P0 BRA 0xf0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, 0xd0 ; /* 0x000000d000097802 */
/* 0x003fe40000000f00 */
/*00c0*/ CALL.REL.NOINC 0x160 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*00d0*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*00e0*/ BRA 0x130 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*00f0*/ FMUL.FTZ R7, R0, R5 ; /* 0x0000000500077220 */
/* 0x003fe40000410000 */
/*0100*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0110*/ FFMA R0, -R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc80000000100 */
/*0120*/ FFMA R5, R0, R5, R7 ; /* 0x0000000500057223 */
/* 0x000fe40000000007 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0170*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0180*/ @!P0 BRA 0x290 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*01a0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*01b0*/ @!P0 BRA 0x290 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*01d0*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*01e0*/ @P0 BRA 0x290 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*01f0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*0200*/ @P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000050823 */
/* 0x000fc800000000ff */
/*0210*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0220*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0230*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*0240*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0250*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*0260*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0270*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0280*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0290*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*02a0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fc80000000f00 */
/*02c0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffd3004007950 */
/* 0x000fea0003c3ffff */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6simplePf
.globl _Z6simplePf
.p2align 8
.type _Z6simplePf,@function
_Z6simplePf:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6simplePf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6simplePf, .Lfunc_end0-_Z6simplePf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6simplePf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6simplePf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f7148_00000000-6_simple_mod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6simplePfPf
.type _Z25__device_stub__Z6simplePfPf, @function
_Z25__device_stub__Z6simplePfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6simplePf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6simplePfPf, .-_Z25__device_stub__Z6simplePfPf
.globl _Z6simplePf
.type _Z6simplePf, @function
_Z6simplePf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6simplePfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6simplePf, .-_Z6simplePf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n"
.LC3:
.string "gpu:%f cpu: %f \n"
.LC4:
.string "done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call _Znam@PLT
movq %rax, %r12
movl $64, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0x3f800000, (%rax)
leaq 60(%rax), %rdx
.L12:
movss (%rax), %xmm0
addss %xmm0, %xmm0
movss %xmm0, 4(%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r13
.L17:
movss 0(%rbp,%rbx), %xmm1
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L22
sqrtss %xmm1, %xmm1
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx), %xmm0
cvtss2sd %xmm1, %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _ZdaPv@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6simplePfPf
jmp .L13
.L22:
movaps %xmm1, %xmm0
call sqrtf@PLT
movaps %xmm0, %xmm1
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6simplePf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6simplePf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_mod.hip"
.globl _Z21__device_stub__simplePf # -- Begin function _Z21__device_stub__simplePf
.p2align 4, 0x90
.type _Z21__device_stub__simplePf,@function
_Z21__device_stub__simplePf: # @_Z21__device_stub__simplePf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6simplePf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__simplePf, .Lfunc_end0-_Z21__device_stub__simplePf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq _Znam
movq %rax, %rbx
movl $64, %edi
callq _Znam
movq %rax, %r14
movl $1065353216, (%rax) # imm = 0x3F800000
movl $1, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addss %xmm0, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6simplePf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # %call.sqrt
# in Loop: Header=BB1_5 Depth=1
movss %xmm2, 12(%rsp) # 4-byte Spill
callq sqrt
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movapd %xmm0, %xmm1
.LBB1_8: # %.split
# in Loop: Header=BB1_5 Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %r15
cmpq $16, %r15
je .LBB1_9
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI1_1(%rip), %xmm0
jb .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
xorps %xmm1, %xmm1
sqrtsd %xmm0, %xmm1
jmp .LBB1_8
.LBB1_9:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq _ZdaPv
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6simplePf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6simplePf,@object # @_Z6simplePf
.section .rodata,"a",@progbits
.globl _Z6simplePf
.p2align 3, 0x0
_Z6simplePf:
.quad _Z21__device_stub__simplePf
.size _Z6simplePf, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "gpu:%f cpu: %f \n"
.size .L.str.1, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6simplePf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__simplePf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6simplePf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__global__ void naivePrefixSum(int *A, int *B, int size, int iteration) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size) {
if (index >= (1 << (iteration - 1)))
A[index] = B[(int) (index - (1 << (iteration - 1)))] + B[index];
else
A[index] = B[index];
}
} | code for sm_80
Function : _Z14naivePrefixSumPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0090*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00a0*/ USHF.L.U32 UR4, UR5, UR4, URZ ; /* 0x0000000405047299 */
/* 0x000fe4000800063f */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0207 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc6000bf06270 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fd400078e0207 */
/*00f0*/ @!P0 BRA 0x170 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R6, R0, -UR4, RZ ; /* 0x8000000400067c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0120*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*0130*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IADD3 R9, R2, R7, RZ ; /* 0x0000000702097210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101906 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0180*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__global__ void naivePrefixSum(int *A, int *B, int size, int iteration) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size) {
if (index >= (1 << (iteration - 1)))
A[index] = B[(int) (index - (1 << (iteration - 1)))] + B[index];
else
A[index] = B[index];
}
} | .file "tmpxft_001bd04f_00000000-6_naivePrefixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii
.type _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii, @function
_Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14naivePrefixSumPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii, .-_Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii
.globl _Z14naivePrefixSumPiS_ii
.type _Z14naivePrefixSumPiS_ii, @function
_Z14naivePrefixSumPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14naivePrefixSumPiS_ii, .-_Z14naivePrefixSumPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14naivePrefixSumPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14naivePrefixSumPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_b
.bss
.align 8
.type d_b, @object
.size d_b, 8
d_b:
.zero 8
.globl d_a
.align 8
.type d_a, @object
.size d_a, 8
d_a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__global__ void naivePrefixSum(int *A, int *B, int size, int iteration) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size) {
if (index >= (1 << (iteration - 1)))
A[index] = B[(int) (index - (1 << (iteration - 1)))] + B[index];
else
A[index] = B[index];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__global__ void naivePrefixSum(int *A, int *B, int size, int iteration) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size) {
if (index >= (1 << (iteration - 1)))
A[index] = B[(int) (index - (1 << (iteration - 1)))] + B[index];
else
A[index] = B[index];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__global__ void naivePrefixSum(int *A, int *B, int size, int iteration) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size) {
if (index >= (1 << (iteration - 1)))
A[index] = B[(int) (index - (1 << (iteration - 1)))] + B[index];
else
A[index] = B[index];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14naivePrefixSumPiS_ii
.globl _Z14naivePrefixSumPiS_ii
.p2align 8
.type _Z14naivePrefixSumPiS_ii,@function
_Z14naivePrefixSumPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s5, 1, s4
s_mov_b32 s4, exec_lo
v_cmpx_le_i32_e64 s5, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v3, s5, v1
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
.LBB0_3:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14naivePrefixSumPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14naivePrefixSumPiS_ii, .Lfunc_end0-_Z14naivePrefixSumPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14naivePrefixSumPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14naivePrefixSumPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__global__ void naivePrefixSum(int *A, int *B, int size, int iteration) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size) {
if (index >= (1 << (iteration - 1)))
A[index] = B[(int) (index - (1 << (iteration - 1)))] + B[index];
else
A[index] = B[index];
}
} | .text
.file "naivePrefixSum.hip"
.globl _Z29__device_stub__naivePrefixSumPiS_ii # -- Begin function _Z29__device_stub__naivePrefixSumPiS_ii
.p2align 4, 0x90
.type _Z29__device_stub__naivePrefixSumPiS_ii,@function
_Z29__device_stub__naivePrefixSumPiS_ii: # @_Z29__device_stub__naivePrefixSumPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14naivePrefixSumPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__naivePrefixSumPiS_ii, .Lfunc_end0-_Z29__device_stub__naivePrefixSumPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14naivePrefixSumPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_a,@object # @d_a
.bss
.globl d_a
.p2align 3, 0x0
d_a:
.quad 0
.size d_a, 8
.type d_b,@object # @d_b
.globl d_b
.p2align 3, 0x0
d_b:
.quad 0
.size d_b, 8
.type _Z14naivePrefixSumPiS_ii,@object # @_Z14naivePrefixSumPiS_ii
.section .rodata,"a",@progbits
.globl _Z14naivePrefixSumPiS_ii
.p2align 3, 0x0
_Z14naivePrefixSumPiS_ii:
.quad _Z29__device_stub__naivePrefixSumPiS_ii
.size _Z14naivePrefixSumPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14naivePrefixSumPiS_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__naivePrefixSumPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14naivePrefixSumPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14naivePrefixSumPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0090*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00a0*/ USHF.L.U32 UR4, UR5, UR4, URZ ; /* 0x0000000405047299 */
/* 0x000fe4000800063f */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0207 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc6000bf06270 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fd400078e0207 */
/*00f0*/ @!P0 BRA 0x170 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R6, R0, -UR4, RZ ; /* 0x8000000400067c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0120*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*0130*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IADD3 R9, R2, R7, RZ ; /* 0x0000000702097210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101906 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0180*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14naivePrefixSumPiS_ii
.globl _Z14naivePrefixSumPiS_ii
.p2align 8
.type _Z14naivePrefixSumPiS_ii,@function
_Z14naivePrefixSumPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s5, 1, s4
s_mov_b32 s4, exec_lo
v_cmpx_le_i32_e64 s5, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v3, s5, v1
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
.LBB0_3:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14naivePrefixSumPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14naivePrefixSumPiS_ii, .Lfunc_end0-_Z14naivePrefixSumPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14naivePrefixSumPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14naivePrefixSumPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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