system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void expon(float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
if (i < nhalf) {
env[i] = exp(env[i]/nhalf); // exponentiate
}
} | .text
.file "expon.hip"
.globl _Z20__device_stub__exponPfi # -- Begin function _Z20__device_stub__exponPfi
.p2align 4, 0x90
.type _Z20__device_stub__exponPfi,@function
_Z20__device_stub__exponPfi: # @_Z20__device_stub__exponPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5exponPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__exponPfi, .Lfunc_end0-_Z20__device_stub__exponPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5exponPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5exponPfi,@object # @_Z5exponPfi
.section .rodata,"a",@progbits
.globl _Z5exponPfi
.p2align 3, 0x0
_Z5exponPfi:
.quad _Z20__device_stub__exponPfi
.size _Z5exponPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5exponPfi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__exponPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5exponPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5exponPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ I2F R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000201400 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*00c0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x001e240000001000 */
/*00d0*/ FFMA R0, -R4, R7, 1 ; /* 0x3f80000004007423 */
/* 0x001fc80000000107 */
/*00e0*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fe40000000007 */
/*00f0*/ FCHK P0, R5, R4 ; /* 0x0000000405007302 */
/* 0x004e240000000000 */
/*0100*/ FFMA R7, R5, R0, RZ ; /* 0x0000000005077223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R6, -R4, R7, R5 ; /* 0x0000000704067223 */
/* 0x000fc80000000105 */
/*0120*/ FFMA R0, R0, R6, R7 ; /* 0x0000000600007223 */
/* 0x000fe20000000007 */
/*0130*/ @!P0 BRA 0x170 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0140*/ MOV R0, 0x160 ; /* 0x0000016000007802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x240 ; /* 0x000000e000007944 */
/* 0x000fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0006 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff077424 */
/* 0x000fe400078e00ff */
/*01a0*/ FFMA.SAT R4, R0, R5, 0.5 ; /* 0x3f00000000047423 */
/* 0x000fc80000002005 */
/*01b0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*01c0*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */
/* 0x040fe40000000000 */
/*01d0*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */
/* 0x000fe400078e00ff */
/*01e0*/ FFMA R5, R0, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b00057823 */
/* 0x000fc80000000805 */
/*01f0*/ FFMA R5, R0, 1.925963033500011079e-08, R5 ; /* 0x32a5706000057823 */
/* 0x000fcc0000000005 */
/*0200*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000000800 */
/*0210*/ FMUL R7, R4, R5 ; /* 0x0000000504077220 */
/* 0x001fca0000400000 */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ SHF.R.U32.HI R7, RZ, 0x17, R4.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011604 */
/*0250*/ BSSY B1, 0x8a0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0260*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0280*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*02a0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*02b0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*02e0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02f0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0300*/ @!P0 BRA 0x480 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*0320*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0330*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0340*/ @P0 BRA 0x880 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0360*/ @!P0 BRA 0x860 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*0380*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0390*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*03a0*/ @!P1 BRA !P2, 0x860 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03b0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*03c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03d0*/ @P1 BRA 0x840 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03e0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*03f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0400*/ @P0 BRA 0x810 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0420*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0430*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0440*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*0460*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*0470*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*0490*/ BSSY B2, 0x800 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04a0*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*04c0*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*04d0*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*04e0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*0500*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0510*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*0520*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0530*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0540*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*0550*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0560*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*0570*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0580*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0590*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*05a0*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*05b0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05d0*/ @!P0 BRA 0x7e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05f0*/ @P0 BRA 0x7b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0610*/ @P0 BRA 0x7f0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0630*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0640*/ @!P0 BRA 0x7f0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0650*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0660*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0670*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0680*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0690*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*06a0*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*06b0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06d0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*06f0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0700*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0710*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0720*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0740*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0750*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0760*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0770*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0790*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x7f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*07c0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x7f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x890 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0820*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0830*/ BRA 0x890 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0850*/ BRA 0x890 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0860*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0870*/ BRA 0x890 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0880*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*0890*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*08b0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*08c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08d0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff72004007950 */
/* 0x000fea0003c3ffff */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5exponPfi
.globl _Z5exponPfi
.p2align 8
.type _Z5exponPfi,@function
_Z5exponPfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, 0x3fb8aa3b, -v3
v_rndne_f32_e32 v5, v3
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5exponPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5exponPfi, .Lfunc_end0-_Z5exponPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5exponPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5exponPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cd269_00000000-6_expon.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5exponPfiPfi
.type _Z25__device_stub__Z5exponPfiPfi, @function
_Z25__device_stub__Z5exponPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5exponPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z5exponPfiPfi, .-_Z25__device_stub__Z5exponPfiPfi
.globl _Z5exponPfi
.type _Z5exponPfi, @function
_Z5exponPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5exponPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5exponPfi, .-_Z5exponPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5exponPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5exponPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "expon.hip"
.globl _Z20__device_stub__exponPfi # -- Begin function _Z20__device_stub__exponPfi
.p2align 4, 0x90
.type _Z20__device_stub__exponPfi,@function
_Z20__device_stub__exponPfi: # @_Z20__device_stub__exponPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5exponPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__exponPfi, .Lfunc_end0-_Z20__device_stub__exponPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5exponPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5exponPfi,@object # @_Z5exponPfi
.section .rodata,"a",@progbits
.globl _Z5exponPfi
.p2align 3, 0x0
_Z5exponPfi:
.quad _Z20__device_stub__exponPfi
.size _Z5exponPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5exponPfi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__exponPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5exponPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <vector>
#include <iostream>
#include <cstdint>
#include <cmath>
__global__ void vector_sum(std::size_t _size,
float _scale,
float* _a,
float* _b){
const std::size_t index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < _size)
_a[index] = _scale*_a[index] + _b[index];
}
int main(int argc, char *argv[])
{
std::size_t vector_size = (1<<20);
if(argc>1)
vector_size*=std::stoi(argv[1]);
std::cout << "vector sum: " << vector_size << " elements" << std::endl;
std::vector<float> host_a(vector_size,1.f);
std::vector<float> host_b(vector_size,2.f);
const float host_d = 42.f;
//gpu relevant code
float * device_a=nullptr, *device_b=nullptr;
const std::size_t vector_size_byte=vector_size*sizeof(float);
cudaMalloc(&device_a, vector_size_byte);
cudaMalloc(&device_b, vector_size_byte);
cudaMemcpy(device_a, &host_a[0], vector_size_byte,
cudaMemcpyHostToDevice);
cudaMemcpy(device_b, &host_b[0], vector_size_byte,
cudaMemcpyHostToDevice);
vector_sum<<<(vector_size+255)/256, 256>>>(vector_size,
host_d,
device_a,
device_b);
cudaMemcpy(&host_a[0], device_a, vector_size_byte,
cudaMemcpyDeviceToHost);
float max_error = 0.0f;
for (const float& item : host_a )
max_error = std::max(max_error, std::abs(item-44.0f));
std::cout << "Max error: " << max_error << std::endl;
cudaFree(device_a);
cudaFree(device_b);
return 0;
} | code for sm_80
Function : _Z10vector_summfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R4, P1, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R3, R0.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000037a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0000057a10 */
/* 0x000fc60000ffe4ff */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0100*/ FFMA R7, R0, c[0x0][0x168], R5 ; /* 0x00005a0000077a23 */
/* 0x004fca0000000005 */
/*0110*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <vector>
#include <iostream>
#include <cstdint>
#include <cmath>
__global__ void vector_sum(std::size_t _size,
float _scale,
float* _a,
float* _b){
const std::size_t index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < _size)
_a[index] = _scale*_a[index] + _b[index];
}
int main(int argc, char *argv[])
{
std::size_t vector_size = (1<<20);
if(argc>1)
vector_size*=std::stoi(argv[1]);
std::cout << "vector sum: " << vector_size << " elements" << std::endl;
std::vector<float> host_a(vector_size,1.f);
std::vector<float> host_b(vector_size,2.f);
const float host_d = 42.f;
//gpu relevant code
float * device_a=nullptr, *device_b=nullptr;
const std::size_t vector_size_byte=vector_size*sizeof(float);
cudaMalloc(&device_a, vector_size_byte);
cudaMalloc(&device_b, vector_size_byte);
cudaMemcpy(device_a, &host_a[0], vector_size_byte,
cudaMemcpyHostToDevice);
cudaMemcpy(device_b, &host_b[0], vector_size_byte,
cudaMemcpyHostToDevice);
vector_sum<<<(vector_size+255)/256, 256>>>(vector_size,
host_d,
device_a,
device_b);
cudaMemcpy(&host_a[0], device_a, vector_size_byte,
cudaMemcpyDeviceToHost);
float max_error = 0.0f;
for (const float& item : host_a )
max_error = std::max(max_error, std::abs(item-44.0f));
std::cout << "Max error: " << max_error << std::endl;
cudaFree(device_a);
cudaFree(device_b);
return 0;
} | .file "tmpxft_000d3d20_00000000-6_vector_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10vector_summfPfS_mfPfS_
.type _Z34__device_stub__Z10vector_summfPfS_mfPfS_, @function
_Z34__device_stub__Z10vector_summfPfS_mfPfS_:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_summfPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z34__device_stub__Z10vector_summfPfS_mfPfS_, .-_Z34__device_stub__Z10vector_summfPfS_mfPfS_
.globl _Z10vector_summfPfS_
.type _Z10vector_summfPfS_, @function
_Z10vector_summfPfS_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_summfPfS_mfPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z10vector_summfPfS_, .-_Z10vector_summfPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10vector_summfPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_summfPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKfRKS0_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.type _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_:
.LFB4374:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L21
movq %rdi, %rbx
movq %rdx, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L15
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movss 0(%rbp), %xmm0
.L16:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
.L17:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L15:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
jmp .L17
.cfi_endproc
.LFE4374:
.size _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.weak _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.set _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4377:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L25
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L25:
ret
.cfi_endproc
.LFE4377:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1
.LC4:
.string "stoi"
.LC5:
.string "vector sum: "
.LC6:
.string " elements"
.LC12:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $176, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L54
movq 8(%rsi), %rbp
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
testq %rbp, %rbp
je .L63
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 96(%rsp)
cmpq $15, %rax
ja .L64
cmpq $1, %rax
jne .L34
movzbl 0(%rbp), %eax
movb %al, 144(%rsp)
.L35:
movq 96(%rsp), %rax
movq %rax, 136(%rsp)
movq 128(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 128(%rsp), %r12
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
leaq 96(%rsp), %rsi
movl $10, %edx
movq %r12, %rdi
call __isoc23_strtol@PLT
cmpq 96(%rsp), %r12
je .L65
movl (%rbx), %ecx
cmpl $34, %ecx
je .L38
movl $2147483648, %edx
addq %rax, %rdx
movl $4294967295, %esi
cmpq %rdx, %rsi
jb .L38
testl %ecx, %ecx
jne .L41
movl %ebp, (%rbx)
.L41:
movslq %eax, %rbp
salq $20, %rbp
leaq 128(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L29:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0x3f800000, 96(%rsp)
leaq 52(%rsp), %r12
leaq 96(%rsp), %rbx
leaq 64(%rsp), %rdi
movq %r12, %rcx
movq %rbx, %rdx
movq %rbp, %rsi
call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE0:
movl $0x40000000, 52(%rsp)
leaq 40(%rsp), %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE1:
jmp .L66
.L63:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L67
leaq .LC3(%rip), %rdi
.LEHB2:
call _ZSt19__throw_logic_errorPKc@PLT
.L67:
call __stack_chk_fail@PLT
.L64:
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE2:
movq %rax, %rdi
movq %rax, 128(%rsp)
movq 96(%rsp), %rax
movq %rax, 144(%rsp)
.L33:
movq %rbx, %rdx
movq %rbp, %rsi
call memcpy@PLT
jmp .L35
.L34:
testq %rax, %rax
je .L35
leaq 144(%rsp), %rdi
jmp .L33
.L65:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L68
leaq .LC4(%rip), %rdi
.LEHB3:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L68:
call __stack_chk_fail@PLT
.L38:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L69
leaq .LC4(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE3:
.L58:
endbr64
movq %rax, %r12
cmpl $0, (%rbx)
jne .L43
movl %ebp, (%rbx)
.L43:
leaq 128(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L69:
call __stack_chk_fail@PLT
.L44:
movq %r12, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L54:
movl $1048576, %ebp
jmp .L29
.L66:
movq $0, 24(%rsp)
movq $0, 32(%rsp)
leaq 0(,%rbp,4), %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
.LEHB5:
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq 64(%rsp), %rbx
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 96(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movq %rbp, %rax
shrq $8, %rax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movss .LC9(%rip), %xmm0
movq %rbp, %rdi
call _Z34__device_stub__Z10vector_summfPfS_mfPfS_
.L45:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdx
cmpq %rdx, %rbx
je .L55
movq %rbx, %rax
movl $0x00000000, 12(%rsp)
movss .LC10(%rip), %xmm2
movss .LC11(%rip), %xmm1
.L49:
movss (%rax), %xmm0
subss %xmm2, %xmm0
andps %xmm1, %xmm0
maxss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L49
.L46:
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L70
.L55:
movl $0x00000000, 12(%rsp)
jmp .L46
.L70:
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE5:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L51:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L56:
endbr64
movq %rax, %rbx
jmp .L51
.L52:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L58-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4032
.uleb128 .LEHE5-.LEHB5
.uleb128 .L57-.LFB4032
.uleb128 0
.uleb128 .LEHB6-.LFB4032
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1109917696
.align 4
.LC10:
.long 1110441984
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <vector>
#include <iostream>
#include <cstdint>
#include <cmath>
__global__ void vector_sum(std::size_t _size,
float _scale,
float* _a,
float* _b){
const std::size_t index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < _size)
_a[index] = _scale*_a[index] + _b[index];
}
int main(int argc, char *argv[])
{
std::size_t vector_size = (1<<20);
if(argc>1)
vector_size*=std::stoi(argv[1]);
std::cout << "vector sum: " << vector_size << " elements" << std::endl;
std::vector<float> host_a(vector_size,1.f);
std::vector<float> host_b(vector_size,2.f);
const float host_d = 42.f;
//gpu relevant code
float * device_a=nullptr, *device_b=nullptr;
const std::size_t vector_size_byte=vector_size*sizeof(float);
cudaMalloc(&device_a, vector_size_byte);
cudaMalloc(&device_b, vector_size_byte);
cudaMemcpy(device_a, &host_a[0], vector_size_byte,
cudaMemcpyHostToDevice);
cudaMemcpy(device_b, &host_b[0], vector_size_byte,
cudaMemcpyHostToDevice);
vector_sum<<<(vector_size+255)/256, 256>>>(vector_size,
host_d,
device_a,
device_b);
cudaMemcpy(&host_a[0], device_a, vector_size_byte,
cudaMemcpyDeviceToHost);
float max_error = 0.0f;
for (const float& item : host_a )
max_error = std::max(max_error, std::abs(item-44.0f));
std::cout << "Max error: " << max_error << std::endl;
cudaFree(device_a);
cudaFree(device_b);
return 0;
} | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <cstdint>
#include <cmath>
__global__ void vector_sum(std::size_t _size,
float _scale,
float* _a,
float* _b){
const std::size_t index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < _size)
_a[index] = _scale*_a[index] + _b[index];
}
int main(int argc, char *argv[])
{
std::size_t vector_size = (1<<20);
if(argc>1)
vector_size*=std::stoi(argv[1]);
std::cout << "vector sum: " << vector_size << " elements" << std::endl;
std::vector<float> host_a(vector_size,1.f);
std::vector<float> host_b(vector_size,2.f);
const float host_d = 42.f;
//gpu relevant code
float * device_a=nullptr, *device_b=nullptr;
const std::size_t vector_size_byte=vector_size*sizeof(float);
hipMalloc(&device_a, vector_size_byte);
hipMalloc(&device_b, vector_size_byte);
hipMemcpy(device_a, &host_a[0], vector_size_byte,
hipMemcpyHostToDevice);
hipMemcpy(device_b, &host_b[0], vector_size_byte,
hipMemcpyHostToDevice);
vector_sum<<<(vector_size+255)/256, 256>>>(vector_size,
host_d,
device_a,
device_b);
hipMemcpy(&host_a[0], device_a, vector_size_byte,
hipMemcpyDeviceToHost);
float max_error = 0.0f;
for (const float& item : host_a )
max_error = std::max(max_error, std::abs(item-44.0f));
std::cout << "Max error: " << max_error << std::endl;
hipFree(device_a);
hipFree(device_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <cstdint>
#include <cmath>
__global__ void vector_sum(std::size_t _size,
float _scale,
float* _a,
float* _b){
const std::size_t index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < _size)
_a[index] = _scale*_a[index] + _b[index];
}
int main(int argc, char *argv[])
{
std::size_t vector_size = (1<<20);
if(argc>1)
vector_size*=std::stoi(argv[1]);
std::cout << "vector sum: " << vector_size << " elements" << std::endl;
std::vector<float> host_a(vector_size,1.f);
std::vector<float> host_b(vector_size,2.f);
const float host_d = 42.f;
//gpu relevant code
float * device_a=nullptr, *device_b=nullptr;
const std::size_t vector_size_byte=vector_size*sizeof(float);
hipMalloc(&device_a, vector_size_byte);
hipMalloc(&device_b, vector_size_byte);
hipMemcpy(device_a, &host_a[0], vector_size_byte,
hipMemcpyHostToDevice);
hipMemcpy(device_b, &host_b[0], vector_size_byte,
hipMemcpyHostToDevice);
vector_sum<<<(vector_size+255)/256, 256>>>(vector_size,
host_d,
device_a,
device_b);
hipMemcpy(&host_a[0], device_a, vector_size_byte,
hipMemcpyDeviceToHost);
float max_error = 0.0f;
for (const float& item : host_a )
max_error = std::max(max_error, std::abs(item-44.0f));
std::cout << "Max error: " << max_error << std::endl;
hipFree(device_a);
hipFree(device_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_summfPfS_
.globl _Z10vector_summfPfS_
.p2align 8
.type _Z10vector_summfPfS_,@function
_Z10vector_summfPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s0, v4
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_summfPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_summfPfS_, .Lfunc_end0-_Z10vector_summfPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_summfPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_summfPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <cstdint>
#include <cmath>
__global__ void vector_sum(std::size_t _size,
float _scale,
float* _a,
float* _b){
const std::size_t index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < _size)
_a[index] = _scale*_a[index] + _b[index];
}
int main(int argc, char *argv[])
{
std::size_t vector_size = (1<<20);
if(argc>1)
vector_size*=std::stoi(argv[1]);
std::cout << "vector sum: " << vector_size << " elements" << std::endl;
std::vector<float> host_a(vector_size,1.f);
std::vector<float> host_b(vector_size,2.f);
const float host_d = 42.f;
//gpu relevant code
float * device_a=nullptr, *device_b=nullptr;
const std::size_t vector_size_byte=vector_size*sizeof(float);
hipMalloc(&device_a, vector_size_byte);
hipMalloc(&device_b, vector_size_byte);
hipMemcpy(device_a, &host_a[0], vector_size_byte,
hipMemcpyHostToDevice);
hipMemcpy(device_b, &host_b[0], vector_size_byte,
hipMemcpyHostToDevice);
vector_sum<<<(vector_size+255)/256, 256>>>(vector_size,
host_d,
device_a,
device_b);
hipMemcpy(&host_a[0], device_a, vector_size_byte,
hipMemcpyDeviceToHost);
float max_error = 0.0f;
for (const float& item : host_a )
max_error = std::max(max_error, std::abs(item-44.0f));
std::cout << "Max error: " << max_error << std::endl;
hipFree(device_a);
hipFree(device_b);
return 0;
} | .text
.file "vector_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__vector_summfPfS_ # -- Begin function _Z25__device_stub__vector_summfPfS_
.p2align 4, 0x90
.type _Z25__device_stub__vector_summfPfS_,@function
_Z25__device_stub__vector_summfPfS_: # @_Z25__device_stub__vector_summfPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 4(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_summfPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_summfPfS_, .Lfunc_end0-_Z25__device_stub__vector_summfPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc2300000 # float -44
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1048576, %r15d # imm = 0x100000
cmpl $2, %edi
jl .LBB1_34
# %bb.1:
movq 8(%rsi), %rbx
leaq 48(%rsp), %r12
movq %r12, 32(%rsp)
testq %rbx, %rbx
je .LBB1_2
# %bb.4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB1_13
# %bb.5:
testq %r14, %r14
js .LBB1_6
# %bb.8:
movq %r14, %rdi
incq %rdi
js .LBB1_9
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.12: # %.noexc35
movq %rax, 32(%rsp)
movq %r14, 48(%rsp)
.LBB1_13:
testq %r14, %r14
je .LBB1_17
# %bb.14:
movq 32(%rsp), %rdi
cmpq $1, %r14
jne .LBB1_16
# %bb.15:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB1_17
.LBB1_16:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r14, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax,%r14)
movq 32(%rsp), %r14
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rsi
movq %r14, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r14, 72(%rsp)
je .LBB1_18
# %bb.25:
movslq %eax, %rcx
cmpq %rax, %rcx
jne .LBB1_27
# %bb.26:
movl (%rbx), %ecx
cmpl $34, %ecx
je .LBB1_27
# %bb.29:
testl %ecx, %ecx
jne .LBB1_31
# %bb.30:
movl %ebp, (%rbx)
.LBB1_31: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movslq %eax, %r15
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .LBB1_33
# %bb.32: # %.critedge.i.i36
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
shlq $20, %r15
.LBB1_34:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_35
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_39
# %bb.38:
movzbl 67(%r14), %eax
jmp .LBB1_40
.LBB1_39:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r15, %rax
shrq $61, %rax
jne .LBB1_95
# %bb.41: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
testq %r15, %r15
je .LBB1_42
# %bb.43: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
leaq (,%r15,4), %rdi
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, %rbx
jmp .LBB1_44
.LBB1_42:
xorl %ebx, %ebx
.LBB1_44: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rbx, %r13
testq %r15, %r15
je .LBB1_47
# %bb.45: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
leaq (%rbx,%r15,4), %r13
leaq (,%r15,4), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_46: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx) # imm = 0x3F800000
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB1_46
.LBB1_47: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i42
testq %r15, %r15
je .LBB1_48
# %bb.49: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i44
leaq (,%r15,4), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp3:
# %bb.50:
movq %rax, %r14
testq %r15, %r15
jne .LBB1_52
jmp .LBB1_54
.LBB1_48:
xorl %r14d, %r14d
testq %r15, %r15
je .LBB1_54
.LBB1_52: # %.lr.ph.i.i.i.i.i.i.i.i.i46.preheader
leaq (,%r15,4), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_53: # %.lr.ph.i.i.i.i.i.i.i.i.i46
# =>This Inner Loop Header: Depth=1
movl $1073741824, (%r14,%rcx) # imm = 0x40000000
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB1_53
.LBB1_54: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit52
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq (,%r15,4), %r12
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp6:
# %bb.55: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp8:
# %bb.56: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit55
movq 8(%rsp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.57:
movq 16(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.58:
movq %r15, %rax
shrq $8, %rax
movl %eax, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp14:
# %bb.59:
testl %eax, %eax
jne .LBB1_62
# %bb.60:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %r15, 144(%rsp)
movl $1109917696, 28(%rsp) # imm = 0x42280000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp16:
# %bb.61: # %.noexc56
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
.Ltmp17:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z10vector_summfPfS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp18:
.LBB1_62:
movq 8(%rsp), %rsi
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp20:
# %bb.63: # %.preheader
cmpq %r13, %rbx
je .LBB1_64
# %bb.72: # %.lr.ph.preheader
xorps %xmm0, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movq %rbx, %rax
.p2align 4, 0x90
.LBB1_73: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm3
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
andps %xmm2, %xmm0
maxss %xmm3, %xmm0
addq $4, %rax
cmpq %r13, %rax
jne .LBB1_73
# %bb.67: # %._crit_edge.loopexit
cvtss2sd %xmm0, %xmm0
jmp .LBB1_68
.LBB1_64:
xorps %xmm0, %xmm0
.LBB1_68: # %._crit_edge
movsd %xmm0, 88(%rsp) # 8-byte Spill
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.69: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.70: # %_ZNSolsEf.exit
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_71
# %bb.75: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i69
cmpb $0, 56(%r12)
je .LBB1_77
# %bb.76:
movzbl 67(%r12), %eax
jmp .LBB1_79
.LBB1_77:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp27:
# %bb.78: # %.noexc73
movq (%r12), %rax
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp29:
.LBB1_79: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp30:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp31:
# %bb.80: # %.noexc75
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp33:
# %bb.81: # %_ZNSolsEPFRSoS_E.exit
movq 8(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.82:
movq 16(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp37:
# %bb.83:
testq %r14, %r14
je .LBB1_85
# %bb.84:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_85: # %_ZNSt6vectorIfSaIfEED2Ev.exit
testq %rbx, %rbx
je .LBB1_87
# %bb.86:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_87: # %_ZNSt6vectorIfSaIfEED2Ev.exit62
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9: # %.noexc11.i
.cfi_def_cfa_offset 208
.Ltmp46:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp47:
# %bb.10: # %.noexc34
.LBB1_35:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_95: # %.noexc40
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_71:
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp39:
# %bb.74: # %.noexc72
.LBB1_2:
.Ltmp50:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp51:
# %bb.3: # %.noexc
.LBB1_18:
.Ltmp43:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp44:
# %bb.19:
.LBB1_27: # %.critedge.i.i
.Ltmp41:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp42:
# %bb.28:
.LBB1_6: # %.noexc.i
.Ltmp48:
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp49:
# %bb.7: # %.noexc33
.LBB1_65:
.Ltmp4:
movq %rax, %r15
testq %rbx, %rbx
je .LBB1_93
jmp .LBB1_92
.LBB1_20:
.Ltmp45:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_22
# %bb.21:
movl %ebp, (%rbx)
.LBB1_22: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .LBB1_24
# %bb.23: # %.critedge.i.i37
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit39
movq %r14, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_66:
.Ltmp21:
jmp .LBB1_89
.LBB1_88:
.Ltmp40:
.LBB1_89:
movq %rax, %r15
testq %r14, %r14
jne .LBB1_90
# %bb.91: # %_ZNSt6vectorIfSaIfEED2Ev.exit64
testq %rbx, %rbx
jne .LBB1_92
.LBB1_93: # %_ZNSt6vectorIfSaIfEED2Ev.exit66
movq %r15, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_90:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
testq %rbx, %rbx
je .LBB1_93
.LBB1_92:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
movq %r15, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_36:
.Ltmp52:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp20-.Ltmp5 # Call between .Ltmp5 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp37-.Ltmp22 # Call between .Ltmp22 and .Ltmp37
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp38-.Ltmp47 # Call between .Ltmp47 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp51-.Ltmp50 # Call between .Ltmp50 and .Ltmp51
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp42-.Ltmp43 # Call between .Ltmp43 and .Ltmp42
.uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp49 # Call between .Ltmp49 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_summfPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_summfPfS_,@object # @_Z10vector_summfPfS_
.section .rodata,"a",@progbits
.globl _Z10vector_summfPfS_
.p2align 3, 0x0
_Z10vector_summfPfS_:
.quad _Z25__device_stub__vector_summfPfS_
.size _Z10vector_summfPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "vector sum: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " elements"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Max error: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "stoi"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "basic_string: construction from null is not valid"
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "basic_string::_M_create"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.6, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_summfPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_summfPfS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10vector_summfPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_summfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R4, P1, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R3, R0.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000037a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0000057a10 */
/* 0x000fc60000ffe4ff */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0100*/ FFMA R7, R0, c[0x0][0x168], R5 ; /* 0x00005a0000077a23 */
/* 0x004fca0000000005 */
/*0110*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_summfPfS_
.globl _Z10vector_summfPfS_
.p2align 8
.type _Z10vector_summfPfS_,@function
_Z10vector_summfPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s0, v4
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_summfPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_summfPfS_, .Lfunc_end0-_Z10vector_summfPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_summfPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_summfPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d3d20_00000000-6_vector_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10vector_summfPfS_mfPfS_
.type _Z34__device_stub__Z10vector_summfPfS_mfPfS_, @function
_Z34__device_stub__Z10vector_summfPfS_mfPfS_:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_summfPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z34__device_stub__Z10vector_summfPfS_mfPfS_, .-_Z34__device_stub__Z10vector_summfPfS_mfPfS_
.globl _Z10vector_summfPfS_
.type _Z10vector_summfPfS_, @function
_Z10vector_summfPfS_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_summfPfS_mfPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z10vector_summfPfS_, .-_Z10vector_summfPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10vector_summfPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_summfPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKfRKS0_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.type _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_:
.LFB4374:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L21
movq %rdi, %rbx
movq %rdx, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L15
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movss 0(%rbp), %xmm0
.L16:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
.L17:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L15:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
jmp .L17
.cfi_endproc
.LFE4374:
.size _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.weak _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.set _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4377:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L25
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L25:
ret
.cfi_endproc
.LFE4377:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1
.LC4:
.string "stoi"
.LC5:
.string "vector sum: "
.LC6:
.string " elements"
.LC12:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $176, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L54
movq 8(%rsi), %rbp
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
testq %rbp, %rbp
je .L63
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 96(%rsp)
cmpq $15, %rax
ja .L64
cmpq $1, %rax
jne .L34
movzbl 0(%rbp), %eax
movb %al, 144(%rsp)
.L35:
movq 96(%rsp), %rax
movq %rax, 136(%rsp)
movq 128(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 128(%rsp), %r12
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
leaq 96(%rsp), %rsi
movl $10, %edx
movq %r12, %rdi
call __isoc23_strtol@PLT
cmpq 96(%rsp), %r12
je .L65
movl (%rbx), %ecx
cmpl $34, %ecx
je .L38
movl $2147483648, %edx
addq %rax, %rdx
movl $4294967295, %esi
cmpq %rdx, %rsi
jb .L38
testl %ecx, %ecx
jne .L41
movl %ebp, (%rbx)
.L41:
movslq %eax, %rbp
salq $20, %rbp
leaq 128(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L29:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0x3f800000, 96(%rsp)
leaq 52(%rsp), %r12
leaq 96(%rsp), %rbx
leaq 64(%rsp), %rdi
movq %r12, %rcx
movq %rbx, %rdx
movq %rbp, %rsi
call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE0:
movl $0x40000000, 52(%rsp)
leaq 40(%rsp), %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE1:
jmp .L66
.L63:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L67
leaq .LC3(%rip), %rdi
.LEHB2:
call _ZSt19__throw_logic_errorPKc@PLT
.L67:
call __stack_chk_fail@PLT
.L64:
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE2:
movq %rax, %rdi
movq %rax, 128(%rsp)
movq 96(%rsp), %rax
movq %rax, 144(%rsp)
.L33:
movq %rbx, %rdx
movq %rbp, %rsi
call memcpy@PLT
jmp .L35
.L34:
testq %rax, %rax
je .L35
leaq 144(%rsp), %rdi
jmp .L33
.L65:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L68
leaq .LC4(%rip), %rdi
.LEHB3:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L68:
call __stack_chk_fail@PLT
.L38:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L69
leaq .LC4(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE3:
.L58:
endbr64
movq %rax, %r12
cmpl $0, (%rbx)
jne .L43
movl %ebp, (%rbx)
.L43:
leaq 128(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L69:
call __stack_chk_fail@PLT
.L44:
movq %r12, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L54:
movl $1048576, %ebp
jmp .L29
.L66:
movq $0, 24(%rsp)
movq $0, 32(%rsp)
leaq 0(,%rbp,4), %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
.LEHB5:
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq 64(%rsp), %rbx
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 96(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movq %rbp, %rax
shrq $8, %rax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movss .LC9(%rip), %xmm0
movq %rbp, %rdi
call _Z34__device_stub__Z10vector_summfPfS_mfPfS_
.L45:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdx
cmpq %rdx, %rbx
je .L55
movq %rbx, %rax
movl $0x00000000, 12(%rsp)
movss .LC10(%rip), %xmm2
movss .LC11(%rip), %xmm1
.L49:
movss (%rax), %xmm0
subss %xmm2, %xmm0
andps %xmm1, %xmm0
maxss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L49
.L46:
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L70
.L55:
movl $0x00000000, 12(%rsp)
jmp .L46
.L70:
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE5:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L51:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L56:
endbr64
movq %rax, %rbx
jmp .L51
.L52:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L58-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4032
.uleb128 .LEHE5-.LEHB5
.uleb128 .L57-.LFB4032
.uleb128 0
.uleb128 .LEHB6-.LFB4032
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1109917696
.align 4
.LC10:
.long 1110441984
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__vector_summfPfS_ # -- Begin function _Z25__device_stub__vector_summfPfS_
.p2align 4, 0x90
.type _Z25__device_stub__vector_summfPfS_,@function
_Z25__device_stub__vector_summfPfS_: # @_Z25__device_stub__vector_summfPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 4(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_summfPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_summfPfS_, .Lfunc_end0-_Z25__device_stub__vector_summfPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc2300000 # float -44
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1048576, %r15d # imm = 0x100000
cmpl $2, %edi
jl .LBB1_34
# %bb.1:
movq 8(%rsi), %rbx
leaq 48(%rsp), %r12
movq %r12, 32(%rsp)
testq %rbx, %rbx
je .LBB1_2
# %bb.4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB1_13
# %bb.5:
testq %r14, %r14
js .LBB1_6
# %bb.8:
movq %r14, %rdi
incq %rdi
js .LBB1_9
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.12: # %.noexc35
movq %rax, 32(%rsp)
movq %r14, 48(%rsp)
.LBB1_13:
testq %r14, %r14
je .LBB1_17
# %bb.14:
movq 32(%rsp), %rdi
cmpq $1, %r14
jne .LBB1_16
# %bb.15:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB1_17
.LBB1_16:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r14, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax,%r14)
movq 32(%rsp), %r14
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %rbx
movl (%rax), %ebp
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rsi
movq %r14, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r14, 72(%rsp)
je .LBB1_18
# %bb.25:
movslq %eax, %rcx
cmpq %rax, %rcx
jne .LBB1_27
# %bb.26:
movl (%rbx), %ecx
cmpl $34, %ecx
je .LBB1_27
# %bb.29:
testl %ecx, %ecx
jne .LBB1_31
# %bb.30:
movl %ebp, (%rbx)
.LBB1_31: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movslq %eax, %r15
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .LBB1_33
# %bb.32: # %.critedge.i.i36
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
shlq $20, %r15
.LBB1_34:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_35
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_39
# %bb.38:
movzbl 67(%r14), %eax
jmp .LBB1_40
.LBB1_39:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r15, %rax
shrq $61, %rax
jne .LBB1_95
# %bb.41: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
testq %r15, %r15
je .LBB1_42
# %bb.43: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
leaq (,%r15,4), %rdi
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, %rbx
jmp .LBB1_44
.LBB1_42:
xorl %ebx, %ebx
.LBB1_44: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rbx, %r13
testq %r15, %r15
je .LBB1_47
# %bb.45: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
leaq (%rbx,%r15,4), %r13
leaq (,%r15,4), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_46: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx) # imm = 0x3F800000
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB1_46
.LBB1_47: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i42
testq %r15, %r15
je .LBB1_48
# %bb.49: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i44
leaq (,%r15,4), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp3:
# %bb.50:
movq %rax, %r14
testq %r15, %r15
jne .LBB1_52
jmp .LBB1_54
.LBB1_48:
xorl %r14d, %r14d
testq %r15, %r15
je .LBB1_54
.LBB1_52: # %.lr.ph.i.i.i.i.i.i.i.i.i46.preheader
leaq (,%r15,4), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_53: # %.lr.ph.i.i.i.i.i.i.i.i.i46
# =>This Inner Loop Header: Depth=1
movl $1073741824, (%r14,%rcx) # imm = 0x40000000
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB1_53
.LBB1_54: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit52
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq (,%r15,4), %r12
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp6:
# %bb.55: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp8:
# %bb.56: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit55
movq 8(%rsp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.57:
movq 16(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.58:
movq %r15, %rax
shrq $8, %rax
movl %eax, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp14:
# %bb.59:
testl %eax, %eax
jne .LBB1_62
# %bb.60:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %r15, 144(%rsp)
movl $1109917696, 28(%rsp) # imm = 0x42280000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp16:
# %bb.61: # %.noexc56
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
.Ltmp17:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z10vector_summfPfS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp18:
.LBB1_62:
movq 8(%rsp), %rsi
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp20:
# %bb.63: # %.preheader
cmpq %r13, %rbx
je .LBB1_64
# %bb.72: # %.lr.ph.preheader
xorps %xmm0, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movq %rbx, %rax
.p2align 4, 0x90
.LBB1_73: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm3
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
andps %xmm2, %xmm0
maxss %xmm3, %xmm0
addq $4, %rax
cmpq %r13, %rax
jne .LBB1_73
# %bb.67: # %._crit_edge.loopexit
cvtss2sd %xmm0, %xmm0
jmp .LBB1_68
.LBB1_64:
xorps %xmm0, %xmm0
.LBB1_68: # %._crit_edge
movsd %xmm0, 88(%rsp) # 8-byte Spill
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.69: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.70: # %_ZNSolsEf.exit
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_71
# %bb.75: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i69
cmpb $0, 56(%r12)
je .LBB1_77
# %bb.76:
movzbl 67(%r12), %eax
jmp .LBB1_79
.LBB1_77:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp27:
# %bb.78: # %.noexc73
movq (%r12), %rax
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp29:
.LBB1_79: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp30:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp31:
# %bb.80: # %.noexc75
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp33:
# %bb.81: # %_ZNSolsEPFRSoS_E.exit
movq 8(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.82:
movq 16(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp37:
# %bb.83:
testq %r14, %r14
je .LBB1_85
# %bb.84:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_85: # %_ZNSt6vectorIfSaIfEED2Ev.exit
testq %rbx, %rbx
je .LBB1_87
# %bb.86:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_87: # %_ZNSt6vectorIfSaIfEED2Ev.exit62
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9: # %.noexc11.i
.cfi_def_cfa_offset 208
.Ltmp46:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp47:
# %bb.10: # %.noexc34
.LBB1_35:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_95: # %.noexc40
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_71:
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp39:
# %bb.74: # %.noexc72
.LBB1_2:
.Ltmp50:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp51:
# %bb.3: # %.noexc
.LBB1_18:
.Ltmp43:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp44:
# %bb.19:
.LBB1_27: # %.critedge.i.i
.Ltmp41:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp42:
# %bb.28:
.LBB1_6: # %.noexc.i
.Ltmp48:
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp49:
# %bb.7: # %.noexc33
.LBB1_65:
.Ltmp4:
movq %rax, %r15
testq %rbx, %rbx
je .LBB1_93
jmp .LBB1_92
.LBB1_20:
.Ltmp45:
movq %rax, %r14
cmpl $0, (%rbx)
jne .LBB1_22
# %bb.21:
movl %ebp, (%rbx)
.LBB1_22: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .LBB1_24
# %bb.23: # %.critedge.i.i37
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit39
movq %r14, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_66:
.Ltmp21:
jmp .LBB1_89
.LBB1_88:
.Ltmp40:
.LBB1_89:
movq %rax, %r15
testq %r14, %r14
jne .LBB1_90
# %bb.91: # %_ZNSt6vectorIfSaIfEED2Ev.exit64
testq %rbx, %rbx
jne .LBB1_92
.LBB1_93: # %_ZNSt6vectorIfSaIfEED2Ev.exit66
movq %r15, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_90:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
testq %rbx, %rbx
je .LBB1_93
.LBB1_92:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
movq %r15, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.LBB1_36:
.Ltmp52:
movq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp20-.Ltmp5 # Call between .Ltmp5 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp37-.Ltmp22 # Call between .Ltmp22 and .Ltmp37
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp38-.Ltmp47 # Call between .Ltmp47 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp51-.Ltmp50 # Call between .Ltmp50 and .Ltmp51
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp42-.Ltmp43 # Call between .Ltmp43 and .Ltmp42
.uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp49 # Call between .Ltmp49 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_summfPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_summfPfS_,@object # @_Z10vector_summfPfS_
.section .rodata,"a",@progbits
.globl _Z10vector_summfPfS_
.p2align 3, 0x0
_Z10vector_summfPfS_:
.quad _Z25__device_stub__vector_summfPfS_
.size _Z10vector_summfPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "vector sum: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " elements"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Max error: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "stoi"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "basic_string: construction from null is not valid"
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "basic_string::_M_create"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.6, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_summfPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_summfPfS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10vector_summfPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void dual(float* p1, float* p2, const float* u_, const double lambda, const double sigma, const int X, const int Y)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// center point
int c = y*X + x;
float nabla_x = 0.0f;
float nabla_y = 0.0f;
if (x < X-1)
nabla_x = u_[c+1]-u_[c];
if (y < Y-1)
nabla_y = u_[c+X]-u_[c];
//p1[c] = fmaxf(-lambda, fminf(lambda, p1[c] + sigma*nabla_x));
//p2[c] = fmaxf(-lambda, fminf(lambda, p2[c] + sigma*nabla_y));
p1[c] += sigma*nabla_x;
p2[c] += sigma*nabla_y;
float denom = fmaxf(1.0f, sqrt(p1[c]*p1[c] + p2[c]*p2[c])/lambda);
p1[c] /= denom;
p2[c] /= denom;
} | .file "tmpxft_0017b9ab_00000000-6_dual.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii
.type _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii, @function
_Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4dualPfS_PKfddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii, .-_Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii
.globl _Z4dualPfS_PKfddii
.type _Z4dualPfS_PKfddii, @function
_Z4dualPfS_PKfddii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4dualPfS_PKfddii, .-_Z4dualPfS_PKfddii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4dualPfS_PKfddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4dualPfS_PKfddii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void dual(float* p1, float* p2, const float* u_, const double lambda, const double sigma, const int X, const int Y)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// center point
int c = y*X + x;
float nabla_x = 0.0f;
float nabla_y = 0.0f;
if (x < X-1)
nabla_x = u_[c+1]-u_[c];
if (y < Y-1)
nabla_y = u_[c+X]-u_[c];
//p1[c] = fmaxf(-lambda, fminf(lambda, p1[c] + sigma*nabla_x));
//p2[c] = fmaxf(-lambda, fminf(lambda, p2[c] + sigma*nabla_y));
p1[c] += sigma*nabla_x;
p2[c] += sigma*nabla_y;
float denom = fmaxf(1.0f, sqrt(p1[c]*p1[c] + p2[c]*p2[c])/lambda);
p1[c] /= denom;
p2[c] /= denom;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dual(float* p1, float* p2, const float* u_, const double lambda, const double sigma, const int X, const int Y)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// center point
int c = y*X + x;
float nabla_x = 0.0f;
float nabla_y = 0.0f;
if (x < X-1)
nabla_x = u_[c+1]-u_[c];
if (y < Y-1)
nabla_y = u_[c+X]-u_[c];
//p1[c] = fmaxf(-lambda, fminf(lambda, p1[c] + sigma*nabla_x));
//p2[c] = fmaxf(-lambda, fminf(lambda, p2[c] + sigma*nabla_y));
p1[c] += sigma*nabla_x;
p2[c] += sigma*nabla_y;
float denom = fmaxf(1.0f, sqrt(p1[c]*p1[c] + p2[c]*p2[c])/lambda);
p1[c] /= denom;
p2[c] /= denom;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dual(float* p1, float* p2, const float* u_, const double lambda, const double sigma, const int X, const int Y)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// center point
int c = y*X + x;
float nabla_x = 0.0f;
float nabla_y = 0.0f;
if (x < X-1)
nabla_x = u_[c+1]-u_[c];
if (y < Y-1)
nabla_y = u_[c+X]-u_[c];
//p1[c] = fmaxf(-lambda, fminf(lambda, p1[c] + sigma*nabla_x));
//p2[c] = fmaxf(-lambda, fminf(lambda, p2[c] + sigma*nabla_y));
p1[c] += sigma*nabla_x;
p2[c] += sigma*nabla_y;
float denom = fmaxf(1.0f, sqrt(p1[c]*p1[c] + p2[c]*p2[c])/lambda);
p1[c] /= denom;
p2[c] /= denom;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4dualPfS_PKfddii
.globl _Z4dualPfS_PKfddii
.p2align 8
.type _Z4dualPfS_PKfddii,@function
_Z4dualPfS_PKfddii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[4:5], null, s14, s3, v[1:2]
v_mov_b32_e32 v2, 0
v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_add_i32 s5, s4, -1
s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, v6, s4, v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v5, v4
v_cvt_f64_f32_e32 v[4:5], v4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_load_b32 s5, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v6
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v2, s4, v0
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b32 v8, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], s[6:7], v[8:9]
v_cvt_f32_f64_e32 v4, v[4:5]
global_store_b32 v[6:7], v4, off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[6:7], v[4:5]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
global_load_b32 v14, v[6:7], off
v_mul_f32_e32 v2, v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v14, v14
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v4, v3, v2
v_fma_f32 v9, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v3, v3, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], s[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[12:13]
v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f32_e32 v2, 1.0, v2
v_div_scale_f32 v3, null, v2, v2, v14
v_div_scale_f32 v8, vcc_lo, v14, v2, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v8, v4
v_fma_f32 v9, -v3, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v9, v4
v_fma_f32 v3, -v3, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v5
v_div_fixup_f32 v3, v3, v2, v14
global_store_b32 v[6:7], v3, off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v2, v4, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4dualPfS_PKfddii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4dualPfS_PKfddii, .Lfunc_end0-_Z4dualPfS_PKfddii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4dualPfS_PKfddii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4dualPfS_PKfddii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dual(float* p1, float* p2, const float* u_, const double lambda, const double sigma, const int X, const int Y)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// center point
int c = y*X + x;
float nabla_x = 0.0f;
float nabla_y = 0.0f;
if (x < X-1)
nabla_x = u_[c+1]-u_[c];
if (y < Y-1)
nabla_y = u_[c+X]-u_[c];
//p1[c] = fmaxf(-lambda, fminf(lambda, p1[c] + sigma*nabla_x));
//p2[c] = fmaxf(-lambda, fminf(lambda, p2[c] + sigma*nabla_y));
p1[c] += sigma*nabla_x;
p2[c] += sigma*nabla_y;
float denom = fmaxf(1.0f, sqrt(p1[c]*p1[c] + p2[c]*p2[c])/lambda);
p1[c] /= denom;
p2[c] /= denom;
} | .text
.file "dual.hip"
.globl _Z19__device_stub__dualPfS_PKfddii # -- Begin function _Z19__device_stub__dualPfS_PKfddii
.p2align 4, 0x90
.type _Z19__device_stub__dualPfS_PKfddii,@function
_Z19__device_stub__dualPfS_PKfddii: # @_Z19__device_stub__dualPfS_PKfddii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4dualPfS_PKfddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__dualPfS_PKfddii, .Lfunc_end0-_Z19__device_stub__dualPfS_PKfddii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4dualPfS_PKfddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4dualPfS_PKfddii,@object # @_Z4dualPfS_PKfddii
.section .rodata,"a",@progbits
.globl _Z4dualPfS_PKfddii
.p2align 3, 0x0
_Z4dualPfS_PKfddii:
.quad _Z19__device_stub__dualPfS_PKfddii
.size _Z4dualPfS_PKfddii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4dualPfS_PKfddii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__dualPfS_PKfddii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4dualPfS_PKfddii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017b9ab_00000000-6_dual.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii
.type _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii, @function
_Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4dualPfS_PKfddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii, .-_Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii
.globl _Z4dualPfS_PKfddii
.type _Z4dualPfS_PKfddii, @function
_Z4dualPfS_PKfddii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z4dualPfS_PKfddiiPfS_PKfddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4dualPfS_PKfddii, .-_Z4dualPfS_PKfddii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4dualPfS_PKfddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4dualPfS_PKfddii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dual.hip"
.globl _Z19__device_stub__dualPfS_PKfddii # -- Begin function _Z19__device_stub__dualPfS_PKfddii
.p2align 4, 0x90
.type _Z19__device_stub__dualPfS_PKfddii,@function
_Z19__device_stub__dualPfS_PKfddii: # @_Z19__device_stub__dualPfS_PKfddii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4dualPfS_PKfddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__dualPfS_PKfddii, .Lfunc_end0-_Z19__device_stub__dualPfS_PKfddii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4dualPfS_PKfddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4dualPfS_PKfddii,@object # @_Z4dualPfS_PKfddii
.section .rodata,"a",@progbits
.globl _Z4dualPfS_PKfddii
.p2align 3, 0x0
_Z4dualPfS_PKfddii:
.quad _Z19__device_stub__dualPfS_PKfddii
.size _Z4dualPfS_PKfddii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4dualPfS_PKfddii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__dualPfS_PKfddii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4dualPfS_PKfddii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*******************************************************************************
This program uses streams and events to asynchronously perform arithmetic
functions on the GPU. Comparison of timing is shown as output.
Author: Said Darham
*******************************************************************************/
#include <iostream>
#include <stdlib.h> //srand and rand
#include <math.h>
// Test types
#define THREAD 1
#define STREAM 2
//Timer struct declaration. Using CUDA EVENTS
typedef struct timer{
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
float time_ms;
} timerEvent;
/*******************************************************************************
PROFILER FUNCTIONS USING EVENTS
*******************************************************************************/
void startEventTimer(timerEvent *timer){
/* startEventTimer()
Creates and starts recording an event
*/
cudaEventCreate(&timer->startEvent);
cudaEventCreate(&timer->stopEvent);
cudaEventRecord(timer->startEvent);
}
void stopEventTimer(timerEvent *timer){
/* stopEventTimer()
Stops an event and calculates the elapsed time between start and stop event
*/
cudaEventRecord(timer->stopEvent);
cudaEventSynchronize(timer->stopEvent);
cudaEventElapsedTime(&timer->time_ms, timer->startEvent, timer->stopEvent);
}
void freeEventTimer(timerEvent *timer){
/* freeEventTimer()
cleans up the events
*/
cudaEventDestroy(timer->startEvent);
cudaEventDestroy(timer->stopEvent);
}
void checkDevices(void){
//Check and print devices name
cudaDeviceProp prop;
int deviceCount; //number of devices found
int devId = 0; // default device Id
cudaGetDeviceCount(&deviceCount);
if(deviceCount == 0){
std::cout << "No GPU Device Found\n";
exit(0);
}else if(deviceCount == 1){
cudaSetDevice(devId); //set the device 0 as default
}
std::cout << "Number Of Devices Found: " << deviceCount << std::endl;
//Print device names and some basic associated properties
for (int i = 0; i<deviceCount; i++){
cudaGetDeviceProperties(&prop,i);
std::cout << "Device " << i << " Name: " << prop.name << std::endl;
std::cout << "Compute Capability: " << prop.major << "." << prop.minor << std::endl;
}
}
/*******************************************************************************
ARITHMETIC KERNEL FUNCTIONS
*******************************************************************************/
// Add Function
__global__ void add(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
// subtract function
__global__ void subtract(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
// multiply function
__global__ void mult(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
// Moudulu function
__global__ void mod(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] % b[id];
}
/*******************************************************************************
GPU Test
( Sequential Threads & STREAMS)
*******************************************************************************/
void gpuTest(int numBlocks, int totalThreads, const int testType){
/* gpuTest()
runs either sequential transfer and execute or asynchronous streams
testType is either THREAD or STREAM
*/
//Since both transfer and execute routines will use pinned memory, allocating
//and initializing data is the same for both
// Host input/output vectors
int *h_a, *h_b, *h_c_add,*h_c_sub,*h_c_mult,*h_c_mod;
// Device input/output vectors
int *d_a, *d_b, *d_c_add,*d_c_sub,*d_c_mult,*d_c_mod;
// Size, in bytes, of each vector
const unsigned int bytes = totalThreads*sizeof(int);
// Allocate memory for each vector on host Pinned
cudaMallocHost((void**)&h_a, bytes);
cudaMallocHost((void**)&h_b, bytes);
cudaMallocHost((void**)&h_c_add, bytes);
cudaMallocHost((void**)&h_c_sub, bytes);
cudaMallocHost((void**)&h_c_mult, bytes);
cudaMallocHost((void**)&h_c_mod, bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c_add, bytes);
cudaMalloc(&d_c_sub, bytes);
cudaMalloc(&d_c_mult, bytes);
cudaMalloc(&d_c_mod, bytes);
//initialize the input vectors
for(int i = 0;i<totalThreads;i++){
//first array is 0 through number of threads
h_a[i] = i;
// second array is a random number between 0 and 3
h_b[i] = rand() % 4;
}
// create a struct which will contain info for timing using events
timerEvent timer;
switch(testType){
case THREAD:
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Sequential*****" << std::endl;
//Transfer and Profile data from host to device and profile using EVENTS
startEventTimer(&timer);
cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy( d_b, h_b, bytes, cudaMemcpyHostToDevice);
//Execute the kernel arithmetic functions
add<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_add, totalThreads);
subtract<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_sub, totalThreads);
mult<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mult, totalThreads);
mod<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mod, totalThreads);
//Transfer data from device to host
cudaMemcpy(h_c_add, d_c_add, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_sub, d_c_sub, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_mult, d_c_mult, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_mod, d_c_mod, bytes, cudaMemcpyDeviceToHost);
stopEventTimer(&timer);
std::cout << "Time Elaplsed For Sequential Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
case STREAM:
{
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n";
//choose 4 streams for four kernels
int nStreams = 4;
int iStream; //
//create four asynchronous streams
cudaStream_t stream[nStreams];
for(iStream = 0; iStream < nStreams; iStream++)
cudaStreamCreate(&stream[iStream]);
//Copy data from host to device and profile using EVENTS
startEventTimer(&timer);
for(iStream = 0; iStream < nStreams; iStream++ ){
cudaMemcpyAsync(d_a, h_a, bytes, cudaMemcpyHostToDevice, stream[iStream]);
cudaMemcpyAsync(d_b, h_b, bytes, cudaMemcpyHostToDevice, stream[iStream]);
}
add<<<numBlocks, totalThreads, 0, stream[0]>>>(d_a, d_b, d_c_add, totalThreads);
cudaMemcpyAsync(h_c_add, d_c_add, bytes, cudaMemcpyDeviceToHost, stream[0]);
//performing subtract function
subtract<<<numBlocks, totalThreads, 0, stream[1]>>>(d_a, d_b, d_c_sub, totalThreads);
cudaMemcpyAsync(h_c_sub, d_c_sub, bytes, cudaMemcpyDeviceToHost, stream[1]);
//performing mult function
mult<<<numBlocks, totalThreads, 0, stream[2]>>>(d_a, d_b, d_c_mult, totalThreads);
cudaMemcpyAsync(h_c_mult, d_c_mult, bytes, cudaMemcpyDeviceToHost, stream[2]);
//performing mod fuction
mod<<<numBlocks, totalThreads, 0, stream[3]>>>(d_a, d_b, d_c_mod, totalThreads);
cudaMemcpyAsync(h_c_mod, d_c_mod, bytes, cudaMemcpyDeviceToHost, stream[2]);
//Wait till all tasks referenced to streams are finished
for(iStream = 0; iStream < nStreams; iStream++)
cudaStreamSynchronize(stream[iStream]);
stopEventTimer(&timer);
std::cout << "TIME ELAPSED For Asynchronous Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
}
default:
std::cout << "Unknown Test Type!\n";
break;
}
//destroy Event timer
freeEventTimer(&timer);
//free up space on our GPU
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c_add);
cudaFree(d_c_sub);
cudaFree(d_c_mult);
cudaFree(d_c_add);
//free up space on our CPU use cudaFreeHost since pinnned
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c_add);
cudaFreeHost(h_c_sub);
cudaFreeHost(h_c_mult);
cudaFreeHost(h_c_mod);
}
/*******************************************************************************
MAIN
*******************************************************************************/
int main(int argc, char** argv)
{
int totalThreads = (1 << 10);
int blockSize = 256;
//User wants to run the Global vs Pinned Examples
if( argc > 2 && argc < 4){
// Ensure the user supplies both number of threads and block size
// otherwise use default values
totalThreads = atoi(argv[1]);
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
std::cout << "\nUsing " << totalThreads << " Threads and " << blockSize << " BlockSize\n" ;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
std::cout << "Warning: Total thread count is not evenly divisible by the block size\n";
std::cout << "The total number of threads will be rounded up to %d\n";
}
// get number of devices and print some basic properties
checkDevices();
//perform Sequential transfer and execute Test
gpuTest( totalThreads, numBlocks, THREAD);
//perform asynchronous transfer and execute using streams
gpuTest( totalThreads, numBlocks, STREAM);
return 0;
} | code for sm_80
Function : _Z3modPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000e2000c1e1900 */
/*00c0*/ IABS R10, R4.reuse ; /* 0x00000004000a7213 */
/* 0x084fe40000000000 */
/*00d0*/ IABS R12, R4 ; /* 0x00000004000c7213 */
/* 0x000fe40000000000 */
/*00e0*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e660000209400 */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R12 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0a0c */
/*0100*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x008fc80003f46270 */
/*0110*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e240000001000 */
/*0120*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe40007ffe0ff */
/*0130*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fc80000000000 */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0150*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0160*/ IADD3 R11, RZ, -R7, RZ ; /* 0x80000007ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0170*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0190*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R7, R7, R3, R8 ; /* 0x0000000307077224 */
/* 0x000fe400078e0208 */
/*01b0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0209 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0a */
/*01e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R7, R7, -R10, RZ ; /* 0x8000000a07079210 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0220*/ @!P0 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff078212 */
/* 0x000fca00078e33ff */
/*0230*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4multPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8subtractPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, -R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe1ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*******************************************************************************
This program uses streams and events to asynchronously perform arithmetic
functions on the GPU. Comparison of timing is shown as output.
Author: Said Darham
*******************************************************************************/
#include <iostream>
#include <stdlib.h> //srand and rand
#include <math.h>
// Test types
#define THREAD 1
#define STREAM 2
//Timer struct declaration. Using CUDA EVENTS
typedef struct timer{
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
float time_ms;
} timerEvent;
/*******************************************************************************
PROFILER FUNCTIONS USING EVENTS
*******************************************************************************/
void startEventTimer(timerEvent *timer){
/* startEventTimer()
Creates and starts recording an event
*/
cudaEventCreate(&timer->startEvent);
cudaEventCreate(&timer->stopEvent);
cudaEventRecord(timer->startEvent);
}
void stopEventTimer(timerEvent *timer){
/* stopEventTimer()
Stops an event and calculates the elapsed time between start and stop event
*/
cudaEventRecord(timer->stopEvent);
cudaEventSynchronize(timer->stopEvent);
cudaEventElapsedTime(&timer->time_ms, timer->startEvent, timer->stopEvent);
}
void freeEventTimer(timerEvent *timer){
/* freeEventTimer()
cleans up the events
*/
cudaEventDestroy(timer->startEvent);
cudaEventDestroy(timer->stopEvent);
}
void checkDevices(void){
//Check and print devices name
cudaDeviceProp prop;
int deviceCount; //number of devices found
int devId = 0; // default device Id
cudaGetDeviceCount(&deviceCount);
if(deviceCount == 0){
std::cout << "No GPU Device Found\n";
exit(0);
}else if(deviceCount == 1){
cudaSetDevice(devId); //set the device 0 as default
}
std::cout << "Number Of Devices Found: " << deviceCount << std::endl;
//Print device names and some basic associated properties
for (int i = 0; i<deviceCount; i++){
cudaGetDeviceProperties(&prop,i);
std::cout << "Device " << i << " Name: " << prop.name << std::endl;
std::cout << "Compute Capability: " << prop.major << "." << prop.minor << std::endl;
}
}
/*******************************************************************************
ARITHMETIC KERNEL FUNCTIONS
*******************************************************************************/
// Add Function
__global__ void add(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
// subtract function
__global__ void subtract(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
// multiply function
__global__ void mult(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
// Moudulu function
__global__ void mod(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] % b[id];
}
/*******************************************************************************
GPU Test
( Sequential Threads & STREAMS)
*******************************************************************************/
void gpuTest(int numBlocks, int totalThreads, const int testType){
/* gpuTest()
runs either sequential transfer and execute or asynchronous streams
testType is either THREAD or STREAM
*/
//Since both transfer and execute routines will use pinned memory, allocating
//and initializing data is the same for both
// Host input/output vectors
int *h_a, *h_b, *h_c_add,*h_c_sub,*h_c_mult,*h_c_mod;
// Device input/output vectors
int *d_a, *d_b, *d_c_add,*d_c_sub,*d_c_mult,*d_c_mod;
// Size, in bytes, of each vector
const unsigned int bytes = totalThreads*sizeof(int);
// Allocate memory for each vector on host Pinned
cudaMallocHost((void**)&h_a, bytes);
cudaMallocHost((void**)&h_b, bytes);
cudaMallocHost((void**)&h_c_add, bytes);
cudaMallocHost((void**)&h_c_sub, bytes);
cudaMallocHost((void**)&h_c_mult, bytes);
cudaMallocHost((void**)&h_c_mod, bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c_add, bytes);
cudaMalloc(&d_c_sub, bytes);
cudaMalloc(&d_c_mult, bytes);
cudaMalloc(&d_c_mod, bytes);
//initialize the input vectors
for(int i = 0;i<totalThreads;i++){
//first array is 0 through number of threads
h_a[i] = i;
// second array is a random number between 0 and 3
h_b[i] = rand() % 4;
}
// create a struct which will contain info for timing using events
timerEvent timer;
switch(testType){
case THREAD:
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Sequential*****" << std::endl;
//Transfer and Profile data from host to device and profile using EVENTS
startEventTimer(&timer);
cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy( d_b, h_b, bytes, cudaMemcpyHostToDevice);
//Execute the kernel arithmetic functions
add<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_add, totalThreads);
subtract<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_sub, totalThreads);
mult<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mult, totalThreads);
mod<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mod, totalThreads);
//Transfer data from device to host
cudaMemcpy(h_c_add, d_c_add, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_sub, d_c_sub, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_mult, d_c_mult, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_mod, d_c_mod, bytes, cudaMemcpyDeviceToHost);
stopEventTimer(&timer);
std::cout << "Time Elaplsed For Sequential Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
case STREAM:
{
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n";
//choose 4 streams for four kernels
int nStreams = 4;
int iStream; //
//create four asynchronous streams
cudaStream_t stream[nStreams];
for(iStream = 0; iStream < nStreams; iStream++)
cudaStreamCreate(&stream[iStream]);
//Copy data from host to device and profile using EVENTS
startEventTimer(&timer);
for(iStream = 0; iStream < nStreams; iStream++ ){
cudaMemcpyAsync(d_a, h_a, bytes, cudaMemcpyHostToDevice, stream[iStream]);
cudaMemcpyAsync(d_b, h_b, bytes, cudaMemcpyHostToDevice, stream[iStream]);
}
add<<<numBlocks, totalThreads, 0, stream[0]>>>(d_a, d_b, d_c_add, totalThreads);
cudaMemcpyAsync(h_c_add, d_c_add, bytes, cudaMemcpyDeviceToHost, stream[0]);
//performing subtract function
subtract<<<numBlocks, totalThreads, 0, stream[1]>>>(d_a, d_b, d_c_sub, totalThreads);
cudaMemcpyAsync(h_c_sub, d_c_sub, bytes, cudaMemcpyDeviceToHost, stream[1]);
//performing mult function
mult<<<numBlocks, totalThreads, 0, stream[2]>>>(d_a, d_b, d_c_mult, totalThreads);
cudaMemcpyAsync(h_c_mult, d_c_mult, bytes, cudaMemcpyDeviceToHost, stream[2]);
//performing mod fuction
mod<<<numBlocks, totalThreads, 0, stream[3]>>>(d_a, d_b, d_c_mod, totalThreads);
cudaMemcpyAsync(h_c_mod, d_c_mod, bytes, cudaMemcpyDeviceToHost, stream[2]);
//Wait till all tasks referenced to streams are finished
for(iStream = 0; iStream < nStreams; iStream++)
cudaStreamSynchronize(stream[iStream]);
stopEventTimer(&timer);
std::cout << "TIME ELAPSED For Asynchronous Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
}
default:
std::cout << "Unknown Test Type!\n";
break;
}
//destroy Event timer
freeEventTimer(&timer);
//free up space on our GPU
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c_add);
cudaFree(d_c_sub);
cudaFree(d_c_mult);
cudaFree(d_c_add);
//free up space on our CPU use cudaFreeHost since pinnned
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c_add);
cudaFreeHost(h_c_sub);
cudaFreeHost(h_c_mult);
cudaFreeHost(h_c_mod);
}
/*******************************************************************************
MAIN
*******************************************************************************/
int main(int argc, char** argv)
{
int totalThreads = (1 << 10);
int blockSize = 256;
//User wants to run the Global vs Pinned Examples
if( argc > 2 && argc < 4){
// Ensure the user supplies both number of threads and block size
// otherwise use default values
totalThreads = atoi(argv[1]);
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
std::cout << "\nUsing " << totalThreads << " Threads and " << blockSize << " BlockSize\n" ;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
std::cout << "Warning: Total thread count is not evenly divisible by the block size\n";
std::cout << "The total number of threads will be rounded up to %d\n";
}
// get number of devices and print some basic properties
checkDevices();
//perform Sequential transfer and execute Test
gpuTest( totalThreads, numBlocks, THREAD);
//perform asynchronous transfer and execute using streams
gpuTest( totalThreads, numBlocks, STREAM);
return 0;
} | .file "tmpxft_0018079b_00000000-6_assignment7.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15startEventTimerP5timer
.type _Z15startEventTimerP5timer, @function
_Z15startEventTimerP5timer:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaEventCreate@PLT
leaq 8(%rbx), %rdi
call cudaEventCreate@PLT
movq (%rbx), %rdi
movl $0, %esi
call cudaEventRecord@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z15startEventTimerP5timer, .-_Z15startEventTimerP5timer
.globl _Z14stopEventTimerP5timer
.type _Z14stopEventTimerP5timer, @function
_Z14stopEventTimerP5timer:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
movl $0, %esi
call cudaEventRecord@PLT
movq 8(%rbx), %rdi
call cudaEventSynchronize@PLT
movq 8(%rbx), %rdx
movq (%rbx), %rsi
leaq 16(%rbx), %rdi
call cudaEventElapsedTime@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z14stopEventTimerP5timer, .-_Z14stopEventTimerP5timer
.globl _Z14freeEventTimerP5timer
.type _Z14freeEventTimerP5timer, @function
_Z14freeEventTimerP5timer:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call cudaEventDestroy@PLT
movq 8(%rbx), %rdi
call cudaEventDestroy@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z14freeEventTimerP5timer, .-_Z14freeEventTimerP5timer
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "No GPU Device Found\n"
.LC1:
.string "Number Of Devices Found: "
.LC2:
.string "Device "
.LC3:
.string " Name: "
.LC4:
.string "Compute Capability: "
.LC5:
.string "."
.text
.globl _Z12checkDevicesv
.type _Z12checkDevicesv, @function
_Z12checkDevicesv:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L29
cmpl $1, %eax
je .L30
.L11:
movl $25, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 12(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L31
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl $0, 12(%rsp)
jle .L9
movl $0, %ebp
leaq .LC2(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %r13
jmp .L25
.L29:
movl $20, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %edi
call exit@PLT
.L30:
movl $0, %edi
call cudaSetDevice@PLT
jmp .L11
.L31:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L35:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L33
call _ZSt16__throw_bad_castv@PLT
.L33:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L36:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L24:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L9
.L25:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $7, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L35
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $20, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L36
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
jmp .L24
.L9:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z12checkDevicesv, .-_Z12checkDevicesv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.globl _Z32__device_stub__Z8subtractPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8subtractPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8subtractPiS_S_iPiS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8subtractPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z32__device_stub__Z8subtractPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8subtractPiS_S_iPiS_S_i
.globl _Z8subtractPiS_S_i
.type _Z8subtractPiS_S_i, @function
_Z8subtractPiS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8subtractPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z8subtractPiS_S_i, .-_Z8subtractPiS_S_i
.globl _Z28__device_stub__Z4multPiS_S_iPiS_S_i
.type _Z28__device_stub__Z4multPiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4multPiS_S_iPiS_S_i:
.LFB3703:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L58
.L54:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4multPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L54
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z28__device_stub__Z4multPiS_S_iPiS_S_i, .-_Z28__device_stub__Z4multPiS_S_iPiS_S_i
.globl _Z4multPiS_S_i
.type _Z4multPiS_S_i, @function
_Z4multPiS_S_i:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4multPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z4multPiS_S_i, .-_Z4multPiS_S_i
.globl _Z27__device_stub__Z3modPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3modPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3modPiS_S_iPiS_S_i:
.LFB3705:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L66
.L62:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3modPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L62
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z27__device_stub__Z3modPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3modPiS_S_iPiS_S_i
.globl _Z3modPiS_S_i
.type _Z3modPiS_S_i, @function
_Z3modPiS_S_i:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3modPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z3modPiS_S_i, .-_Z3modPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "\n\t\t*****Executing Arithmetic Functions Using Sequential*****"
.align 8
.LC7:
.string "Time Elaplsed For Sequential Transfer and Execute: "
.section .rodata.str1.1
.LC8:
.string " ms"
.section .rodata.str1.8
.align 8
.LC9:
.string "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n"
.align 8
.LC10:
.string "TIME ELAPSED For Asynchronous Transfer and Execute: "
.section .rodata.str1.1
.LC11:
.string "Unknown Test Type!\n"
.text
.globl _Z7gpuTestiii
.type _Z7gpuTestiii, @function
_Z7gpuTestiii:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $200, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, %r14d
movl %esi, %r12d
movl %edx, -216(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movslq %esi, %r15
leal 0(,%r12,4), %ebx
leaq -200(%rbp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq -192(%rbp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq -184(%rbp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq -176(%rbp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq -168(%rbp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq -160(%rbp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq -152(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -144(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -136(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -128(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -120(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
jle .L71
movl $0, %r13d
.L72:
movq -200(%rbp), %rax
movl %r13d, (%rax,%r13,4)
call rand@PLT
cltd
shrl $30, %edx
addl %edx, %eax
andl $3, %eax
subl %edx, %eax
movq -192(%rbp), %rdx
movl %eax, (%rdx,%r13,4)
addq $1, %r13
cmpq %r13, %r15
jne .L72
.L71:
movl -216(%rbp), %eax
cmpl $1, %eax
je .L73
cmpl $2, %eax
je .L74
movl $19, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L88:
leaq -80(%rbp), %rdi
call _Z14freeEventTimerP5timer
movq -152(%rbp), %rdi
call cudaFree@PLT
movq -144(%rbp), %rdi
call cudaFree@PLT
movq -136(%rbp), %rdi
call cudaFree@PLT
movq -128(%rbp), %rdi
call cudaFree@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -136(%rbp), %rdi
call cudaFree@PLT
movq -200(%rbp), %rdi
call cudaFreeHost@PLT
movq -192(%rbp), %rdi
call cudaFreeHost@PLT
movq -184(%rbp), %rdi
call cudaFreeHost@PLT
movq -176(%rbp), %rdi
call cudaFreeHost@PLT
movq -168(%rbp), %rdi
call cudaFreeHost@PLT
movq -160(%rbp), %rdi
call cudaFreeHost@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L108
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L73:
.cfi_restore_state
movl $60, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r13
testq %r13, %r13
je .L109
cmpb $0, 56(%r13)
je .L78
movzbl 67(%r13), %esi
.L79:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq -80(%rbp), %rdi
call _Z15startEventTimerP5timer
movl $1, %ecx
movq %rbx, %rdx
movq -200(%rbp), %rsi
movq -152(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -192(%rbp), %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L110
.L80:
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L111
.L81:
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L112
.L82:
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L113
.L83:
movl $2, %ecx
movq %rbx, %rdx
movq -136(%rbp), %rsi
movq -184(%rbp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -128(%rbp), %rsi
movq -176(%rbp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -120(%rbp), %rsi
movq -168(%rbp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -112(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
leaq -80(%rbp), %rdi
call _Z14stopEventTimerP5timer
movl $51, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd -64(%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L114
cmpb $0, 56(%r12)
je .L86
movzbl 67(%r12), %esi
.L87:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L88
.L109:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L115
call _ZSt16__throw_bad_castv@PLT
.L115:
call __stack_chk_fail@PLT
.L78:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L79
.L110:
movl %r12d, %ecx
movq -136(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L80
.L111:
movl %r12d, %ecx
movq -128(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z32__device_stub__Z8subtractPiS_S_iPiS_S_i
jmp .L81
.L112:
movl %r12d, %ecx
movq -120(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z28__device_stub__Z4multPiS_S_iPiS_S_i
jmp .L82
.L113:
movl %r12d, %ecx
movq -112(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z27__device_stub__Z3modPiS_S_iPiS_S_i
jmp .L83
.L114:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L116
call _ZSt16__throw_bad_castv@PLT
.L116:
call __stack_chk_fail@PLT
.L86:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L87
.L74:
movq %rsp, -232(%rbp)
movl $58, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rsp, %rax
.L89:
cmpq %rax, %rsp
je .L90
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L89
.L90:
subq $32, %rsp
orq $0, 24(%rsp)
leaq 7(%rsp), %rax
movq %rax, %rcx
shrq $3, %rcx
movq %rcx, -224(%rbp)
andq $-8, %rax
movq %rax, %r13
movq %rax, %rdi
call cudaStreamCreate@PLT
leaq 8(%r13), %rdi
call cudaStreamCreate@PLT
leaq 16(%r13), %rdi
call cudaStreamCreate@PLT
leaq 24(%r13), %rdi
call cudaStreamCreate@PLT
leaq -80(%rbp), %rdi
call _Z15startEventTimerP5timer
movq %r13, %r15
leaq 32(%r13), %rax
movq %rax, -216(%rbp)
.L92:
movq 0(%r13), %r8
movl $1, %ecx
movq %rbx, %rdx
movq -200(%rbp), %rsi
movq -152(%rbp), %rdi
call cudaMemcpyAsync@PLT
movq 0(%r13), %r8
movl $1, %ecx
movq %rbx, %rdx
movq -192(%rbp), %rsi
movq -144(%rbp), %rdi
call cudaMemcpyAsync@PLT
addq $8, %r13
cmpq %r13, -216(%rbp)
jne .L92
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movq -224(%rbp), %rax
movq 0(,%rax,8), %r9
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L117
.L93:
movq -224(%rbp), %r13
movq 0(,%r13,8), %r8
movl $2, %ecx
movq %rbx, %rdx
movq -136(%rbp), %rsi
movq -184(%rbp), %rdi
call cudaMemcpyAsync@PLT
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movq 8(,%r13,8), %r9
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L118
.L94:
movq -224(%rbp), %r13
movq 8(,%r13,8), %r8
movl $2, %ecx
movq %rbx, %rdx
movq -128(%rbp), %rsi
movq -176(%rbp), %rdi
call cudaMemcpyAsync@PLT
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movq 16(,%r13,8), %r9
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L119
.L95:
movq -224(%rbp), %r13
movq 16(,%r13,8), %r8
movl $2, %ecx
movq %rbx, %rdx
movq -120(%rbp), %rsi
movq -168(%rbp), %rdi
call cudaMemcpyAsync@PLT
movl %r12d, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r14d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movq 24(,%r13,8), %r9
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L120
.L96:
movq -224(%rbp), %rax
movq 16(,%rax,8), %r8
movl $2, %ecx
movq %rbx, %rdx
movq -112(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpyAsync@PLT
.L97:
movq (%r15), %rdi
call cudaStreamSynchronize@PLT
addq $8, %r15
movq -216(%rbp), %rax
cmpq %rax, %r15
jne .L97
leaq -80(%rbp), %rdi
call _Z14stopEventTimerP5timer
movl $52, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd -64(%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L121
cmpb $0, 56(%r12)
je .L100
movzbl 67(%r12), %esi
.L101:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq -232(%rbp), %rsp
jmp .L88
.L117:
movl %r12d, %ecx
movq -136(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L93
.L118:
movl %r12d, %ecx
movq -128(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z32__device_stub__Z8subtractPiS_S_iPiS_S_i
jmp .L94
.L119:
movl %r12d, %ecx
movq -120(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z28__device_stub__Z4multPiS_S_iPiS_S_i
jmp .L95
.L120:
movl %r12d, %ecx
movq -112(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z27__device_stub__Z3modPiS_S_iPiS_S_i
jmp .L96
.L121:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L122
call _ZSt16__throw_bad_castv@PLT
.L122:
call __stack_chk_fail@PLT
.L100:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L101
.L108:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size _Z7gpuTestiii, .-_Z7gpuTestiii
.section .rodata.str1.1
.LC12:
.string "\nUsing "
.LC13:
.string " Threads and "
.LC14:
.string " BlockSize\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Warning: Total thread count is not evenly divisible by the block size\n"
.align 8
.LC16:
.string "The total number of threads will be rounded up to %d\n"
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
cmpl $3, %edi
je .L128
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $256, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $4, %ebp
movl $1024, %ebx
.L125:
call _Z12checkDevicesv
movl $1, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z7gpuTestiii
movl $2, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z7gpuTestiii
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L128:
.cfi_restore_state
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %ebx, %eax
cltd
idivl %r12d
movl %edx, %r14d
movl %eax, %r13d
movl %eax, %ebp
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
testl %r14d, %r14d
je .L125
leal 1(%r13), %ebp
movl %r12d, %ebx
imull %ebp, %ebx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC16(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L125
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z3modPiS_S_i"
.LC18:
.string "_Z4multPiS_S_i"
.LC19:
.string "_Z8subtractPiS_S_i"
.LC20:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3708:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z3modPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z4multPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8subtractPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*******************************************************************************
This program uses streams and events to asynchronously perform arithmetic
functions on the GPU. Comparison of timing is shown as output.
Author: Said Darham
*******************************************************************************/
#include <iostream>
#include <stdlib.h> //srand and rand
#include <math.h>
// Test types
#define THREAD 1
#define STREAM 2
//Timer struct declaration. Using CUDA EVENTS
typedef struct timer{
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
float time_ms;
} timerEvent;
/*******************************************************************************
PROFILER FUNCTIONS USING EVENTS
*******************************************************************************/
void startEventTimer(timerEvent *timer){
/* startEventTimer()
Creates and starts recording an event
*/
cudaEventCreate(&timer->startEvent);
cudaEventCreate(&timer->stopEvent);
cudaEventRecord(timer->startEvent);
}
void stopEventTimer(timerEvent *timer){
/* stopEventTimer()
Stops an event and calculates the elapsed time between start and stop event
*/
cudaEventRecord(timer->stopEvent);
cudaEventSynchronize(timer->stopEvent);
cudaEventElapsedTime(&timer->time_ms, timer->startEvent, timer->stopEvent);
}
void freeEventTimer(timerEvent *timer){
/* freeEventTimer()
cleans up the events
*/
cudaEventDestroy(timer->startEvent);
cudaEventDestroy(timer->stopEvent);
}
void checkDevices(void){
//Check and print devices name
cudaDeviceProp prop;
int deviceCount; //number of devices found
int devId = 0; // default device Id
cudaGetDeviceCount(&deviceCount);
if(deviceCount == 0){
std::cout << "No GPU Device Found\n";
exit(0);
}else if(deviceCount == 1){
cudaSetDevice(devId); //set the device 0 as default
}
std::cout << "Number Of Devices Found: " << deviceCount << std::endl;
//Print device names and some basic associated properties
for (int i = 0; i<deviceCount; i++){
cudaGetDeviceProperties(&prop,i);
std::cout << "Device " << i << " Name: " << prop.name << std::endl;
std::cout << "Compute Capability: " << prop.major << "." << prop.minor << std::endl;
}
}
/*******************************************************************************
ARITHMETIC KERNEL FUNCTIONS
*******************************************************************************/
// Add Function
__global__ void add(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
// subtract function
__global__ void subtract(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
// multiply function
__global__ void mult(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
// Moudulu function
__global__ void mod(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] % b[id];
}
/*******************************************************************************
GPU Test
( Sequential Threads & STREAMS)
*******************************************************************************/
void gpuTest(int numBlocks, int totalThreads, const int testType){
/* gpuTest()
runs either sequential transfer and execute or asynchronous streams
testType is either THREAD or STREAM
*/
//Since both transfer and execute routines will use pinned memory, allocating
//and initializing data is the same for both
// Host input/output vectors
int *h_a, *h_b, *h_c_add,*h_c_sub,*h_c_mult,*h_c_mod;
// Device input/output vectors
int *d_a, *d_b, *d_c_add,*d_c_sub,*d_c_mult,*d_c_mod;
// Size, in bytes, of each vector
const unsigned int bytes = totalThreads*sizeof(int);
// Allocate memory for each vector on host Pinned
cudaMallocHost((void**)&h_a, bytes);
cudaMallocHost((void**)&h_b, bytes);
cudaMallocHost((void**)&h_c_add, bytes);
cudaMallocHost((void**)&h_c_sub, bytes);
cudaMallocHost((void**)&h_c_mult, bytes);
cudaMallocHost((void**)&h_c_mod, bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c_add, bytes);
cudaMalloc(&d_c_sub, bytes);
cudaMalloc(&d_c_mult, bytes);
cudaMalloc(&d_c_mod, bytes);
//initialize the input vectors
for(int i = 0;i<totalThreads;i++){
//first array is 0 through number of threads
h_a[i] = i;
// second array is a random number between 0 and 3
h_b[i] = rand() % 4;
}
// create a struct which will contain info for timing using events
timerEvent timer;
switch(testType){
case THREAD:
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Sequential*****" << std::endl;
//Transfer and Profile data from host to device and profile using EVENTS
startEventTimer(&timer);
cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy( d_b, h_b, bytes, cudaMemcpyHostToDevice);
//Execute the kernel arithmetic functions
add<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_add, totalThreads);
subtract<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_sub, totalThreads);
mult<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mult, totalThreads);
mod<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mod, totalThreads);
//Transfer data from device to host
cudaMemcpy(h_c_add, d_c_add, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_sub, d_c_sub, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_mult, d_c_mult, bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c_mod, d_c_mod, bytes, cudaMemcpyDeviceToHost);
stopEventTimer(&timer);
std::cout << "Time Elaplsed For Sequential Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
case STREAM:
{
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n";
//choose 4 streams for four kernels
int nStreams = 4;
int iStream; //
//create four asynchronous streams
cudaStream_t stream[nStreams];
for(iStream = 0; iStream < nStreams; iStream++)
cudaStreamCreate(&stream[iStream]);
//Copy data from host to device and profile using EVENTS
startEventTimer(&timer);
for(iStream = 0; iStream < nStreams; iStream++ ){
cudaMemcpyAsync(d_a, h_a, bytes, cudaMemcpyHostToDevice, stream[iStream]);
cudaMemcpyAsync(d_b, h_b, bytes, cudaMemcpyHostToDevice, stream[iStream]);
}
add<<<numBlocks, totalThreads, 0, stream[0]>>>(d_a, d_b, d_c_add, totalThreads);
cudaMemcpyAsync(h_c_add, d_c_add, bytes, cudaMemcpyDeviceToHost, stream[0]);
//performing subtract function
subtract<<<numBlocks, totalThreads, 0, stream[1]>>>(d_a, d_b, d_c_sub, totalThreads);
cudaMemcpyAsync(h_c_sub, d_c_sub, bytes, cudaMemcpyDeviceToHost, stream[1]);
//performing mult function
mult<<<numBlocks, totalThreads, 0, stream[2]>>>(d_a, d_b, d_c_mult, totalThreads);
cudaMemcpyAsync(h_c_mult, d_c_mult, bytes, cudaMemcpyDeviceToHost, stream[2]);
//performing mod fuction
mod<<<numBlocks, totalThreads, 0, stream[3]>>>(d_a, d_b, d_c_mod, totalThreads);
cudaMemcpyAsync(h_c_mod, d_c_mod, bytes, cudaMemcpyDeviceToHost, stream[2]);
//Wait till all tasks referenced to streams are finished
for(iStream = 0; iStream < nStreams; iStream++)
cudaStreamSynchronize(stream[iStream]);
stopEventTimer(&timer);
std::cout << "TIME ELAPSED For Asynchronous Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
}
default:
std::cout << "Unknown Test Type!\n";
break;
}
//destroy Event timer
freeEventTimer(&timer);
//free up space on our GPU
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c_add);
cudaFree(d_c_sub);
cudaFree(d_c_mult);
cudaFree(d_c_add);
//free up space on our CPU use cudaFreeHost since pinnned
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c_add);
cudaFreeHost(h_c_sub);
cudaFreeHost(h_c_mult);
cudaFreeHost(h_c_mod);
}
/*******************************************************************************
MAIN
*******************************************************************************/
int main(int argc, char** argv)
{
int totalThreads = (1 << 10);
int blockSize = 256;
//User wants to run the Global vs Pinned Examples
if( argc > 2 && argc < 4){
// Ensure the user supplies both number of threads and block size
// otherwise use default values
totalThreads = atoi(argv[1]);
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
std::cout << "\nUsing " << totalThreads << " Threads and " << blockSize << " BlockSize\n" ;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
std::cout << "Warning: Total thread count is not evenly divisible by the block size\n";
std::cout << "The total number of threads will be rounded up to %d\n";
}
// get number of devices and print some basic properties
checkDevices();
//perform Sequential transfer and execute Test
gpuTest( totalThreads, numBlocks, THREAD);
//perform asynchronous transfer and execute using streams
gpuTest( totalThreads, numBlocks, STREAM);
return 0;
} | /*******************************************************************************
This program uses streams and events to asynchronously perform arithmetic
functions on the GPU. Comparison of timing is shown as output.
Author: Said Darham
*******************************************************************************/
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h> //srand and rand
#include <math.h>
// Test types
#define THREAD 1
#define STREAM 2
//Timer struct declaration. Using CUDA EVENTS
typedef struct timer{
hipEvent_t startEvent;
hipEvent_t stopEvent;
float time_ms;
} timerEvent;
/*******************************************************************************
PROFILER FUNCTIONS USING EVENTS
*******************************************************************************/
void startEventTimer(timerEvent *timer){
/* startEventTimer()
Creates and starts recording an event
*/
hipEventCreate(&timer->startEvent);
hipEventCreate(&timer->stopEvent);
hipEventRecord(timer->startEvent);
}
void stopEventTimer(timerEvent *timer){
/* stopEventTimer()
Stops an event and calculates the elapsed time between start and stop event
*/
hipEventRecord(timer->stopEvent);
hipEventSynchronize(timer->stopEvent);
hipEventElapsedTime(&timer->time_ms, timer->startEvent, timer->stopEvent);
}
void freeEventTimer(timerEvent *timer){
/* freeEventTimer()
cleans up the events
*/
hipEventDestroy(timer->startEvent);
hipEventDestroy(timer->stopEvent);
}
void checkDevices(void){
//Check and print devices name
hipDeviceProp_t prop;
int deviceCount; //number of devices found
int devId = 0; // default device Id
hipGetDeviceCount(&deviceCount);
if(deviceCount == 0){
std::cout << "No GPU Device Found\n";
exit(0);
}else if(deviceCount == 1){
hipSetDevice(devId); //set the device 0 as default
}
std::cout << "Number Of Devices Found: " << deviceCount << std::endl;
//Print device names and some basic associated properties
for (int i = 0; i<deviceCount; i++){
hipGetDeviceProperties(&prop,i);
std::cout << "Device " << i << " Name: " << prop.name << std::endl;
std::cout << "Compute Capability: " << prop.major << "." << prop.minor << std::endl;
}
}
/*******************************************************************************
ARITHMETIC KERNEL FUNCTIONS
*******************************************************************************/
// Add Function
__global__ void add(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
// subtract function
__global__ void subtract(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
// multiply function
__global__ void mult(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
// Moudulu function
__global__ void mod(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] % b[id];
}
/*******************************************************************************
GPU Test
( Sequential Threads & STREAMS)
*******************************************************************************/
void gpuTest(int numBlocks, int totalThreads, const int testType){
/* gpuTest()
runs either sequential transfer and execute or asynchronous streams
testType is either THREAD or STREAM
*/
//Since both transfer and execute routines will use pinned memory, allocating
//and initializing data is the same for both
// Host input/output vectors
int *h_a, *h_b, *h_c_add,*h_c_sub,*h_c_mult,*h_c_mod;
// Device input/output vectors
int *d_a, *d_b, *d_c_add,*d_c_sub,*d_c_mult,*d_c_mod;
// Size, in bytes, of each vector
const unsigned int bytes = totalThreads*sizeof(int);
// Allocate memory for each vector on host Pinned
hipHostMalloc((void**)&h_a, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_b, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_add, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_sub, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_mult, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_mod, bytes, hipHostMallocDefault);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c_add, bytes);
hipMalloc(&d_c_sub, bytes);
hipMalloc(&d_c_mult, bytes);
hipMalloc(&d_c_mod, bytes);
//initialize the input vectors
for(int i = 0;i<totalThreads;i++){
//first array is 0 through number of threads
h_a[i] = i;
// second array is a random number between 0 and 3
h_b[i] = rand() % 4;
}
// create a struct which will contain info for timing using events
timerEvent timer;
switch(testType){
case THREAD:
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Sequential*****" << std::endl;
//Transfer and Profile data from host to device and profile using EVENTS
startEventTimer(&timer);
hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy( d_b, h_b, bytes, hipMemcpyHostToDevice);
//Execute the kernel arithmetic functions
add<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_add, totalThreads);
subtract<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_sub, totalThreads);
mult<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mult, totalThreads);
mod<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mod, totalThreads);
//Transfer data from device to host
hipMemcpy(h_c_add, d_c_add, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_sub, d_c_sub, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_mult, d_c_mult, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_mod, d_c_mod, bytes, hipMemcpyDeviceToHost);
stopEventTimer(&timer);
std::cout << "Time Elaplsed For Sequential Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
case STREAM:
{
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n";
//choose 4 streams for four kernels
int nStreams = 4;
int iStream; //
//create four asynchronous streams
hipStream_t stream[nStreams];
for(iStream = 0; iStream < nStreams; iStream++)
hipStreamCreate(&stream[iStream]);
//Copy data from host to device and profile using EVENTS
startEventTimer(&timer);
for(iStream = 0; iStream < nStreams; iStream++ ){
hipMemcpyAsync(d_a, h_a, bytes, hipMemcpyHostToDevice, stream[iStream]);
hipMemcpyAsync(d_b, h_b, bytes, hipMemcpyHostToDevice, stream[iStream]);
}
add<<<numBlocks, totalThreads, 0, stream[0]>>>(d_a, d_b, d_c_add, totalThreads);
hipMemcpyAsync(h_c_add, d_c_add, bytes, hipMemcpyDeviceToHost, stream[0]);
//performing subtract function
subtract<<<numBlocks, totalThreads, 0, stream[1]>>>(d_a, d_b, d_c_sub, totalThreads);
hipMemcpyAsync(h_c_sub, d_c_sub, bytes, hipMemcpyDeviceToHost, stream[1]);
//performing mult function
mult<<<numBlocks, totalThreads, 0, stream[2]>>>(d_a, d_b, d_c_mult, totalThreads);
hipMemcpyAsync(h_c_mult, d_c_mult, bytes, hipMemcpyDeviceToHost, stream[2]);
//performing mod fuction
mod<<<numBlocks, totalThreads, 0, stream[3]>>>(d_a, d_b, d_c_mod, totalThreads);
hipMemcpyAsync(h_c_mod, d_c_mod, bytes, hipMemcpyDeviceToHost, stream[2]);
//Wait till all tasks referenced to streams are finished
for(iStream = 0; iStream < nStreams; iStream++)
hipStreamSynchronize(stream[iStream]);
stopEventTimer(&timer);
std::cout << "TIME ELAPSED For Asynchronous Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
}
default:
std::cout << "Unknown Test Type!\n";
break;
}
//destroy Event timer
freeEventTimer(&timer);
//free up space on our GPU
hipFree(d_a);
hipFree(d_b);
hipFree(d_c_add);
hipFree(d_c_sub);
hipFree(d_c_mult);
hipFree(d_c_add);
//free up space on our CPU use cudaFreeHost since pinnned
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c_add);
hipHostFree(h_c_sub);
hipHostFree(h_c_mult);
hipHostFree(h_c_mod);
}
/*******************************************************************************
MAIN
*******************************************************************************/
int main(int argc, char** argv)
{
int totalThreads = (1 << 10);
int blockSize = 256;
//User wants to run the Global vs Pinned Examples
if( argc > 2 && argc < 4){
// Ensure the user supplies both number of threads and block size
// otherwise use default values
totalThreads = atoi(argv[1]);
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
std::cout << "\nUsing " << totalThreads << " Threads and " << blockSize << " BlockSize\n" ;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
std::cout << "Warning: Total thread count is not evenly divisible by the block size\n";
std::cout << "The total number of threads will be rounded up to %d\n";
}
// get number of devices and print some basic properties
checkDevices();
//perform Sequential transfer and execute Test
gpuTest( totalThreads, numBlocks, THREAD);
//perform asynchronous transfer and execute using streams
gpuTest( totalThreads, numBlocks, STREAM);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*******************************************************************************
This program uses streams and events to asynchronously perform arithmetic
functions on the GPU. Comparison of timing is shown as output.
Author: Said Darham
*******************************************************************************/
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h> //srand and rand
#include <math.h>
// Test types
#define THREAD 1
#define STREAM 2
//Timer struct declaration. Using CUDA EVENTS
typedef struct timer{
hipEvent_t startEvent;
hipEvent_t stopEvent;
float time_ms;
} timerEvent;
/*******************************************************************************
PROFILER FUNCTIONS USING EVENTS
*******************************************************************************/
void startEventTimer(timerEvent *timer){
/* startEventTimer()
Creates and starts recording an event
*/
hipEventCreate(&timer->startEvent);
hipEventCreate(&timer->stopEvent);
hipEventRecord(timer->startEvent);
}
void stopEventTimer(timerEvent *timer){
/* stopEventTimer()
Stops an event and calculates the elapsed time between start and stop event
*/
hipEventRecord(timer->stopEvent);
hipEventSynchronize(timer->stopEvent);
hipEventElapsedTime(&timer->time_ms, timer->startEvent, timer->stopEvent);
}
void freeEventTimer(timerEvent *timer){
/* freeEventTimer()
cleans up the events
*/
hipEventDestroy(timer->startEvent);
hipEventDestroy(timer->stopEvent);
}
void checkDevices(void){
//Check and print devices name
hipDeviceProp_t prop;
int deviceCount; //number of devices found
int devId = 0; // default device Id
hipGetDeviceCount(&deviceCount);
if(deviceCount == 0){
std::cout << "No GPU Device Found\n";
exit(0);
}else if(deviceCount == 1){
hipSetDevice(devId); //set the device 0 as default
}
std::cout << "Number Of Devices Found: " << deviceCount << std::endl;
//Print device names and some basic associated properties
for (int i = 0; i<deviceCount; i++){
hipGetDeviceProperties(&prop,i);
std::cout << "Device " << i << " Name: " << prop.name << std::endl;
std::cout << "Compute Capability: " << prop.major << "." << prop.minor << std::endl;
}
}
/*******************************************************************************
ARITHMETIC KERNEL FUNCTIONS
*******************************************************************************/
// Add Function
__global__ void add(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
// subtract function
__global__ void subtract(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
// multiply function
__global__ void mult(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
// Moudulu function
__global__ void mod(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] % b[id];
}
/*******************************************************************************
GPU Test
( Sequential Threads & STREAMS)
*******************************************************************************/
void gpuTest(int numBlocks, int totalThreads, const int testType){
/* gpuTest()
runs either sequential transfer and execute or asynchronous streams
testType is either THREAD or STREAM
*/
//Since both transfer and execute routines will use pinned memory, allocating
//and initializing data is the same for both
// Host input/output vectors
int *h_a, *h_b, *h_c_add,*h_c_sub,*h_c_mult,*h_c_mod;
// Device input/output vectors
int *d_a, *d_b, *d_c_add,*d_c_sub,*d_c_mult,*d_c_mod;
// Size, in bytes, of each vector
const unsigned int bytes = totalThreads*sizeof(int);
// Allocate memory for each vector on host Pinned
hipHostMalloc((void**)&h_a, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_b, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_add, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_sub, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_mult, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_mod, bytes, hipHostMallocDefault);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c_add, bytes);
hipMalloc(&d_c_sub, bytes);
hipMalloc(&d_c_mult, bytes);
hipMalloc(&d_c_mod, bytes);
//initialize the input vectors
for(int i = 0;i<totalThreads;i++){
//first array is 0 through number of threads
h_a[i] = i;
// second array is a random number between 0 and 3
h_b[i] = rand() % 4;
}
// create a struct which will contain info for timing using events
timerEvent timer;
switch(testType){
case THREAD:
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Sequential*****" << std::endl;
//Transfer and Profile data from host to device and profile using EVENTS
startEventTimer(&timer);
hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy( d_b, h_b, bytes, hipMemcpyHostToDevice);
//Execute the kernel arithmetic functions
add<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_add, totalThreads);
subtract<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_sub, totalThreads);
mult<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mult, totalThreads);
mod<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mod, totalThreads);
//Transfer data from device to host
hipMemcpy(h_c_add, d_c_add, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_sub, d_c_sub, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_mult, d_c_mult, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_mod, d_c_mod, bytes, hipMemcpyDeviceToHost);
stopEventTimer(&timer);
std::cout << "Time Elaplsed For Sequential Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
case STREAM:
{
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n";
//choose 4 streams for four kernels
int nStreams = 4;
int iStream; //
//create four asynchronous streams
hipStream_t stream[nStreams];
for(iStream = 0; iStream < nStreams; iStream++)
hipStreamCreate(&stream[iStream]);
//Copy data from host to device and profile using EVENTS
startEventTimer(&timer);
for(iStream = 0; iStream < nStreams; iStream++ ){
hipMemcpyAsync(d_a, h_a, bytes, hipMemcpyHostToDevice, stream[iStream]);
hipMemcpyAsync(d_b, h_b, bytes, hipMemcpyHostToDevice, stream[iStream]);
}
add<<<numBlocks, totalThreads, 0, stream[0]>>>(d_a, d_b, d_c_add, totalThreads);
hipMemcpyAsync(h_c_add, d_c_add, bytes, hipMemcpyDeviceToHost, stream[0]);
//performing subtract function
subtract<<<numBlocks, totalThreads, 0, stream[1]>>>(d_a, d_b, d_c_sub, totalThreads);
hipMemcpyAsync(h_c_sub, d_c_sub, bytes, hipMemcpyDeviceToHost, stream[1]);
//performing mult function
mult<<<numBlocks, totalThreads, 0, stream[2]>>>(d_a, d_b, d_c_mult, totalThreads);
hipMemcpyAsync(h_c_mult, d_c_mult, bytes, hipMemcpyDeviceToHost, stream[2]);
//performing mod fuction
mod<<<numBlocks, totalThreads, 0, stream[3]>>>(d_a, d_b, d_c_mod, totalThreads);
hipMemcpyAsync(h_c_mod, d_c_mod, bytes, hipMemcpyDeviceToHost, stream[2]);
//Wait till all tasks referenced to streams are finished
for(iStream = 0; iStream < nStreams; iStream++)
hipStreamSynchronize(stream[iStream]);
stopEventTimer(&timer);
std::cout << "TIME ELAPSED For Asynchronous Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
}
default:
std::cout << "Unknown Test Type!\n";
break;
}
//destroy Event timer
freeEventTimer(&timer);
//free up space on our GPU
hipFree(d_a);
hipFree(d_b);
hipFree(d_c_add);
hipFree(d_c_sub);
hipFree(d_c_mult);
hipFree(d_c_add);
//free up space on our CPU use cudaFreeHost since pinnned
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c_add);
hipHostFree(h_c_sub);
hipHostFree(h_c_mult);
hipHostFree(h_c_mod);
}
/*******************************************************************************
MAIN
*******************************************************************************/
int main(int argc, char** argv)
{
int totalThreads = (1 << 10);
int blockSize = 256;
//User wants to run the Global vs Pinned Examples
if( argc > 2 && argc < 4){
// Ensure the user supplies both number of threads and block size
// otherwise use default values
totalThreads = atoi(argv[1]);
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
std::cout << "\nUsing " << totalThreads << " Threads and " << blockSize << " BlockSize\n" ;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
std::cout << "Warning: Total thread count is not evenly divisible by the block size\n";
std::cout << "The total number of threads will be rounded up to %d\n";
}
// get number of devices and print some basic properties
checkDevices();
//perform Sequential transfer and execute Test
gpuTest( totalThreads, numBlocks, THREAD);
//perform asynchronous transfer and execute using streams
gpuTest( totalThreads, numBlocks, STREAM);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8subtractPiS_S_i
.globl _Z8subtractPiS_S_i
.p2align 8
.type _Z8subtractPiS_S_i,@function
_Z8subtractPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8subtractPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8subtractPiS_S_i, .Lfunc_end1-_Z8subtractPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4multPiS_S_i
.globl _Z4multPiS_S_i
.p2align 8
.type _Z4multPiS_S_i,@function
_Z4multPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4multPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z4multPiS_S_i, .Lfunc_end2-_Z4multPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3modPiS_S_i
.globl _Z3modPiS_S_i
.p2align 8
.type _Z3modPiS_S_i,@function
_Z3modPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_xor_b32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3modPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3modPiS_S_i, .Lfunc_end3-_Z3modPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8subtractPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8subtractPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4multPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4multPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3modPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3modPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*******************************************************************************
This program uses streams and events to asynchronously perform arithmetic
functions on the GPU. Comparison of timing is shown as output.
Author: Said Darham
*******************************************************************************/
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h> //srand and rand
#include <math.h>
// Test types
#define THREAD 1
#define STREAM 2
//Timer struct declaration. Using CUDA EVENTS
typedef struct timer{
hipEvent_t startEvent;
hipEvent_t stopEvent;
float time_ms;
} timerEvent;
/*******************************************************************************
PROFILER FUNCTIONS USING EVENTS
*******************************************************************************/
void startEventTimer(timerEvent *timer){
/* startEventTimer()
Creates and starts recording an event
*/
hipEventCreate(&timer->startEvent);
hipEventCreate(&timer->stopEvent);
hipEventRecord(timer->startEvent);
}
void stopEventTimer(timerEvent *timer){
/* stopEventTimer()
Stops an event and calculates the elapsed time between start and stop event
*/
hipEventRecord(timer->stopEvent);
hipEventSynchronize(timer->stopEvent);
hipEventElapsedTime(&timer->time_ms, timer->startEvent, timer->stopEvent);
}
void freeEventTimer(timerEvent *timer){
/* freeEventTimer()
cleans up the events
*/
hipEventDestroy(timer->startEvent);
hipEventDestroy(timer->stopEvent);
}
void checkDevices(void){
//Check and print devices name
hipDeviceProp_t prop;
int deviceCount; //number of devices found
int devId = 0; // default device Id
hipGetDeviceCount(&deviceCount);
if(deviceCount == 0){
std::cout << "No GPU Device Found\n";
exit(0);
}else if(deviceCount == 1){
hipSetDevice(devId); //set the device 0 as default
}
std::cout << "Number Of Devices Found: " << deviceCount << std::endl;
//Print device names and some basic associated properties
for (int i = 0; i<deviceCount; i++){
hipGetDeviceProperties(&prop,i);
std::cout << "Device " << i << " Name: " << prop.name << std::endl;
std::cout << "Compute Capability: " << prop.major << "." << prop.minor << std::endl;
}
}
/*******************************************************************************
ARITHMETIC KERNEL FUNCTIONS
*******************************************************************************/
// Add Function
__global__ void add(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
// subtract function
__global__ void subtract(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
// multiply function
__global__ void mult(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
// Moudulu function
__global__ void mod(int *a, int *b, int *c, int n){
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] % b[id];
}
/*******************************************************************************
GPU Test
( Sequential Threads & STREAMS)
*******************************************************************************/
void gpuTest(int numBlocks, int totalThreads, const int testType){
/* gpuTest()
runs either sequential transfer and execute or asynchronous streams
testType is either THREAD or STREAM
*/
//Since both transfer and execute routines will use pinned memory, allocating
//and initializing data is the same for both
// Host input/output vectors
int *h_a, *h_b, *h_c_add,*h_c_sub,*h_c_mult,*h_c_mod;
// Device input/output vectors
int *d_a, *d_b, *d_c_add,*d_c_sub,*d_c_mult,*d_c_mod;
// Size, in bytes, of each vector
const unsigned int bytes = totalThreads*sizeof(int);
// Allocate memory for each vector on host Pinned
hipHostMalloc((void**)&h_a, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_b, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_add, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_sub, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_mult, bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_c_mod, bytes, hipHostMallocDefault);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c_add, bytes);
hipMalloc(&d_c_sub, bytes);
hipMalloc(&d_c_mult, bytes);
hipMalloc(&d_c_mod, bytes);
//initialize the input vectors
for(int i = 0;i<totalThreads;i++){
//first array is 0 through number of threads
h_a[i] = i;
// second array is a random number between 0 and 3
h_b[i] = rand() % 4;
}
// create a struct which will contain info for timing using events
timerEvent timer;
switch(testType){
case THREAD:
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Sequential*****" << std::endl;
//Transfer and Profile data from host to device and profile using EVENTS
startEventTimer(&timer);
hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy( d_b, h_b, bytes, hipMemcpyHostToDevice);
//Execute the kernel arithmetic functions
add<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_add, totalThreads);
subtract<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_sub, totalThreads);
mult<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mult, totalThreads);
mod<<<numBlocks, totalThreads>>>(d_a, d_b, d_c_mod, totalThreads);
//Transfer data from device to host
hipMemcpy(h_c_add, d_c_add, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_sub, d_c_sub, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_mult, d_c_mult, bytes, hipMemcpyDeviceToHost);
hipMemcpy(h_c_mod, d_c_mod, bytes, hipMemcpyDeviceToHost);
stopEventTimer(&timer);
std::cout << "Time Elaplsed For Sequential Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
case STREAM:
{
std::cout << "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n";
//choose 4 streams for four kernels
int nStreams = 4;
int iStream; //
//create four asynchronous streams
hipStream_t stream[nStreams];
for(iStream = 0; iStream < nStreams; iStream++)
hipStreamCreate(&stream[iStream]);
//Copy data from host to device and profile using EVENTS
startEventTimer(&timer);
for(iStream = 0; iStream < nStreams; iStream++ ){
hipMemcpyAsync(d_a, h_a, bytes, hipMemcpyHostToDevice, stream[iStream]);
hipMemcpyAsync(d_b, h_b, bytes, hipMemcpyHostToDevice, stream[iStream]);
}
add<<<numBlocks, totalThreads, 0, stream[0]>>>(d_a, d_b, d_c_add, totalThreads);
hipMemcpyAsync(h_c_add, d_c_add, bytes, hipMemcpyDeviceToHost, stream[0]);
//performing subtract function
subtract<<<numBlocks, totalThreads, 0, stream[1]>>>(d_a, d_b, d_c_sub, totalThreads);
hipMemcpyAsync(h_c_sub, d_c_sub, bytes, hipMemcpyDeviceToHost, stream[1]);
//performing mult function
mult<<<numBlocks, totalThreads, 0, stream[2]>>>(d_a, d_b, d_c_mult, totalThreads);
hipMemcpyAsync(h_c_mult, d_c_mult, bytes, hipMemcpyDeviceToHost, stream[2]);
//performing mod fuction
mod<<<numBlocks, totalThreads, 0, stream[3]>>>(d_a, d_b, d_c_mod, totalThreads);
hipMemcpyAsync(h_c_mod, d_c_mod, bytes, hipMemcpyDeviceToHost, stream[2]);
//Wait till all tasks referenced to streams are finished
for(iStream = 0; iStream < nStreams; iStream++)
hipStreamSynchronize(stream[iStream]);
stopEventTimer(&timer);
std::cout << "TIME ELAPSED For Asynchronous Transfer and Execute: " << timer.time_ms << " ms" << std::endl;
break;
}
default:
std::cout << "Unknown Test Type!\n";
break;
}
//destroy Event timer
freeEventTimer(&timer);
//free up space on our GPU
hipFree(d_a);
hipFree(d_b);
hipFree(d_c_add);
hipFree(d_c_sub);
hipFree(d_c_mult);
hipFree(d_c_add);
//free up space on our CPU use cudaFreeHost since pinnned
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c_add);
hipHostFree(h_c_sub);
hipHostFree(h_c_mult);
hipHostFree(h_c_mod);
}
/*******************************************************************************
MAIN
*******************************************************************************/
int main(int argc, char** argv)
{
int totalThreads = (1 << 10);
int blockSize = 256;
//User wants to run the Global vs Pinned Examples
if( argc > 2 && argc < 4){
// Ensure the user supplies both number of threads and block size
// otherwise use default values
totalThreads = atoi(argv[1]);
blockSize = atoi(argv[2]);
}
int numBlocks = totalThreads/blockSize;
std::cout << "\nUsing " << totalThreads << " Threads and " << blockSize << " BlockSize\n" ;
// validate command line arguments
if (totalThreads % blockSize != 0) {
++numBlocks;
totalThreads = numBlocks*blockSize;
std::cout << "Warning: Total thread count is not evenly divisible by the block size\n";
std::cout << "The total number of threads will be rounded up to %d\n";
}
// get number of devices and print some basic properties
checkDevices();
//perform Sequential transfer and execute Test
gpuTest( totalThreads, numBlocks, THREAD);
//perform asynchronous transfer and execute using streams
gpuTest( totalThreads, numBlocks, STREAM);
return 0;
} | .text
.file "assignment7.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z15startEventTimerP5timer # -- Begin function _Z15startEventTimerP5timer
.p2align 4, 0x90
.type _Z15startEventTimerP5timer,@function
_Z15startEventTimerP5timer: # @_Z15startEventTimerP5timer
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipEventCreate
leaq 8(%rbx), %rdi
callq hipEventCreate
movq (%rbx), %rdi
xorl %esi, %esi
popq %rbx
.cfi_def_cfa_offset 8
jmp hipEventRecord # TAILCALL
.Lfunc_end0:
.size _Z15startEventTimerP5timer, .Lfunc_end0-_Z15startEventTimerP5timer
.cfi_endproc
# -- End function
.globl _Z14stopEventTimerP5timer # -- Begin function _Z14stopEventTimerP5timer
.p2align 4, 0x90
.type _Z14stopEventTimerP5timer,@function
_Z14stopEventTimerP5timer: # @_Z14stopEventTimerP5timer
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rbx), %rdi
callq hipEventSynchronize
leaq 16(%rbx), %rdi
movq (%rbx), %rsi
movq 8(%rbx), %rdx
popq %rbx
.cfi_def_cfa_offset 8
jmp hipEventElapsedTime # TAILCALL
.Lfunc_end1:
.size _Z14stopEventTimerP5timer, .Lfunc_end1-_Z14stopEventTimerP5timer
.cfi_endproc
# -- End function
.globl _Z14freeEventTimerP5timer # -- Begin function _Z14freeEventTimerP5timer
.p2align 4, 0x90
.type _Z14freeEventTimerP5timer,@function
_Z14freeEventTimerP5timer: # @_Z14freeEventTimerP5timer
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
callq hipEventDestroy
movq 8(%rbx), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp hipEventDestroy # TAILCALL
.Lfunc_end2:
.size _Z14freeEventTimerP5timer, .Lfunc_end2-_Z14freeEventTimerP5timer
.cfi_endproc
# -- End function
.globl _Z12checkDevicesv # -- Begin function _Z12checkDevicesv
.p2align 4, 0x90
.type _Z12checkDevicesv,@function
_Z12checkDevicesv: # @_Z12checkDevicesv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %eax
cmpl $1, %eax
je .LBB3_3
# %bb.1:
testl %eax, %eax
jne .LBB3_4
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
xorl %edi, %edi
callq exit
.LBB3_3:
xorl %edi, %edi
callq hipSetDevice
.LBB3_4:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_20
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB3_8
.LBB3_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 4(%rsp)
jle .LBB3_19
# %bb.9: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_10 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB3_10 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB3_19
.LBB3_10: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_20
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
# in Loop: Header=BB3_10 Depth=1
cmpb $0, 56(%r12)
je .LBB3_13
# %bb.12: # in Loop: Header=BB3_10 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_10 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
# in Loop: Header=BB3_10 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_20
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB3_10 Depth=1
cmpb $0, 56(%r15)
je .LBB3_17
# %bb.16: # in Loop: Header=BB3_10 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_18
.LBB3_19: # %._crit_edge
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_20:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z12checkDevicesv, .Lfunc_end3-_Z12checkDevicesv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end4-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__subtractPiS_S_i # -- Begin function _Z23__device_stub__subtractPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__subtractPiS_S_i,@function
_Z23__device_stub__subtractPiS_S_i: # @_Z23__device_stub__subtractPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8subtractPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z23__device_stub__subtractPiS_S_i, .Lfunc_end5-_Z23__device_stub__subtractPiS_S_i
.cfi_endproc
# -- End function
.globl _Z19__device_stub__multPiS_S_i # -- Begin function _Z19__device_stub__multPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__multPiS_S_i,@function
_Z19__device_stub__multPiS_S_i: # @_Z19__device_stub__multPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4multPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z19__device_stub__multPiS_S_i, .Lfunc_end6-_Z19__device_stub__multPiS_S_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__modPiS_S_i # -- Begin function _Z18__device_stub__modPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__modPiS_S_i,@function
_Z18__device_stub__modPiS_S_i: # @_Z18__device_stub__modPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3modPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z18__device_stub__modPiS_S_i, .Lfunc_end7-_Z18__device_stub__modPiS_S_i
.cfi_endproc
# -- End function
.globl _Z7gpuTestiii # -- Begin function _Z7gpuTestiii
.p2align 4, 0x90
.type _Z7gpuTestiii,@function
_Z7gpuTestiii: # @_Z7gpuTestiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $264, %rsp # imm = 0x108
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl %edx, %r12d
movl %esi, %r14d
movl %edi, -228(%rbp) # 4-byte Spill
leal (,%r14,4), %ebx
leaq -256(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq -248(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq -288(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq -280(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq -272(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq -264(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq -136(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -128(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -184(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -224(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -216(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq -240(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %r14d, %r14d
jle .LBB8_3
# %bb.1: # %.lr.ph.preheader
movl %r14d, %r13d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq -256(%rbp), %rax
movl %r15d, (%rax,%r15,4)
callq rand
# kill: def $eax killed $eax def $rax
leal 3(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-4, %ecx
subl %ecx, %eax
movq -248(%rbp), %rcx
movl %eax, (%rcx,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB8_2
.LBB8_3: # %._crit_edge
movl $_ZSt4cout, %edi
cmpl $1, %r12d
je .LBB8_22
# %bb.4: # %._crit_edge
cmpl $2, %r12d
jne .LBB8_41
# %bb.5:
movl $.L.str.9, %esi
movl $58, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rsp, -296(%rbp) # 8-byte Spill
movq %rsp, %r13
addq $-32, %r13
movq %r13, %rsp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_6: # =>This Inner Loop Header: Depth=1
leaq (%r15,%r13), %rdi
callq hipStreamCreate
addq $8, %r15
cmpq $32, %r15
jne .LBB8_6
# %bb.7:
leaq -208(%rbp), %rdi
callq hipEventCreate
leaq -200(%rbp), %rdi
callq hipEventCreate
movq -208(%rbp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB8_8: # =>This Inner Loop Header: Depth=1
movq -136(%rbp), %rdi
movq -256(%rbp), %rsi
movq (%r13,%r12,8), %r8
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq -128(%rbp), %rdi
movq -248(%rbp), %rsi
movq (%r13,%r12,8), %r8
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpyAsync
incq %r12
cmpq $4, %r12
jne .LBB8_8
# %bb.9:
movq (%r13), %r9
movl -228(%rbp), %r15d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %r14d, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_11
# %bb.10:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -184(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3addPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_11:
movq -288(%rbp), %rdi
movq -184(%rbp), %rsi
movq (%r13), %r8
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%r13), %r9
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_13
# %bb.12:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -224(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z8subtractPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_13:
movq -280(%rbp), %rdi
movq -224(%rbp), %rsi
movq 8(%r13), %r8
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 16(%r13), %r9
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_15
# %bb.14:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -216(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z4multPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_15:
movq -272(%rbp), %rdi
movq -216(%rbp), %rsi
movq 16(%r13), %r8
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 24(%r13), %r9
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_17
# %bb.16:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -240(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3modPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_17:
movq -264(%rbp), %rdi
movq -240(%rbp), %rsi
movq 16(%r13), %r8
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpyAsync
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_18: # =>This Inner Loop Header: Depth=1
movq (%r13,%rbx,8), %rdi
callq hipStreamSynchronize
incq %rbx
cmpq $4, %rbx
jne .LBB8_18
# %bb.19:
movq -200(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -200(%rbp), %rdi
callq hipEventSynchronize
leaq -192(%rbp), %rdi
movq -208(%rbp), %rsi
movq -200(%rbp), %rdx
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -192(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.8, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB8_43
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i157
cmpb $0, 56(%r14)
je .LBB8_39
# %bb.21:
movzbl 67(%r14), %eax
jmp .LBB8_40
.LBB8_22:
movl $.L.str.6, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB8_43
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB8_25
# %bb.24:
movzbl 67(%r12), %eax
jmp .LBB8_26
.LBB8_41:
movl $.L.str.11, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_42
.LBB8_39:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit160
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -296(%rbp), %rsp # 8-byte Reload
jmp .LBB8_42
.LBB8_25:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -208(%rbp), %rdi
callq hipEventCreate
leaq -200(%rbp), %rdi
callq hipEventCreate
movq -208(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -136(%rbp), %rdi
movq -256(%rbp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -128(%rbp), %rdi
movq -248(%rbp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl -228(%rbp), %r15d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %r14d, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_28
# %bb.27:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -184(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3addPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_28:
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_30
# %bb.29:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -224(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z8subtractPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_30:
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_32
# %bb.31:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -216(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z4multPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_32:
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_34
# %bb.33:
movq -136(%rbp), %rax
movq -128(%rbp), %rcx
movq -240(%rbp), %rdx
movq %rax, -120(%rbp)
movq %rcx, -112(%rbp)
movq %rdx, -104(%rbp)
movl %r14d, -44(%rbp)
leaq -120(%rbp), %rax
movq %rax, -176(%rbp)
leaq -112(%rbp), %rax
movq %rax, -168(%rbp)
leaq -104(%rbp), %rax
movq %rax, -160(%rbp)
leaq -44(%rbp), %rax
movq %rax, -152(%rbp)
leaq -96(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -64(%rbp), %rdx
leaq -56(%rbp), %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
leaq -176(%rbp), %r9
movl $_Z3modPiS_S_i, %edi
pushq -56(%rbp)
pushq -64(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB8_34:
movq -288(%rbp), %rdi
movq -184(%rbp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -280(%rbp), %rdi
movq -224(%rbp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -272(%rbp), %rdi
movq -216(%rbp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -264(%rbp), %rdi
movq -240(%rbp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq -200(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -200(%rbp), %rdi
callq hipEventSynchronize
leaq -192(%rbp), %rdi
movq -208(%rbp), %rsi
movq -200(%rbp), %rdx
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $51, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -192(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.8, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB8_43
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i152
cmpb $0, 56(%r14)
je .LBB8_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB8_38
.LBB8_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit155
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB8_42:
movq -208(%rbp), %rdi
callq hipEventDestroy
movq -200(%rbp), %rdi
callq hipEventDestroy
movq -136(%rbp), %rdi
callq hipFree
movq -128(%rbp), %rdi
callq hipFree
movq -184(%rbp), %rdi
callq hipFree
movq -224(%rbp), %rdi
callq hipFree
movq -216(%rbp), %rdi
callq hipFree
movq -184(%rbp), %rdi
callq hipFree
movq -256(%rbp), %rdi
callq hipHostFree
movq -248(%rbp), %rdi
callq hipHostFree
movq -288(%rbp), %rdi
callq hipHostFree
movq -280(%rbp), %rdi
callq hipHostFree
movq -272(%rbp), %rdi
callq hipHostFree
movq -264(%rbp), %rdi
callq hipHostFree
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB8_43:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end8:
.size _Z7gpuTestiii, .Lfunc_end8-_Z7gpuTestiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB9_1
# %bb.2:
movq 8(%rsi), %rdi
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB9_3
.LBB9_1:
movl $256, %r14d # imm = 0x100
movl $1024, %ebx # imm = 0x400
.LBB9_3:
movl %ebx, %eax
cltd
idivl %r14d
movl %edx, %r15d
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.13, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movl $.L.str.14, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %r15d, %r15d
je .LBB9_5
# %bb.4:
incl %ebp
imull %ebp, %r14d
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $70, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $53, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r14d, %ebx
.LBB9_5:
callq _Z12checkDevicesv
movl %ebx, %edi
movl %ebp, %esi
movl $1, %edx
callq _Z7gpuTestiii
movl %ebx, %edi
movl %ebp, %esi
movl $2, %edx
callq _Z7gpuTestiii
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8subtractPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4multPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3modPiS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "No GPU Device Found\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number Of Devices Found: "
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Name: "
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute Capability: "
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "."
.size .L.str.5, 2
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type _Z8subtractPiS_S_i,@object # @_Z8subtractPiS_S_i
.globl _Z8subtractPiS_S_i
.p2align 3, 0x0
_Z8subtractPiS_S_i:
.quad _Z23__device_stub__subtractPiS_S_i
.size _Z8subtractPiS_S_i, 8
.type _Z4multPiS_S_i,@object # @_Z4multPiS_S_i
.globl _Z4multPiS_S_i
.p2align 3, 0x0
_Z4multPiS_S_i:
.quad _Z19__device_stub__multPiS_S_i
.size _Z4multPiS_S_i, 8
.type _Z3modPiS_S_i,@object # @_Z3modPiS_S_i
.globl _Z3modPiS_S_i
.p2align 3, 0x0
_Z3modPiS_S_i:
.quad _Z18__device_stub__modPiS_S_i
.size _Z3modPiS_S_i, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "\n\t\t*****Executing Arithmetic Functions Using Sequential*****"
.size .L.str.6, 61
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Time Elaplsed For Sequential Transfer and Execute: "
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " ms"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\n\t\t*****Executing Arithmetic Functions Using Streams*****\n"
.size .L.str.9, 59
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "TIME ELAPSED For Asynchronous Transfer and Execute: "
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Unknown Test Type!\n"
.size .L.str.11, 20
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nUsing "
.size .L.str.12, 8
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Threads and "
.size .L.str.13, 14
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " BlockSize\n"
.size .L.str.14, 12
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Warning: Total thread count is not evenly divisible by the block size\n"
.size .L.str.15, 71
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "The total number of threads will be rounded up to %d\n"
.size .L.str.16, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8subtractPiS_S_i"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z4multPiS_S_i"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3modPiS_S_i"
.size .L__unnamed_4, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym _Z23__device_stub__subtractPiS_S_i
.addrsig_sym _Z19__device_stub__multPiS_S_i
.addrsig_sym _Z18__device_stub__modPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _Z8subtractPiS_S_i
.addrsig_sym _Z4multPiS_S_i
.addrsig_sym _Z3modPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3modPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000e2000c1e1900 */
/*00c0*/ IABS R10, R4.reuse ; /* 0x00000004000a7213 */
/* 0x084fe40000000000 */
/*00d0*/ IABS R12, R4 ; /* 0x00000004000c7213 */
/* 0x000fe40000000000 */
/*00e0*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e660000209400 */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R12 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0a0c */
/*0100*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x008fc80003f46270 */
/*0110*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e240000001000 */
/*0120*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe40007ffe0ff */
/*0130*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fc80000000000 */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0150*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0160*/ IADD3 R11, RZ, -R7, RZ ; /* 0x80000007ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0170*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0190*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R7, R7, R3, R8 ; /* 0x0000000307077224 */
/* 0x000fe400078e0208 */
/*01b0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0209 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0a */
/*01e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R7, R7, -R10, RZ ; /* 0x8000000a07079210 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0220*/ @!P0 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff078212 */
/* 0x000fca00078e33ff */
/*0230*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4multPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8subtractPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, -R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe1ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8subtractPiS_S_i
.globl _Z8subtractPiS_S_i
.p2align 8
.type _Z8subtractPiS_S_i,@function
_Z8subtractPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8subtractPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8subtractPiS_S_i, .Lfunc_end1-_Z8subtractPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4multPiS_S_i
.globl _Z4multPiS_S_i
.p2align 8
.type _Z4multPiS_S_i,@function
_Z4multPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4multPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z4multPiS_S_i, .Lfunc_end2-_Z4multPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3modPiS_S_i
.globl _Z3modPiS_S_i
.p2align 8
.type _Z3modPiS_S_i,@function
_Z3modPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_xor_b32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3modPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3modPiS_S_i, .Lfunc_end3-_Z3modPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8subtractPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8subtractPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4multPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4multPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3modPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3modPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define N 4096000
__global__ void mulKernel(int *a, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]*2;
}
}
int main(void)
{
int *a_h[2], *c_h[2];
//device memory pointers
int *a_d[2];
int *c_d[2];
cudaStream_t stream[2];
for (int i = 0; i < 2; ++i)
{
cudaStreamCreate(&stream[i]); //stream creation
//pinned memory allocation
cudaMallocHost((void**)&a_h[i], (N/2)*sizeof(int));
cudaMallocHost((void**)&c_h[i], (N/2)*sizeof(int));
//allocate device memory
cudaMalloc((void**)&a_d[i], (N/2)*sizeof(int));
//cudaMalloc((void**)&b_d[i], (N/2)*sizeof(int));
cudaMalloc((void**)&c_d[i], (N/2)*sizeof(int));
}
//load arrays with some numbers
for(int i=0; i<2; i++)
{
for(int ii=0; ii<N/2; ii++)
{
a_h[i][ii] = i*N/2+ii;
}
}
//CUDA events to measure time
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
//start timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// grid and block size stuff
dim3 grid(N/32, N/32, 1);
dim3 block(32, 32, 1);
// stream 0
cudaMemcpyAsync(&a_d[0], &a_h[0], (N/2)*sizeof(int),
cudaMemcpyHostToDevice, stream[0]);
mulKernel <<< grid, block, 0, stream[0]>>>(a_d[0], c_d[0]);
cudaMemcpyAsync(&c_h[0], &c_d[0], (N/2)*sizeof(int),
cudaMemcpyDeviceToHost, stream[0]);
//stream 1
cudaMemcpyAsync(&a_d[1], &a_h[1], (N/2)*sizeof(int),
cudaMemcpyHostToDevice, stream[1]);
mulKernel <<<grid, block, 0, stream[1]>>>(a_d[1], c_d[1]);
cudaMemcpyAsync(&c_h[1], &c_d[1], (N/2)*sizeof(int),
cudaMemcpyDeviceToHost, stream[1]);
//stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
// Check results
for(int ii=0; ii<N/2; ii++)
{
if (2*a_h[0][ii] != c_h[0][ii] || 2*a_h[1][ii] != c_h[1][ii])
{
printf("Error: CPU and GPU result [%d] do not match\n", ii);
printf("CPU0:%d GPU0:%d\n", 2*a_h[0][ii], c_h[0][ii]);
printf("CPU1:%d GPU1:%d\n", 2*a_h[1][ii], c_h[1][ii]);
break;
}
}
for (int i = 0; i < 2; ++i)
{
cudaStreamDestroy(stream[i]);
//clean up
cudaFreeHost(a_h[i]);
cudaFreeHost(c_h[i]);
}
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z9mulKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3e7fff, PT ; /* 0x003e7fff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ SHF.L.U32 R7, R2, 0x1, RZ ; /* 0x0000000102077819 */
/* 0x004fca00000006ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define N 4096000
__global__ void mulKernel(int *a, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]*2;
}
}
int main(void)
{
int *a_h[2], *c_h[2];
//device memory pointers
int *a_d[2];
int *c_d[2];
cudaStream_t stream[2];
for (int i = 0; i < 2; ++i)
{
cudaStreamCreate(&stream[i]); //stream creation
//pinned memory allocation
cudaMallocHost((void**)&a_h[i], (N/2)*sizeof(int));
cudaMallocHost((void**)&c_h[i], (N/2)*sizeof(int));
//allocate device memory
cudaMalloc((void**)&a_d[i], (N/2)*sizeof(int));
//cudaMalloc((void**)&b_d[i], (N/2)*sizeof(int));
cudaMalloc((void**)&c_d[i], (N/2)*sizeof(int));
}
//load arrays with some numbers
for(int i=0; i<2; i++)
{
for(int ii=0; ii<N/2; ii++)
{
a_h[i][ii] = i*N/2+ii;
}
}
//CUDA events to measure time
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
//start timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// grid and block size stuff
dim3 grid(N/32, N/32, 1);
dim3 block(32, 32, 1);
// stream 0
cudaMemcpyAsync(&a_d[0], &a_h[0], (N/2)*sizeof(int),
cudaMemcpyHostToDevice, stream[0]);
mulKernel <<< grid, block, 0, stream[0]>>>(a_d[0], c_d[0]);
cudaMemcpyAsync(&c_h[0], &c_d[0], (N/2)*sizeof(int),
cudaMemcpyDeviceToHost, stream[0]);
//stream 1
cudaMemcpyAsync(&a_d[1], &a_h[1], (N/2)*sizeof(int),
cudaMemcpyHostToDevice, stream[1]);
mulKernel <<<grid, block, 0, stream[1]>>>(a_d[1], c_d[1]);
cudaMemcpyAsync(&c_h[1], &c_d[1], (N/2)*sizeof(int),
cudaMemcpyDeviceToHost, stream[1]);
//stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
// Check results
for(int ii=0; ii<N/2; ii++)
{
if (2*a_h[0][ii] != c_h[0][ii] || 2*a_h[1][ii] != c_h[1][ii])
{
printf("Error: CPU and GPU result [%d] do not match\n", ii);
printf("CPU0:%d GPU0:%d\n", 2*a_h[0][ii], c_h[0][ii]);
printf("CPU1:%d GPU1:%d\n", 2*a_h[1][ii], c_h[1][ii]);
break;
}
}
for (int i = 0; i < 2; ++i)
{
cudaStreamDestroy(stream[i]);
//clean up
cudaFreeHost(a_h[i]);
cudaFreeHost(c_h[i]);
}
cudaDeviceReset();
return 0;
} | .file "tmpxft_0008ef03_00000000-6_ex2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9mulKernelPiS_PiS_
.type _Z30__device_stub__Z9mulKernelPiS_PiS_, @function
_Z30__device_stub__Z9mulKernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9mulKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9mulKernelPiS_PiS_, .-_Z30__device_stub__Z9mulKernelPiS_PiS_
.globl _Z9mulKernelPiS_
.type _Z9mulKernelPiS_, @function
_Z9mulKernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9mulKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9mulKernelPiS_, .-_Z9mulKernelPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Time to calculate results: %f ms.\n"
.align 8
.LC1:
.string "Error: CPU and GPU result [%d] do not match\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU0:%d GPU0:%d\n"
.LC3:
.string "CPU1:%d GPU1:%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $144, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 48(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 64(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 80(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 56(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 72(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 88(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movq 48(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $2048000, %rax
jne .L12
movl $2048000, %edx
movl $0, %eax
.L13:
movq 56(%rsp), %rcx
movl %edx, (%rcx,%rax)
addq $4, %rax
addl $1, %edx
cmpq $8192000, %rax
jne .L13
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $128000, 24(%rsp)
movl $128000, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdi
movq 112(%rsp), %r8
movl $1, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
movl 44(%rsp), %ecx
movq 112(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
leaq 96(%rsp), %rsi
leaq 64(%rsp), %rdi
movq 112(%rsp), %r8
movl $2, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
leaq 56(%rsp), %rsi
leaq 88(%rsp), %rdi
movq 120(%rsp), %r8
movl $1, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
movl 44(%rsp), %ecx
movq 120(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L15:
leaq 104(%rsp), %rsi
leaq 72(%rsp), %rdi
movq 120(%rsp), %r8
movl $2, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rdi
movq 72(%rsp), %rsi
movl $0, %ebx
.L18:
movl (%rcx,%rbx,4), %eax
addl %eax, %eax
cmpl (%rdx,%rbx,4), %eax
jne .L16
movl (%rdi,%rbx,4), %eax
addl %eax, %eax
cmpl (%rsi,%rbx,4), %eax
jne .L16
addq $1, %rbx
cmpq $2048000, %rbx
jne .L18
jmp .L19
.L26:
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z30__device_stub__Z9mulKernelPiS_PiS_
jmp .L14
.L27:
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z30__device_stub__Z9mulKernelPiS_PiS_
jmp .L15
.L16:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 64(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movq 48(%rsp), %rax
movl (%rax,%rbx,4), %edx
addl %edx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movq 56(%rsp), %rax
movl (%rax,%rbx,4), %edx
addl %edx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
movq 112(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 64(%rsp), %rdi
call cudaFreeHost@PLT
movq 120(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rdi
call cudaFreeHost@PLT
call cudaDeviceReset@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9mulKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mulKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define N 4096000
__global__ void mulKernel(int *a, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]*2;
}
}
int main(void)
{
int *a_h[2], *c_h[2];
//device memory pointers
int *a_d[2];
int *c_d[2];
cudaStream_t stream[2];
for (int i = 0; i < 2; ++i)
{
cudaStreamCreate(&stream[i]); //stream creation
//pinned memory allocation
cudaMallocHost((void**)&a_h[i], (N/2)*sizeof(int));
cudaMallocHost((void**)&c_h[i], (N/2)*sizeof(int));
//allocate device memory
cudaMalloc((void**)&a_d[i], (N/2)*sizeof(int));
//cudaMalloc((void**)&b_d[i], (N/2)*sizeof(int));
cudaMalloc((void**)&c_d[i], (N/2)*sizeof(int));
}
//load arrays with some numbers
for(int i=0; i<2; i++)
{
for(int ii=0; ii<N/2; ii++)
{
a_h[i][ii] = i*N/2+ii;
}
}
//CUDA events to measure time
cudaEvent_t start;
cudaEvent_t stop;
float elapsedTime;
//start timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// grid and block size stuff
dim3 grid(N/32, N/32, 1);
dim3 block(32, 32, 1);
// stream 0
cudaMemcpyAsync(&a_d[0], &a_h[0], (N/2)*sizeof(int),
cudaMemcpyHostToDevice, stream[0]);
mulKernel <<< grid, block, 0, stream[0]>>>(a_d[0], c_d[0]);
cudaMemcpyAsync(&c_h[0], &c_d[0], (N/2)*sizeof(int),
cudaMemcpyDeviceToHost, stream[0]);
//stream 1
cudaMemcpyAsync(&a_d[1], &a_h[1], (N/2)*sizeof(int),
cudaMemcpyHostToDevice, stream[1]);
mulKernel <<<grid, block, 0, stream[1]>>>(a_d[1], c_d[1]);
cudaMemcpyAsync(&c_h[1], &c_d[1], (N/2)*sizeof(int),
cudaMemcpyDeviceToHost, stream[1]);
//stop timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
// Check results
for(int ii=0; ii<N/2; ii++)
{
if (2*a_h[0][ii] != c_h[0][ii] || 2*a_h[1][ii] != c_h[1][ii])
{
printf("Error: CPU and GPU result [%d] do not match\n", ii);
printf("CPU0:%d GPU0:%d\n", 2*a_h[0][ii], c_h[0][ii]);
printf("CPU1:%d GPU1:%d\n", 2*a_h[1][ii], c_h[1][ii]);
break;
}
}
for (int i = 0; i < 2; ++i)
{
cudaStreamDestroy(stream[i]);
//clean up
cudaFreeHost(a_h[i]);
cudaFreeHost(c_h[i]);
}
cudaDeviceReset();
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#define N 4096000
__global__ void mulKernel(int *a, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]*2;
}
}
int main(void)
{
int *a_h[2], *c_h[2];
//device memory pointers
int *a_d[2];
int *c_d[2];
hipStream_t stream[2];
for (int i = 0; i < 2; ++i)
{
hipStreamCreate(&stream[i]); //stream creation
//pinned memory allocation
hipHostMalloc((void**)&a_h[i], (N/2)*sizeof(int), hipHostMallocDefault);
hipHostMalloc((void**)&c_h[i], (N/2)*sizeof(int), hipHostMallocDefault);
//allocate device memory
hipMalloc((void**)&a_d[i], (N/2)*sizeof(int));
//cudaMalloc((void**)&b_d[i], (N/2)*sizeof(int));
hipMalloc((void**)&c_d[i], (N/2)*sizeof(int));
}
//load arrays with some numbers
for(int i=0; i<2; i++)
{
for(int ii=0; ii<N/2; ii++)
{
a_h[i][ii] = i*N/2+ii;
}
}
//CUDA events to measure time
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
//start timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// grid and block size stuff
dim3 grid(N/32, N/32, 1);
dim3 block(32, 32, 1);
// stream 0
hipMemcpyAsync(&a_d[0], &a_h[0], (N/2)*sizeof(int),
hipMemcpyHostToDevice, stream[0]);
mulKernel <<< grid, block, 0, stream[0]>>>(a_d[0], c_d[0]);
hipMemcpyAsync(&c_h[0], &c_d[0], (N/2)*sizeof(int),
hipMemcpyDeviceToHost, stream[0]);
//stream 1
hipMemcpyAsync(&a_d[1], &a_h[1], (N/2)*sizeof(int),
hipMemcpyHostToDevice, stream[1]);
mulKernel <<<grid, block, 0, stream[1]>>>(a_d[1], c_d[1]);
hipMemcpyAsync(&c_h[1], &c_d[1], (N/2)*sizeof(int),
hipMemcpyDeviceToHost, stream[1]);
//stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
// Check results
for(int ii=0; ii<N/2; ii++)
{
if (2*a_h[0][ii] != c_h[0][ii] || 2*a_h[1][ii] != c_h[1][ii])
{
printf("Error: CPU and GPU result [%d] do not match\n", ii);
printf("CPU0:%d GPU0:%d\n", 2*a_h[0][ii], c_h[0][ii]);
printf("CPU1:%d GPU1:%d\n", 2*a_h[1][ii], c_h[1][ii]);
break;
}
}
for (int i = 0; i < 2; ++i)
{
hipStreamDestroy(stream[i]);
//clean up
hipHostFree(a_h[i]);
hipHostFree(c_h[i]);
}
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define N 4096000
__global__ void mulKernel(int *a, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]*2;
}
}
int main(void)
{
int *a_h[2], *c_h[2];
//device memory pointers
int *a_d[2];
int *c_d[2];
hipStream_t stream[2];
for (int i = 0; i < 2; ++i)
{
hipStreamCreate(&stream[i]); //stream creation
//pinned memory allocation
hipHostMalloc((void**)&a_h[i], (N/2)*sizeof(int), hipHostMallocDefault);
hipHostMalloc((void**)&c_h[i], (N/2)*sizeof(int), hipHostMallocDefault);
//allocate device memory
hipMalloc((void**)&a_d[i], (N/2)*sizeof(int));
//cudaMalloc((void**)&b_d[i], (N/2)*sizeof(int));
hipMalloc((void**)&c_d[i], (N/2)*sizeof(int));
}
//load arrays with some numbers
for(int i=0; i<2; i++)
{
for(int ii=0; ii<N/2; ii++)
{
a_h[i][ii] = i*N/2+ii;
}
}
//CUDA events to measure time
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
//start timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// grid and block size stuff
dim3 grid(N/32, N/32, 1);
dim3 block(32, 32, 1);
// stream 0
hipMemcpyAsync(&a_d[0], &a_h[0], (N/2)*sizeof(int),
hipMemcpyHostToDevice, stream[0]);
mulKernel <<< grid, block, 0, stream[0]>>>(a_d[0], c_d[0]);
hipMemcpyAsync(&c_h[0], &c_d[0], (N/2)*sizeof(int),
hipMemcpyDeviceToHost, stream[0]);
//stream 1
hipMemcpyAsync(&a_d[1], &a_h[1], (N/2)*sizeof(int),
hipMemcpyHostToDevice, stream[1]);
mulKernel <<<grid, block, 0, stream[1]>>>(a_d[1], c_d[1]);
hipMemcpyAsync(&c_h[1], &c_d[1], (N/2)*sizeof(int),
hipMemcpyDeviceToHost, stream[1]);
//stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
// Check results
for(int ii=0; ii<N/2; ii++)
{
if (2*a_h[0][ii] != c_h[0][ii] || 2*a_h[1][ii] != c_h[1][ii])
{
printf("Error: CPU and GPU result [%d] do not match\n", ii);
printf("CPU0:%d GPU0:%d\n", 2*a_h[0][ii], c_h[0][ii]);
printf("CPU1:%d GPU1:%d\n", 2*a_h[1][ii], c_h[1][ii]);
break;
}
}
for (int i = 0; i < 2; ++i)
{
hipStreamDestroy(stream[i]);
//clean up
hipHostFree(a_h[i]);
hipHostFree(c_h[i]);
}
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mulKernelPiS_
.globl _Z9mulKernelPiS_
.p2align 8
.type _Z9mulKernelPiS_,@function
_Z9mulKernelPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3e8000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mulKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mulKernelPiS_, .Lfunc_end0-_Z9mulKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mulKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mulKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define N 4096000
__global__ void mulKernel(int *a, int *c)
{
int tdx = blockIdx.x * blockDim.x + threadIdx.x;
if(tdx < N)
{
c[tdx] = a[tdx]*2;
}
}
int main(void)
{
int *a_h[2], *c_h[2];
//device memory pointers
int *a_d[2];
int *c_d[2];
hipStream_t stream[2];
for (int i = 0; i < 2; ++i)
{
hipStreamCreate(&stream[i]); //stream creation
//pinned memory allocation
hipHostMalloc((void**)&a_h[i], (N/2)*sizeof(int), hipHostMallocDefault);
hipHostMalloc((void**)&c_h[i], (N/2)*sizeof(int), hipHostMallocDefault);
//allocate device memory
hipMalloc((void**)&a_d[i], (N/2)*sizeof(int));
//cudaMalloc((void**)&b_d[i], (N/2)*sizeof(int));
hipMalloc((void**)&c_d[i], (N/2)*sizeof(int));
}
//load arrays with some numbers
for(int i=0; i<2; i++)
{
for(int ii=0; ii<N/2; ii++)
{
a_h[i][ii] = i*N/2+ii;
}
}
//CUDA events to measure time
hipEvent_t start;
hipEvent_t stop;
float elapsedTime;
//start timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// grid and block size stuff
dim3 grid(N/32, N/32, 1);
dim3 block(32, 32, 1);
// stream 0
hipMemcpyAsync(&a_d[0], &a_h[0], (N/2)*sizeof(int),
hipMemcpyHostToDevice, stream[0]);
mulKernel <<< grid, block, 0, stream[0]>>>(a_d[0], c_d[0]);
hipMemcpyAsync(&c_h[0], &c_d[0], (N/2)*sizeof(int),
hipMemcpyDeviceToHost, stream[0]);
//stream 1
hipMemcpyAsync(&a_d[1], &a_h[1], (N/2)*sizeof(int),
hipMemcpyHostToDevice, stream[1]);
mulKernel <<<grid, block, 0, stream[1]>>>(a_d[1], c_d[1]);
hipMemcpyAsync(&c_h[1], &c_d[1], (N/2)*sizeof(int),
hipMemcpyDeviceToHost, stream[1]);
//stop timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
//print out execution time
printf("Time to calculate results: %f ms.\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
// Check results
for(int ii=0; ii<N/2; ii++)
{
if (2*a_h[0][ii] != c_h[0][ii] || 2*a_h[1][ii] != c_h[1][ii])
{
printf("Error: CPU and GPU result [%d] do not match\n", ii);
printf("CPU0:%d GPU0:%d\n", 2*a_h[0][ii], c_h[0][ii]);
printf("CPU1:%d GPU1:%d\n", 2*a_h[1][ii], c_h[1][ii]);
break;
}
}
for (int i = 0; i < 2; ++i)
{
hipStreamDestroy(stream[i]);
//clean up
hipHostFree(a_h[i]);
hipHostFree(c_h[i]);
}
hipDeviceReset();
return 0;
} | .text
.file "ex2.hip"
.globl _Z24__device_stub__mulKernelPiS_ # -- Begin function _Z24__device_stub__mulKernelPiS_
.p2align 4, 0x90
.type _Z24__device_stub__mulKernelPiS_,@function
_Z24__device_stub__mulKernelPiS_: # @_Z24__device_stub__mulKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9mulKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__mulKernelPiS_, .Lfunc_end0-_Z24__device_stub__mulKernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $200, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $32, %rdi
callq hipStreamCreate
leaq (%rsp,%rbx), %rdi
addq $16, %rdi
movl $8192000, %esi # imm = 0x7D0000
xorl %edx, %edx
callq hipHostMalloc
leaq (%rsp,%rbx), %rdi
addq $48, %rdi
movl $8192000, %esi # imm = 0x7D0000
xorl %edx, %edx
callq hipHostMalloc
leaq (%rsp,%rbx), %rdi
addq $176, %rdi
movl $8192000, %esi # imm = 0x7D0000
callq hipMalloc
leaq (%rsp,%rbx), %rdi
addq $160, %rdi
movl $8192000, %esi # imm = 0x7D0000
callq hipMalloc
addq $8, %rbx
cmpq $8, %rbx
je .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq 16(%rsp,%rcx,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $2048000, %rsi # imm = 0x1F4000
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
leaq 1(%rcx), %rdx
addq $2048000, %rax # imm = 0x1F4000
testq %rcx, %rcx
movq %rdx, %rcx
je .LBB1_3
# %bb.6:
movabsq $549755814016000, %r14 # imm = 0x1F4000001F400
movabsq $137438953504, %rbx # imm = 0x2000000020
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %r8
leaq 176(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $8192000, %edx # imm = 0x7D0000
movl $1, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 176(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 144(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9mulKernelPiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %r8
leaq 48(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $8192000, %edx # imm = 0x7D0000
movl $2, %ecx
callq hipMemcpyAsync
leaq 184(%rsp), %rdi
leaq 24(%rsp), %rsi
movq 40(%rsp), %r8
movl $8192000, %edx # imm = 0x7D0000
movl $1, %ecx
callq hipMemcpyAsync
movq 40(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 184(%rsp), %rax
movq 168(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 144(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9mulKernelPiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
leaq 56(%rsp), %rdi
leaq 168(%rsp), %rsi
movq 40(%rsp), %r8
movl $8192000, %edx # imm = 0x7D0000
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 48(%rsp), %rdx
movq 56(%rsp), %rsi
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movl (%rax,%rbx,4), %edi
addl %edi, %edi
cmpl (%rdx,%rbx,4), %edi
jne .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl (%rcx,%rbx,4), %edi
addl %edi, %edi
cmpl (%rsi,%rbx,4), %edi
jne .LBB1_13
# %bb.17: # in Loop: Header=BB1_11 Depth=1
incq %rbx
cmpq $2048000, %rbx # imm = 0x1F4000
jne .LBB1_11
jmp .LBB1_14
.LBB1_13:
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
addl %esi, %esi
movq 48(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rax
movl (%rax,%rbx,4), %esi
addl %esi, %esi
movq 56(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB1_14: # %.loopexit.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_15: # %.loopexit
# =>This Inner Loop Header: Depth=1
movq 32(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
movq 16(%rsp,%rbx,8), %rdi
callq hipHostFree
movq 48(%rsp,%rbx,8), %rdi
callq hipHostFree
incq %rbx
cmpq $1, %rbx
je .LBB1_15
# %bb.16:
callq hipDeviceReset
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mulKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mulKernelPiS_,@object # @_Z9mulKernelPiS_
.section .rodata,"a",@progbits
.globl _Z9mulKernelPiS_
.p2align 3, 0x0
_Z9mulKernelPiS_:
.quad _Z24__device_stub__mulKernelPiS_
.size _Z9mulKernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time to calculate results: %f ms.\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: CPU and GPU result [%d] do not match\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU0:%d GPU0:%d\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU1:%d GPU1:%d\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mulKernelPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mulKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mulKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9mulKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3e7fff, PT ; /* 0x003e7fff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ SHF.L.U32 R7, R2, 0x1, RZ ; /* 0x0000000102077819 */
/* 0x004fca00000006ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mulKernelPiS_
.globl _Z9mulKernelPiS_
.p2align 8
.type _Z9mulKernelPiS_,@function
_Z9mulKernelPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3e8000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mulKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mulKernelPiS_, .Lfunc_end0-_Z9mulKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mulKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mulKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008ef03_00000000-6_ex2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9mulKernelPiS_PiS_
.type _Z30__device_stub__Z9mulKernelPiS_PiS_, @function
_Z30__device_stub__Z9mulKernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9mulKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9mulKernelPiS_PiS_, .-_Z30__device_stub__Z9mulKernelPiS_PiS_
.globl _Z9mulKernelPiS_
.type _Z9mulKernelPiS_, @function
_Z9mulKernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9mulKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9mulKernelPiS_, .-_Z9mulKernelPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Time to calculate results: %f ms.\n"
.align 8
.LC1:
.string "Error: CPU and GPU result [%d] do not match\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU0:%d GPU0:%d\n"
.LC3:
.string "CPU1:%d GPU1:%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $144, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 48(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 64(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 80(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 56(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 72(%rsp), %rdi
movl $8192000, %esi
call cudaMallocHost@PLT
leaq 88(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $8192000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movq 48(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $2048000, %rax
jne .L12
movl $2048000, %edx
movl $0, %eax
.L13:
movq 56(%rsp), %rcx
movl %edx, (%rcx,%rax)
addq $4, %rax
addl $1, %edx
cmpq $8192000, %rax
jne .L13
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $128000, 24(%rsp)
movl $128000, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdi
movq 112(%rsp), %r8
movl $1, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
movl 44(%rsp), %ecx
movq 112(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
leaq 96(%rsp), %rsi
leaq 64(%rsp), %rdi
movq 112(%rsp), %r8
movl $2, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
leaq 56(%rsp), %rsi
leaq 88(%rsp), %rdi
movq 120(%rsp), %r8
movl $1, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
movl 44(%rsp), %ecx
movq 120(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L15:
leaq 104(%rsp), %rsi
leaq 72(%rsp), %rdi
movq 120(%rsp), %r8
movl $2, %ecx
movl $8192000, %edx
call cudaMemcpyAsync@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rdi
movq 72(%rsp), %rsi
movl $0, %ebx
.L18:
movl (%rcx,%rbx,4), %eax
addl %eax, %eax
cmpl (%rdx,%rbx,4), %eax
jne .L16
movl (%rdi,%rbx,4), %eax
addl %eax, %eax
cmpl (%rsi,%rbx,4), %eax
jne .L16
addq $1, %rbx
cmpq $2048000, %rbx
jne .L18
jmp .L19
.L26:
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z30__device_stub__Z9mulKernelPiS_PiS_
jmp .L14
.L27:
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z30__device_stub__Z9mulKernelPiS_PiS_
jmp .L15
.L16:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 64(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movq 48(%rsp), %rax
movl (%rax,%rbx,4), %edx
addl %edx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movq 56(%rsp), %rax
movl (%rax,%rbx,4), %edx
addl %edx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
movq 112(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 64(%rsp), %rdi
call cudaFreeHost@PLT
movq 120(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rdi
call cudaFreeHost@PLT
call cudaDeviceReset@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9mulKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mulKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex2.hip"
.globl _Z24__device_stub__mulKernelPiS_ # -- Begin function _Z24__device_stub__mulKernelPiS_
.p2align 4, 0x90
.type _Z24__device_stub__mulKernelPiS_,@function
_Z24__device_stub__mulKernelPiS_: # @_Z24__device_stub__mulKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9mulKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__mulKernelPiS_, .Lfunc_end0-_Z24__device_stub__mulKernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $200, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $32, %rdi
callq hipStreamCreate
leaq (%rsp,%rbx), %rdi
addq $16, %rdi
movl $8192000, %esi # imm = 0x7D0000
xorl %edx, %edx
callq hipHostMalloc
leaq (%rsp,%rbx), %rdi
addq $48, %rdi
movl $8192000, %esi # imm = 0x7D0000
xorl %edx, %edx
callq hipHostMalloc
leaq (%rsp,%rbx), %rdi
addq $176, %rdi
movl $8192000, %esi # imm = 0x7D0000
callq hipMalloc
leaq (%rsp,%rbx), %rdi
addq $160, %rdi
movl $8192000, %esi # imm = 0x7D0000
callq hipMalloc
addq $8, %rbx
cmpq $8, %rbx
je .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq 16(%rsp,%rcx,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $2048000, %rsi # imm = 0x1F4000
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
leaq 1(%rcx), %rdx
addq $2048000, %rax # imm = 0x1F4000
testq %rcx, %rcx
movq %rdx, %rcx
je .LBB1_3
# %bb.6:
movabsq $549755814016000, %r14 # imm = 0x1F4000001F400
movabsq $137438953504, %rbx # imm = 0x2000000020
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %r8
leaq 176(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $8192000, %edx # imm = 0x7D0000
movl $1, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 176(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 144(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9mulKernelPiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %r8
leaq 48(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $8192000, %edx # imm = 0x7D0000
movl $2, %ecx
callq hipMemcpyAsync
leaq 184(%rsp), %rdi
leaq 24(%rsp), %rsi
movq 40(%rsp), %r8
movl $8192000, %edx # imm = 0x7D0000
movl $1, %ecx
callq hipMemcpyAsync
movq 40(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 184(%rsp), %rax
movq 168(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 144(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9mulKernelPiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
leaq 56(%rsp), %rdi
leaq 168(%rsp), %rsi
movq 40(%rsp), %r8
movl $8192000, %edx # imm = 0x7D0000
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 48(%rsp), %rdx
movq 56(%rsp), %rsi
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movl (%rax,%rbx,4), %edi
addl %edi, %edi
cmpl (%rdx,%rbx,4), %edi
jne .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl (%rcx,%rbx,4), %edi
addl %edi, %edi
cmpl (%rsi,%rbx,4), %edi
jne .LBB1_13
# %bb.17: # in Loop: Header=BB1_11 Depth=1
incq %rbx
cmpq $2048000, %rbx # imm = 0x1F4000
jne .LBB1_11
jmp .LBB1_14
.LBB1_13:
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
addl %esi, %esi
movq 48(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rax
movl (%rax,%rbx,4), %esi
addl %esi, %esi
movq 56(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB1_14: # %.loopexit.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_15: # %.loopexit
# =>This Inner Loop Header: Depth=1
movq 32(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
movq 16(%rsp,%rbx,8), %rdi
callq hipHostFree
movq 48(%rsp,%rbx,8), %rdi
callq hipHostFree
incq %rbx
cmpq $1, %rbx
je .LBB1_15
# %bb.16:
callq hipDeviceReset
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mulKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mulKernelPiS_,@object # @_Z9mulKernelPiS_
.section .rodata,"a",@progbits
.globl _Z9mulKernelPiS_
.p2align 3, 0x0
_Z9mulKernelPiS_:
.quad _Z24__device_stub__mulKernelPiS_
.size _Z9mulKernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time to calculate results: %f ms.\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: CPU and GPU result [%d] do not match\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU0:%d GPU0:%d\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU1:%d GPU1:%d\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mulKernelPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mulKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mulKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void cudaHello()
{
int const threadId = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My threadId is %d\n", threadId);
}
int main()
{
int const TB = 1; // Number of thread blocks
int const TPB = 256; // Number of threads per block
cudaHello<<<TB, TPB>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z9cudaHellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void cudaHello()
{
int const threadId = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My threadId is %d\n", threadId);
}
int main()
{
int const TB = 1; // Number of thread blocks
int const TPB = 256; // Number of threads per block
cudaHello<<<TB, TPB>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_00170f74_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9cudaHellovv
.type _Z27__device_stub__Z9cudaHellovv, @function
_Z27__device_stub__Z9cudaHellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9cudaHellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9cudaHellovv, .-_Z27__device_stub__Z9cudaHellovv
.globl _Z9cudaHellov
.type _Z9cudaHellov, @function
_Z9cudaHellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9cudaHellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9cudaHellov, .-_Z9cudaHellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z27__device_stub__Z9cudaHellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9cudaHellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaHellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void cudaHello()
{
int const threadId = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My threadId is %d\n", threadId);
}
int main()
{
int const TB = 1; // Number of thread blocks
int const TPB = 256; // Number of threads per block
cudaHello<<<TB, TPB>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cudaHello()
{
int const threadId = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My threadId is %d\n", threadId);
}
int main()
{
int const TB = 1; // Number of thread blocks
int const TPB = 256; // Number of threads per block
cudaHello<<<TB, TPB>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cudaHello()
{
int const threadId = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My threadId is %d\n", threadId);
}
int main()
{
int const TB = 1; // Number of thread blocks
int const TPB = 256; // Number of threads per block
cudaHello<<<TB, TPB>>>();
hipDeviceSynchronize();
} | .text
.file "helloworld.hip"
.globl _Z24__device_stub__cudaHellov # -- Begin function _Z24__device_stub__cudaHellov
.p2align 4, 0x90
.type _Z24__device_stub__cudaHellov,@function
_Z24__device_stub__cudaHellov: # @_Z24__device_stub__cudaHellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9cudaHellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__cudaHellov, .Lfunc_end0-_Z24__device_stub__cudaHellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9cudaHellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaHellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cudaHellov,@object # @_Z9cudaHellov
.section .rodata,"a",@progbits
.globl _Z9cudaHellov
.p2align 3, 0x0
_Z9cudaHellov:
.quad _Z24__device_stub__cudaHellov
.size _Z9cudaHellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cudaHellov"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cudaHellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cudaHellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00170f74_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9cudaHellovv
.type _Z27__device_stub__Z9cudaHellovv, @function
_Z27__device_stub__Z9cudaHellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9cudaHellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9cudaHellovv, .-_Z27__device_stub__Z9cudaHellovv
.globl _Z9cudaHellov
.type _Z9cudaHellov, @function
_Z9cudaHellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9cudaHellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9cudaHellov, .-_Z9cudaHellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z27__device_stub__Z9cudaHellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9cudaHellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaHellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloworld.hip"
.globl _Z24__device_stub__cudaHellov # -- Begin function _Z24__device_stub__cudaHellov
.p2align 4, 0x90
.type _Z24__device_stub__cudaHellov,@function
_Z24__device_stub__cudaHellov: # @_Z24__device_stub__cudaHellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9cudaHellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__cudaHellov, .Lfunc_end0-_Z24__device_stub__cudaHellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9cudaHellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaHellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cudaHellov,@object # @_Z9cudaHellov
.section .rodata,"a",@progbits
.globl _Z9cudaHellov
.p2align 3, 0x0
_Z9cudaHellov:
.quad _Z24__device_stub__cudaHellov
.size _Z9cudaHellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cudaHellov"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cudaHellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cudaHellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduce(double *a,double *z, int sizeOut){
int tid = blockDim.x*blockIdx.x + threadIdx.x;
if(tid > N/2)return;
extern __shared__ double subTotals[];
subTotals[threadIdx.x]=(a[tid*2]+a[tid*2+1])/2;//sum every two values using all threads
__syncthreads();
int level=2;
while ((blockDim.x/level) >= sizeOut){//keep halving values until sizeout remains
if(threadIdx.x % level==0){//use half threads every iteration
subTotals[threadIdx.x]=(subTotals[threadIdx.x]+subTotals[threadIdx.x+(level/2)])/2;
}
__syncthreads();//we have to sync threads every time here :(
level = level * 2;
}
level = level /2;
if(threadIdx.x % level==0){
z[tid/level] = subTotals[threadIdx.x];
}
} | code for sm_80
Function : _Z6reducePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R2 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xc350, PT ; /* 0x0000c3500000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00a0*/ LDG.E.64 R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fca00078e00ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc80000011603 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fe20000000f00 */
/*0100*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004e0c0000000008 */
/*0110*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001e0e0000000000 */
/*0120*/ STS.64 [R2.X8], R6 ; /* 0x0000000602007388 */
/* 0x0011e80000008a00 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @!P0 BRA 0x4d0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.SHL.U32 R3, R2, 0x8, RZ ; /* 0x0000000802037824 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fc800078e00ff */
/*0170*/ I2F.U32.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e620000209000 */
/*0180*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25070 */
/*0190*/ BSSY B0, 0x360 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0005 */
/*01b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*01c0*/ IADD3 R6, R4, 0xffffffe, RZ ; /* 0x0ffffffe04067810 */
/* 0x003fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*01f0*/ IMAD.MOV R8, RZ, RZ, -R7 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a07 */
/*0200*/ IMAD R9, R8, R5, RZ ; /* 0x0000000508097224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*0220*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fca00078e00ff */
/*0230*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fca0007ffe1ff */
/*0240*/ IMAD R8, R5, R7, R2 ; /* 0x0000000705087224 */
/* 0x000fca00078e0202 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f06070 */
/*0260*/ @P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a05 */
/*0270*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f06070 */
/*0280*/ @P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108080824 */
/* 0x000fe200078e0a05 */
/*0290*/ @!P1 LOP3.LUT R8, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff089212 */
/* 0x000fc800078e33ff */
/*02a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*02b0*/ @P0 BRA 0x350 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*02c0*/ LEA.HI R4, R5, R5, RZ, 0x1 ; /* 0x0000000505047211 */
/* 0x000fe200078f08ff */
/*02d0*/ LDS.64 R6, [R2.X8] ; /* 0x0000000002067984 */
/* 0x000fe60000008a00 */
/*02e0*/ SHF.L.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047819 */
/* 0x000fc800000006ff */
/*02f0*/ LOP3.LUT R4, R4, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff804047812 */
/* 0x000fca00078ec0ff */
/*0300*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x000fca00078e0204 */
/*0310*/ LDS.64 R8, [R4] ; /* 0x0000000004087984 */
/* 0x000e240000000a00 */
/*0320*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e0c0000000008 */
/*0330*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001e0e0000000000 */
/*0340*/ STS.64 [R2.X8], R6 ; /* 0x0000000602007388 */
/* 0x0011e80000008a00 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0380*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a05 */
/*0390*/ ISETP.NE.U32.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f45070 */
/*03a0*/ I2F.U32.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e700000209000 */
/*03b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*03c0*/ IADD3 R6, R4, 0xffffffe, RZ ; /* 0x0ffffffe04067810 */
/* 0x003fcc0007ffe0ff */
/*03d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*03e0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x001fe20000000f00 */
/*03f0*/ IMAD R9, R9, R7, RZ ; /* 0x0000000709097224 */
/* 0x002fc800078e02ff */
/*0400*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*0410*/ IMAD.HI.U32 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a27 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.MOV R8, RZ, RZ, -R7 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a07 */
/*0430*/ IMAD R8, R5, R8, c[0x0][0x0] ; /* 0x0000000005087624 */
/* 0x000fca00078e0208 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f06070 */
/*0450*/ @P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108080824 */
/* 0x000fe200078e0a05 */
/*0460*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0470*/ ISETP.GE.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f26070 */
/*0480*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0490*/ @!P2 LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff07a212 */
/* 0x000fc800078e33ff */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06070 */
/*04b0*/ @P0 BRA 0x170 ; /* 0xfffffcb000000947 */
/* 0x000fea000383ffff */
/*04c0*/ LOP3.LUT R3, R10, 0x7ffffffe, RZ, 0xc0, !PT ; /* 0x7ffffffe0a037812 */
/* 0x000fc800078ec0ff */
/*04d0*/ I2F.U32.RP R6, R3 ; /* 0x0000000300067306 */
/* 0x001e220000209000 */
/*04e0*/ ISETP.NE.U32.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f25070 */
/*04f0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0500*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0510*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0520*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x001fe20000000f00 */
/*0530*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0540*/ IMAD R7, R8, R3, RZ ; /* 0x0000000308077224 */
/* 0x000fc800078e02ff */
/*0550*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0560*/ LOP3.LUT R7, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff077212 */
/* 0x000fca00078e33ff */
/*0570*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0590*/ IMAD R8, R3, R5, R2 ; /* 0x0000000503087224 */
/* 0x000fca00078e0202 */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*05b0*/ @P0 IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a03 */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*05d0*/ @P0 IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a03 */
/*05e0*/ SEL R8, R7, R8, !P1 ; /* 0x0000000807087207 */
/* 0x000fc80004800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0600*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0610*/ IABS R9, R3.reuse ; /* 0x0000000300097213 */
/* 0x080fe40000000000 */
/*0620*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*0630*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e220000209400 */
/*0640*/ IABS R12, R3.reuse ; /* 0x00000003000c7213 */
/* 0x080fe40000000000 */
/*0650*/ LOP3.LUT R0, R0, R3, RZ, 0x3c, !PT ; /* 0x0000000300007212 */
/* 0x000fc800078e3cff */
/*0660*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*0670*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0680*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0690*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*06b0*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x002fca0007ffe0ff */
/*06c0*/ IMAD R11, R8, R9, RZ ; /* 0x00000009080b7224 */
/* 0x000fe400078e02ff */
/*06d0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*06e0*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fc800078e0004 */
/*06f0*/ IMAD.MOV R11, RZ, RZ, -R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a0c */
/*0700*/ IMAD.HI.U32 R6, R5, R8, RZ ; /* 0x0000000805067227 */
/* 0x000fe400078e00ff */
/*0710*/ LDS.64 R4, [R2.X8] ; /* 0x0000000002047984 */
/* 0x0000640000008a00 */
/*0720*/ IMAD R8, R6, R11, R8 ; /* 0x0000000b06087224 */
/* 0x000fca00078e0208 */
/*0730*/ ISETP.GT.U32.AND P2, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fda0003f44070 */
/*0740*/ @!P2 IADD3 R8, R8, -R9.reuse, RZ ; /* 0x800000090808a210 */
/* 0x080fe40007ffe0ff */
/*0750*/ @!P2 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606a810 */
/* 0x000fe40007ffe0ff */
/*0760*/ ISETP.GE.U32.AND P1, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fda0003f26070 */
/*0770*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0780*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f25270 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe400078e00ff */
/*07a0*/ @!P0 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff068224 */
/* 0x000fca00078e0a06 */
/*07b0*/ SEL R2, R7, R6, !P1 ; /* 0x0000000607027207 */
/* 0x001fca0004800000 */
/*07c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*07d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduce(double *a,double *z, int sizeOut){
int tid = blockDim.x*blockIdx.x + threadIdx.x;
if(tid > N/2)return;
extern __shared__ double subTotals[];
subTotals[threadIdx.x]=(a[tid*2]+a[tid*2+1])/2;//sum every two values using all threads
__syncthreads();
int level=2;
while ((blockDim.x/level) >= sizeOut){//keep halving values until sizeout remains
if(threadIdx.x % level==0){//use half threads every iteration
subTotals[threadIdx.x]=(subTotals[threadIdx.x]+subTotals[threadIdx.x+(level/2)])/2;
}
__syncthreads();//we have to sync threads every time here :(
level = level * 2;
}
level = level /2;
if(threadIdx.x % level==0){
z[tid/level] = subTotals[threadIdx.x];
}
} | .file "tmpxft_000017e9_00000000-6_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6reducePdS_iPdS_i
.type _Z28__device_stub__Z6reducePdS_iPdS_i, @function
_Z28__device_stub__Z6reducePdS_iPdS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6reducePdS_iPdS_i, .-_Z28__device_stub__Z6reducePdS_iPdS_i
.globl _Z6reducePdS_i
.type _Z6reducePdS_i, @function
_Z6reducePdS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6reducePdS_i, .-_Z6reducePdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6reducePdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduce(double *a,double *z, int sizeOut){
int tid = blockDim.x*blockIdx.x + threadIdx.x;
if(tid > N/2)return;
extern __shared__ double subTotals[];
subTotals[threadIdx.x]=(a[tid*2]+a[tid*2+1])/2;//sum every two values using all threads
__syncthreads();
int level=2;
while ((blockDim.x/level) >= sizeOut){//keep halving values until sizeout remains
if(threadIdx.x % level==0){//use half threads every iteration
subTotals[threadIdx.x]=(subTotals[threadIdx.x]+subTotals[threadIdx.x+(level/2)])/2;
}
__syncthreads();//we have to sync threads every time here :(
level = level * 2;
}
level = level /2;
if(threadIdx.x % level==0){
z[tid/level] = subTotals[threadIdx.x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce(double *a,double *z, int sizeOut){
int tid = blockDim.x*blockIdx.x + threadIdx.x;
if(tid > N/2)return;
extern __shared__ double subTotals[];
subTotals[threadIdx.x]=(a[tid*2]+a[tid*2+1])/2;//sum every two values using all threads
__syncthreads();
int level=2;
while ((blockDim.x/level) >= sizeOut){//keep halving values until sizeout remains
if(threadIdx.x % level==0){//use half threads every iteration
subTotals[threadIdx.x]=(subTotals[threadIdx.x]+subTotals[threadIdx.x+(level/2)])/2;
}
__syncthreads();//we have to sync threads every time here :(
level = level * 2;
}
level = level /2;
if(threadIdx.x % level==0){
z[tid/level] = subTotals[threadIdx.x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce(double *a,double *z, int sizeOut){
int tid = blockDim.x*blockIdx.x + threadIdx.x;
if(tid > N/2)return;
extern __shared__ double subTotals[];
subTotals[threadIdx.x]=(a[tid*2]+a[tid*2+1])/2;//sum every two values using all threads
__syncthreads();
int level=2;
while ((blockDim.x/level) >= sizeOut){//keep halving values until sizeout remains
if(threadIdx.x % level==0){//use half threads every iteration
subTotals[threadIdx.x]=(subTotals[threadIdx.x]+subTotals[threadIdx.x+(level/2)])/2;
}
__syncthreads();//we have to sync threads every time here :(
level = level * 2;
}
level = level /2;
if(threadIdx.x % level==0){
z[tid/level] = subTotals[threadIdx.x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reducePdS_i
.globl _Z6reducePdS_i
.p2align 8
.type _Z6reducePdS_i,@function
_Z6reducePdS_i:
s_load_b32 s2, s[0:1], 0x24
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmpx_gt_i32_e32 0xc351, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
v_lshlrev_b32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_lshr_b32 s5, s2, 1
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_mov_b32 s4, 1
s_cmp_lt_u32 s5, s3
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[2:3], 0.5
v_lshl_add_u32 v2, v0, 3, 0
ds_store_b64 v2, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s5, s4, 1
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v3, s5
s_sub_i32 s7, 0, s5
s_barrier
buffer_gl0_inv
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_readfirstlane_b32 s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s6
s_mul_hi_u32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_mul_hi_u32 s6, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s6, s5
s_add_i32 s8, s6, 1
s_sub_i32 s7, s2, s7
s_sub_i32 s9, s7, s5
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s3
s_cbranch_scc0 .LBB0_6
.LBB0_4:
s_mov_b32 s4, s5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, s5, v0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_3
s_lshr_b32 s6, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s6, v0
v_lshl_add_u32 v5, v3, 3, 0
ds_load_b64 v[3:4], v2
ds_load_b64 v[5:6], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0.5
ds_store_b64 v2, v[3:4]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_and_b32 s4, s4, 0x7ffffffe
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s4, -1
v_and_b32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
v_ashrrev_i32_e32 v4, 31, v1
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
ds_load_b64 v[2:3], v2
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reducePdS_i, .Lfunc_end0-_Z6reducePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce(double *a,double *z, int sizeOut){
int tid = blockDim.x*blockIdx.x + threadIdx.x;
if(tid > N/2)return;
extern __shared__ double subTotals[];
subTotals[threadIdx.x]=(a[tid*2]+a[tid*2+1])/2;//sum every two values using all threads
__syncthreads();
int level=2;
while ((blockDim.x/level) >= sizeOut){//keep halving values until sizeout remains
if(threadIdx.x % level==0){//use half threads every iteration
subTotals[threadIdx.x]=(subTotals[threadIdx.x]+subTotals[threadIdx.x+(level/2)])/2;
}
__syncthreads();//we have to sync threads every time here :(
level = level * 2;
}
level = level /2;
if(threadIdx.x % level==0){
z[tid/level] = subTotals[threadIdx.x];
}
} | .text
.file "reduce.hip"
.globl _Z21__device_stub__reducePdS_i # -- Begin function _Z21__device_stub__reducePdS_i
.p2align 4, 0x90
.type _Z21__device_stub__reducePdS_i,@function
_Z21__device_stub__reducePdS_i: # @_Z21__device_stub__reducePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePdS_i, .Lfunc_end0-_Z21__device_stub__reducePdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePdS_i,@object # @_Z6reducePdS_i
.section .rodata,"a",@progbits
.globl _Z6reducePdS_i
.p2align 3, 0x0
_Z6reducePdS_i:
.quad _Z21__device_stub__reducePdS_i
.size _Z6reducePdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6reducePdS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6reducePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R2 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xc350, PT ; /* 0x0000c3500000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00a0*/ LDG.E.64 R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fca00078e00ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc80000011603 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fe20000000f00 */
/*0100*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004e0c0000000008 */
/*0110*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001e0e0000000000 */
/*0120*/ STS.64 [R2.X8], R6 ; /* 0x0000000602007388 */
/* 0x0011e80000008a00 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @!P0 BRA 0x4d0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.SHL.U32 R3, R2, 0x8, RZ ; /* 0x0000000802037824 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fc800078e00ff */
/*0170*/ I2F.U32.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e620000209000 */
/*0180*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25070 */
/*0190*/ BSSY B0, 0x360 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0005 */
/*01b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*01c0*/ IADD3 R6, R4, 0xffffffe, RZ ; /* 0x0ffffffe04067810 */
/* 0x003fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*01f0*/ IMAD.MOV R8, RZ, RZ, -R7 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a07 */
/*0200*/ IMAD R9, R8, R5, RZ ; /* 0x0000000508097224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*0220*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fca00078e00ff */
/*0230*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fca0007ffe1ff */
/*0240*/ IMAD R8, R5, R7, R2 ; /* 0x0000000705087224 */
/* 0x000fca00078e0202 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f06070 */
/*0260*/ @P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a05 */
/*0270*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f06070 */
/*0280*/ @P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108080824 */
/* 0x000fe200078e0a05 */
/*0290*/ @!P1 LOP3.LUT R8, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff089212 */
/* 0x000fc800078e33ff */
/*02a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*02b0*/ @P0 BRA 0x350 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*02c0*/ LEA.HI R4, R5, R5, RZ, 0x1 ; /* 0x0000000505047211 */
/* 0x000fe200078f08ff */
/*02d0*/ LDS.64 R6, [R2.X8] ; /* 0x0000000002067984 */
/* 0x000fe60000008a00 */
/*02e0*/ SHF.L.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047819 */
/* 0x000fc800000006ff */
/*02f0*/ LOP3.LUT R4, R4, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff804047812 */
/* 0x000fca00078ec0ff */
/*0300*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x000fca00078e0204 */
/*0310*/ LDS.64 R8, [R4] ; /* 0x0000000004087984 */
/* 0x000e240000000a00 */
/*0320*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e0c0000000008 */
/*0330*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001e0e0000000000 */
/*0340*/ STS.64 [R2.X8], R6 ; /* 0x0000000602007388 */
/* 0x0011e80000008a00 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0380*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a05 */
/*0390*/ ISETP.NE.U32.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f45070 */
/*03a0*/ I2F.U32.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e700000209000 */
/*03b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*03c0*/ IADD3 R6, R4, 0xffffffe, RZ ; /* 0x0ffffffe04067810 */
/* 0x003fcc0007ffe0ff */
/*03d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*03e0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x001fe20000000f00 */
/*03f0*/ IMAD R9, R9, R7, RZ ; /* 0x0000000709097224 */
/* 0x002fc800078e02ff */
/*0400*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*0410*/ IMAD.HI.U32 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a27 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.MOV R8, RZ, RZ, -R7 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a07 */
/*0430*/ IMAD R8, R5, R8, c[0x0][0x0] ; /* 0x0000000005087624 */
/* 0x000fca00078e0208 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f06070 */
/*0450*/ @P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108080824 */
/* 0x000fe200078e0a05 */
/*0460*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0470*/ ISETP.GE.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f26070 */
/*0480*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0490*/ @!P2 LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff07a212 */
/* 0x000fc800078e33ff */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06070 */
/*04b0*/ @P0 BRA 0x170 ; /* 0xfffffcb000000947 */
/* 0x000fea000383ffff */
/*04c0*/ LOP3.LUT R3, R10, 0x7ffffffe, RZ, 0xc0, !PT ; /* 0x7ffffffe0a037812 */
/* 0x000fc800078ec0ff */
/*04d0*/ I2F.U32.RP R6, R3 ; /* 0x0000000300067306 */
/* 0x001e220000209000 */
/*04e0*/ ISETP.NE.U32.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f25070 */
/*04f0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0500*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0510*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0520*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x001fe20000000f00 */
/*0530*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0540*/ IMAD R7, R8, R3, RZ ; /* 0x0000000308077224 */
/* 0x000fc800078e02ff */
/*0550*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0560*/ LOP3.LUT R7, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff077212 */
/* 0x000fca00078e33ff */
/*0570*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0590*/ IMAD R8, R3, R5, R2 ; /* 0x0000000503087224 */
/* 0x000fca00078e0202 */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*05b0*/ @P0 IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a03 */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*05d0*/ @P0 IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a03 */
/*05e0*/ SEL R8, R7, R8, !P1 ; /* 0x0000000807087207 */
/* 0x000fc80004800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0600*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0610*/ IABS R9, R3.reuse ; /* 0x0000000300097213 */
/* 0x080fe40000000000 */
/*0620*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*0630*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e220000209400 */
/*0640*/ IABS R12, R3.reuse ; /* 0x00000003000c7213 */
/* 0x080fe40000000000 */
/*0650*/ LOP3.LUT R0, R0, R3, RZ, 0x3c, !PT ; /* 0x0000000300007212 */
/* 0x000fc800078e3cff */
/*0660*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*0670*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0680*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0690*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*06b0*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x002fca0007ffe0ff */
/*06c0*/ IMAD R11, R8, R9, RZ ; /* 0x00000009080b7224 */
/* 0x000fe400078e02ff */
/*06d0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*06e0*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fc800078e0004 */
/*06f0*/ IMAD.MOV R11, RZ, RZ, -R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a0c */
/*0700*/ IMAD.HI.U32 R6, R5, R8, RZ ; /* 0x0000000805067227 */
/* 0x000fe400078e00ff */
/*0710*/ LDS.64 R4, [R2.X8] ; /* 0x0000000002047984 */
/* 0x0000640000008a00 */
/*0720*/ IMAD R8, R6, R11, R8 ; /* 0x0000000b06087224 */
/* 0x000fca00078e0208 */
/*0730*/ ISETP.GT.U32.AND P2, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fda0003f44070 */
/*0740*/ @!P2 IADD3 R8, R8, -R9.reuse, RZ ; /* 0x800000090808a210 */
/* 0x080fe40007ffe0ff */
/*0750*/ @!P2 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606a810 */
/* 0x000fe40007ffe0ff */
/*0760*/ ISETP.GE.U32.AND P1, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fda0003f26070 */
/*0770*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0780*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f25270 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe400078e00ff */
/*07a0*/ @!P0 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff068224 */
/* 0x000fca00078e0a06 */
/*07b0*/ SEL R2, R7, R6, !P1 ; /* 0x0000000607027207 */
/* 0x001fca0004800000 */
/*07c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*07d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reducePdS_i
.globl _Z6reducePdS_i
.p2align 8
.type _Z6reducePdS_i,@function
_Z6reducePdS_i:
s_load_b32 s2, s[0:1], 0x24
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmpx_gt_i32_e32 0xc351, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
v_lshlrev_b32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_lshr_b32 s5, s2, 1
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_mov_b32 s4, 1
s_cmp_lt_u32 s5, s3
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[2:3], 0.5
v_lshl_add_u32 v2, v0, 3, 0
ds_store_b64 v2, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s5, s4, 1
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v3, s5
s_sub_i32 s7, 0, s5
s_barrier
buffer_gl0_inv
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_readfirstlane_b32 s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s6
s_mul_hi_u32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_mul_hi_u32 s6, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s6, s5
s_add_i32 s8, s6, 1
s_sub_i32 s7, s2, s7
s_sub_i32 s9, s7, s5
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s3
s_cbranch_scc0 .LBB0_6
.LBB0_4:
s_mov_b32 s4, s5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, s5, v0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_3
s_lshr_b32 s6, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s6, v0
v_lshl_add_u32 v5, v3, 3, 0
ds_load_b64 v[3:4], v2
ds_load_b64 v[5:6], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0.5
ds_store_b64 v2, v[3:4]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_and_b32 s4, s4, 0x7ffffffe
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s4, -1
v_and_b32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
v_ashrrev_i32_e32 v4, 31, v1
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
ds_load_b64 v[2:3], v2
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reducePdS_i, .Lfunc_end0-_Z6reducePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000017e9_00000000-6_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6reducePdS_iPdS_i
.type _Z28__device_stub__Z6reducePdS_iPdS_i, @function
_Z28__device_stub__Z6reducePdS_iPdS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6reducePdS_iPdS_i, .-_Z28__device_stub__Z6reducePdS_iPdS_i
.globl _Z6reducePdS_i
.type _Z6reducePdS_i, @function
_Z6reducePdS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6reducePdS_i, .-_Z6reducePdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6reducePdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce.hip"
.globl _Z21__device_stub__reducePdS_i # -- Begin function _Z21__device_stub__reducePdS_i
.p2align 4, 0x90
.type _Z21__device_stub__reducePdS_i,@function
_Z21__device_stub__reducePdS_i: # @_Z21__device_stub__reducePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePdS_i, .Lfunc_end0-_Z21__device_stub__reducePdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePdS_i,@object # @_Z6reducePdS_i
.section .rodata,"a",@progbits
.globl _Z6reducePdS_i
.p2align 3, 0x0
_Z6reducePdS_i:
.quad _Z21__device_stub__reducePdS_i
.size _Z6reducePdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6reducePdS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void normalize_N(float* N, float* norm, int npix_per_component) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int c = blockIdx.y*blockDim.y + threadIdx.y;
if (i < npix_per_component) {
N[c*npix_per_component + i] = N[c*npix_per_component + i] / norm[i];
}
} | code for sm_80
Function : _Z11normalize_NPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*00a0*/ IMAD.WIDE R4, R0, R6, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0206 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R3, R2, c[0x0][0x4], R3 ; /* 0x0000010002037a24 */
/* 0x001fc800078e0203 */
/*00d0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0206 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0100*/ BSSY B0, 0x1c0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0110*/ MUFU.RCP R9, R4 ; /* 0x0000000400097308 */
/* 0x004e240000001000 */
/*0120*/ FFMA R0, -R4, R9, 1 ; /* 0x3f80000004007423 */
/* 0x001fc80000000109 */
/*0130*/ FFMA R0, R9, R0, R9 ; /* 0x0000000009007223 */
/* 0x000fe40000000009 */
/*0140*/ FCHK P0, R7, R4 ; /* 0x0000000407007302 */
/* 0x008e240000000000 */
/*0150*/ FFMA R9, R7, R0, RZ ; /* 0x0000000007097223 */
/* 0x000fc800000000ff */
/*0160*/ FFMA R6, -R4, R9, R7 ; /* 0x0000000904067223 */
/* 0x000fc80000000107 */
/*0170*/ FFMA R9, R0, R6, R9 ; /* 0x0000000600097223 */
/* 0x000fe20000000009 */
/*0180*/ @!P0 BRA 0x1b0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0190*/ MOV R0, 0x1b0 ; /* 0x000001b000007802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*01f0*/ BSSY B1, 0x840 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.U32.HI R5, RZ, 0x17, R7.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011607 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0220*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0240*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0250*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fc40007ffe0ff */
/*0260*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0280*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0290*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02a0*/ @!P0 BRA 0x420 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02e0*/ @P0 BRA 0x820 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0300*/ @!P0 BRA 0x800 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0320*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*0340*/ @!P1 BRA !P2, 0x800 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0350*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0360*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0370*/ @P1 BRA 0x7e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03a0*/ @P0 BRA 0x7b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*03c0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03d0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 FFMA R8, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007088823 */
/* 0x000fe400000000ff */
/*0400*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*0410*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0420*/ LEA R4, R6, 0xc0800000, 0x17 ; /* 0xc080000006047811 */
/* 0x000fe200078eb8ff */
/*0430*/ BSSY B2, 0x7a0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0440*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe400078e0a04 */
/*0460*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0470*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0480*/ FADD.FTZ R7, -R9, -RZ ; /* 0x800000ff09077221 */
/* 0x000fc80000010100 */
/*0490*/ FFMA R11, R4, R7, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000007 */
/*04a0*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*04b0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R11, R7, R4, R8 ; /* 0x00000004070b7223 */
/* 0x000fc80000000008 */
/*04d0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*04e0*/ FFMA R8, R7, R12, R8 ; /* 0x0000000c07087223 */
/* 0x000fe20000000008 */
/*04f0*/ IADD3 R7, R5, 0x7f, -R6 ; /* 0x0000007f05077810 */
/* 0x000fc60007ffe806 */
/*0500*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fe4000000000c */
/*0510*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fc600078e020a */
/*0520*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0530*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0540*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0550*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 BRA 0x780 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0590*/ @P0 BRA 0x750 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05b0*/ @P0 BRA 0x790 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05d0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05e0*/ @!P0 BRA 0x790 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0600*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0610*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0620*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0630*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0640*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0650*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0670*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0690*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06a0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06c0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06e0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06f0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0700*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0710*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0730*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x790 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0760*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x790 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0790*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x830 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*07c0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x830 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*07f0*/ BRA 0x830 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0810*/ BRA 0x830 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0820*/ FADD.FTZ R4, R7, R4 ; /* 0x0000000407047221 */
/* 0x000fe40000010000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0004 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0870*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff78004007950 */
/* 0x000fea0003c3ffff */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void normalize_N(float* N, float* norm, int npix_per_component) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int c = blockIdx.y*blockDim.y + threadIdx.y;
if (i < npix_per_component) {
N[c*npix_per_component + i] = N[c*npix_per_component + i] / norm[i];
}
} | .file "tmpxft_0015bb47_00000000-6_normalize_N.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11normalize_NPfS_iPfS_i
.type _Z34__device_stub__Z11normalize_NPfS_iPfS_i, @function
_Z34__device_stub__Z11normalize_NPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11normalize_NPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11normalize_NPfS_iPfS_i, .-_Z34__device_stub__Z11normalize_NPfS_iPfS_i
.globl _Z11normalize_NPfS_i
.type _Z11normalize_NPfS_i, @function
_Z11normalize_NPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11normalize_NPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11normalize_NPfS_i, .-_Z11normalize_NPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11normalize_NPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11normalize_NPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void normalize_N(float* N, float* norm, int npix_per_component) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int c = blockIdx.y*blockDim.y + threadIdx.y;
if (i < npix_per_component) {
N[c*npix_per_component + i] = N[c*npix_per_component + i] / norm[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normalize_N(float* N, float* norm, int npix_per_component) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int c = blockIdx.y*blockDim.y + threadIdx.y;
if (i < npix_per_component) {
N[c*npix_per_component + i] = N[c*npix_per_component + i] / norm[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normalize_N(float* N, float* norm, int npix_per_component) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int c = blockIdx.y*blockDim.y + threadIdx.y;
if (i < npix_per_component) {
N[c*npix_per_component + i] = N[c*npix_per_component + i] / norm[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11normalize_NPfS_i
.globl _Z11normalize_NPfS_i
.p2align 8
.type _Z11normalize_NPfS_i,@function
_Z11normalize_NPfS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v0, v4, v0, v1
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11normalize_NPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11normalize_NPfS_i, .Lfunc_end0-_Z11normalize_NPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11normalize_NPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11normalize_NPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normalize_N(float* N, float* norm, int npix_per_component) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int c = blockIdx.y*blockDim.y + threadIdx.y;
if (i < npix_per_component) {
N[c*npix_per_component + i] = N[c*npix_per_component + i] / norm[i];
}
} | .text
.file "normalize_N.hip"
.globl _Z26__device_stub__normalize_NPfS_i # -- Begin function _Z26__device_stub__normalize_NPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__normalize_NPfS_i,@function
_Z26__device_stub__normalize_NPfS_i: # @_Z26__device_stub__normalize_NPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11normalize_NPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__normalize_NPfS_i, .Lfunc_end0-_Z26__device_stub__normalize_NPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11normalize_NPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11normalize_NPfS_i,@object # @_Z11normalize_NPfS_i
.section .rodata,"a",@progbits
.globl _Z11normalize_NPfS_i
.p2align 3, 0x0
_Z11normalize_NPfS_i:
.quad _Z26__device_stub__normalize_NPfS_i
.size _Z11normalize_NPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11normalize_NPfS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__normalize_NPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11normalize_NPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11normalize_NPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*00a0*/ IMAD.WIDE R4, R0, R6, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0206 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R3, R2, c[0x0][0x4], R3 ; /* 0x0000010002037a24 */
/* 0x001fc800078e0203 */
/*00d0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0206 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0100*/ BSSY B0, 0x1c0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0110*/ MUFU.RCP R9, R4 ; /* 0x0000000400097308 */
/* 0x004e240000001000 */
/*0120*/ FFMA R0, -R4, R9, 1 ; /* 0x3f80000004007423 */
/* 0x001fc80000000109 */
/*0130*/ FFMA R0, R9, R0, R9 ; /* 0x0000000009007223 */
/* 0x000fe40000000009 */
/*0140*/ FCHK P0, R7, R4 ; /* 0x0000000407007302 */
/* 0x008e240000000000 */
/*0150*/ FFMA R9, R7, R0, RZ ; /* 0x0000000007097223 */
/* 0x000fc800000000ff */
/*0160*/ FFMA R6, -R4, R9, R7 ; /* 0x0000000904067223 */
/* 0x000fc80000000107 */
/*0170*/ FFMA R9, R0, R6, R9 ; /* 0x0000000600097223 */
/* 0x000fe20000000009 */
/*0180*/ @!P0 BRA 0x1b0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0190*/ MOV R0, 0x1b0 ; /* 0x000001b000007802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*01f0*/ BSSY B1, 0x840 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.U32.HI R5, RZ, 0x17, R7.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011607 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0220*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0240*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0250*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fc40007ffe0ff */
/*0260*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0280*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0290*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02a0*/ @!P0 BRA 0x420 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02e0*/ @P0 BRA 0x820 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0300*/ @!P0 BRA 0x800 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0320*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*0340*/ @!P1 BRA !P2, 0x800 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0350*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0360*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0370*/ @P1 BRA 0x7e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03a0*/ @P0 BRA 0x7b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*03c0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03d0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 FFMA R8, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007088823 */
/* 0x000fe400000000ff */
/*0400*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*0410*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0420*/ LEA R4, R6, 0xc0800000, 0x17 ; /* 0xc080000006047811 */
/* 0x000fe200078eb8ff */
/*0430*/ BSSY B2, 0x7a0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0440*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe400078e0a04 */
/*0460*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0470*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0480*/ FADD.FTZ R7, -R9, -RZ ; /* 0x800000ff09077221 */
/* 0x000fc80000010100 */
/*0490*/ FFMA R11, R4, R7, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000007 */
/*04a0*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*04b0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R11, R7, R4, R8 ; /* 0x00000004070b7223 */
/* 0x000fc80000000008 */
/*04d0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*04e0*/ FFMA R8, R7, R12, R8 ; /* 0x0000000c07087223 */
/* 0x000fe20000000008 */
/*04f0*/ IADD3 R7, R5, 0x7f, -R6 ; /* 0x0000007f05077810 */
/* 0x000fc60007ffe806 */
/*0500*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fe4000000000c */
/*0510*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fc600078e020a */
/*0520*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0530*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0540*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0550*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 BRA 0x780 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0590*/ @P0 BRA 0x750 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05b0*/ @P0 BRA 0x790 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05d0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05e0*/ @!P0 BRA 0x790 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0600*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0610*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0620*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0630*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0640*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0650*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0670*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0690*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06a0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06c0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06e0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06f0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0700*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0710*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0730*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x790 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0760*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x790 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0790*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x830 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*07c0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x830 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*07f0*/ BRA 0x830 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0810*/ BRA 0x830 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0820*/ FADD.FTZ R4, R7, R4 ; /* 0x0000000407047221 */
/* 0x000fe40000010000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0004 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0870*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff78004007950 */
/* 0x000fea0003c3ffff */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11normalize_NPfS_i
.globl _Z11normalize_NPfS_i
.p2align 8
.type _Z11normalize_NPfS_i,@function
_Z11normalize_NPfS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v0, v4, v0, v1
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11normalize_NPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11normalize_NPfS_i, .Lfunc_end0-_Z11normalize_NPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11normalize_NPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11normalize_NPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015bb47_00000000-6_normalize_N.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11normalize_NPfS_iPfS_i
.type _Z34__device_stub__Z11normalize_NPfS_iPfS_i, @function
_Z34__device_stub__Z11normalize_NPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11normalize_NPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11normalize_NPfS_iPfS_i, .-_Z34__device_stub__Z11normalize_NPfS_iPfS_i
.globl _Z11normalize_NPfS_i
.type _Z11normalize_NPfS_i, @function
_Z11normalize_NPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11normalize_NPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11normalize_NPfS_i, .-_Z11normalize_NPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11normalize_NPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11normalize_NPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "normalize_N.hip"
.globl _Z26__device_stub__normalize_NPfS_i # -- Begin function _Z26__device_stub__normalize_NPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__normalize_NPfS_i,@function
_Z26__device_stub__normalize_NPfS_i: # @_Z26__device_stub__normalize_NPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11normalize_NPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__normalize_NPfS_i, .Lfunc_end0-_Z26__device_stub__normalize_NPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11normalize_NPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11normalize_NPfS_i,@object # @_Z11normalize_NPfS_i
.section .rodata,"a",@progbits
.globl _Z11normalize_NPfS_i
.p2align 3, 0x0
_Z11normalize_NPfS_i:
.quad _Z26__device_stub__normalize_NPfS_i
.size _Z11normalize_NPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11normalize_NPfS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__normalize_NPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11normalize_NPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
#include "SiPotential.h"
//-------------------- force between two Si particles ---------------------//
__host__ __device__ double f2_derivative_of_rij_tag(double r_ij_tag)
{
double first = -4*B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag));
double second = ((B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag)))-1)*(1.0/((r_ij_tag-a_Si)*(r_ij_tag-a_Si)));
double print = first-second;
double r_ij_tag_minus_a = r_ij_tag - a_Si;//r'ij-a
double r_ij_tag_minus_a2 = r_ij_tag_minus_a*r_ij_tag_minus_a;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a);//(r'ij-a)^(-1)
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a2));//(r'ij-a)^(-2)
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double r_ij_tag5 = r_ij_tag4*r_ij_tag;
double r_ij_tag_in_mFive = (1.0/(r_ij_tag5));//r'ij^(-5)
double r_ij_tag_in_mFour = (1.0/(r_ij_tag4));//r'ij^(-4)
double expression = B_Si * r_ij_tag_in_mFour;
expression = expression - 1.0;//(B*r'ij^(-4) - 1)
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double f2_derivative_part_1 = -4.0 * B_Si * r_ij_tag_in_mFive;
double f2_derivative_part_2 = expression * r_ij_tag_minus_a_in_mTwo;
return A_Si*exponent*(f2_derivative_part_1 - f2_derivative_part_2);
}
__host__ __device__ double v2_derivative_of_rix(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);//v2 derivative of distance
double dist_x = (i.x - j.x);
dist_x = dist_x / (r_ij);
double v2_derivative = f2_derivative * dist_x;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riy(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_y = i.y - j.y;
dist_y = dist_y / (r_ij);
double v2_derivative = f2_derivative * dist_y;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riz(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_z = i.z - j.z;
dist_z = dist_z / (r_ij);
double v2_derivative = f2_derivative * dist_z;
return v2_derivative;
}
//----------------------------------------------------------------------------//
//-------------------- potential between two Si particles ---------------------//
__host__ __device__ double f2(double r_ij_tag)
{
if(r_ij_tag >= a_Si)
{
return 0;
}
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double expression = (1.0/(r_ij_tag4));
expression *= B_Si;
expression -= 1.0;
return A_Si*expression*exponent;
}
__host__ __device__ double v2(double r_ij_tag)
{
if(r_ij_tag == pow(2.0,1.0/6.0))
{
return -epsilon_Si;
}
return f2(r_ij_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
//------------------------ force between three Si particles -------------------//
__host__ __device__ double hi_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag - a_Si) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag) / (r_ij_tag*r_ij_tag * r_ik_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hi_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag) / (r_ik_tag*r_ik_tag * r_ij_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_jk_tag*r_jk_tag + r_ik_tag*r_ik_tag) / (r_ij_tag*r_ij_tag * r_jk_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosIjk_plus_oneThird);
return lamda_Si*exponent*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ik_tag) / (r_ij_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = (1.0/(r_ik_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ij_tag) / (r_ik_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag + r_ij_tag*r_ij_tag) / (r_ik_tag*r_ik_tag * r_jk_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosIkj_plus_oneThird);
return lamda_Si*exponent*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double f3_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rij = 0.0;
double hj_derivative_of_rij = 0.0;
double hk_derivative_of_rij = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
hi_derivative_of_rij = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rij = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rij = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rij + hj_derivative_of_rij + hk_derivative_of_rij;
}
__host__ __device__ double f3_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rik = 0.0;
double hj_derivative_of_rik = 0.0;
double hk_derivative_of_rik = 0.0;
if(r_ik_tag < a_Si && r_ij_tag < a_Si)
{
hi_derivative_of_rik = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rik = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rik = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rik + hj_derivative_of_rik + hk_derivative_of_rik;
}
__host__ __device__ double v3_derivative_of_rix(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijx = (i.x-j.x);
double dist_ikx = (i.x-k.x);
double expression1 = (dist_ijx/(r_ij));
double expression2 = (dist_ikx/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riy(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijy = (i.y-j.y);
double dist_iky = (i.y-k.y);
double expression1 = (dist_ijy/(r_ij));
double expression2 = (dist_iky/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riz(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijz = (i.z-j.z);
double dist_ikz = (i.z-k.z);
double expression1 = (dist_ijz/(r_ij));
double expression2 = (dist_ikz/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
//----------------------------------------------------------------------------//
//-------------------- potential between three Si particles -------------------//
__host__ __device__ double hi(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_ik_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosJik_plus_oneThird*cosJik_plus_oneThird;
}
__host__ __device__ double hj(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIjk_plus_oneThird*cosIjk_plus_oneThird;
}
__host__ __device__ double hk(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_jk_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1.0/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIkj_plus_oneThird*cosIkj_plus_oneThird;
}
__host__ __device__ double f3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double h_i = 0.0;
double h_j = 0.0;
double h_k = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_i = hi(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_j = hj(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
h_k = hk(r_ij_tag,r_ik_tag,r_jk_tag);
}
return h_i + h_j + h_k;
}
__host__ __device__ double v3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
return f3(r_ij_tag,r_ik_tag,r_jk_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
#include "SiPotential.h"
//-------------------- force between two Si particles ---------------------//
__host__ __device__ double f2_derivative_of_rij_tag(double r_ij_tag)
{
double first = -4*B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag));
double second = ((B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag)))-1)*(1.0/((r_ij_tag-a_Si)*(r_ij_tag-a_Si)));
double print = first-second;
double r_ij_tag_minus_a = r_ij_tag - a_Si;//r'ij-a
double r_ij_tag_minus_a2 = r_ij_tag_minus_a*r_ij_tag_minus_a;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a);//(r'ij-a)^(-1)
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a2));//(r'ij-a)^(-2)
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double r_ij_tag5 = r_ij_tag4*r_ij_tag;
double r_ij_tag_in_mFive = (1.0/(r_ij_tag5));//r'ij^(-5)
double r_ij_tag_in_mFour = (1.0/(r_ij_tag4));//r'ij^(-4)
double expression = B_Si * r_ij_tag_in_mFour;
expression = expression - 1.0;//(B*r'ij^(-4) - 1)
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double f2_derivative_part_1 = -4.0 * B_Si * r_ij_tag_in_mFive;
double f2_derivative_part_2 = expression * r_ij_tag_minus_a_in_mTwo;
return A_Si*exponent*(f2_derivative_part_1 - f2_derivative_part_2);
}
__host__ __device__ double v2_derivative_of_rix(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);//v2 derivative of distance
double dist_x = (i.x - j.x);
dist_x = dist_x / (r_ij);
double v2_derivative = f2_derivative * dist_x;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riy(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_y = i.y - j.y;
dist_y = dist_y / (r_ij);
double v2_derivative = f2_derivative * dist_y;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riz(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_z = i.z - j.z;
dist_z = dist_z / (r_ij);
double v2_derivative = f2_derivative * dist_z;
return v2_derivative;
}
//----------------------------------------------------------------------------//
//-------------------- potential between two Si particles ---------------------//
__host__ __device__ double f2(double r_ij_tag)
{
if(r_ij_tag >= a_Si)
{
return 0;
}
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double expression = (1.0/(r_ij_tag4));
expression *= B_Si;
expression -= 1.0;
return A_Si*expression*exponent;
}
__host__ __device__ double v2(double r_ij_tag)
{
if(r_ij_tag == pow(2.0,1.0/6.0))
{
return -epsilon_Si;
}
return f2(r_ij_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
//------------------------ force between three Si particles -------------------//
__host__ __device__ double hi_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag - a_Si) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag) / (r_ij_tag*r_ij_tag * r_ik_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hi_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag) / (r_ik_tag*r_ik_tag * r_ij_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_jk_tag*r_jk_tag + r_ik_tag*r_ik_tag) / (r_ij_tag*r_ij_tag * r_jk_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosIjk_plus_oneThird);
return lamda_Si*exponent*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ik_tag) / (r_ij_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = (1.0/(r_ik_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ij_tag) / (r_ik_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag + r_ij_tag*r_ij_tag) / (r_ik_tag*r_ik_tag * r_jk_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosIkj_plus_oneThird);
return lamda_Si*exponent*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double f3_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rij = 0.0;
double hj_derivative_of_rij = 0.0;
double hk_derivative_of_rij = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
hi_derivative_of_rij = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rij = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rij = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rij + hj_derivative_of_rij + hk_derivative_of_rij;
}
__host__ __device__ double f3_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rik = 0.0;
double hj_derivative_of_rik = 0.0;
double hk_derivative_of_rik = 0.0;
if(r_ik_tag < a_Si && r_ij_tag < a_Si)
{
hi_derivative_of_rik = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rik = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rik = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rik + hj_derivative_of_rik + hk_derivative_of_rik;
}
__host__ __device__ double v3_derivative_of_rix(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijx = (i.x-j.x);
double dist_ikx = (i.x-k.x);
double expression1 = (dist_ijx/(r_ij));
double expression2 = (dist_ikx/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riy(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijy = (i.y-j.y);
double dist_iky = (i.y-k.y);
double expression1 = (dist_ijy/(r_ij));
double expression2 = (dist_iky/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riz(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijz = (i.z-j.z);
double dist_ikz = (i.z-k.z);
double expression1 = (dist_ijz/(r_ij));
double expression2 = (dist_ikz/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
//----------------------------------------------------------------------------//
//-------------------- potential between three Si particles -------------------//
__host__ __device__ double hi(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_ik_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosJik_plus_oneThird*cosJik_plus_oneThird;
}
__host__ __device__ double hj(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIjk_plus_oneThird*cosIjk_plus_oneThird;
}
__host__ __device__ double hk(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_jk_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1.0/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIkj_plus_oneThird*cosIkj_plus_oneThird;
}
__host__ __device__ double f3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double h_i = 0.0;
double h_j = 0.0;
double h_k = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_i = hi(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_j = hj(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
h_k = hk(r_ij_tag,r_ik_tag,r_jk_tag);
}
return h_i + h_j + h_k;
}
__host__ __device__ double v3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
return f3(r_ij_tag,r_ik_tag,r_jk_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
*/ | .file "tmpxft_000195b0_00000000-6_SiPotential.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
#include "SiPotential.h"
//-------------------- force between two Si particles ---------------------//
__host__ __device__ double f2_derivative_of_rij_tag(double r_ij_tag)
{
double first = -4*B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag));
double second = ((B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag)))-1)*(1.0/((r_ij_tag-a_Si)*(r_ij_tag-a_Si)));
double print = first-second;
double r_ij_tag_minus_a = r_ij_tag - a_Si;//r'ij-a
double r_ij_tag_minus_a2 = r_ij_tag_minus_a*r_ij_tag_minus_a;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a);//(r'ij-a)^(-1)
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a2));//(r'ij-a)^(-2)
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double r_ij_tag5 = r_ij_tag4*r_ij_tag;
double r_ij_tag_in_mFive = (1.0/(r_ij_tag5));//r'ij^(-5)
double r_ij_tag_in_mFour = (1.0/(r_ij_tag4));//r'ij^(-4)
double expression = B_Si * r_ij_tag_in_mFour;
expression = expression - 1.0;//(B*r'ij^(-4) - 1)
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double f2_derivative_part_1 = -4.0 * B_Si * r_ij_tag_in_mFive;
double f2_derivative_part_2 = expression * r_ij_tag_minus_a_in_mTwo;
return A_Si*exponent*(f2_derivative_part_1 - f2_derivative_part_2);
}
__host__ __device__ double v2_derivative_of_rix(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);//v2 derivative of distance
double dist_x = (i.x - j.x);
dist_x = dist_x / (r_ij);
double v2_derivative = f2_derivative * dist_x;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riy(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_y = i.y - j.y;
dist_y = dist_y / (r_ij);
double v2_derivative = f2_derivative * dist_y;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riz(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_z = i.z - j.z;
dist_z = dist_z / (r_ij);
double v2_derivative = f2_derivative * dist_z;
return v2_derivative;
}
//----------------------------------------------------------------------------//
//-------------------- potential between two Si particles ---------------------//
__host__ __device__ double f2(double r_ij_tag)
{
if(r_ij_tag >= a_Si)
{
return 0;
}
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double expression = (1.0/(r_ij_tag4));
expression *= B_Si;
expression -= 1.0;
return A_Si*expression*exponent;
}
__host__ __device__ double v2(double r_ij_tag)
{
if(r_ij_tag == pow(2.0,1.0/6.0))
{
return -epsilon_Si;
}
return f2(r_ij_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
//------------------------ force between three Si particles -------------------//
__host__ __device__ double hi_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag - a_Si) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag) / (r_ij_tag*r_ij_tag * r_ik_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hi_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag) / (r_ik_tag*r_ik_tag * r_ij_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_jk_tag*r_jk_tag + r_ik_tag*r_ik_tag) / (r_ij_tag*r_ij_tag * r_jk_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosIjk_plus_oneThird);
return lamda_Si*exponent*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ik_tag) / (r_ij_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = (1.0/(r_ik_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ij_tag) / (r_ik_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag + r_ij_tag*r_ij_tag) / (r_ik_tag*r_ik_tag * r_jk_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosIkj_plus_oneThird);
return lamda_Si*exponent*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double f3_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rij = 0.0;
double hj_derivative_of_rij = 0.0;
double hk_derivative_of_rij = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
hi_derivative_of_rij = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rij = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rij = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rij + hj_derivative_of_rij + hk_derivative_of_rij;
}
__host__ __device__ double f3_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rik = 0.0;
double hj_derivative_of_rik = 0.0;
double hk_derivative_of_rik = 0.0;
if(r_ik_tag < a_Si && r_ij_tag < a_Si)
{
hi_derivative_of_rik = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rik = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rik = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rik + hj_derivative_of_rik + hk_derivative_of_rik;
}
__host__ __device__ double v3_derivative_of_rix(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijx = (i.x-j.x);
double dist_ikx = (i.x-k.x);
double expression1 = (dist_ijx/(r_ij));
double expression2 = (dist_ikx/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riy(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijy = (i.y-j.y);
double dist_iky = (i.y-k.y);
double expression1 = (dist_ijy/(r_ij));
double expression2 = (dist_iky/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riz(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijz = (i.z-j.z);
double dist_ikz = (i.z-k.z);
double expression1 = (dist_ijz/(r_ij));
double expression2 = (dist_ikz/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
//----------------------------------------------------------------------------//
//-------------------- potential between three Si particles -------------------//
__host__ __device__ double hi(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_ik_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosJik_plus_oneThird*cosJik_plus_oneThird;
}
__host__ __device__ double hj(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIjk_plus_oneThird*cosIjk_plus_oneThird;
}
__host__ __device__ double hk(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_jk_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1.0/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIkj_plus_oneThird*cosIkj_plus_oneThird;
}
__host__ __device__ double f3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double h_i = 0.0;
double h_j = 0.0;
double h_k = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_i = hi(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_j = hj(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
h_k = hk(r_ij_tag,r_ik_tag,r_jk_tag);
}
return h_i + h_j + h_k;
}
__host__ __device__ double v3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
return f3(r_ij_tag,r_ik_tag,r_jk_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
*/ | #include <hip/hip_runtime.h>
/*
#include "SiPotential.h"
//-------------------- force between two Si particles ---------------------//
__host__ __device__ double f2_derivative_of_rij_tag(double r_ij_tag)
{
double first = -4*B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag));
double second = ((B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag)))-1)*(1.0/((r_ij_tag-a_Si)*(r_ij_tag-a_Si)));
double print = first-second;
double r_ij_tag_minus_a = r_ij_tag - a_Si;//r'ij-a
double r_ij_tag_minus_a2 = r_ij_tag_minus_a*r_ij_tag_minus_a;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a);//(r'ij-a)^(-1)
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a2));//(r'ij-a)^(-2)
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double r_ij_tag5 = r_ij_tag4*r_ij_tag;
double r_ij_tag_in_mFive = (1.0/(r_ij_tag5));//r'ij^(-5)
double r_ij_tag_in_mFour = (1.0/(r_ij_tag4));//r'ij^(-4)
double expression = B_Si * r_ij_tag_in_mFour;
expression = expression - 1.0;//(B*r'ij^(-4) - 1)
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double f2_derivative_part_1 = -4.0 * B_Si * r_ij_tag_in_mFive;
double f2_derivative_part_2 = expression * r_ij_tag_minus_a_in_mTwo;
return A_Si*exponent*(f2_derivative_part_1 - f2_derivative_part_2);
}
__host__ __device__ double v2_derivative_of_rix(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);//v2 derivative of distance
double dist_x = (i.x - j.x);
dist_x = dist_x / (r_ij);
double v2_derivative = f2_derivative * dist_x;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riy(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_y = i.y - j.y;
dist_y = dist_y / (r_ij);
double v2_derivative = f2_derivative * dist_y;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riz(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_z = i.z - j.z;
dist_z = dist_z / (r_ij);
double v2_derivative = f2_derivative * dist_z;
return v2_derivative;
}
//----------------------------------------------------------------------------//
//-------------------- potential between two Si particles ---------------------//
__host__ __device__ double f2(double r_ij_tag)
{
if(r_ij_tag >= a_Si)
{
return 0;
}
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double expression = (1.0/(r_ij_tag4));
expression *= B_Si;
expression -= 1.0;
return A_Si*expression*exponent;
}
__host__ __device__ double v2(double r_ij_tag)
{
if(r_ij_tag == pow(2.0,1.0/6.0))
{
return -epsilon_Si;
}
return f2(r_ij_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
//------------------------ force between three Si particles -------------------//
__host__ __device__ double hi_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag - a_Si) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag) / (r_ij_tag*r_ij_tag * r_ik_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hi_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag) / (r_ik_tag*r_ik_tag * r_ij_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_jk_tag*r_jk_tag + r_ik_tag*r_ik_tag) / (r_ij_tag*r_ij_tag * r_jk_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosIjk_plus_oneThird);
return lamda_Si*exponent*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ik_tag) / (r_ij_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = (1.0/(r_ik_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ij_tag) / (r_ik_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag + r_ij_tag*r_ij_tag) / (r_ik_tag*r_ik_tag * r_jk_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosIkj_plus_oneThird);
return lamda_Si*exponent*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double f3_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rij = 0.0;
double hj_derivative_of_rij = 0.0;
double hk_derivative_of_rij = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
hi_derivative_of_rij = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rij = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rij = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rij + hj_derivative_of_rij + hk_derivative_of_rij;
}
__host__ __device__ double f3_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rik = 0.0;
double hj_derivative_of_rik = 0.0;
double hk_derivative_of_rik = 0.0;
if(r_ik_tag < a_Si && r_ij_tag < a_Si)
{
hi_derivative_of_rik = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rik = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rik = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rik + hj_derivative_of_rik + hk_derivative_of_rik;
}
__host__ __device__ double v3_derivative_of_rix(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijx = (i.x-j.x);
double dist_ikx = (i.x-k.x);
double expression1 = (dist_ijx/(r_ij));
double expression2 = (dist_ikx/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riy(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijy = (i.y-j.y);
double dist_iky = (i.y-k.y);
double expression1 = (dist_ijy/(r_ij));
double expression2 = (dist_iky/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riz(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijz = (i.z-j.z);
double dist_ikz = (i.z-k.z);
double expression1 = (dist_ijz/(r_ij));
double expression2 = (dist_ikz/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
//----------------------------------------------------------------------------//
//-------------------- potential between three Si particles -------------------//
__host__ __device__ double hi(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_ik_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosJik_plus_oneThird*cosJik_plus_oneThird;
}
__host__ __device__ double hj(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIjk_plus_oneThird*cosIjk_plus_oneThird;
}
__host__ __device__ double hk(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_jk_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1.0/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIkj_plus_oneThird*cosIkj_plus_oneThird;
}
__host__ __device__ double f3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double h_i = 0.0;
double h_j = 0.0;
double h_k = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_i = hi(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_j = hj(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
h_k = hk(r_ij_tag,r_ik_tag,r_jk_tag);
}
return h_i + h_j + h_k;
}
__host__ __device__ double v3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
return f3(r_ij_tag,r_ik_tag,r_jk_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
#include "SiPotential.h"
//-------------------- force between two Si particles ---------------------//
__host__ __device__ double f2_derivative_of_rij_tag(double r_ij_tag)
{
double first = -4*B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag));
double second = ((B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag)))-1)*(1.0/((r_ij_tag-a_Si)*(r_ij_tag-a_Si)));
double print = first-second;
double r_ij_tag_minus_a = r_ij_tag - a_Si;//r'ij-a
double r_ij_tag_minus_a2 = r_ij_tag_minus_a*r_ij_tag_minus_a;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a);//(r'ij-a)^(-1)
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a2));//(r'ij-a)^(-2)
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double r_ij_tag5 = r_ij_tag4*r_ij_tag;
double r_ij_tag_in_mFive = (1.0/(r_ij_tag5));//r'ij^(-5)
double r_ij_tag_in_mFour = (1.0/(r_ij_tag4));//r'ij^(-4)
double expression = B_Si * r_ij_tag_in_mFour;
expression = expression - 1.0;//(B*r'ij^(-4) - 1)
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double f2_derivative_part_1 = -4.0 * B_Si * r_ij_tag_in_mFive;
double f2_derivative_part_2 = expression * r_ij_tag_minus_a_in_mTwo;
return A_Si*exponent*(f2_derivative_part_1 - f2_derivative_part_2);
}
__host__ __device__ double v2_derivative_of_rix(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);//v2 derivative of distance
double dist_x = (i.x - j.x);
dist_x = dist_x / (r_ij);
double v2_derivative = f2_derivative * dist_x;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riy(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_y = i.y - j.y;
dist_y = dist_y / (r_ij);
double v2_derivative = f2_derivative * dist_y;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riz(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_z = i.z - j.z;
dist_z = dist_z / (r_ij);
double v2_derivative = f2_derivative * dist_z;
return v2_derivative;
}
//----------------------------------------------------------------------------//
//-------------------- potential between two Si particles ---------------------//
__host__ __device__ double f2(double r_ij_tag)
{
if(r_ij_tag >= a_Si)
{
return 0;
}
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double expression = (1.0/(r_ij_tag4));
expression *= B_Si;
expression -= 1.0;
return A_Si*expression*exponent;
}
__host__ __device__ double v2(double r_ij_tag)
{
if(r_ij_tag == pow(2.0,1.0/6.0))
{
return -epsilon_Si;
}
return f2(r_ij_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
//------------------------ force between three Si particles -------------------//
__host__ __device__ double hi_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag - a_Si) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag) / (r_ij_tag*r_ij_tag * r_ik_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hi_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag) / (r_ik_tag*r_ik_tag * r_ij_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_jk_tag*r_jk_tag + r_ik_tag*r_ik_tag) / (r_ij_tag*r_ij_tag * r_jk_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosIjk_plus_oneThird);
return lamda_Si*exponent*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ik_tag) / (r_ij_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = (1.0/(r_ik_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ij_tag) / (r_ik_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag + r_ij_tag*r_ij_tag) / (r_ik_tag*r_ik_tag * r_jk_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosIkj_plus_oneThird);
return lamda_Si*exponent*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double f3_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rij = 0.0;
double hj_derivative_of_rij = 0.0;
double hk_derivative_of_rij = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
hi_derivative_of_rij = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rij = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rij = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rij + hj_derivative_of_rij + hk_derivative_of_rij;
}
__host__ __device__ double f3_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rik = 0.0;
double hj_derivative_of_rik = 0.0;
double hk_derivative_of_rik = 0.0;
if(r_ik_tag < a_Si && r_ij_tag < a_Si)
{
hi_derivative_of_rik = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rik = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rik = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rik + hj_derivative_of_rik + hk_derivative_of_rik;
}
__host__ __device__ double v3_derivative_of_rix(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijx = (i.x-j.x);
double dist_ikx = (i.x-k.x);
double expression1 = (dist_ijx/(r_ij));
double expression2 = (dist_ikx/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riy(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijy = (i.y-j.y);
double dist_iky = (i.y-k.y);
double expression1 = (dist_ijy/(r_ij));
double expression2 = (dist_iky/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riz(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijz = (i.z-j.z);
double dist_ikz = (i.z-k.z);
double expression1 = (dist_ijz/(r_ij));
double expression2 = (dist_ikz/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
//----------------------------------------------------------------------------//
//-------------------- potential between three Si particles -------------------//
__host__ __device__ double hi(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_ik_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosJik_plus_oneThird*cosJik_plus_oneThird;
}
__host__ __device__ double hj(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIjk_plus_oneThird*cosIjk_plus_oneThird;
}
__host__ __device__ double hk(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_jk_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1.0/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIkj_plus_oneThird*cosIkj_plus_oneThird;
}
__host__ __device__ double f3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double h_i = 0.0;
double h_j = 0.0;
double h_k = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_i = hi(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_j = hj(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
h_k = hk(r_ij_tag,r_ik_tag,r_jk_tag);
}
return h_i + h_j + h_k;
}
__host__ __device__ double v3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
return f3(r_ij_tag,r_ik_tag,r_jk_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
#include "SiPotential.h"
//-------------------- force between two Si particles ---------------------//
__host__ __device__ double f2_derivative_of_rij_tag(double r_ij_tag)
{
double first = -4*B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag));
double second = ((B_Si*(1.0/(r_ij_tag*r_ij_tag*r_ij_tag*r_ij_tag)))-1)*(1.0/((r_ij_tag-a_Si)*(r_ij_tag-a_Si)));
double print = first-second;
double r_ij_tag_minus_a = r_ij_tag - a_Si;//r'ij-a
double r_ij_tag_minus_a2 = r_ij_tag_minus_a*r_ij_tag_minus_a;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a);//(r'ij-a)^(-1)
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a2));//(r'ij-a)^(-2)
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double r_ij_tag5 = r_ij_tag4*r_ij_tag;
double r_ij_tag_in_mFive = (1.0/(r_ij_tag5));//r'ij^(-5)
double r_ij_tag_in_mFour = (1.0/(r_ij_tag4));//r'ij^(-4)
double expression = B_Si * r_ij_tag_in_mFour;
expression = expression - 1.0;//(B*r'ij^(-4) - 1)
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double f2_derivative_part_1 = -4.0 * B_Si * r_ij_tag_in_mFive;
double f2_derivative_part_2 = expression * r_ij_tag_minus_a_in_mTwo;
return A_Si*exponent*(f2_derivative_part_1 - f2_derivative_part_2);
}
__host__ __device__ double v2_derivative_of_rix(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);//v2 derivative of distance
double dist_x = (i.x - j.x);
dist_x = dist_x / (r_ij);
double v2_derivative = f2_derivative * dist_x;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riy(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_y = i.y - j.y;
dist_y = dist_y / (r_ij);
double v2_derivative = f2_derivative * dist_y;
return v2_derivative;
}
__host__ __device__ double v2_derivative_of_riz(real3 i, real3 j, double r_ij)
{
if(r_ij/sigma_Si == pow(2.0,1.0/6.0))
{
return 0;
}
double f2_derivative = f2_derivative_of_rij_tag(r_ij/sigma_Si);
f2_derivative = f2_derivative * (epsilon_Si/sigma_Si);
double dist_z = i.z - j.z;
dist_z = dist_z / (r_ij);
double v2_derivative = f2_derivative * dist_z;
return v2_derivative;
}
//----------------------------------------------------------------------------//
//-------------------- potential between two Si particles ---------------------//
__host__ __device__ double f2(double r_ij_tag)
{
if(r_ij_tag >= a_Si)
{
return 0;
}
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
double exponent = exp(r_ij_tag_minus_a_in_mOne);
double r_ij_tag2 = r_ij_tag*r_ij_tag;
double r_ij_tag4 = r_ij_tag2*r_ij_tag2;
double expression = (1.0/(r_ij_tag4));
expression *= B_Si;
expression -= 1.0;
return A_Si*expression*exponent;
}
__host__ __device__ double v2(double r_ij_tag)
{
if(r_ij_tag == pow(2.0,1.0/6.0))
{
return -epsilon_Si;
}
return f2(r_ij_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
//------------------------ force between three Si particles -------------------//
__host__ __device__ double hi_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag - a_Si) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag) / (r_ij_tag*r_ij_tag * r_ik_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hi_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_ik_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag) / (r_ik_tag*r_ik_tag * r_ij_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosJik_plus_oneThird);
return lamda_Si*exponent*cosJik_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a = r_ij_tag - a_Si;
double r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a) * gama_Si;
double r_ij_tag_minus_a_in_mTwo = (1.0/(r_ij_tag_minus_a*r_ij_tag_minus_a)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ij_tag*r_ij_tag - r_jk_tag*r_jk_tag + r_ik_tag*r_ik_tag) / (r_ij_tag*r_ij_tag * r_jk_tag);
expression -= (r_ij_tag_minus_a_in_mTwo*cosIjk_plus_oneThird);
return lamda_Si*exponent*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hj_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = (1.0/(r_ij_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ik_tag) / (r_ij_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIjk_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = (1.0/(r_ik_tag - a_Si)) * gama_Si;
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (-r_ij_tag) / (r_ik_tag * r_jk_tag);
return lamda_Si*exponent*2.0*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double hk_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_jk_tag_minus_a_in_mOne = (1.0/(r_jk_tag - a_Si)) * gama_Si;
double r_ik_tag_minus_a = r_ik_tag - a_Si;
double r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a) * gama_Si;
double r_ik_tag_minus_a_in_mTwo = (1.0/(r_ik_tag_minus_a*r_ik_tag_minus_a)) * gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne+r_jk_tag_minus_a_in_mOne);
double expression = (r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag + r_ij_tag*r_ij_tag) / (r_ik_tag*r_ik_tag * r_jk_tag);
expression -= (r_ik_tag_minus_a_in_mTwo*cosIkj_plus_oneThird);
return lamda_Si*exponent*cosIkj_plus_oneThird*expression;
}
__host__ __device__ double f3_derivative_of_rij_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rij = 0.0;
double hj_derivative_of_rij = 0.0;
double hk_derivative_of_rij = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
hi_derivative_of_rij = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rij = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rij = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rij + hj_derivative_of_rij + hk_derivative_of_rij;
}
__host__ __device__ double f3_derivative_of_rik_tag(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double hi_derivative_of_rik = 0.0;
double hj_derivative_of_rik = 0.0;
double hk_derivative_of_rik = 0.0;
if(r_ik_tag < a_Si && r_ij_tag < a_Si)
{
hi_derivative_of_rik = hi_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ij_tag < a_Si)
{
hj_derivative_of_rik = hj_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
hk_derivative_of_rik = hk_derivative_of_rij_tag(r_ij_tag,r_ik_tag,r_jk_tag);
}
return hi_derivative_of_rik + hj_derivative_of_rik + hk_derivative_of_rik;
}
__host__ __device__ double v3_derivative_of_rix(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijx = (i.x-j.x);
double dist_ikx = (i.x-k.x);
double expression1 = (dist_ijx/(r_ij));
double expression2 = (dist_ikx/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riy(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijy = (i.y-j.y);
double dist_iky = (i.y-k.y);
double expression1 = (dist_ijy/(r_ij));
double expression2 = (dist_iky/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
__host__ __device__ double v3_derivative_of_riz(real3 i, real3 j, real3 k, double r_ij, double r_ik, double r_jk)
{
double v3_derived_by_rij = (f3_derivative_of_rij_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double v3_derived_by_rik = (f3_derivative_of_rik_tag(r_ij/sigma_Si, r_ik/sigma_Si, r_jk/sigma_Si))*(epsilon_Si/sigma_Si);
double dist_ijz = (i.z-j.z);
double dist_ikz = (i.z-k.z);
double expression1 = (dist_ijz/(r_ij));
double expression2 = (dist_ikz/(r_ik));
return v3_derived_by_rij*expression1 + v3_derived_by_rik*expression2;
}
//----------------------------------------------------------------------------//
//-------------------- potential between three Si particles -------------------//
__host__ __device__ double hi(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosJik_plus_oneThird = ((r_ij_tag*r_ij_tag + r_ik_tag*r_ik_tag - r_jk_tag*r_jk_tag)/(2.0 * r_ij_tag * r_ik_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_ik_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosJik_plus_oneThird*cosJik_plus_oneThird;
}
__host__ __device__ double hj(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIjk_plus_oneThird = ((r_ij_tag*r_ij_tag + r_jk_tag*r_jk_tag - r_ik_tag*r_ik_tag)/(2.0 * r_ij_tag * r_jk_tag)) + (1.0/3.0);
double r_ij_tag_minus_a_in_mOne = r_ij_tag - a_Si;
r_ij_tag_minus_a_in_mOne = (1.0/r_ij_tag_minus_a_in_mOne);
r_ij_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ij_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIjk_plus_oneThird*cosIjk_plus_oneThird;
}
__host__ __device__ double hk(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double cosIkj_plus_oneThird = ((r_ik_tag*r_ik_tag + r_jk_tag*r_jk_tag - r_ij_tag*r_ij_tag)/(2.0 * r_ik_tag * r_jk_tag)) + (1.0/3.0);
double r_ik_tag_minus_a_in_mOne = r_ik_tag - a_Si;
r_ik_tag_minus_a_in_mOne = (1.0/r_ik_tag_minus_a_in_mOne);
r_ik_tag_minus_a_in_mOne *= gama_Si;
double r_jk_tag_minus_a_in_mOne = r_jk_tag - a_Si;
r_jk_tag_minus_a_in_mOne = (1.0/r_jk_tag_minus_a_in_mOne);
r_jk_tag_minus_a_in_mOne *= gama_Si;
double exponent = exp(r_ik_tag_minus_a_in_mOne + r_jk_tag_minus_a_in_mOne);
return lamda_Si*exponent*cosIkj_plus_oneThird*cosIkj_plus_oneThird;
}
__host__ __device__ double f3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
double h_i = 0.0;
double h_j = 0.0;
double h_k = 0.0;
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_i = hi(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_ij_tag < a_Si && r_ik_tag < a_Si)
{
h_j = hj(r_ij_tag,r_ik_tag,r_jk_tag);
}
if(r_jk_tag < a_Si && r_ik_tag < a_Si)
{
h_k = hk(r_ij_tag,r_ik_tag,r_jk_tag);
}
return h_i + h_j + h_k;
}
__host__ __device__ double v3(double r_ij_tag, double r_ik_tag, double r_jk_tag)
{
return f3(r_ij_tag,r_ik_tag,r_jk_tag)*epsilon_Si;
}
//----------------------------------------------------------------------------//
*/ | .text
.file "SiPotential.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000195b0_00000000-6_SiPotential.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SiPotential.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda.h>
#include<stdio.h>
#include<time.h>
#include<fstream>
__global__ void matrixMulKernel(int *d_M, int *d_N, int *d_P, int width){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int Pvalue;
if((row < width)&&(col < width)){
Pvalue = 0;
for (int k = 0; k < width ; ++k){
Pvalue += d_M[row*width+k] * d_N[k*width+col];
}
d_P[row*width+col] = Pvalue;
}
}
int matrixMulHost(int *h_M, int *h_N, int *h_P, int width){
int Pvalue;
for(int row = 0; row < width ; ++row){
for(int col = 0; col < width ; ++col){
Pvalue = 0;
for(int k = 0; k < width ; ++k){
Pvalue += h_M[row*width+k] * h_N[k*width+col];
}
h_P[row*width+col] = Pvalue;
}
}
return 0;
}
int initValues(int *data, int width){
for(int i = 0; i < width*width; i++)
data[i] = 2;
return 0;
}
int printData(int *data, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
printf("%d ", data[(i*width)+j]);
}
printf("\n");
}
return 0;
}
int testValues(int *A, int *B, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
if(A[(i*width)+j]!=B[(i*width)+j]){
printf("Mal Cálculo...\n");
return 0;
}
}
}
printf("Buen Cálculo ...\n");
return 0;
}
int main(){
int *h_M, *h_N, *h_P,*h_P_d;
int *d_M, *d_N,*d_P;
int width = 2048;
cudaError_t error = cudaSuccess;
int size = width * width * sizeof(int);
clock_t start, end, startGPU, endGPU;
double cpu_time_used, gpu_time_used;
h_M = (int*)malloc(size);
h_N = (int*)malloc(size);
h_P = (int*)malloc(size);
h_P_d = (int*)malloc(size);
if(h_P_d == NULL)
return 0;
initValues(h_M, width);
initValues(h_N, width);
/////////Algoritmo Secuencial////////////////////////////////////////////
start = clock();
matrixMulHost(h_M, h_N, h_P, width);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo secuencial: %.10f\n", cpu_time_used);
/////////Algoritmo Secuencial/////////////////////////////////////////////
error = cudaMalloc((void**)&d_M,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_M");
exit(0);
}
error = cudaMalloc((void**)&d_N,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_N");
exit(0);
}
error = cudaMalloc((void**)&d_P,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_P");
exit(0);
}
//////////////////////Algoritmo Paralelo///////////////////////////
startGPU = clock();
error = cudaMemcpy(d_M, h_M, size, cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error copiando datos a d_M");
exit(0);
}
error = cudaMemcpy(d_N, h_N, size, cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error copiando datos a d_N");
exit(0);
}
int blockSize = 32;
dim3 dimBlock(blockSize,blockSize,1);
dim3 dimGrid(ceil(width/float(blockSize)),ceil(width/float(blockSize)),1);
matrixMulKernel<<<dimGrid,dimBlock>>>(d_M,d_N,d_P,width);
cudaDeviceSynchronize();
cudaMemcpy(h_P_d,d_P,size,cudaMemcpyDeviceToHost);
endGPU = clock();
gpu_time_used = ((double) (endGPU - startGPU)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo paralelo: %.10f\n", gpu_time_used);
printf("La aceleración obtenida es de %.10fX\n",cpu_time_used/gpu_time_used);
///////////////////////Algoritmo Paralelo////////////////////////////
testValues(h_P_d,h_P,width);
free(h_M);
free(h_N);
free(h_P);
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
return 0;
} | code for sm_80
Function : _Z15matrixMulKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<stdio.h>
#include<time.h>
#include<fstream>
__global__ void matrixMulKernel(int *d_M, int *d_N, int *d_P, int width){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int Pvalue;
if((row < width)&&(col < width)){
Pvalue = 0;
for (int k = 0; k < width ; ++k){
Pvalue += d_M[row*width+k] * d_N[k*width+col];
}
d_P[row*width+col] = Pvalue;
}
}
int matrixMulHost(int *h_M, int *h_N, int *h_P, int width){
int Pvalue;
for(int row = 0; row < width ; ++row){
for(int col = 0; col < width ; ++col){
Pvalue = 0;
for(int k = 0; k < width ; ++k){
Pvalue += h_M[row*width+k] * h_N[k*width+col];
}
h_P[row*width+col] = Pvalue;
}
}
return 0;
}
int initValues(int *data, int width){
for(int i = 0; i < width*width; i++)
data[i] = 2;
return 0;
}
int printData(int *data, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
printf("%d ", data[(i*width)+j]);
}
printf("\n");
}
return 0;
}
int testValues(int *A, int *B, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
if(A[(i*width)+j]!=B[(i*width)+j]){
printf("Mal Cálculo...\n");
return 0;
}
}
}
printf("Buen Cálculo ...\n");
return 0;
}
int main(){
int *h_M, *h_N, *h_P,*h_P_d;
int *d_M, *d_N,*d_P;
int width = 2048;
cudaError_t error = cudaSuccess;
int size = width * width * sizeof(int);
clock_t start, end, startGPU, endGPU;
double cpu_time_used, gpu_time_used;
h_M = (int*)malloc(size);
h_N = (int*)malloc(size);
h_P = (int*)malloc(size);
h_P_d = (int*)malloc(size);
if(h_P_d == NULL)
return 0;
initValues(h_M, width);
initValues(h_N, width);
/////////Algoritmo Secuencial////////////////////////////////////////////
start = clock();
matrixMulHost(h_M, h_N, h_P, width);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo secuencial: %.10f\n", cpu_time_used);
/////////Algoritmo Secuencial/////////////////////////////////////////////
error = cudaMalloc((void**)&d_M,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_M");
exit(0);
}
error = cudaMalloc((void**)&d_N,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_N");
exit(0);
}
error = cudaMalloc((void**)&d_P,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_P");
exit(0);
}
//////////////////////Algoritmo Paralelo///////////////////////////
startGPU = clock();
error = cudaMemcpy(d_M, h_M, size, cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error copiando datos a d_M");
exit(0);
}
error = cudaMemcpy(d_N, h_N, size, cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error copiando datos a d_N");
exit(0);
}
int blockSize = 32;
dim3 dimBlock(blockSize,blockSize,1);
dim3 dimGrid(ceil(width/float(blockSize)),ceil(width/float(blockSize)),1);
matrixMulKernel<<<dimGrid,dimBlock>>>(d_M,d_N,d_P,width);
cudaDeviceSynchronize();
cudaMemcpy(h_P_d,d_P,size,cudaMemcpyDeviceToHost);
endGPU = clock();
gpu_time_used = ((double) (endGPU - startGPU)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo paralelo: %.10f\n", gpu_time_used);
printf("La aceleración obtenida es de %.10fX\n",cpu_time_used/gpu_time_used);
///////////////////////Algoritmo Paralelo////////////////////////////
testValues(h_P_d,h_P,width);
free(h_M);
free(h_N);
free(h_P);
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
return 0;
} | .file "tmpxft_00080bbf_00000000-6_simpleMatrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3807:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13matrixMulHostPiS_S_i
.type _Z13matrixMulHostPiS_S_i, @function
_Z13matrixMulHostPiS_S_i:
.LFB3800:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %rbp
movq %rdx, %r11
movl %ecx, %r13d
movslq %ecx, %r12
leaq 0(,%r12,4), %rdi
movq %r8, %rbx
addq %rdi, %r8
movl $0, %r14d
.L5:
movq %rbp, %r10
movl $0, %r9d
.L8:
movq %r10, %rcx
movq %rbx, %rax
movl $0, %esi
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
movl %esi, (%r11,%r9,4)
addq $1, %r9
addq $4, %r10
cmpq %r12, %r9
jne .L8
addl $1, %r14d
addq %rdi, %r11
addq %rdi, %rbx
addq %rdi, %r8
cmpl %r14d, %r13d
jne .L5
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
movl $0, %eax
ret
.cfi_endproc
.LFE3800:
.size _Z13matrixMulHostPiS_S_i, .-_Z13matrixMulHostPiS_S_i
.globl _Z10initValuesPii
.type _Z10initValuesPii, @function
_Z10initValuesPii:
.LFB3801:
.cfi_startproc
endbr64
imull %esi, %esi
testl %esi, %esi
jle .L15
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L16:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
.L15:
movl $0, %eax
ret
.cfi_endproc
.LFE3801:
.size _Z10initValuesPii, .-_Z10initValuesPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z9printDataPii
.type _Z9printDataPii, @function
_Z9printDataPii:
.LFB3802:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L19
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L20:
leaq 0(%rbp,%r14), %rbx
.L21:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L20
.L19:
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3802:
.size _Z9printDataPii, .-_Z9printDataPii
.section .rodata.str1.1
.LC2:
.string "Mal C\303\241lculo...\n"
.LC3:
.string "Buen C\303\241lculo ...\n"
.text
.globl _Z10testValuesPiS_i
.type _Z10testValuesPiS_i, @function
_Z10testValuesPiS_i:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L25
movslq %edx, %rax
leaq 0(,%rax,4), %r10
negq %rax
leaq 0(,%rax,4), %r8
movq %r10, %rcx
movl $0, %r9d
.L26:
leaq (%rcx,%r8), %rax
.L29:
movl (%rsi,%rax), %r11d
cmpl %r11d, (%rdi,%rax)
jne .L32
addq $4, %rax
cmpq %rcx, %rax
jne .L29
addl $1, %r9d
addq %r10, %rcx
cmpl %r9d, %edx
jne .L26
.L25:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _Z10testValuesPiS_i, .-_Z10testValuesPiS_i
.globl _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i:
.LFB3829:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMulKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3829:
.size _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
.globl _Z15matrixMulKernelPiS_S_i
.type _Z15matrixMulKernelPiS_S_i, @function
_Z15matrixMulKernelPiS_S_i:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _Z15matrixMulKernelPiS_S_i, .-_Z15matrixMulKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Tiempo algoritmo secuencial: %.10f\n"
.align 8
.LC6:
.string "Error reservando memoria para d_M"
.align 8
.LC7:
.string "Error reservando memoria para d_N"
.align 8
.LC8:
.string "Error reservando memoria para d_P"
.section .rodata.str1.1
.LC9:
.string "Error copiando datos a d_M"
.LC10:
.string "Error copiando datos a d_N"
.section .rodata.str1.8
.align 8
.LC11:
.string "Tiempo algoritmo paralelo: %.10f\n"
.align 8
.LC12:
.string "La aceleraci\303\263n obtenida es de %.10fX\n"
.text
.globl main
.type main, @function
main:
.LFB3804:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $16777216, %edi
call malloc@PLT
testq %rax, %rax
je .L42
movq %rax, %r12
movl $2048, %esi
movq %rbx, %rdi
call _Z10initValuesPii
movl $2048, %esi
movq %rbp, %rdi
call _Z10initValuesPii
call clock@PLT
movq %rax, %r14
movl $2048, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13matrixMulHostPiS_S_i
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %r15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L43
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L44
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L44:
leaq 40(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L45
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L45:
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L46
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L46:
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L47
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L47:
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $64, 60(%rsp)
movl $64, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L48:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $16777216, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %xmm2
divsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2048, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z10testValuesPiS_i
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L42:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl $2048, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
jmp .L48
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3804:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z15matrixMulKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3832:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3832:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<stdio.h>
#include<time.h>
#include<fstream>
__global__ void matrixMulKernel(int *d_M, int *d_N, int *d_P, int width){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int Pvalue;
if((row < width)&&(col < width)){
Pvalue = 0;
for (int k = 0; k < width ; ++k){
Pvalue += d_M[row*width+k] * d_N[k*width+col];
}
d_P[row*width+col] = Pvalue;
}
}
int matrixMulHost(int *h_M, int *h_N, int *h_P, int width){
int Pvalue;
for(int row = 0; row < width ; ++row){
for(int col = 0; col < width ; ++col){
Pvalue = 0;
for(int k = 0; k < width ; ++k){
Pvalue += h_M[row*width+k] * h_N[k*width+col];
}
h_P[row*width+col] = Pvalue;
}
}
return 0;
}
int initValues(int *data, int width){
for(int i = 0; i < width*width; i++)
data[i] = 2;
return 0;
}
int printData(int *data, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
printf("%d ", data[(i*width)+j]);
}
printf("\n");
}
return 0;
}
int testValues(int *A, int *B, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
if(A[(i*width)+j]!=B[(i*width)+j]){
printf("Mal Cálculo...\n");
return 0;
}
}
}
printf("Buen Cálculo ...\n");
return 0;
}
int main(){
int *h_M, *h_N, *h_P,*h_P_d;
int *d_M, *d_N,*d_P;
int width = 2048;
cudaError_t error = cudaSuccess;
int size = width * width * sizeof(int);
clock_t start, end, startGPU, endGPU;
double cpu_time_used, gpu_time_used;
h_M = (int*)malloc(size);
h_N = (int*)malloc(size);
h_P = (int*)malloc(size);
h_P_d = (int*)malloc(size);
if(h_P_d == NULL)
return 0;
initValues(h_M, width);
initValues(h_N, width);
/////////Algoritmo Secuencial////////////////////////////////////////////
start = clock();
matrixMulHost(h_M, h_N, h_P, width);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo secuencial: %.10f\n", cpu_time_used);
/////////Algoritmo Secuencial/////////////////////////////////////////////
error = cudaMalloc((void**)&d_M,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_M");
exit(0);
}
error = cudaMalloc((void**)&d_N,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_N");
exit(0);
}
error = cudaMalloc((void**)&d_P,size);
if(error != cudaSuccess){
printf("Error reservando memoria para d_P");
exit(0);
}
//////////////////////Algoritmo Paralelo///////////////////////////
startGPU = clock();
error = cudaMemcpy(d_M, h_M, size, cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error copiando datos a d_M");
exit(0);
}
error = cudaMemcpy(d_N, h_N, size, cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error copiando datos a d_N");
exit(0);
}
int blockSize = 32;
dim3 dimBlock(blockSize,blockSize,1);
dim3 dimGrid(ceil(width/float(blockSize)),ceil(width/float(blockSize)),1);
matrixMulKernel<<<dimGrid,dimBlock>>>(d_M,d_N,d_P,width);
cudaDeviceSynchronize();
cudaMemcpy(h_P_d,d_P,size,cudaMemcpyDeviceToHost);
endGPU = clock();
gpu_time_used = ((double) (endGPU - startGPU)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo paralelo: %.10f\n", gpu_time_used);
printf("La aceleración obtenida es de %.10fX\n",cpu_time_used/gpu_time_used);
///////////////////////Algoritmo Paralelo////////////////////////////
testValues(h_P_d,h_P,width);
free(h_M);
free(h_N);
free(h_P);
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
return 0;
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
#include<fstream>
__global__ void matrixMulKernel(int *d_M, int *d_N, int *d_P, int width){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int Pvalue;
if((row < width)&&(col < width)){
Pvalue = 0;
for (int k = 0; k < width ; ++k){
Pvalue += d_M[row*width+k] * d_N[k*width+col];
}
d_P[row*width+col] = Pvalue;
}
}
int matrixMulHost(int *h_M, int *h_N, int *h_P, int width){
int Pvalue;
for(int row = 0; row < width ; ++row){
for(int col = 0; col < width ; ++col){
Pvalue = 0;
for(int k = 0; k < width ; ++k){
Pvalue += h_M[row*width+k] * h_N[k*width+col];
}
h_P[row*width+col] = Pvalue;
}
}
return 0;
}
int initValues(int *data, int width){
for(int i = 0; i < width*width; i++)
data[i] = 2;
return 0;
}
int printData(int *data, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
printf("%d ", data[(i*width)+j]);
}
printf("\n");
}
return 0;
}
int testValues(int *A, int *B, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
if(A[(i*width)+j]!=B[(i*width)+j]){
printf("Mal Cálculo...\n");
return 0;
}
}
}
printf("Buen Cálculo ...\n");
return 0;
}
int main(){
int *h_M, *h_N, *h_P,*h_P_d;
int *d_M, *d_N,*d_P;
int width = 2048;
hipError_t error = hipSuccess;
int size = width * width * sizeof(int);
clock_t start, end, startGPU, endGPU;
double cpu_time_used, gpu_time_used;
h_M = (int*)malloc(size);
h_N = (int*)malloc(size);
h_P = (int*)malloc(size);
h_P_d = (int*)malloc(size);
if(h_P_d == NULL)
return 0;
initValues(h_M, width);
initValues(h_N, width);
/////////Algoritmo Secuencial////////////////////////////////////////////
start = clock();
matrixMulHost(h_M, h_N, h_P, width);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo secuencial: %.10f\n", cpu_time_used);
/////////Algoritmo Secuencial/////////////////////////////////////////////
error = hipMalloc((void**)&d_M,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_M");
exit(0);
}
error = hipMalloc((void**)&d_N,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_N");
exit(0);
}
error = hipMalloc((void**)&d_P,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_P");
exit(0);
}
//////////////////////Algoritmo Paralelo///////////////////////////
startGPU = clock();
error = hipMemcpy(d_M, h_M, size, hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error copiando datos a d_M");
exit(0);
}
error = hipMemcpy(d_N, h_N, size, hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error copiando datos a d_N");
exit(0);
}
int blockSize = 32;
dim3 dimBlock(blockSize,blockSize,1);
dim3 dimGrid(ceil(width/float(blockSize)),ceil(width/float(blockSize)),1);
matrixMulKernel<<<dimGrid,dimBlock>>>(d_M,d_N,d_P,width);
hipDeviceSynchronize();
hipMemcpy(h_P_d,d_P,size,hipMemcpyDeviceToHost);
endGPU = clock();
gpu_time_used = ((double) (endGPU - startGPU)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo paralelo: %.10f\n", gpu_time_used);
printf("La aceleración obtenida es de %.10fX\n",cpu_time_used/gpu_time_used);
///////////////////////Algoritmo Paralelo////////////////////////////
testValues(h_P_d,h_P,width);
free(h_M);
free(h_N);
free(h_P);
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
#include<fstream>
__global__ void matrixMulKernel(int *d_M, int *d_N, int *d_P, int width){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int Pvalue;
if((row < width)&&(col < width)){
Pvalue = 0;
for (int k = 0; k < width ; ++k){
Pvalue += d_M[row*width+k] * d_N[k*width+col];
}
d_P[row*width+col] = Pvalue;
}
}
int matrixMulHost(int *h_M, int *h_N, int *h_P, int width){
int Pvalue;
for(int row = 0; row < width ; ++row){
for(int col = 0; col < width ; ++col){
Pvalue = 0;
for(int k = 0; k < width ; ++k){
Pvalue += h_M[row*width+k] * h_N[k*width+col];
}
h_P[row*width+col] = Pvalue;
}
}
return 0;
}
int initValues(int *data, int width){
for(int i = 0; i < width*width; i++)
data[i] = 2;
return 0;
}
int printData(int *data, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
printf("%d ", data[(i*width)+j]);
}
printf("\n");
}
return 0;
}
int testValues(int *A, int *B, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
if(A[(i*width)+j]!=B[(i*width)+j]){
printf("Mal Cálculo...\n");
return 0;
}
}
}
printf("Buen Cálculo ...\n");
return 0;
}
int main(){
int *h_M, *h_N, *h_P,*h_P_d;
int *d_M, *d_N,*d_P;
int width = 2048;
hipError_t error = hipSuccess;
int size = width * width * sizeof(int);
clock_t start, end, startGPU, endGPU;
double cpu_time_used, gpu_time_used;
h_M = (int*)malloc(size);
h_N = (int*)malloc(size);
h_P = (int*)malloc(size);
h_P_d = (int*)malloc(size);
if(h_P_d == NULL)
return 0;
initValues(h_M, width);
initValues(h_N, width);
/////////Algoritmo Secuencial////////////////////////////////////////////
start = clock();
matrixMulHost(h_M, h_N, h_P, width);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo secuencial: %.10f\n", cpu_time_used);
/////////Algoritmo Secuencial/////////////////////////////////////////////
error = hipMalloc((void**)&d_M,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_M");
exit(0);
}
error = hipMalloc((void**)&d_N,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_N");
exit(0);
}
error = hipMalloc((void**)&d_P,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_P");
exit(0);
}
//////////////////////Algoritmo Paralelo///////////////////////////
startGPU = clock();
error = hipMemcpy(d_M, h_M, size, hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error copiando datos a d_M");
exit(0);
}
error = hipMemcpy(d_N, h_N, size, hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error copiando datos a d_N");
exit(0);
}
int blockSize = 32;
dim3 dimBlock(blockSize,blockSize,1);
dim3 dimGrid(ceil(width/float(blockSize)),ceil(width/float(blockSize)),1);
matrixMulKernel<<<dimGrid,dimBlock>>>(d_M,d_N,d_P,width);
hipDeviceSynchronize();
hipMemcpy(h_P_d,d_P,size,hipMemcpyDeviceToHost);
endGPU = clock();
gpu_time_used = ((double) (endGPU - startGPU)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo paralelo: %.10f\n", gpu_time_used);
printf("La aceleración obtenida es de %.10fX\n",cpu_time_used/gpu_time_used);
///////////////////////Algoritmo Paralelo////////////////////////////
testValues(h_P_d,h_P,width);
free(h_M);
free(h_N);
free(h_P);
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMulKernelPiS_S_i
.globl _Z15matrixMulKernelPiS_S_i
.p2align 8
.type _Z15matrixMulKernelPiS_S_i,@function
_Z15matrixMulKernelPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMulKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMulKernelPiS_S_i, .Lfunc_end0-_Z15matrixMulKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMulKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMulKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
#include<fstream>
__global__ void matrixMulKernel(int *d_M, int *d_N, int *d_P, int width){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int Pvalue;
if((row < width)&&(col < width)){
Pvalue = 0;
for (int k = 0; k < width ; ++k){
Pvalue += d_M[row*width+k] * d_N[k*width+col];
}
d_P[row*width+col] = Pvalue;
}
}
int matrixMulHost(int *h_M, int *h_N, int *h_P, int width){
int Pvalue;
for(int row = 0; row < width ; ++row){
for(int col = 0; col < width ; ++col){
Pvalue = 0;
for(int k = 0; k < width ; ++k){
Pvalue += h_M[row*width+k] * h_N[k*width+col];
}
h_P[row*width+col] = Pvalue;
}
}
return 0;
}
int initValues(int *data, int width){
for(int i = 0; i < width*width; i++)
data[i] = 2;
return 0;
}
int printData(int *data, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
printf("%d ", data[(i*width)+j]);
}
printf("\n");
}
return 0;
}
int testValues(int *A, int *B, int width){
for(int i = 0; i < width; ++i){
for(int j = 0; j < width; ++j){
if(A[(i*width)+j]!=B[(i*width)+j]){
printf("Mal Cálculo...\n");
return 0;
}
}
}
printf("Buen Cálculo ...\n");
return 0;
}
int main(){
int *h_M, *h_N, *h_P,*h_P_d;
int *d_M, *d_N,*d_P;
int width = 2048;
hipError_t error = hipSuccess;
int size = width * width * sizeof(int);
clock_t start, end, startGPU, endGPU;
double cpu_time_used, gpu_time_used;
h_M = (int*)malloc(size);
h_N = (int*)malloc(size);
h_P = (int*)malloc(size);
h_P_d = (int*)malloc(size);
if(h_P_d == NULL)
return 0;
initValues(h_M, width);
initValues(h_N, width);
/////////Algoritmo Secuencial////////////////////////////////////////////
start = clock();
matrixMulHost(h_M, h_N, h_P, width);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo secuencial: %.10f\n", cpu_time_used);
/////////Algoritmo Secuencial/////////////////////////////////////////////
error = hipMalloc((void**)&d_M,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_M");
exit(0);
}
error = hipMalloc((void**)&d_N,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_N");
exit(0);
}
error = hipMalloc((void**)&d_P,size);
if(error != hipSuccess){
printf("Error reservando memoria para d_P");
exit(0);
}
//////////////////////Algoritmo Paralelo///////////////////////////
startGPU = clock();
error = hipMemcpy(d_M, h_M, size, hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error copiando datos a d_M");
exit(0);
}
error = hipMemcpy(d_N, h_N, size, hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error copiando datos a d_N");
exit(0);
}
int blockSize = 32;
dim3 dimBlock(blockSize,blockSize,1);
dim3 dimGrid(ceil(width/float(blockSize)),ceil(width/float(blockSize)),1);
matrixMulKernel<<<dimGrid,dimBlock>>>(d_M,d_N,d_P,width);
hipDeviceSynchronize();
hipMemcpy(h_P_d,d_P,size,hipMemcpyDeviceToHost);
endGPU = clock();
gpu_time_used = ((double) (endGPU - startGPU)) / CLOCKS_PER_SEC;
printf("Tiempo algoritmo paralelo: %.10f\n", gpu_time_used);
printf("La aceleración obtenida es de %.10fX\n",cpu_time_used/gpu_time_used);
///////////////////////Algoritmo Paralelo////////////////////////////
testValues(h_P_d,h_P,width);
free(h_M);
free(h_N);
free(h_P);
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
return 0;
} | .text
.file "simpleMatrixMult.hip"
.globl _Z30__device_stub__matrixMulKernelPiS_S_i # -- Begin function _Z30__device_stub__matrixMulKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPiS_S_i,@function
_Z30__device_stub__matrixMulKernelPiS_S_i: # @_Z30__device_stub__matrixMulKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMulKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMulKernelPiS_S_i, .Lfunc_end0-_Z30__device_stub__matrixMulKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13matrixMulHostPiS_S_i # -- Begin function _Z13matrixMulHostPiS_S_i
.p2align 4, 0x90
.type _Z13matrixMulHostPiS_S_i,@function
_Z13matrixMulHostPiS_S_i: # @_Z13matrixMulHostPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB1_7
# %bb.1: # %.preheader26.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %r9d
imull (%r11,%r12,4), %r9d
addl %r9d, %ebp
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB1_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
movl %ebp, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB1_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB1_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB1_2
.LBB1_7: # %._crit_edge32
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13matrixMulHostPiS_S_i, .Lfunc_end1-_Z13matrixMulHostPiS_S_i
.cfi_endproc
# -- End function
.globl _Z10initValuesPii # -- Begin function _Z10initValuesPii
.p2align 4, 0x90
.type _Z10initValuesPii,@function
_Z10initValuesPii: # @_Z10initValuesPii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
je .LBB2_3
# %bb.1: # %.lr.ph.preheader
imull %esi, %esi
cmpl $1, %esi
adcl $0, %esi
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $2, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
jne .LBB2_2
.LBB2_3: # %._crit_edge
xorl %eax, %eax
retq
.Lfunc_end2:
.size _Z10initValuesPii, .Lfunc_end2-_Z10initValuesPii
.cfi_endproc
# -- End function
.globl _Z9printDataPii # -- Begin function _Z9printDataPii
.p2align 4, 0x90
.type _Z9printDataPii,@function
_Z9printDataPii: # @_Z9printDataPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %ebp
cmpq %r15, %r12
jne .LBB3_2
.LBB3_5: # %._crit_edge13
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9printDataPii, .Lfunc_end3-_Z9printDataPii
.cfi_endproc
# -- End function
.globl _Z10testValuesPiS_i # -- Begin function _Z10testValuesPiS_i
.p2align 4, 0x90
.type _Z10testValuesPiS_i,@function
_Z10testValuesPiS_i: # @_Z10testValuesPiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r8
testl %edx, %edx
setg %dil
jle .LBB4_10
# %bb.1: # %.preheader.lr.ph
movl %edx, %r15d
leaq 4(%r8), %r12
leaq (,%r15,4), %rdx
leaq 4(%rsi), %rbx
leaq -1(%r15), %r14
xorl %r13d, %r13d
movq %rsi, 32(%rsp) # 8-byte Spill
movq %r8, 24(%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_7: # %.critedge
# in Loop: Header=BB4_2 Depth=1
incq %r13
cmpq %r15, %r13
setb %dil
addq %rdx, %r12
addq %rdx, %rbx
cmpq %r15, %r13
je .LBB4_10
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movq %r13, %rax
imulq %r15, %rax
movl (%r8,%rax,4), %ecx
cmpl (%rsi,%rax,4), %ecx
jne .LBB4_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rax, %r14
je .LBB4_7
# %bb.5: # in Loop: Header=BB4_4 Depth=2
movl (%r12,%rax,4), %ecx
leaq 1(%rax), %rbp
cmpl (%rbx,%rax,4), %ecx
movq %rbp, %rax
je .LBB4_4
# %bb.6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movb %dil, 15(%rsp) # 1-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdx # 8-byte Reload
movq 24(%rsp), %r8 # 8-byte Reload
movzbl 15(%rsp), %eax # 1-byte Folded Reload
movq 32(%rsp), %rsi # 8-byte Reload
cmpq %r15, %rbp
jae .LBB4_7
# %bb.9: # %.loopexit
testb $1, %al
jne .LBB4_11
.LBB4_10: # %.critedge25
movl $.Lstr.1, %edi
callq puts@PLT
.LBB4_11:
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_8: # %.critedge46
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl $.Lstr, %edi
callq puts@PLT
movl %ebx, %eax
testb $1, %al
je .LBB4_10
jmp .LBB4_11
.Lfunc_end4:
.size _Z10testValuesPiS_i, .Lfunc_end4-_Z10testValuesPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movl $16777216, %edi # imm = 0x1000000
callq malloc
testq %rax, %rax
je .LBB5_32
# %bb.1: # %.lr.ph.i.preheader
movq %rax, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $2, (%rbx,%rax,4)
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB5_2
# %bb.3: # %.lr.ph.i61.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_4: # %.lr.ph.i61
# =>This Inner Loop Header: Depth=1
movl $2, (%r14,%rax,4)
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB5_4
# %bb.5: # %_Z10initValuesPii.exit65
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movq %rbx, %rax
.p2align 4, 0x90
.LBB5_6: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB5_7 Depth 2
# Child Loop BB5_8 Depth 3
movq %rbp, %rcx
shlq $13, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_7: # %.preheader.i
# Parent Loop BB5_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_8 Depth 3
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_8: # Parent Loop BB5_6 Depth=1
# Parent Loop BB5_7 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%rax,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $8192, %r8 # imm = 0x2000
cmpq $2048, %rdi # imm = 0x800
jne .LBB5_8
# %bb.9: # %._crit_edge.i
# in Loop: Header=BB5_7 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $2048, %rsi # imm = 0x800
jne .LBB5_7
# %bb.10: # %._crit_edge30.i
# in Loop: Header=BB5_6 Depth=1
incq %rbp
addq $8192, %rax # imm = 0x2000
cmpq $2048, %rbp # imm = 0x800
jne .LBB5_6
# %bb.11: # %_Z13matrixMulHostPiS_S_i.exit
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str.4, %edi
movsd %xmm0, 48(%rsp) # 8-byte Spill
movb $1, %al
callq printf
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.14:
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_15
# %bb.16:
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_17
# %bb.18:
callq clock
movq %rax, %r13
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_19
# %bb.20:
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_21
# %bb.22:
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_24
# %bb.23:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2048, 36(%rsp) # imm = 0x800
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15matrixMulKernelPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_24:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movb $1, %bpl
movl $.L.str.10, %edi
movb $1, %al
callq printf
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.11, %edi
movb $1, %al
callq printf
movq %r15, %rax
addq $4, %rax
movq %r12, %rcx
addq $4, %rcx
xorl %edx, %edx
.LBB5_25: # %.preheader.i69
# =>This Loop Header: Depth=1
# Child Loop BB5_27 Depth 2
movq %rdx, %rsi
shlq $13, %rsi
movl (%r12,%rsi), %edi
cmpl (%r15,%rsi), %edi
jne .LBB5_29
# %bb.26: # %.lr.ph.preheader
# in Loop: Header=BB5_25 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_27: # %.lr.ph
# Parent Loop BB5_25 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $2047, %rsi # imm = 0x7FF
je .LBB5_33
# %bb.28: # in Loop: Header=BB5_27 Depth=2
movl (%rcx,%rsi,4), %edi
leaq 1(%rsi), %r8
cmpl (%rax,%rsi,4), %edi
movq %r8, %rsi
je .LBB5_27
jmp .LBB5_29
.p2align 4, 0x90
.LBB5_33: # %.critedge.i
# in Loop: Header=BB5_25 Depth=1
cmpq $2047, %rdx # imm = 0x7FF
leaq 1(%rdx), %rsi
setb %bpl
addq $8192, %rax # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
movq %rsi, %rdx
cmpq $2048, %rsi # imm = 0x800
jne .LBB5_25
jmp .LBB5_30
.LBB5_29: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
testb $1, %bpl
jne .LBB5_31
.LBB5_30: # %.critedge25.i
movl $.Lstr.1, %edi
callq puts@PLT
.LBB5_31: # %_Z10testValuesPiS_i.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
.LBB5_32:
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_12:
.cfi_def_cfa_offset 224
movl $.L.str.5, %edi
jmp .LBB5_13
.LBB5_15:
movl $.L.str.6, %edi
jmp .LBB5_13
.LBB5_17:
movl $.L.str.7, %edi
jmp .LBB5_13
.LBB5_19:
movl $.L.str.8, %edi
jmp .LBB5_13
.LBB5_21:
movl $.L.str.9, %edi
.LBB5_13:
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMulKernelPiS_S_i,@object # @_Z15matrixMulKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixMulKernelPiS_S_i
.p2align 3, 0x0
_Z15matrixMulKernelPiS_S_i:
.quad _Z30__device_stub__matrixMulKernelPiS_S_i
.size _Z15matrixMulKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo algoritmo secuencial: %.10f\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error reservando memoria para d_M"
.size .L.str.5, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error reservando memoria para d_N"
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error reservando memoria para d_P"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error copiando datos a d_M"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error copiando datos a d_N"
.size .L.str.9, 27
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Tiempo algoritmo paralelo: %.10f\n"
.size .L.str.10, 34
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "La aceleraci\303\263n obtenida es de %.10fX\n"
.size .L.str.11, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMulKernelPiS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Mal C\303\241lculo..."
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Buen C\303\241lculo ..."
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMulKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMulKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrixMulKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMulKernelPiS_S_i
.globl _Z15matrixMulKernelPiS_S_i
.p2align 8
.type _Z15matrixMulKernelPiS_S_i,@function
_Z15matrixMulKernelPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMulKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMulKernelPiS_S_i, .Lfunc_end0-_Z15matrixMulKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMulKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMulKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080bbf_00000000-6_simpleMatrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3807:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13matrixMulHostPiS_S_i
.type _Z13matrixMulHostPiS_S_i, @function
_Z13matrixMulHostPiS_S_i:
.LFB3800:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %rbp
movq %rdx, %r11
movl %ecx, %r13d
movslq %ecx, %r12
leaq 0(,%r12,4), %rdi
movq %r8, %rbx
addq %rdi, %r8
movl $0, %r14d
.L5:
movq %rbp, %r10
movl $0, %r9d
.L8:
movq %r10, %rcx
movq %rbx, %rax
movl $0, %esi
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
movl %esi, (%r11,%r9,4)
addq $1, %r9
addq $4, %r10
cmpq %r12, %r9
jne .L8
addl $1, %r14d
addq %rdi, %r11
addq %rdi, %rbx
addq %rdi, %r8
cmpl %r14d, %r13d
jne .L5
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
movl $0, %eax
ret
.cfi_endproc
.LFE3800:
.size _Z13matrixMulHostPiS_S_i, .-_Z13matrixMulHostPiS_S_i
.globl _Z10initValuesPii
.type _Z10initValuesPii, @function
_Z10initValuesPii:
.LFB3801:
.cfi_startproc
endbr64
imull %esi, %esi
testl %esi, %esi
jle .L15
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L16:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
.L15:
movl $0, %eax
ret
.cfi_endproc
.LFE3801:
.size _Z10initValuesPii, .-_Z10initValuesPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z9printDataPii
.type _Z9printDataPii, @function
_Z9printDataPii:
.LFB3802:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L19
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L20:
leaq 0(%rbp,%r14), %rbx
.L21:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L20
.L19:
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3802:
.size _Z9printDataPii, .-_Z9printDataPii
.section .rodata.str1.1
.LC2:
.string "Mal C\303\241lculo...\n"
.LC3:
.string "Buen C\303\241lculo ...\n"
.text
.globl _Z10testValuesPiS_i
.type _Z10testValuesPiS_i, @function
_Z10testValuesPiS_i:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L25
movslq %edx, %rax
leaq 0(,%rax,4), %r10
negq %rax
leaq 0(,%rax,4), %r8
movq %r10, %rcx
movl $0, %r9d
.L26:
leaq (%rcx,%r8), %rax
.L29:
movl (%rsi,%rax), %r11d
cmpl %r11d, (%rdi,%rax)
jne .L32
addq $4, %rax
cmpq %rcx, %rax
jne .L29
addl $1, %r9d
addq %r10, %rcx
cmpl %r9d, %edx
jne .L26
.L25:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _Z10testValuesPiS_i, .-_Z10testValuesPiS_i
.globl _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i:
.LFB3829:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMulKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3829:
.size _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
.globl _Z15matrixMulKernelPiS_S_i
.type _Z15matrixMulKernelPiS_S_i, @function
_Z15matrixMulKernelPiS_S_i:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _Z15matrixMulKernelPiS_S_i, .-_Z15matrixMulKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Tiempo algoritmo secuencial: %.10f\n"
.align 8
.LC6:
.string "Error reservando memoria para d_M"
.align 8
.LC7:
.string "Error reservando memoria para d_N"
.align 8
.LC8:
.string "Error reservando memoria para d_P"
.section .rodata.str1.1
.LC9:
.string "Error copiando datos a d_M"
.LC10:
.string "Error copiando datos a d_N"
.section .rodata.str1.8
.align 8
.LC11:
.string "Tiempo algoritmo paralelo: %.10f\n"
.align 8
.LC12:
.string "La aceleraci\303\263n obtenida es de %.10fX\n"
.text
.globl main
.type main, @function
main:
.LFB3804:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $16777216, %edi
call malloc@PLT
testq %rax, %rax
je .L42
movq %rax, %r12
movl $2048, %esi
movq %rbx, %rdi
call _Z10initValuesPii
movl $2048, %esi
movq %rbp, %rdi
call _Z10initValuesPii
call clock@PLT
movq %rax, %r14
movl $2048, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13matrixMulHostPiS_S_i
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %r15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L43
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L44
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L44:
leaq 40(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L45
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L45:
call clock@PLT
movq %rax, %r14
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L46
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L46:
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L47
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L47:
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $64, 60(%rsp)
movl $64, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L48:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $16777216, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %xmm2
divsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2048, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z10testValuesPiS_i
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L42:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl $2048, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z15matrixMulKernelPiS_S_iPiS_S_i
jmp .L48
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3804:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z15matrixMulKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3832:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3832:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpleMatrixMult.hip"
.globl _Z30__device_stub__matrixMulKernelPiS_S_i # -- Begin function _Z30__device_stub__matrixMulKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPiS_S_i,@function
_Z30__device_stub__matrixMulKernelPiS_S_i: # @_Z30__device_stub__matrixMulKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMulKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMulKernelPiS_S_i, .Lfunc_end0-_Z30__device_stub__matrixMulKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13matrixMulHostPiS_S_i # -- Begin function _Z13matrixMulHostPiS_S_i
.p2align 4, 0x90
.type _Z13matrixMulHostPiS_S_i,@function
_Z13matrixMulHostPiS_S_i: # @_Z13matrixMulHostPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB1_7
# %bb.1: # %.preheader26.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %r9d
imull (%r11,%r12,4), %r9d
addl %r9d, %ebp
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB1_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
movl %ebp, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB1_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB1_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB1_2
.LBB1_7: # %._crit_edge32
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13matrixMulHostPiS_S_i, .Lfunc_end1-_Z13matrixMulHostPiS_S_i
.cfi_endproc
# -- End function
.globl _Z10initValuesPii # -- Begin function _Z10initValuesPii
.p2align 4, 0x90
.type _Z10initValuesPii,@function
_Z10initValuesPii: # @_Z10initValuesPii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
je .LBB2_3
# %bb.1: # %.lr.ph.preheader
imull %esi, %esi
cmpl $1, %esi
adcl $0, %esi
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $2, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
jne .LBB2_2
.LBB2_3: # %._crit_edge
xorl %eax, %eax
retq
.Lfunc_end2:
.size _Z10initValuesPii, .Lfunc_end2-_Z10initValuesPii
.cfi_endproc
# -- End function
.globl _Z9printDataPii # -- Begin function _Z9printDataPii
.p2align 4, 0x90
.type _Z9printDataPii,@function
_Z9printDataPii: # @_Z9printDataPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %ebp
cmpq %r15, %r12
jne .LBB3_2
.LBB3_5: # %._crit_edge13
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9printDataPii, .Lfunc_end3-_Z9printDataPii
.cfi_endproc
# -- End function
.globl _Z10testValuesPiS_i # -- Begin function _Z10testValuesPiS_i
.p2align 4, 0x90
.type _Z10testValuesPiS_i,@function
_Z10testValuesPiS_i: # @_Z10testValuesPiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r8
testl %edx, %edx
setg %dil
jle .LBB4_10
# %bb.1: # %.preheader.lr.ph
movl %edx, %r15d
leaq 4(%r8), %r12
leaq (,%r15,4), %rdx
leaq 4(%rsi), %rbx
leaq -1(%r15), %r14
xorl %r13d, %r13d
movq %rsi, 32(%rsp) # 8-byte Spill
movq %r8, 24(%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_7: # %.critedge
# in Loop: Header=BB4_2 Depth=1
incq %r13
cmpq %r15, %r13
setb %dil
addq %rdx, %r12
addq %rdx, %rbx
cmpq %r15, %r13
je .LBB4_10
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movq %r13, %rax
imulq %r15, %rax
movl (%r8,%rax,4), %ecx
cmpl (%rsi,%rax,4), %ecx
jne .LBB4_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rax, %r14
je .LBB4_7
# %bb.5: # in Loop: Header=BB4_4 Depth=2
movl (%r12,%rax,4), %ecx
leaq 1(%rax), %rbp
cmpl (%rbx,%rax,4), %ecx
movq %rbp, %rax
je .LBB4_4
# %bb.6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movb %dil, 15(%rsp) # 1-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdx # 8-byte Reload
movq 24(%rsp), %r8 # 8-byte Reload
movzbl 15(%rsp), %eax # 1-byte Folded Reload
movq 32(%rsp), %rsi # 8-byte Reload
cmpq %r15, %rbp
jae .LBB4_7
# %bb.9: # %.loopexit
testb $1, %al
jne .LBB4_11
.LBB4_10: # %.critedge25
movl $.Lstr.1, %edi
callq puts@PLT
.LBB4_11:
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_8: # %.critedge46
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl $.Lstr, %edi
callq puts@PLT
movl %ebx, %eax
testb $1, %al
je .LBB4_10
jmp .LBB4_11
.Lfunc_end4:
.size _Z10testValuesPiS_i, .Lfunc_end4-_Z10testValuesPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movl $16777216, %edi # imm = 0x1000000
callq malloc
testq %rax, %rax
je .LBB5_32
# %bb.1: # %.lr.ph.i.preheader
movq %rax, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $2, (%rbx,%rax,4)
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB5_2
# %bb.3: # %.lr.ph.i61.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_4: # %.lr.ph.i61
# =>This Inner Loop Header: Depth=1
movl $2, (%r14,%rax,4)
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB5_4
# %bb.5: # %_Z10initValuesPii.exit65
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movq %rbx, %rax
.p2align 4, 0x90
.LBB5_6: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB5_7 Depth 2
# Child Loop BB5_8 Depth 3
movq %rbp, %rcx
shlq $13, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_7: # %.preheader.i
# Parent Loop BB5_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_8 Depth 3
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_8: # Parent Loop BB5_6 Depth=1
# Parent Loop BB5_7 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%rax,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $8192, %r8 # imm = 0x2000
cmpq $2048, %rdi # imm = 0x800
jne .LBB5_8
# %bb.9: # %._crit_edge.i
# in Loop: Header=BB5_7 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $2048, %rsi # imm = 0x800
jne .LBB5_7
# %bb.10: # %._crit_edge30.i
# in Loop: Header=BB5_6 Depth=1
incq %rbp
addq $8192, %rax # imm = 0x2000
cmpq $2048, %rbp # imm = 0x800
jne .LBB5_6
# %bb.11: # %_Z13matrixMulHostPiS_S_i.exit
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str.4, %edi
movsd %xmm0, 48(%rsp) # 8-byte Spill
movb $1, %al
callq printf
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.14:
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_15
# %bb.16:
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_17
# %bb.18:
callq clock
movq %rax, %r13
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_19
# %bb.20:
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_21
# %bb.22:
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_24
# %bb.23:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2048, 36(%rsp) # imm = 0x800
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15matrixMulKernelPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_24:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movb $1, %bpl
movl $.L.str.10, %edi
movb $1, %al
callq printf
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.11, %edi
movb $1, %al
callq printf
movq %r15, %rax
addq $4, %rax
movq %r12, %rcx
addq $4, %rcx
xorl %edx, %edx
.LBB5_25: # %.preheader.i69
# =>This Loop Header: Depth=1
# Child Loop BB5_27 Depth 2
movq %rdx, %rsi
shlq $13, %rsi
movl (%r12,%rsi), %edi
cmpl (%r15,%rsi), %edi
jne .LBB5_29
# %bb.26: # %.lr.ph.preheader
# in Loop: Header=BB5_25 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_27: # %.lr.ph
# Parent Loop BB5_25 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $2047, %rsi # imm = 0x7FF
je .LBB5_33
# %bb.28: # in Loop: Header=BB5_27 Depth=2
movl (%rcx,%rsi,4), %edi
leaq 1(%rsi), %r8
cmpl (%rax,%rsi,4), %edi
movq %r8, %rsi
je .LBB5_27
jmp .LBB5_29
.p2align 4, 0x90
.LBB5_33: # %.critedge.i
# in Loop: Header=BB5_25 Depth=1
cmpq $2047, %rdx # imm = 0x7FF
leaq 1(%rdx), %rsi
setb %bpl
addq $8192, %rax # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
movq %rsi, %rdx
cmpq $2048, %rsi # imm = 0x800
jne .LBB5_25
jmp .LBB5_30
.LBB5_29: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
testb $1, %bpl
jne .LBB5_31
.LBB5_30: # %.critedge25.i
movl $.Lstr.1, %edi
callq puts@PLT
.LBB5_31: # %_Z10testValuesPiS_i.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
.LBB5_32:
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_12:
.cfi_def_cfa_offset 224
movl $.L.str.5, %edi
jmp .LBB5_13
.LBB5_15:
movl $.L.str.6, %edi
jmp .LBB5_13
.LBB5_17:
movl $.L.str.7, %edi
jmp .LBB5_13
.LBB5_19:
movl $.L.str.8, %edi
jmp .LBB5_13
.LBB5_21:
movl $.L.str.9, %edi
.LBB5_13:
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMulKernelPiS_S_i,@object # @_Z15matrixMulKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixMulKernelPiS_S_i
.p2align 3, 0x0
_Z15matrixMulKernelPiS_S_i:
.quad _Z30__device_stub__matrixMulKernelPiS_S_i
.size _Z15matrixMulKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo algoritmo secuencial: %.10f\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error reservando memoria para d_M"
.size .L.str.5, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error reservando memoria para d_N"
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error reservando memoria para d_P"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error copiando datos a d_M"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error copiando datos a d_N"
.size .L.str.9, 27
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Tiempo algoritmo paralelo: %.10f\n"
.size .L.str.10, 34
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "La aceleraci\303\263n obtenida es de %.10fX\n"
.size .L.str.11, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMulKernelPiS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Mal C\303\241lculo..."
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Buen C\303\241lculo ..."
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMulKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMulKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define m 10
#define n 5
__global__ void matrix_sum(int A[], int B[], int C[], int fil, int col)
{
int my_ij = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < fil && threadIdx.x < col)
C[my_ij] = A[my_ij] + B[my_ij];
}
void fill_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
A[i*n+j] = rand()%99;
}
}
void print_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
printf("%d ", A[i*n+j]);
printf("\n");
}
}
int main(int argc, char* argv[]) {
int *h_A, *h_B, *h_C;
int *d_A, *d_B, *d_C;
size_t size;
size = m*n*sizeof(int);
h_A = (int*) malloc(size);
h_B = (int*) malloc(size);
h_C = (int*) malloc(size);
fill_matrix(h_A, m, n);
fill_matrix(h_B, m, n);
print_matrix(h_A, m, n);
printf("\n");
print_matrix(h_B, m, n);
printf("\n");
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_C, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
matrix_sum<<<m, n>>>(d_A, d_B, d_C, m, n);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
print_matrix(h_C, m, n);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | code for sm_80
Function : _Z10matrix_sumPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0020*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0030*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x001fc80003f06070 */
/*0040*/ ISETP.GE.U32.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x002fda0000706470 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x000fe200078e0203 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define m 10
#define n 5
__global__ void matrix_sum(int A[], int B[], int C[], int fil, int col)
{
int my_ij = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < fil && threadIdx.x < col)
C[my_ij] = A[my_ij] + B[my_ij];
}
void fill_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
A[i*n+j] = rand()%99;
}
}
void print_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
printf("%d ", A[i*n+j]);
printf("\n");
}
}
int main(int argc, char* argv[]) {
int *h_A, *h_B, *h_C;
int *d_A, *d_B, *d_C;
size_t size;
size = m*n*sizeof(int);
h_A = (int*) malloc(size);
h_B = (int*) malloc(size);
h_C = (int*) malloc(size);
fill_matrix(h_A, m, n);
fill_matrix(h_B, m, n);
print_matrix(h_A, m, n);
printf("\n");
print_matrix(h_B, m, n);
printf("\n");
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_C, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
matrix_sum<<<m, n>>>(d_A, d_B, d_C, m, n);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
print_matrix(h_C, m, n);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .file "tmpxft_000ecceb_00000000-6_matrix_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_matrixPiii
.type _Z11fill_matrixPiii, @function
_Z11fill_matrixPiii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movl %edx, %r14d
movslq %edx, %rax
leaq (%rdi,%rax,4), %rbp
leal (%rsi,%rsi,4), %r15d
movl $0, %r12d
jmp .L5
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $5, %r12d
addq $20, %rbp
cmpl %r15d, %r12d
je .L3
.L5:
movslq %r12d, %rax
leaq 0(%r13,%rax,4), %rbx
testl %r14d, %r14d
jg .L6
jmp .L8
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_matrixPiii, .-_Z11fill_matrixPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPiii
.type _Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L24
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movl %edx, %r15d
movslq %edx, %rax
leaq (%rdi,%rax,4), %rbp
leal (%rsi,%rsi,4), %eax
movl %eax, 12(%rsp)
movl $0, %r13d
leaq .LC0(%rip), %r12
jmp .L17
.L18:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $5, %r13d
addq $20, %rbp
movl 12(%rsp), %eax
cmpl %eax, %r13d
je .L15
.L17:
movslq %r13d, %rax
leaq (%r14,%rax,4), %rbx
testl %r15d, %r15d
jg .L18
jmp .L20
.L15:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z12print_matrixPiii, .-_Z12print_matrixPiii
.globl _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_sumPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
.globl _Z10matrix_sumPiS_S_ii
.type _Z10matrix_sumPiS_S_ii, @function
_Z10matrix_sumPiS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrix_sumPiS_S_ii, .-_Z10matrix_sumPiS_S_ii
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, %rbp
movl $200, %edi
call malloc@PLT
movq %rax, %rbx
movl $200, %edi
call malloc@PLT
movq %rax, %r12
movl $5, %edx
movl $10, %esi
movq %rbp, %rdi
call _Z11fill_matrixPiii
movl $5, %edx
movl $10, %esi
movq %rbx, %rdi
call _Z11fill_matrixPiii
movl $5, %edx
movl $10, %esi
movq %rbp, %rdi
call _Z12print_matrixPiii
leaq .LC1(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %edx
movl $10, %esi
movq %rbx, %rdi
call _Z12print_matrixPiii
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
movl $2, %ecx
movl $200, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $5, %edx
movl $10, %esi
movq %r12, %rdi
call _Z12print_matrixPiii
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $5, %r8d
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10matrix_sumPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_sumPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define m 10
#define n 5
__global__ void matrix_sum(int A[], int B[], int C[], int fil, int col)
{
int my_ij = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < fil && threadIdx.x < col)
C[my_ij] = A[my_ij] + B[my_ij];
}
void fill_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
A[i*n+j] = rand()%99;
}
}
void print_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
printf("%d ", A[i*n+j]);
printf("\n");
}
}
int main(int argc, char* argv[]) {
int *h_A, *h_B, *h_C;
int *d_A, *d_B, *d_C;
size_t size;
size = m*n*sizeof(int);
h_A = (int*) malloc(size);
h_B = (int*) malloc(size);
h_C = (int*) malloc(size);
fill_matrix(h_A, m, n);
fill_matrix(h_B, m, n);
print_matrix(h_A, m, n);
printf("\n");
print_matrix(h_B, m, n);
printf("\n");
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_C, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
matrix_sum<<<m, n>>>(d_A, d_B, d_C, m, n);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
print_matrix(h_C, m, n);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define m 10
#define n 5
__global__ void matrix_sum(int A[], int B[], int C[], int fil, int col)
{
int my_ij = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < fil && threadIdx.x < col)
C[my_ij] = A[my_ij] + B[my_ij];
}
void fill_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
A[i*n+j] = rand()%99;
}
}
void print_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
printf("%d ", A[i*n+j]);
printf("\n");
}
}
int main(int argc, char* argv[]) {
int *h_A, *h_B, *h_C;
int *d_A, *d_B, *d_C;
size_t size;
size = m*n*sizeof(int);
h_A = (int*) malloc(size);
h_B = (int*) malloc(size);
h_C = (int*) malloc(size);
fill_matrix(h_A, m, n);
fill_matrix(h_B, m, n);
print_matrix(h_A, m, n);
printf("\n");
print_matrix(h_B, m, n);
printf("\n");
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_C, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
matrix_sum<<<m, n>>>(d_A, d_B, d_C, m, n);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
print_matrix(h_C, m, n);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define m 10
#define n 5
__global__ void matrix_sum(int A[], int B[], int C[], int fil, int col)
{
int my_ij = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < fil && threadIdx.x < col)
C[my_ij] = A[my_ij] + B[my_ij];
}
void fill_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
A[i*n+j] = rand()%99;
}
}
void print_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
printf("%d ", A[i*n+j]);
printf("\n");
}
}
int main(int argc, char* argv[]) {
int *h_A, *h_B, *h_C;
int *d_A, *d_B, *d_C;
size_t size;
size = m*n*sizeof(int);
h_A = (int*) malloc(size);
h_B = (int*) malloc(size);
h_C = (int*) malloc(size);
fill_matrix(h_A, m, n);
fill_matrix(h_B, m, n);
print_matrix(h_A, m, n);
printf("\n");
print_matrix(h_B, m, n);
printf("\n");
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_C, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
matrix_sum<<<m, n>>>(d_A, d_B, d_C, m, n);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
print_matrix(h_C, m, n);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_sumPiS_S_ii
.globl _Z10matrix_sumPiS_S_ii
.p2align 8
.type _Z10matrix_sumPiS_S_ii,@function
_Z10matrix_sumPiS_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_cmp_lt_u32 s15, s2
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_sumPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_sumPiS_S_ii, .Lfunc_end0-_Z10matrix_sumPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_sumPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_sumPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define m 10
#define n 5
__global__ void matrix_sum(int A[], int B[], int C[], int fil, int col)
{
int my_ij = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < fil && threadIdx.x < col)
C[my_ij] = A[my_ij] + B[my_ij];
}
void fill_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
A[i*n+j] = rand()%99;
}
}
void print_matrix(int A[], int fil, int col) {
int i, j;
for (i = 0; i < fil; i++) {
for (j = 0; j < col; j++)
printf("%d ", A[i*n+j]);
printf("\n");
}
}
int main(int argc, char* argv[]) {
int *h_A, *h_B, *h_C;
int *d_A, *d_B, *d_C;
size_t size;
size = m*n*sizeof(int);
h_A = (int*) malloc(size);
h_B = (int*) malloc(size);
h_C = (int*) malloc(size);
fill_matrix(h_A, m, n);
fill_matrix(h_B, m, n);
print_matrix(h_A, m, n);
printf("\n");
print_matrix(h_B, m, n);
printf("\n");
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_C, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
matrix_sum<<<m, n>>>(d_A, d_B, d_C, m, n);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
print_matrix(h_C, m, n);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.file "matrix_sum.hip"
.globl _Z25__device_stub__matrix_sumPiS_S_ii # -- Begin function _Z25__device_stub__matrix_sumPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__matrix_sumPiS_S_ii,@function
_Z25__device_stub__matrix_sumPiS_S_ii: # @_Z25__device_stub__matrix_sumPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_sumPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_sumPiS_S_ii, .Lfunc_end0-_Z25__device_stub__matrix_sumPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z11fill_matrixPiii # -- Begin function _Z11fill_matrixPiii
.p2align 4, 0x90
.type _Z11fill_matrixPiii,@function
_Z11fill_matrixPiii: # @_Z11fill_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %r15d
movl 12(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addl $5, %r13d
cmpq %r15, %rbp
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq %rbx, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge11
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11fill_matrixPiii, .Lfunc_end1-_Z11fill_matrixPiii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPiii # -- Begin function _Z12print_matrixPiii
.p2align 4, 0x90
.type _Z12print_matrixPiii,@function
_Z12print_matrixPiii: # @_Z12print_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %r15d
movl 12(%rsp), %r12d # 4-byte Reload
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl $5, %ebp
cmpq %r15, %r13
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge11
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12print_matrixPiii, .Lfunc_end2-_Z12print_matrixPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $200, %edi
callq malloc
movq %rax, %rbx
movl $200, %edi
callq malloc
movq %rax, %r14
movl $200, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $5, %rbp
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %r12
addq $20, %r13
cmpq $10, %r12
jne .LBB3_1
# %bb.4: # %.preheader.i22.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB3_5: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $5, %rbp
jne .LBB3_6
# %bb.7: # %._crit_edge.i27
# in Loop: Header=BB3_5 Depth=1
incq %r12
addq $20, %r13
cmpq $10, %r12
jne .LBB3_5
# %bb.8: # %.preheader.i31.preheader
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_9: # %.preheader.i31
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $5, %rbp
jne .LBB3_10
# %bb.11: # %._crit_edge.i36
# in Loop: Header=BB3_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $20, %r12
cmpq $10, %r13
jne .LBB3_9
# %bb.12: # %_Z12print_matrixPiii.exit
movl $10, %edi
callq putchar@PLT
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_13: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_14: # Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $5, %rbp
jne .LBB3_14
# %bb.15: # %._crit_edge.i44
# in Loop: Header=BB3_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $20, %r12
cmpq $10, %r13
jne .LBB3_13
# %bb.16: # %_Z12print_matrixPiii.exit48
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $200, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $200, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $200, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967301, %rdx # imm = 0x100000005
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.17:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
movl $5, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10matrix_sumPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_18:
movq 8(%rsp), %rsi
movl $200, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_19: # %.preheader.i49
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_20: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $5, %rbp
jne .LBB3_20
# %bb.21: # %._crit_edge.i54
# in Loop: Header=BB3_19 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $20, %r12
cmpq $10, %r13
jne .LBB3_19
# %bb.22: # %_Z12print_matrixPiii.exit58
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_sumPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_sumPiS_S_ii,@object # @_Z10matrix_sumPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10matrix_sumPiS_S_ii
.p2align 3, 0x0
_Z10matrix_sumPiS_S_ii:
.quad _Z25__device_stub__matrix_sumPiS_S_ii
.size _Z10matrix_sumPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_sumPiS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_sumPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_sumPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrix_sumPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0020*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0030*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x001fc80003f06070 */
/*0040*/ ISETP.GE.U32.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x002fda0000706470 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x000fe200078e0203 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_sumPiS_S_ii
.globl _Z10matrix_sumPiS_S_ii
.p2align 8
.type _Z10matrix_sumPiS_S_ii,@function
_Z10matrix_sumPiS_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_cmp_lt_u32 s15, s2
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_sumPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_sumPiS_S_ii, .Lfunc_end0-_Z10matrix_sumPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_sumPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_sumPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ecceb_00000000-6_matrix_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_matrixPiii
.type _Z11fill_matrixPiii, @function
_Z11fill_matrixPiii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movl %edx, %r14d
movslq %edx, %rax
leaq (%rdi,%rax,4), %rbp
leal (%rsi,%rsi,4), %r15d
movl $0, %r12d
jmp .L5
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $5, %r12d
addq $20, %rbp
cmpl %r15d, %r12d
je .L3
.L5:
movslq %r12d, %rax
leaq 0(%r13,%rax,4), %rbx
testl %r14d, %r14d
jg .L6
jmp .L8
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_matrixPiii, .-_Z11fill_matrixPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPiii
.type _Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L24
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movl %edx, %r15d
movslq %edx, %rax
leaq (%rdi,%rax,4), %rbp
leal (%rsi,%rsi,4), %eax
movl %eax, 12(%rsp)
movl $0, %r13d
leaq .LC0(%rip), %r12
jmp .L17
.L18:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $5, %r13d
addq $20, %rbp
movl 12(%rsp), %eax
cmpl %eax, %r13d
je .L15
.L17:
movslq %r13d, %rax
leaq (%r14,%rax,4), %rbx
testl %r15d, %r15d
jg .L18
jmp .L20
.L15:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z12print_matrixPiii, .-_Z12print_matrixPiii
.globl _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_sumPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
.globl _Z10matrix_sumPiS_S_ii
.type _Z10matrix_sumPiS_S_ii, @function
_Z10matrix_sumPiS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrix_sumPiS_S_ii, .-_Z10matrix_sumPiS_S_ii
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, %rbp
movl $200, %edi
call malloc@PLT
movq %rax, %rbx
movl $200, %edi
call malloc@PLT
movq %rax, %r12
movl $5, %edx
movl $10, %esi
movq %rbp, %rdi
call _Z11fill_matrixPiii
movl $5, %edx
movl $10, %esi
movq %rbx, %rdi
call _Z11fill_matrixPiii
movl $5, %edx
movl $10, %esi
movq %rbp, %rdi
call _Z12print_matrixPiii
leaq .LC1(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %edx
movl $10, %esi
movq %rbx, %rdi
call _Z12print_matrixPiii
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
movl $2, %ecx
movl $200, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $5, %edx
movl $10, %esi
movq %r12, %rdi
call _Z12print_matrixPiii
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $5, %r8d
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z10matrix_sumPiS_S_iiPiS_S_ii
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10matrix_sumPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_sumPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_sum.hip"
.globl _Z25__device_stub__matrix_sumPiS_S_ii # -- Begin function _Z25__device_stub__matrix_sumPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__matrix_sumPiS_S_ii,@function
_Z25__device_stub__matrix_sumPiS_S_ii: # @_Z25__device_stub__matrix_sumPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_sumPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_sumPiS_S_ii, .Lfunc_end0-_Z25__device_stub__matrix_sumPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z11fill_matrixPiii # -- Begin function _Z11fill_matrixPiii
.p2align 4, 0x90
.type _Z11fill_matrixPiii,@function
_Z11fill_matrixPiii: # @_Z11fill_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %r15d
movl 12(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addl $5, %r13d
cmpq %r15, %rbp
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq %rbx, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge11
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11fill_matrixPiii, .Lfunc_end1-_Z11fill_matrixPiii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPiii # -- Begin function _Z12print_matrixPiii
.p2align 4, 0x90
.type _Z12print_matrixPiii,@function
_Z12print_matrixPiii: # @_Z12print_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %r15d
movl 12(%rsp), %r12d # 4-byte Reload
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl $5, %ebp
cmpq %r15, %r13
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge11
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12print_matrixPiii, .Lfunc_end2-_Z12print_matrixPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $200, %edi
callq malloc
movq %rax, %rbx
movl $200, %edi
callq malloc
movq %rax, %r14
movl $200, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $5, %rbp
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %r12
addq $20, %r13
cmpq $10, %r12
jne .LBB3_1
# %bb.4: # %.preheader.i22.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB3_5: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $5, %rbp
jne .LBB3_6
# %bb.7: # %._crit_edge.i27
# in Loop: Header=BB3_5 Depth=1
incq %r12
addq $20, %r13
cmpq $10, %r12
jne .LBB3_5
# %bb.8: # %.preheader.i31.preheader
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_9: # %.preheader.i31
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $5, %rbp
jne .LBB3_10
# %bb.11: # %._crit_edge.i36
# in Loop: Header=BB3_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $20, %r12
cmpq $10, %r13
jne .LBB3_9
# %bb.12: # %_Z12print_matrixPiii.exit
movl $10, %edi
callq putchar@PLT
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_13: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_14: # Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $5, %rbp
jne .LBB3_14
# %bb.15: # %._crit_edge.i44
# in Loop: Header=BB3_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $20, %r12
cmpq $10, %r13
jne .LBB3_13
# %bb.16: # %_Z12print_matrixPiii.exit48
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $200, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $200, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $200, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967301, %rdx # imm = 0x100000005
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.17:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
movl $5, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10matrix_sumPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_18:
movq 8(%rsp), %rsi
movl $200, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_19: # %.preheader.i49
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_20: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $5, %rbp
jne .LBB3_20
# %bb.21: # %._crit_edge.i54
# in Loop: Header=BB3_19 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $20, %r12
cmpq $10, %r13
jne .LBB3_19
# %bb.22: # %_Z12print_matrixPiii.exit58
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_sumPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_sumPiS_S_ii,@object # @_Z10matrix_sumPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10matrix_sumPiS_S_ii
.p2align 3, 0x0
_Z10matrix_sumPiS_S_ii:
.quad _Z25__device_stub__matrix_sumPiS_S_ii
.size _Z10matrix_sumPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_sumPiS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_sumPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_sumPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <time.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000
void initializeMatrices(int a[N][N], int b[N][N]) {
srand(time(NULL));
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
a[i][j] = rand() % 50;
b[i][j] = rand() % 50;
}
}
}
__global__ void matrixProduct(int *a, int *b, int *c, int width) {
int sum = 0;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int col = threadIdx.x + blockDim.x * blockIdx.x;
// printf("Thread in block position: (%d, %d) \n", row, col);
if (col < width && row < width) {
for (int k=0; k<width; k++) {
sum += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = sum;
}
}
void showMatrices(int a[N][N], int b[N][N], int c[N][N]) {
printf("***** MATRIX A *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", a[i][j]) : printf("%d,", a[i][j]);
}
}
printf("***** MATRIX B *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", b[i][j]) : printf("%d,", b[i][j]);
}
}
printf("***** MATRIX C *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", c[i][j]) : printf("%d,", c[i][j]);
}
}
}
int main() {
struct timeval t1, t2;
gettimeofday(&t1, 0);
int h_a[N][N], h_b[N][N], h_c[N][N];
int *d_a, *d_b, *d_c;
initializeMatrices(h_a, h_b);
double size = (double) N * N * sizeof(int);
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
matrixProduct<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);
cudaDeviceSynchronize();
cudaGetLastError();
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// showMatrices(a, b, c);
cudaDeviceReset();
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000000.0;
printf("Time to calculate: %3.1f ms \n", time);
return 0;
} | code for sm_80
Function : _Z13matrixProductPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <time.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000
void initializeMatrices(int a[N][N], int b[N][N]) {
srand(time(NULL));
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
a[i][j] = rand() % 50;
b[i][j] = rand() % 50;
}
}
}
__global__ void matrixProduct(int *a, int *b, int *c, int width) {
int sum = 0;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int col = threadIdx.x + blockDim.x * blockIdx.x;
// printf("Thread in block position: (%d, %d) \n", row, col);
if (col < width && row < width) {
for (int k=0; k<width; k++) {
sum += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = sum;
}
}
void showMatrices(int a[N][N], int b[N][N], int c[N][N]) {
printf("***** MATRIX A *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", a[i][j]) : printf("%d,", a[i][j]);
}
}
printf("***** MATRIX B *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", b[i][j]) : printf("%d,", b[i][j]);
}
}
printf("***** MATRIX C *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", c[i][j]) : printf("%d,", c[i][j]);
}
}
}
int main() {
struct timeval t1, t2;
gettimeofday(&t1, 0);
int h_a[N][N], h_b[N][N], h_c[N][N];
int *d_a, *d_b, *d_c;
initializeMatrices(h_a, h_b);
double size = (double) N * N * sizeof(int);
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
matrixProduct<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);
cudaDeviceSynchronize();
cudaGetLastError();
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// showMatrices(a, b, c);
cudaDeviceReset();
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000000.0;
printf("Time to calculate: %3.1f ms \n", time);
return 0;
} | .file "tmpxft_001398af_00000000-6_matrix_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18initializeMatricesPA10000_iS0_
.type _Z18initializeMatricesPA10000_iS0_, @function
_Z18initializeMatricesPA10000_iS0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
movq %rsi, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r15, %r13
addq $400000000, %r15
.L4:
movq %r13, %r12
movq %r14, %rbp
movl $0, %ebx
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $40000, %rbx
jne .L5
addq $40000, %r13
addq $40000, %r14
cmpq %r15, %r13
jne .L4
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z18initializeMatricesPA10000_iS0_, .-_Z18initializeMatricesPA10000_iS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "***** MATRIX A *****\n"
.LC1:
.string "%d \n"
.LC2:
.string "%d,"
.LC3:
.string "***** MATRIX B *****\n"
.LC4:
.string "***** MATRIX C *****\n"
.text
.globl _Z12showMatricesPA10000_iS0_S0_
.type _Z12showMatricesPA10000_iS0_S0_, @function
_Z12showMatricesPA10000_iS0_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %r14
addq $400000000, %r15
leaq .LC2(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L10
.L11:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
je .L12
.L13:
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $10000, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9999, %edx
jne .L11
movl 39996(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
addq $40000, %r14
cmpq %r15, %r14
je .L14
.L10:
movq %r14, %rbp
movl $0, %ebx
jmp .L13
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %r15
movq %r15, %r14
addq $400000000, %r15
leaq .LC2(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L15
.L16:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
je .L17
.L18:
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $10000, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9999, %edx
jne .L16
movl 39996(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
addq $40000, %r14
cmpq %r15, %r14
je .L19
.L15:
movq %r14, %rbp
movl $0, %ebx
jmp .L18
.L19:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %r15
movq %r15, %r14
addq $400000000, %r15
leaq .LC2(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L20
.L21:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
je .L22
.L23:
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $10000, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9999, %edx
jne .L21
movl 39996(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
addq $40000, %r14
cmpq %r14, %r15
je .L9
.L20:
movq %r14, %rbp
movl $0, %ebx
jmp .L23
.L9:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12showMatricesPA10000_iS0_S0_, .-_Z12showMatricesPA10000_iS0_S0_
.globl _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixProductPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
.globl _Z13matrixProductPiS_S_i
.type _Z13matrixProductPiS_S_i, @function
_Z13matrixProductPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13matrixProductPiS_S_i, .-_Z13matrixProductPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Time to calculate: %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -1199996928(%rsp), %r11
.cfi_def_cfa 11, 1199996952
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3176, %rsp
.cfi_def_cfa_offset 1200000128
movq %fs:40, %rax
movq %rax, 1200000088(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 400000080(%rsp), %rbx
leaq 80(%rsp), %rbp
movq %rbx, %rsi
movq %rbp, %rdi
call _Z18initializeMatricesPA10000_iS0_
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $10000, 36(%rsp)
movl $10000, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L38:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
leaq 800000080(%rsp), %rdi
movl $2, %ecx
movl $400000000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC5(%rip), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 72(%rsp), %xmm2
addsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 56(%rsp), %xmm2
subsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1200000088(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $1200000104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl $10000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
jmp .L38
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13matrixProductPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixProductPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <time.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000
void initializeMatrices(int a[N][N], int b[N][N]) {
srand(time(NULL));
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
a[i][j] = rand() % 50;
b[i][j] = rand() % 50;
}
}
}
__global__ void matrixProduct(int *a, int *b, int *c, int width) {
int sum = 0;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int col = threadIdx.x + blockDim.x * blockIdx.x;
// printf("Thread in block position: (%d, %d) \n", row, col);
if (col < width && row < width) {
for (int k=0; k<width; k++) {
sum += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = sum;
}
}
void showMatrices(int a[N][N], int b[N][N], int c[N][N]) {
printf("***** MATRIX A *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", a[i][j]) : printf("%d,", a[i][j]);
}
}
printf("***** MATRIX B *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", b[i][j]) : printf("%d,", b[i][j]);
}
}
printf("***** MATRIX C *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", c[i][j]) : printf("%d,", c[i][j]);
}
}
}
int main() {
struct timeval t1, t2;
gettimeofday(&t1, 0);
int h_a[N][N], h_b[N][N], h_c[N][N];
int *d_a, *d_b, *d_c;
initializeMatrices(h_a, h_b);
double size = (double) N * N * sizeof(int);
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
matrixProduct<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);
cudaDeviceSynchronize();
cudaGetLastError();
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// showMatrices(a, b, c);
cudaDeviceReset();
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000000.0;
printf("Time to calculate: %3.1f ms \n", time);
return 0;
} | #include <hip/hip_runtime.h>
#include <time.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000
void initializeMatrices(int a[N][N], int b[N][N]) {
srand(time(NULL));
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
a[i][j] = rand() % 50;
b[i][j] = rand() % 50;
}
}
}
__global__ void matrixProduct(int *a, int *b, int *c, int width) {
int sum = 0;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int col = threadIdx.x + blockDim.x * blockIdx.x;
// printf("Thread in block position: (%d, %d) \n", row, col);
if (col < width && row < width) {
for (int k=0; k<width; k++) {
sum += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = sum;
}
}
void showMatrices(int a[N][N], int b[N][N], int c[N][N]) {
printf("***** MATRIX A *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", a[i][j]) : printf("%d,", a[i][j]);
}
}
printf("***** MATRIX B *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", b[i][j]) : printf("%d,", b[i][j]);
}
}
printf("***** MATRIX C *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", c[i][j]) : printf("%d,", c[i][j]);
}
}
}
int main() {
struct timeval t1, t2;
gettimeofday(&t1, 0);
int h_a[N][N], h_b[N][N], h_c[N][N];
int *d_a, *d_b, *d_c;
initializeMatrices(h_a, h_b);
double size = (double) N * N * sizeof(int);
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
matrixProduct<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);
hipDeviceSynchronize();
hipGetLastError();
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// showMatrices(a, b, c);
hipDeviceReset();
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000000.0;
printf("Time to calculate: %3.1f ms \n", time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000
void initializeMatrices(int a[N][N], int b[N][N]) {
srand(time(NULL));
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
a[i][j] = rand() % 50;
b[i][j] = rand() % 50;
}
}
}
__global__ void matrixProduct(int *a, int *b, int *c, int width) {
int sum = 0;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int col = threadIdx.x + blockDim.x * blockIdx.x;
// printf("Thread in block position: (%d, %d) \n", row, col);
if (col < width && row < width) {
for (int k=0; k<width; k++) {
sum += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = sum;
}
}
void showMatrices(int a[N][N], int b[N][N], int c[N][N]) {
printf("***** MATRIX A *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", a[i][j]) : printf("%d,", a[i][j]);
}
}
printf("***** MATRIX B *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", b[i][j]) : printf("%d,", b[i][j]);
}
}
printf("***** MATRIX C *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", c[i][j]) : printf("%d,", c[i][j]);
}
}
}
int main() {
struct timeval t1, t2;
gettimeofday(&t1, 0);
int h_a[N][N], h_b[N][N], h_c[N][N];
int *d_a, *d_b, *d_c;
initializeMatrices(h_a, h_b);
double size = (double) N * N * sizeof(int);
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
matrixProduct<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);
hipDeviceSynchronize();
hipGetLastError();
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// showMatrices(a, b, c);
hipDeviceReset();
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000000.0;
printf("Time to calculate: %3.1f ms \n", time);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixProductPiS_S_i
.globl _Z13matrixProductPiS_S_i
.p2align 8
.type _Z13matrixProductPiS_S_i,@function
_Z13matrixProductPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixProductPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixProductPiS_S_i, .Lfunc_end0-_Z13matrixProductPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixProductPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13matrixProductPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000
void initializeMatrices(int a[N][N], int b[N][N]) {
srand(time(NULL));
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
a[i][j] = rand() % 50;
b[i][j] = rand() % 50;
}
}
}
__global__ void matrixProduct(int *a, int *b, int *c, int width) {
int sum = 0;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int col = threadIdx.x + blockDim.x * blockIdx.x;
// printf("Thread in block position: (%d, %d) \n", row, col);
if (col < width && row < width) {
for (int k=0; k<width; k++) {
sum += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = sum;
}
}
void showMatrices(int a[N][N], int b[N][N], int c[N][N]) {
printf("***** MATRIX A *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", a[i][j]) : printf("%d,", a[i][j]);
}
}
printf("***** MATRIX B *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", b[i][j]) : printf("%d,", b[i][j]);
}
}
printf("***** MATRIX C *****\n");
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
(j % N == N-1) ? printf("%d \n", c[i][j]) : printf("%d,", c[i][j]);
}
}
}
int main() {
struct timeval t1, t2;
gettimeofday(&t1, 0);
int h_a[N][N], h_b[N][N], h_c[N][N];
int *d_a, *d_b, *d_c;
initializeMatrices(h_a, h_b);
double size = (double) N * N * sizeof(int);
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
dim3 dimGrid(1, 1);
dim3 dimBlock(N, N);
matrixProduct<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);
hipDeviceSynchronize();
hipGetLastError();
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// showMatrices(a, b, c);
hipDeviceReset();
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000000.0;
printf("Time to calculate: %3.1f ms \n", time);
return 0;
} | .text
.file "matrix_product.hip"
.globl _Z18initializeMatricesPA10000_iS0_ # -- Begin function _Z18initializeMatricesPA10000_iS0_
.p2align 4, 0x90
.type _Z18initializeMatricesPA10000_iS0_,@function
_Z18initializeMatricesPA10000_iS0_: # @_Z18initializeMatricesPA10000_iS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r15
addq $40000, %rbx # imm = 0x9C40
addq $40000, %r14 # imm = 0x9C40
cmpq $10000, %r15 # imm = 0x2710
jne .LBB0_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18initializeMatricesPA10000_iS0_, .Lfunc_end0-_Z18initializeMatricesPA10000_iS0_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matrixProductPiS_S_i # -- Begin function _Z28__device_stub__matrixProductPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__matrixProductPiS_S_i,@function
_Z28__device_stub__matrixProductPiS_S_i: # @_Z28__device_stub__matrixProductPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixProductPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__matrixProductPiS_S_i, .Lfunc_end1-_Z28__device_stub__matrixProductPiS_S_i
.cfi_endproc
# -- End function
.globl _Z12showMatricesPA10000_iS0_S0_ # -- Begin function _Z12showMatricesPA10000_iS0_S0_
.p2align 4, 0x90
.type _Z12showMatricesPA10000_iS0_S0_,@function
_Z12showMatricesPA10000_iS0_S0_: # @_Z12showMatricesPA10000_iS0_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_1: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-10000, %rbp # imm = 0xD8F0
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 40000(%r15,%rbp,4), %esi
incq %rbp
movl $.L.str.2, %edi
cmoveq %r12, %rdi
xorl %eax, %eax
callq printf
testq %rbp, %rbp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r13
addq $40000, %r15 # imm = 0x9C40
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_1
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.preheader39
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movq $-10000, %r13 # imm = 0xD8F0
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl 40000(%r14,%r13,4), %esi
incq %r13
movl $.L.str.2, %edi
cmoveq %r15, %rdi
xorl %eax, %eax
callq printf
testq %r13, %r13
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %r12
addq $40000, %r14 # imm = 0x9C40
cmpq $10000, %r12 # imm = 0x2710
jne .LBB2_5
# %bb.8:
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.1, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
movq $-10000, %r12 # imm = 0xD8F0
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movl 40000(%rbx,%r12,4), %esi
incq %r12
movl $.L.str.2, %edi
cmoveq %r14, %rdi
xorl %eax, %eax
callq printf
testq %r12, %r12
jne .LBB2_10
# %bb.11: # in Loop: Header=BB2_9 Depth=1
incq %r15
addq $40000, %rbx # imm = 0x9C40
cmpq $10000, %r15 # imm = 0x2710
jne .LBB2_9
# %bb.12:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12showMatricesPA10000_iS0_S0_, .Lfunc_end2-_Z12showMatricesPA10000_iS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1200000136, %rsp # imm = 0x47868C88
.cfi_def_cfa_offset 1200000176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 400000128(%rsp), %r14
leaq 800000128(%rsp), %r15
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r12,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rbx
addq $40000, %r14 # imm = 0x9C40
addq $40000, %r15 # imm = 0x9C40
cmpq $10000, %rbx # imm = 0x2710
jne .LBB3_1
# %bb.4: # %_Z18initializeMatricesPA10000_iS0_.exit
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq 24(%rsp), %rdi
leaq 800000128(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 400000128(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $42949672970000, %rdx # imm = 0x271000002710
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 36(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13matrixProductPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
callq hipGetLastError
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rax
subq 112(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sdq 48(%rsp), %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $1200000136, %rsp # imm = 0x47868C88
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixProductPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13matrixProductPiS_S_i,@object # @_Z13matrixProductPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13matrixProductPiS_S_i
.p2align 3, 0x0
_Z13matrixProductPiS_S_i:
.quad _Z28__device_stub__matrixProductPiS_S_i
.size _Z13matrixProductPiS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d \n"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d,"
.size .L.str.2, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time to calculate: %3.1f ms \n"
.size .L.str.5, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixProductPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "***** MATRIX A *****"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "***** MATRIX B *****"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "***** MATRIX C *****"
.size .Lstr.2, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixProductPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13matrixProductPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13matrixProductPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixProductPiS_S_i
.globl _Z13matrixProductPiS_S_i
.p2align 8
.type _Z13matrixProductPiS_S_i,@function
_Z13matrixProductPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixProductPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixProductPiS_S_i, .Lfunc_end0-_Z13matrixProductPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixProductPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13matrixProductPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001398af_00000000-6_matrix_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18initializeMatricesPA10000_iS0_
.type _Z18initializeMatricesPA10000_iS0_, @function
_Z18initializeMatricesPA10000_iS0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
movq %rsi, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r15, %r13
addq $400000000, %r15
.L4:
movq %r13, %r12
movq %r14, %rbp
movl $0, %ebx
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $40000, %rbx
jne .L5
addq $40000, %r13
addq $40000, %r14
cmpq %r15, %r13
jne .L4
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z18initializeMatricesPA10000_iS0_, .-_Z18initializeMatricesPA10000_iS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "***** MATRIX A *****\n"
.LC1:
.string "%d \n"
.LC2:
.string "%d,"
.LC3:
.string "***** MATRIX B *****\n"
.LC4:
.string "***** MATRIX C *****\n"
.text
.globl _Z12showMatricesPA10000_iS0_S0_
.type _Z12showMatricesPA10000_iS0_S0_, @function
_Z12showMatricesPA10000_iS0_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %r14
addq $400000000, %r15
leaq .LC2(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L10
.L11:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
je .L12
.L13:
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $10000, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9999, %edx
jne .L11
movl 39996(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
addq $40000, %r14
cmpq %r15, %r14
je .L14
.L10:
movq %r14, %rbp
movl $0, %ebx
jmp .L13
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %r15
movq %r15, %r14
addq $400000000, %r15
leaq .LC2(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L15
.L16:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
je .L17
.L18:
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $10000, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9999, %edx
jne .L16
movl 39996(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
addq $40000, %r14
cmpq %r15, %r14
je .L19
.L15:
movq %r14, %rbp
movl $0, %ebx
jmp .L18
.L19:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %r15
movq %r15, %r14
addq $400000000, %r15
leaq .LC2(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L20
.L21:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
je .L22
.L23:
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $10000, %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9999, %edx
jne .L21
movl 39996(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
addq $40000, %r14
cmpq %r14, %r15
je .L9
.L20:
movq %r14, %rbp
movl $0, %ebx
jmp .L23
.L9:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12showMatricesPA10000_iS0_S0_, .-_Z12showMatricesPA10000_iS0_S0_
.globl _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixProductPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
.globl _Z13matrixProductPiS_S_i
.type _Z13matrixProductPiS_S_i, @function
_Z13matrixProductPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13matrixProductPiS_S_i, .-_Z13matrixProductPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Time to calculate: %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -1199996928(%rsp), %r11
.cfi_def_cfa 11, 1199996952
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3176, %rsp
.cfi_def_cfa_offset 1200000128
movq %fs:40, %rax
movq %rax, 1200000088(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 400000080(%rsp), %rbx
leaq 80(%rsp), %rbp
movq %rbx, %rsi
movq %rbp, %rdi
call _Z18initializeMatricesPA10000_iS0_
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $10000, 36(%rsp)
movl $10000, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L38:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
leaq 800000080(%rsp), %rdi
movl $2, %ecx
movl $400000000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC5(%rip), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 72(%rsp), %xmm2
addsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 56(%rsp), %xmm2
subsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1200000088(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $1200000104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl $10000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z38__device_stub__Z13matrixProductPiS_S_iPiS_S_i
jmp .L38
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13matrixProductPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixProductPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_product.hip"
.globl _Z18initializeMatricesPA10000_iS0_ # -- Begin function _Z18initializeMatricesPA10000_iS0_
.p2align 4, 0x90
.type _Z18initializeMatricesPA10000_iS0_,@function
_Z18initializeMatricesPA10000_iS0_: # @_Z18initializeMatricesPA10000_iS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r15
addq $40000, %rbx # imm = 0x9C40
addq $40000, %r14 # imm = 0x9C40
cmpq $10000, %r15 # imm = 0x2710
jne .LBB0_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18initializeMatricesPA10000_iS0_, .Lfunc_end0-_Z18initializeMatricesPA10000_iS0_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matrixProductPiS_S_i # -- Begin function _Z28__device_stub__matrixProductPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__matrixProductPiS_S_i,@function
_Z28__device_stub__matrixProductPiS_S_i: # @_Z28__device_stub__matrixProductPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixProductPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__matrixProductPiS_S_i, .Lfunc_end1-_Z28__device_stub__matrixProductPiS_S_i
.cfi_endproc
# -- End function
.globl _Z12showMatricesPA10000_iS0_S0_ # -- Begin function _Z12showMatricesPA10000_iS0_S0_
.p2align 4, 0x90
.type _Z12showMatricesPA10000_iS0_S0_,@function
_Z12showMatricesPA10000_iS0_S0_: # @_Z12showMatricesPA10000_iS0_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_1: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-10000, %rbp # imm = 0xD8F0
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 40000(%r15,%rbp,4), %esi
incq %rbp
movl $.L.str.2, %edi
cmoveq %r12, %rdi
xorl %eax, %eax
callq printf
testq %rbp, %rbp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r13
addq $40000, %r15 # imm = 0x9C40
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_1
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.preheader39
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movq $-10000, %r13 # imm = 0xD8F0
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl 40000(%r14,%r13,4), %esi
incq %r13
movl $.L.str.2, %edi
cmoveq %r15, %rdi
xorl %eax, %eax
callq printf
testq %r13, %r13
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %r12
addq $40000, %r14 # imm = 0x9C40
cmpq $10000, %r12 # imm = 0x2710
jne .LBB2_5
# %bb.8:
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.1, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
movq $-10000, %r12 # imm = 0xD8F0
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movl 40000(%rbx,%r12,4), %esi
incq %r12
movl $.L.str.2, %edi
cmoveq %r14, %rdi
xorl %eax, %eax
callq printf
testq %r12, %r12
jne .LBB2_10
# %bb.11: # in Loop: Header=BB2_9 Depth=1
incq %r15
addq $40000, %rbx # imm = 0x9C40
cmpq $10000, %r15 # imm = 0x2710
jne .LBB2_9
# %bb.12:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12showMatricesPA10000_iS0_S0_, .Lfunc_end2-_Z12showMatricesPA10000_iS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1200000136, %rsp # imm = 0x47868C88
.cfi_def_cfa_offset 1200000176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 400000128(%rsp), %r14
leaq 800000128(%rsp), %r15
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r12,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rbx
addq $40000, %r14 # imm = 0x9C40
addq $40000, %r15 # imm = 0x9C40
cmpq $10000, %rbx # imm = 0x2710
jne .LBB3_1
# %bb.4: # %_Z18initializeMatricesPA10000_iS0_.exit
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq 24(%rsp), %rdi
leaq 800000128(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 400000128(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $42949672970000, %rdx # imm = 0x271000002710
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 36(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13matrixProductPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
callq hipGetLastError
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rax
subq 112(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sdq 48(%rsp), %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $1200000136, %rsp # imm = 0x47868C88
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixProductPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13matrixProductPiS_S_i,@object # @_Z13matrixProductPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13matrixProductPiS_S_i
.p2align 3, 0x0
_Z13matrixProductPiS_S_i:
.quad _Z28__device_stub__matrixProductPiS_S_i
.size _Z13matrixProductPiS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d \n"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d,"
.size .L.str.2, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time to calculate: %3.1f ms \n"
.size .L.str.5, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixProductPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "***** MATRIX A *****"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "***** MATRIX B *****"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "***** MATRIX C *****"
.size .Lstr.2, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixProductPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13matrixProductPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/**
* Element-wise Vector Multiplication: C[i] = A[i] * B[i].
* This sample is a very basic sample that implements element by element vector multiplication.
*/
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
/**
* CUDA Kernel Device code
* Computes the element-wise vector multiplication of A and B into C. The 3 vectors have the same number of
elements numElements.
*/
__global__ void vectorMultiply(float *A, float *B, float *C, int numElements)
{
int size = numElements * sizeof(float);
float *d_A, *d_B, *d_C;
int i = threadIdx.x + 2* blockDim.x*blockIdx.x;
if (i < numElements) C[i] = A[i] * B[i];
if (i < numElements + blockDim.x) C[i + blockDim.x] = A[i + blockDim.x] + B[i + blockDim.x];
}
//Host main routine
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the vector length to be used, and compute its size
float EPS = 0.00001;
int numElements = 50000;
size_t size = numElements * sizeof(float);
printf("[Vector multiplication of %d elements]\n", numElements);
// Allocate the host input vector A
float *h_A = (float *)malloc(size);
// Allocate the host input vector B
float *h_B = (float *)malloc(size);
// Allocate the host output vector C
float *h_C = (float *)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < numElements; i++)
{
*(h_A + i) = (float)i;
//printf("h_A = %f\n", h_A[i]);
}
for (int i = 0; i < numElements; i++)
*(h_B + i) = (1 / (EPS + i));
// Allocate the device input vector A
float *d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device input vector B
float *d_B = NULL;
err = cudaMalloc((void **)&d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device output vector C
float *d_C = NULL;
err = cudaMalloc((void **)&d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the host input vectors A and B in host memory to the device input vectors in device memory
printf("Copy input data from the host memory to the CUDA device\n");
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Launch the VectorMultiply CUDA Kernel
int threadsPerBlock = 256;
int blocksPerGrid = ceil(numElements / (float) threadsPerBlock);
vectorMultiply <<< blocksPerGrid, threadsPerBlock >>>(d_A, d_B, d_C, numElements);
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < numElements; ++i)
{
if (fabs((h_A[i] * h_B[i]) - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
// Free device global memory
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
printf("Done\n");
return 0;
} | code for sm_80
Function : _Z14vectorMultiplyPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.L.U32 UR4, UR5, 0x1, URZ ; /* 0x0000000105047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x001fca000f8e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0x120 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0100*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101906 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0140*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fcc000fffe03f */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0160*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0180*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fd20007ffe0ff */
/*0190*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*01a0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*01b0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*01e0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/**
* Element-wise Vector Multiplication: C[i] = A[i] * B[i].
* This sample is a very basic sample that implements element by element vector multiplication.
*/
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
/**
* CUDA Kernel Device code
* Computes the element-wise vector multiplication of A and B into C. The 3 vectors have the same number of
elements numElements.
*/
__global__ void vectorMultiply(float *A, float *B, float *C, int numElements)
{
int size = numElements * sizeof(float);
float *d_A, *d_B, *d_C;
int i = threadIdx.x + 2* blockDim.x*blockIdx.x;
if (i < numElements) C[i] = A[i] * B[i];
if (i < numElements + blockDim.x) C[i + blockDim.x] = A[i + blockDim.x] + B[i + blockDim.x];
}
//Host main routine
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the vector length to be used, and compute its size
float EPS = 0.00001;
int numElements = 50000;
size_t size = numElements * sizeof(float);
printf("[Vector multiplication of %d elements]\n", numElements);
// Allocate the host input vector A
float *h_A = (float *)malloc(size);
// Allocate the host input vector B
float *h_B = (float *)malloc(size);
// Allocate the host output vector C
float *h_C = (float *)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < numElements; i++)
{
*(h_A + i) = (float)i;
//printf("h_A = %f\n", h_A[i]);
}
for (int i = 0; i < numElements; i++)
*(h_B + i) = (1 / (EPS + i));
// Allocate the device input vector A
float *d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device input vector B
float *d_B = NULL;
err = cudaMalloc((void **)&d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device output vector C
float *d_C = NULL;
err = cudaMalloc((void **)&d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the host input vectors A and B in host memory to the device input vectors in device memory
printf("Copy input data from the host memory to the CUDA device\n");
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Launch the VectorMultiply CUDA Kernel
int threadsPerBlock = 256;
int blocksPerGrid = ceil(numElements / (float) threadsPerBlock);
vectorMultiply <<< blocksPerGrid, threadsPerBlock >>>(d_A, d_B, d_C, numElements);
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < numElements; ++i)
{
if (fabs((h_A[i] * h_B[i]) - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
// Free device global memory
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
printf("Done\n");
return 0;
} | .file "tmpxft_00169828_00000000-6_VectorMultiply2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14vectorMultiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
.globl _Z14vectorMultiplyPfS_S_i
.type _Z14vectorMultiplyPfS_S_i, @function
_Z14vectorMultiplyPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14vectorMultiplyPfS_S_i, .-_Z14vectorMultiplyPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "[Vector multiplication of %d elements]\n"
.align 8
.LC1:
.string "Failed\tto allocate host vectors!\n"
.align 8
.LC4:
.string "Failed\tto allocate device vector A (error code %s)!\n"
.align 8
.LC5:
.string "Failed to allocate device vector B (error code\t%s)!\n"
.align 8
.LC6:
.string "Failed\tto allocate\tdevice vector C (error code\t%s)!\n"
.align 8
.LC7:
.string "Copy input data\tfrom the host memory to the CUDA device\n"
.align 8
.LC8:
.string "CUDA kernel launch with\t%d blocks of %d threads\n"
.align 8
.LC9:
.string "Failed\tto launch vectorAdd\tkernel (error code %s)!\n"
.align 8
.LC10:
.string "Copy output data from the CUDA device to the host memory\n"
.align 8
.LC13:
.string "Result\tverification failed\tat element %d!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC14:
.string "Test PASSED\n"
.LC15:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $50000, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $200000, %edi
call malloc@PLT
movq %rax, %rbp
movl $200000, %edi
call malloc@PLT
movq %rax, %rbx
movl $200000, %edi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L25
testq %r12, %r12
je .L25
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $50000, %rax
jne .L12
movl $0, %eax
movss .LC2(%rip), %xmm3
movss .LC3(%rip), %xmm2
.L14:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm3, %xmm0
movaps %xmm2, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
addq $1, %rax
cmpq $50000, %rax
jne .L14
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $196, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L18:
movl $256, %ecx
movl $196, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $200000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %eax
movss .LC11(%rip), %xmm2
movsd .LC12(%rip), %xmm1
.L22:
movss 0(%rbp,%rax,4), %xmm0
mulss (%rbx,%rax,4), %xmm0
subss (%r12,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L37
addq $1, %rax
cmpq $50000, %rax
jne .L22
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl $50000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
jmp .L18
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z14vectorMultiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vectorMultiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 925353388
.align 4
.LC3:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/**
* Element-wise Vector Multiplication: C[i] = A[i] * B[i].
* This sample is a very basic sample that implements element by element vector multiplication.
*/
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
/**
* CUDA Kernel Device code
* Computes the element-wise vector multiplication of A and B into C. The 3 vectors have the same number of
elements numElements.
*/
__global__ void vectorMultiply(float *A, float *B, float *C, int numElements)
{
int size = numElements * sizeof(float);
float *d_A, *d_B, *d_C;
int i = threadIdx.x + 2* blockDim.x*blockIdx.x;
if (i < numElements) C[i] = A[i] * B[i];
if (i < numElements + blockDim.x) C[i + blockDim.x] = A[i + blockDim.x] + B[i + blockDim.x];
}
//Host main routine
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the vector length to be used, and compute its size
float EPS = 0.00001;
int numElements = 50000;
size_t size = numElements * sizeof(float);
printf("[Vector multiplication of %d elements]\n", numElements);
// Allocate the host input vector A
float *h_A = (float *)malloc(size);
// Allocate the host input vector B
float *h_B = (float *)malloc(size);
// Allocate the host output vector C
float *h_C = (float *)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < numElements; i++)
{
*(h_A + i) = (float)i;
//printf("h_A = %f\n", h_A[i]);
}
for (int i = 0; i < numElements; i++)
*(h_B + i) = (1 / (EPS + i));
// Allocate the device input vector A
float *d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device input vector B
float *d_B = NULL;
err = cudaMalloc((void **)&d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device output vector C
float *d_C = NULL;
err = cudaMalloc((void **)&d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the host input vectors A and B in host memory to the device input vectors in device memory
printf("Copy input data from the host memory to the CUDA device\n");
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Launch the VectorMultiply CUDA Kernel
int threadsPerBlock = 256;
int blocksPerGrid = ceil(numElements / (float) threadsPerBlock);
vectorMultiply <<< blocksPerGrid, threadsPerBlock >>>(d_A, d_B, d_C, numElements);
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < numElements; ++i)
{
if (fabs((h_A[i] * h_B[i]) - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
// Free device global memory
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
printf("Done\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/**
* Element-wise Vector Multiplication: C[i] = A[i] * B[i].
* This sample is a very basic sample that implements element by element vector multiplication.
*/
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
/**
* CUDA Kernel Device code
* Computes the element-wise vector multiplication of A and B into C. The 3 vectors have the same number of
elements numElements.
*/
__global__ void vectorMultiply(float *A, float *B, float *C, int numElements)
{
int size = numElements * sizeof(float);
float *d_A, *d_B, *d_C;
int i = threadIdx.x + 2* blockDim.x*blockIdx.x;
if (i < numElements) C[i] = A[i] * B[i];
if (i < numElements + blockDim.x) C[i + blockDim.x] = A[i + blockDim.x] + B[i + blockDim.x];
}
//Host main routine
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the vector length to be used, and compute its size
float EPS = 0.00001;
int numElements = 50000;
size_t size = numElements * sizeof(float);
printf("[Vector multiplication of %d elements]\n", numElements);
// Allocate the host input vector A
float *h_A = (float *)malloc(size);
// Allocate the host input vector B
float *h_B = (float *)malloc(size);
// Allocate the host output vector C
float *h_C = (float *)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < numElements; i++)
{
*(h_A + i) = (float)i;
//printf("h_A = %f\n", h_A[i]);
}
for (int i = 0; i < numElements; i++)
*(h_B + i) = (1 / (EPS + i));
// Allocate the device input vector A
float *d_A = NULL;
err = hipMalloc((void **)&d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device input vector B
float *d_B = NULL;
err = hipMalloc((void **)&d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device output vector C
float *d_C = NULL;
err = hipMalloc((void **)&d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the host input vectors A and B in host memory to the device input vectors in device memory
printf("Copy input data from the host memory to the CUDA device\n");
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Launch the VectorMultiply CUDA Kernel
int threadsPerBlock = 256;
int blocksPerGrid = ceil(numElements / (float) threadsPerBlock);
vectorMultiply <<< blocksPerGrid, threadsPerBlock >>>(d_A, d_B, d_C, numElements);
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < numElements; ++i)
{
if (fabs((h_A[i] * h_B[i]) - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
// Free device global memory
hipFree(d_A); hipFree(d_B); hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
printf("Done\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/**
* Element-wise Vector Multiplication: C[i] = A[i] * B[i].
* This sample is a very basic sample that implements element by element vector multiplication.
*/
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
/**
* CUDA Kernel Device code
* Computes the element-wise vector multiplication of A and B into C. The 3 vectors have the same number of
elements numElements.
*/
__global__ void vectorMultiply(float *A, float *B, float *C, int numElements)
{
int size = numElements * sizeof(float);
float *d_A, *d_B, *d_C;
int i = threadIdx.x + 2* blockDim.x*blockIdx.x;
if (i < numElements) C[i] = A[i] * B[i];
if (i < numElements + blockDim.x) C[i + blockDim.x] = A[i + blockDim.x] + B[i + blockDim.x];
}
//Host main routine
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the vector length to be used, and compute its size
float EPS = 0.00001;
int numElements = 50000;
size_t size = numElements * sizeof(float);
printf("[Vector multiplication of %d elements]\n", numElements);
// Allocate the host input vector A
float *h_A = (float *)malloc(size);
// Allocate the host input vector B
float *h_B = (float *)malloc(size);
// Allocate the host output vector C
float *h_C = (float *)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < numElements; i++)
{
*(h_A + i) = (float)i;
//printf("h_A = %f\n", h_A[i]);
}
for (int i = 0; i < numElements; i++)
*(h_B + i) = (1 / (EPS + i));
// Allocate the device input vector A
float *d_A = NULL;
err = hipMalloc((void **)&d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device input vector B
float *d_B = NULL;
err = hipMalloc((void **)&d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device output vector C
float *d_C = NULL;
err = hipMalloc((void **)&d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the host input vectors A and B in host memory to the device input vectors in device memory
printf("Copy input data from the host memory to the CUDA device\n");
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Launch the VectorMultiply CUDA Kernel
int threadsPerBlock = 256;
int blocksPerGrid = ceil(numElements / (float) threadsPerBlock);
vectorMultiply <<< blocksPerGrid, threadsPerBlock >>>(d_A, d_B, d_C, numElements);
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < numElements; ++i)
{
if (fabs((h_A[i] * h_B[i]) - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
// Free device global memory
hipFree(d_A); hipFree(d_B); hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
printf("Done\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14vectorMultiplyPfS_S_i
.globl _Z14vectorMultiplyPfS_S_i
.p2align 8
.type _Z14vectorMultiplyPfS_S_i,@function
_Z14vectorMultiplyPfS_S_i:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v0, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14vectorMultiplyPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14vectorMultiplyPfS_S_i, .Lfunc_end0-_Z14vectorMultiplyPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14vectorMultiplyPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14vectorMultiplyPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/**
* Element-wise Vector Multiplication: C[i] = A[i] * B[i].
* This sample is a very basic sample that implements element by element vector multiplication.
*/
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
/**
* CUDA Kernel Device code
* Computes the element-wise vector multiplication of A and B into C. The 3 vectors have the same number of
elements numElements.
*/
__global__ void vectorMultiply(float *A, float *B, float *C, int numElements)
{
int size = numElements * sizeof(float);
float *d_A, *d_B, *d_C;
int i = threadIdx.x + 2* blockDim.x*blockIdx.x;
if (i < numElements) C[i] = A[i] * B[i];
if (i < numElements + blockDim.x) C[i + blockDim.x] = A[i + blockDim.x] + B[i + blockDim.x];
}
//Host main routine
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the vector length to be used, and compute its size
float EPS = 0.00001;
int numElements = 50000;
size_t size = numElements * sizeof(float);
printf("[Vector multiplication of %d elements]\n", numElements);
// Allocate the host input vector A
float *h_A = (float *)malloc(size);
// Allocate the host input vector B
float *h_B = (float *)malloc(size);
// Allocate the host output vector C
float *h_C = (float *)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < numElements; i++)
{
*(h_A + i) = (float)i;
//printf("h_A = %f\n", h_A[i]);
}
for (int i = 0; i < numElements; i++)
*(h_B + i) = (1 / (EPS + i));
// Allocate the device input vector A
float *d_A = NULL;
err = hipMalloc((void **)&d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device input vector B
float *d_B = NULL;
err = hipMalloc((void **)&d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Allocate the device output vector C
float *d_C = NULL;
err = hipMalloc((void **)&d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the host input vectors A and B in host memory to the device input vectors in device memory
printf("Copy input data from the host memory to the CUDA device\n");
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Launch the VectorMultiply CUDA Kernel
int threadsPerBlock = 256;
int blocksPerGrid = ceil(numElements / (float) threadsPerBlock);
vectorMultiply <<< blocksPerGrid, threadsPerBlock >>>(d_A, d_B, d_C, numElements);
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < numElements; ++i)
{
if (fabs((h_A[i] * h_B[i]) - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
// Free device global memory
hipFree(d_A); hipFree(d_B); hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
printf("Done\n");
return 0;
} | .text
.file "VectorMultiply2.hip"
.globl _Z29__device_stub__vectorMultiplyPfS_S_i # -- Begin function _Z29__device_stub__vectorMultiplyPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__vectorMultiplyPfS_S_i,@function
_Z29__device_stub__vectorMultiplyPfS_S_i: # @_Z29__device_stub__vectorMultiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14vectorMultiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__vectorMultiplyPfS_S_i, .Lfunc_end0-_Z29__device_stub__vectorMultiplyPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3727c5ac # float 9.99999974E-6
.LCPI1_1:
.long 0x3f800000 # float 1
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $50000, %esi # imm = 0xC350
xorl %eax, %eax
callq printf
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %rbx
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %r14
movl $200000, %edi # imm = 0x30D40
callq malloc
testq %rbx, %rbx
je .LBB1_22
# %bb.1:
testq %r14, %r14
je .LBB1_22
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB1_22
# %bb.3: # %.preheader81.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.preheader81
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $50000, %rax # imm = 0xC350
jne .LBB1_4
# %bb.5: # %.preheader.preheader
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_6: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %eax, %xmm2
addss %xmm0, %xmm2
movaps %xmm1, %xmm3
divss %xmm2, %xmm3
movss %xmm3, (%r14,%rax,4)
incq %rax
cmpq $50000, %rax # imm = 0xC350
jne .LBB1_6
# %bb.7:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.10:
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967492, %rdi # imm = 0x1000000C4
leaq 60(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $50000, 36(%rsp) # imm = 0xC350
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14vectorMultiplyPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movl $.L.str.6, %edi
movl $196, %esi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movl $200000, %edx # imm = 0x30D40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %edx, %edx
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_19: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss (%r14,%rdx,4), %xmm2
subss (%r15,%rdx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_23
# %bb.20: # in Loop: Header=BB1_19 Depth=1
incq %rdx
cmpq $50000, %rdx # imm = 0xC350
jne .LBB1_19
# %bb.21:
movl $.Lstr.2, %edi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_22:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_9
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_9
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_9
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
.LBB1_9:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14vectorMultiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14vectorMultiplyPfS_S_i,@object # @_Z14vectorMultiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14vectorMultiplyPfS_S_i
.p2align 3, 0x0
_Z14vectorMultiplyPfS_S_i:
.quad _Z29__device_stub__vectorMultiplyPfS_S_i
.size _Z14vectorMultiplyPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Vector multiplication of %d elements]\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed\tto allocate host vectors!\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed\tto allocate device vector A (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device vector B (error code\t%s)!\n"
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed\tto allocate\tdevice vector C (error code\t%s)!\n"
.size .L.str.4, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA kernel launch with\t%d blocks of %d threads\n"
.size .L.str.6, 49
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed\tto launch vectorAdd\tkernel (error code %s)!\n"
.size .L.str.7, 52
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result\tverification failed\tat element %d!\n"
.size .L.str.9, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14vectorMultiplyPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copy input data\tfrom the host memory to the CUDA device"
.size .Lstr, 56
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copy output data from the CUDA device to the host memory"
.size .Lstr.1, 57
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test PASSED"
.size .Lstr.2, 12
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Done"
.size .Lstr.3, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__vectorMultiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14vectorMultiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14vectorMultiplyPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.L.U32 UR4, UR5, 0x1, URZ ; /* 0x0000000105047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x001fca000f8e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0x120 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0100*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101906 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0140*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fcc000fffe03f */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0160*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0180*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fd20007ffe0ff */
/*0190*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*01a0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*01b0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*01e0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14vectorMultiplyPfS_S_i
.globl _Z14vectorMultiplyPfS_S_i
.p2align 8
.type _Z14vectorMultiplyPfS_S_i,@function
_Z14vectorMultiplyPfS_S_i:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v0, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14vectorMultiplyPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14vectorMultiplyPfS_S_i, .Lfunc_end0-_Z14vectorMultiplyPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14vectorMultiplyPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14vectorMultiplyPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169828_00000000-6_VectorMultiply2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14vectorMultiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
.globl _Z14vectorMultiplyPfS_S_i
.type _Z14vectorMultiplyPfS_S_i, @function
_Z14vectorMultiplyPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14vectorMultiplyPfS_S_i, .-_Z14vectorMultiplyPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "[Vector multiplication of %d elements]\n"
.align 8
.LC1:
.string "Failed\tto allocate host vectors!\n"
.align 8
.LC4:
.string "Failed\tto allocate device vector A (error code %s)!\n"
.align 8
.LC5:
.string "Failed to allocate device vector B (error code\t%s)!\n"
.align 8
.LC6:
.string "Failed\tto allocate\tdevice vector C (error code\t%s)!\n"
.align 8
.LC7:
.string "Copy input data\tfrom the host memory to the CUDA device\n"
.align 8
.LC8:
.string "CUDA kernel launch with\t%d blocks of %d threads\n"
.align 8
.LC9:
.string "Failed\tto launch vectorAdd\tkernel (error code %s)!\n"
.align 8
.LC10:
.string "Copy output data from the CUDA device to the host memory\n"
.align 8
.LC13:
.string "Result\tverification failed\tat element %d!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC14:
.string "Test PASSED\n"
.LC15:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $50000, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $200000, %edi
call malloc@PLT
movq %rax, %rbp
movl $200000, %edi
call malloc@PLT
movq %rax, %rbx
movl $200000, %edi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L25
testq %r12, %r12
je .L25
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $50000, %rax
jne .L12
movl $0, %eax
movss .LC2(%rip), %xmm3
movss .LC3(%rip), %xmm2
.L14:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm3, %xmm0
movaps %xmm2, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
addq $1, %rax
cmpq $50000, %rax
jne .L14
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $196, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L18:
movl $256, %ecx
movl $196, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $200000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %eax
movss .LC11(%rip), %xmm2
movsd .LC12(%rip), %xmm1
.L22:
movss 0(%rbp,%rax,4), %xmm0
mulss (%rbx,%rax,4), %xmm0
subss (%r12,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L37
addq $1, %rax
cmpq $50000, %rax
jne .L22
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl $50000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z14vectorMultiplyPfS_S_iPfS_S_i
jmp .L18
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z14vectorMultiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vectorMultiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 925353388
.align 4
.LC3:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorMultiply2.hip"
.globl _Z29__device_stub__vectorMultiplyPfS_S_i # -- Begin function _Z29__device_stub__vectorMultiplyPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__vectorMultiplyPfS_S_i,@function
_Z29__device_stub__vectorMultiplyPfS_S_i: # @_Z29__device_stub__vectorMultiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14vectorMultiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__vectorMultiplyPfS_S_i, .Lfunc_end0-_Z29__device_stub__vectorMultiplyPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3727c5ac # float 9.99999974E-6
.LCPI1_1:
.long 0x3f800000 # float 1
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $50000, %esi # imm = 0xC350
xorl %eax, %eax
callq printf
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %rbx
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %r14
movl $200000, %edi # imm = 0x30D40
callq malloc
testq %rbx, %rbx
je .LBB1_22
# %bb.1:
testq %r14, %r14
je .LBB1_22
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB1_22
# %bb.3: # %.preheader81.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.preheader81
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $50000, %rax # imm = 0xC350
jne .LBB1_4
# %bb.5: # %.preheader.preheader
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_6: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %eax, %xmm2
addss %xmm0, %xmm2
movaps %xmm1, %xmm3
divss %xmm2, %xmm3
movss %xmm3, (%r14,%rax,4)
incq %rax
cmpq $50000, %rax # imm = 0xC350
jne .LBB1_6
# %bb.7:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.10:
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967492, %rdi # imm = 0x1000000C4
leaq 60(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $50000, 36(%rsp) # imm = 0xC350
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14vectorMultiplyPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movl $.L.str.6, %edi
movl $196, %esi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movl $200000, %edx # imm = 0x30D40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %edx, %edx
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_19: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss (%r14,%rdx,4), %xmm2
subss (%r15,%rdx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_23
# %bb.20: # in Loop: Header=BB1_19 Depth=1
incq %rdx
cmpq $50000, %rdx # imm = 0xC350
jne .LBB1_19
# %bb.21:
movl $.Lstr.2, %edi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_22:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_9
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_9
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_9
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
.LBB1_9:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14vectorMultiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14vectorMultiplyPfS_S_i,@object # @_Z14vectorMultiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14vectorMultiplyPfS_S_i
.p2align 3, 0x0
_Z14vectorMultiplyPfS_S_i:
.quad _Z29__device_stub__vectorMultiplyPfS_S_i
.size _Z14vectorMultiplyPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Vector multiplication of %d elements]\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed\tto allocate host vectors!\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed\tto allocate device vector A (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device vector B (error code\t%s)!\n"
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed\tto allocate\tdevice vector C (error code\t%s)!\n"
.size .L.str.4, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA kernel launch with\t%d blocks of %d threads\n"
.size .L.str.6, 49
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed\tto launch vectorAdd\tkernel (error code %s)!\n"
.size .L.str.7, 52
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result\tverification failed\tat element %d!\n"
.size .L.str.9, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14vectorMultiplyPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copy input data\tfrom the host memory to the CUDA device"
.size .Lstr, 56
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copy output data from the CUDA device to the host memory"
.size .Lstr.1, 57
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test PASSED"
.size .Lstr.2, 12
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Done"
.size .Lstr.3, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__vectorMultiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14vectorMultiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <time.h>
#include <stdio.h>
#define N (48*1024)
#define M (48*1024)
#define P 256
#define SIZE 4
float rand_unit_box() {
return (rand() + 0.5) / (RAND_MAX + 1.0) - 0.5;
}
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T*) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T*) __smem;
}
};
__global__
void compute(float *__restrict__ G, const float *__restrict__ Y, const float *__restrict__ X) {
// const int i = threadIdx.x + blockIdx.x * P;
auto ys = SharedMemory<float>();
//
// for (int tile = 0; tile < M / P; tile++) {
// const int j0 = tile * P * SIZE;
// int base = threadIdx.x * SIZE;
// ys[base] = Y[j0 + base];
// ys[base + 1] = Y[j0 + base + 1];
// ys[base + 2] = Y[j0 + base + 2];
// __syncthreads();
//#pragma unroll 128
// for (int j = 0; j < P; j++) {
// const int i0 = i * SIZE;
// const int j0 = j * SIZE;
// const auto dx = X[i0] - ys[j0];
// const auto dy = X[i0 + 1] - ys[j0 + 1];
// const auto dz = X[i0 + 2] - ys[j0 + 2];
// const auto tmp = rsqrt(dx * dx + dy * dy + dz * dz);
// const auto r3inv = tmp * tmp * tmp;
// G[i0] += dx * r3inv ;
// G[i0 + 1] += dy * r3inv;
// G[i0 + 2] += dz * r3inv;
// }
// __syncthreads();
// }
//
const int i = threadIdx.x + blockIdx.x * P;
const auto G0 = (SIZE+1) * i;
float g1 = 0.0;
float g2 = 0.0;
float g3 = 0.0;
float g4 = 0.0;
for (int tile = 0; tile < M / P; tile++) {
const int j0 = tile * P * SIZE;
int base = threadIdx.x * SIZE;
ys[base] = Y[j0 + base];
ys[base + 1] = Y[j0 + base + 1];
ys[base + 2] = Y[j0 + base + 2];
__syncthreads();
//if (i < N) {
const auto X0 = SIZE * i;
const auto x1 = X[X0];
const auto x2 = X[X0 + 1];
const auto x3 = X[X0 + 2];
for (int j = 0; j < P; j++) {
const auto Y0 = SIZE * j;
const auto dx1 = x1 - ys[Y0]; // 1 OP
const auto dx2 = x2 - ys[Y0 + 1]; // 1 OP
const auto dx3 = x3 - ys[Y0 + 2]; // 1 OP
const auto r2 = dx1 * dx1 + dx2 * dx2 + dx3 * dx3; // 5 OP
const auto rinv = rsqrt(r2); // 1 OP
const auto nrinv3 = -rinv * rinv * rinv; // 3 OP
g1 = g1 + dx1 * nrinv3; // 2 OP
g2 = g2 + dx2 * nrinv3; // 2 OP
g3 = g3 + dx3 * nrinv3; // 2 OP
g4 = g4 - rinv; // 1 OP
}
__syncthreads();
// }
}
G[G0] = g1;
G[G0 + 1] = g2;
G[G0 + 2] = g3;
G[G0 + 3] = g4;
}
int main() {
float *hostX;
float *hostY;
float *hostG;
float *deviceX;
float *deviceY;
float *deviceG;
cudaSetDeviceFlags (cudaDeviceMapHost);
cudaHostAlloc((void**) &hostG, (SIZE+1) * N * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostAlloc((void**) &hostX, (SIZE) * N * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostAlloc((void**) &hostY, (SIZE) * M * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostGetDevicePointer((void**) &deviceG, hostG, 0);
cudaHostGetDevicePointer((void**) &deviceX, hostX, 0);
cudaHostGetDevicePointer((void**) &deviceY, hostY, 0);
for (int i = 0; i < N; i++) {
for (int d = 0; d < SIZE; d++) {
hostX[SIZE * i] = rand_unit_box();
hostX[SIZE * i + 1] = rand_unit_box();
hostX[SIZE * i + 2] = rand_unit_box();
}
}
for (int i = 0; i < M; i++) {
for (int d = 0; d < SIZE; d++) {
hostY[SIZE * i] = rand_unit_box();
hostY[SIZE * i + 1] = rand_unit_box();
hostY[SIZE * i + 2] = rand_unit_box();
}
}
auto start = time(NULL);
for (int i = 0; i < 1000; i++) {
compute<<<N/P,P,P * SIZE*sizeof(float)>>>(deviceG,deviceX,deviceY);
cudaDeviceSynchronize();
auto end = time(NULL);
double ops = (i + 1) * (double) N * (double) M * 20.0 / (1024.0 * 1024.0 * 1024.0 * 1024.0);
double t = (double) (end - start);
double flops = ops / t;
printf("%i %e TFLOP in %e seconds for %e TFLOPS\n", i, ops, t, flops);
}
} | code for sm_80
Function : _Z7computePfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ LEA R20, R3, R0, 0x8 ; /* 0x0000000003147211 */
/* 0x001fc800078e40ff */
/*0060*/ SHF.L.U32 R4, R20, 0x2, RZ ; /* 0x0000000214047819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E.CONSTANT R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000168000c1e9900 */
/*0090*/ LDG.E.CONSTANT R2, [R4.64+0x4] ; /* 0x0000040604027981 */
/* 0x000168000c1e9900 */
/*00a0*/ LDG.E.CONSTANT R17, [R4.64+0x8] ; /* 0x0000080604117981 */
/* 0x000162000c1e9900 */
/*00b0*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*00c0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*00d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fe200000001ff */
/*00e0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fc40000000f00 */
/*00f0*/ LEA R20, R20, R20, 0x2 ; /* 0x0000001414147211 */
/* 0x000fe400078e10ff */
/*0100*/ LEA R4, R19, R0, 0x8 ; /* 0x0000000013047211 */
/* 0x001fe400078e40ff */
/*0110*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fe40000000f00 */
/*0120*/ SHF.L.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047819 */
/* 0x000fca00000006ff */
/*0130*/ IMAD.WIDE R4, R4, R21, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0215 */
/*0140*/ LDG.E.CONSTANT R7, [R4.64+0x4] ; /* 0x0000040604077981 */
/* 0x000ea8000c1e9900 */
/*0150*/ LDG.E.CONSTANT R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e9900 */
/*0160*/ LDG.E.CONSTANT R9, [R4.64+0x8] ; /* 0x0000080604097981 */
/* 0x000ee2000c1e9900 */
/*0170*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ MOV R22, 0x20 ; /* 0x0000002000167802 */
/* 0x000fc40000000f00 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R19, 0xc0, PT ; /* 0x000000c01300780c */
/* 0x000fe20003f06070 */
/*01b0*/ STS.64 [R0.X16], R6 ; /* 0x0000000600007388 */
/* 0x0041e8000000ca00 */
/*01c0*/ STS [R0.X16+0x8], R9 ; /* 0x0000080900007388 */
/* 0x0081e8000000c800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ LDS.128 R4, [UR4] ; /* 0x00000004ff047984 */
/* 0x001e220008000c00 */
/*01f0*/ IADD3 R22, R22, 0x40, RZ ; /* 0x0000004016167810 */
/* 0x000fc60007ffe0ff */
/*0200*/ LDS.128 R8, [UR4+0x20] ; /* 0x00002004ff087984 */
/* 0x000e620008000c00 */
/*0210*/ FADD R24, R2, -R5 ; /* 0x8000000502187221 */
/* 0x021fe40000000000 */
/*0220*/ FADD R26, R3, -R4 ; /* 0x80000004031a7221 */
/* 0x000fe40000000000 */
/*0230*/ FMUL R5, R24, R24 ; /* 0x0000001818057220 */
/* 0x000fe40000400000 */
/*0240*/ FADD R25, R17, -R6 ; /* 0x8000000611197221 */
/* 0x000fe40000000000 */
/*0250*/ FFMA R4, R26, R26, R5 ; /* 0x0000001a1a047223 */
/* 0x000fe40000000005 */
/*0260*/ FADD R9, R2, -R9 ; /* 0x8000000902097221 */
/* 0x002fc40000000000 */
/*0270*/ FFMA R29, R25, R25, R4 ; /* 0x00000019191d7223 */
/* 0x000fe40000000004 */
/*0280*/ LDS.128 R4, [UR4+0x10] ; /* 0x00001004ff047984 */
/* 0x000e220008000c00 */
/*0290*/ FADD R8, R3, -R8 ; /* 0x8000000803087221 */
/* 0x000fe40000000000 */
/*02a0*/ FSETP.GEU.AND P1, PT, |R29|, 1.175494350822287508e-38, PT ; /* 0x008000001d00780b */
/* 0x000fe20003f2e200 */
/*02b0*/ FMUL R11, R9, R9 ; /* 0x00000009090b7220 */
/* 0x000fe40000400000 */
/*02c0*/ FADD R10, R17, -R10 ; /* 0x8000000a110a7221 */
/* 0x000fe40000000000 */
/*02d0*/ FFMA R11, R8, R8, R11 ; /* 0x00000008080b7223 */
/* 0x000fd0000000000b */
/*02e0*/ @!P1 FMUL R29, R29, 16777216 ; /* 0x4b8000001d1d9820 */
/* 0x000fc80000400000 */
/*02f0*/ MUFU.RSQ R27, R29 ; /* 0x0000001d001b7308 */
/* 0x000e640000001400 */
/*0300*/ @!P1 FMUL R27, R27, 4096 ; /* 0x458000001b1b9820 */
/* 0x002fc80000400000 */
/*0310*/ FMUL R28, R27, R27 ; /* 0x0000001b1b1c7220 */
/* 0x000fe40000400000 */
/*0320*/ FADD R7, R17, -R6 ; /* 0x8000000611077221 */
/* 0x001fe40000000000 */
/*0330*/ FMUL R28, R27.reuse, R28 ; /* 0x0000001c1b1c7220 */
/* 0x040fe40000400000 */
/*0340*/ FADD R16, -R27, R16 ; /* 0x000000101b107221 */
/* 0x000fe40000000100 */
/*0350*/ FFMA R26, -R26, R28.reuse, R13 ; /* 0x0000001c1a1a7223 */
/* 0x080fe4000000010d */
/*0360*/ LDS.128 R12, [UR4+0x30] ; /* 0x00003004ff0c7984 */
/* 0x000e220008000c00 */
/*0370*/ FFMA R23, -R24, R28, R23 ; /* 0x0000001c18177223 */
/* 0x000fe20000000117 */
/*0380*/ UIADD3 UR4, UR4, 0x40, URZ ; /* 0x0000004004047890 */
/* 0x000fe2000fffe03f */
/*0390*/ FADD R24, R2, -R5 ; /* 0x8000000502187221 */
/* 0x000fc40000000000 */
/*03a0*/ FADD R5, R3, -R4 ; /* 0x8000000403057221 */
/* 0x000fe40000000000 */
/*03b0*/ FMUL R4, R24, R24 ; /* 0x0000001818047220 */
/* 0x000fe40000400000 */
/*03c0*/ FFMA R18, -R25, R28, R18 ; /* 0x0000001c19127223 */
/* 0x000fe40000000112 */
/*03d0*/ FFMA R4, R5, R5, R4 ; /* 0x0000000505047223 */
/* 0x000fc80000000004 */
/*03e0*/ FFMA R25, R7, R7, R4 ; /* 0x0000000707197223 */
/* 0x000fca0000000004 */
/*03f0*/ FSETP.GEU.AND P1, PT, |R25|, 1.175494350822287508e-38, PT ; /* 0x008000001900780b */
/* 0x000fda0003f2e200 */
/*0400*/ @!P1 FMUL R25, R25, 16777216 ; /* 0x4b80000019199820 */
/* 0x000fe40000400000 */
/*0410*/ FADD R4, R2, -R13 ; /* 0x8000000d02047221 */
/* 0x001fe40000000000 */
/*0420*/ FADD R12, R3, -R12 ; /* 0x8000000c030c7221 */
/* 0x000fe40000000000 */
/*0430*/ FMUL R13, R4, R4 ; /* 0x00000004040d7220 */
/* 0x000fe40000400000 */
/*0440*/ FADD R14, R17, -R14 ; /* 0x8000000e110e7221 */
/* 0x000fe40000000000 */
/*0450*/ FFMA R13, R12, R12, R13 ; /* 0x0000000c0c0d7223 */
/* 0x000fc4000000000d */
/*0460*/ FFMA R15, R10, R10, R11 ; /* 0x0000000a0a0f7223 */
/* 0x000fe4000000000b */
/*0470*/ FFMA R6, R14, R14, R13 ; /* 0x0000000e0e067223 */
/* 0x000fe4000000000d */
/*0480*/ MUFU.RSQ R13, R25 ; /* 0x00000019000d7308 */
/* 0x000e220000001400 */
/*0490*/ FSETP.GEU.AND P2, PT, |R15|, 1.175494350822287508e-38, PT ; /* 0x008000000f00780b */
/* 0x000fe40003f4e200 */
/*04a0*/ FSETP.GEU.AND P3, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fd60003f6e200 */
/*04b0*/ @!P2 FMUL R15, R15, 16777216 ; /* 0x4b8000000f0fa820 */
/* 0x000fe40000400000 */
/*04c0*/ @!P3 FMUL R6, R6, 16777216 ; /* 0x4b8000000606b820 */
/* 0x000fe40000400000 */
/*04d0*/ MUFU.RSQ R11, R15 ; /* 0x0000000f000b7308 */
/* 0x000e620000001400 */
/*04e0*/ @!P1 FMUL R13, R13, 4096 ; /* 0x458000000d0d9820 */
/* 0x001fe20000400000 */
/*04f0*/ ISETP.NE.AND P1, PT, R22, 0x1020, PT ; /* 0x000010201600780c */
/* 0x000fc60003f25270 */
/*0500*/ FMUL R28, R13.reuse, R13 ; /* 0x0000000d0d1c7220 */
/* 0x040fe40000400000 */
/*0510*/ FADD R16, R16, -R13 ; /* 0x8000000d10107221 */
/* 0x000fe20000000000 */
/*0520*/ MUFU.RSQ R6, R6 ; /* 0x0000000600067308 */
/* 0x000e220000001400 */
/*0530*/ FMUL R28, R13, R28 ; /* 0x0000001c0d1c7220 */
/* 0x000fc80000400000 */
/*0540*/ FFMA R5, -R5, R28.reuse, R26 ; /* 0x0000001c05057223 */
/* 0x080fe4000000011a */
/*0550*/ FFMA R24, -R24, R28.reuse, R23 ; /* 0x0000001c18187223 */
/* 0x080fe40000000117 */
/*0560*/ @!P2 FMUL R11, R11, 4096 ; /* 0x458000000b0ba820 */
/* 0x002fe40000400000 */
/*0570*/ FFMA R7, -R7, R28, R18 ; /* 0x0000001c07077223 */
/* 0x000fe40000000112 */
/*0580*/ FMUL R26, R11, R11 ; /* 0x0000000b0b1a7220 */
/* 0x000fe40000400000 */
/*0590*/ @!P3 FMUL R6, R6, 4096 ; /* 0x458000000606b820 */
/* 0x001fc40000400000 */
/*05a0*/ FMUL R26, R11, R26 ; /* 0x0000001a0b1a7220 */
/* 0x000fe40000400000 */
/*05b0*/ FMUL R13, R6, R6 ; /* 0x00000006060d7220 */
/* 0x000fe40000400000 */
/*05c0*/ FFMA R5, -R8, R26.reuse, R5 ; /* 0x0000001a08057223 */
/* 0x080fe40000000105 */
/*05d0*/ FFMA R9, -R9, R26, R24 ; /* 0x0000001a09097223 */
/* 0x000fe40000000118 */
/*05e0*/ FMUL R18, R6, R13 ; /* 0x0000000d06127220 */
/* 0x000fe40000400000 */
/*05f0*/ FADD R11, R16, -R11 ; /* 0x8000000b100b7221 */
/* 0x000fc40000000000 */
/*0600*/ FFMA R7, -R10, R26, R7 ; /* 0x0000001a0a077223 */
/* 0x000fe40000000107 */
/*0610*/ FFMA R13, -R12, R18.reuse, R5 ; /* 0x000000120c0d7223 */
/* 0x080fe40000000105 */
/*0620*/ FFMA R23, -R4, R18.reuse, R9 ; /* 0x0000001204177223 */
/* 0x080fe40000000109 */
/*0630*/ FADD R16, R11, -R6 ; /* 0x800000060b107221 */
/* 0x000fe40000000000 */
/*0640*/ FFMA R18, -R14, R18, R7 ; /* 0x000000120e127223 */
/* 0x000fe20000000107 */
/*0650*/ @P1 BRA 0x1e0 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ @!P0 BRA 0x100 ; /* 0xfffffa8000008947 */
/* 0x000fea000383ffff */
/*0680*/ IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fca00078e0215 */
/*0690*/ STG.E [R20.64], R13 ; /* 0x0000000d14007986 */
/* 0x000fe8000c101906 */
/*06a0*/ STG.E [R20.64+0x4], R23 ; /* 0x0000041714007986 */
/* 0x000fe8000c101906 */
/*06b0*/ STG.E [R20.64+0x8], R18 ; /* 0x0000081214007986 */
/* 0x000fe8000c101906 */
/*06c0*/ STG.E [R20.64+0xc], R16 ; /* 0x00000c1014007986 */
/* 0x000fe2000c101906 */
/*06d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06e0*/ BRA 0x6e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <time.h>
#include <stdio.h>
#define N (48*1024)
#define M (48*1024)
#define P 256
#define SIZE 4
float rand_unit_box() {
return (rand() + 0.5) / (RAND_MAX + 1.0) - 0.5;
}
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T*) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T*) __smem;
}
};
__global__
void compute(float *__restrict__ G, const float *__restrict__ Y, const float *__restrict__ X) {
// const int i = threadIdx.x + blockIdx.x * P;
auto ys = SharedMemory<float>();
//
// for (int tile = 0; tile < M / P; tile++) {
// const int j0 = tile * P * SIZE;
// int base = threadIdx.x * SIZE;
// ys[base] = Y[j0 + base];
// ys[base + 1] = Y[j0 + base + 1];
// ys[base + 2] = Y[j0 + base + 2];
// __syncthreads();
//#pragma unroll 128
// for (int j = 0; j < P; j++) {
// const int i0 = i * SIZE;
// const int j0 = j * SIZE;
// const auto dx = X[i0] - ys[j0];
// const auto dy = X[i0 + 1] - ys[j0 + 1];
// const auto dz = X[i0 + 2] - ys[j0 + 2];
// const auto tmp = rsqrt(dx * dx + dy * dy + dz * dz);
// const auto r3inv = tmp * tmp * tmp;
// G[i0] += dx * r3inv ;
// G[i0 + 1] += dy * r3inv;
// G[i0 + 2] += dz * r3inv;
// }
// __syncthreads();
// }
//
const int i = threadIdx.x + blockIdx.x * P;
const auto G0 = (SIZE+1) * i;
float g1 = 0.0;
float g2 = 0.0;
float g3 = 0.0;
float g4 = 0.0;
for (int tile = 0; tile < M / P; tile++) {
const int j0 = tile * P * SIZE;
int base = threadIdx.x * SIZE;
ys[base] = Y[j0 + base];
ys[base + 1] = Y[j0 + base + 1];
ys[base + 2] = Y[j0 + base + 2];
__syncthreads();
//if (i < N) {
const auto X0 = SIZE * i;
const auto x1 = X[X0];
const auto x2 = X[X0 + 1];
const auto x3 = X[X0 + 2];
for (int j = 0; j < P; j++) {
const auto Y0 = SIZE * j;
const auto dx1 = x1 - ys[Y0]; // 1 OP
const auto dx2 = x2 - ys[Y0 + 1]; // 1 OP
const auto dx3 = x3 - ys[Y0 + 2]; // 1 OP
const auto r2 = dx1 * dx1 + dx2 * dx2 + dx3 * dx3; // 5 OP
const auto rinv = rsqrt(r2); // 1 OP
const auto nrinv3 = -rinv * rinv * rinv; // 3 OP
g1 = g1 + dx1 * nrinv3; // 2 OP
g2 = g2 + dx2 * nrinv3; // 2 OP
g3 = g3 + dx3 * nrinv3; // 2 OP
g4 = g4 - rinv; // 1 OP
}
__syncthreads();
// }
}
G[G0] = g1;
G[G0 + 1] = g2;
G[G0 + 2] = g3;
G[G0 + 3] = g4;
}
int main() {
float *hostX;
float *hostY;
float *hostG;
float *deviceX;
float *deviceY;
float *deviceG;
cudaSetDeviceFlags (cudaDeviceMapHost);
cudaHostAlloc((void**) &hostG, (SIZE+1) * N * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostAlloc((void**) &hostX, (SIZE) * N * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostAlloc((void**) &hostY, (SIZE) * M * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostGetDevicePointer((void**) &deviceG, hostG, 0);
cudaHostGetDevicePointer((void**) &deviceX, hostX, 0);
cudaHostGetDevicePointer((void**) &deviceY, hostY, 0);
for (int i = 0; i < N; i++) {
for (int d = 0; d < SIZE; d++) {
hostX[SIZE * i] = rand_unit_box();
hostX[SIZE * i + 1] = rand_unit_box();
hostX[SIZE * i + 2] = rand_unit_box();
}
}
for (int i = 0; i < M; i++) {
for (int d = 0; d < SIZE; d++) {
hostY[SIZE * i] = rand_unit_box();
hostY[SIZE * i + 1] = rand_unit_box();
hostY[SIZE * i + 2] = rand_unit_box();
}
}
auto start = time(NULL);
for (int i = 0; i < 1000; i++) {
compute<<<N/P,P,P * SIZE*sizeof(float)>>>(deviceG,deviceX,deviceY);
cudaDeviceSynchronize();
auto end = time(NULL);
double ops = (i + 1) * (double) N * (double) M * 20.0 / (1024.0 * 1024.0 * 1024.0 * 1024.0);
double t = (double) (end - start);
double flops = ops / t;
printf("%i %e TFLOP in %e seconds for %e TFLOPS\n", i, ops, t, flops);
}
} | .file "tmpxft_001b8024_00000000-6_cuda_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13rand_unit_boxv
.type _Z13rand_unit_boxv, @function
_Z13rand_unit_boxv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC0(%rip), %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13rand_unit_boxv, .-_Z13rand_unit_boxv
.globl _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
.type _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_, @function
_Z32__device_stub__Z7computePfPKfS1_PfPKfS1_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfPKfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_, .-_Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
.globl _Z7computePfPKfS1_
.type _Z7computePfPKfS1_, @function
_Z7computePfPKfS1_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7computePfPKfS1_, .-_Z7computePfPKfS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "%i %e TFLOP in %e seconds for %e TFLOPS\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $8, %edi
call cudaSetDeviceFlags@PLT
leaq 16(%rsp), %rdi
movl $3, %edx
movl $983040, %esi
call cudaHostAlloc@PLT
movq %rsp, %rdi
movl $3, %edx
movl $786432, %esi
call cudaHostAlloc@PLT
leaq 8(%rsp), %rdi
movl $3, %edx
movl $786432, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq 16(%rsp), %rsi
call cudaHostGetDevicePointer@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movq (%rsp), %rsi
call cudaHostGetDevicePointer@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movq 8(%rsp), %rsi
call cudaHostGetDevicePointer@PLT
movl $0, %ebp
jmp .L14
.L27:
addq $16, %rbp
cmpq $786432, %rbp
je .L22
.L14:
leaq 4(%rbp), %r14
leaq 8(%rbp), %r13
movl $4, %ebx
.L15:
movq %rbp, %r12
addq (%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r14, %r12
addq (%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r13, %r12
addq (%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
subl $1, %ebx
jne .L15
jmp .L27
.L29:
addq $16, %rbp
cmpq $786432, %rbp
je .L28
.L16:
leaq 4(%rbp), %r14
leaq 8(%rbp), %r13
movl $4, %ebx
.L17:
movq %rbp, %r12
addq 8(%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r14, %r12
addq 8(%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r13, %r12
addq 8(%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
subl $1, %ebx
jne .L17
jmp .L29
.L22:
movl $0, %ebp
jmp .L16
.L28:
movl $0, %edi
call time@PLT
movq %rax, %r12
movl $0, %ebp
leaq .LC5(%rip), %r13
jmp .L20
.L19:
call cudaDeviceSynchronize@PLT
movl $0, %edi
call time@PLT
leal 1(%rbp), %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
subq %r12, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
cmpl $1000, %ebx
je .L30
movl %ebx, %ebp
.L20:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $192, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
jmp .L19
.L30:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "_Z7computePfPKfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfPKfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.align 8
.LC1:
.long 0
.long 1040187392
.align 8
.LC2:
.long 0
.long 1088946176
.align 8
.LC3:
.long 0
.long 1077149696
.align 8
.LC4:
.long 0
.long 1030750208
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <time.h>
#include <stdio.h>
#define N (48*1024)
#define M (48*1024)
#define P 256
#define SIZE 4
float rand_unit_box() {
return (rand() + 0.5) / (RAND_MAX + 1.0) - 0.5;
}
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T*) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T*) __smem;
}
};
__global__
void compute(float *__restrict__ G, const float *__restrict__ Y, const float *__restrict__ X) {
// const int i = threadIdx.x + blockIdx.x * P;
auto ys = SharedMemory<float>();
//
// for (int tile = 0; tile < M / P; tile++) {
// const int j0 = tile * P * SIZE;
// int base = threadIdx.x * SIZE;
// ys[base] = Y[j0 + base];
// ys[base + 1] = Y[j0 + base + 1];
// ys[base + 2] = Y[j0 + base + 2];
// __syncthreads();
//#pragma unroll 128
// for (int j = 0; j < P; j++) {
// const int i0 = i * SIZE;
// const int j0 = j * SIZE;
// const auto dx = X[i0] - ys[j0];
// const auto dy = X[i0 + 1] - ys[j0 + 1];
// const auto dz = X[i0 + 2] - ys[j0 + 2];
// const auto tmp = rsqrt(dx * dx + dy * dy + dz * dz);
// const auto r3inv = tmp * tmp * tmp;
// G[i0] += dx * r3inv ;
// G[i0 + 1] += dy * r3inv;
// G[i0 + 2] += dz * r3inv;
// }
// __syncthreads();
// }
//
const int i = threadIdx.x + blockIdx.x * P;
const auto G0 = (SIZE+1) * i;
float g1 = 0.0;
float g2 = 0.0;
float g3 = 0.0;
float g4 = 0.0;
for (int tile = 0; tile < M / P; tile++) {
const int j0 = tile * P * SIZE;
int base = threadIdx.x * SIZE;
ys[base] = Y[j0 + base];
ys[base + 1] = Y[j0 + base + 1];
ys[base + 2] = Y[j0 + base + 2];
__syncthreads();
//if (i < N) {
const auto X0 = SIZE * i;
const auto x1 = X[X0];
const auto x2 = X[X0 + 1];
const auto x3 = X[X0 + 2];
for (int j = 0; j < P; j++) {
const auto Y0 = SIZE * j;
const auto dx1 = x1 - ys[Y0]; // 1 OP
const auto dx2 = x2 - ys[Y0 + 1]; // 1 OP
const auto dx3 = x3 - ys[Y0 + 2]; // 1 OP
const auto r2 = dx1 * dx1 + dx2 * dx2 + dx3 * dx3; // 5 OP
const auto rinv = rsqrt(r2); // 1 OP
const auto nrinv3 = -rinv * rinv * rinv; // 3 OP
g1 = g1 + dx1 * nrinv3; // 2 OP
g2 = g2 + dx2 * nrinv3; // 2 OP
g3 = g3 + dx3 * nrinv3; // 2 OP
g4 = g4 - rinv; // 1 OP
}
__syncthreads();
// }
}
G[G0] = g1;
G[G0 + 1] = g2;
G[G0 + 2] = g3;
G[G0 + 3] = g4;
}
int main() {
float *hostX;
float *hostY;
float *hostG;
float *deviceX;
float *deviceY;
float *deviceG;
cudaSetDeviceFlags (cudaDeviceMapHost);
cudaHostAlloc((void**) &hostG, (SIZE+1) * N * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostAlloc((void**) &hostX, (SIZE) * N * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostAlloc((void**) &hostY, (SIZE) * M * sizeof(float), cudaHostAllocMapped | cudaHostAllocPortable);
cudaHostGetDevicePointer((void**) &deviceG, hostG, 0);
cudaHostGetDevicePointer((void**) &deviceX, hostX, 0);
cudaHostGetDevicePointer((void**) &deviceY, hostY, 0);
for (int i = 0; i < N; i++) {
for (int d = 0; d < SIZE; d++) {
hostX[SIZE * i] = rand_unit_box();
hostX[SIZE * i + 1] = rand_unit_box();
hostX[SIZE * i + 2] = rand_unit_box();
}
}
for (int i = 0; i < M; i++) {
for (int d = 0; d < SIZE; d++) {
hostY[SIZE * i] = rand_unit_box();
hostY[SIZE * i + 1] = rand_unit_box();
hostY[SIZE * i + 2] = rand_unit_box();
}
}
auto start = time(NULL);
for (int i = 0; i < 1000; i++) {
compute<<<N/P,P,P * SIZE*sizeof(float)>>>(deviceG,deviceX,deviceY);
cudaDeviceSynchronize();
auto end = time(NULL);
double ops = (i + 1) * (double) N * (double) M * 20.0 / (1024.0 * 1024.0 * 1024.0 * 1024.0);
double t = (double) (end - start);
double flops = ops / t;
printf("%i %e TFLOP in %e seconds for %e TFLOPS\n", i, ops, t, flops);
}
} | #include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#define N (48*1024)
#define M (48*1024)
#define P 256
#define SIZE 4
float rand_unit_box() {
return (rand() + 0.5) / (RAND_MAX + 1.0) - 0.5;
}
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T*) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T*) __smem;
}
};
__global__
void compute(float *__restrict__ G, const float *__restrict__ Y, const float *__restrict__ X) {
// const int i = threadIdx.x + blockIdx.x * P;
auto ys = SharedMemory<float>();
//
// for (int tile = 0; tile < M / P; tile++) {
// const int j0 = tile * P * SIZE;
// int base = threadIdx.x * SIZE;
// ys[base] = Y[j0 + base];
// ys[base + 1] = Y[j0 + base + 1];
// ys[base + 2] = Y[j0 + base + 2];
// __syncthreads();
//#pragma unroll 128
// for (int j = 0; j < P; j++) {
// const int i0 = i * SIZE;
// const int j0 = j * SIZE;
// const auto dx = X[i0] - ys[j0];
// const auto dy = X[i0 + 1] - ys[j0 + 1];
// const auto dz = X[i0 + 2] - ys[j0 + 2];
// const auto tmp = rsqrt(dx * dx + dy * dy + dz * dz);
// const auto r3inv = tmp * tmp * tmp;
// G[i0] += dx * r3inv ;
// G[i0 + 1] += dy * r3inv;
// G[i0 + 2] += dz * r3inv;
// }
// __syncthreads();
// }
//
const int i = threadIdx.x + blockIdx.x * P;
const auto G0 = (SIZE+1) * i;
float g1 = 0.0;
float g2 = 0.0;
float g3 = 0.0;
float g4 = 0.0;
for (int tile = 0; tile < M / P; tile++) {
const int j0 = tile * P * SIZE;
int base = threadIdx.x * SIZE;
ys[base] = Y[j0 + base];
ys[base + 1] = Y[j0 + base + 1];
ys[base + 2] = Y[j0 + base + 2];
__syncthreads();
//if (i < N) {
const auto X0 = SIZE * i;
const auto x1 = X[X0];
const auto x2 = X[X0 + 1];
const auto x3 = X[X0 + 2];
for (int j = 0; j < P; j++) {
const auto Y0 = SIZE * j;
const auto dx1 = x1 - ys[Y0]; // 1 OP
const auto dx2 = x2 - ys[Y0 + 1]; // 1 OP
const auto dx3 = x3 - ys[Y0 + 2]; // 1 OP
const auto r2 = dx1 * dx1 + dx2 * dx2 + dx3 * dx3; // 5 OP
const auto rinv = rsqrt(r2); // 1 OP
const auto nrinv3 = -rinv * rinv * rinv; // 3 OP
g1 = g1 + dx1 * nrinv3; // 2 OP
g2 = g2 + dx2 * nrinv3; // 2 OP
g3 = g3 + dx3 * nrinv3; // 2 OP
g4 = g4 - rinv; // 1 OP
}
__syncthreads();
// }
}
G[G0] = g1;
G[G0 + 1] = g2;
G[G0 + 2] = g3;
G[G0 + 3] = g4;
}
int main() {
float *hostX;
float *hostY;
float *hostG;
float *deviceX;
float *deviceY;
float *deviceG;
hipSetDeviceFlags (hipDeviceMapHost);
hipHostAlloc((void**) &hostG, (SIZE+1) * N * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostAlloc((void**) &hostX, (SIZE) * N * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostAlloc((void**) &hostY, (SIZE) * M * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostGetDevicePointer((void**) &deviceG, hostG, 0);
hipHostGetDevicePointer((void**) &deviceX, hostX, 0);
hipHostGetDevicePointer((void**) &deviceY, hostY, 0);
for (int i = 0; i < N; i++) {
for (int d = 0; d < SIZE; d++) {
hostX[SIZE * i] = rand_unit_box();
hostX[SIZE * i + 1] = rand_unit_box();
hostX[SIZE * i + 2] = rand_unit_box();
}
}
for (int i = 0; i < M; i++) {
for (int d = 0; d < SIZE; d++) {
hostY[SIZE * i] = rand_unit_box();
hostY[SIZE * i + 1] = rand_unit_box();
hostY[SIZE * i + 2] = rand_unit_box();
}
}
auto start = time(NULL);
for (int i = 0; i < 1000; i++) {
compute<<<N/P,P,P * SIZE*sizeof(float)>>>(deviceG,deviceX,deviceY);
hipDeviceSynchronize();
auto end = time(NULL);
double ops = (i + 1) * (double) N * (double) M * 20.0 / (1024.0 * 1024.0 * 1024.0 * 1024.0);
double t = (double) (end - start);
double flops = ops / t;
printf("%i %e TFLOP in %e seconds for %e TFLOPS\n", i, ops, t, flops);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#define N (48*1024)
#define M (48*1024)
#define P 256
#define SIZE 4
float rand_unit_box() {
return (rand() + 0.5) / (RAND_MAX + 1.0) - 0.5;
}
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T*) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T*) __smem;
}
};
__global__
void compute(float *__restrict__ G, const float *__restrict__ Y, const float *__restrict__ X) {
// const int i = threadIdx.x + blockIdx.x * P;
auto ys = SharedMemory<float>();
//
// for (int tile = 0; tile < M / P; tile++) {
// const int j0 = tile * P * SIZE;
// int base = threadIdx.x * SIZE;
// ys[base] = Y[j0 + base];
// ys[base + 1] = Y[j0 + base + 1];
// ys[base + 2] = Y[j0 + base + 2];
// __syncthreads();
//#pragma unroll 128
// for (int j = 0; j < P; j++) {
// const int i0 = i * SIZE;
// const int j0 = j * SIZE;
// const auto dx = X[i0] - ys[j0];
// const auto dy = X[i0 + 1] - ys[j0 + 1];
// const auto dz = X[i0 + 2] - ys[j0 + 2];
// const auto tmp = rsqrt(dx * dx + dy * dy + dz * dz);
// const auto r3inv = tmp * tmp * tmp;
// G[i0] += dx * r3inv ;
// G[i0 + 1] += dy * r3inv;
// G[i0 + 2] += dz * r3inv;
// }
// __syncthreads();
// }
//
const int i = threadIdx.x + blockIdx.x * P;
const auto G0 = (SIZE+1) * i;
float g1 = 0.0;
float g2 = 0.0;
float g3 = 0.0;
float g4 = 0.0;
for (int tile = 0; tile < M / P; tile++) {
const int j0 = tile * P * SIZE;
int base = threadIdx.x * SIZE;
ys[base] = Y[j0 + base];
ys[base + 1] = Y[j0 + base + 1];
ys[base + 2] = Y[j0 + base + 2];
__syncthreads();
//if (i < N) {
const auto X0 = SIZE * i;
const auto x1 = X[X0];
const auto x2 = X[X0 + 1];
const auto x3 = X[X0 + 2];
for (int j = 0; j < P; j++) {
const auto Y0 = SIZE * j;
const auto dx1 = x1 - ys[Y0]; // 1 OP
const auto dx2 = x2 - ys[Y0 + 1]; // 1 OP
const auto dx3 = x3 - ys[Y0 + 2]; // 1 OP
const auto r2 = dx1 * dx1 + dx2 * dx2 + dx3 * dx3; // 5 OP
const auto rinv = rsqrt(r2); // 1 OP
const auto nrinv3 = -rinv * rinv * rinv; // 3 OP
g1 = g1 + dx1 * nrinv3; // 2 OP
g2 = g2 + dx2 * nrinv3; // 2 OP
g3 = g3 + dx3 * nrinv3; // 2 OP
g4 = g4 - rinv; // 1 OP
}
__syncthreads();
// }
}
G[G0] = g1;
G[G0 + 1] = g2;
G[G0 + 2] = g3;
G[G0 + 3] = g4;
}
int main() {
float *hostX;
float *hostY;
float *hostG;
float *deviceX;
float *deviceY;
float *deviceG;
hipSetDeviceFlags (hipDeviceMapHost);
hipHostAlloc((void**) &hostG, (SIZE+1) * N * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostAlloc((void**) &hostX, (SIZE) * N * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostAlloc((void**) &hostY, (SIZE) * M * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostGetDevicePointer((void**) &deviceG, hostG, 0);
hipHostGetDevicePointer((void**) &deviceX, hostX, 0);
hipHostGetDevicePointer((void**) &deviceY, hostY, 0);
for (int i = 0; i < N; i++) {
for (int d = 0; d < SIZE; d++) {
hostX[SIZE * i] = rand_unit_box();
hostX[SIZE * i + 1] = rand_unit_box();
hostX[SIZE * i + 2] = rand_unit_box();
}
}
for (int i = 0; i < M; i++) {
for (int d = 0; d < SIZE; d++) {
hostY[SIZE * i] = rand_unit_box();
hostY[SIZE * i + 1] = rand_unit_box();
hostY[SIZE * i + 2] = rand_unit_box();
}
}
auto start = time(NULL);
for (int i = 0; i < 1000; i++) {
compute<<<N/P,P,P * SIZE*sizeof(float)>>>(deviceG,deviceX,deviceY);
hipDeviceSynchronize();
auto end = time(NULL);
double ops = (i + 1) * (double) N * (double) M * 20.0 / (1024.0 * 1024.0 * 1024.0 * 1024.0);
double t = (double) (end - start);
double flops = ops / t;
printf("%i %e TFLOP in %e seconds for %e TFLOPS\n", i, ops, t, flops);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfPKfS1_
.globl _Z7computePfPKfS1_
.p2align 8
.type _Z7computePfPKfS1_,@function
_Z7computePfPKfS1_:
v_lshl_add_u32 v6, s15, 8, v0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v11, 2, v0
s_mov_b32 s4, 0
v_mov_b32_e32 v5, 0
v_lshlrev_b32_e32 v1, 2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
v_or_b32_e32 v7, 2, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
s_clause 0x2
global_load_b32 v7, v[1:2], off
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[9:10], off
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v10, v0, 4, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v12, 4, v10
v_add_nc_u32_e32 v13, 8, v10
.LBB0_1:
v_lshl_add_u32 v4, s4, 10, v11
v_mov_b32_e32 v15, v5
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v14, 1, v4
v_lshlrev_b64 v[16:17], 2, v[4:5]
v_or_b32_e32 v4, 2, v4
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[18:19], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
s_clause 0x2
global_load_b32 v4, v[16:17], off
global_load_b32 v14, v[14:15], off
global_load_b32 v15, v[18:19], off
s_waitcnt vmcnt(2)
ds_store_b32 v10, v4
s_waitcnt vmcnt(1)
ds_store_b32 v12, v14
s_waitcnt vmcnt(0)
ds_store_b32 v13, v15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_add_i32 s6, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[20:21], v2
v_mov_b32_e32 v4, s6
v_cvt_f64_f32_e32 v[2:3], v3
s_add_i32 s5, s5, 16
ds_load_2addr_b32 v[14:15], v4 offset1:1
ds_load_b32 v4, v4 offset:8
s_cmpk_eq_i32 s5, 0x1000
s_waitcnt lgkmcnt(1)
v_sub_f32_e32 v24, v8, v15
v_sub_f32_e32 v22, v7, v14
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v14, v24, v24
v_cvt_f64_f32_e32 v[24:25], v24
v_cvt_f64_f32_e32 v[26:27], v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v22, v22
v_cvt_f64_f32_e32 v[22:23], v22
v_fmac_f32_e32 v14, v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[14:15], v14
v_rsq_f64_e32 v[16:17], v[14:15]
s_waitcnt_depctr 0xfff
v_mul_f64 v[14:15], v[16:17], -v[14:15]
v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x180
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[16:17], 1.0
v_mul_f64 v[18:19], v[16:17], v[14:15]
v_fma_f64 v[14:15], v[14:15], 0x3fd80000, 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[18:19], v[14:15], v[16:17]
v_cvt_f64_f32_e32 v[18:19], v0
v_cvt_f64_f32_e32 v[0:1], v1
v_dual_cndmask_b32 v15, v17, v15 :: v_dual_cndmask_b32 v14, v16, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[16:17], v[14:15], -v[14:15]
v_add_f64 v[2:3], v[2:3], -v[14:15]
v_mul_f64 v[16:17], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v3, v[2:3]
v_fma_f64 v[14:15], v[16:17], v[22:23], v[18:19]
v_fma_f64 v[18:19], v[16:17], v[24:25], v[0:1]
v_fma_f64 v[16:17], v[16:17], v[26:27], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v0, v[14:15]
v_cvt_f32_f64_e32 v1, v[18:19]
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f32_f64_e32 v2, v[16:17]
s_cbranch_scc0 .LBB0_2
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s4, 0xc0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
v_lshl_add_u32 v4, v6, 2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfPKfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfPKfS1_, .Lfunc_end0-_Z7computePfPKfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfPKfS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfPKfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#define N (48*1024)
#define M (48*1024)
#define P 256
#define SIZE 4
float rand_unit_box() {
return (rand() + 0.5) / (RAND_MAX + 1.0) - 0.5;
}
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T*) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T*) __smem;
}
};
__global__
void compute(float *__restrict__ G, const float *__restrict__ Y, const float *__restrict__ X) {
// const int i = threadIdx.x + blockIdx.x * P;
auto ys = SharedMemory<float>();
//
// for (int tile = 0; tile < M / P; tile++) {
// const int j0 = tile * P * SIZE;
// int base = threadIdx.x * SIZE;
// ys[base] = Y[j0 + base];
// ys[base + 1] = Y[j0 + base + 1];
// ys[base + 2] = Y[j0 + base + 2];
// __syncthreads();
//#pragma unroll 128
// for (int j = 0; j < P; j++) {
// const int i0 = i * SIZE;
// const int j0 = j * SIZE;
// const auto dx = X[i0] - ys[j0];
// const auto dy = X[i0 + 1] - ys[j0 + 1];
// const auto dz = X[i0 + 2] - ys[j0 + 2];
// const auto tmp = rsqrt(dx * dx + dy * dy + dz * dz);
// const auto r3inv = tmp * tmp * tmp;
// G[i0] += dx * r3inv ;
// G[i0 + 1] += dy * r3inv;
// G[i0 + 2] += dz * r3inv;
// }
// __syncthreads();
// }
//
const int i = threadIdx.x + blockIdx.x * P;
const auto G0 = (SIZE+1) * i;
float g1 = 0.0;
float g2 = 0.0;
float g3 = 0.0;
float g4 = 0.0;
for (int tile = 0; tile < M / P; tile++) {
const int j0 = tile * P * SIZE;
int base = threadIdx.x * SIZE;
ys[base] = Y[j0 + base];
ys[base + 1] = Y[j0 + base + 1];
ys[base + 2] = Y[j0 + base + 2];
__syncthreads();
//if (i < N) {
const auto X0 = SIZE * i;
const auto x1 = X[X0];
const auto x2 = X[X0 + 1];
const auto x3 = X[X0 + 2];
for (int j = 0; j < P; j++) {
const auto Y0 = SIZE * j;
const auto dx1 = x1 - ys[Y0]; // 1 OP
const auto dx2 = x2 - ys[Y0 + 1]; // 1 OP
const auto dx3 = x3 - ys[Y0 + 2]; // 1 OP
const auto r2 = dx1 * dx1 + dx2 * dx2 + dx3 * dx3; // 5 OP
const auto rinv = rsqrt(r2); // 1 OP
const auto nrinv3 = -rinv * rinv * rinv; // 3 OP
g1 = g1 + dx1 * nrinv3; // 2 OP
g2 = g2 + dx2 * nrinv3; // 2 OP
g3 = g3 + dx3 * nrinv3; // 2 OP
g4 = g4 - rinv; // 1 OP
}
__syncthreads();
// }
}
G[G0] = g1;
G[G0 + 1] = g2;
G[G0 + 2] = g3;
G[G0 + 3] = g4;
}
int main() {
float *hostX;
float *hostY;
float *hostG;
float *deviceX;
float *deviceY;
float *deviceG;
hipSetDeviceFlags (hipDeviceMapHost);
hipHostAlloc((void**) &hostG, (SIZE+1) * N * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostAlloc((void**) &hostX, (SIZE) * N * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostAlloc((void**) &hostY, (SIZE) * M * sizeof(float), hipHostMallocMapped | hipHostMallocPortable);
hipHostGetDevicePointer((void**) &deviceG, hostG, 0);
hipHostGetDevicePointer((void**) &deviceX, hostX, 0);
hipHostGetDevicePointer((void**) &deviceY, hostY, 0);
for (int i = 0; i < N; i++) {
for (int d = 0; d < SIZE; d++) {
hostX[SIZE * i] = rand_unit_box();
hostX[SIZE * i + 1] = rand_unit_box();
hostX[SIZE * i + 2] = rand_unit_box();
}
}
for (int i = 0; i < M; i++) {
for (int d = 0; d < SIZE; d++) {
hostY[SIZE * i] = rand_unit_box();
hostY[SIZE * i + 1] = rand_unit_box();
hostY[SIZE * i + 2] = rand_unit_box();
}
}
auto start = time(NULL);
for (int i = 0; i < 1000; i++) {
compute<<<N/P,P,P * SIZE*sizeof(float)>>>(deviceG,deviceX,deviceY);
hipDeviceSynchronize();
auto end = time(NULL);
double ops = (i + 1) * (double) N * (double) M * 20.0 / (1024.0 * 1024.0 * 1024.0 * 1024.0);
double t = (double) (end - start);
double flops = ops / t;
printf("%i %e TFLOP in %e seconds for %e TFLOPS\n", i, ops, t, flops);
}
} | .text
.file "cuda_test.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13rand_unit_boxv
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI0_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI0_2:
.quad 0xbfe0000000000000 # double -0.5
.text
.globl _Z13rand_unit_boxv
.p2align 4, 0x90
.type _Z13rand_unit_boxv,@function
_Z13rand_unit_boxv: # @_Z13rand_unit_boxv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
addsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
addsd .LCPI0_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13rand_unit_boxv, .Lfunc_end0-_Z13rand_unit_boxv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfPKfS1_ # -- Begin function _Z22__device_stub__computePfPKfS1_
.p2align 4, 0x90
.type _Z22__device_stub__computePfPKfS1_,@function
_Z22__device_stub__computePfPKfS1_: # @_Z22__device_stub__computePfPKfS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfPKfS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__computePfPKfS1_, .Lfunc_end1-_Z22__device_stub__computePfPKfS1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI2_2:
.quad 0xbfe0000000000000 # double -0.5
.LCPI2_3:
.quad 0x40e8000000000000 # double 49152
.LCPI2_4:
.quad 0x4034000000000000 # double 20
.LCPI2_5:
.quad 0x3d70000000000000 # double 9.0949470177292824E-13
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8, %edi
callq hipSetDeviceFlags
leaq 48(%rsp), %rdi
movl $983040, %esi # imm = 0xF0000
movl $3, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movl $786432, %esi # imm = 0xC0000
movl $3, %edx
callq hipHostAlloc
leaq 8(%rsp), %rdi
movl $786432, %esi # imm = 0xC0000
movl $3, %edx
callq hipHostAlloc
movq 48(%rsp), %rsi
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
xorl %edx, %edx
callq hipHostGetDevicePointer
movq 16(%rsp), %rsi
leaq 40(%rsp), %rdi
xorl %edx, %edx
callq hipHostGetDevicePointer
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
xorl %edx, %edx
callq hipHostGetDevicePointer
.p2align 4, 0x90
.LBB2_1: # %.preheader35
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
leaq (,%rbx,4), %r14
leaq 1(,%rbx,4), %r15
leaq 2(,%rbx,4), %r12
movl $4, %ebp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r14,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r15,4)
callq rand
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm1, %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
decl %ebp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rbx
cmpq $49152, %rbx # imm = 0xC000
jne .LBB2_1
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
leaq (,%rbx,4), %r14
leaq 1(,%rbx,4), %r15
leaq 2(,%rbx,4), %r12
movl $4, %ebp
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r14,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
decl %ebp
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %rbx
cmpq $49152, %rbx # imm = 0xC000
jne .LBB2_5
# %bb.8:
movabsq $4294967488, %rbx # imm = 0x1000000C0
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movq %rax, %r14
leaq 64(%rbx), %r15
leaq 128(%rsp), %r13
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
callq hipDeviceSynchronize
xorl %edi, %edi
callq time
leal 1(%r12), %ebp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd .LCPI2_3(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI2_4(%rip), %xmm0
mulsd .LCPI2_5(%rip), %xmm0
subq %r14, %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movl $.L.str, %edi
movl %r12d, %esi
movb $3, %al
callq printf
movl %ebp, %r12d
cmpl $1000, %ebp # imm = 0x3E8
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl $4096, %r8d # imm = 0x1000
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7computePfPKfS1_, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_11
.LBB2_12:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfPKfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePfPKfS1_,@object # @_Z7computePfPKfS1_
.section .rodata,"a",@progbits
.globl _Z7computePfPKfS1_
.p2align 3, 0x0
_Z7computePfPKfS1_:
.quad _Z22__device_stub__computePfPKfS1_
.size _Z7computePfPKfS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i %e TFLOP in %e seconds for %e TFLOPS\n"
.size .L.str, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfPKfS1_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfPKfS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePfPKfS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ LEA R20, R3, R0, 0x8 ; /* 0x0000000003147211 */
/* 0x001fc800078e40ff */
/*0060*/ SHF.L.U32 R4, R20, 0x2, RZ ; /* 0x0000000214047819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E.CONSTANT R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000168000c1e9900 */
/*0090*/ LDG.E.CONSTANT R2, [R4.64+0x4] ; /* 0x0000040604027981 */
/* 0x000168000c1e9900 */
/*00a0*/ LDG.E.CONSTANT R17, [R4.64+0x8] ; /* 0x0000080604117981 */
/* 0x000162000c1e9900 */
/*00b0*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*00c0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*00d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fe200000001ff */
/*00e0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fc40000000f00 */
/*00f0*/ LEA R20, R20, R20, 0x2 ; /* 0x0000001414147211 */
/* 0x000fe400078e10ff */
/*0100*/ LEA R4, R19, R0, 0x8 ; /* 0x0000000013047211 */
/* 0x001fe400078e40ff */
/*0110*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fe40000000f00 */
/*0120*/ SHF.L.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047819 */
/* 0x000fca00000006ff */
/*0130*/ IMAD.WIDE R4, R4, R21, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0215 */
/*0140*/ LDG.E.CONSTANT R7, [R4.64+0x4] ; /* 0x0000040604077981 */
/* 0x000ea8000c1e9900 */
/*0150*/ LDG.E.CONSTANT R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e9900 */
/*0160*/ LDG.E.CONSTANT R9, [R4.64+0x8] ; /* 0x0000080604097981 */
/* 0x000ee2000c1e9900 */
/*0170*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ MOV R22, 0x20 ; /* 0x0000002000167802 */
/* 0x000fc40000000f00 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R19, 0xc0, PT ; /* 0x000000c01300780c */
/* 0x000fe20003f06070 */
/*01b0*/ STS.64 [R0.X16], R6 ; /* 0x0000000600007388 */
/* 0x0041e8000000ca00 */
/*01c0*/ STS [R0.X16+0x8], R9 ; /* 0x0000080900007388 */
/* 0x0081e8000000c800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ LDS.128 R4, [UR4] ; /* 0x00000004ff047984 */
/* 0x001e220008000c00 */
/*01f0*/ IADD3 R22, R22, 0x40, RZ ; /* 0x0000004016167810 */
/* 0x000fc60007ffe0ff */
/*0200*/ LDS.128 R8, [UR4+0x20] ; /* 0x00002004ff087984 */
/* 0x000e620008000c00 */
/*0210*/ FADD R24, R2, -R5 ; /* 0x8000000502187221 */
/* 0x021fe40000000000 */
/*0220*/ FADD R26, R3, -R4 ; /* 0x80000004031a7221 */
/* 0x000fe40000000000 */
/*0230*/ FMUL R5, R24, R24 ; /* 0x0000001818057220 */
/* 0x000fe40000400000 */
/*0240*/ FADD R25, R17, -R6 ; /* 0x8000000611197221 */
/* 0x000fe40000000000 */
/*0250*/ FFMA R4, R26, R26, R5 ; /* 0x0000001a1a047223 */
/* 0x000fe40000000005 */
/*0260*/ FADD R9, R2, -R9 ; /* 0x8000000902097221 */
/* 0x002fc40000000000 */
/*0270*/ FFMA R29, R25, R25, R4 ; /* 0x00000019191d7223 */
/* 0x000fe40000000004 */
/*0280*/ LDS.128 R4, [UR4+0x10] ; /* 0x00001004ff047984 */
/* 0x000e220008000c00 */
/*0290*/ FADD R8, R3, -R8 ; /* 0x8000000803087221 */
/* 0x000fe40000000000 */
/*02a0*/ FSETP.GEU.AND P1, PT, |R29|, 1.175494350822287508e-38, PT ; /* 0x008000001d00780b */
/* 0x000fe20003f2e200 */
/*02b0*/ FMUL R11, R9, R9 ; /* 0x00000009090b7220 */
/* 0x000fe40000400000 */
/*02c0*/ FADD R10, R17, -R10 ; /* 0x8000000a110a7221 */
/* 0x000fe40000000000 */
/*02d0*/ FFMA R11, R8, R8, R11 ; /* 0x00000008080b7223 */
/* 0x000fd0000000000b */
/*02e0*/ @!P1 FMUL R29, R29, 16777216 ; /* 0x4b8000001d1d9820 */
/* 0x000fc80000400000 */
/*02f0*/ MUFU.RSQ R27, R29 ; /* 0x0000001d001b7308 */
/* 0x000e640000001400 */
/*0300*/ @!P1 FMUL R27, R27, 4096 ; /* 0x458000001b1b9820 */
/* 0x002fc80000400000 */
/*0310*/ FMUL R28, R27, R27 ; /* 0x0000001b1b1c7220 */
/* 0x000fe40000400000 */
/*0320*/ FADD R7, R17, -R6 ; /* 0x8000000611077221 */
/* 0x001fe40000000000 */
/*0330*/ FMUL R28, R27.reuse, R28 ; /* 0x0000001c1b1c7220 */
/* 0x040fe40000400000 */
/*0340*/ FADD R16, -R27, R16 ; /* 0x000000101b107221 */
/* 0x000fe40000000100 */
/*0350*/ FFMA R26, -R26, R28.reuse, R13 ; /* 0x0000001c1a1a7223 */
/* 0x080fe4000000010d */
/*0360*/ LDS.128 R12, [UR4+0x30] ; /* 0x00003004ff0c7984 */
/* 0x000e220008000c00 */
/*0370*/ FFMA R23, -R24, R28, R23 ; /* 0x0000001c18177223 */
/* 0x000fe20000000117 */
/*0380*/ UIADD3 UR4, UR4, 0x40, URZ ; /* 0x0000004004047890 */
/* 0x000fe2000fffe03f */
/*0390*/ FADD R24, R2, -R5 ; /* 0x8000000502187221 */
/* 0x000fc40000000000 */
/*03a0*/ FADD R5, R3, -R4 ; /* 0x8000000403057221 */
/* 0x000fe40000000000 */
/*03b0*/ FMUL R4, R24, R24 ; /* 0x0000001818047220 */
/* 0x000fe40000400000 */
/*03c0*/ FFMA R18, -R25, R28, R18 ; /* 0x0000001c19127223 */
/* 0x000fe40000000112 */
/*03d0*/ FFMA R4, R5, R5, R4 ; /* 0x0000000505047223 */
/* 0x000fc80000000004 */
/*03e0*/ FFMA R25, R7, R7, R4 ; /* 0x0000000707197223 */
/* 0x000fca0000000004 */
/*03f0*/ FSETP.GEU.AND P1, PT, |R25|, 1.175494350822287508e-38, PT ; /* 0x008000001900780b */
/* 0x000fda0003f2e200 */
/*0400*/ @!P1 FMUL R25, R25, 16777216 ; /* 0x4b80000019199820 */
/* 0x000fe40000400000 */
/*0410*/ FADD R4, R2, -R13 ; /* 0x8000000d02047221 */
/* 0x001fe40000000000 */
/*0420*/ FADD R12, R3, -R12 ; /* 0x8000000c030c7221 */
/* 0x000fe40000000000 */
/*0430*/ FMUL R13, R4, R4 ; /* 0x00000004040d7220 */
/* 0x000fe40000400000 */
/*0440*/ FADD R14, R17, -R14 ; /* 0x8000000e110e7221 */
/* 0x000fe40000000000 */
/*0450*/ FFMA R13, R12, R12, R13 ; /* 0x0000000c0c0d7223 */
/* 0x000fc4000000000d */
/*0460*/ FFMA R15, R10, R10, R11 ; /* 0x0000000a0a0f7223 */
/* 0x000fe4000000000b */
/*0470*/ FFMA R6, R14, R14, R13 ; /* 0x0000000e0e067223 */
/* 0x000fe4000000000d */
/*0480*/ MUFU.RSQ R13, R25 ; /* 0x00000019000d7308 */
/* 0x000e220000001400 */
/*0490*/ FSETP.GEU.AND P2, PT, |R15|, 1.175494350822287508e-38, PT ; /* 0x008000000f00780b */
/* 0x000fe40003f4e200 */
/*04a0*/ FSETP.GEU.AND P3, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fd60003f6e200 */
/*04b0*/ @!P2 FMUL R15, R15, 16777216 ; /* 0x4b8000000f0fa820 */
/* 0x000fe40000400000 */
/*04c0*/ @!P3 FMUL R6, R6, 16777216 ; /* 0x4b8000000606b820 */
/* 0x000fe40000400000 */
/*04d0*/ MUFU.RSQ R11, R15 ; /* 0x0000000f000b7308 */
/* 0x000e620000001400 */
/*04e0*/ @!P1 FMUL R13, R13, 4096 ; /* 0x458000000d0d9820 */
/* 0x001fe20000400000 */
/*04f0*/ ISETP.NE.AND P1, PT, R22, 0x1020, PT ; /* 0x000010201600780c */
/* 0x000fc60003f25270 */
/*0500*/ FMUL R28, R13.reuse, R13 ; /* 0x0000000d0d1c7220 */
/* 0x040fe40000400000 */
/*0510*/ FADD R16, R16, -R13 ; /* 0x8000000d10107221 */
/* 0x000fe20000000000 */
/*0520*/ MUFU.RSQ R6, R6 ; /* 0x0000000600067308 */
/* 0x000e220000001400 */
/*0530*/ FMUL R28, R13, R28 ; /* 0x0000001c0d1c7220 */
/* 0x000fc80000400000 */
/*0540*/ FFMA R5, -R5, R28.reuse, R26 ; /* 0x0000001c05057223 */
/* 0x080fe4000000011a */
/*0550*/ FFMA R24, -R24, R28.reuse, R23 ; /* 0x0000001c18187223 */
/* 0x080fe40000000117 */
/*0560*/ @!P2 FMUL R11, R11, 4096 ; /* 0x458000000b0ba820 */
/* 0x002fe40000400000 */
/*0570*/ FFMA R7, -R7, R28, R18 ; /* 0x0000001c07077223 */
/* 0x000fe40000000112 */
/*0580*/ FMUL R26, R11, R11 ; /* 0x0000000b0b1a7220 */
/* 0x000fe40000400000 */
/*0590*/ @!P3 FMUL R6, R6, 4096 ; /* 0x458000000606b820 */
/* 0x001fc40000400000 */
/*05a0*/ FMUL R26, R11, R26 ; /* 0x0000001a0b1a7220 */
/* 0x000fe40000400000 */
/*05b0*/ FMUL R13, R6, R6 ; /* 0x00000006060d7220 */
/* 0x000fe40000400000 */
/*05c0*/ FFMA R5, -R8, R26.reuse, R5 ; /* 0x0000001a08057223 */
/* 0x080fe40000000105 */
/*05d0*/ FFMA R9, -R9, R26, R24 ; /* 0x0000001a09097223 */
/* 0x000fe40000000118 */
/*05e0*/ FMUL R18, R6, R13 ; /* 0x0000000d06127220 */
/* 0x000fe40000400000 */
/*05f0*/ FADD R11, R16, -R11 ; /* 0x8000000b100b7221 */
/* 0x000fc40000000000 */
/*0600*/ FFMA R7, -R10, R26, R7 ; /* 0x0000001a0a077223 */
/* 0x000fe40000000107 */
/*0610*/ FFMA R13, -R12, R18.reuse, R5 ; /* 0x000000120c0d7223 */
/* 0x080fe40000000105 */
/*0620*/ FFMA R23, -R4, R18.reuse, R9 ; /* 0x0000001204177223 */
/* 0x080fe40000000109 */
/*0630*/ FADD R16, R11, -R6 ; /* 0x800000060b107221 */
/* 0x000fe40000000000 */
/*0640*/ FFMA R18, -R14, R18, R7 ; /* 0x000000120e127223 */
/* 0x000fe20000000107 */
/*0650*/ @P1 BRA 0x1e0 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ @!P0 BRA 0x100 ; /* 0xfffffa8000008947 */
/* 0x000fea000383ffff */
/*0680*/ IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fca00078e0215 */
/*0690*/ STG.E [R20.64], R13 ; /* 0x0000000d14007986 */
/* 0x000fe8000c101906 */
/*06a0*/ STG.E [R20.64+0x4], R23 ; /* 0x0000041714007986 */
/* 0x000fe8000c101906 */
/*06b0*/ STG.E [R20.64+0x8], R18 ; /* 0x0000081214007986 */
/* 0x000fe8000c101906 */
/*06c0*/ STG.E [R20.64+0xc], R16 ; /* 0x00000c1014007986 */
/* 0x000fe2000c101906 */
/*06d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06e0*/ BRA 0x6e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfPKfS1_
.globl _Z7computePfPKfS1_
.p2align 8
.type _Z7computePfPKfS1_,@function
_Z7computePfPKfS1_:
v_lshl_add_u32 v6, s15, 8, v0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v11, 2, v0
s_mov_b32 s4, 0
v_mov_b32_e32 v5, 0
v_lshlrev_b32_e32 v1, 2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
v_or_b32_e32 v7, 2, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
s_clause 0x2
global_load_b32 v7, v[1:2], off
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[9:10], off
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v10, v0, 4, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v12, 4, v10
v_add_nc_u32_e32 v13, 8, v10
.LBB0_1:
v_lshl_add_u32 v4, s4, 10, v11
v_mov_b32_e32 v15, v5
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v14, 1, v4
v_lshlrev_b64 v[16:17], 2, v[4:5]
v_or_b32_e32 v4, 2, v4
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[18:19], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
s_clause 0x2
global_load_b32 v4, v[16:17], off
global_load_b32 v14, v[14:15], off
global_load_b32 v15, v[18:19], off
s_waitcnt vmcnt(2)
ds_store_b32 v10, v4
s_waitcnt vmcnt(1)
ds_store_b32 v12, v14
s_waitcnt vmcnt(0)
ds_store_b32 v13, v15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_add_i32 s6, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[20:21], v2
v_mov_b32_e32 v4, s6
v_cvt_f64_f32_e32 v[2:3], v3
s_add_i32 s5, s5, 16
ds_load_2addr_b32 v[14:15], v4 offset1:1
ds_load_b32 v4, v4 offset:8
s_cmpk_eq_i32 s5, 0x1000
s_waitcnt lgkmcnt(1)
v_sub_f32_e32 v24, v8, v15
v_sub_f32_e32 v22, v7, v14
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v14, v24, v24
v_cvt_f64_f32_e32 v[24:25], v24
v_cvt_f64_f32_e32 v[26:27], v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v22, v22
v_cvt_f64_f32_e32 v[22:23], v22
v_fmac_f32_e32 v14, v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[14:15], v14
v_rsq_f64_e32 v[16:17], v[14:15]
s_waitcnt_depctr 0xfff
v_mul_f64 v[14:15], v[16:17], -v[14:15]
v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x180
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[16:17], 1.0
v_mul_f64 v[18:19], v[16:17], v[14:15]
v_fma_f64 v[14:15], v[14:15], 0x3fd80000, 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[18:19], v[14:15], v[16:17]
v_cvt_f64_f32_e32 v[18:19], v0
v_cvt_f64_f32_e32 v[0:1], v1
v_dual_cndmask_b32 v15, v17, v15 :: v_dual_cndmask_b32 v14, v16, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[16:17], v[14:15], -v[14:15]
v_add_f64 v[2:3], v[2:3], -v[14:15]
v_mul_f64 v[16:17], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v3, v[2:3]
v_fma_f64 v[14:15], v[16:17], v[22:23], v[18:19]
v_fma_f64 v[18:19], v[16:17], v[24:25], v[0:1]
v_fma_f64 v[16:17], v[16:17], v[26:27], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v0, v[14:15]
v_cvt_f32_f64_e32 v1, v[18:19]
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f32_f64_e32 v2, v[16:17]
s_cbranch_scc0 .LBB0_2
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s4, 0xc0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
v_lshl_add_u32 v4, v6, 2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfPKfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfPKfS1_, .Lfunc_end0-_Z7computePfPKfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfPKfS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfPKfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b8024_00000000-6_cuda_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13rand_unit_boxv
.type _Z13rand_unit_boxv, @function
_Z13rand_unit_boxv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC0(%rip), %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13rand_unit_boxv, .-_Z13rand_unit_boxv
.globl _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
.type _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_, @function
_Z32__device_stub__Z7computePfPKfS1_PfPKfS1_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfPKfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_, .-_Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
.globl _Z7computePfPKfS1_
.type _Z7computePfPKfS1_, @function
_Z7computePfPKfS1_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7computePfPKfS1_, .-_Z7computePfPKfS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "%i %e TFLOP in %e seconds for %e TFLOPS\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $8, %edi
call cudaSetDeviceFlags@PLT
leaq 16(%rsp), %rdi
movl $3, %edx
movl $983040, %esi
call cudaHostAlloc@PLT
movq %rsp, %rdi
movl $3, %edx
movl $786432, %esi
call cudaHostAlloc@PLT
leaq 8(%rsp), %rdi
movl $3, %edx
movl $786432, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq 16(%rsp), %rsi
call cudaHostGetDevicePointer@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movq (%rsp), %rsi
call cudaHostGetDevicePointer@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movq 8(%rsp), %rsi
call cudaHostGetDevicePointer@PLT
movl $0, %ebp
jmp .L14
.L27:
addq $16, %rbp
cmpq $786432, %rbp
je .L22
.L14:
leaq 4(%rbp), %r14
leaq 8(%rbp), %r13
movl $4, %ebx
.L15:
movq %rbp, %r12
addq (%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r14, %r12
addq (%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r13, %r12
addq (%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
subl $1, %ebx
jne .L15
jmp .L27
.L29:
addq $16, %rbp
cmpq $786432, %rbp
je .L28
.L16:
leaq 4(%rbp), %r14
leaq 8(%rbp), %r13
movl $4, %ebx
.L17:
movq %rbp, %r12
addq 8(%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r14, %r12
addq 8(%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
movq %r13, %r12
addq 8(%rsp), %r12
call _Z13rand_unit_boxv
movss %xmm0, (%r12)
subl $1, %ebx
jne .L17
jmp .L29
.L22:
movl $0, %ebp
jmp .L16
.L28:
movl $0, %edi
call time@PLT
movq %rax, %r12
movl $0, %ebp
leaq .LC5(%rip), %r13
jmp .L20
.L19:
call cudaDeviceSynchronize@PLT
movl $0, %edi
call time@PLT
leal 1(%rbp), %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
subq %r12, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
cmpl $1000, %ebx
je .L30
movl %ebx, %ebp
.L20:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $192, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z32__device_stub__Z7computePfPKfS1_PfPKfS1_
jmp .L19
.L30:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "_Z7computePfPKfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfPKfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.align 8
.LC1:
.long 0
.long 1040187392
.align 8
.LC2:
.long 0
.long 1088946176
.align 8
.LC3:
.long 0
.long 1077149696
.align 8
.LC4:
.long 0
.long 1030750208
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_test.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13rand_unit_boxv
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI0_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI0_2:
.quad 0xbfe0000000000000 # double -0.5
.text
.globl _Z13rand_unit_boxv
.p2align 4, 0x90
.type _Z13rand_unit_boxv,@function
_Z13rand_unit_boxv: # @_Z13rand_unit_boxv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
addsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
addsd .LCPI0_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13rand_unit_boxv, .Lfunc_end0-_Z13rand_unit_boxv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfPKfS1_ # -- Begin function _Z22__device_stub__computePfPKfS1_
.p2align 4, 0x90
.type _Z22__device_stub__computePfPKfS1_,@function
_Z22__device_stub__computePfPKfS1_: # @_Z22__device_stub__computePfPKfS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfPKfS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__computePfPKfS1_, .Lfunc_end1-_Z22__device_stub__computePfPKfS1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI2_2:
.quad 0xbfe0000000000000 # double -0.5
.LCPI2_3:
.quad 0x40e8000000000000 # double 49152
.LCPI2_4:
.quad 0x4034000000000000 # double 20
.LCPI2_5:
.quad 0x3d70000000000000 # double 9.0949470177292824E-13
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8, %edi
callq hipSetDeviceFlags
leaq 48(%rsp), %rdi
movl $983040, %esi # imm = 0xF0000
movl $3, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movl $786432, %esi # imm = 0xC0000
movl $3, %edx
callq hipHostAlloc
leaq 8(%rsp), %rdi
movl $786432, %esi # imm = 0xC0000
movl $3, %edx
callq hipHostAlloc
movq 48(%rsp), %rsi
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
xorl %edx, %edx
callq hipHostGetDevicePointer
movq 16(%rsp), %rsi
leaq 40(%rsp), %rdi
xorl %edx, %edx
callq hipHostGetDevicePointer
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
xorl %edx, %edx
callq hipHostGetDevicePointer
.p2align 4, 0x90
.LBB2_1: # %.preheader35
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
leaq (,%rbx,4), %r14
leaq 1(,%rbx,4), %r15
leaq 2(,%rbx,4), %r12
movl $4, %ebp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r14,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r15,4)
callq rand
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd %xmm1, %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
decl %ebp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rbx
cmpq $49152, %rbx # imm = 0xC000
jne .LBB2_1
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
leaq (,%rbx,4), %r14
leaq 1(,%rbx,4), %r15
leaq 2(,%rbx,4), %r12
movl $4, %ebp
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r14,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
decl %ebp
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %rbx
cmpq $49152, %rbx # imm = 0xC000
jne .LBB2_5
# %bb.8:
movabsq $4294967488, %rbx # imm = 0x1000000C0
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movq %rax, %r14
leaq 64(%rbx), %r15
leaq 128(%rsp), %r13
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
callq hipDeviceSynchronize
xorl %edi, %edi
callq time
leal 1(%r12), %ebp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd .LCPI2_3(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI2_4(%rip), %xmm0
mulsd .LCPI2_5(%rip), %xmm0
subq %r14, %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movl $.L.str, %edi
movl %r12d, %esi
movb $3, %al
callq printf
movl %ebp, %r12d
cmpl $1000, %ebp # imm = 0x3E8
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl $4096, %r8d # imm = 0x1000
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7computePfPKfS1_, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_11
.LBB2_12:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfPKfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePfPKfS1_,@object # @_Z7computePfPKfS1_
.section .rodata,"a",@progbits
.globl _Z7computePfPKfS1_
.p2align 3, 0x0
_Z7computePfPKfS1_:
.quad _Z22__device_stub__computePfPKfS1_
.size _Z7computePfPKfS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i %e TFLOP in %e seconds for %e TFLOPS\n"
.size .L.str, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfPKfS1_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfPKfS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePfPKfS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void GPUmemo( float *data, int pts )
{
__shared__ float* trace;
trace = (float *)malloc(pts*sizeof(float));
int Blocks;
for( Blocks = 0; Blocks < gridDim.x; Blocks++ )
{
trace[threadIdx.x] = data[threadIdx.x + Blocks*pts];
}
} | code for sm_80
Function : _Z7GPUmemoPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD.WIDE UR4, UR4, 0x4, URZ ; /* 0x00000004040478a5 */
/* 0x000fe2000f8e023f */
/*0040*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006a0000000a00 */
/*0050*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fe4000f8e00ff */
/*0060*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fc4000f8e00ff */
/*0070*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe4000f8e00ff */
/*0080*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe4000f8e00ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*00a0*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x001fe20000000000 */
/*00b0*/ MOV R9, 0x120 ; /* 0x0000012000097802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R9, R6 ; /* 0x0000000914147210 */
/* 0x000fc8000791e106 */
/*0100*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0120*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f05270 */
/*0130*/ STS.64 [RZ], R4 ; /* 0x00000004ff007388 */
/* 0x0001d80000000a00 */
/*0140*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0150*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x001fe20000000f00 */
/*0160*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0180*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*0190*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*01c0*/ @!P1 BRA 0x4a0 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B0, 0x4a0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IADD3 R3, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002037a10 */
/* 0x041fe20007ffe0ff */
/*0200*/ IMAD.SHL.U32 R7, R2, 0x4, RZ ; /* 0x0000000402077824 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R6, R0, -c[0x0][0xc], RZ ; /* 0x8000030000067a10 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0230*/ SHF.R.U32.HI R8, RZ, 0x1e, R2.reuse ; /* 0x0000001eff087819 */
/* 0x100fe20000011602 */
/*0240*/ IMAD R4, R5.reuse, 0x2, R2.reuse ; /* 0x0000000205047824 */
/* 0x140fe200078e0202 */
/*0250*/ MOV R12, R2 ; /* 0x00000002000c7202 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD R10, R5, 0x3, R2 ; /* 0x00000003050a7824 */
/* 0x000fe400078e0202 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0280*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0290*/ LDS.64 R14, [RZ] ; /* 0x00000000ff0e7984 */
/* 0x001e240000000a00 */
/*02a0*/ IMAD.WIDE.U32 R22, R12, R11, c[0x0][0x160] ; /* 0x000058000c167625 */
/* 0x000fca00078e000b */
/*02b0*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R16, R3, R11, c[0x0][0x160] ; /* 0x0000580003107625 */
/* 0x000fe200078e000b */
/*02d0*/ IADD3 R14, P1, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x001fca0007f3e0ff */
/*02e0*/ IMAD.X R15, R15, 0x1, R8, P1 ; /* 0x000000010f0f7824 */
/* 0x000fca00008e0608 */
/*02f0*/ ST.E [R14.64], R13 ; /* 0x0000000d0e007985 */
/* 0x004fe8000c101904 */
/*0300*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000ea2000c1e1900 */
/*0310*/ IMAD.WIDE.U32 R20, R4, R11, c[0x0][0x160] ; /* 0x0000580004147625 */
/* 0x000fc600078e000b */
/*0320*/ LDS.64 R18, [RZ] ; /* 0x00000000ff127984 */
/* 0x000e240000000a00 */
/*0330*/ IADD3 R18, P1, R18, R7, RZ ; /* 0x0000000712127210 */
/* 0x001fca0007f3e0ff */
/*0340*/ IMAD.X R19, R19, 0x1, R8, P1 ; /* 0x0000000113137824 */
/* 0x000fca00008e0608 */
/*0350*/ ST.E [R18.64], R25 ; /* 0x0000001912007985 */
/* 0x004fe8000c101904 */
/*0360*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE.U32 R14, R10, R11, c[0x0][0x160] ; /* 0x000058000a0e7625 */
/* 0x000fc600078e000b */
/*0380*/ LDS.64 R22, [RZ] ; /* 0x00000000ff167984 */
/* 0x000e240000000a00 */
/*0390*/ IADD3 R22, P1, R22, R7, RZ ; /* 0x0000000716167210 */
/* 0x001fc80007f3e0ff */
/*03a0*/ IADD3.X R23, R23, R8, RZ, P1, !PT ; /* 0x0000000817177210 */
/* 0x000fca0000ffe4ff */
/*03b0*/ ST.E [R22.64], R21 ; /* 0x0000001516007985 */
/* 0x004fe8000c101904 */
/*03c0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD R3, R5.reuse, 0x4, R3 ; /* 0x0000000405037824 */
/* 0x040fe200078e0203 */
/*03f0*/ LEA R12, R5.reuse, R12, 0x2 ; /* 0x0000000c050c7211 */
/* 0x040fe200078e10ff */
/*0400*/ LDS.64 R16, [RZ] ; /* 0x00000000ff107984 */
/* 0x000e220000000a00 */
/*0410*/ IMAD R4, R5, 0x4, R4 ; /* 0x0000000405047824 */
/* 0x000fe400078e0204 */
/*0420*/ IMAD.IADD R11, R6, 0x1, R9 ; /* 0x00000001060b7824 */
/* 0x000fc400078e0209 */
/*0430*/ IMAD R10, R5, 0x4, R10 ; /* 0x00000004050a7824 */
/* 0x000fe200078e020a */
/*0440*/ IADD3 R16, P1, R16, R7, RZ ; /* 0x0000000710107210 */
/* 0x001fca0007f3e0ff */
/*0450*/ IMAD.X R17, R17, 0x1, R8, P1 ; /* 0x0000000111117824 */
/* 0x000fe200008e0608 */
/*0460*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f25270 */
/*0470*/ ST.E [R16.64], R15 ; /* 0x0000000f10007985 */
/* 0x0041f2000c101904 */
/*0480*/ @P1 BRA 0x270 ; /* 0xfffffde000001947 */
/* 0x000fea000383ffff */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04b0*/ IMAD R9, R9, c[0x0][0x168], R2 ; /* 0x00005a0009097a24 */
/* 0x001fe400078e0202 */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*04d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*04e0*/ LDS.64 R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x001e240000000a00 */
/*04f0*/ IMAD.WIDE.U32 R4, R9, R4, c[0x0][0x160] ; /* 0x0000580009047625 */
/* 0x000fcc00078e0004 */
/*0500*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3 R9, R9, c[0x0][0x168], RZ ; /* 0x00005a0009097a10 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R6, P0, R2, R6, 0x2 ; /* 0x0000000602067211 */
/* 0x001fc800078010ff */
/*0540*/ LEA.HI.X R7, R2, R7, RZ, 0x2, P0 ; /* 0x0000000702077211 */
/* 0x000fe400000f14ff */
/*0550*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0560*/ ST.E [R6.64], R5 ; /* 0x0000000506007985 */
/* 0x0041f4000c101904 */
/*0570*/ @P0 BRA 0x4c0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void GPUmemo( float *data, int pts )
{
__shared__ float* trace;
trace = (float *)malloc(pts*sizeof(float));
int Blocks;
for( Blocks = 0; Blocks < gridDim.x; Blocks++ )
{
trace[threadIdx.x] = data[threadIdx.x + Blocks*pts];
}
} | .file "tmpxft_00118d8d_00000000-6_GPUmemo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7GPUmemoPfiPfi
.type _Z27__device_stub__Z7GPUmemoPfiPfi, @function
_Z27__device_stub__Z7GPUmemoPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7GPUmemoPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7GPUmemoPfiPfi, .-_Z27__device_stub__Z7GPUmemoPfiPfi
.globl _Z7GPUmemoPfi
.type _Z7GPUmemoPfi, @function
_Z7GPUmemoPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7GPUmemoPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7GPUmemoPfi, .-_Z7GPUmemoPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7GPUmemoPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7GPUmemoPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void GPUmemo( float *data, int pts )
{
__shared__ float* trace;
trace = (float *)malloc(pts*sizeof(float));
int Blocks;
for( Blocks = 0; Blocks < gridDim.x; Blocks++ )
{
trace[threadIdx.x] = data[threadIdx.x + Blocks*pts];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void GPUmemo( float *data, int pts )
{
__shared__ float* trace;
trace = (float *)malloc(pts*sizeof(float));
int Blocks;
for( Blocks = 0; Blocks < gridDim.x; Blocks++ )
{
trace[threadIdx.x] = data[threadIdx.x + Blocks*pts];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void GPUmemo( float *data, int pts )
{
__shared__ float* trace;
trace = (float *)malloc(pts*sizeof(float));
int Blocks;
for( Blocks = 0; Blocks < gridDim.x; Blocks++ )
{
trace[threadIdx.x] = data[threadIdx.x + Blocks*pts];
}
} | .text
.file "GPUmemo.hip"
.globl _Z22__device_stub__GPUmemoPfi # -- Begin function _Z22__device_stub__GPUmemoPfi
.p2align 4, 0x90
.type _Z22__device_stub__GPUmemoPfi,@function
_Z22__device_stub__GPUmemoPfi: # @_Z22__device_stub__GPUmemoPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7GPUmemoPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__GPUmemoPfi, .Lfunc_end0-_Z22__device_stub__GPUmemoPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7GPUmemoPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7GPUmemoPfi,@object # @_Z7GPUmemoPfi
.section .rodata,"a",@progbits
.globl _Z7GPUmemoPfi
.p2align 3, 0x0
_Z7GPUmemoPfi:
.quad _Z22__device_stub__GPUmemoPfi
.size _Z7GPUmemoPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7GPUmemoPfi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__GPUmemoPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7GPUmemoPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118d8d_00000000-6_GPUmemo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7GPUmemoPfiPfi
.type _Z27__device_stub__Z7GPUmemoPfiPfi, @function
_Z27__device_stub__Z7GPUmemoPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7GPUmemoPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7GPUmemoPfiPfi, .-_Z27__device_stub__Z7GPUmemoPfiPfi
.globl _Z7GPUmemoPfi
.type _Z7GPUmemoPfi, @function
_Z7GPUmemoPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7GPUmemoPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7GPUmemoPfi, .-_Z7GPUmemoPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7GPUmemoPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7GPUmemoPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GPUmemo.hip"
.globl _Z22__device_stub__GPUmemoPfi # -- Begin function _Z22__device_stub__GPUmemoPfi
.p2align 4, 0x90
.type _Z22__device_stub__GPUmemoPfi,@function
_Z22__device_stub__GPUmemoPfi: # @_Z22__device_stub__GPUmemoPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7GPUmemoPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__GPUmemoPfi, .Lfunc_end0-_Z22__device_stub__GPUmemoPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7GPUmemoPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7GPUmemoPfi,@object # @_Z7GPUmemoPfi
.section .rodata,"a",@progbits
.globl _Z7GPUmemoPfi
.p2align 3, 0x0
_Z7GPUmemoPfi:
.quad _Z22__device_stub__GPUmemoPfi
.size _Z7GPUmemoPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7GPUmemoPfi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__GPUmemoPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7GPUmemoPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void kernel()
{
printf("Hello World! My threadId is %d\n", blockDim.x * blockIdx.x + threadIdx.x);
}
int main()
{
kernel<<<1, 256>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void kernel()
{
printf("Hello World! My threadId is %d\n", blockDim.x * blockIdx.x + threadIdx.x);
}
int main()
{
kernel<<<1, 256>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_001a5770_00000000-6_exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
__global__ void kernel()
{
printf("Hello World! My threadId is %d\n", blockDim.x * blockIdx.x + threadIdx.x);
}
int main()
{
kernel<<<1, 256>>>();
cudaDeviceSynchronize();
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void kernel()
{
printf("Hello World! My threadId is %d\n", blockDim.x * blockIdx.x + threadIdx.x);
}
int main()
{
kernel<<<1, 256>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void kernel()
{
printf("Hello World! My threadId is %d\n", blockDim.x * blockIdx.x + threadIdx.x);
}
int main()
{
kernel<<<1, 256>>>();
hipDeviceSynchronize();
} | .text
.file "exercise_1.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a5770_00000000-6_exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_1.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void binaryentropy_32(const int lengthX, const float *x, const float *y, float *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | .file "tmpxft_0009c7e6_00000000-6_binaryentropy_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf
.type _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf, @function
_Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq binaryentropy_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf, .-_Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf
.globl binaryentropy_32
.type binaryentropy_32, @function
binaryentropy_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size binaryentropy_32, .-binaryentropy_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "binaryentropy_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq binaryentropy_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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